M28256

256 Kbit (32Kb x8) Parallel EEPROM

with Software Data Protection
PRELIMINARY DATA

FAST ACCESS TIME:

– 90ns at 5V
– 120ns at 3V
SINGLE SUPPLY VOLTAGE:
– 5V ± 10% for M28256 28
– 2.7V to 3.6V for M28256-xxW
LOW POWER CONSUMPTION 1
FAST WRITE CYCLE: PDIP28 (BS) PLCC32 (KA)
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle
ENHANCED END of WRITE DETECTION:
28
– Data Polling
– Toggle Bit 1
STATUS REGISTER
SO28 (MS) TSOP28 (NS)
HIGH RELIABILITY DOUBLE POLYSILICON, 300 mils 8 x13.4mm
CMOS TECHNOLOGY:
– Endurance >100,000 Erase/Write Cycles
– Data Retention >10 Years
JEDEC APPROVED BYTEWIDE PIN OUT Figure 1. Logic Diagram
ADDRESS and DATA LATCHED ON-CHIP
SOFTWARE DATA PROTECTION

VCC
DESCRIPTION
The M28256 and M28256-Ware 32K x8 low power 15 8
Parallel EEPROM fabricatedwith STMicroelectron-
ics proprietary double polysilicon CMOS technol- A0-A14 DQ0-DQ7
ogy.
W M28256
Table 1. Signal Names
A0-A14 Address Input E

DQ0-DQ7 Data Input / Output G

W Write Enable

E Chip Enable

G Output Enable VSS

AI01885
VCC Supply Voltage

VSS Ground

January 1999 1/21

This is preliminary information on a new product now in developmentor undergoing evaluation . Detail s are subject to change without notice.
M28256

Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections

VCC
A12
A14

A13
A14 1 28 VCC

DU
A7

W
A12 2 27 W
A7 3 26 A13 1 32
A6 4 25 A8 A6 A8
A5 5 24 A9 A5 A9
A4 6 23 A11 A4 A11
A3 7 22 G A3 NC
M28256 A2 9 M28256 25 G
A2 8 21 A10
A1 9 20 E A1 A10
A0 10 19 DQ7 A0 E
DQ0 11 18 DQ6 NC DQ7
DQ1 12 17 DQ5 DQ0 DQ6
17
DQ2 13 16 DQ4

DQ1
DQ2

DQ3
DQ4
DQ5
VSS
DU
VSS 14 15 DQ3
AI01886
AI01887

Warning: NC = Not Connected, DU = Don’t Use.

Figure 2C. SO Pin Connections Figure 2D. TSOP Pin Connections

A14 1 28 VCC G 22 21 A10

A12 2 27 W A11 E
A7 3 26 A13 A9 DQ7
A6 4 25 A8 A8 DQ6
A5 5 24 A9 A13 DQ5
A4 6 23 A11 W DQ4
A3 7 22 G VCC 28 15 DQ3
M28256 M28256
A2 8 21 A10 A14 1 14 VSS
A1 9 20 E A12 DQ2
A0 10 19 DQ7 A7 DQ1
DQ0 11 18 DQ6 A6 DQ0
DQ1 12 17 DQ5 A5 A0
DQ2 13 16 DQ4 A4 A1
VSS 14 15 DQ3 A3 7 8 A2
AI01888
AI01889

2/21
 M28256

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit
(2)
TA Ambient Operating Temperature – 40 to 85 °C
T STG Storage Temperature Range – 65 to 150 °C
VCC Supply Voltage – 0.3 to 6.5 V
V IO Input/Output Voltage – 0.3 to VCC +0.6 V
VI Input Voltage – 0.3 to 6.5 V
(3)
VESD Electrostatic Discharge Voltage (Human Body model) 4000 V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Depends on range.
3. 100pF through 1500Ω; MIL-STD-883C, 3015.7

Figure 3. Block Diagram

E G W

VPP GEN RESET CONTROL LOGIC

ADDRESS
A6-A14
LATCH
(Page Address)
X DECODE

256K ARRAY

ADDRESS
A0-A5
LATCH

Y DECODE SENSE AND DATA LATCH

I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
AI01697

3/21
M28256

Table 3. Operating Modes (1)

Mode E G W DQ0 - DQ7

Read VIL VIL VIH Data Out

Write VIL VIH VIL Data In

Standby / Write Inhibit VIH X X Hi-Z

Write Inhibit X X VIH Data Out or Hi-Z

Write Inhibit X VIL X Data Out or Hi-Z

Output Disable X VIH X Hi-Z

Notes: 1. X = VIH or VIL.

DESCRIPTION (Cont’d) Read

The device is accessed like a static RAM. When E
The devices offer fast access time with low power and G are low with W high, the data addressed is
dissipation and requires a 5V or 3V power supply. presented on the I/O pins. The I/O pins are high
The circuit has been designed to offer a flexible impedance when either G or E is high.
microcontroller interface featuring both hardware Write
and software handshaking with Data Polling and
Toggle Bit and access to a status register. The Write operations are initiated when both W and E
devices support a 64 byte page write operation. A are low and G is high.The device supports both E
Software Data Protection (SDP) is also possible and W controlled write cycles. The Address is
using the standard JEDEC algorithm. latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
PIN DESCRIPTION operation is internally timed until completion and
Addresses (A0-A14). The address inputs select the status of the Data Polling and the Toggle Bit
an 8-bit memory location during a read or write functions on DQ7 and DQ6 is controlled accord-
operation. ingly.
Chip Enable (E). The chip enable input must be Page Write
low to enable all read/write operations.When Chip Page write allows up to 64 bytes within the same
Enable is high, power consumption is reduced. page to be consecutively latched into the memory
Output Enable (G). The Output Enable input con- prior to initiating a programming cycle. All bytes
trols the data output buffers and is used to initiate must be located in a single page address, that is
read operations. A14-A6 must be the same for all bytes; if not, the
Data In/ Out (DQ0- DQ7). Data is written to or read Page Write instruction is not executed. The page
from the memory through the I/O pins. write can be initiated by any byte write operation.
Write Enable (W). The Write Enable input controls A page write is composed of successive Write
the writing of data to the memory. instructions which have to be sequenced with a
specific period of time between two consecutive
Write instructions, period of time which has to be
OPERATIONS smaller than the tWHWH value (see Table 12 and
Write Protection Table 13).
In order to prevent data corruption and inadvertent If this period of time exceeds the tWHWH value, the
write operations; an internal VCC comparatorinhib- internal programmingcycle will start. Once initiated
its Write operations if VCC is below VWI (see Table the write operation is internally timed until comple-
7 andTable 9).Access to the memoryin write mode tion and the status of the Data Polling and the
is allowed after a power-up as specified in Table 7 Toggle Bit functions on DQ7 and DQ6 is controlled
and Table 9. accordingly.

4/21
 M28256

Status Register Software Data Protection

The devices provide several Write operation status The devices offer a software controlled write pro-
flags that can be used to minimize the application tection facility that allows the user to inhibit all write
write time. These signals are available on the I/O modes to the device. This can be useful in protect-
port bits during programming cycle only. ing the memory from inadvertent write cycles that
may occur due to uncontrolledbus conditions.
Data Polling bit (DQ7). During the internal write
cycle, any attempt to read the last byte written will The devices are shipped as standardin the ”unpro-
tected” state meaning that the memory contents
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin- can be changed as required by the user. After the
ished the true logic value appears on DQ7 in the Software Data Protection enable algorithm is is-
sued, the device enters the ”Protect Mode” of
read cycle.
operation where no further write commands have
Toggle bit (DQ6). The devices offer another way any effect on the memory contents.
for determining when the internal write cycle is The devices remain in this mode until a valid
completed. During the internal Erase/Write cycle, Software Data Protection (SDP) disable sequence
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the is received whereby the device reverts to its ”un-
first read value is ”0”) on subsequent attempts to protected” state. The Software Data Protection is
read any byte of the memory. When the internal fully non-volatile and is not changed by power
cycle is completed the toggling will stop and the on/off sequences. To enable the Software Data
data read on DQ7-DQ0 is the addressed memory Protection (SDP) the device requires the user to
byte. The device is now accessible for a new Read write (with a Page Write addressing three specific
or Write operation. data bytes to three specific memorylocations,each
Page Load TimerStatus bit(DQ5). Duringa Page location in a different page) as per Figure 6. Simi-
Write instruction, the devices expect to receive the larly to disable the Software Data Protection the
stream of data with a minimum period of time user has to write specific data bytes into six differ-
between each data byte. This period of time ent locations as per Figure 5 (with a Page Write
(tWHWH) is defined by the on-chip Page Load timer adressing different bytes in different pages).
which running/overflow status is available on DQ5. This complexseries ensures that the userwill never
DQ5 Low indicates that the timer is running, DQ5 enable or disable the Software Data Protection
High indicates the time-out after which the internal accidentally.
write cycle will start. To write into the devices when SDP is set, the
sequence shown in Figure 6 must be used. This
Figure 4. Status Bit Assignment sequence provides an unlock key to enable the
write action, and at the same time SDP continues
to be set.
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
An extension to this is where SDP is required to be
DP TB PLTS X X X X X set, and data is to be written.
Using the same sequence as above, the data can
DP = Data Polling
TB = Toggle Bit
be written and SDP is set at the same time, giving
PLTS = Page Load Timer Status both these actions in the same Write cycle (tWC).

5/21
M28256

Figure 5. Software Data Protection Enable Algorithm and Memory Write

SDP SDP
Set not Set

WRITE AAh in WRITE AAh in

Address 5555h Address 5555h

Page WRITE 55h in WRITE 55h in

Write Address 2AAAh Address 2AAAh
Instruction
Page
WRITE A0h in Write WRITE A0h in
Address 5555h Instruction Address 5555h
WRITE
is enabled
SDP is set
WRITE Data to
be Written in
any Address

Write Write Data

SDP ENABLE ALGORITHM in Memory +
SDP Set
after tWC

AI01698B

Figure 6. Software Data Protection Disable Algorithm

WRITE AAh in
Address 5555h

WRITE 55h in
Address 2AAAh

WRITE 80h in
Page Address 5555h
Write
Instruction
WRITE AAh in
Address 5555h

WRITE 55h in
Address 2AAAh

WRITE 20h in
Address 5555h

Unprotected State
after
tWC (Write Cycle time)

AI01699B

6/21
 M28256

Table 4. AC Measurement Conditions

Input Rise and Fall Times ≤ 20ns
Input Pulse Voltages (M28256) 0.4V to 2.4V
Input Pulse Voltages (M28256-W) 0V to V CC –0.3V
Input and Output Timing Ref. Voltages (M28256) 0.8V to 2.0V
Input and Output Timing Ref. Voltages (M28256-W) 0.5 VCC

Figure 7. AC Testing Input Output Waveforms Figure 8. AC Testing Equivalent Load Circuit
4.5V to 5.5V Operating Voltage

2.4V
2.0V

0.8V IOL
0.4V
DEVICE
UNDER OUT
2.7V to 3.6V Operating Voltage TEST
IOH
VCC – 0.3V CL = 100pF
0.5 VCC

0V

AI02101B
CL includes JIG capacitance
AI02102B

Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )

Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6 pF

C OUT Output Capacitance VOUT = 0V 12 pF

Note: 1. Sampled only, not 100% tested.

Table 6. Read Mode DC Characteristics for M28256

(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC 10 µA
ILO Output Leakage Current 0V ≤ VIN ≤ VCC 10 µA

(1) Supply Current (TTL inputs) E = VIL, G = VIL , f = 5 MHz 30 mA

ICC
Supply Current (CMOS inputs) E = VIL, G = VIL , f = 5 MHz 25 mA
(1)
ICC1 Supply Current (Standby) TTL E = VIH 1 mA
(1)
ICC2 Supply Current (Standby) CMOS E > VCC –0.3V 100 µA
VIL Input Low Voltage – 0.3 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 2.1 mA 0.4 V
VOH Output High Voltage IOH = –400 µA 2.4
Note: 1. All I/O’s open circuit.

7/21
M28256

Table 7. Power Up Timing for M28256 (1)

(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol Parameter Min Max Unit

tPUR Time Delay to Read Operation 1 µs

tPUW Time Delay to Write Operation (once VCC ≥ VWI) 5 ms
VWI Write Inhibit Threshold 3.0 4.2 V
Note: 1. Sampled only, not 100% tested.

Table 8. Read Mode DC Characteristics for M28256-W

(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC 10 µA
ILO Output Leakage Current 0V ≤ VIN ≤ VCC 10 µA

(1) E = VIL, G = VIL, f = 5 MHz, V CC = 3.3V 15 mA

ICC Supply Current (CMOS inputs)
E = VIL, G = VIL, f = 5 MHz, V CC = 3.6V 15 mA
(1)
ICC2 Supply Current (Standby) CMOS E > VCC –0.3V 20 µA
VIL Input Low Voltage – 0.3 0.6 V
VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 2.1 mA 0.2 VCC V

VOH Output High Voltage IOH = –400 µA 0.8 VCC V
Note: 1. All I/O’s open circuit.

Table 9. Power Up Timing for M28256-W (1)

(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol Parameter Min Max Unit

tPUR Time Delay to Read Operation 1 µs

tPUW Time Delay to Write Operation (once VCC ≥ VWI) 10 ms

VWI Write Inhibit Threshold 1.5 2.5 V

Note: 1. Sampled only, not 100% tested.

8/21
 M28256

Table 10. Read Mode AC Characteristics

(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
M28256
Symbol Alt Parameter Test Condition Unit
-90 -12 -15 -20
min max min max min max min max

Address Valid to
tAVQV tACC E = VIL, G = VIL 90 120 150 200 ns
Output Valid

Chip Enable Low to

tELQV tCE G = VIL 90 120 150 200 ns
Output Valid
Output Enable Low
tGLQV tOE E = VIL 40 45 50 50 ns
to Output Valid

Chip Enable High to

tEHQZ (1) tDF G = VIL 0 40 0 45 0 50 0 50 ns
Output Hi-Z
Output Enable High
tGHQZ (1) tDF E = VIL 0 40 0 45 0 50 0 50 ns
to Output Hi-Z
Address Transition
tAXQX tOH E = VIL, G = VIL 0 0 0 0 ns
to Output Transition
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.

Table 11. Read Mode AC Characteristics

(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
M28256-W
Symbol Alt Parameter Test Condition Unit
-12 -15 -20 -25
min max min max min max min max
Address Valid to
tAVQV tACC E = VIL, G = VIL 120 150 200 250 ns
Output Valid
Chip Enable Low to
tELQV tCE G = VIL 120 150 200 250 ns
Output Valid
Output Enable Low
tGLQV tOE E = VIL 45 70 80 100 ns
to Output Valid

(1) Chip Enable High to

tEHQZ tDF G = VIL 0 45 0 50 0 55 0 60 ns
Output Hi-Z

Output Enable High

tGHQZ (1) tDF E = VIL 0 45 0 50 0 55 0 60 ns
to Output Hi-Z
Address Transition
tAXQX tOH E = VIL, G = VIL 0 0 0 0 ns
to Output Transition
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.

9/21
M28256

Table 12. Write Mode AC Characteristics

(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
M28256
Symbol Alt Parameter Test Condition Unit
Min Max

tAVWL tAS Address Valid to Write Enable Low E = VIL, G = VIH 0 ns

tAVEL tAS Address Valid to Chip Enable Low G = VIH, W = VIL 0 ns

tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns

Output Enable High to Write Enable

tGHWL tOES E = VIL 0 ns
Low

tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns

tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns

tWLAX tAH Write Enable Low to Address Transition 50 ns

tELAX tAH Chip Enable Low to Address Transition 50 ns

tWLDV tDV Write Enable Low to Input Valid E = VIL, G = VIH 1 µs

tELDV tDV Chip Enable Low to Input Valid G = VIH, W = VIL 1 µs

tELEH tWP Chip Enable Low to Chip Enable High 50 ns

tWHEH tCEH Write Enable High to Chip Enable High 0 ns

Write Enable High to Output Enable

tWHGL tOEH 0 ns
Low

tEHGL tOEH Chip Enable High to Output Enable Low 0 ns

tEHWH tWEH Chip Enable High to Write Enable High 0 ns

tWHDX tDH Write Enable High to Input Transition 0 ns

tEHDX tDH Chip Enable High to Input Transition 0 ns

tWHWL tWPH Write Enable High to Write Enable Low 100 ns

tWLWH tWP Write Enable Low to Write Enable High 50 ns

tWHWH tBLC Byte Load Repeat Cycle Time 0.15 150 µs

tWHRH tWC Write Cycle Time 5 ms

tEL, tWL E or W Input Filter Pulse Width Note 1 10 ns

tDVWH tDS Data Valid before Write Enable High 50 ns

tDVEH tDS Data Valid before Chip Enable High 50 ns

Note: 1. Characterized only but not tested in production.

10/21
 M28256

Table 13. Write Mode AC Characteristics

(TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
M28256-W
Symbol Alt Parameter Test Condition Unit
Min Max

tAVWL tAS Address Valid to Write Enable Low E = VIL, G = VIH 0 ns

tAVEL tAS Address Valid to Chip Enable Low G = VIH, W = VIL 0 ns

tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns

Output Enable High to Write Enable

tGHWL tOES E = VIL 0 ns
Low

tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns

tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns

tWLAX tAH Write Enable Low to Address Transition 70 ns

tELAX tAH Chip Enable Low to Address Transition 70 ns

tWLDV tDV Write Enable Low to Input Valid E = VIL, G = VIH 1 µs

tELDV tDV Chip Enable Low to Input Valid G = VIH, W = VIL 1 µs

tELEH tWP Chip Enable Low to Chip Enable High 100 ns

tWHEH tCEH Write Enable High to Chip Enable High 0 ns

Write Enable High to Output Enable

tWHGL tOEH 0 ns
Low

tEHGL tOEH Chip Enable High to Output Enable Low 0 ns

tEHWH tWEH Chip Enable High to Write Enable High 0 ns

tWHDX tDH Write Enable High to Input Transition 0 ns

tEHDX tDH Chip Enable High to Input Transition 0 ns

tWHWL tWPH Write Enable High to Write Enable Low 100 ns

tWLWH tWP Write Enable Low to Write Enable High 100 ns

tWHWH tBLC Byte Load Repeat Cycle Time 0.2 150 µs

tWHRH tWC Write Cycle Time 5 ms

tEL, tWL E or W Input Filter Pulse Width Note 1 10 ns

tDVWH tDS Data Valid before Write Enable High 50 ns

tDVEH tDS Data Valid before Chip Enable High 50 ns

Note: 1. Characterized only but not tested in production.

11/21
M28256

Figure 9. Read Mode AC Waveforms

A0-A14 VALID

tAVQV tAXQX

tGLQV tEHQZ

tELQV tGHQZ
Hi-Z
DQ0-DQ7 DATA OUT

AI01700

Note: Write Enable (W) = High.

Figure 10. Write Mode AC Waveforms - Write Enable Controlled

A0-A14 VALID

tAVWL tWLAX

tELWL tWHEH

tGHWL tWLWH tWHGL

tWLDV tWHWL

DQ0-DQ7 DATA IN

tDVWH tWHDX

AI01701

12/21
 M28256

Figure 11. Write Mode AC Waveforms - Chip Enable Controlled

A0-A14 VALID

tAVEL tELAX

tGHEL tELEH

tWLEL tEHGL

tELDV tEHWH

DQ0-DQ7 DATA IN

tDVEH tEHDX

AI01702

Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled

A0-A14 Addr 0 Addr 1 Addr 2 Addr n

tWHWL tWHRH

tWLWH tWHWH tWHWH

DQ0-DQ7 Byte 0 Byte 1 Byte 2 Byte n

DQ5 Byte n

AI01703B

13/21
M28256

Figure 13. Software Protected Write Cycle Waveforms

tWLWH tWHWL tWHWH

tAVEL tWLAX

A0-A5 Byte Address

tWHDX

A6-A14 5555h 2AAAh 5555h Page Address

tDVWH

DQ0-DQ7 AAh 55h A0h Byte 0 Byte 62 Byte 63

AI01704

Note: A6 through A14 must specify the same page address during each high to low transition of W (or E) after the software code has been
entered. G must be high only when W and E are both low.

Figure 14. Data Polling Waveform Sequence

A0-A14 Address of the last byte of the Page Write instruction

DQ7

DQ7 DQ7 DQ7 DQ7 DQ7

LAST WRITE INTERNAL WRITE SEQUENCE READY

AI01705

14/21
 M28256

Figure 15. Toggle Bit Waveform Sequence

A0-A14

DQ6 (1)

DQ6 DQ6

LAST WRITE TOGGLE READY

INTERNAL WRITE SEQUENCE

AI01706

Note: 1. First Toggle bit is forced to ’0’.

15/21
M28256

ORDERING INFORMATION SCHEME

Example: M28256 – 15 W KA 6 T

Speed Operating Voltage Package Temperature Range Option

90 (1)
90ns blank 4.5V to 5.5V BS PDIP28 1 (3)
0 to 70 °C T Tape & Reel
Packing
12 120ns W 2.7V to 3.6V KA PLCC32 6 –40 to 85 °C
15 150ns MS SO28 300 mils
20 200ns NS TSOP28
8 x 13.4mm
25 (2) 250ns

Notes: 1. Not available for ”W” operating voltage.

2. Available for ”W” operating voltage only.
3. Temperature Range on request only.

Devices are shipped from the factory with the memory content set at all ”1’s” (FFh).

For a list of available options (Speed, Package, etc...) or for further informationon any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.

16/21
 M28256

PDIP28 - 28 pin Plastic DIP, 600 mils width

mm inches
Symb
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 36.83 37.34 1.450 1.470
D2 33.02 – – 1.300 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.08 0.070 0.082
α 0° 10° 0° 10°
N 28 28

A2 A

A1 L α
B1 B e1 C
eA
D2 eB

D
S
N

E1 E

1
PDIP

Drawing is not to scale.

17/21
M28256

PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular

mm inches
Symb
Typ Min Max Typ Min Max
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N 32 32
Nd 7 7
Ne 9 9

D A1
D1 A2

1 N
B1

E1 E e
Ne F D2/E2
B
0.51 (.020)

1.14 (.045)

Nd A

R CP
PLCC

Drawing is not to scale.

18/21
 M28256

SO28 - 28 lead Plastic Small Outline, 300 mils body width

mm inches
Symb
Typ Min Max Typ Min Max
A 2.46 2.64 0.097 0.104
A1 0.13 0.29 0.005 0.011
B 0.35 0.48 0.014 0.019
C 0.23 0.32 0.009 0.013
D 17.81 18.06 0.701 0.711
E 7.42 7.59 0.292 0.299
e 1.27 – – 0.050 – –
H 10.16 10.41 0.400 0.410
L 0.61 1.02 0.024 0.040
α 0° 8° 0° 8°
N 28 28
CP 0.10 0.004

A2 A
C
B
e CP

E H
1
A1 α L

SO-b

Drawing is not to scale.

19/21
M28256

TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm

mm inches
Symb
Typ Min Max Typ Min Max
A 1.25 0.049
A1 0.20 0.008
A2 0.95 1.15 0.037 0.045
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 13.20 13.60 0.520 0.535
D1 11.70 11.90 0.461 0.469
E 7.90 8.10 0.311 0.319
e 0.55 - - 0.022 - -
L 0.50 0.70 0.020 0.028

α 0° 5° 0° 5°
N 28 28
CP 0.10 0.004

A2

22 21
e

28
1 E

B
7 8

D1 A
D CP

DIE

TSOP-c A1 α L

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