M24128-U

Datasheet

128-Kbit serial I²C bus EEPROM with unique identifier

Features
I²C interface
• Compatible with the following I²C bus modes:
– 100 kHz (Standard-mode)
– 400 kHz (Fast-mode)
SO8N (MN) – 1 MHz (Fast-mode Plus)
150 mil width
Memory
• 128-Kbit (16-Kbyte) of EEPROM
• Page size: 64-byte

Identification page
• 512-bit (64-byte) locked in read-only at factory delivery
Product status

M24128-U UID
• 128-bit (16-byte) unique factory-programmed serial number
Product label
Supply voltage
• Wide voltage range: 1.7 V to 5.5 V

Temperature
• Operating temperature range: -40 °C to +85 °C

Performance
• Enhanced ESD and latch-up protection
• ESD protection: 4 kV (HBM)
• More than 4 million write cycles
• More than 200-year data retention

Advanced features
• Random and sequential read modes
• Hardware write protection of the whole memory array
• Byte and page write within 5 ms

Package
• SO8N (ECOPACK2 compliant)

Applications

Applications of EEPROM UID include:

• Improved traceability for accessory recognition
• Enhanced repairability

DS14837 - Rev 1 - February 2025 www.st.com

For further information, contact your local STMicroelectronics sales office.
 M24128-U

• Promoting sustainability in the consumer and industrial segments, such as:

– Data centers
– Logistics
– Healthcare
– Personal electronics

DS14837 - Rev 1 page 2/37

 M24128-U
Description

1 Description

The M24128-U is a 128-Kbit I²C-compatible EEPROM (electrically erasable programmable memory) organized as
16 K × 8 bits. It can operate with a supply voltage of 1.7 V to 5.5 V, over an ambient temperature range from -40
°C to +85 °C.
The device offers an additional page, named the identification page (64 bytes). This page stores a 128‑bit (16
bytes) unique factory-programmed serial number, which is frozen in read-only mode on delivery from the factory.
The uniqueness of the serial number is ensured across the whole portfolio of serial EEPROMs manufactured by
STMicroelectronics, offering a unique identifier.

Figure 1. Logic diagram

VCC

3
E0-E2

SCL M24xxx SDA

WC

DT74692V1
VSS

Table 1. Signal names

Signal name Function Direction

E2, E1, E0 Chip enable Input

SDA Serial data I/O
SCL Serial clock Input
VCC Supply voltage -
VSS Ground -
WC Write control Input

Figure 2. 8-pin package connections, top view

E0 1 8 VCC

E1 2 7 WC

E2 3 6 SCL
DT74509V2

VSS 4 5 SDA

DS14837 - Rev 1 page 3/37

 M24128-U
Signal description

2 Signal description

2.1 Serial clock (SCL)

SCL is an input. The signal applied on it is used to strobe the data available on SDA(in) and to output the data on
SDA(out).

2.2 Serial data (SDA)

SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that
may be wired‑AND with other open drain or open collector signals on the bus. A pull‑up resistor must be
connected from serial data (SDA) to VCC (Figure 14 and Figure 15 indicate how to calculate the value of the
pull‑up resistor).

2.3 Chip enable (E2, E1, E0)

The input signals E2, E1, and E0 set the value for the three least significant bits (b3, b2, and b1) of the 7-bit
device select code (see Table 3). They must be connected to VCC or VSS to establish the device select code, as
shown in Figure 3. When they are not connected (left floating), these inputs are read as low (0, 0, 0).

Figure 3. Chip enable inputs connection

VCC VCC

M24xxx-U M24xxx-U

Ei Ei

DT74693V1
VSS VSS

2.4 Write control (WC)

This input signal is useful for protecting the whole content of the memory from inadvertent write operations. Write
operations are:
• Disabled to the whole memory array when write control is driven high.
• Enabled when write control is either driven low or left floating.
When the write control signal is driven high, the device select and address bytes are acknowledged, but data
bytes are not acknowledged.

2.5 VSS (ground)

VSS is the reference for all signals, including the VCC supply voltage.

2.6 Supply voltage (VCC)

2.6.1 Operating supply voltage (VCC)

Before selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified
[VCC(min), VCC(max)] range must be applied (see Table 7). To secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually from 10 to 100 nF) close to the
VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write
instruction, until the completion of the internal write cycle (tW).

DS14837 - Rev 1 page 4/37

 M24128-U
Signal description

2.6.2 Power-up conditions

The VCC voltage must rise continuously from 0 V up to the minimum VCC operating voltage (see Table 7).

2.6.3 Device reset

To prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold
voltage. This threshold is lower than the minimum VCC operating voltage (see Table 7). When VCC passes over
the POR threshold, the device is reset and enters the standby power mode; however, the device must not be
accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see
Table 7).
Similarly, during power-down, when VCC decreases, the device must not be accessed once VCC drops below
VCC(min). When VCC drops below the POR threshold voltage, the device stops responding to any instruction
sent to it.

2.6.4 Power-down conditions

During power-down, when VCC decreases, the device must be in the standby power mode (the mode is reached
after decoding a stop condition, with no internal write cycle in progress).

DS14837 - Rev 1 page 5/37

 M24128-U
Memory organization

3 Memory organization

The memory is organized as shown in the following figure.

Figure 4. Block diagram

SENSE AMPLIFIERS
DATA REGISTER
+
ECC
PAGE LATCHES X DECODER

Y DECODER
SCL ARRAY

I/O

SDA
(1)
CONTROL IDENTIFICATION PAGE
START & STOP LOGIC
WC HV GENERATOR
DETECT +
Ei SEQUENCER

ADDRESS
REGISTER

1. Identification page with the UID

DS14837 - Rev 1 page 6/37

 M24128-U
Device features

4 Device features

4.1 Identification page

This is an additional 64-byte page, permanently locked in read-only mode. The user can read it by issuing the
read identification page instruction. This instruction uses the same protocol and format as the random address
read (from the memory array), except for the following differences (refer to Table 3, Table 4, and Table 5):
• Device type identifier = 1011
• MSB address bits from A15 to A8 are Don't care
• LSB address bits from A7 to A6 are Don't care
• LSB address bits from A5 to A0: Define the byte address within the identification page

4.2 Unique identifier (UID)

The M24128-U provides an additional feature: a serial number programmed at factory level, and locked in
read‑only mode within the identification page. This preprogrammed, 16-byte unique ID is a 128-bit serial number.
The 128-bit serial number is unique across the all STMicroelectronics UID-family EEPROM devices.
This UID can be read by issuing the read identification page instruction.
• Device type identifier = 1011
• MSB address bits from A15 to A8 must be equal to 0
• LSB address bits from A7 to A4 must be equal to 0
• LSB address bits from A3 to A0 define the UID byte address within the identification page
The description of the UID is given in the following table.

Table 2. UID address in the identification page

UID address in the identification page (hex) Description Value (hex)

00 Header – STM code 20

01 Header – Bus protocol E0
02 Header - Density 0E
03 Header – Unused FF
04
05
06
07
08
09
UID
0A
0B
0C
0D
0E
0F

DS14837 - Rev 1 page 7/37

 M24128-U
Device operation

5 Device operation

The device supports the I²C protocol. This is summarized in Figure 5. Any device that sends data onto the bus is
defined as a transmitter, and any device that reads the data is defined as a receiver. The device that controls the
data transfer is known as the bus controller, and the other as the target device. A data transfer can only be
initiated by the bus controller, which also provides the serial clock for synchronization. The device is always a
target in all communications.

Figure 5. I²C bus protocol

SCL

SDA

SDA SDA
START STOP
Input Change
Condition Condition

SCL 1 2 3 7 8 9

SDA MSB ACK

START
Condition

SCL 1 2 3 7 8 9

SDA MSB ACK

DT00792D_V1

STOP
Condition

5.1 Start condition

The start condition is identified by a falling edge of serial data (SDA) while the serial clock (SCL) is stable in the
high state. This condition must precede any data transfer instruction. The device continuously monitors the SDA
and SCL for a start condition, except during a write cycle.

5.2 Stop condition

The stop condition is identified by a rising edge of serial data (SDA) while the serial clock (SCL) is stable in the
high state. This condition terminates the communication between the device and the bus controller. A read
instruction followed by a NO ACK can be followed by a stop condition to force the device into the standby mode.
A stop condition at the end of a write instruction triggers the internal write cycle.

DS14837 - Rev 1 page 8/37

 M24128-U
Device operation

5.3 Data input

During data input, the device samples serial data on the rising edge of the serial clock. For proper device
operation, the SDA must be stable during the rising edge of the SCL, and the SDA signal must change only when
the SCL is driven low.

5.4 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether a bus controller
or target device, releases serial data (SDA) after sending eight bits of data. During the ninth clock pulse period,
the receiver pulls SDA low to acknowledge the receipt of the eight data bits.

5.5 Device addressing

To start communication between the bus controller and the target device, the bus controller must initiate a start
condition. Following this, the bus controller sends the device select code and bytes address as specified in
Table 3, Table 4, and Table 5.
If a match occurs on the device select code, the corresponding device gives an acknowledgment on the serial
data (SDA) during the interval. If the device does not match the device select code, it deselects itself from the
bus, and goes into standby mode.
The eighth bit is the read/write bit (RW), set to 1 for read operations and to 0 for write operations.

Table 3. Device select code

Device type identifier Chip enable address RW

Features
Bit 7 (MSB)(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

Memory 1 0 1 0 E2 E1 E0 RW
Identification page 1 0 1 1 E2 E1 E0 RW
UID 1 0 1 1 E2 E1 E0 RW

1. The most significant bit, b7, is sent first.

Table 4. First byte address

Features Bit 7 (MSB)(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

Memory A15(2) A14(2) A13 A12 A11 A10 A9 A8

Identification page X(3) X X X X X X X

UID 0 0 0 0 0 0 0 0

1. The most significant bit, b7, is sent first.

2. Don't care
3. X = Don't care bit.

Table 5. Second byte address

Features Bit 7 (MSB)(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

Memory A7 A6 A5 A4 A3 A2 A1 A0

Identification page X (2) X A5 A4 A3 A2 A1 A0

UID 0 0 0 0 A3 A2 A1 A0

1. The most significant bit, b7, is sent first.

2. X = Don't care bit.

DS14837 - Rev 1 page 9/37

 M24128-U
Instructions

6 Instructions

6.1 Write operations on memory array

Following a start condition, the bus controller sends a device select code with the RW bit reset to 0. The device
acknowledges this, as shown in Figure 6, and waits for two address bytes. The device responds to each address
byte with an acknowledge bit, and then waits for the data byte.
When the bus controller generates a stop condition immediately after a data byte ACK bit (in the tenth bit time
slot), either at the end of a byte write or a page write, the internal write cycle tW is triggered. A stop condition at
any other time slot does not trigger the internal write cycle.
After the stop condition and the successful completion of an internal write cycle (tW), the device internal address
counter is automatically incremented to point to the next byte after the last modified byte.
During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any
requests.
If the addressed area is write protected with the write control input (WC) driven high, the write instruction is not
executed and the accompanying data bytes are not acknowledged, as shown in Figure 7.

DS14837 - Rev 1 page 10/37

 M24128-U
Instructions

6.1.1 Byte write

After the device select code and the address bytes, the bus controller sends one data byte. If the addressed
location is write-protected, by write control (WC) being driven high, the device replies with NO ACK, and the
location is not modified. If, instead, the addressed location is not write-protected, the device replies with ACK. The
bus controller terminates the transfer by generating a stop condition, as shown in the following figure.

Figure 6. Write mode sequences with WC = 0 (data write enabled)

WC

ACK ACK ACK ACK

Byte write Dev sel Byte addr Byte addr Data in

Start

Stop
RW

WC

ACK ACK ACK ACK

Page write Dev sel Byte addr Byte addr Data in 1 Data in 2
Start

RW

WC (cont’d)

ACK ACK

Page write (cont’d) Data in N

DT01106dV2
Stop

DS14837 - Rev 1 page 11/37

 M24128-U
Instructions

6.1.2 Page write

The page write allows up to 64-byte to be written in a single write cycle, provided that they are all located in the
same page. This means the most significant memory address bits from A15 to A6 are the same. If more bytes are
sent than fit within the page, a roll-over occurs: the bytes exceeding the page end are written from location 0 on
the same page.
The bus controller sends from 1 to 64 bytes of data, each of them is acknowledged by the device if write control
(WC) is low. If write control (WC) is high, the contents of the addressed memory location are not modified, and
each data byte is followed by a NO ACK, as shown in Figure 7. After each transferred byte, the internal page
address counter increments.
The transfer is terminated by the bus controller generating a stop condition.

Figure 7. Write mode sequences with WC = 1 (data write inhibited)

WC

Byte write

WC

Page write

Page write (cont’d)

DT01120dV2

DS14837 - Rev 1 page 12/37

 M24128-U
Instructions

6.2 Write operations on the identification page

Write operations on the identification page are not allowed, as this page is delivered locked in read-only.

6.3 Error correction code (ECC) and write cycling

The ECC is an internal logic function transparent for the I2C communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes. Within a group, if a single bit happens to be
erroneous during a read operation, the ECC detects this bit and replaces it with the correct value. The read
reliability is therefore much improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently.
In this case, the ECC function also writes/cycles the three other bytes located in the same group (a group of four
bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.)
As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over
the four bytes of the group: the sum of the cycles seen by byte 0, byte 1, byte 2, and byte 3 of the same group
must remain below the maximum value defined in Table 10.

DS14837 - Rev 1 page 13/37

 M24128-U
Instructions

6.4 Minimizing write delays by polling on ACK

During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its
internal latches to the memory cells. The maximum write time (tw) is shown in the AC characteristics tables in
Section 9: DC and AC parameters, but the typical time is shorter. The bus controller can implement a polling
sequence to utilize this feature.
The sequence, as shown in Figure 8, is:
• Initial condition: A write cycle is in progress.
• Step 1: The bus controller issues a start condition followed by a device select code (the first byte of the
new instruction).
• Step 2: If the device is busy with the internal write cycle, NO ACK is returned and the bus controller goes
back to step 1. If the device has terminated the internal write cycle, it responds with an ACK, indicating that
the device is ready to receive the second part of the instruction (the first byte of this instruction having been
sent during step 1).

Figure 8. Write cycle polling flowchart using ACK

Write cycle
in progress

Start condition

Device select
with RW = 0

NO ACK
returned

First byte of instruction YES

with RW = 0 already
decoded by the device

Next
NO operation is YES
addressing the
memory
Send address
Restart and receive ACK

Stop NO YES
StartCondition

Data for the Device select

write operation with RW = 1
DT01847eV1

Continue the Continue the

write operation random read operation

1. The seven most significant bits of the device select code in a random read (bottom right box in the figure) must match those
of the device select code in the write operation (polling instruction in the figure).

DS14837 - Rev 1 page 14/37

 M24128-U
Instructions

6.5 Read operations on the memory array

Following a start condition the bus controller sends a device select code with the RW bit set to 0. The device
acknowledges this and waits for the two-bytes address. The device responds to each address byte with an
acknowledge bit. Then, the bus controller sends another start condition, and repeats the device select code, with
the RW bit set to 1. The device acknowledges this, and outputs the contents of the data. See in
Section 5.5: Device addressing (Table 3, Table 4, and Table 5) how to address the memory array.
After each byte read (data out), the device waits for an acknowledgment (data in) during the ninth bit time. If the
bus controller does not acknowledge during this interval, the device terminates the data transfer and switches to
its standby mode after a stop condition.
After successfully completing a read operation, the system increments the internal address counter by one to
point to the next byte address.

Figure 9. Read mode sequences

ACK NO ACK
Current
address Dev sel Data out
read
Start

Stop
RW

ACK ACK ACK ACK NO ACK

Random
address Dev sel * Byte addr Byte addr Dev sel * Data out
read
Start

Start

Stop
RW RW

ACK ACK ACK NO ACK

Sequential
current Dev sel Data out 1 Data out N
read
Start

Stop

RW

ACK ACK ACK ACK ACK

Sequential
random Dev sel * Byte addr Byte addr Dev sel * Data out1
read
Start

Start

RW RW

ACK NO ACK

Data out N
DT01105dV1
Stop

Note: *: The seven most significant bits of the first device select code in a random read must match those of the device
select code in the write operation.

DS14837 - Rev 1 page 15/37

 M24128-U
Instructions

6.5.1 Random address read

A dummy write is first performed to load the address into this address counter (as shown in Figure 9. Read mode
sequences) without sending a stop condition. Then, the bus controller sends another start condition, and repeats
the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the
addressed byte. The bus controller must not acknowledge the byte, and terminates the transfer with a stop
condition.

6.5.2 Current address read

For the current address read operation, following a start condition, the bus controller sends only a device select
code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal
address counter. The counter is then incremented. The bus controller terminates the transfer with a stop
condition, as shown in Figure 9. Read mode sequences, without acknowledging the byte.
Note: The address counter value is defined by instructions accessing either the memory or the identification page.
When accessing the identification page, the address counter value is loaded with the identification page byte
location, therefore the next current address read in the memory uses this new address counter value. When
accessing the memory, it is safer to use the random address read instruction (this instruction loads the address
counter with the byte location to read in the memory) instead of the current address read instruction.

6.5.3 Sequential read

This operation can be used after a current address read or a random address read. The bus controller does
acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the
next byte in sequence. To terminate the stream of bytes, the bus controller must not acknowledge the last byte,
and must generate a stop condition, as shown in Figure 9. Read mode sequences.
The output data comes from consecutive addresses, with the internal address counter automatically incremented
after each byte output. After the last memory address, the address counter rolls-over, and the device continues to
output data from memory address 00h.

DS14837 - Rev 1 page 16/37

 M24128-U
Instructions

6.6 Read operations on identification page

Following a start condition, the bus controller sends a device select code with the RW bit set to 0. The device
acknowledges this and waits for the address bytes where the identification page is located. The device responds
to each address byte with an acknowledge bit. The bits from A5 to A0 define the byte address within the
identification page. Then, the bus controller sends another start condition, and repeats the same device select
code but with the RW bit set to 1. The device acknowledges this, and outputs the contents of the identification
page. See in Table 3, Table 4, and Table 5 how to address the identification page.
The number of bytes to read in the ID page must not exceed the page boundary (for instance: when reading the
identification page from location 10d, the number of bytes should be less than or equal to 54, as the ID page
boundary is 64 bytes).
To terminate the stream of data byte, the bus controller must not acknowledge the byte, and must generate a stop
condition, as shown in Figure 10.

Figure 10. Random read on identification page

ACK ACK ACK ACK NO ACK

Random
address Dev sel * Byte addr Byte addr Dev sel * Data out
read
Start

Start

Stop
RW RW

ACK ACK ACK ACK ACK

Sequential
random Dev sel * Byte addr Byte addr Dev sel * Data out1
read
Start

Start

RW RW

ACK NO ACK

Data out N

DT54535V2
Stop

Note: *: The seven most significant bits of the first device select code in a random read must match those of the device
select code in the write operation.

6.7 Read lock status on identification page

The lock or unlock status of the identification page can be checked by transmitting a specific truncated command.
Following a start condition the bus controller sends a device select code with the RW bit set to 0. The device
acknowledges this and waits for the address bytes where the identification page is located. The device responds
to each address byte with an acknowledge bit, and then waits for the data byte. See in Table 3, Table 4, and
Table 5 how to address the identification page.
The device returns an acknowledge bit after the data byte if the identification page is unlocked (unlock status) as
shown in Figure 11, otherwise a NO ACK bit as shown in Figure 12, if the identification page is locked (lock
status).
Right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that:
• Start: the truncated command is not executed because the start condition resets the device internal logic
• Stop: the device is set back into standby mode by the stop condition

DS14837 - Rev 1 page 17/37

 M24128-U
Instructions

Figure 11. Read lock status (identification page unlocked)

ACK ACK ACK ACK

Dev sel Byte addr Byte addr Data in

DT54538V1
Stop
Start

Start
RW

Figure 12. Read lock status (identification page locked)

ACK ACK ACK NO ACK

Dev sel Byte addr Byte addr Data in

DT54539V1
Stop
Start

Start
RW

Note: As the identification page is delivered in read-only mode, the EEPROM consistently behaves as described in
Figure 12.

DS14837 - Rev 1 page 18/37

 M24128-U
Initial delivery state

7 Initial delivery state

The device is delivered with:

• All the memory array bits are set to 1 (each byte contains FFh).
• The identification page is locked and set with the first 16 bytes containing the value of the UID. The content
of the following bytes is FFh.

DS14837 - Rev 1 page 19/37

 M24128-U
Maximum ratings

8 Maximum ratings

Stressing the device outside the ratings listed in Table 6 may permanently damage it. These are stress ratings
only, and operation of the device at these, or any other conditions outside those indicated in the operating
sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Table 6. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

- Ambient operating temperature -40 130 °C

TSTG Storage temperature -65 150 °C

TLEAD Lead temperature during soldering See note (1) °C

IOL DC output current (SDA = 0) - 5 mA

VIO Input or output range -0.50 6.5 V

VCC Supply voltage -0.50 6.5 V

VESD Electrostatic pulse (human body model) (2) - 4000 V

1. Compliant with JEDEC standard J-STD-020 (for small-body, Sn-Pb or Pb free assembly), the ST ECOPACK 7191395
specification, and the European directive on Restrictions on Hazardous Substances (RoHS directive 2011/65/EU of July
2011).
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant
with ANSI/ESDA/JEDEC JS-001, C1 = 100 pF, R1 = 1500 Ω).

DS14837 - Rev 1 page 20/37

 M24128-U
DC and AC parameters

9 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the
device.

Table 7. Operating conditions

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.7 5.5 V

TA Ambient operating temperature -40 85 °C

fC Operating clock frequency - 1 MHz

Table 8. AC measurement conditions

Symbol Parameter Min. Max. Unit

Cbus Load capacitance - 100 pF

- SCL input rise/fall time, SDA input fall time - 50 ns

- Input levels 0.2 VCC to 0.8 VCC V

- Input and output timing reference levels 0.3 VCC to 0.7 VCC V

Figure 13. AC measurement I/O waveform

Input voltage levels Input and output

Timing reference levels
0.8VCC
0.7VCC

DT19774V1
0.3VCC
0.2VCC

Table 9. Input parameters

Symbol Parameter Test condition Min. Max. Unit

CIN (1)
Input capacitance (SDA) - - 8 pF

CIN (1) Input capacitance (other pins) - - 6 pF

ZL (2) VIN < 0.3 VCC 50 -

Input impedance (E2, E1, E0, WC)(3) kΩ
ZH(2) VIN > 0.7 VCC 500 -

1. Specified by design - Not tested in production.

2. Evaluated by characterization - Not tested in production.
3. Input impedance when the memory is selected (after a start condition).

DS14837 - Rev 1 page 21/37

 M24128-U
DC and AC parameters

Table 10. Cycling performance by groups of four bytes

Symbol Parameter Test condition Max. Unit

TA ≤ 25 °C, VCC(min) < VCC < VCC(max) 4 000 000

Ncycle Write cycle endurance(1) Write cycles(2)
TA = 85 °C, VCC(min) < VCC < VCC(max) 1 200 000

1. The write cycle endurance is defined by characterization and qualification. The write cycle endurance is defined for group of
four bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer.
2. A write cycle is executed when a write instruction is decoded. When using the byte write or the page write, refer also to
Section 6.3: Error correction code (ECC) and write cycling.

Table 11. Memory cell data retention

Parameter Test condition Min. Unit

Data retention (1) TA = 55 °C 200 Year

1. The data retention behaviour is checked in production, while the data retention limit is extracted from characterization and
qualification results.

Table 12. DC characteristics (VCC ≥ 1.7 V)

Test conditions (in addition to those in Table 7 and

Symbol Parameter Min. Max. Unit
Table 8)

Input leakage current VIN = VSS or VCC

ILI - ±2 µA
(Ei, SCL, SDA) device in Standby mode
ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA

VCC = 1.7 V, fc= 400 kHz - 0.8

ICC Supply current (Read) mA
fC = 1 MHz - 2.5

During tW,
ICC0(1) Supply current (Write) - 2 mA
VCC ≤ 1.8 V

Device not selected(2),

ICC1 Standby supply current - 1 µA
VIN = VSS or VCC, VCC = 1.7 V

Input low voltage

VIL VCC < 2.5 V -0.45 0.25 VCC V
(SCL, SDA, WC, Ei)(3)
Input high voltage
VCC < 2.5 V 0.75 VCC 6.5 V
(SCL, SDA)
VIH
Input high voltage
VCC < 2.5 V 0.75 VCC VCC + 0.6 V
(WC, Ei)(4)
VOL Output low voltage IOL = 1 mA, VCC = 1.7 V - 0.2 V

1. Evaluated by characterization - Not tested in production.

2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the
internal write cycle tW (tW is triggered by the correct decoding of a write instruction).
3. Ei inputs should be tied to VSS (see Section 2.3: Chip enable (E2, E1, E0))
4. Ei inputs should be tied to VCC (see Section 2.3: Chip enable (E2, E1, E0))

DS14837 - Rev 1 page 22/37

 M24128-U
DC and AC parameters

Table 13. DC characteristics (VCC ≥ 1.8V)

Test conditions (in addition to those in Table 7 and

Symbol Parameter Min. Max. Unit
Table 8)

Input leakage current

ILI VIN = VSS or VCC, device in standby mode - ±2 µA
(Ei, SCL, SDA)
ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA

VCC = 1.8 V, fc = 400 kHz - 0.8

ICC Supply current (Read) mA
fc= 1 MHz - 2.5

During tW,
ICC0(1) Supply current (Write) - 2 mA
1.8 V ≤ VCC ≤ 2.5 V

Device not selected,(2)

ICC1 Standby supply current - 1 µA
VIN = VSS or VCC, VCC = 1.8 V

Input low voltage

VIL 1.8 V ≤ VCC ≤ 2.5 V -0.45 0.25 VCC V
(SCL, SDA, WC, Ei)(3)
Input high voltage
1.8 V ≤ VCC < 2.5 V 0.75 VCC 6.5 V
(SCL, SDA)
VIH
Input high voltage
1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC + 0.6 V
(WC, Ei)(4)
VOL Output low voltage IOL = 1 mA, VCC = 1.8 V - 0.2 V

1. Evaluated by characterization - Not tested in production.

2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the
internal write cycle tW (tW is triggered by the correct decoding of a write instruction).
3. Ei inputs should be tied to VSS (see Section 2.3: Chip enable (E2, E1, E0))
4. Ei inputs should be tied to VCC (see Section 2.3: Chip enable (E2, E1, E0))

DS14837 - Rev 1 page 23/37

 M24128-U
DC and AC parameters

Table 14. DC characteristics (Vcc ≥ 2.5V)

Symbol Parameter Test conditions (in addition to those in Table 7 and Table 8) Min. Max. Unit

Input leakage current

ILI VIN = VSS or VCC, device in standby mode - ±2 µA
(Ei, SCL, SDA)
ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA

fC = 400 kHz, 2.5 V ≤ VCC ≤ 5.5 V - 2

ICC Supply current (Read) mA
fC = 1 MHz, 2.5 V ≤ VCC ≤ 5.5 V - 2.5

During tW,
ICC0(1) Supply current (Write) - 2.5 mA
2.5 V ≤ VCC ≤ 5.5 V

Device not selected(2),

- 2 μA
VIN = VSS or VCC, VCC = 2.5 V
ICC1 Standby supply current
Device not selected(2),
- 3 μA
VIN = VSS or VCC, VCC = 5.5 V

Input low voltage

VIL - -0.45 0.3 VCC V
(SCL, SDA, WC,Ei)(3)
Input high voltage
- 0.7 VCC 6.5
(SCL, SDA)
VIH V
Input high voltage
- 0.7 VCC VCC + 0.6
(WC, Ei)(4)
IOL = 2.1 mA, VCC = 2.5 V or
VOL Output low voltage - 0.4 V
IOL = 3 mA, VCC = 5.5 V

1. Evaluated by characterization - Not tested in production.

2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the
internal write cycle tW (tW is triggered by the correct decoding of a write instruction).
3. Ei inputs should be tied to VSS (see Section 2.3: Chip enable (E2, E1, E0)).
4. Ei inputs should be tied to VCC (see Section 2.3: Chip enable (E2, E1, E0))

DS14837 - Rev 1 page 24/37

 M24128-U
DC and AC parameters

Table 15. AC characteristics (Fast-mode)

Symbol Alt. Parameter Min. Max. Unit

fC fSCL Clock frequency - 400 kHz

tCHCL tHIGH Clock pulse width high 600 - ns

tCLCH tLOW Clock pulse width low 1300 - ns

tQL1QL2 (1) tF SDA (out) fall time 20(2) 300 ns

tXH1XH2(1) tR Input signal rise time (3) (3) ns

tXL1XL2 (1) tF (3) (3)

Input signal fall time ns

tDXCH tSU:DAT Data in set up time 100 - ns

tCLDX tHD:DAT Data in hold time 0 - ns

tCLQX (4) tDH Data out hold time 50 - ns

tCLQV(5) tAA Clock low to next data valid (access time) - 900 ns

tCHDL tSU:STA Start condition setup time 600 - ns

tDLCL tHD:STA Start condition hold time 600 - ns

tCHDH tSU:STO Stop condition set up time 600 - ns

tDHDL tBUF Time between Stop condition and next Start condition 1300 - ns

tWLDL(1)(6) tSU:WC WC set up time (before the start condition) 0 -

μs
tDHWH(1)(7) tHD:WC WC hold time (after the stop condition) 1 -

tW tWR Write time - 5 ms

tNS(1) - Pulse width ignored (input filter on SCL and SDA) - single glitch - 50 ns

1. Evaluated by characterization - Not tested in production.

2. With CL = 10 pF.
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification
that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz.
4. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of
SDA.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming
that Rbus × Cbus time constant is within the values specified in Figure 14.
6. WC = 0 set up time condition to enable the execution of a write command.
7. WC = 0 hold time condition to enable the execution of a write command.

DS14837 - Rev 1 page 25/37

 M24128-U
DC and AC parameters

Table 16. AC characteristics (Fast-mode Plus)

Symbol Alt. Parameter Min. Max. Unit

fC fSCL Clock frequency - 1 MHz

tCHCL tHIGH Clock pulse width high 260 - ns

tCLCH tLOW Clock pulse width low 500 - ns

tXH1XH2(2) tR Input signal rise time (1) (1) ns

tXL1XL2(2) tF Input signal fall time (1) (1) ns

tQL1QL2(2) tF SDA (out) fall time 20(3) 120 ns

tDXCH tSU:DAT Data in setup time 50 - ns

tCLDX tHD:DAT Data in hold time 0 - ns

tCLQX(4) tDH Data out hold time 50 - ns

tCLQV(5) tAA Clock low to next data valid (access time) - 450 ns

tCHDL tSU:STA Start condition setup time 250 - ns

tDLCL tHD:STA Start condition hold time 250 - ns

tCHDH tSU:STO Stop condition setup time 250 - ns

tDHDL tBUF Time between Stop condition and next Start condition 500 - ns

tWLDL (2)(6) tSU:WC WC set up time (before the Start condition) 0 - µs

tDHWH(2)(7) tHD:WC WC hold time (after the Stop condition) 1 - µs

tW tWR Write time - 5 ms

tNS (2)
- Pulse width ignored (input filter on SCL and SDA) - 50 ns

1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification
that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.
2. Evaluated by characterization - Not tested in production.
3. With CL = 10 pF.
4. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of
SDA.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming
that the Rbus × Cbus time constant is within the values specified in Figure 15.
6. WC = 0 set up time condition to enable the execution of a write command.
7. WC = 0 hold time condition to enable the execution of a write command.

DS14837 - Rev 1 page 26/37

 M24128-U
DC and AC parameters

Figure 14. Rbus value versus bus parasitic capacitance (Cbus) for an I2Cbus (fC = 400 kHz)

100 VCC
The Rbus x Cbus time
constant must be below
Bus line Pull up resistor (kΩ)

the 400 ns time constant

line displayed on the left Rbus

Rb
10 us
xC I²C bus SCL
bu
M24xxx
s =4 controller
Here Rbus x Cbus = 120 ns
00 SDA
4
ns
Cbus

DT37916V5
10 30 100 1000

Bus line capacitor (pF)

Figure 15. Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus (fC = 1 MHz)

100
VCC
The Rbus x Cbus time
Bus line pull-up resistor (kΩ)

constant must be below

the 150 ns time Rbus
constant line displayed
Rbu
10 s xC
bus on the left
= 15
0 ns I²C bus SCL
M24xxx
controller
4
Here Rbus x Cbus = 120 ns SDA

Cbus

DT19745V8
1
10 30 100

Bus line capacitor (pF)

DS14837 - Rev 1 page 27/37

 M24128-U
DC and AC parameters

Figure 16. AC waveforms

Start Stop Start

condition condition condition

tXL1XL2 tCHCL
tXH1XH2 tCLCH

SCL
tDLCL

tXL1XL2

SDA In

SDA
tCHDL tXH1XH2 Input tCLDX SDA tDXCH tCHDH tDHDL
Change
WC

tWLDL tDHWH

Stop
Start
condition
condition

SCL

SDA In
tW
tCHDH tCHDL
Write cycle

tCHCL

SCL
tCLQV tCLQX tQL1QL2

DT00795iV1
SDA Out Data valid Data valid

DS14837 - Rev 1 page 28/37

 M24128-U
Package information

10 Package information

To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product
status are available at: www.st.com. ECOPACK is an ST trademark.

10.1 SO8N package information

This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mil body width package.

Figure 17. SO8N - Outline

h x 45˚

A2 A
c
b ccc
e

0.25 mm
D SEATING GAUGE PLANE
PLANE
C k
8

O7_SO8_ME_V2
E1 E
1 L
A1
L1

1. Drawing is not to scale.

DS14837 - Rev 1 page 29/37

 M24128-U
Package information

Table 17. SO8N - Mechanical data

millimeters inches (1)

Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 1.750 - - 0.0689
A1 0.100 - 0.250 0.0039 - 0.0098
A2 1.250 - - 0.0492 - -
b 0.280 - 0.480 0.0110 - 0.0189
c 0.170 - 0.230 0.0067 - 0.0091

D(2) 4.800 4.900 5.000 0.1890 0.1929 0.1969

E 5.800 6.000 6.200 0.2283 0.2362 0.2441

E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575

e - 1.270 - - 0.0500 -
h 0.250 - 0.500 0.0098 - 0.0197
k 0° - 8° 0° - 8°
L 0.400 - 1.270 0.0157 - 0.0500
L1 - 1.040 - - 0.0409 -
ccc - - 0.100 - - 0.0039

1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 mm per side
3. Dimension E1 does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per
side.

Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the
outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interleads flash, but
including any mismatch between the top and bottom of the plastic body. The measurement side for mold flash,
protusions, or gate burrs is the bottom side.

Figure 18. SO8N - Footprint example

0.6 (x8)
3.9
6.7

O7_SO8N_FP_V2

1.27

1. Dimensions are expressed in millimeters.

DS14837 - Rev 1 page 30/37

 M24128-U
Ordering information

11 Ordering information

Table 18. Ordering information scheme

Example: M24 128 -U F MN 6 T P /K

Device type
M24 = I²C serial access EEPROM
Device function
128 = 128-Kbit (16K x 8 bit)
Device family
U = With UID
Operating voltage
F = VCC = 1.7 V to 5.5 V

Package(1)
MN = SO8N (150 mil width)
Device grade
6 = Industrial: device tested with standard test flow over -40 to 85 °C

Option
T = Tape and reel packing
Blank = tube packing
Plating technology
P or G = RoHS compliant and halogen-free (ECOPACK2)

Process(2)
/K = Manufacturing technology code

1. All packages are ECOPACK2 (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants).
2. The process letter appears on the device package (marking) and on the shipment box. Contact your nearest ST Sales
Office for further information.

Note: For a list of available options (memory, package, and so on) or for further information on any aspect of this
device, contact your nearest ST sales office.
Note: Parts marked as “ES” or “E” are not yet qualified and therefore not approved for use in production. ST is not
responsible for any consequences resulting from such use. In no event will ST be liable for the customer using
any of these engineering samples in production. ST’s Quality department must be contacted prior to any
decision to use these engineering samples to run a qualification activity.

DS14837 - Rev 1 page 31/37

 M24128-U

Revision history
Table 19. Document revision history

Date Revision Changes

21-Feb-2025 1 Initial release.

DS14837 - Rev 1 page 32/37

 M24128-U
Contents

Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Chip enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Write control (WC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.6.1 Operating supply voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.1 Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Unique identifier (UID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
5.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.3 Data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.5 Device addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6.1 Write operations on memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1.2 Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 Write operations on the identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.3 Error correction code (ECC) and write cycling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.4 Minimizing write delays by polling on ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5 Read operations on the memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.5.1 Random address read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.5.2 Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.5.3 Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.6 Read operations on identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DS14837 - Rev 1 page 33/37

 M24128-U
Contents

6.7 Read lock status on identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
10.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

DS14837 - Rev 1 page 34/37

 M24128-U
List of tables

List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. UID address in the identification page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. First byte address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Second byte address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Input parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. DC characteristics (VCC ≥ 1.7 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. DC characteristics (VCC ≥ 1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. DC characteristics (Vcc ≥ 2.5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. AC characteristics (Fast-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16. AC characteristics (Fast-mode Plus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 17. SO8N - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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 M24128-U
List of figures

List of figures
Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. Chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. I²C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Write mode sequences with WC = 1 (data write inhibited). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Random read on identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Read lock status (identification page unlocked) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Read lock status (identification page locked) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Rbus value versus bus parasitic capacitance (Cbus) for an I2Cbus (fC = 400 kHz) . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus (fC = 1 MHz). . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. SO8N - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18. SO8N - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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 M24128-U

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DS14837 - Rev 1 page 37/37