24C08B/16B

8K/16K 5.0V I2C™ Serial EEPROMs

FEATURES PACKAGE TYPES
• Single supply with operation from 4.5-5.5V PDIP
• Low power CMOS technology A0 1 8 VCC

24C08B/16B
- 1 mA active current typical
A1 2 7 WP
- 10 µA standby current typical at 5.5V
• Organized as 4 or 8 blocks of 256 bytes
(4 x 256 x 8) or (8 x 256 x 8) A2 3 6 SCL
• 2-wire serial interface bus, I2C compatible
• Schmitt trigger, filtered inputs for noise suppres- VSS 4 5 SDA
sion
• Output slope control to eliminate ground bounce
• 100 kHz compatibility
• Self-timed write cycle (including auto-erase) 8-lead
• Page-write buffer for up to 16 bytes SOIC 1 8
A0 VCC
• 2 ms typical write cycle time for page-write

24C08B/16B
• Hardware write protect for entire memory A1 2 7 WP
• Can be operated as a serial ROM
• ESD protection > 4,000V 3 6
A2 SCL
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years 4 5
VSS SDA
• 8-pin DIP, 8-lead or 14-lead SOIC packages
• Available for extended temperature range
- Commercial (C): 0°C to +70°C 14-lead
1 14 NC
- Industrial (I): -40°C to +85°C SOIC NC
- Automotive (E): -40˚C to +125˚C A0 2 13 VCC
24C08B/16B
3 12
DESCRIPTION A1 WP

NC 4 11 NC
The Microchip Technology Inc. 24C08B/16B is an 8K or
16K bit Electrically Erasable PROM intended for use in A2 5 10 SCL
extended/automotive temperature ranges. The device 6 9
VSS SDA
is organized as four or eight blocks of 256 x 8-bit mem-
ory with a 2-wire serial interface. The 24C08B/16B also NC 7 8 NC
has a page-write capability for up to 16 bytes of data.
The 24C08B/16B is available in the standard 8-pin DIP
and both 8-lead and 14-lead surface mount SOIC pack- BLOCK DIAGRAM
ages. WP

HV GENERATOR

I/O MEMORY EEPROM

CONTROL CONTROL ARRAY
LOGIC LOGIC XDEC
PAGE LATCHES

SDA SCL
YDEC

VCC SENSE AMP

VSS R/W CONTROL

I2C is a trademark of Philips Corporation.

 1999 Microchip Technology Inc. DS21081F-page 1

24C08B/16B
1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PIN FUNCTION TABLE

1.1 Maximum Ratings* Name Function

VCC...................................................................................7.0V VSS Ground
All inputs and outputs w.r.t. VSS ................-0.6V to VCC +1.0V
Storage temperature ..................................... -65˚C to +150˚C SDA Serial Address/Data I/O
Ambient temp. with power applied................. -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
SCL Serial Clock
ESD protection on all pins ..................................................≥ 4 kV WP Write Protect Input
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat- VCC +4.5V to 5.5V Power Supply
ing only and functional operation of the device at those or any
A0, A1, A2 No Internal Connection
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

VCC = +4.5V to +5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial (I): Tamb = -40°C to +85°C
Automotive (E): Tamb = -40˚C to +125˚C
Parameter Symbol Min Max Units Conditions
WP, SCL and SDA pins:
High level input voltage VIH .7 Vcc — V
Low Level input voltage VIL — .3 VCC V
Hysteresis of Schmitt trigger VHYS .05 Vcc — V (Note)
inputs
Low level output voltage VOL — .40 V IOL = 3.0 mA, VCC=4.5V
Input leakage current ILI -10 10 µA VIN =.1V to VCC
Output leakage current ILO -10 10 µA VOUT = .1V to VCC
Pin capacitance CIN, COUT — 10 pF VCC = 5.0V (Note 1)
(all inputs/outputs) Tamb = 25˚C, FCLK=1 MHz
Operating current ICC write — 3 mA VCC = 5.5V, SCL = 400 kHz
ICC read — 1 mA
Standby current ICCS — 100 µA VCC = 5.5V, SDA = SCL = VCC
WP = VSS
Note: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1: BUS TIMING START/STOP

VHYS

SCL
THD:STA
TSU:STA TSU:STO

SDA

START STOP

DS21081F-page 2  1999 Microchip Technology Inc.

 24C08B/16B

TABLE 1-3: AC CHARACTERISTICS

Parameter Symbol Min Max Units Remarks

Clock frequency FCLK — 100 kHz
Clock high time THIGH 4000 — ns
Clock low time TLOW 4700 — ns
SDA and SCL rise time TR — 1000 ns (Note1)
SDA and SCL fall time TF — 300 ns (Note 1)
START condition hold time THD:STA 4000 — ns After this period the first clock
pulse is generated
START condition setup TSU:STA 4700 — ns Only relevant for repeated
time START condition
Data input hold time THD:DAT 0 — ns
Data input setup time TSU:DAT 250 — ns
STOP condition setup time TSU:STO 4000 — ns
Output valid from clock TAA — 3500 ns (Note 2)
Bus free time TBUF 4700 — ns Time the bus must be free before
a new transmission can start
Output fall time from VIH TOF — 250 ns (Note 1), CB ≤ 100 pF
min to VIL max
Input filter spike suppres- TSP — 50 ns (Note 3)
sion (SDA and SCL pins)
Write cycle time TWR — 10 ms Byte or Page mode
Endurance — 1M — cycles 25°C, VCC = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2: BUS TIMING DATA
TF TR
THIGH
TLOW

SCL
TSU:STA
THD:DAT TSU:DAT TSU:STO
THD:STA
SDA
IN TSP

TAA TAA TBUF

THD:STA

SDA
OUT

 1999 Microchip Technology Inc. DS21081F-page 3

24C08B/16B
2.0 FUNCTIONAL DESCRIPTION 3.4 Data Valid (D)
The 24C08B/16B supports a Bi-directional 2-wire bus The state of the data line represents valid data when,
and data transmission protocol. A device that sends after a START condition, the data line is stable for the
data onto the bus is defined as transmitter, and a duration of the HIGH period of the clock signal.
device receiving data as receiver. The bus has to be
The data on the line must be changed during the LOW
controlled by a master device which generates the
period of the clock signal. There is one clock pulse per
serial clock (SCL), controls the bus access, and gener-
bit of data.
ates the START and STOP conditions, while the
24C08B/16B works as slave. Both, master and slave Each data transfer is initiated with a START condition
can operate as transmitter or receiver but the master and terminated with a STOP condition. The number of
device determines which mode is activated. the data bytes transferred between the START and
STOP conditions is determined by the master device
3.0 BUS CHARACTERISTICS and is theoretically unlimited, although only the last 16
The following bus protocol has been defined: will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
• Data transfer may be initiated only when the bus
out fashion.
is not busy.
• During data transfer, the data line must remain 3.5 Acknowledge
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be Each receiving device, when addressed, is obliged to
interpreted as a START or STOP condition. generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
Accordingly, the following bus conditions have been
pulse which is associated with this acknowledge bit.
defined (Figure 3-1).
Note: The 24C08B/16B does not generate any
3.1 Bus not Busy (A) acknowledge bits if an internal program-
ming cycle is in progress.
Both data and clock lines remain HIGH.
The device that acknowledges, has to pull down the
3.2 Start Data Transfer (B) SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
A HIGH to LOW transition of the SDA line while the period of the acknowledge related clock pulse. Of
clock (SCL) is HIGH determines a START condition. course, setup and hold times must be taken into
All commands must be preceded by a START condi- account. During reads, a master must signal an end of
tion. data to the slave by NOT generating an acknowledge
bit on the last byte that has been clocked out of the
3.3 Stop Data Transfer (C)
slave. In this case, the slave (24C08B/16B) will leave
A LOW to HIGH transition of the SDA line while the the data line HIGH to enable the master to generate the
clock (SCL) is HIGH determines a STOP condition. All STOP condition.
operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

SCL

SDA

START ADDRESS OR DATA STOP

CONDITION ACKNOWLEDGE ALLOWED CONDITION
VALID TO CHANGE

DS21081F-page 4  1999 Microchip Technology Inc.

 24C08B/16B
3.6 Device Addressing 4.0 WRITE OPERATION
A control byte is the first byte received following the 4.1 Byte Write
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24C08B/16B Following the start condition from the master, the
this is set as 1010 binary for read and write operations. device code (4 bits), the block address (3 bits), and the
The next three bits of the control byte are the block R/W bit which is a logic low is placed onto the bus by
select bits (B2, B1, B0). They are used by the master the master transmitter. This indicates to the addressed
device to select which of the eight 256 word blocks of slave receiver that a byte with a word address will follow
memory are to be accessed. These bits are in effect the after it has generated an acknowledge bit during the
three most significant bits of the word address. ninth clock cycle. Therefore the next byte transmitted by
The last bit of the control byte defines the operation to the master is the word address and will be written into
be performed. When set to one a read operation is the address pointer of the 24C08B/16B. After receiving
selected, when set to zero a write operation is selected. another acknowledge signal from the 24C08B/16B the
Following the start condition, the 24C08B/16B monitors master device will transmit the data word to be written
the SDA bus checking the device type identifier being into the addressed memory location. The 24C08B/16B
transmitted, upon a 1010 code the slave device outputs acknowledges again and the master generates a stop
an acknowledge signal on the SDA line. Depending on condition. This initiates the internal write cycle, and dur-
the state of the R/W bit, the 24C08B/16B will select a ing this time the 24C08B/16B will not generate
read or write operation. acknowledge signals (Figure 4-1).

Control 4.2 Page Write

Operation Block Select R/W
Code
The write control byte, word address and the first data
Read 1010 Block Address 1 byte are transmitted to the 24C08B/16B in the same
Write 1010 Block Address 0 way as in a byte write. But instead of generating a stop
condition the master transmits up to 16 data bytes to
FIGURE 3-2: CONTROL BYTE the 24C08B/16B which are temporarily stored in the
ALLOCATION on-chip page buffer and will be written into the memory
START READ/WRITE after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
SLAVE ADDRESS R/W A higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
1 0 1 0 B2 B1 B0 operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).

Note: Page write operations are limited to writing

bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or Ôpage sizeÕ) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.

 1999 Microchip Technology Inc. DS21081F-page 5

24C08B/16B
FIGURE 4-1: BYTE WRITE
S S
BUS ACTIVITY T CONTROL WORD T
MASTER A BYTE ADDRESS DATA O
R P
T

SDA LINE S P

A A A
BUS ACTIVITY C C C
K K K

FIGURE 4-2: PAGE WRITE

S S
BUS ACTIVITY T T
MASTER A CONTROL WORD
BYTE ADDRESS (n) DATA n DATA n + 1 DATA n + 15 O
R P
T
SDA LINE S P
A A A A A
BUS ACTIVITY C C C C C
K K K K K

DS21081F-page 6  1999 Microchip Technology Inc.

 24C08B/16B
5.0 ACKNOWLEDGE POLLING 7.0 READ OPERATION
Since the device will not acknowledge during a write Read operations are initiated in the same way as write
cycle, this can be used to determine when the cycle is operations with the exception that the R/W bit of the
complete (this feature can be used to maximize bus slave address is set to one. There are three basic types
throughput). Once the stop condition for a write com- of read operations: current address read, random
mand has been issued from the master, the device ini- read, and sequential read.
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send- 7.1 Current Address Read
ing a start condition followed by the control byte for a
The 24C08B/16B contains an address counter that
write command (R/W = 0). If the device is still busy with
maintains the address of the last word accessed, inter-
the write cycle, then no ACK will be returned. If the
nally incremented by one. Therefore, if the previous
cycle is complete, then the device will return the ACK
access (either a read or write operation) was to
and the master can then proceed with the next read or
address n, the next current address read operation
write command. See Figure 5-1 for flow diagram.
would access data from address n + 1. Upon receipt of
FIGURE 5-1: ACKNOWLEDGE POLLING the slave address with R/W bit set to one, the
FLOW 24C08B/16B issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
Send transfer but does generate a stop condition and the
Write Command 24C08B/16B discontinues transmission (Figure 7-1).

7.2 Random Read

Send Stop Random read operations allow the master to access
Condition to any memory location in a random manner. To perform
Initiate Write Cycle this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C08B/16B as part of a write operation. After the word
Send Start address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
Send Control Byte with the R/W bit set to a one. The 24C08B/16B will then
with R/W = 0 issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24C08B/16B
discontinues transmission (Figure 7-2).
Did Device NO
Acknowledge 7.3 Sequential Read
(ACK = 0)?
Sequential reads are initiated in the same way as a ran-
YES dom read except that after the 24C08B/16B transmits
the first data byte, the master issues an acknowledge
Next
Operation as opposed to a stop condition in a random read. This
directs the 24C08B/16B to transmit the next sequen-
tially addressed 8 bit word (Figure 7-3).

6.0 WRITE PROTECTION To provide sequential reads the 24C08B/16B contains

an internal address pointer which is incremented by
The 24C08B/16B can be used as a serial ROM when one at the completion of each operation. This address
the WP pin is connected to VCC. Programming will be pointer allows the entire memory contents to be serially
inhibited and the entire memory will be write-protected. read during one operation.

7.4 Noise Protection

The 24C08B/16B employs a VCC threshold detector cir-
cuit which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

 1999 Microchip Technology Inc. DS21081F-page 7

24C08B/16B
FIGURE 7-1: CURRENT ADDRESS READ
S
T CONTROL S
BUS ACTIVITY A T
MASTER BYTE DATA n
R O
T P

SDA LINE S P

A N
BUS ACTIVITY C O
K
A
C
K

FIGURE 7-2: RANDOM READ

S S
T T S
BUS ACTIVITY A CONTROL WORD A CONTROL T
MASTER R BYTE ADDRESS (n) R BYTE DATA (n) O
T T P
S S P
SDA LINE
A A A N
C C C O
K K K
BUS ACTIVITY A
C
K

FIGURE 7-3: SEQUENTIAL READ

S
T
O
BUS ACTIVITY CONTROL P
MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X

SDA LINE P
A A A A N
BUS ACTIVITY C C C C O
K K K K
A
C
K

8.0 PIN DESCRIPTIONS 8.3 WP

8.1 SDA Serial Address/Data Input/Output This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
This is a Bi-directional pin used to transfer addresses (read/write the entire memory 000-7FF).
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up If tied to VCC, WRITE operations are inhibited. The
resistor to VCC (typical 10 kΩ). entire memory will be write-protected. Read opera-
tions are not affected.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are This feature allows the user to use the 24C08B/16B as
reserved for indicating the START and STOP condi- a serial ROM when WP is enabled (tied to VCC).
tions.
8.4 A0, A1, A2
8.2 SCL Serial Clock
These pins are not used by the 24C08B/16B. They
This input is used to synchronize the data transfer from may be left floating or tied to either VSS or VCC.
and to the device.

DS21081F-page 8  1999 Microchip Technology Inc.

 24C08B/16B
NOTES:

 1999 Microchip Technology Inc. DS21081F-page 9

24C08B/16B
NOTES:

DS21081F-page 10  1999 Microchip Technology Inc.

 24C08B/16B
24C08B/16B Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

24C08B/16B – E /P
P = Plastic DIP (300 mil Body), 8-lead
Package: SL = Plastic SOIC (150 mil Body), 14-lead
SN = Plastic SOIC (150 mil Body), 8-lead
Temperature Blank = 0°C to +70°C
Range: I = -40°C to +85°C
E = -40°C to +125°C

24C08B 8K I2C Serial EEPROM

Device: 24C08BT 8K I2C Serial EEPROM (Tape and Reel)
24C16B 16K I2C Serial EEPROM
24C16BT 16K I2C Serial EEPROM (Tape and Reel)

Sales and Support

Data Sheets
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mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
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Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

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 1999 Microchip Technology Inc. DS21081F-page 11

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 1999 Microchip Technology Inc.