1996 Microchip Technology Inc.
DS21051E-page 1
FEATURES
Single supply with operation down to 2.5V
Low power CMOS technology
- 1 mA active current typical
- 10
A standby current typical at 5.5V
- 5
A standby current typical at 3.0V
Organized as two or four blocks of 256 bytes
(2 x 256 x 8) and (4 x 256 x 8)
2-wire serial interface bus, I
2
C
compatible
Schmitt trigger, ltered inputs for noise suppres-
sion
Output slope control to eliminate ground bounce
100 kHz (2.5V) and 400 kHz (5V) compatibility
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 16 bytes
2 ms typical write cycle time for page-write
Hardware write protect for entire memory
Can be operated as a serial ROM
Factory programming (QTP) available
ESD protection > 4,000V
1,000,000 erase/write cycles guaranteed
Data retention > 200 years
8-pin DIP, 8-lead or 14-lead SOIC packages
Available for extended temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24LC04B/08B is a 4K or
8K bit Electrically Erasable PROM. The device is orga-
nized as two or four blocks of 256 x 8-bit memory with
a 2-wire serial interface. Low voltage design permits
operation down to 2.5 volts with typical standby and
active currents of only 5
A and 1 mA respectively. The
24LC04B/08B also has a page-write capability for up to
16 bytes of data. The 24LC04B/08B is available in the
standard 8-pin DIP and both 8-lead and 14-lead surface
mount SOIC packages.
- Commercial (C): 0
C to +70
C
- Industrial (I): -40
C to +85
C
PACKAGE TYPES
BLOCK DIAGRAM
NC
SS
CC A0
A1
NC
A2
NC
V
1
2
3
4
5
6
7
14
13
12
NC
SCL
SDA
NC
9
8
11
10
WP
V
NC
14-lead
SOIC
2
4
L
C
0
4
B
/
0
8
B
2
4
L
C
0
4
B
/
0
8
B
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
2
4
L
C
0
4
B
/
0
8
B
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
PDIP
8-lead
SOIC
HV GENERATOR
EEPROM ARRAY
(2 x 256 x 8) or
(4 X 256 X 8)
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
WP
SDA SCL
VCC
VSS
24LC04B/08B
4K/8K 2.5V I
2
C
Serial EEPROMs
I
2
C is a trademark of Philips Corporation.
This document was created with FrameMaker 4 0 4
24LC04B/08B
DS21051E-page 2
1996 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
.............. -0.3V to V
CC
+ 1.0V
Storage temperature ..................................... -65C to +150C
Ambient temp. with power applied ................ -65C to +125C
Soldering temperature of leads (10 seconds) ............. +300C
ESD protection on all pins
..................................................
4 kV
*Notice:
Stresses above those listed under Maximum ratings
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specication is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1: PIN FUNCTION TABLE
Name Function
V
SS
Ground
SDA Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
V
CC
+2.5V to 5.5V Power Supply
A0, A1, A2
No Internal Connection
TABLE 1-2: DC CHARACTERISTICS
FIGURE 1-1: BUS TIMING START/STOP
V
CC
= +2.5V to +5.5V
Commercial (C): Tamb = 0C to +70C
Industrial (I): Tamb = -40C to +85C
Parameter Symbol Min Max Units
WP, SCL and SDA pins:
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger
Inputs
Low level output voltage
V
IH
V
IL
V
HYS
V
OL
.7 V
CC
.05 V
CC
.3 V
CC
.40
V
V
V
V
(Note)
I
OL
= 3.0mA, V
CC
= 2.5V
Input leakage current I
LI
-10 10
A V
IN
= .1V to V
CC
Output leakage current I
LO
-10 10
A V
OUT
= .1V to V
CC
Pin capacitance
(all inputs/outputs)
C
IN
, C
OUT
10 pF V
CC
= 5.0V (Note)
Tamb = 25C, Fclk = 1 MHz
Operating current I
CC
W
RITE
I
CC
R
EAD
3
1
mA
mA
V
CC
= 5.5V, SCL = 400 kHz
Standby current I
CCS
30
100
A
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
Note: This parameter is periodically sampled and not 100% tested.
TSU:STA
THD:STA
VHYS
TSU:STO
START STOP
SCL
SDA
1996 Microchip Technology Inc. DS21051E-page 3
24LC04B/08B
TABLE 1-3: AC CHARACTERISTICS
FIGURE 1-2: BUS TIMING DATA
Parameter Symbol
STANDARD
MODE
V
CC
= 4.5 - 5.5V
FAST MODE
Units Remarks
Min Max Min Max
Clock frequency F
CLK
100 400 kHz
Clock high time T
HIGH
4000 600 ns
Clock low time T
LOW
4700 1300 ns
SDA and SCL rise time T
R
1000 300 ns (Note 1)
SDA and SCL fall time T
F
300 300 ns (Note 1)
START condition hold time T
HD
:
STA
4000 600 ns After this period the rst clock
pulse is generated
START condition setup time T
SU
:
STA
4700 600 ns Only relevant for repeated
START condition
Data input hold time T
HD
:
DAT
0 0 ns
Data input setup time T
SU
:
DAT
250 100 ns
STOP condition setup time T
SU
:
STO
4000 600 ns
Output valid from clock T
AA
3500 900 ns (Note 2)
Bus free time T
BUF
4700 1300 ns Time the bus must be free
before a new transmission can
start
Output fall time from V
IH
min
to V
IL
max
T
OF
250 20 +0.1
C
B
250 ns (Note 1), C
B
100 pF
Input lter spike suppression
(SDA and SCL pins)
T
SP
50 50 ns (Note 3)
Write cycle time T
WR
10 10 ms Byte or Page mode
Endurance 24LC04B
24LC08B
10M
1M
10M
1M
cycles 25
C, Vcc = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undened region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specication for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specic appli-
cation, please consult the Total Endurance Model whcih can be obtained on our BBS or website.
TSU:STA
TF
TLOW
THIGH
TR
THD:DAT TSU:DAT TSU:STO
THD:STA
TBUF TAA
TAA
TSP
THD:STA
SCL
SDA
IN
SDA
OUT
24LC04B/08B
DS21051E-page 4 1996 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LC04B/08B supports a Bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is dened as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LC04B/08B
works as slave. Both, master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been dened:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
dened (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a rst in rst
out fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Note: The 24LC04B/08B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D) (A) (C)
SCL
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SDA
1996 Microchip Technology Inc. DS21051E-page 5
24LC04B/08B
3.6 Device Addressing
A control byte is the rst byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24LC04B/08B
this is set as 1010 binary for read and write operations.
The next three bits of the control byte are the block
select bits (B2, B1, B0). B2 is a don't care for both the
24LC04B and 24LC08B; B1 is a don't care for the
24LC04B. They are used by the master device to select
which of the two or four 256 word blocks of memory are
to be accessed. These bits are in effect the most sig-
nicant bits of the word address.
The last bit of the control byte denes the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC04B/08B moni-
tors the SDA bus checking the device type identier
being transmitted, upon a 1010 code the slave device
outputs an acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the 24LC04B/
08B will select a read or write operation.
FIGURE 3-2: CONTROL BYTE
ALLOCATION
Operation
Control
Code
Block Select R/W
Read 1010 Block Address 1
Write 1010 Block Address 0
SLAVE ADDRESS
X = Dont care. B1 is dont care for 24LC04B.
1 0 1 0 X B1 B0
R/W A
START READ/WRITE
4.0 WRITE OPERATION
4.1 Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24LC04B/08B. After
receiving another acknowledge signal from the
24LC04B/08B the master device will transmit the data
word to be written into the addressed memory location.
The 24LC04B/08B acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24LC04B/08B will
not generate acknowledge signals (Figure 4-1).
4.2 Page Write
The write control byte, word address and the rst data
byte are transmitted to the 24LC04B/08B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to 16 data bytes to
the 24LC04B/08B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: PAGE WRITE
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS
DATA
A
C
K
A
C
K
A
C
K
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n DATA n + 15
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DATA n + 1
This document was created with FrameMaker 4 0 4
24LC04B/08B
DS21051E-page 6 1996 Microchip Technology Inc.
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for ow diagram.
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
6.0 WRITE PROTECTION
The 24LC04B/08B can be used as a serial ROM when
the WP pin is connected to VCC. Programming will be
inhibited and the entire memory will be write-protected.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
7.1 Current Address Read
The 24LC04B/08B contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24LC04B/
08B issues an acknowledge and transmits the 8-bit
data word. The master will not acknowledge the trans-
fer but does generate a stop condition and the
24LC04B/08B discontinues transmission (Figure 7-1).
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, rst the word address must
be set. This is done by sending the word address to the
24LC04B/08B as part of a write operation. After the
word address is sent, the master generates a start con-
dition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W bit set to a one. The 24LC04B/
08B will then issue an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24LC04B/08B discontinues transmission (Figure 7-2).
7.3 Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC04B/08B transmits
the rst data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24LC04B/08B to transmit the next sequen-
tially addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC04B/08B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
7.4 Noise Protection
The 24LC04B/08B employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and lter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
1996 Microchip Technology Inc. DS21051E-page 7
24LC04B/08B
FIGURE 7-1: CURRENT ADDRESS READ
FIGURE 7-2: RANDOM READ
FIGURE 7-3: SEQUENTIAL READ
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
DATA n
A
C
K
N
O
A
C
K
S P S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
A
C
K
WORD
ADDRESS (n)
CONTROL
BYTE
S
T
A
R
T
DATA (n)
A
C
K
A
C
K
N
O
A
C
K
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA n DATA n + 1 DATA n + 2 DATA n + X
A
C
K
A
C
K
A
C
K
8.0 PIN DESCRIPTIONS
8.1 SDA Serial Address/Data Input/Output
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 10K for 100 kHz, 1K for 400
kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
8.2 SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3 WP
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC04B/08B as
a serial ROM when WP is enabled (tied to VCC).
8.4 A0, A1, A2
These pins are not used by the 24LC04B/08B. They
may be left oating or tied to either VSS or VCC.
24LC04B/08B
DS21051E-page 8 1996 Microchip Technology Inc.
NOTES:
1996 Microchip Technology Inc. DS21051E-page 9
24LC04B/08B
NOTES:
24LC04B/08B
DS21051E-page 10 1996 Microchip Technology Inc.
NOTES:
24LC04B/08B
1996 Microchip Technology Inc. DS21051E-page 11
24LC04B/08B Product Identication System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales ofces.
Package: P = Plastic DIP (300 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (207 mil Body), 8-lead
Temperature Blank = 0C to +70C
Range: I = -40C to +85C
Device: 24LC04B 4K I
2
C Serial EEPROM
24LC04BT 4K1
2
C Serial EEPROM (Tape and Reel)
24LC08B 8K1
2
C Serial EEPROM
24LC04BT 8K 1
2
C Serial EEPROM (Tape and Reel)
24LC04B/08B /P
DS21051E-page 12 1996 Microchip Technology Inc.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchips products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
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All rights reserved. 1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
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