M 24LC01B/02B MODULES

1K/2K I2C™ Serial EEPROMs in ISO Micromodules

FEATURES ISO MODULE LAYOUT
• ISO 7816 Compliant pad locations
• Low power CMOS technology
- 1 mA active current typical VDD VSS
- 10 µA standby current typical at 5.5V
• Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8)
• 2-wire serial interface bus, I2C™ compatible
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase) SCL SDA
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write
• ESD protection > 4 kV
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• Temperature ranges available:
- Commercial (C): 0°C to +70°C BLOCK DIAGRAM

DESCRIPTION HV GENERATOR

The Microchip Technology Inc. 24LC01B and 24LC02B

are 1K-bit and 2K-bit Electrically Erasable PROMs in I/O MEMORY EEPROM
CONTROL CONTROL ARRAY
ISO modules for smart card applications. The devices LOGIC LOGIC XDEC
are organized as a single block of 128 x 8-bit or 256 x PAGE LATCHES
8-bit memory with a two-wire serial interface. The
24LC01B and 24LC02B also have page-write capabil- SDA SCL
ity for up to 8 bytes of data. YDEC

VCC SENSE AMP

VSS R/W CONTROL

 1997 Microchip Technology Inc. DS21222A-page 1

24LC01B/02B Modules
1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PAD FUNCTION TABLE
Name Function
1.1 Maximum Ratings*
VSS Ground
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ................-0.6V to VCC +1.0V SDA Serial Address/Data I/O
Storage temperature ..................................... -65˚C to +150˚C SCL Serial Clock
Ambient temp. with power applied................. -65˚C to +125˚C
VCC +2.5V to 5.5V Power Supply
ESD protection on all pads............................................. ≥4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
1.2 Pad Descriptions
ing only and functional operation of the device at those or any
1.2.1 SDA (Serial Data)
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
This is a bi-directional pad used to transfer addresses
conditions for extended periods may affect device reliability.
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 KΩ for 100 kHz, 2 KΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.

1.2.2 SCL (Serial Clock)

This input is used to synchronize the data transfer from

and to the device.

TABLE 1-1 DC CHARACTERISTICS

All Parameters apply across the recom- Commercial (C): Tamb = 0˚C to +70˚C, VCC = 2.5V to 5.5V
mended operating ranges unless other-
wise noted.
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pins:
High level input voltage VIH 0.7 VCC V (Note)
Low level input voltage VIL 0.3 VCC V (Note)
Hysteresis of Schmitt trigger inputs VHYS 0.05 VCC — V Vcc ≥ 2.5V (Note)
Low level output voltage VOL 0.40 V IOL = 3.0 mA, VCC = 4.5V
IOL = 2.1 mA, VCC = 2.5V
Input leakage current ILI -10 10 µA VIN = VCC or VSS
Output leakage current ILO -10 10 µA VOUT = VCC or VSS
Pin capacitance (all inputs/outputs) CIN, — 10 pF VCC = 5.0V (Note)
COUT Tamb = 25˚C, f = 1 MHz
Operating current ICC Write — 3 mA VCC = 5.5V, SCL = 400 kHz
ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS — 100 µA VCC = 5.5V, SDA = SCL = VCC
Note: This parameter is periodically sampled and not 100% tested.

DS21222A-page 2  1997 Microchip Technology Inc.

 24LC01B/02B Modules
TABLE 1-2 AC CHARACTERISTICS

All parameters apply across the specified operat- Vcc = 2.5V to 5.5V
ing ranges unless otherwise noted. Commercial (C): Tamb = 0 °C to +70°C
Vcc = 2.5V - 5.5V Vcc = 4.5V - 5.5V
Parameter Symbol STD MODE FAST MODE Units Remarks
Min. Max. Min. Max.
Clock frequency FCLK — 100 — 400 kHz
Clock high time THIGH 4000 — 600 — ns
Clock low time TLOW 4700 — 1300 — ns
SDA and SCL rise time TR — 1000 — 300 ns (Note 1)
SDA and SCL fall time TF — 300 — 300 ns (Note 1)
START condition hold time THD:STA 4000 — 600 — ns After this period the first
clock pulse is generated
START condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated
START condition
Data input hold time THD:DAT 0 — 0 — ns (Note 2)
Data input setup time TSU:DAT 250 — 100 — ns
STOP condition setup time TSU:STO 4000 — 600 — ns
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH TOF — 250 20 +0.1 250 ns (Note 1), CB ≤ 100 pF
minimum to VIL maximum CB
Input filter spike suppression TSP — 50 — 50 ns (Notes 1, 3)
(SDA and SCL pins)
Write cycle time TWC — 10 — 10 ms Byte or Page mode
Endurance 1M — 1M — cycles 25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-1: BUS TIMING DATA

THIGH
TF TR

SCL
TSU:STA
TLOW THD:DAT TSU:DAT TSU:STO
SDA
THD:STA
IN TSP

TBUF
TAA

SDA
OUT

 1997 Microchip Technology Inc. DS21222A-page 3

24LC01B/02B Modules
2.0 FUNCTIONAL DESCRIPTION 3.4 Data Valid (D)
The 24LC01B/02B supports a bi-directional two-wire The state of the data line represents valid data when,
bus and data transmission protocol. A device that after a START condition, the data line is stable for the
sends data onto the bus is defined as transmitter, and duration of the HIGH period of the clock signal.
a device receiving data as receiver. The bus has to be
The data on the line must be changed during the LOW
controlled by a master device which generates the
period of the clock signal. There is one clock pulse per
serial clock (SCL), controls the bus access, and gener-
bit of data.
ates the START and STOP conditions, while the
24LC01B/02B works as slave. Both master and slave Each data transfer is initiated with a START condition
can operate as transmitter or receiver, but the master and terminated with a STOP condition. The number of
device determines which mode is activated. the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
3.0 BUS CHARACTERISTICS will be stored when doing a write operation. When an
The following bus protocol has been defined: overwrite does occur, it will replace data in a first in first
• Data transfer may be initiated only when the bus is out fashion.
not busy.
3.5 Acknowledge
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes Each receiving device, when addressed, is obliged to
in the data line while the clock line is HIGH will be generate an acknowledge after the reception of each
interpreted as a START or STOP condition. byte. The master device must generate an extra clock
Accordingly, the following bus conditions have been pulse which is associated with this acknowledge bit.
defined (Figure 3-1). Note: The 24LC01B/02B does not generate any
acknowledge bits if an internal program-
3.1 Bus not Busy (A) ming cycle is in progress.
Both data and clock lines remain HIGH. The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
3.2 Start Data Transfer (B) way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
A HIGH to LOW transition of the SDA line while the
course, setup and hold times must be taken into
clock (SCL) is HIGH determines a START condition. All
account. A master must signal an end of data to the
commands must be preceded by a START condition.
slave by not generating an acknowledge bit on the last
3.3 Stop Data Transfer (C) byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
A LOW to HIGH transition of the SDA line while the master to generate the STOP condition.
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A ) (B) (D) (D) (C) (A)
SCL

SDA

START ADDRESS OR DATA STOP

CONDITION ACKNOWLEDGE ALLOWED CONDITION
VALID TO CHANGE

DS21222A-page 4  1997 Microchip Technology Inc.

 24LC01B/02B Modules
4.0 BUS CHARACTERISTICS 5.0 WRITE OPERATION
4.1 Slave Address 5.1 Byte Write
After generating a START condition, the bus master Following the start signal from the master, the device
transmits the slave address consisting of a 4-bit device code (4 bits), the don't care bits (3 bits), and the R/W
code (1010) for the 24LC01B/02B, followed by three bit, which is a logic low, is placed onto the bus by the
don't care bits. master transmitter. This indicates to the addressed
The eighth bit of slave address determines if the master slave receiver that a byte with a word address will follow
device wants to read or write to the 24LC01B/02B after it has generated an acknowledge bit during the
(Figure 4-1). ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
The 24LC01B/02B monitors the bus for its correspond- into the address pointer of the 24LC01B/02B. After
ing slave address all the time. It generates an acknowl- receiving another acknowledge signal from the
edge bit if the slave address was true, and it is not in a 24LC01B/02B, the master device will transmit the data
programming mode. word to be written into the addressed memory location.
The 24LC01B/02B acknowledges again and the master
Control Chip generates a stop condition. This initiates the internal
Operation R/W
Code Select write cycle, and during this time the 24LC01B/02B will
Read 1010 XXX 1 not generate acknowledge signals (Figure 5-1).
Write 1010 XXX 0
5.2 Page Write

FIGURE 4-1: CONTROL BYTE The write control byte, word address, and the first data
ALLOCATION byte are transmitted to the 24LC01B/02B in the same
way as in a byte write. But instead of generating a stop
START READ/WRITE condition, the master transmits up to eight data bytes to
the 24LC01B/02B, which are temporarily stored in the
on-chip page buffer and will be written into the memory
SLAVE ADDRESS R/W A
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con-
1 0 1 0 X X X stant. If the master should transmit more than eight
words prior to generating the stop condition, the
X = Don’t care address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 5-2).

FIGURE 5-1: BYTE WRITE

S
BUS ACTIVITY T CONTROL WORD S
MASTER A BYTE ADDRESS DATA T
R O
T P

SDA LINE S P

A A A
BUS ACTIVITY C C C
K K K

FIGURE 5-2: PAGE WRITE

BUS ACTIVITY S
T CONTROL S
MASTER A WORD
BYTE ADDRESS (n) T
R DATA n DATAn + 1 DATAn + 7 O
T P
SDA LINE S P
A A A A A
BUS ACTIVITY C C C C C
K K K K K

 1997 Microchip Technology Inc. DS21222A-page 5

24LC01B/02B Modules
6.0 ACKNOWLEDGE POLLING 7.0 READ OPERATION
Since the device will not acknowledge during a write Read operations are initiated in the same way as write
cycle, this can be used to determine when the cycle is operations with the exception that the R/W bit of the
complete (this feature can be used to maximize bus slave address is set to one. There are three basic types
throughput). Once the stop condition for a write com- of read operations: current address read, random read,
mand has been issued from the master, the device ini- and sequential read.
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send- 7.1 Current Address Read
ing a start condition followed by the control byte for a
The 24LC01B/02B contains an address counter that
write command (R/W = 0). If the device is still busy with
maintains the address of the last word accessed, inter-
the write cycle, then NO ACK will be returned. If the
nally incremented by one. Therefore, if the previous
cycle is complete, then the device will return the ACK,
access (either a read or write operation) was to address
and the master can then proceed with the next read or
n, the next current address read operation would
write command. See Figure 6-1 for flow diagram.
access data from address n + 1. Upon receipt of the
slave address with R/W bit set to one, the 24LC01B/
FIGURE 6-1: ACKNOWLEDGE POLLING 02B issues an acknowledge and transmits the 8-bit
FLOW data word. The master will not acknowledge the transfer
but does generate a stop condition and the 24LC01B/
Send 02B discontinues transmission (Figure 7-1).
Write Command
7.2 Random Read
Random read operations allow the master to access
Send Stop any memory location in a random manner. To perform
Condition to this type of read operation, first the word address must
Initiate Write Cycle be set. This is done by sending the word address to the
24LC01B/02B as part of a write operation. After the
word address is sent, the master generates a start con-
dition following the acknowledge. This terminates the
Send Start
write operation, but not before the internal address
pointer is set. Then, the master issues the control byte
again but with the R/W bit set to a one. The 24LC01B/
02B will then issue an acknowledge and transmits the
Send Control Byte
with R/W = 0 8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24LC01B/02B discontinues transmission (Figure 7-1).

Did Device 7.3 Sequential Read

NO
Acknowledge
(ACK = 0)? Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC01B/02B transmits
YES the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
Next directs the 24LC01B/02B to transmit the next sequen-
Operation
tially addressed 8-bit word (Figure 7-2).
To provide sequential reads the 24LC01B/02B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.

7.4 Noise Protection

The 24LC01B/02B employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

DS21222A-page 6  1997 Microchip Technology Inc.

 24LC01B/02B Modules
FIGURE 7-1: CURRENT ADDRESS READ
S
BUS ACTIVITY T S
A CONTROL T
MASTER R BYTE DATA n O
T P

SDA LINE
S P

BUS ACTIVITY A N
C O
K
A
C
K

FIGURE 7-1: RANDOM READ

S S
T T S
BUS ACTIVITY A CONTROL WORD A CONTROL T
MASTER R BYTE ADDRESS (n) R BYTE DATA n O
T T P

SDA LINE S S P
A A A N
BUS ACTIVITY C C C O
K K K
A
C
K

FIGURE 7-2: SEQUENTIAL READ

S
A A A T
BUS ACTIVITY CONTROL C C C O
MASTER BYTE K K K P
SDA LINE P
A N
BUS ACTIVITY C DATA n DATA n + 1 DATA n + 2 DATA n + X O
K
A
C
K

 1997 Microchip Technology Inc. DS21222A-page 7

24LC01B/02B Modules
8.0 SHIPPING METHOD
The micromodules will be shipped to customers in clear
plastic trays. Each tray holds 150 modules, and the
trays can be stacked in a manner similar to shipping die
in waffle packs. A tray drawing with dimensions is
shown in Figure 8-1.

FIGURE 8-1: TRAY DIMENSIONS

9.374 [238.09]

8.145 [206.88]

0.500 [12.70]
0.980 [24.89] TYP

0.860 [21.84] TYP.

14.000 [355.60]
12.040 [305.82]

SMART CARD MODULES ANTISTATIC

R 0.300 [7.62] TYP
R 0.270 [6.86] TYP

0.905 [22.99]
0.617 [15.68]

DS21222A-page 8  1997 Microchip Technology Inc.

 DEVICE SIDE
0.465 ± 0.002
FIGURE 8-2:

[11.80 ± 0.05]

0.090 [2.29] MIN EPOXY 0.285 [7.24] MAX

FREE AREA (TYP.)
0.146 ± 0.002 0.174 ± 0.002
R. 0.059 [1.50] (4X) [3.71 ± 0.05] [4.42 ± 0.05]

VIA HOLES (8x)

I.D. ¯ 0.026 [0.66]
O.D. ¯ 0.042 [1.06]

 1997 Microchip Technology Inc.

0.1043 ± 0.002
[2.65 ± 0.05] TYP.

0.270 [6.86] MAX.

MODULE DIMENSIONS

0.419 ± 0.002 A A
[10.63 ± 0.05]

0.209 ± 0.002
[5.31 ± 0.05]
0.1043 ± 0.002
[2.65 ± 0.05]
(8x)

0.232 ± 0.002 CONTACT SIDE

[5.90 ± 0.05]

DIE 0.0235 [0.60] MAX.

SECTION A-A
GLOB SIZE
0.015 [0.38] MAX.
FR4 TAPE 0.004 [0.10] MAX.

0.007 [0.18] MAX.

COPPER BASE NICKEL PLATED, 150 MIN m IN

GOLD FLASH 3-7 m IN

DS21222A-page 9
24LC01B/02B Modules
24LC01B/02B Modules
NOTES:

DS21222A-page 10  1997 Microchip Technology Inc.

 24LC01B/02B Modules
24LC01B/02B PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

24LC01B/02B — /MT
Package MT = Micromodules in trays

Temperature Blank = 0˚C to +70˚C

Range:

24LC01B 1K I2C Serial EEPROM in ISO Module

Device:
24LC02B 2K I2C Serial EEPROM in ISO Module

Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

 1997 Microchip Technology Inc. DS21222A-page 11

 M
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All rights reserved. ©1997, Microchip Technology Incorporated, USA. 8/97 Printed on recycled paper.

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DS21222A-page 12  1997 Microchip Technology Inc.