24C01SC/02SC

1K/2K 5.0V I2C™ Serial EEPROMs for Smart Cards

FEATURES DIE LAYOUT

• ISO Standard 7816 pad locations VSS
• Low power CMOS technology
- 1 mA active current typical
VCC
- 10 µA standby current typical at 5.5V
• Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8) SDA
• 2-wire serial interface bus, I2C™ compatible
• 100 kHz and 400 kHz compatibility DC
SCL
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write BLOCK DIAGRAM
• ESD protection > 4 kV
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years HV GENERATOR

• Available for extended temperature ranges

- Commercial (C): 0°C to +70°C I/O MEMORY EEPROM
CONTROL CONTROL ARRAY
LOGIC LOGIC XDEC
DESCRIPTION
PAGE LATCHES

The Microchip Technology Inc. 24C01SC and

24C02SC are 1K-bit and 2K-bit Electrically Erasable SDA SCL
YDEC
PROMs with bondpad positions optimized for smart
card applications. The devices are organized as a sin-
gle block of 128 x 8-bit or 256 x 8-bit memory with a VCC SENSE AMP
two-wire serial interface. The 24C01SC and 24C02SC VSS R/W CONTROL

also have page-write capability for up to 8 bytes of data.

I2C is a trademark of Philips Corporation.

 1999 Microchip Technology Inc. DS21170D-page 1

24C01SC/02SC
1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PAD FUNCTION TABLE

1.1 Maximum Ratings* Name Function

VCC...................................................................................7.0V
VSS Ground
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V SDA Serial Address/Data I/O
Storage temperature .....................................-65°C to +150°C SCL Serial Clock
Ambient temp. with power applied ................-65°C to +125°C
ESD protection on all pads............................................ Š4 kV VCC +4.5V to 5.5V Power Supply
*Notice: Stresses above those listed under “Maximum ratings” DC Don’t connect
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

VCC = +4.5V to +5.5V Commercial (C): Tamb = 0°C to +70°C
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pads:
High level input voltage VIH .7 VCC — —
Low level input voltage VIL — .3 VCC V
Hysteresis of Schmidt trigger inputs VHYS .05 VCC — V (Note)
Low level output voltage VOL — .40 V IOL = 3.0 mA, VCC = 4.5V
Input leakage current (SCL) ILI -10 10 µA VIN = .1V to 5.5V
Output leakage current (SDA) ILO -10 10 µA VOUT = .1V to 5.5V
Pin capacitance (all inputs/outputs) CIN, — 10 pF VCC = 5.0V (Note 1)
COUT Tamb = 25°C, FCLK = 1 MHz
Operating current ICC Write — 3 mA VCC = 5.5V
ICC Read — 1 mA Vcc = 5.5V, SCL = 400 KHz
Standby current ICCS — 100 µA VCC = 5.5V, SDA = SCL = VCC
Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING START/STOP
VHYS

SCL
THD:STA
TSU:STA TSU:STO

SDA

START STOP

DS21170D-page 2  1999 Microchip Technology Inc.

 24C01SC/02SC
TABLE 1-3: AC CHARACTERISTICS

Parameter Symbol Min. Max. Units Remarks

Clock frequency FCLK — 400 kHz
Clock high time THIGH 600 — ns
Clock low time TLOW 1300 — ns
SDA and SCL rise time TR — 300 ns (Note 1)
SDA and SCL fall time TF — 300 ns (Note 1)
START condition hold time THD:STA 600 — ns After this period the first clock
pulse is generated
START condition setup time TSU:STA 600 — ns Only relevant for repeated
START condition
Data input hold time THD:DAT 0 — ns (Note 2)
Data input setup time TSU:DAT 100 — ns
STOP condition setup time TSU:STO 600 — ns
Output valid from clock TAA — 900 ns (Note 2)
Bus free time TBUF 1300 — ns Time the bus must be free
before a new transmission can
start
Output fall time from VIH TOF 20 +0.1 250 ns (Note 1), CB ð 100 pF
minimum to VIL maximum CB
Input filter spike suppression TSP — 50 ns (Note 3)
(SDA and SCL pins)
Write cycle time TWR — 10 ms Byte or Page mode
Endurance — 1M — cycles 25°C, Vcc = 5V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2: BUS TIMING DATA
TF TR
THIGH
TLOW

SCL
TSU:STA
THD:DAT TSU:DAT TSU:STO
THD:STA
SDA
IN TSP

TAA THD:STA
TAA TBUF

SDA
OUT

 1999 Microchip Technology Inc. DS21170D-page 3

24C01SC/02SC
2.0 FUNCTIONAL DESCRIPTION 3.4 Data Valid (D)
The 24C01SC/02SC supports a bi-directional two-wire The state of the data line represents valid data when,
bus and data transmission protocol. A device that after a START condition, the data line is stable for the
sends data onto the bus is defined as transmitter, and duration of the HIGH period of the clock signal.
a device receiving data as receiver. The bus has to be
The data on the line must be changed during the LOW
controlled by a master device which generates the
period of the clock signal. There is one clock pulse per
serial clock (SCL), controls the bus access, and gener-
bit of data.
ates the START and STOP conditions, while the
24C01SC/02SC works as slave. Both master and slave Each data transfer is initiated with a START condition
can operate as transmitter or receiver, but the master and terminated with a STOP condition. The number of
device determines which mode is activated. the data bytes transferred between the START and
STOP conditions is determined by the master device
3.0 BUS CHARACTERISTICS and is theoretically unlimited, although only the last 16
The following bus protocol has been defined: will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first in first
• Data transfer may be initiated only when the bus
out fashion.
is not busy.
• During data transfer, the data line must remain 3.5 Acknowledge
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be Each receiving device, when addressed, is obliged to
interpreted as a START or STOP condition. generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
Accordingly, the following bus conditions have been
pulse which is associated with this acknowledge bit.
defined (Figure 3-1).
Note: The 24C01SC/02SC does not generate
3.1 Bus not Busy (A) any acknowledge bits if an internal pro-
gramming cycle is in progress.
Both data and clock lines remain HIGH.
The device that acknowledges has to pull down the
3.2 Start Data Transfer (B) SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
A HIGH to LOW transition of the SDA line while the period of the acknowledge related clock pulse. Of
clock (SCL) is HIGH determines a START condition. All course, setup and hold times must be taken into
commands must be preceded by a START condition. account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
3.3 Stop Data Transfer (C)
byte that has been clocked out of the slave. In this case,
A LOW to HIGH transition of the SDA line while the the slave must leave the data line HIGH to enable the
clock (SCL) is HIGH determines a STOP condition. All master to generate the STOP condition.
operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A ) (B) (D) (D) (C) (A)
SCL

SDA

START ADDRESS OR DATA STOP

CONDITION ACKNOWLEDGE ALLOWED CONDITION
VALID TO CHANGE

DS21170D-page 4  1999 Microchip Technology Inc.

 24C01SC/02SC
3.6 Slave Address 4.0 WRITE OPERATION
After generating a START condition, the bus master 4.1 Byte Write
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C01SC/02SC, followed by three Following the start signal from the master, the device
don’t care bits. code (4 bits), the don’t care bits (3 bits), and the R/W
The eighth bit of slave address determines if the master bit, which is a logic low, is placed onto the bus by the
device wants to read or write to the 24C01SC/02SC master transmitter. This indicates to the addressed
(Figure 3-2). slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
The 24C01SC/02SC monitors the bus for its corre- ninth clock cycle. Therefore, the next byte transmitted
sponding slave address all the time. It generates an by the master is the word address and will be written
acknowledge bit if the slave address was true, and it is into the address pointer of the 24C01SC/02SC. After
not in a programming mode. receiving another acknowledge signal from the
24C01SC/02SC, the master device will transmit the
Control Chip data word to be written into the addressed memory
Operation R/W
Code Select location. The 24C01SC/02SC acknowledges again and
Read 1010 XXX 1 the master generates a stop condition. This initiates the
Write 1010 XXX 0 internal write cycle, and during this time the
24C01SC/02SC will not generate acknowledge signals
FIGURE 3-2: CONTROL BYTE (Figure 4-1).
ALLOCATION
4.2 Page Write
START READ/WRITE
The write control byte, word address, and the first data
byte are transmitted to the 24C01SC/02SC in the same
SLAVE ADDRESS R/W A way as in a byte write. But instead of generating a stop
condition, the master transmits up to eight data bytes to
the 24C01SC/02SC, which are temporarily stored in
the on-chip page buffer and will be written into the
1 0 1 0 X X X memory after the master has transmitted a stop condi-
tion. After the receipt of each word, the three lower
X = Don’t care order address pointer bits are internally incremented by
one. The higher order five bits of the word address
remains constant. If the master should transmit more
than eight words prior to generating the stop condition,
the address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).

Note: Page write operations are limited to writing

bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.

 1999 Microchip Technology Inc. DS21170D-page 5

24C01SC/02SC
FIGURE 4-1: BYTE WRITE
S
BUS ACTIVITY T CONTROL WORD S
MASTER A BYTE ADDRESS DATA T
R O
T P

SDA LINE S P

A A A
BUS ACTIVITY C C C
K K K

FIGURE 4-2: PAGE WRITE

BUS ACTIVITY S
T CONTROL S
MASTER A WORD
BYTE ADDRESS (n) T
R DATA n DATAn + 1 DATAn + 7 O
T P
SDA LINE S P
A A A A A
BUS ACTIVITY C C C C C
K K K K K

DS21170D-page 6  1999 Microchip Technology Inc.

 24C01SC/02SC
5.0 ACKNOWLEDGE POLLING 6.0 READ OPERATION
Since the device will not acknowledge during a write Read operations are initiated in the same way as write
cycle, this can be used to determine when the cycle is operations with the exception that the R/W bit of the
complete (this feature can be used to maximize bus slave address is set to one. There are three basic types
throughput). Once the stop condition for a write com- of read operations: current address read, random read,
mand has been issued from the master, the device ini- and sequential read.
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send- 6.1 Current Address Read
ing a start condition followed by the control byte for a
The 24C01SC/02SC contains an address counter that
write command (R/W = 0). If the device is still busy with
maintains the address of the last word accessed, inter-
the write cycle, then NO ACK will be returned. If the
nally incremented by one. Therefore, if the previous
cycle is complete, then the device will return the ACK,
access (either a read or write operation) was to
and the master can then proceed with the next read or
address n, the next current address read operation
write command. See Figure 5-1 for flow diagram.
would access data from address n + 1. Upon receipt of
FIGURE 5-1: ACKNOWLEDGE POLLING the slave address with R/W bit set to one, the
FLOW 24C01SC/02SC issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
Send 24C01SC/02SC discontinues transmission
Write Command (Figure 6-1).

6.2 Random Read

Send Stop
Random read operations allow the master to access
Condition to
Initiate Write Cycle any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C01SC/02SC as part of a write operation. After the
Send Start word address is sent, the master generates a start con-
dition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then, the master issues the control byte
Send Control Byte again but with the R/W bit set to a one. The
with R/W = 0 24C01SC/02SC will then issue an acknowledge and
transmits the 8-bit data word. The master will not
acknowledge the transfer but does generate a stop
condition and the 24C01SC/02SC discontinues trans-
Did Device NO
Acknowledge mission (Figure 6-2).
(ACK = 0)?
YES

Next
Operation

 1999 Microchip Technology Inc. DS21170D-page 7

24C01SC/02SC
6.3 Sequential Read 6.4 Noise Protection
Sequential reads are initiated in the same way as a ran- The 24C01SC/02SC employs a VCC threshold detector
dom read except that after the 24C01SC/02SC trans- circuit which disables the internal erase/write logic if the
mits the first data byte, the master issues an VCC is below 1.5 volts at nominal conditions.
acknowledge as opposed to a stop condition in a ran- The SCL and SDA inputs have Schmitt trigger and filter
dom read. This directs the 24C01SC/02SC to transmit circuits which suppress noise spikes to assure proper
the next sequentially addressed 8-bit word device operation even on a noisy bus.
(Figure 6-3).
To provide sequential reads the 24C01SC/02SC con-
tains an internal address pointer which is incremented
by one at the completion of each operation. This
address pointer allows the entire memory contents to
be serially read during one operation.

FIGURE 6-1: CURRENT ADDRESS READ

S
BUS ACTIVITY T S
A CONTROL T
MASTER R BYTE DATA n O
T P

SDA LINE
S P

BUS ACTIVITY A N
C O
K
A
C
K

FIGURE 6-2: RANDOM READ

S S
T T S
BUS ACTIVITY A CONTROL WORD A CONTROL T
MASTER R BYTE ADDRESS (n) R BYTE DATA n O
T T P

SDA LINE S S P
A A A N
BUS ACTIVITY C C C O
K K K
A
C
K

FIGURE 6-3: SEQUENTIAL READ

S
T
BUS ACTIVITY CONTROL DATA n DATA n + 1 DATA n + 2 DATA n + X O
MASTER BYTE P
SDA LINE P
A A A A N
BUS ACTIVITY C C C C O
K K K K
A
C
K

DS21170D-page 8  1999 Microchip Technology Inc.

 24C01SC/02SC
7.0 PAD DESCRIPTIONS 8.0 DIE CHARACTERISTICS
Figure 8-1 shows the die layout of the 24C01SC/02SC,
7.1 SDA Serial Address/Data Input/Output
including bondpad positions. Table 8-1 shows the
This is a bi-directional pad used to transfer addresses actual coordinates of the bondpad midpoints with
and data into and data out of the device. It is an open respect to the center of the die.
drain terminal, therefore the SDA bus requires a pull-up
FIGURE 8-1: DIE LAYOUT
resistor to VCC (typical 10K¾ for 100 kHz, 2 K¾ for
400 kHz). DIP
For normal data transfer SDA is allowed to change only VSS
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi- VCC
tions.

7.2 SCL Serial Clock SDA

This input is used to synchronize the data transfer from DC

SCL
and to the device.

7.3 DC Don’t Connect TABLE 8-1: BONDPAD COORDINATES

This pad is used for test purposes and should not be Pad Midpoint, Pad Midpoint,
bonded out. It is pulled down to VSS through an internal Pad Name
X dir. Y dir.
resistor.
VSS -495.000 749.130
SDA -605.875 -271.875
SCL 479.875 -746.625
VCC 605.875 -261.375
Note 1: Dimensions are in microns.
2: Center of die is at the 0,0 point.

 1999 Microchip Technology Inc. DS21170D-page 9

24C01SC/02SC
NOTES:

DS21170D-page 10  1999 Microchip Technology Inc.

 24C01SC/02SC
24C01SC/02SC Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.

24C01SC/02SC — /S
Die Thickness Blank = 11 mils
08 = 8 mils
Other die thicknesses available, please
consult factory.

Package: S = Die in Wafer Pak

W = Wafer
WF = Sawed Wafer on Frame

Temperature Blank = 0°C to +70°C

Range:

Device: 24C01SC 1K 12C ISO Smart Card die

24C02SC 2K 12C ISO Smart Card die

Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

4. Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 1999 Microchip Technology Inc. DS21170D-page 11

Note the following details of the code protection feature on PICmicro® MCUs.

• The PICmicro family meets the specifications contained in the Microchip Data Sheet.
• Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
• Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.

Information contained in this publication regarding device Trademarks

applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, FilterLab,
ensure that your application meets with your specifications. KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
No representation or warranty is given and no liability is PICSTART, PRO MATE, SEEVAL and The Embedded Control
assumed by Microchip Technology Incorporated with respect Solutions Company are registered trademarks of Microchip Tech-
to the accuracy or use of such information, or infringement of nology Incorporated in the U.S.A. and other countries.
patents or other intellectual property rights arising from such
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
use or otherwise. Use of Microchip’s products as critical com-
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
ponents in life support systems is not authorized except with
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
express written approval by Microchip. No licenses are con-
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
veyed, implicitly or otherwise, under any intellectual property
and Total Endurance are trademarks of Microchip Technology
rights.
Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

© 2002, Microchip Technology Incorporated, Printed in the

U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.

 2002 Microchip Technology Inc.

M
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01/18/02

 2002 Microchip Technology Inc.