24C32

32K 5.0V I2C Smart Serial EEPROM

FEATURES PACKAGE TYPES

• Voltage operating range: 4.5V to 5.5V PDIP
- Peak write current 3 mA at 5.5V
- Maximum read current 150 µA at 5.5V A0 1 8 VCC
- Standby current 1 µA typical
A1 2 7 NC
• Industry standard two-wire bus protocol, I2C

24C32
compatible
- Including 100 kHz and 400 kHz modes A2 3 6 SCL
• Self-timed write cycle (including auto-erase)
• Power on/off data protection circuitry VSS 4 5 SDA
• Endurance:
- 10,000,000 Erase/Write cycles
guaranteed for High Endurance Block
- 1,000,000 E/W cycles guaranteed for
Standard Endurance Block SOIC
• 8 byte page, or byte modes available
• 1 page x 8 line input cache (64 bytes) for fast write
loads A0 1 8 VCC
• Schmitt trigger, filtered inputs for noise suppres-
sion A1 2 7 NC

24C32
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page A2 3 6 SCL
• Up to 8 chips may be connected to the same bus
for up to 256K bits total memory VSS 4 5 SDA
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
BLOCK DIAGRAM
- Commercial (C): 0˚C to +70˚C
A0..A2 HV GENERATOR
- Industrial (I): -40˚C to +85˚C

DESCRIPTION I/O MEMORY

XDEC EEPROM ARRAY
CONTROL CONTROL
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K LOGIC LOGIC
bit) Serial Electrically Erasable PROM. This device has PAGE LATCHES
been developed for advanced, low power applications
I/O
such as personal communications or data acquisition. SCL
Cache
The 24C32 features an input cache for fast write loads
with a capacity of eight 8-byte pages, or 64 bytes. It SDA
also features a fixed 4K-bit block of ultra-high endur- YDEC
ance memory for data that changes frequently. The
24C32 is capable of both random and sequential reads VCC
up to the 32K boundary. Functional address lines allow VSS
SENSE AMP
R/W CONTROL
up to 8 - 24C32 devices on the same bus, for up to 256K
bits address space. Advanced CMOS technology
makes this device ideal for low-power non-volatile code
and data applications. The 24C32 is available in the
standard 8-pin plastic DIP and 8-pin surface mount
SOIC package

I2C is a trademark of Philips Corporation.

 1996 Microchip Technology Inc. DS21061F-page 1

This document was created with FrameMaker 4 0 4

24C32
1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PIN FUNCTION TABLE

1.1 Maximum Ratings* Name Function

VCC ..................................................................................7.0V
A0..A2 User Configurable Chip Selects
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V VSS Ground
Storage temperature ..................................... -65˚C to +150˚C SDA Serial Address/Data I/O
Ambient temp. with power applied ................ -65˚C to +125˚C
SCL Serial Clock
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins ..................................................≥ 4 kV VCC +4.5V to 5.5V Power Supply
*Notice: Stresses above those listed under “Maximum Ratings” NC No Internal Connection
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

VCC = +4.5V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C
Parameter Symbol Min Max Units Conditions
A0, A1, A2, SCL and SDA pins:
High level input voltage VIH .7 Vcc — V
Low level input voltage VIL — .3 Vcc V
Hysteresis of Schmitt Trigger inputs VHYS .05 Vcc — V (Note)
Low level output voltage VOL — .40 V IOL = 3.0 mA
Input leakage current ILI -10 10 µA VIN = .1V TO VCC
Output leakage current ILO -10 10 µA VOUT = .1V to VCC
Pin capacitance CIN, COUT — 10 pF VCC = 5.0V (Note 1)
(all inputs/outputs) Tamb = 25˚C, Fclk = 1 MHz
Operating current ICC WRITE — 3 mA VCC = 5.5V, SCL = 400 kHz
ICC Read — 150 µA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS — 5 µA VCC = 5.5V, SCL = SDA = VCC
(Note)
Note: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1: BUS TIMING START/STOP

VHYS

SCL
THD:STA
TSU:STA TSU:STO

SDA

START STOP

DS21061F-page 2  1996 Microchip Technology Inc.

 24C32
TABLE 1-3: AC CHARACTERISTICS

STD. MODE FAST MODE

Parameter Symbol Units Remarks
Min Max Min Max
Clock frequency FCLK — 100 — 400 kHz
Clock high time THIGH 4000 — 600 — ns
Clock low time TLOW 4700 — 1300 — ns
SDA and SCL rise time TR — 1000 — 300 ns (Note 1)
SDA and SCL fall time TF — 300 — 300 ns (Note 1)
START condition hold time THD:STA 4000 — 600 — ns After this period the first clock
pulse is generated
START condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated
START condition
Data input hold time THD:DAT 0 — 0 — ns
Data input setup time TSU:DAT 250 — 100 — ns
STOP condition setup time TSU:STO 4000 — 600 — ns
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free
before a new transmission can
start
Output fall time from VIH min TOF — 250 20 + 0.1 250 ns (Note 1), CB ≤ 100 pF
to VIL max CB
Input filter spike suppres- TSP — 50 — 50 ns (Note 3)
sion (SDA and SCL pins)
Write cycle time TWR — 5 — 5 ms/page (Note 4)
Endurance
High Endurance Block — 10M — 10M — cycles 25°C, Vcc = 5.0V, Block Mode
Rest of Array — 1M — 1M — (Note 5)
Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2: BUS TIMING DATA

TF TR
THIGH
TLOW

SCL
TSU:STA THD:DAT TSU:DAT TSU:STO
THD:STA
SDA
IN TSP
TBUF
TAA
TAA
SDA
OUT

 1996 Microchip Technology Inc. DS21061F-page 3

24C32
2.0 FUNCTIONAL DESCRIPTION 3.4 Data Valid (D)
The 24C32 supports a bidirectional two-wire bus and The state of the data line represents valid data when,
data transmission protocol. A device that sends data after a START condition, the data line is stable for the
onto the bus is defined as transmitter, and a device duration of the HIGH period of the clock signal.
receiving data as receiver. The bus must be controlled
The data on the line must be changed during the LOW
by a master device which generates the serial clock
period of the clock signal. There is one clock pulse per
(SCL), controls the bus access, and generates the
bit of data.
START and STOP conditions, while the 24C32 works
as slave. Both master and slave can operate as trans- Each data transfer is initiated with a START condition
mitter or receiver but the master device determines and terminated with a STOP condition. The number of
which mode is activated. the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined: 3.5 Acknowledge
• Data transfer may be initiated only when the bus is Each receiving device, when addressed, is obliged to
not busy. generate an acknowledge signal after the reception of
• During data transfer, the data line must remain each byte. The master device must generate an extra
stable whenever the clock line is HIGH. Changes clock pulse which is associated with this acknowledge
in the data line while the clock line is HIGH will be bit.
interpreted as a START or STOP condition.
Note: The 24C32 does not generate any
Accordingly, the following bus conditions have been acknowledge bits if an internal program-
defined (Figure 3-1). ming cycle is in progress.

3.1 Bus not Busy (A) A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
Both data and clock lines remain HIGH. that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
3.2 Start Data Transfer (B) setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
A HIGH to LOW transition of the SDA line while the slave by NOT generating an acknowledge bit on the last
clock (SCL) is HIGH determines a START condition. All byte that has been clocked out of the slave. In this
commands must be preceded by a START condition. case, the slave (24C32) will leave the data line HIGH to
enable the master to generate the STOP condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

SCL

SDA

START CONDITION ADDRESS DATA ALLOWED STOP

OR TO CHANGE CONDITION
ACKNOWLEDGE
VALID

DS21061F-page 4  1996 Microchip Technology Inc.

 24C32
3.6 Device Addressing acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24C32 will select a read or write
A control byte is the first byte received following the operation.
start condition from the master device. The control byte
consists of a four bit control code; for the 24C32 this is Control
set as 1010 binary for read and write operations. The Operation Device Select R/W
Code
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device Read 1010 Device Address 1
to select which of the eight devices are to be accessed. Write 1010 Device Address 0
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte (R/W) FIGURE 3-2: CONTROL BYTE
defines the operation to be performed. When set to a ALLOCATION
one a read operation is selected, and when set to a
zero a write operation is selected. The next two bytes START READ/WRITE
received define the address of the first data byte
(Figure 3-3). Because only A11..A0 are used, the upper SLAVE ADDRESS R/W A
four address bits must be zeros. The most significant bit
of the most significant byte of the address is transferred
first. Following the start condition, the 24C32 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri- 1 0 1 0 A2 A1 A0
ate device select bits, the slave device outputs an

FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS

CONTROL BYTE ADDRESS BYTE 1 ADDRESS BYTE 0

A A A A A A A A A
1 0 1 0 2 1 0 R/W 0 0 0 0 11 10 9 8 7 • • • • • • 0

SLAVE DEVICE
ADDRESS SELECT
BUS

 1996 Microchip Technology Inc. DS21061F-page 5

24C32
4.0 WRITE OPERATION 4.3 Page Write

4.1 Split Endurance The write control byte, word address and the first data
byte are transmitted to the 24C32 in the same way as
The 24C32 is organized as a continuous 32K block of in a byte write. But instead of generating a stop condi-
memory. However, the first 4K, starting at address 000, tion, the master transmits up to eight pages of eight
is rated at 10,000,000 E/W cycles guaranteed. The data bytes each (64 bytes total) which are temporarily
remainder of the array, 28K bits, is rated at 100K E/W stored in the on-chip page cache of the 24C32. They
cycles guaranteed. This feature is helpful in applica- will be written from cache into the EEPROM array after
tions in which some data change frequently, while a the master has transmitted a stop condition. After the
majority of the data change infrequently. One example receipt of each word, the six lower order address
would be a cellular telephone in which last-number pointer bits are internally incremented by one. The
redial and microcontroller scratch pad require a high- higher order seven bits of the word address remain con-
endurance block, while speed dials and lookup tables stant. If the master should transmit more than eight
change infrequently and so require only a standard bytes prior to generating the stop condition (writing
endurance rating. across a page boundary), the address counter (lower
three bits) will roll over and the pointer will be incre-
4.2 Byte Write mented to point to the next line in the cache. This can
continue to occur up to eight times or until the cache is
Following the start condition from the master, the con-
full, at which time a stop condition should be generated
trol code (four bits), the device select (three bits), and
by the master. If a stop condition is not received, the
the R/W bit which is a logic low are clocked onto the bus
cache pointer will roll over to the first line (byte 0) of the
by the master transmitter. This indicates to the
cache, and any further data received will overwrite pre-
addressed slave receiver that a byte with a word
viously captured data. The stop condition can be sent
address will follow after it has generated an acknowl-
at any time during the transfer. As with the byte write
edge bit during the ninth clock cycle. Therefore the next
operation, once a stop condition is received, an internal
byte transmitted by the master is the high-order byte of
write cycle will begin. The 64-byte cache will continue
the word address and will be written into the address
to capture data until a stop condition occurs or the oper-
pointer of the 24C32. The next byte is the least signifi-
ation is aborted (Figure 4-2).
cant address byte. After receiving another acknowl-
edge signal from the 24C32 the master device will
transmit the data word to be written into the addressed
memory location. The 24C32 acknowledges again and
the master generates a stop condition. This initiates the
internal write cycle, and during this time the 24C32 will
not generate acknowledge signals (Figure 4-1).

FIGURE 4-1: BYTE WRITE

S
t S
Bus Activity: a Control Word Word t
Master r Byte Address (1) Address (0) Data o
t p
SDA Line 0000
Bus Activity A A A A
C C C C
K K K K

FIGURE 4-2: PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 6-3)
S
T S
BUS A CONTROL WORD WORD T
ACTIVITY BYTE ADDRESS (1) ADDRESS (0) DATA n DATA n + 7
R O
MASTER T P

SDA LINE 0 0 0 0

A A A A A
BUS C C C C C
ACTIVITY K K K K K

DS21061F-page 6  1996 Microchip Technology Inc.

 24C32
5.0 ACKNOWLEDGE POLLING 6.0 READ OPERATION
Since the device will not acknowledge during a write Read operations are initiated in the same way as write
cycle, this can be used to determine when the cycle is operations with the exception that the R/W bit of the
complete (this feature can be used to maximize bus slave address is set to one. There are three basic types
throughput). Once the stop condition for a write com- of read operations: current address read, random read,
mand has been issued from the master, the device ini- and sequential read.
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send- 6.1 Current Address Read
ing a start condition followed by the control byte for a
The 24C32 contains an address counter that maintains
write command (R/W = 0). If the device is still busy with
the address of the last word accessed, internally incre-
the write cycle, then no ACK will be returned. If the
mented by one. Therefore, if the previous access (either
cycle is complete, then the device will return the ACK
a read or write operation) was to address n (n is any
and the master can then proceed with the next read or
legal address), the next current address read operation
write command. See Figure 5-1 for flow diagram
would access data from address n + 1. Upon receipt of
FIGURE 5-1: ACKNOWLEDGE POLLING the slave address with R/W bit set to one, the 24C32
FLOW issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
Send does generate a stop condition and the 24C32 discon-
Write Command tinues transmission (Figure 6-1).

6.2 Random Read

Send Stop Random read operations allow the master to access

Condition to any memory location in a random manner. To perform
Initiate Write Cycle this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C32 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
Send Start
start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then the master issues the con-
trol byte again but with the R/W bit set to a one. The
Send Control Byte
with R/W = 0 24C32 will then issue an acknowledge and transmit the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24C32 to discontinue transmission
Did Device NO (Figure 6-2).
Acknowledge
(ACK = 0)?
YES

Next
Operation

FIGURE 6-1: CURRENT ADDRESS READ

S
T S
BUS ACTIVITY A T
MASTER CONTROL
R BYTE DATA n O
T P

SDA LINE
A N
C O
BUS ACTIVITY K
A
C
K

 1996 Microchip Technology Inc. DS21061F-page 7

24C32
6.3 Contiguous Addressing Across To provide sequential reads the 24C32 contains an
Multiple Devices internal address pointer which is incremented by one at
the completion of each operation. This address pointer
The device select bits A2, A1, A0 can be used to allows the entire memory contents to be serially read
expand the contiguous address space for up to 256K during one operation. The address pointer, however,
bits by adding up to eight 24C32's on the same bus. In will not roll over from address 07FF to address 0000. It
this case, software can use A0 of the control byte as will roll from 07FF to unused memory space.
address bit A12, A1 as address bit A13, and A2 as
address bit A14. 6.5 Noise Protection

6.4 Sequential Read The SCL and SDA inputs have filter circuits which sup-
press noise spikes to ensure proper device operation
Sequential reads are initiated in the same way as a ran- even on a noisy bus. All I/O lines incorporate Schmitt
dom read except that after the 24C32 transmits the first triggers for 400 kHz (Fast Mode) compatibility.
data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24C32 to transmit the
next sequentially addressed 8 bit word. (Figure 6-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition.

FIGURE 6-2: RANDOM READ

S S
T T S
A CONTROL WORD WORD A CONTROL T
BYTE ADDRESS (1) ADDRESS (0) R BYTE DATA n
R T O
T P

SDA LINE 0 0 0 0

A A A A N
BUS C C C C O
ACTIVITY: K K K K
A
C
K

FIGURE 6-3: SEQUENTIAL READ

S
T
BUS ACTIVITY CONTROL O
MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X P

SDA LINE P
A A A A N
BUS ACTIVITY C C C C O
K K K K
A
C
K

DS21061F-page 8  1996 Microchip Technology Inc.

 24C32
7.0 PAGE CACHE AND ARRAY will'roll over' and be loaded into the first two bytes of
page 0 (of the cache). When the stop bit is sent, page
MAPPING 0 of the cache is written to page 3 of the array. The
The cache is a 64 byte (8 pages x 8 bytes) FIFO buffer. remaining pages in the cache are then loaded sequen-
The cache allows the loading of up to 64 bytes of data tially to the array. A write cycle is executed after each
before the write cycle is actually begun, effectively pro- page is written. If a partially loaded page in the cache
viding a 64-byte burst write at the maximum bus rate. remains when the STOP bit is sent, only the bytes that
Whenever a write command is initiated, the cache have been loaded will be written to the array.
starts loading and will continue to load until a stop bit is
received to start the internal write cycle. The total length 7.3 Power Management
of the write cycle will depend on how many pages are
loaded into the cache before the stop bit is given. Max- This design incorporates a power standby mode when
imum cycle time for each page is 5 ms. Even if a page the device is not in use and automatically powers off
is only partially loaded, it will still require the same cycle after the normal termination of any operation when a
time as a full page. If more than 64 bytes of data are stop bit is received and all internal functions are com-
loaded before the stop bit is given, the address pointer plete. This includes any error conditions, ie. not receiv-
will'wrap around' to the beginning of cache page 0 and ing an acknowledge or stop condition per the two-wire
existing bytes in the cache will be overwritten. The bus specification. The device also incorporates VDD
device will not respond to any commands while the monitor circuitry to prevent inadvertent writes (data cor-
write cycle is in progress. ruption) during low-voltage conditions. The VDD moni-
tor circuitry is powered off when the device is in standby
7.1 Cache Write Starting at a Page mode in order to further reduce power consumption.
Boundary 8.0 PIN DESCRIPTIONS
If a write command begins at a page boundary
8.1 A0, A1, A2 Chip Address Inputs
(address bits A2, A1 and A0 are zero), then all data
loaded into the cache will be written to the array in The A0..A2 inputs are used by the 24C32 for multiple
sequential addresses. This includes writing across a 4K device operation and conform to the two-wire bus stan-
block boundary. In the example shown below, dard. The levels applied to these pins define the
(Figure 8-1) a write command is initiated starting at address block occupied by the device in the address
byte 0 of page 3 with a fully loaded cache (64 bytes). map. A particular device is selected by transmitting the
The first byte in the cache is written to byte 0 of page 3 corresponding bits (A2, A1, A0) in the control byte
(of the array), with the remaining pages in the cache (Figure 3-3).
written to sequential pages in the array. A write cycle is
executed after each page is written. Since the write 8.2 SDA Serial Address/Data Input/Output
begins at page 3 and 8 pages are loaded into the
cache, the last 3 pages of the cache are written to the This is a bidirectional pin used to transfer addresses
next row in the array. and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
7.2 Cache Write Starting at a Non-Page resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400
Boundary kHz).
For normal data transfer SDA is allowed to change only
When a write command is initiated that does not begin
during SCL low. Changes during SCL high are
at a page boundary (i.e., address bits A2, A1 and A0
reserved for indicating the START and STOP condi-
are not all zero), it is important to note how the data is
tions.
loaded into the cache, and how the data in the cache is
written to the array. When a write command begins, the 8.3 SCL Serial Clock
first byte loaded into the cache is always loaded into
page 0. The byte within page 0 of the cache where the This input is used to synchronize the data transfer from
load begins is determined by the three least significant and to the device.
address bits (A2, A1, A0) that were sent as part of the
write command. If the write command does not start at
byte 0 of a page and the cache is fully loaded, then the
last byte(s) loaded into the cache will roll around to
page 0 of the cache and fill the remaining empty bytes.
If more than 64 bytes of data are loaded into the cache,
data already loaded will be overwritten. In the example
shown in Figure 8-2, a write command has been initi-
ated starting at byte 2 of page 3 in the array with a fully
loaded cache of 64 bytes. Since the cache started load-
ing at byte 2, the last two bytes loaded into the cache

 1996 Microchip Technology Inc. DS21061F-page 9

24C32
FIGURE 8-1: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY

1 Write command initiated at byte 0 of page 3 in the array;

First data byte is loaded into the cache byte 0. 2 64 bytes of data are loaded into cache.

cache page 0

cache cache cache cache page 1 cache page 2 cache page 7

• • • • • •
byte 0 byte 1 byte 7 bytes 8-15 bytes 16-23 bytes 56-63

3 Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array. 4 Remaining pages in cache are written
Write cycle is executed after every page is written. to sequential pages in array.

page 0 page 1 page 2 byte 0 byte 1 • • • byte 7 page 4 • • • page 7 array row n
page 0 page 1 page 2 page 3 page 4 • • • page 7 array row n + 1

5 Last page in cache written to page 2 in next row.

FIGURE 8-2: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY

1 Write command initiated; 64 bytes of data 2 Last 2 bytes loaded 'roll over'
loaded into cache starting at byte 2 of page 0. to beginning.
Last 2 bytes 3
loaded into
page 0 of cache. cache cache cache cache cache page 1 cache page 2 cache page 7
• • • • • •
byte 0 byte 1 byte 2 byte 7 bytes 8-15 bytes 16-23 bytes 56-63

4 Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array. 5 Remaining bytes in cache are
Write cycle is executed after every page is written. written sequentially to array.

page 0 page 1 page 2 byte 0 byte 1 byte 2 byte 3 byte 4 • • • byte 7 page 4 • • • page 7 array
row n
page 0 page 1 page 2 page 3 page 4 • • • page 7 array
row
n+1
6 Last 3 pages in cache written to next row in array.

DS21061F-page 10  1996 Microchip Technology Inc.

24C32
24C32 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

24C32 - /P
Package: P = Plastic DIP (300 mil Body), 8-lead
SM = Plastic SOIC (207 mil Body, EIAJ standard)
Temperature Blank = 0°C to +70°C
Range: I = -40°C to +85°C

Device: 24C32 32K I2C Serial EEPROM (100 kHz/400 kHz)

24C32T 32K I2C Serial EEPROM (Tape and Reel)

 1996 Microchip Technology Inc. DS21061F-page 11

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Itasca, IL 60143 Microchip Technology Viale Colleoni 1
Tel: 708 285-0071 Fax: 708 285-0075 168-1, Youngbo Bldg. 3 Floor 20041 Agrate Brianza
Dallas Samsung-Dong, Kangnam-Ku, Milan Italy
Microchip Technology Inc. Seoul, Korea Tel: 39 39 6899939 Fax: 39 39 689 9883
14651 Dallas Parkway, Suite 816 Tel: 82 2 554 7200 Fax: 82 2 558 5934
JAPAN
Dallas, TX 75240-8809 Singapore
Microchip Technology Intl. Inc.
Tel: 972 991-7177 Fax: 972 991-8588 Microchip Technology
Benex S-1 6F
Dayton 200 Middle Road
3-18-20, Shin Yokohama
Microchip Technology Inc. #10-03 Prime Centre
Kohoku-Ku, Yokohama
Suite 150 Singapore 188980
Kanagawa 222 Japan
Two Prestige Place Tel: 65 334 8870 Fax: 65 334 8850
Tel: 81 45 471 6166 Fax: 81 45 471 6122
Miamisburg, OH 45342 Taiwan, R.O.C
Tel: 513 291-1654 Fax: 513 291-9175 Microchip Technology 9/3/96
Los Angeles 10F-1C 207
Microchip Technology Inc. Tung Hua North Road
18201 Von Karman, Suite 1090 Taipei, Taiwan, ROC
Irvine, CA 92612 Tel: 886 2 717 7175 Fax: 886 2 545 0139
Tel: 714 263-1888 Fax: 714 263-1338
New York
Microchip Technmgy Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408 436-7950 Fax: 408 436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905 405-6279 Fax: 905 405-6253

All rights reserved.  1996, Microchip Technology Incorporated, USA. 9/96

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sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21061F-page 12  1996 Microchip Technology Inc.