24C01C

1K 5.0V I2C™ Serial EEPROM

Features: Description:
• Single Supply with Operation from 4.5V to 5.5V The Microchip Technology Inc. 24C01C is a 1K bit
• Low-Power CMOS Technology: Serial Electrically Erasable PROM with a voltage range
- Read current 1 mA, max. of 4.5V to 5.5V. The device is organized as a single
block of 128 x 8-bit memory with a 2-wire serial
- Standby current 5 A, max.
interface. Low-current design permits operation with
• 2-Wire Serial Interface, I2C™ Compatible max. standby and active currents of only 5 A and 1
• Cascadable up to Eight Devices mA, respectively. The device has a page write capabil-
• Schmitt Trigger Inputs for Noise Suppression ity for up to 16 bytes of data and has fast write cycle
• Output Slope Control to Eliminate Ground Bounce times of only 1 ms for both byte and page writes. Func-
tional address lines allow the connection of up to eight
• 100 kHz and 400 kHz Clock Compatibility
24C01C devices on the same bus for up to 8K bits of
• Page Write Time 1 ms max. contiguous EEPROM memory. The device is available
• Self-Timed Erase/Write Cycle in the standard 8-pin PDIP, 8-pin SOIC (3.90 mm),
• 16-Byte Page Write Buffer 8-pin 2x3 DFN and TDFN, 8-pin MSOP and TSSOP
• ESD Protection >4000V packages. The 24C01C is also available in the 6-lead
• More than 1 Million Erase/Write Cycles SOT-23 package.
• Data Retention >200 Years
Block Diagram
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN, MSOP and 6-lead SOT-23 A0 A1 A2
HV Generator
• Pb-Free and RoHS Compliant
• Temperature Ranges: I/O Memory
- Industrial (I): -40C to +85C Control Control
Logic EEPROM
- Automotive (E): -40C to +125C Logic XDEC
Array

SDA SCL

VCC YDEC
VSS

Sense Amp.
R/W Control

Package Types
PDIP, MSOP SOIC, TSSOP DFN/TDFN SOT-23

A0 1 8 VCC SCL 1 6 VCC

A0 1 8 VCC 1 8
A0 VCC
A1 2 7 Test
A1 2 7 Test VSS 2 5 A0
A1 2 7 Test 6 SCL
A2 3
A2 3 6 SCL A2 3 6 SCL VSS 4 5 SDA SDA 3 4 A1
VSS 4 5 SDA VSS 4 5 SDA

 1997-2012 Microchip Technology Inc. DS21201K-page 1

24C01C
1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC .............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins  4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

Electrical Characteristics:
DC CHARACTERISTICS Industrial (I): VCC = +4.5V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +4.5V to 5.5V TA = -40°C to +125°C
Param.
Sym. Characteristic Min. Max. Units Conditions
No.
D1 — A0, A1, A2, SCL, SDA — — — —
and WP pins:
D2 VIH High-level input voltage 0.7 VCC — V —
D3 VIL Low-level input voltage — 0.3 VCC V —

D4 VHYS Hysteresis of Schmitt 0.05 VCC — V (Note)

Trigger inputs
(SDA, SCL pins)
D5 VOL Low-level output voltage — 0.40 V IOL = 3.0 mA @ VCC = 4.5V

D6 ILI Input leakage current — ±1 A VIN = VSS or VCC, WP = VSS

D7 ILO Output leakage current — ±1 A VOUT = VSS or VCC

D8 CIN, Pin capacitance — 10 pF VCC = 5.0V (Note)
COUT (all inputs/outputs) TA = 25°C, f = 1 MHz
D9 ICC Read Operating current — 1 mA VCC = 5.5V, SCL = 400 kHz
ICC Write — 3 mA VCC = 5.5V
D10 ICCS Standby current — 5 A VCC = 5.5V, SDA = SCL = VCC
WP = VSS
Note: This parameter is periodically sampled and not 100% tested.

DS21201K-page 2  1997-2012 Microchip Technology Inc.

 24C01C
TABLE 1-2: AC CHARACTERISTICS
Electrical Characteristics:
AC CHARACTERISTICS Industrial (I): VCC = +4.5V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +4.5V to 5.5V TA = -40°C to +125°C
Param.
Sym. Characteristic Min. Max. Units Conditions
No.
1 FCLK Clock frequency — 100 kHz —
— 400 (I-temp)
2 THIGH Clock high time 4000 — ns —
600 — (I-temp)
3 TLOW Clock low time 4700 — ns —
1300 — (I-temp)
4 TR SDA and SCL rise time — 1000 ns —
(Note 1) — 300 (I-temp)
5 TF SDA and SCL fall time — 300 ns —
(Note 1)
6 THD:STA Start condition hold time 4000 — ns —
600 — (I-temp)
7 TSU:STA Start condition setup time 4700 — ns —
600 — (I-temp)
8 THD:DAT Data input hold time 0 — ns (Note 2)
9 TSU:DAT Data input setup time 250 — ns —
100 — (I-temp)
10 TSU:STO Stop condition setup time 4000 — ns —
600 — (I-temp)
11 TAA Output valid from clock — 3500 ns —
(Note 2) — 900 (I-temp)
12 TBUF Bus free time: Time the bus 4700 — ns —
must be free before a new 1300 — (I-temp)
transmission can start
13 TOF Output fall time from VIH 10 + 0.1CB 250 ns (Note 1)
minimum to VIL maximum
CB  100 pF
14 TSP Input filter spike suppression — 50 ns (Note 3)
(SDA and SCL pins)
15 TWC Write cycle time (byte or — 1.5 ms —
page) 1 (I-temp)
16 — Endurance 1,000,000 — cycles 25°C (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.

 1997-2012 Microchip Technology Inc. DS21201K-page 3

24C01C
FIGURE 1-1: BUS TIMING DATA

5 4
2 D4

SCL
7
3 8 9 10
SDA
6
IN
14

11 12
SDA
OUT

DS21201K-page 4  1997-2012 Microchip Technology Inc.

 24C01C
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

8-pin 8-pin 8-pin 8-pin 8-pin
Name SOT-23 Function
PDIP SOIC TSSOP MSOP DFN/TDFN
A0 1 1 1 1 1 5 Chip Select
A1 2 2 2 2 2 4 Chip Select
A2 3 3 3 3 3 — Chip Select
VSS 4 4 4 4 4 2 Ground
SDA 5 5 5 5 5 3 Serial Data
SCL 6 6 6 6 6 1 Serial Clock
Test 7 7 7 7 7 — Test
VCC 8 8 8 8 8 6 +4.5V to 5.5V Power Supply

2.1 SDA Serial Data 2.5 Noise Protection

This is a bidirectional pin used to transfer addresses The 24C01C employs a VCC threshold detector circuit
and data into and data out of the device. It is an open which disables the internal erase/write logic if the VCC
drain terminal; therefore, the SDA bus requires a pull- is below 3.8 volts at nominal conditions.
up resistor to VCC (typical 10 k for 100 kHz, 2 k for The SCL and SDA inputs have Schmitt Trigger and
400 kHz). filter circuits which suppress noise spikes to assure
For normal data transfer SDA is allowed to change only proper device operation even on a noisy bus.
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.

2.2 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

2.3 A0, A1, A2

The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C01C devices may be connected to the
same bus by using different Chip Select bit combina-
tions. These inputs must be connected to either VCC or
VSS.
For the SOT-23 devices up to four devices may be con-
nected to the same bus using different Chip Select bit
combinations.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.

2.4 Test
This pin is utilized for testing purposes only. It may be
tied high, tied low or left floating.

 1997-2012 Microchip Technology Inc. DS21201K-page 5

24C01C
3.0 FUNCTIONAL DESCRIPTION 4.4 Data Valid (D)
The 24C01C supports a bidirectional 2-wire bus and The state of the data line represents valid data when,
data transmission protocol. A device that sends data after a Start condition, the data line is stable for the
onto the bus is defined as transmitter, and a device duration of the high period of the clock signal.
receiving data as receiver. The bus has to be controlled The data on the line must be changed during the low
by a master device that generates the Serial Clock period of the clock signal. There is one bit of data per
(SCL), controls the bus access, and generates the Start clock pulse.
and Stop conditions, while the 24C01C works as slave.
Both master and slave can operate as transmitter or Each data transfer is initiated with a Start condition and
receiver, but the master device determines which mode terminated with a Stop condition. The number of the
is activated. data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
4.0 BUS CHARACTERISTICS will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first-in first-
The following bus protocol has been defined:
out fashion.
• Data transfer may be initiated only when the bus
is not busy. 4.5 Acknowledge
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in Each receiving device, when addressed, is required to
the data line while the clock line is high will be generate an acknowledge after the reception of each
interpreted as a Start or Stop condition. byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
Accordingly, the following bus conditions have been
defined (Figure 4-1). Note: The 24C01C does not generate any
Acknowledge bits if an internal program-
4.1 Bus Not Busy (A) ming cycle is in progress.

Both data and clock lines remain high. The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
4.2 Start Data Transfer (B)
period of the acknowledge related clock pulse. Of
A high-to-low transition of the SDA line while the clock course, setup and hold times must be taken into
(SCL) is high determines a Start condition. All account. A master must signal an end of data to the
commands must be preceded by a Start condition. slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
4.3 Stop Data Transfer (C) the slave must leave the data line high to enable the
master to generate the Stop condition (Figure 4-2)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.

DS21201K-page 6  1997-2012 Microchip Technology Inc.

 24C01C
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (C) (D) (C) (A)

SCL

SDA

Start Address or Data Stop

Condition Acknowledge Allowed Condition
Valid to Change

FIGURE 4-2: ACKNOWLEDGE TIMING

Acknowledge
Bit

SCL 1 2 3 4 5 6 7 8 9 1 2 3

SDA Data from transmitter Data from transmitter

Transmitter must release the SDA line at this point Receiver must release the SDA line at this
allowing the Receiver to pull the SDA line low to point so the Transmitter can continue send-
acknowledge the previous eight bits of data. ing data.

 1997-2012 Microchip Technology Inc. DS21201K-page 7

24C01C
5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE
FORMAT
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1). Read/Write Bit
The control byte consists of a four-bit control code; for
the 24C01C this is set as ‘1010’ binary for read and Chip Select
write operations. The next three bits of the control byte Control Code Bits
are the Chip Select bits (A2, A1, A0). The Chip Select
bits allow the use of up to eight 24C01C devices on the
S 1 0 1 0 A2 A1 A0 R/W ACK
same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2, Slave Address
A1 and A0 pins for the device to respond. These bits Start Bit Acknowledge Bit
are in effect the three Most Significant bits of the word
address.
For the SOT-23 package, the A2 address pin is not 5.1 Contiguous Addressing Across
available. During device addressing, the A2 Chip Multiple Devices
Select bit should be set to ‘0’.
The Chip Select bits A2, A1, A0 can be used to expand
The last bit of the control byte defines the operation to
the contiguous address space for up to 8K bits by
be performed. When set to a ‘1’ a read operation is
adding up to eight 24C01C devices on the same bus.
selected, and when set to a ‘0’ a write operation is
In this case, software can use A0 of the control byte as
selected. Following the Start condition, the 24C01C
address bit A8, A1 as address bit A9, and A2 as
monitors the SDA bus checking the control byte being
address bit A10. It is not possible to sequentially read
transmitted. Upon receiving a ‘1010’ code and appro-
across device boundaries.
priate Chip Select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the For the SOT-23 package, up to four 24C01C devices
state of the R/W bit, the 24C01C will select a read or can be added for up to 4K bits of address space. In this
write operation. case, software can use A0 of the control byte as
address bit A8, and A1 as address bit A9. It is not pos-
sible to sequentially read across device boundaries.

DS21201K-page 8  1997-2012 Microchip Technology Inc.

 24C01C
6.0 WRITE OPERATIONS After the receipt of each word, the four lower order
Address Pointer bits are internally incremented by one.
The higher order four bits of the word address remains
6.1 Byte Write
constant. If the master should transmit more than 16
Following the Start signal from the master, the device bytes prior to generating the Stop condition, the
code (4 bits), the Chip Select bits (3 bits), and the R/W address counter will roll over and the previously
bit, which is a logic low, is placed onto the bus by the received data will be overwritten. As with the byte write
master transmitter. The device will acknowledge this operation, once the Stop condition is received an
control byte during the ninth clock pulse. The next byte internal write cycle will begin (Figure 6-2).
transmitted by the master is the word address and will
be written into the Address Pointer of the 24C01C.
After receiving another Acknowledge signal from the Note: Page write operations are limited to writ-
24C01C the master device will transmit the data word ing bytes within a single physical page,
to be written into the addressed memory location. The regardless of the number of bytes actu-
24C01C acknowledges again and the master gener- ally being written. Physical page boundar-
ates a Stop condition. This initiates the internal write ies start at addresses that are integer
cycle, and during this time the 24C01C will not multiples of the page buffer size (or ‘page
generate Acknowledge signals (Figure 6-1). size’) and end at addresses that are
integer multiples of [page size – 1]. If a
6.2 Page Write Page Write command attempts to write
across a physical page boundary, the
The write control byte, word address and the first data result is that the data wraps around to the
byte are transmitted to the 24C01C in the same way as beginning of the current page (overwriting
in a byte write. But instead of generating a Stop data previously stored there), instead of
condition, the master transmits up to 15 additional data being written to the next page as might be
bytes to the 24C01C which are temporarily stored in expected. It is therefore necessary for the
the on-chip page buffer and will be written into the application software to prevent page write
memory after the master has transmitted a Stop operations that would attempt to cross a
condition. page boundary.

FIGURE 6-1: BYTE WRITE

S S
Bus Activity T Control Word T
Master A Byte Address Data O
R P
T
SDA Line S P

A A A
Bus Activity C C C
K K K

FIGURE 6-2: PAGE WRITE

S
Bus Activity T S
Master A Control Word T
R Byte Address (n) Data n Data n +1 Data n + 15 O
T P
SDA Line S P
A A A A A
Bus Activity C C C C C
K K K K K

 1997-2012 Microchip Technology Inc. DS21201K-page 9

24C01C
7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write Send
command has been issued from the master, the device Write Command
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte Send Stop
for a Write command (R/W = 0). If the device is still Condition to
busy with the write cycle, then no ACK will be returned. Initiate Write Cycle
If no ACK is returned, then the Start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See Send Start
Figure 7-1 for flow diagram.

Send Control Byte

with R/W = 0

Did Device NO
Acknowledge
(ACK = 0)?
YES

Next
Operation

DS21201K-page 10  1997-2012 Microchip Technology Inc.

 24C01C
8.0 READ OPERATION 8.2 Random Read
Read operations are initiated in the same way as write Random read operations allow the master to access
operations with the exception that the R/W bit of the any memory location in a random manner. To perform
slave address is set to one. There are three basic types this type of read operation, first the word address must
of read operations: current address read, random read be set. This is done by sending the word address to the
and sequential read. 24C01C as part of a write operation.
After the word address is sent, the master generates a
8.1 Current Address Read Start condition following the acknowledge. This
terminates the write operation, but not before the
The 24C01C contains an address counter that main-
internal Address Pointer is set. Then the master issues
tains the address of the last word accessed, internally
the control byte again but with the R/W bit set to a one.
incremented by one. Therefore, if the previous read
The 24C01C will then issue an acknowledge and trans-
access was to address n, the next current address read
mits the eight bit data word. The master will not
operation would access data from address n + 1. Upon
acknowledge the transfer, but does generate a Stop
receipt of the slave address with the R/W bit set to one,
condition and the 24C01C discontinues transmission
the 24C01C issues an acknowledge and transmits the
(Figure 8-2). After this command, the internal address
eight-bit data word. The master will not acknowledge
counter will point to the address location following the
the transfer, but does generate a Stop condition and the
one that was just read.
24C01C discontinues transmission (Figure 8-1).

FIGURE 8-1: CURRENT ADDRESS

8.3 Sequential Read
READ Sequential reads are initiated in the same way as a
S
random read except that after the 24C01C transmits
T S the first data byte, the master issues an acknowledge
Bus Activity A Control T
Master R Byte Data O
as opposed to a Stop condition in a random read. This
T P directs the 24C01C to transmit the next sequentially
SDA Line S P addressed 8-bit word (Figure 8-3).
A N To provide sequential reads the 24C01C contains an
Bus Activity C O internal Address Pointer which is incremented by one
K
A at the completion of each operation. This Address
C
K Pointer allows the entire memory contents to be serially
read during one operation. The internal Address
Pointer will automatically roll over from address 7F to
address 00.

FIGURE 8-2: RANDOM READ

S S
T T S
Bus Activity A Control Word A Control T
Master R Byte Address (n) R Byte Data (n) O
T T P
S S P
SDA Line
A A A N
C C C O
K K K
Bus Activity A
C
K
FIGURE 8-3: SEQUENTIAL READ
S
Bus Activity Control T
Master Byte Data n Data n + 1 Data n + 2 Data n + X O
P

SDA Line P
A A A A N
C C C C O
Bus Activity K K K K A
C
K

 1997-2012 Microchip Technology Inc. DS21201K-page 11

24C01C
9.0 PACKAGING INFORMATION

9.1 Package Marking Information

8-Lead PDIP (300 mil) Example:

XXXXXXXX 24C01C
T/XXXNNN I/P e3 13F
YYWW 0527

8-Lead SOIC (3.90 mm) Example:

XXXXXXXT 24C01CI
XXXXYYWW SN e3 0527
NNN 13F

8-Lead TSSOP Example:

XXXX 4C1C
TYWW I527
NNN 13F

8-Lead MSOP Example:

XXXXT 4C1CI
YWWNNN 52713F

8-Lead 2x3 DFN Example:

XXX 2N7
YWW 527
NN 13

8-Lead 2x3 TDFN Example:

XXX AN7
YWW 527
NN 13

DS21201K-page 12  1997-2012 Microchip Technology Inc.

 24C01C

1st Line Marking Codes

Part Number DFN TDFN SOT-23

TSSOP MSOP
I Temp. E Temp. I Temp. E Temp. I Temp. E Temp.
24C01C 4C1C 4C1CT 2N7 2N8 AN7 AN8 HANN HBNN
Note: T = Temperature grade (I, E)

6-Lead SOT-23 Example:

XXNN HAEC

Legend: XX...X Part number or part number code

T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
e3 Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

 1997-2012 Microchip Technology Inc. DS21201K-page 13

24C01C


 
  
  
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DS21201K-page 14  1997-2012 Microchip Technology Inc.

 24C01C

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 1997-2012 Microchip Technology Inc. DS21201K-page 15

24C01C

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS21201K-page 16  1997-2012 Microchip Technology Inc.

 24C01C


  

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 1997-2012 Microchip Technology Inc. DS21201K-page 17

24C01C


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DS21201K-page 18  1997-2012 Microchip Technology Inc.

 24C01C

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 1997-2012 Microchip Technology Inc. DS21201K-page 19

24C01C

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS21201K-page 20  1997-2012 Microchip Technology Inc.

 24C01C

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 1997-2012 Microchip Technology Inc. DS21201K-page 21

24C01C

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS21201K-page 22  1997-2012 Microchip Technology Inc.

 24C01C


 
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 1997-2012 Microchip Technology Inc. DS21201K-page 23

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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS21201K-page 24  1997-2012 Microchip Technology Inc.

 24C01C

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 1997-2012 Microchip Technology Inc. DS21201K-page 25

24C01C

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS21201K-page 26  1997-2012 Microchip Technology Inc.

 24C01C


 
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 1997-2012 Microchip Technology Inc. DS21201K-page 27

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DS21201K-page 28  1997-2012 Microchip Technology Inc.

 24C01C

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 1997-2012 Microchip Technology Inc. DS21201K-page 29

24C01C
APPENDIX A: REVISION HISTORY

Revision A (06/1997)
Initial release.

Revision B (07/1998)

Revision C (08/1999)

Revision D (12/2003)
Corrections to Section 1.0, Electrical Characteristics.

Revision E (04/2005)
Added DFN package.

Revision F (01/2007)
Revised Features Section; Deleted Commercial Temp;
Replaced Package Drawings; Replaced On-Line
Support page; Revised Product ID System.

Revision G (03/2007)
Replaced Package Drawings (Rev. AM).

Revision H (04/2008)
Replaced Package Drawings; Added TDFN package;
Revised Product ID section.

Revision J (08/2008)
Updated Features Section; Added Table 2-1 Pin
Function Table; Corrections to Table 1-1, DC Charac-
teristics; Updated Table 1-2, AC Characteristics;
Updated Package Drawings.

Revision K (03/2012)
Add 6-Lead SOT-23 Package

DS21201K-page 30  1997-2012 Microchip Technology Inc.

 24C01C
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design • Development Systems Information Line
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or field application engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the web site
program member listing at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

 1997-2012 Microchip Technology Inc. DS21201K-page 31

24C01C
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.

TO: Technical Publications Manager Total Pages Sent ________

RE: Reader Response

From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N

Device: 24C01C Literature Number: DS21201K

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21201K-page 32  1997-2012 Microchip Technology Inc.

 24C01C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX
Examples:
Device Temperature Package a) 24C01C-I/P: Industrial Temperature,
Range PDIP Package
b) 24C01C-E/SN: Extended Temperature,
SOIC Package
Device: 24C01C: 1K I2C Serial EEPROM c) 24C01C-I/MNY: Industrial Temperature,
24C01CT:1K I2C Serial EEPROM (Tape and Reel) 2x3 TDFN Package

Temperature I = -40C to +85C

Range: E = -40C to +125C

Package: P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC, (3.90 mm body), 8-lead
ST = Plastic TSSOP (4.4 mm body), 8-lead
OT = Plastic SOT-23, 6-lead (Tape and Reel only)
MS = Plastic MSOP (Micro Small Outline), 8-lead
MC = Plastic DFN (2x3x0.90 mm body), 8-lead
MNY(1)= Plastic TDFN (2x7x0.75 mm body), 8-lead

Note 1: “Y” indicates a Nickel, Palladium, Gold (NiPdAu) finish.

 1997-2012 Microchip Technology Inc. DS21201K-page 33

24C01C
NOTES:

DS21201K-page 34  1997-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT,
devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC,
intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 1997-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.

ISBN: 9781620761632

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
== ISO/TS 16949 == devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 1997-2012 Microchip Technology Inc. DS21201K-page 35

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393
Tel: 480-792-7200 Harbour City, Kowloon Denmark - Copenhagen
India - New Delhi
Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://www.microchip.com/ Fax: 852-2401-3431
India - Pune France - Paris
support
Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20
Web Address:
Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79
www.microchip.com
Fax: 61-2-9868-6755 Germany - Munich
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Santa Clara, CA Tel: 86-27-5980-5300 Tel: 886-2-2500-6610
Tel: 408-961-6444 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102
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Toronto Tel: 86-29-8833-7252 Tel: 66-2-694-1351
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Canada China - Xiamen
Tel: 905-673-0699 Tel: 86-592-2388138
Fax: 905-673-6509 Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
11/29/11
Fax: 86-756-3210049

DS21201K-page 36  1997-2012 Microchip Technology Inc.