24C32

32K 5.0V CMOS Serial EEPROM

FEATURES PACKAGE TYPE

• Voltage operating range: 4.5V to 5.5V PDIP
- Peak write current 3 mA at 5.5V
A0 1 8 VCC
- Maximum read current 150 µA at 5.5V
- Standby current 1 µA typical A1 2 7 NC
• Industry standard two-wire bus protocol, I2C 24C32
A2 3 6 SCL
compatible
- Including 100 kHz and 400 kHz modes VSS 4 5 SDA
• Self-timed write cycle (including auto-erase)
• Power on/off data protection circuitry
SOIC
• Endurance:
- 10,000,000 ERASE/WRITE cycles
A0 1 8 VCC
guaranteed for High Endurance Block
- 100,000 E/W cycles guaranteed for A1 2 7 NC
Standard Endurance Block 24C32
A2 3 6 SCL
• 8 byte page, or byte modes available
• 1 page x 8 line input cache (64 bytes) for fast VSS 4 5 SDA
write loads
• Schmitt trigger, filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page BLOCK DIAGRAM
• Factory programming (QTP) available
• Up to 8 chips may be connected to the same bus A0..A2 HV GENERATOR
for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
I/O MEMORY
• Data retention > 200 years CONTROL CONTROL XDEC EEPROM ARRAY
• 8-pin PDIP/SOIC packages LOGIC LOGIC
• Temperature ranges: PAGE LATCHES
- Commercial: 0˚C to +70˚C I/O
- Industrial: -40˚C to +85˚C SCL
Cache

DESCRIPTION SDA
YDEC
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM. This device has VCC
been developed for advanced, low power applications SENSE AMP
VSS
such as personal communications or data acquisition. R/W CONTROL

The 24C32 features an input cache for fast write loads

with a capacity of eight 8-byte pages, or 64 bytes. It
also features a fixed 4K-bit block of ultra-high endur-
ance memory for data that changes frequently. The
24C32 is capable of both random and sequential reads
up to the 32K boundary. Functional address lines allow
up to 8 - 24C32 devices on the same bus, for up to
256K bits address space. Advanced CMOS technol-
ogy makes this device ideal for low-power non-volatile
code and data applications. The 24C32 is available in
the standard 8-pin plastic DIP and 8-pin surface mount
SOIC package.

I2C is a trademark of Philips Corporation

 1995 Microchip Technology Inc. DS21061E-page 1

24C32
1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PIN FUNCTION TABLE

1.1 Maximum Ratings* Name Function

VCC ........................................................................ 7.0V A0..A2 User Configurable Chip Selects

All inputs and outputs w.r.t. VSS ...... -0.6V to VCC +1.0V VSS Ground
Storage temperature ...........................-65˚C to +150˚C
SDA Serial Address/Data I/O
Ambient temp. with power applied.......-65˚C to +125˚C
SCL Serial Clock
Soldering temperature of leads (10 seconds) ...+300˚C
VCC +4.5V to 5.5V Power Supply
ESD protection on all pins ......................................≥ 4 kV
*Notice: Stresses above those listed under “Maximum Ratings” NC No Internal Connection
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

VCC = +4.5V to +5.5V

Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C

Parameter Symbol Min Max Units Conditions

A0, A1, A2, SCL and SDA pins:

High level input voltage VIH .7 Vcc — V
Low level input voltage VIL — .3 Vcc V
Hysteresis of Schmitt Trigger inputs VHYS .05 Vcc — V Note 1
Low level output voltage VOL — .40 V IOL = 3.0 mA
Input leakage current ILI -10 10 µA VIN = .1V TO VCC
Output leakage current ILO -10 10 µA VOUT = .1V to VCC
Pin capacitance CIN, COUT — 10 pF VCC = 5.0V (Note 1)
(all inputs/outputs) Tamb = 25˚C, Fclk = 1 MHz
Operating current ICC WRITE — 3 mA VCC = 5.5V, SCL = 400 kHz
ICC Read — 150 µA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS — 5 µA VCC = 5.5V, SCL = SDA = VCC
Note 1
Note 1: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1: BUS TIMING START/STOP

VHYS

SCL
T HD:STA
T SU:STA T SU:STO

SDA

START STOP

DS21061E-page 2  1995 Microchip Technology Inc.

 24C32
TABLE 1-3: AC CHARACTERISTICS

VCC = 4.5V - 5.5V VCC = 4.5V - 5.5V

STD. MODE FAST MODE
Parameter Symbol Units Remarks
Min Max Min Max

Clock frequency FCLK — 100 — 400 kHz

Clock high time THIGH 4000 — 600 — ns
Clock low time TLOW 4700 — 1300 — ns
SDA and SCL rise time TR — 1000 — 300 ns Note 1
SDA and SCL fall time TF — 300 — 300 ns Note 1
START condition hold time THD:STA 4000 — 600 — ns After this period the first clock
pulse is generated
START condition setup TSU:STA 4700 — 600 — ns Only relevant for repeated START
time condition
Data input hold time THD:DAT 0 — 0 — ns
Data input setup time TSU:DAT 250 — 100 — ns
STOP condition setup time TSU:STO 4000 — 600 — ns
Output valid from clock TAA — 3500 — 900 ns Note 2
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free before a
new transmission can start
Output fall time from VIH TOF — 250 20 + 0.1 250 ns Note 1, CB ≤ 100 pF
min to VIL max CB
Input filter spike suppres- TSP — 50 — 50 ns Note 3
sion (SDA and SCL pins)
Write cycle time TWR — 5 — 5 ms/page Note 4
Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.
Note 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
Note 4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.

FIGURE 1-2: BUS TIMING DATA

tF tR
t HIGH
t LOW

SCL
t SU:STA tHD:DAT t SU:DAT t SU:STO
t HD:STA
SDA t SP
IN
t BUF
tAA
t AA
SDA
OUT

 1995 Microchip Technology Inc. DS21061E-page 3

24C32
2.0 FUNCTIONAL DESCRIPTION 3.4 Data Valid (D)
The 24C32 supports a bidirectional two-wire bus and The state of the data line represents valid data when,
data transmission protocol. A device that sends data after a START condition, the data line is stable for the
onto the bus is defined as transmitter, and a device duration of the HIGH period of the clock signal.
receiving data as receiver. The bus must be controlled
The data on the line must be changed during the LOW
by a master device which generates the serial clock
period of the clock signal. There is one clock pulse per
(SCL), controls the bus access, and generates the
bit of data.
START and STOP conditions, while the 24C32 works
as slave. Both master and slave can operate as trans- Each data transfer is initiated with a START condition
mitter or receiver but the master device determines and terminated with a STOP condition. The number of
which mode is activated. the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined: 3.5 Acknowledge
• Data transfer may be initiated only when the bus Each receiving device, when addressed, is obliged to
is not busy. generate an acknowledge signal after the reception of
• During data transfer, the data line must remain each byte. The master device must generate an extra
stable whenever the clock line is HIGH. Changes clock pulse which is associated with this acknowledge
in the data line while the clock line is HIGH will be bit.
interpreted as a START or STOP condition.
Note: The 24C32 does not generate any
Accordingly, the following bus conditions have been acknowledge bits if an internal program-
defined (see Figure 3-1). ming cycle is in progress.

3.1 Bus not Busy (A) A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
Both data and clock lines remain HIGH. that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
3.2 Start Data Transfer (B) setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
A HIGH to LOW transition of the SDA line while the slave by NOT generating an acknowledge bit on the
clock (SCL) is HIGH determines a START condition. last byte that has been clocked out of the slave. In this
All commands must be preceded by a START condi- case, the slave (24C32) will leave the data line HIGH to
tion. enable the master to generate the STOP condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

SCL

SDA

START CONDITION ADDRESS DATA ALLOWED STOP

OR TO CHANGE CONDITION
ACKNOWLEDGE
VALID

DS21061E-page 4  1995 Microchip Technology Inc.

 24C32
4.0 BUS CHARACTERISTICS slave device outputs an acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
4.1 Device Addressing and Operation 24C32 will select a read or write operation.
(Figure 4-1)
Control
Operation Device Select R/W
A control byte is the first byte received following the Code
start condition from the master device. The control
byte consists of a four bit control code; for the 24C32 Read 1010 Device Address 1
this is set as 1010 binary for read and write operations. Write 1010 Device Address 0
The next three bits of the control byte are the device
select bits (A2, A1, A0). They are used by the master FIGURE 4-1: CONTROL BYTE
device to select which of the eight devices are to be ALLOCATION
accessed. These bits are in effect the three most sig-
nificant bits of the word address. The last bit of the con-
trol byte (R/W) defines the operation to be performed. START READ/WRITE
When set to a one a read operation is selected, and
when set to a zero a write operation is selected. The
SLAVE ADDRESS R/W A
next two bytes received define the address of the first
data byte (see Figure 4-2). Because only A11..A0 are
used, the upper four address bits must be zeros. The
most significant bit of the most significant byte of the
address is transferred first. Following the start condi- 1 0 1 0 A2 A1 A0
tion, the 24C32 monitors the SDA bus checking the
device type identifier being transmitted. Upon receiv-
ing a 1010 code and appropriate device select bits, the

FIGURE 4-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

Control Byte Address Byte 1 Address Byte 0

A A
1 0 1 0 A A A R/W 0 0 0 0 A A A A 7 • • • • • • 0
2 1 0 11 10 9 8

Slave Device
Address Select
Bits

 1995 Microchip Technology Inc. DS21061E-page 5

24C32
4.2 WRITE OPERATION tion. This initiates the internal write cycle, and during
this time the 24C32 will not generate acknowledge sig-
4.3 Split Endurance nals (see Figure 4-3).

The 24C32 is organized as a continuous 32K block of 4.5 Page Write

memory. However, the first 4K, starting at address 000,
is rated at 10,000,000 E/W cycles guaranteed. The The write control byte, word address and the first data
remainder of the array, 28K bits, is rated at 100K E/W byte are transmitted to the 24C32 in the same way as
cycles guaranteed. This feature is helpful in applica- in a byte write. But instead of generating a stop condi-
tions in which some data change frequently, while a tion, the master transmits up to eight pages of eight
majority of the data change infrequently. One example data bytes each (64 bytes total) which are temporarily
would be a cellular telephone in which last-number stored in the on-chip page cache of the 24C32. They
redial and microcontroller scratch pad require a high- will be written from cache into the EEPROM array after
endurance block, while speed dials and lookup tables the master has transmitted a stop condition. After the
change infrequently and so require only a standard receipt of each word, the six lower order address
endurance rating. pointer bits are internally incremented by one. The
higher order seven bits of the word address remain
4.4 Byte Write constant. If the master should transmit more than eight
bytes prior to generating the stop condition (writing
Following the start condition from the master, the con- across a page boundary), the address counter (lower
trol code (four bits), the device select (three bits), and three bits) will roll over and the pointer will be incre-
the R/W bit which is a logic low are clocked onto the mented to point to the next line in the cache. This can
bus by the master transmitter. This indicates to the continue to occur up to eight times or until the cache is
addressed slave receiver that a byte with a word full, at which time a stop condition should be generated
address will follow after it has generated an acknowl- by the master. If a stop condition is not received, the
edge bit during the ninth clock cycle. Therefore the cache pointer will roll over to the first line (byte 0) of the
next byte transmitted by the master is the high-order cache, and any further data received will overwrite pre-
byte of the word address and will be written into the viously captured data. The stop condition can be sent
address pointer of the 24C32. The next byte is the at any time during the transfer. As with the byte write
least significant address byte. After receiving another operation, once a stop condition is received, an internal
acknowledge signal from the 24C32 the master device write cycle will begin. The 64-byte cache will continue
will transmit the data word to be written into the to capture data until a stop condition occurs or the
addressed memory location. The 24C32 acknowl- operation is aborted (see Figure 4-4).
edges again and the master generates a stop condi-

FIGURE 4-3: BYTE WRITE

S
t S
Bus Activity: a Control Word Word t
Master r Byte Address (1) Address (0) Data o
t p
SDA Line 0000
Bus Activity A A A A
C C C C
K K K K

FIGURE 4-4: PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 6-3)

S
T S
BUS A CONTROL WORD WORD T
ACTIVITY: R BYTE ADDRESS (1) ADDRESS (0) DATA n DATA n + 7
O
MASTER T P

SDA LINE 0 0 0 0

A A A A A
BUS C C C C C
ACTIVITY: K K K K K

DS21061E-page 6  1995 Microchip Technology Inc.

 24C32
5.0 ACKNOWLEDGE POLLING 6.0 READ OPERATION
Since the device will not acknowledge during a write Read operations are initiated in the same way as write
cycle, this can be used to determine when the cycle is operations with the exception that the R/W bit of the
complete (this feature can be used to maximize bus slave address is set to one. There are three basic
throughput). Once the stop condition for a write com- types of read operations: current address read, random
mand has been issued from the master, the device ini- read, and sequential read.
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master 6.1 Current Address Read
sending a start condition followed by the control byte
The 24C32 contains an address counter that maintains
for a write command (R/W = 0). If the device is still
the address of the last word accessed, internally incre-
busy with the write cycle, then no ACK will be returned.
mented by one. Therefore, if the previous access
If the cycle is complete, then the device will return the
(either a read or write operation) was to address n (n is
ACK and the master can then proceed with the next
any legal address), the next current address read oper-
read or write command. See Figure 5-1 for flow dia-
ation would access data from address n + 1. Upon
gram
receipt of the slave address with R/W bit set to one, the
FIGURE 5-1: ACKNOWLEDGE POLLING 24C32 issues an acknowledge and transmits the eight
FLOW bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
Send 24C32 discontinues transmission (see Figure 6-1).
Write Command
6.2 Random Read

Send Stop
Random read operations allow the master to access
Condition to any memory location in a random manner. To perform
Initiate Write Cycle this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C32 as part of a write operation (R/W bit set to 0).
Send Start After the word address is sent, the master generates a
start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then the master issues the con-
Send Control Byte trol byte again but with the R/W bit set to a one. The
with R/W = 0
24C32 will then issue an acknowledge and transmit the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
Did Device No causes the 24C32 to discontinue transmission (see
Acknowledge
(ACK = 0)? Figure 6-2).

Yes

Next
Operation

FIGURE 6-1: CURRENT ADDRESS READ

S
T S
A CONTROL T
BUS ACTIVITY R BYTE DATA n O
MASTER T P

SDA LINE

A N
BUS ACTIVITY C O
K
A
C
K

 1995 Microchip Technology Inc. DS21061E-page 7

24C32
6.3 Contiguous Addressing Across To provide sequential reads the 24C32 contains an
Multiple Devices internal address pointer which is incremented by one at
the completion of each operation. This address pointer
The device select bits A2, A1, A0 can be used to allows the entire memory contents to be serially read
expand the contiguous address space for up to 256K during one operation. The address pointer, however,
bits by adding up to eight 24C32's on the same bus. In will not roll over from address 07FF to address 0000. It
this case, software can use A0 of the control byte as will roll from 07FF to unused memory space.
address bit A12, A1 as address bit A13, and A2 as
address bit A14. 6.5 Noise Protection

6.4 Sequential Read The SCL and SDA inputs have filter circuits which sup-
press noise spikes to ensure proper device operation
Sequential reads are initiated in the same way as a ran- even on a noisy bus. All I/O lines incorporate Schmitt
dom read except that after the 24C32 transmits the first triggers for 400 kHz (Fast Mode) compatibility.
data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24C32 to transmit the
next sequentially addressed 8 bit word. (See Figure 6-
3). Following the final byte transmitted to the master,
the master will NOT generate an acknowledge but will
generate a stop condition.

FIGURE 6-2: RANDOM READ

S S
T T S
A CONTROL WORD WORD A CONTROL T
BYTE ADDRESS (1) ADDRESS (0) R BYTE DATA n
R T O
T P

SDA LINE 0 0 0 0

A A A A N
BUS C C C C O
ACTIVITY: K K K K
A
C
K

FIGURE 6-3: SEQUENTIAL READ

S
t
Data n Data n + 1 Data n + 2 Data n + X o
Bus Activity: Control
Master Byte p
SDA Line
Bus Activity A A A A N
C C C C O
K K K K
A
C
K

DS21061E-page 8  1995 Microchip Technology Inc.

 24C32
7.0 PAGE CACHE AND ARRAY loaded into the cache will 'roll over' and be loaded into
the first two bytes of page 0 (of the cache). When the
MAPPING stop bit is sent, page 0 of the cache is written to page 3
The cache is a 64 byte (8 pages x 8 bytes) FIFO buffer. of the array. The remaining pages in the cache are
The cache allows the loading of up to 64 bytes of data then loaded sequentially to the array. A write cycle is
before the write cycle is actually begun, effectively pro- executed after each page is written. If a partially
viding a 64-byte burst write at the maximum bus rate. loaded page in the cache remains when the STOP bit
Whenever a write command is initiated, the cache is sent, only the bytes that have been loaded will be
starts loading and will continue to load until a stop bit is written to the array.
received to start the internal write cycle. The total
length of the write cycle will depend on how many 7.3 Power Management
pages are loaded into the cache before the stop bit is
given. Maximum cycle time for each page is 5 ms. This design incorporates a power standby mode when
Even if a page is only partially loaded, it will still require the device is not in use and automatically powers off
the same cycle time as a full page. If more than 64 after the normal termination of any operation when a
bytes of data are loaded before the stop bit is given, the stop bit is received and all internal functions are com-
address pointer will 'wrap around' to the beginning of plete. This includes any error conditions, ie. not receiv-
cache page 0 and existing bytes in the cache will be ing an acknowledge or stop condition per the two-wire
overwritten. The device will not respond to any com- bus specification. The device also incorporates VDD
mands while the write cycle is in progress. monitor circuitry to prevent inadvertent writes (data cor-
ruption) during low-voltage conditions. The VDD moni-
7.1 Cache Write Starting at a Page tor circuitry is powered off when the device is in
Boundary standby mode in order to further reduce power con-
sumption.
If a write command begins at a page boundary
(address bits A2, A1 and A0 are zero), then all data
8.0 PIN DESCRIPTIONS
loaded into the cache will be written to the array in
8.1 A0, A1, A2 Chip Address Inputs
sequential addresses. This includes writing across a
4K block boundary. In the example shown below, (see The A0..A2 inputs are used by the 24C32 for multiple
Figure 8-1) a write command is initiated starting at byte device operation and conform to the two-wire bus stan-
0 of page 3 with a fully loaded cache (64 bytes). The dard. The levels applied to these pins define the
first byte in the cache is written to byte 0 of page 3 (of address block occupied by the device in the address
the array), with the remaining pages in the cache writ- map. A particular device is selected by transmitting the
ten to sequential pages in the array. A write cycle is corresponding bits (A2, A1, A0) in the control byte (see
executed after each page is written. Since the write Figure 4-2).
begins at page 3 and 8 pages are loaded into the
cache, the last 3 pages of the cache are written to the 8.2 SDA Serial Address/Data Input/Output
next row in the array.
This is a bidirectional pin used to transfer addresses
7.2 Cache Write Starting at a Non-Page and data into and data out of the device. It is an open
Boundary drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400
When a write command is initiated that does not begin kHz).
at a page boundary (i.e., address bits A2, A1 and A0
For normal data transfer SDA is allowed to change only
are not all zero), it is important to note how the data is
during SCL low. Changes during SCL high are
loaded into the cache, and how the data in the cache is
reserved for indicating the START and STOP condi-
written to the array. When a write command begins,
tions.
the first byte loaded into the cache is always loaded
into page 0. The byte within page 0 of the cache where 8.3 SCL Serial Clock
the load begins is determined by the three least signif-
icant address bits (A2, A1, A0) that were sent as part of This input is used to synchronize the data transfer from
the write command. If the write command does not and to the device.
start at byte 0 of a page and the cache is fully loaded,
then the last byte(s) loaded into the cache will roll
around to page 0 of the cache and fill the remaining
empty bytes. If more than 64 bytes of data are loaded
into the cache, data already loaded will be overwritten.
In the example shown in Figure 8-2, a write command
has been initiated starting at byte 2 of page 3 in the
array with a fully loaded cache of 64 bytes. Since the
cache started loading at byte 2, the last two bytes

 1995 Microchip Technology Inc. DS21061E-page 9

24C32
FIGURE 8-1: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY

1 Write command initiated at byte 0 of page 3 in the array;

First data byte is loaded into the cache byte 0. 2 64 bytes of data are loaded into cache.

cache page 0

cache cache cache cache page 1 cache page 2 cache page 7

• • • • • •
byte 0 byte 1 byte 7 bytes 8-15 bytes 16-23 bytes 56-63

3 Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array. 4 Remaining pages in cache are written
Write cycle is executed after every page is written. to sequential pages in array.

page 0 page 1 page 2 byte 0 byte 1 • • • byte 7 page 4 • • • page 7 array row n
page 0 page 1 page 2 page 3 page 4 • • • page 7 array row n + 1

5 Last page in cache written to page 2 in next row.

FIGURE 8-2: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY

1 Write command initiated; 64 bytes of data 2 Last 2 bytes loaded 'roll over'
loaded into cache starting at byte 2 of page 0. to beginning.
Last 2 bytes 3
loaded into
page 0 of cache. cache cache cache cache cache page 1 cache page 2 cache page 7
• • • • • •
byte 0 byte 1 byte 2 byte 7 bytes 8-15 bytes 16-23 bytes 56-63

4 Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array. 5 Remaining bytes in cache are
Write cycle is executed after every page is written. written sequentially to array.

page 0 page 1 page 2 byte 0 byte 1 byte 2 byte 3 byte 4 • • • byte 7 page 4 • • • page 7 array
row n
page 0 page 1 page 2 page 3 page 4 • • • page 7 array
row
n+1
6 Last 3 pages in cache written to next row in array.

DS21061E-page 10  1995 Microchip Technology Inc.

 24C32
NOTES

 1995 Microchip Technology Inc. DS21061E-page 11

24C32
24C32 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

24C32 - /P

Package: P = Plastic DIP (300 mil Body), 8-lead

SM = Plastic SOIC (207 mil Body, EIAJ standard)

Temperature Blank = 0°C to +70°C

Range: I = -40°C to +85°C

Device: 24C32 32K CMOS Serial EEPROM (100 kHz/400 kHz)

24C32T 32K CMOS Serial EEPROM (Tape and Reel)

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Tel: 708 285-0071 Fax: 708 285-0075 Agrate Brianza (MI) Italy
200 Middle Road Tel: 39 039 689 9939 Fax: 39 039 689 9883
Dallas #10-03 Prime Centre
Microchip Technology Inc. Singapore 188980 JAPAN
14651 Dallas Parkway, Suite 816 Tel: 65 334 8870 Fax: 65 334 8850 Microchip Technology Intl. Inc.
Dallas, TX 75240-8809 Taiwan Benex S-1 6F
Tel: 214 991-7177 Fax: 214 991-8588 Microchip Technology 3-18-20, Shin Yokohama
Dayton 10F-1C 207 Kohoku-Ku, Yokohama
Microchip Technology Inc. Tung Hua North Road Kanagawa 222 Japan
35 Rockridge Road Taipei, Taiwan, ROC Tel: 81 45 471 6166 Fax: 81 45 471 6122
Englewood, OH 45322 Tel: 886 2 717 7175 Fax: 886 2 545 0139
Tel: 513 832-2543 Fax: 513 832-2841 9/5/95
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 455
Irvine, CA 92715
Tel: 714 263-1888 Fax: 714 263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788 Printed in the USA, 9/95
Tel: 516 273-5305 Fax: 516 273-5335  1995, Microchip Technology Incorporated

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DS21061E-page 12  1995 Microchip Technology Inc.