24C02C

2K 5.0V I2C™ Serial EEPROM

Features: Description:
• Single-Supply with Operation from 4.5V to 5.5V The Microchip Technology Inc. 24C02C is a 2K bit
• Low-Power CMOS Technology: Serial Electrically Erasable PROM with a voltage range
- Read current 1 mA, max. of 4.5V to 5.5V. The device is organized as a single
block of 256 x 8-bit memory with a 2-wire serial
- Standby current 5 μA, max.
interface. Low-current design permits operation with
• 2-Wire Serial Interface, I2C™ Compatible max. standby and active currents of only 5 μA and 1
• Cascadable up to Eight Devices mA, respectively. The device has a page write capabil-
• Schmitt Trigger Inputs for Noise Suppression ity for up to 16 bytes of data and has fast write cycle
• Output Slope Control to Eliminate Ground Bounce times of only 1 ms for both byte and page writes.
Functional address lines allow the connection of up to
• 100 kHz and 400 kHz Clock Compatibility
eight 24C02C devices on the same bus for up to 16K
• Fast Page or Byte Write Time 1 ms, typical bits of contiguous EEPROM memory. The device is
• Self-Timed Erase/Write Cycle available in the standard 8-pin PDIP, 8-pin SOIC (3.90
• 16-Byte Page Write Buffer mm), 8-pin 2x3 DFN and TDFN, 8-pin MSOP and
• Hardware Write-Protect for Upper Half of the TSSOP packages.
Array (80h-FFh)
• ESD Protection >4,000V Block Diagram
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years A0 A1 A2 WP
HV Generator
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC, TSSOP,
I/O Memory
DFN, TDFN and MSOP Control Control
Logic EEPROM
• Pb-Free and RoHS Compliant Logic XDEC
Array
• Temperature ranges:
- Industrial (I): -40°C to +85°C
SDA SCL
- Automotive (E): -40°C to +125°C
Write-Protect
Vcc Circuitry
YDEC
Vss

Sense Amp.
R/W Control

Package Types
PDIP, MSOP SOIC, TSSOP DFN/TDFN

A0 1 8 VCC 1 8 A0 1 8 VCC
A0 VCC
A1 2 7 WP
A1 2 7 WP A1 2 7 WP
A2 3 6 SCL
A2 3 6 SCL A2 3 6 SCL VSS 4 5 SDA

VSS 4 5 SDA VSS 4 5 SDA

© 2008 Microchip Technology Inc. DS21202J-page 1

24C02C
1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC .............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

Electrical Characteristics:
DC CHARACTERISTICS Industrial (I): VCC = +4.5V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +4.5V to 5.5V TA = -40°C to +125°C
Param.
Sym. Characteristic Min. Max. Units Conditions
No.
D1 — A0, A1, A2, SCL, SDA — — — —
and WP pins:
D2 VIH High-level input voltage 0.7 VCC — V —
D3 VIL Low-level input voltage — 0.3 VCC V —
D4 VHYS Hysteresis of Schmitt 0.05 VCC — V (Note)
Trigger inputs
(SDA, SCL pins)
D5 VOL Low-level output voltage — 0.40 V IOL = 3.0 ma @ VCC = 4.5V
D6 ILI Input leakage current — ±1 μA VIN = VSS or VCC, WP = VSS
D7 ILO Output leakage current — ±1 μA VOUT = VSS or VCC
D8 CIN, Pin capacitance — 10 pF VCC = 5.0V (Note)
COUT (all inputs/outputs) TA = 25°C, f = 1 MHz
D9 ICC Read Operating current — 1 mA VCC = 5.5V, SCL = 400 kHz
ICC Write — 3 mA VCC = 5.5V
D10 ICCS Standby current — 5 μA VCC = 5.5VSCL = SDA = VCC
WP = VSS
Note: This parameter is periodically sampled and not 100% tested.

DS21202J-page 2 © 2008 Microchip Technology Inc.

 24C02C
TABLE 1-2: AC CHARACTERISTICS
Electrical Characteristics:
AC CHARACTERISTICS Industrial (I): VCC = +4.5V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +4.5V to 5.5V TA = -40°C to +125°C
Param.
Sym. Characteristic Min. Max. Units Conditions
No.
1 FCLK Clock frequency — 100 kHz —
— 400 (I-temp)
2 THIGH Clock high time 4000 — ns —
600 — (I-temp)
3 TLOW Clock low time 4700 — ns —
1300 — (I-temp)
4 TR SDA and SCL rise time — 1000 ns —
(Note 1) — 300 (I-temp)
5 TF SDA and SCL fall time — 300 ns —
(Note 1) (I-temp)
6 THD:STA Start condition hold time 4000 — ns —
600 — (I-temp)
7 TSU:STA Start condition setup time 4700 — ns —
600 — (I-temp)
8 THD:DAT Data input hold time 0 — ns (Note 2)
9 TSU:DAT Data input setup time 250 — ns —
100 — (I-temp)
10 TSU:STO Stop condition setup time 4000 — ns —
600 — (I-temp)
11 TAA Output valid from clock — 3500 ns —
(Note 2) — 900 (I-temp)
12 TBUF Bus free time: Time the bus 4700 — ns —
must be free before a new 1300 — (I-temp)
transmission can start
13 TOF Output fall time from VIH 10 + 0.1CB 250 ns (Note 1)
minimum to VIL maximum
CB ≤ 100 pF
14 TSP Input filter spike suppression — 50 ns (Note 3)
(SDA and SCL pins)
15 TWC Write cycle time (byte or — 1.5 ms —
page) 1 (I-temp)
16 — Endurance 1,000,000 — cycles 25°C (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide
improved noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.

© 2008 Microchip Technology Inc. DS21202J-page 3

24C02C
FIGURE 1-1: BUS TIMING DATA

5 4
2 D4

SCL
7
3 8 9 10
SDA
6
IN
14

11 12
SDA
OUT

DS21202J-page 4 © 2008 Microchip Technology Inc.

 24C02C
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Name PDIP SOIC TSSOP DFN/TDFN MSOP Function
A0 1 1 1 1 1 Address Pin A0
A1 2 2 2 2 2 Address Pin A1
A2 3 3 3 3 3 Address Pin A2
VSS 4 4 4 4 4 Ground
SDA 5 5 5 5 5 Serial Address/Data I/O
SCL 6 6 6 6 6 Serial Clock
WP 7 7 7 7 7 Write-Protect Input
VCC 8 8 8 8 8 +4.5 V to 5.5 V Power Supply

2.1 SDA Serial Data

This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal; therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.

2.2 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

2.3 A0, A1, A2

The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C02C devices may be connected to the
same bus by using different Chip Select bit combina-
tions. These inputs must be connected to either VCC or
VSS.

2.4 WP
This is the hardware write-protect pin. It must be tied to
VCC or VSS. If tied to Vcc, the hardware write protection
is enabled. If the WP pin is tied to VSS the hardware
write protection is disabled.

2.5 Noise Protection

The 24C02C employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 3.8 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.

© 2008 Microchip Technology Inc. DS21202J-page 5

24C02C
3.0 FUNCTIONAL DESCRIPTIONS 4.4 Data Valid (D)
The 24C02C supports a bidirectional 2-wire bus and The state of the data line represents valid data when,
data transmission protocol. A device that sends data after a Start condition, the data line is stable for the
onto the bus is defined as transmitter, and a device duration of the high period of the clock signal.
receiving data as receiver. The bus has to be controlled The data on the line must be changed during the low
by a master device that generates the Serial Clock period of the clock signal. There is one bit of data per
(SCL), controls the bus access, and generates the Start clock pulse.
and Stop conditions, while the 24C02C works as slave.
Both master and slave can operate as transmitter or Each data transfer is initiated with a Start condition and
receiver but the master device determines which mode terminated with a Stop condition. The number of the
is activated. data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
4.0 BUS CHARACTERISTICS will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first-in first-
The following bus protocol has been defined:
out fashion.
• Data transfer may be initiated only when the bus
is not busy. 4.5 Acknowledge
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in Each receiving device, when addressed, is required to
the data line while the clock line is high will be generate an acknowledge after the reception of each
interpreted as a Start or Stop condition. byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
Accordingly, the following bus conditions have been
defined (Figure 4-1). Note: The 24C02C does not generate any
Acknowledge bits if an internal
4.1 Bus Not Busy (A) programming cycle is in progress.
The device that acknowledges has to pull down the
Both data and clock lines remain high.
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
4.2 Start Data Transfer (B) period of the acknowledge related clock pulse. Of
A high-to-low transition of the SDA line while the clock course, setup and hold times must be taken into
(SCL) is high determines a Start condition. All account. A master must signal an end of data to the
commands must be preceded by a Start condition. slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
4.3 Stop Data Transfer (C)
the master to generate the Stop condition (Figure 4-2).
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All opera-
tions must be ended with a Stop condition.

DS21202J-page 6 © 2008 Microchip Technology Inc.

 24C02C
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (C) (D) (C) (A)

SCL

SDA

Start Address or Data Stop

Condition Acknowledge Allowed Condition
Valid to Change

FIGURE 4-2: ACKNOWLEDGE TIMING

Acknowledge
Bit

SCL 1 2 3 4 5 6 7 8 9 1 2 3

SDA Data from transmitter Data from transmitter

Transmitter must release the SDA line at this point Receiver must release the SDA line at this point
allowing the Receiver to pull the SDA line low to so the Transmitter can continue sending data.
acknowledge the previous eight bits of data.

© 2008 Microchip Technology Inc. DS21202J-page 7

24C02C
5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE FORMAT
Read/Write Bit
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a four-bit control code; for Chip Select
Control Code Bits
the 24C02C this is set as ‘1010’ binary for read and
write operations. The next three bits of the control byte
are the Chip Select bits (A2, A1, A0). The Chip Select S 1 0 1 0 A2 A1 A0 R/W ACK
bits allow the use of up to eight 24C02C devices on the
same bus and are used to select which device is Slave Address
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2, Start Bit Acknowledge Bit
A1 and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address. 5.1 Contiguous Addressing Across
The last bit of the control byte defines the operation to Multiple Devices
be performed. When set to a ‘1’ a read operation is The Chip Select bits A2, A1, A0 can be used to expand
selected, and when set to a ‘0’ a write operation is the contiguous address space for up to 16K bits by
selected. Following the Start condition, the 24C02C adding up to eight 24C02C devices on the same bus.
monitors the SDA bus checking the control byte being In this case, software can use A0 of the control byte
transmitted. Upon receiving a ‘1010’ code and appro- as address bit A9, A1 as address bit A10, and A2 as
priate Chip Select bits, the slave device outputs an address bit A11. It is not possible to write or read across
Acknowledge signal on the SDA line. Depending on the device boundaries.
state of the R/W bit, the 24C02C will select a read or
write operation.

DS21202J-page 8 © 2008 Microchip Technology Inc.

 24C02C
6.0 WRITE OPERATIONS As with the byte write operation, once the Stop
condition is received an internal write cycle will begin
6.1 Byte Write (Figure 6-2). If an attempt is made to write to the
protected portion of the array when the hardware write
Following the Start signal from the master, the device protection has been enabled, the device will acknowl-
code (4 bits), the Chip Select bits (3 bits) and the R/W edge the command, but no data will be written. The
bit, which is a logic low, is placed onto the bus by the write cycle time must be observed even if the write
master transmitter. The device will acknowledge this protection is enabled.
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will Note: Page write operations are limited to writing
be written into the Address Pointer of the 24C02C. bytes within a single physical page,
After receiving another Acknowledge signal from the regardless of the number of bytes
24C02C the master device will transmit the data word actually being written. Physical page
to be written into the addressed memory location. The boundaries start at addresses that are
24C02C acknowledges again and the master gener- integer multiples of the page buffer size (or
ates a Stop condition. This initiates the internal write ‘page size’) and end at addresses that are
cycle, and during this time the 24C02C will not gener- integer multiples of [page size – 1]. If a
ate Acknowledge signals (Figure 6-1). If an attempt is Page Write command attempts to write
made to write to the protected portion of the array when across a physical page boundary, the
the hardware write protection has been enabled, the result is that the data wraps around to the
device will acknowledge the command but no data will beginning of the current page (overwriting
be written. The write cycle time must be observed even data previously stored there), instead of
if the write protection is enabled. being written to the next page as might be
expected. It is therefore necessary for the
6.2 Page Write application software to prevent page write
operations that would attempt to cross a
The write control byte, word address and the first data page boundary.
byte are transmitted to the 24C02C in the same way as
in a byte write. But instead of generating a Stop 6.3 Write Protection
condition, the master transmits up to 15 additional data
bytes to the 24C02C which are temporarily stored in The WP pin must be tied to VCC or VSS. If tied to VCC,
the on-chip page buffer and will be written into the the upper half of the array (080-0FF) will be write-
memory after the master has transmitted a Stop protected. If the WP pin is tied to VSS, then write
condition. After the receipt of each word, the four lower operations to all address locations are allowed.
order Address Pointer bits are internally incremented
by one. The higher order four bits of the word address
remains constant. If the master should transmit more
than 16 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten.

FIGURE 6-1: BYTE WRITE

S S
Bus Activity T Control Word T
Master A Byte Address Data O
R P
T
SDA Line S P

A A A
Bus Activity C C C
K K K

FIGURE 6-2: PAGE WRITE

S
Bus Activity T S
Master A Control Word T
R Byte Address (n) Data n Data n +1 Data n + 15 O
T P
SDA Line S P
A A A A A
Bus Activity C C C C C
K K K K K

© 2008 Microchip Technology Inc. DS21202J-page 9

24C02C
7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus Send
throughput). Once the Stop condition for a Write Write Command
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master Send Stop
sending a Start condition followed by the control byte Condition to
for a Write command (R/W = 0). If the device is still Initiate Write Cycle
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be re-sent. If the cycle is complete, then the
Send Start
device will return the ACK and the master can then
proceed with the next Read or Write command. See
Figure 7-1 for flow diagram.
Send Control Byte
with R/W = 0

Did Device No
Acknowledge
(ACK = 0)?

Yes

Next
Operation

DS21202J-page 10 © 2008 Microchip Technology Inc.

 24C02C
8.0 READ OPERATION 8.2 Random Read
Read operations are initiated in the same way as write Random read operations allow the master to access
operations with the exception that the R/W bit of the any memory location in a random manner. To perform
slave address is set to one. There are three basic types this type of read operation, first the word address must
of read operations: current address read, random read, be set. This is done by sending the word address to the
and sequential read. 24C02C as part of a write operation. After the word
address is sent, the master generates a Start condition
8.1 Current Address Read following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
The 24C02C contains an address counter that main- set. Then the master issues the control byte again but
tains the address of the last word accessed, internally with the R/W bit set to a one. The 24C02C will then
incremented by one. Therefore, if the previous read issue an acknowledge and transmits the eight bit data
access was to address n, the next current address read word. The master will not acknowledge the transfer but
operation would access data from address n + 1. Upon does generate a Stop condition and the 24C02C
receipt of the slave address with the R/W bit set to one, discontinues transmission (Figure 8-2). After this
the 24C02C issues an acknowledge and transmits the command, the internal address counter will point to the
eight bit data word. The master will not acknowledge address location following the one that was just read.
the transfer, but does generate a Stop condition and the
24C02C discontinues transmission (Figure 8-1). 8.3 Sequential Read
FIGURE 8-1: CURRENT ADDRESS Sequential reads are initiated in the same way as a
READ random read except that after the 24C02C transmits
the first data byte, the master issues an acknowledge
S as opposed to a Stop condition in a random read. This
T S
Bus Activity A Control T directs the 24C02C to transmit the next sequentially
Master Byte Data
R O addressed 8-bit word (Figure 8-3).
T P
SDA line S P To provide sequential reads, the 24C02C contains an
A
internal Address Pointer which is incremented by one
N
Bus Activity C O at the completion of each operation. This Address
K Pointer allows the entire memory contents to be serially
A
C read during one operation. The internal Address
K
Pointer will automatically roll over from address FF to
address 00.

FIGURE 8-2: RANDOM READ

S S
T T S
Bus Activity A Control Word A Control T
Master R Byte Address (n) R Byte Data (n) O
T T P
S S P
SDA line
A A A N
C C C O
K K K
Bus Activity A
C
K

FIGURE 8-3: SEQUENTIAL READ

S
Bus Activity T
Master Control
Byte Data n Data n + 1 Data n + 2 Data n + X O
P

SDA line P
A A A A N
C C C C O
Bus Activity K K K K A
C
K

© 2008 Microchip Technology Inc. DS21202J-page 11

24C02C
9.0 PACKAGING INFORMATION

9.1 Package Marking Information

8-Lead PDIP (300 mil) Example:

XXXXXXXX 24C02C
T/XXXNNN I/P e3 13F
YYWW 0527

8-Lead SOIC (3.90 mm) Example:

XXXXXXXT 24C02CI
XXXXYYWW SN e3 0527
NNN 13F

8-Lead TSSOP Example:

XXXX 4C2C
TYWW I527
NNN 13F

8-Lead MSOP Example:

XXXXT 4C2CI
YWWNNN 52713F

8-Lead 2x3 DFN Example:

XXX 2P7
YWW 527
NN 13

8-Lead 2x3 TDFN Example:

XXX AP7
YWW 527
NN 13

DS21202J-page 12 © 2008 Microchip Technology Inc.

 24C02C

1st Line Marking Codes

Part Number DFN TDFN

TSSOP MSOP
I Temp. E Temp. I Temp. E Temp.
24C02C 4C2C 4C2CT 2P7 2P8 AP7 AP8
Note: T = Temperature grade (I, E)

Legend: XX...X Part number or part number code

T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
e3 Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

© 2008 Microchip Technology Inc. DS21202J-page 13

24C02C


 
  
  
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© 2008 Microchip Technology Inc. DS21202J-page 15

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DS21202J-page 22 © 2008 Microchip Technology Inc.

 24C02C
APPENDIX A: REVISION HISTORY

Revision D
Corrections to Section 1.0, Electrical Characteristics.

Revision E
Added DFN package.

Revision F (02/2007)
Revised Features section; Section 1.0 revised Ambient
temperature; Revised Tables 1-1, 1-2, (removed com-
mercial temp); Revised Table 2-1; Replaced On-line
Support page; Replaced Package Drawings; Revised
Product ID section.

Revision G (03/2007)
Replaced Package Drawings (Rev. AM).

Revision H (04/2008)
Replaced Package Drawings; Added TDFN package;
Revised Product ID section.

Revision J (08/2008)
Corrections to Table 1-1, DC Characteristics; Updated
Table 1-2, AC Characteristics; Revised Figure 1-1;
Updated Package Drawings.

© 2008 Microchip Technology Inc. DS21202J-page 23

24C02C
NOTES:

DS21202J-page 24 © 2008 Microchip Technology Inc.

 24C02C
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design • Development Systems Information Line
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or field application engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the web site
program member listing at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.

© 2008 Microchip Technology Inc. DS21202J-page 25

24C02C
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager Total Pages Sent ________

RE: Reader Response

From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N

Device: 24C02C Literature Number: DS21202J

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21202J-page 26 © 2008 Microchip Technology Inc.

 24C02C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX
Examples:
Device Temperature Package a) 24C02C-I/P: Industrial Temperature,
Range PDIP Package
b) 24C02C-E/SN: Extended Temperature,
SOIC Package
Device: 24C02C: 2K I2C™ Serial EEPROM
24C02CT: 2K I2C™ Serial EEPROM (Tape and Reel)
c) 24C02C-I/MNY: Industrial Temperature,
2x3 TDFN Package

Temperature I = -40°C to +85°C

Range: E = -40°C to +125°C

Package: P =
Plastic DIP (300 mil Body), 8-lead
SN =
Plastic SOIC, (3.90 mm Body), 8-lead
ST =
TSSOP (4.4 mm Body), 8-lead
MS =
Plastic Micro Small Outline (MSOP), 8-lead
MC =
Plastic Dual Flat (DFN), No lead package,
2x3 mm body, 8-lead
MNY(1) = Plastic Dual Flat (TDFN), No lead package,
2x3 mm body, 8-lead

Note 1: “Y” indicates a Nickel, Palladium, Gold (NiPdAu) finish.

© 2008 Microchip Technology Inc. DS21202J-page 27

24C02C
NOTES:

DS21202J-page 28 © 2008 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, rfPIC and SmartShunt are registered trademarks
MICROCHIP MAKES NO REPRESENTATIONS OR
of Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

© 2008 Microchip Technology Inc. DS21202J-page 29

 WORLDWIDE SALES AND SERVICE
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Fax: 86-756-3210049

01/02/08

DS21202J-page 30 © 2008 Microchip Technology Inc.