INDEX
❖ DAY-1: Basic Logic Gates implementation using NAND (universal
gate).
❖ DAY-2: Basic Logic Gates implementation using NOR (universal gate).
❖ DAY-3: Random Boolean expression(ABC+A`C`+D) Implementation
using Verilog
❖ DAY-4: Implementation of minimized Boolean expression using 6-
Variable K-map and Verilog code.
❖ DAY-5: Implementation of Half Adder using Dataflow Modelling.
❖ DAY-6: Implementation of Full Adder using Dataflow Modelling.
❖ DAY-7: Implementing Full adder using two Half adders
❖ DAY-8: Implementation of 4-Bit Ripple Carry Adder.
❖ DAY-9: Implementation of 4-Bit Carry Select Adder using Full Adders
and Multiplexers.
❖ DAY-10: Implementation of 4-Bit Carry Skip Adder
❖ DAY-11: Implementation of BCD adder Using Verilog
❖ DAY-12: Implementing 2x1 multiplexer using Verilog
❖ DAY-13: Implementing 4x1 mux using Verilog
❖ DAY-14: Implementing 8x1 mux using 2x1 mux .
❖ DAY-15: Implementing 16x1 mux using 2x1 mux .
❖ DAY-16: Implementation of 16 bit ALU with 16 operations
❖ DAY-17: Implementation of K:1 Mux using parameter statement
(K=64).
❖ DAY-18: Implementation of 1x8 Demux using Verilog.
❖ DAY-19: Implementation of 1x32 Demux using Verilog.
❖ DAY-20: Implementation of N-Bit Comparator Using Verilog.
❖ DAY-21: Implementation of 2x4 Decoder using Verilog.
❖ DAY-22: Implementation of 3x8 Decoder using 2x4 Decoder.
❖ DAY-23: Implementation of Full Adder using 3:8 Decoder
❖ DAY-24: Implementation of 8x3 priority Encoder using Verilog
❖ DAY-25: Implementation of Tri state Buffer
❖ DAY-26: Implementation of Binary to Gray Conversion using Verilog.
❖ DAY-27: Implementation of Gray to Binary Conversion using Verilog.
❖ DAY-28: Implementation of Full Subtractor using Verilog.
❖ DAY-29: Implementation of CMOS Inverter.
❖ DAY-30: Implementation of SR Flipflop using Verilog.
❖ DAY-31: Implementation of JK Flipflop using Verilog.
❖ DAY-32: Implementation of D Flipflop using Verilog
❖ DAY-33: Implementation of T Flipflop using Verilog.
❖ DAY-34: Implementation of 32-bit RAM using Verilog.
❖ DAY-35: Implementation of UP Counter using Verilog.
❖ DAY-36: Implementation of Down Counter using Verilog.
❖ DAY-37: Implementation of Up and Down Counter using Verilog.
❖ DAY-38: Implementation of Left and Right Shift Registers using
Verilog.
❖ DAY-39: Implementing of SR FF TO D FF using Verilog.
❖ DAY-40: Implementation of D F/F TO SR F/F using Verilog.
❖ DAY-41: Implementation of SR F/F TO JK F/F using Verilog.
❖ DAY-42: Implementation of D F/F TO T F/F using Verilog.
❖ DAY-43: Implementation of T F/F TO D F/F using Verilog.
❖ DAY-44: Implementation of T F/F TO SR F/F using Verilog.
❖ DAY-45: Implementation of SR F/F TO T F/F using Verilog.
❖ DAY-46: Implementation of JK F/F TO SR F/F using Verilog.
❖ DAY-47: Implementation of D F/F TO JK F/F using Verilog.
❖ DAY-48: Implementation of SR GATED NAND LATCH using Verilog.
❖ DAY-49: Implementation of SR-GATED NOR LATCH using Verilog.
❖ DAY-50: Implementation of Parity Bit Generator using Verilog.
❖ DAY-51: Implementation of Clock Divider using Verilog.
❖ DAY-52: Implementation of Ring Counter using Verilog.
❖ DAY-53: Implementation of Johnson Counter using Verilog.
❖ DAY-54: Implementation of majority circuit using Verilog.
❖ DAY-55: Implementation of Odd Parity Generator using Verilog
❖ DAY-56: Implementation of Binary to One-Hot using Verilog.
❖ DAY-57: Implementation of 4-Bit Synchronous BCD Counter using
Verilog.
❖ DAY-58: Implementation of Serial In Serial Out Shift Register (SISO)
using Verilog
❖ DAY-59: Implementation of Serial In Parallel Out Shift Register (SIPO)
using Verilog.
❖ DAY-60: Implementation of Parallel In Serial Out Shift Register (PISO)
using Verilog.
❖ DAY-61: Implementation of Parallel In Parallel Out Shift Register
(PIPO) using Verilog.
❖ DAY-62: Bi-Directional Shift Register using Verilog.
❖ DAY-63: Implementing Pseudo Random Bit Sequence Generator using
Verilog.
❖ DAY-64: Implementing 8 Bit subtractor using Verilog.
❖ DAY-65: Implementing 8 Bit Adder Subtractor using Verilog.
❖ DAY-66: Implementing 4 Bit multiplier using Verilog
❖ DAY-67: Implementing Fixed-Point Restoring Division using Verilog.
❖ DAY-68: Implementing Master Slave JK FF using Verilog.
❖ DAY-69: Implementing Positive Edge Detector using Verilog.
❖ DAY-70: Implementing Moore 1010 FSM Sequence Detector using
Verilog.
❖ DAY-71: Implementing BCD Time Counter using Verilog.
❖ DAY-72: Implementing BCD To Seven Segment Display using Verilog.
❖ DAY-73: Implementing D Latch using a 2:1 Mux using Verilog.
❖ DAY-74: Implementing 1-Bit Comparator Using a 4x1 MUX using
Verilog.
❖ DAY-75: Implementing Logical, Algebraic and Rotate shift operator
using Verilog.
❖ DAY-76: Implementing CN(CHANGE-NO CHANGE FLIPFLOP)
USING 2:1 MUX using Verilog.
❖ DAY-77: Implementing Frequency Divider By Odd Numbers using
Verilog.
❖ DAY-78: Implementing Greatest Common Divisor using Verilog.
❖ DAY-79: Implementing Greatest Common Divisor using FSM using
Verilog.
❖ DAY-80: Implementing Single Port RAM using Verilog.
❖ DAY-81: Implementing Dual Port RAM using Verilog.
❖ DAY-82: Implementing Clock Buffer using Verilog.
❖ DAY-83: Implementing Synchronous FIFO using Verilog
❖ DAY-84: Implementing Fixed Priority Arbiter using Verilog.
❖ DAY-85: Implementing Synchronous RAM using Verilog.
❖ DAY-86: Implementing 1 MB 32 bit Memory using Verilog.
❖ DAY-87: Implementing 24 Hour Timer using Verilog.
❖ DAY-88: Implementing Automatic Door Controller using Verilog.
❖ DAY-89: Implementing Clock Gating using Dual Latch using Verilog.
❖ DAY-90: Implementing Fibonacci Generator using Verilog.
❖ DAY-91: Implementing Clock Phasing using Verilog.
❖ DAY-92: Implementing Triangle Wave Generator using Verilog.
❖ DAY-93: Implementing Ring Oscillator using Verilog.
❖ DAY-94: Implementing Pulse Width Modulation using Verilog.
❖ DAY-95: Implementing I2C Master Communication using Verilog.
❖ DAY-96: Implementing UART Transmitter using Verilog.
❖ DAY-97: Implementing Traffic Light Controller using FSM using
Verilog.
❖ DAY-98: Implementing Stop Watch using Verilog
❖ DAY-99: Implementing SPI Controller using Verilog.
❖ DAY-100: Implementing Router 1x3 using Verilog.
DAY-1
#100DAYSRTL
AIM : Basic Logic Gates implementation using
NAND(universal gate)
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC :
=======================================
DAY-2
#100DAYSRTL
AIM : Basic Logic Gates implementation using
NOR(universal gate)
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-3
#100DAYSRTL
AIM : Random Boolean expression (ABC+A`C`+D)
Implementation using Verilog
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-4
#100DAYSRTL
AIM : Implementation of minimized boolean
expression using 6-Variable K-map and Verilog
code.
F(A,B,C,D,E,F)=Mintermsof(0,5,7,8,9,12,13,23,24,
25,28,29,37,40,42,44,46,55,56,57,60,61); Minimized
Expression= bc'e + a'ce' + ab'cf' + bc'def + b'c'def +
a'b'c'df + a'b'd'e'f
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-5
#100DAYSRTL
AIM : Implementation of Half Adder using Dataflow
Modelling.
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-6
#100DAYSRTL
AIM: Implementation of Full Adder using Dataflow
modelling.
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-7
#100DAYSRTL
AIM : Implementing Full adder using two Half adders
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-8
#100DAYSRTL
AIM : Implementation of 4-Bit Ripple Carry Adder.
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-9
#100DAYSRTL
AIM : Implementation of 4-Bit Carry Select Adder
using Full Adders and Multiplexers.
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-10
#100DAYSRTL
AIM : Implementation of 4-Bit Carry Skip Adder.
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-11
#100DAYSRTL
AIM : Implementation of BCD adder Using Verilog
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC :
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DAY-12
#100DAYSRTL
AIM : Implementing 2x1 multiplexer using Verilog
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-13
#100DAYSRTL
AIM : Implementing 4x1 mux using Verilog
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-14
#100DAYSRTL
AIM : Implementing 8x1 mux using 2x1 mux .
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-15
#100DAYSRTL
AIM : Implementing 16x1 mux using 2x1 mux .
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-16
#100DAYSRTL
AIM : Implementation of 16 bit ALU with 16
operations
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-17
#100DAYSRTL
AIM : Implementation of K:1 Mux using parameter
statement (K=64).
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-18
#100DAYSRTL
AIM : Implementation of 1x8 Demux using Verilog .
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-19
#100DAYSRTL
AIM : Implementation of 1x32 Demux using Verilog .
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-20
#100DAYSRTL
AIM : Implementation of N-Bit Comparator Using
Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-21
#100DAYSRTL
AIM : Implementation of 2x4 Decoder using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-22
#100DAYSRTL
AIM : Implementation of 3x8 Decoder using 2x4
Decoder.
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-23
#100DAYSRTL
AIM : Implementation of Full Adder using 3:8
Decoder.
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-24
#100DAYSRTL
AIM : Implementation of 8x3 priority Encoder using
Verilog
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-25
#100DAYSRTL
AIM : Implementation of Tri state Buffer
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-25
#100DAYSRTL
AIM : Implementation of Binary to Gray Conversion
using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC :
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DAY-27
#100DAYSRTL
AIM : Implementation of Gray to Binary Conversion
using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-28
#100DAYSRTL
AIM : Implementation of Full Subtractor using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC :
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DAY-29
#100DAYSRTL
AIM : Implementation of CMOS Inverter..
RTL CODE:
TEST BENCH:
WAVE FORM:
=======================================
DAY-30
#100DAYSRTL
AIM : Implementation of SR Flipflop using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT :
WAVE FORM:
SCHEMATIC :
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DAY-31
#100DAYSRTL
AIM: Implementation of JK Flipflop using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-32
#100DAYSRTL
AIM: Implementation of D Flipflop using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-33
#100DAYSRTL
AIM: Implementation of T Flipflop using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
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DAY-34
#100DAYSRTL
AIM: Implementation of 32-bit RAM using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
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SCHEMATIC :
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DAY-35
#100DAYSRTL
AIM : Implementation of UP Counter using Verilog .
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC :
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DAY-36
#100DAYSRTL
AIM : Implementation of Down Counter using Verilog .
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC :
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DAY-37
#100DAYSRTL
AIM : Implementation of Up and Down Counter using
Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC :
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DAY-38
#100DAYSRTL
AIM : Implementation of Left and Right Shift Registers
using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC :
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DAY-39
#100DAYSRTL
AIM : Implementing of SR FF TO D FF using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC :
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DAY-40
#100DAYSRTL
AIM : Implementation of D F/F TO SR F/F using
Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-40
#100DAYSRTL
AIM : Implementation of D F/F TO SR F/F using
Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-42
#100DAYSRTL
AIM : Implementation of D F/F TO T F/F using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-43
#100DAYSRTL
AIM : Implementation of T F/F TO D F/F using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-44
#100DAYSRTL
AIM : Implementation of T F/F TO SR F/F using
Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC :
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DAY-45
#100DAYSRTL
AIM : Implementation of SR F/F TO T F/F using
Verilog.
RTL CODE:
TEST BENCH:
OUTPUT:
WAVE FORM:
SCHEMATIC :
=======================================
DAY-46
#100DAYSRTL
AIM : Implementation of JK F/F TO SR F/F using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC :
=======================================
DAY-47
#100DAYSRTL
AIM : Implementation of D F/F TO JK F/F using
Verilog.
RTL CODE:
TEST BENCH:
OUTPUT :
WAVE FORM:
SCHEMATIC:
=======================================
DAY-48
#100DAYSRTL
AIM : Implementation of SR GATED NAND LATCH
using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT :
WAVE FORM:
SCHEMATIC:
=======================================
DAY-49
#100DAYSRTL
AIM : Implementation of SR-GATED NOR LATCH
using Verilog.
RTL CODE:
TEST BENCH:
OUTPUT :
WAVE FORM:
SCHEMATIC:
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DAY-50
#100DAYSRTL
AIM : Implementation of Parity Bit Generator using
Verilog.
RTL CODE:
TEST BENCH:
OUTPUT :
WAVE FORM:
SCHEMATIC:
=======================================
DAY-51
#100DAYSRTL
AIM : Implementation of Clock Divider using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
=======================================
DAY-51
#100DAYSRTL
AIM : Implementation of Ring Counter using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC :
=======================================
DAY-53
#100DAYSRTL
AIM : Implementation of Johnson Counter using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC :
=======================================
DAY-54
#100DAYSRTL
AIM : Implementation of majority circuit using
Verilog.
RTL CODE:
TEST BENCH:
OUTPUT :
WAVE FORM:
SCHEMATIC :
=======================================
DAY-55
#100DAYSRTL
AIM : Implementation of Odd Parity Generator using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-56
#100DAYSRTL
AIM : Implementation of Binary to One-Hot using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-57
#100DAYSRTL
AIM : Implementation of 4-Bit Synchronous BCD
Counter using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-58
#100DAYSRTL
AIM: Implementation of Serial In Serial Out Shift
Register (SISO) using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-59
#100DAYSRTL
AIM: Implementation of Serial In Parallel Out Shift
Register (SIPO) using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-60
#100DAYSRTL
AIM: Implementation of Parallel In Serial Out Shift
Register (PISO) using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-61
#100DAYSRTL
AIM: Implementation of Parallel In Parallel Out Shift
Register (PIPO) using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-62
#100DAYSRTL
AIM : Bi-Directional Shift Register using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC :
=======================================
DAY-63
#100DAYSRTL
AIM : Implementing Pseudo Random Bit Sequence
Generator using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-64
#100DAYSRTL
AIM : Implementing 8 Bit subtractor using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-65
#100DAYSRTL
AIM : Implementing 8 Bit Adder Subtractor using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC :
=======================================
DAY-66
#100DAYSRTL
AIM : Implementing 4 Bit multiplier using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC :
=======================================
DAY-67
#100DAYSRTL
AIM : Implementing Fixed-Point Restoring Division
using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC :
=======================================
DAY-68
#100DAYSRTL
AIM : Implementing Master Slave JK FF using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC :
=======================================
DAY-69
#100DAYSRTL
AIM: Implementing Positive Edge Detector using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-70
#100DAYSRTL
AIM: Implementing Moore 1010 FSM Sequence
Detector using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-71
#100DAYSRTL
AIM: Implementing BCD Time Counter using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-72
#100DAYSRTL
AIM: Implementing BCD To Seven Segment Display
using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-73
#100DAYSRTL
AIM: Implementing D Latch using a 2:1 Mux using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-74
#100DAYSRTL
AIM: Implementing 1-Bit Comparator Using a 4x1
MUX using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-75
#100DAYSRTL
AIM: Implementing Logical, Algebraic and Rotate shift
operator using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-76
#100DAYSRTL
AIM: Implementing CN(CHANGE-NO CHANGE
FLIPFLOP) USING 2:1 MUX using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-77
#100DAYSRTL
AIM: Implementing Frequency Divider By Odd
Numbers using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-78
#100DAYSRTL
AIM: Implementing Greatest Common Divisor using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-79
#100DAYSRTL
AIM: Implementing Greatest Common Divisor using
FSM using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-80
#100DAYSRTL
AIM: Implementing Single Port RAM using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-80
#100DAYSRTL
AIM: Implementing Single Port RAM using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-81
#100DAYSRTL
AIM: Implementing Dual Port RAM using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-82
#100DAYSRTL
AIM: Implementing Clock Buffer using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-83
#100DAYSRTL
AIM: Implementing Synchronous FIFO using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-84
#100DAYSRTL
AIM: Implementing Fixed Priority Arbiter using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-85
#100DAYSRTL
AIM: Implementing Synchronous RAM using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-86
#100DAYSRTL
AIM: Implementing 1 MB 32 bit Memory using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-87
#100DAYSRTL
AIM: Implementing 24 Hour Timer using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
DAY-88
#100DAYSRTL
AIM: Implementing Automatic Door Controller using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-89
#100DAYSRTL
AIM: Implementing Clock Gating using Dual Latch
using Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-90
#100DAYSRTL
AIM: Implementing Fibonacci Generator using
Verilog.
RTL CODE:
TEST BENCH:
WAVE FORM:
SCHEMATIC:
=======================================
DAY-91
#100DAYSRTL
AIM: Implementing Clock Phasing using Verilog.
RTL CODE:
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DAY-92
#100DAYSRTL
AIM: Implementing Triangle Wave Generator using
Verilog.
RTL CODE:
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DAY-93
#100DAYSRTL
AIM: Implementing Ring Oscillator using Verilog.
RTL CODE:
TEST BENCH:
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DAY-94
#100DAYSRTL
AIM: Implementing Pulse Width Modulation using
Verilog.
RTL CODE:
TEST BENCH:
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DAY-95
#100DAYSRTL
AIM: Implementing I2C Master Communication using
Verilog.
RTL CODE:
TEST BENCH:
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DAY-96
#100DAYSRTL
AIM: Implementing UART Transmitter using Verilog.
RTL CODE:
TEST BENCH:
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DAY-97
#100DAYSRTL
AIM: Implementing Traffic Light Controller using
FSM using Verilog.
RTL CODE:
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DAY-98
#100DAYSRTL
AIM: Implementing Stop Watch using Verilog.
RTL CODE:
TEST BENCH:
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SCHEMATIC:
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DAY-99
#100DAYSRTL
AIM: Implementing SPI Controller using Verilog.
RTL CODE:
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DAY-100
#100DAYSRTL
AIM: Implementing Router 1x3 using Verilog.
RTL CODE:
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