VLSI Training Center
Setting standards in VLSI Design
Final Test
Time : 3 Hrs & 30 Mins Total Marks : 100
Part - A
Marks : 40
Digital (12 Marks)
1. Give the minimum count of inverters (NOT gates) & 3 input gates required for the
implementation of the below expression. Please don’t use any 2 input gates. -- (6 Marks)
BC'D' +ABC'+AC'D+AB'D+A'BD'
2. Design a positive edge triggered D flipflop using 2:1 Muxes. -- (6 Marks)
Verilog (12 Marks)
3. Write an RTL code to design a sequence detector in MOORE non-overlapping manner to
detect 1011 with LSB first. -- (8 Marks)
4. Find out the bug in the code & the hardware inferred by the following code and explain its
functionality? -- (3 Marks)
module (input [7:0] ain, output [2:0]y);
always@(*)
begin
case(1'b1)
ain[7]: y = 7;
ain[6]: y = 6;
ain[5]: y = 5;
ain[4]: y = 4;
ain[3]: y = 3;
ain[2]: y = 2;
ain[1]: y = 1;
ain[0]: y = 0;
default : y = 3'dx;
endcase
end
endmodule
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Setting standards in VLSI Design
Verification (16 Marks)
5. Predict the output for the following program. -- (6 Marks)
6. Write at least 4 System Verilog Assertions for the given Logic circuit with synchronous
active low clear input. Use only X, Y and clr and q qbar signals while writing assertions.
Don’t use intermediate signals. -- (4 Marks)
7. What do you mean by factory overriding? What are the different ways to do factory
overriding in UVM? -- (4 Marks)
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Setting standards in VLSI Design
Part - B
Marks : 40
Digital (12 Marks)
8. Design a three input logic circuit that will cause an output F to go active LOW under the following
conditions.
• All inputs are logic 1
• An odd number of inputs are logic 1
• None of the inputs are logic 1
To do this, use one full adder and few nor gates. Assume that all inputs are available in the complement
form. -- (5 Marks)
9. Draw a Moore overlapping FSM for the circuit which follows the following specifications.
Inputs: Two single bit inputs X1 and X2. -- (7 Marks)
Output: Single bit Z
Specifications: a) If X1 X2= 00, Z does not change
b) If X1 X2= 01, Z=1
c) If X1 X2 =10, Z=0
d) Z changes its value when two consecutive 11 are received at the input
X1 X2.
Verilog (12 Marks)
10. Which of the following code will generate a clock signal with a time period of 15ns with
a 50% duty cycle? Explain. -- (6 Marks)
11. Draw the waveform for the following code. -- (6 Marks)
module test( );
reg rst,data,clk;
parameter cycle = 10,
Thold = 2,
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Setting standards in VLSI Design
Tsetup = 2;
task apply_data;
begin
rst <= 1'b0;
data <= 1'b1;
@(posedge clk);
#(Thold);
{rst,data} <= 2'bxx;
#(cycle-Thold-Tsetup);
end
endtask
initial
begin
clk = 1'b0;
forever
#cycle clk = ~ clk;
end
initial
begin
rst = 1'b1;
repeat (2)
@(posedge clk);
repeat (2)
apply_data ();
$stop;
end
endmodule
12. Write a Verilog TB to read the test vectors from a file "data_in.txt" and display the even
parity of each test vector into an output file called "data_out.txt". -- (6 Marks)
data_in.txt:
10101010
11111111
11110000
00001111
00000000
11111111
11001100
00110011
Verification (16 Marks)
13. Please find the below snippet in which there are two dynamic arrays (num & sqr). Please
write your own logic that can be inserted in the space given for you to fulfill the following
requirements. All the 10 numbers in ‘num’ array must be unique and they should be within
a range of 1 to 50. All 10 numbers in ‘sqr’ array must be equal to squares of the
corresponding number in ‘num’ array. Please don’t use ‘*’ and ‘**’ operator to calculate
the squares. (Hint: Square a number ‘n’ is equal to the sum of first ‘n’ odd numbers.)
-- (8 Marks)
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module test();
class AB;
rand int num[];
rand int sqr[];
constraint array_size{num.size == 10;
sqr.size == 10;}
/*----------------------------------
// Space for writing your own logic
------------------------------------*/
endclass
AB a_h = new();
initial
begin
void'(a_h.randomize());
$display("numbers are %p", a_h.num);
$display("squares are %p", a_h.sqr);
end
endmodule
14. How to connect the static interface with UVM test bench components? Write snippet of
code to explain this. -- (8 Marks)
Part – C (Basic Electronics, CMOS, Networks, FPGA, STA)
Marks : 20
15. What is an emitter follower circuit? Prove that, its voltage gain is unity. -- (4 Marks)
16. Draw the layout diagram for a CMOS logic circuit whose output Y is described with the
following Boolean expression. -- (4 Marks)
̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑌 = 𝐴+𝐵+𝐶
17. In the below network, determine the current through RL & maximum power delivered to
RL. -- (4 Marks)
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18. Explain the differences between FPGA & ASIC. -- (3 Marks)
19. In the below circuit with 3 flipflops, Determine the Max. Clock frequency -- (5 Marks)
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