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Lab 6

The document contains RTL descriptions for a 101 sequence detector and a synchronous logic control unit for a vending machine, along with their respective test benches. The sequence detector uses a finite state machine to detect the sequence '101' based on input signals, while the vending machine manages states based on coin inputs. Both modules are designed to be verified through simulation using test benches.

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Suyash Mishra
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229 views9 pages

Lab 6

The document contains RTL descriptions for a 101 sequence detector and a synchronous logic control unit for a vending machine, along with their respective test benches. The sequence detector uses a finite state machine to detect the sequence '101' based on input signals, while the vending machine manages states based on coin inputs. Both modules are designed to be verified through simulation using test benches.

Uploaded by

Suyash Mishra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LAB-6

1.Write an RTL description for 101 sequence detector and verify


using test bench.
module seq_detector(
input x,clk,reset,
output reg z
);
parameter S0 = 0 , S1 = 1 , S2 = 2 , S3 = 3 ;
reg [1:0] PS,NS ;
always@(posedge clk or posedge reset)
begin
if(reset)
PS <= S0;
else
PS <= NS ;
end
always@(PS or x)
begin
case(PS)
S0 : begin
z=0;
NS = x ? S1 : S0 ;
$display(PS);
end
S1 : begin
z=0;
NS = x ? S1 : S2 ;
$display(PS);
end
S2 : begin
z=0;
NS = x ? S3 : S0 ;
$display(PS);
End
endcase
end
endmodule

//TESTBENCH

module testbench;
reg x;
reg clk;
reg reset;
wire z;
seq_detector dut (
.x(x),
.clk(clk),
.reset(reset),
.z(z)
);
initial
begin
clk = 1'b0;
reset = 1'b1;
#15 reset = 1'b0;
End
always #5 clk = ~ clk;
initial begin
#12 x = 0;#10 x = 0 ; #10 x = 1 ; #10 x = 0 ;
#12 x = 1;#10 x = 1 ; #10 x = 0 ; #10 x = 1 ;
#12 x = 1;#10 x = 0 ; #10 x = 0 ; #10 x = 1 ;
#12 x = 0;#10 x = 1 ; #10 x = 1 ; #10 x = 0 ;
#10 $finish;
end
endmodule
2. Design a synchronous logic control unit for vending machine and
verify using test bench.

module vending_machine(
input clk,rst_n,
input [1:0] coin,
output reg out, change
);
reg [2:0] state,nx_state;
parameter [2:0] IDLE=3'd0,S1=3'd1,S2=3'd2 ,S3=3'd3,S4=3'd4;
always @(posedge clk or negedge rst_n)
if(!rst_n)
state<=IDLE;
else
state<=nx_state;
always @(*) begin
nx_state=IDLE;
case(state)
IDLE: if(coin==2'd1) nx_state=S1;else if(coin==2'd2)
nx_state=S2; else nx_state=IDLE;
S1: if(coin==2'd1) nx_state=S2;else if(coin==2'd2)
nx_state=S3; else nx_state=S1;
S2: if(coin==2'd1) nx_state=S3;else if(coin==2'd2)
nx_state=S4; else nx_state=S2;
S3: nx_state=IDLE;
S4: nx_state=IDLE;
default:nx_state=IDLE;
endcase
end
always @(posedge clk or negedge rst_n)
if(!rst_n)
{out, change}<='b0;
else
case(nx_state)
S3: {out, change}<=10;
S4: {out, change}<=11;
endcase
endmodule

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