50 Days of

RTL
JAGRUTHI K
 INDEX
DAY 1: 8 TO 1 MULTIPLEXER

DAY 2: 1 TO 8 DEMULTIPLEXER

DAY 3: 3 TO 8 DECODER

DAY 4: 8 TO 3 ENCODER

DAY 5: 4-BIT RIPPLE CARRY ADDER

DAY 6: CARRY LOOK AHEAD ADDER

DAY 7: 4 BIT BINARY ADDER-SUBTRACTOR

DAY 8: 8 BIT ALU

DAY 9: BINARY MULTIPLIER

DAY 10: MAGNITUDE COMPARATOR

DAY 11: 1 TO 8 ROUTER

DAY 12: BOOTH’S MULTIPLIER

DAY 13: FLIPFLOPS

DAY 14: 8 BIT UP-DOWN COUNTER

DAY 15: SISO and SIPO SHIFT REGISTERS

DAY 16: PISO and PIPO SHIFT REGISTERS

DAY 17: SRAM (SYNCHRONOUS RAM)

DAY 18: DUAL PORT RAM

DAY 19: RING COUNTER

DAY 20: JOHNSON COUNTER

DAY 21: SYNCHRONOUS FIFO

DAY 22: EDGE DETECTOR

DAY 23: CLOCK DIVIDER

DAY 24: BARREL SHIFTER

DAY 25: CONTENT ADDRESSABLE MEMORY (CAM)

DAY 26: BCD TO 7 SEGMENT DISPLAY

DAY 27: GRAY CODE COUNTER

DAY 28: 24 HOUR TIMER

DAY 29: MOORE SEQUENCE DETECTOR (1101- OVERLAPPING)

DAY 30: AUTOMATIC DOOR CONTROLLER (MEALY FSM)

DAY 31: CLOCK GATING USING DUAL LATCH

DAY 32: FREQUENCY COUNTER

DAY 33: LOGIC GATES USING CMOS LOGIC

DAY 34: PARITY GENERATOR

DAY 35: BCD ADDER

DAY 36: FIBONACCI GENERATOR

DAY 37: 2 FLIP FLOP SYNCHRONIZER

DAY 38: N -BIT SYNCHRONIZER

DAY 39: MASTER SLAVE JK FLIPFLOP (ASYNCHRONOUS RESET)

DAY 40: MOD – N COUNTER

DAY 41: MULTIBIT JK FLIPFLOP (ASYNCHRONOUS RESET)

DAY 42: PARALLEL TO SERIAL CONVERTER

DAY 43: PSEUDO RANDOM SEQUENCE GENERATOR

DAY 44: CLOCK PHASING

DAY 45: ASYNCHRONOUS FIFO

DAY 46: GENERATE TRIANGLE WAVE

DAY 47: RING OSCILLATOR

DAY 48: GCD OF 2 N- BIT NUMBERS

DAY 49: FIXED PRIORITY ARBITER

DAY 50: ROUND ROBIN ARBITER

 50 DAYS of RTL CHALLENGE
DAY 1

AIM: To design, simulate, and verify the behavior of an 8-to-1 multiplexer. The MUX will select one of
eight input signals based on a 3-bit selection signal and output the selected input.

OPERATION: An 8-to-1 multiplexer selects one input from eight possible inputs (I0 to I7) based on a 3-bit
selection line (S2, S1, S0). Depending on the value of the select lines, one of the inputs is passed to the
output.

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:
POWER ANALYSIS:
 50 DAYS of RTL CHALLENGE

DAY 2

AIM: A demultiplexer (DEMUX) is a digital logic component that routes a single input to one of
several output lines based on a select signal. The 1-to-8 demultiplexer takes one input and routes it
to one of eight output lines according to a 3-bit select input.

OPERATION: The 1-to-8 demultiplexer consists of:

• 1 input (i): The data input that will be directed to one of the outputs.

• 1 select input (s): A 3-bit wide select line that determines which output line will receive the
input data.

• 8 output lines (y[7:0]): The outputs, of which only one will carry the data i depending on the
value of the select input.

Functionality

The 1-to-8 demux operates as follows:

• When the 3-bit select input s is 000, the data input i is directed to y[0].

• When s is 001, the data input i is routed to y[1].

• This process continues for all values of s up to 111, where i is routed to y[7].

• For all other values of s no output is activated (all bits in y are set to 0 by default).

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:
POWER ANALYSIS:
 50 DAYS of RTL CHALLENGE

DAY 3

AIM: To simulate and verify the functionality of a 3-to-8 decoder using Verilog. The goal is to ensure
that for every 3-bit input, exactly one corresponding output from the 8 output lines is activated (set
to high), while all others remain low.

OPERATION: A 3-to-8 decoder takes a 3-bit binary input and generates 8 outputs, with only one
output active (logic high) at a time. The output corresponding to the binary input is set to high (1),
while all other outputs remain low (0). The decoder essentially performs a 1-of-8 selection based on
the 3-bit input.

Functionality

The operation of the 3-to-8 decoder is defined as follows:

• When the input is 000, output Y0 is high.

• When the input is 001, output Y1 is high.

• When the input is 010, output Y2 is high.

• When the input is 011, output Y3 is high.

• When the input is 100, output Y4 is high.

• When the input is 101, output Y5 is high.

• When the input is 110, output Y6 is high.

• When the input is 111, output Y7 is high.

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
Other ways to write rtl code of a decoder:

2.
 50 DAYS of RTL CHALLENGE

DAY 4

AIM: The aim of simulating an 8-to-3 encoder is to ensure that:

1. Functionality: The encoder correctly produces a 3-bit binary representation of the highest
priority input bit that is set to 1.

2. Correct Output: The output corresponds to the binary index of the highest priority input bit.

3. Behavior: The encoder handles different scenarios correctly, including when multiple input
bits are set to 1 or when all inputs are 0.

OPERATION: An 8-to-3 encoder takes an 8-bit input and outputs a 3-bit binary value corresponding
to the index of the highest priority input bit that is set. The priority is usually from the most
significant bit (MSB) to the least significant bit (LSB). If multiple bits are 1, the encoder outputs the
index of the highest priority bit.

RTL DESIGN:

TESTBENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
Other ways to write RTL code of an Encoder:
 50 DAYS of RTL CHALLENGE

DAY 5

Aim of the 4-bit Ripple Carry Adder:

The aim of a 4-bit ripple carry adder is to perform the addition of two 4-bit binary numbers along
with an optional carry input (usually from a previous addition). It also generates a 4-bit sum and a
carry-out that can be passed to the next higher-order adder in multi-bit additions. This adder serves
as the basic building block for arithmetic operations in digital circuits like microprocessors and ALUs.

Operation of the 4-bit Ripple Carry Adder:

A ripple carry adder works by linking multiple single-bit full adders in series. Each full adder adds
corresponding bits of two binary numbers along with a carry from the previous stage. The name
"ripple carry" comes from the fact that the carry output of each full adder ripples through to the next
stage, which impacts the next bit's addition.

RTL DESIGN:
TESTBENCH:

SIMULATION RESULTS:
SCHEMATIC:

POWER ANALYSIS:
Other ways to write RTL code of a 4 bit ripple adder:

2. For n-bit ripple adder

`timescale 1ns /1ps
module ripple_carry_adder( input [N-1:0] A, input [N-1:0] B, input Cin, output [N-1:0] Sum, output
Cout);
wire [N:0] carry;
assign carry[0] = Cin;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin
fulladder FA_inst (.A(A[i]),.B(B[i]), .Cin(carry[i]),.Sum(Sum[i]),.Cout(carry[i+1]);
end
endgenerate
assign Cout = carry[N];
endmodule
 50 DAYS of RTL CHALLENGE

DAY 6

Aim:To design and implement a 4-bit Carry Look Ahead Adder (CLA) in Verilog, simulate its operation

Operation of Carry Look Ahead Adder:

A Carry Look Ahead Adder (CLA) is designed to speed up the process of binary addition by
calculating the carry signals in advance, independent of the actual sum computation. This minimizes
the delay caused by the propagation of the carry bit through each stage of the addition, which is a
significant bottleneck in Ripple Carry Adders.

Key Concepts:

1. Generate (G) and Propagate (P) Signals:

o Generate (G): A carry is generated when both bits of the input are 1. For bit
positions i, Gi=Ai⋅Bi.

o Propagate (P): A carry is propagated when at least one of the inputs is 1. For bit
positions i, Pi=Ai⊕Bi.

2. Carry Look Ahead Logic:

o The carry for each stage is computed using the generate and propagate signals rather
than waiting for the ripple from the previous stage.

o The carry-out of each bit position is calculated as follows: The carry-out of each bit
position is calculated as follows:

1. C1=G0+(P0⋅C0)

2. C2=G1+(P1⋅C1)

3. C3=G2+(P2⋅C2)

4. C4=G3+(P3⋅C3)

3. Sum Calculation:

o The sum bits are computed using the propagate signals and the carry bits: Where iii
is the bit position.

Si=Pi⊕Ci
RTL DESIGN:

TESTBENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
Structural model RTL:

RTL code for N – bit carry look ahead adder:

module carry_lookahead_adder_n_bit( input [N-1:0] A,input [99:0] B,input Cin, output [N-
1:0] Sum, output Cout);
wire [N-1:0] P;
wire [N-1:0] G;
wire [N-1:0] C;
assign C[0] = Cin;
genvar I;
generate
for (i = 0; i < N; i = i + 1) begin
assign P[i] = A[i] ^ B[i];
assign G[i] = A[i] & B[i];
end
endgenerate
generate
for (i = 1; i <= N; i = i + 1) begin
assign C[i] = G[i-1] | (P[i-1] & C[i-1]);
end
endgenerate
generate
for (i = 0; i < N; i = i + 1) begin
assign Sum[i] = P[i] ^ C[i];
end
endgenerate
assign Cout = C[N];
endmodule
 50 DAYS of RTL CHALLENGE

DAY 7

Aim:to design, simulate, and verify a 4-bit binary adder-subtractor circuit. This circuit should be
capable of performing both addition and subtraction based on a control signal (mode).

Operation:

The adder-subtractor circuit operates based on the value of a control signal (mode):

• Mode = 0: The circuit functions as a binary adder and adds two 4-bit inputs, A and B. It
produces a 4-bit result (Sum) along with a carry-out (Cout).

• Mode = 1: The circuit functions as a subtractor. It subtracts the second input (B) from the
first input (A) using two's complement arithmetic. The result is a 4-bit difference (Sum), and
the carry-out (Cout) can be treated as a borrow indicator.

The operation is based on the following principles:

1. Addition:

o When mode = 0, the inputs A and B are directly added, and the result is the sum of
the two numbers.

o The carry-out (Cout) indicates whether there was an overflow from the most
significant bit.

2. Subtraction:

o When mode = 1, the input B is complemented (inverted) and 1 is added to it,

following the two's complement method. This effectively subtracts B from A.

o The carry-out (Cout) serves as a borrow indicator, though it is interpreted as a

positive carry when working with two's complement arithmetic.
RTL DESIGN:

TESTBENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
Behavioural and Dataflow models:
 50 DAYS OF RTL CHALLENGE

DAY 8

Aim: The aim of the 8-bit ALU (Arithmetic Logic Unit) is to perform a variety of arithmetic and logical
operations on 8-bit binary inputs. This unit can serve as a fundamental building block for digital
systems, such as CPUs or microcontrollers, allowing for efficient data manipulation.

RTL DESIGN:
TESTBENCH:

SIMULATION RESULTS:

POWER ANALYSIS:
SCHEMATIC:
 50 DAYS OF RTL CHALLENGE

DAY 9

Aim of a Binary Multiplier

The primary aim of a binary multiplier is to perform multiplication of two binary numbers, resulting
in a product that is typically larger than either of the multiplicands. This operation is fundamental in
digital systems for various applications, including arithmetic calculations, signal processing, and
digital circuit design.

Operation of a Binary Multiplier

1. Input Representation:

o Two binary numbers (multiplicand and multiplier) are taken as inputs. In the case of
a 4-bit binary multiplier, both inputs are 4 bits wide.

2. Partial Products Generation:

o The binary multiplier generates partial products based on the bits of the multiplier.
Each bit of the multiplier is checked:

▪ If a bit is 1, the corresponding shifted version of the multiplicand is

generated (using logical AND).

▪ If a bit is 0, the partial product for that position is zero.

3. Shifting:

o Each partial product is shifted left according to its bit position in the multiplier. For
example, the least significant bit (LSB) corresponds to no shift, the next bit
corresponds to a shift of one position, and so on.

4. Addition of Partial Products:

o All the generated partial products are added together. This can be done using binary
addition methods, which may involve carrying bits as necessary.

5. Output:

o The final output is the sum of all the partial products, resulting in a product that can
be wider than the original inputs (for two 4-bit numbers, the product is an 8-bit
number).

1. Sum partial products:

o 0000 + 00110 + 0000 + 0000 = 0110 (6 in decimal)

RTL DESIGN:

TESTBENCH:
SIMULATION RESULTS:

POWER ANALYSIS:

SCHEMATIC:
BEHAVIOURAL MODEL:

STRUCTURAL MODEL(USING RIPPLE ADDER):

 50 DAYS OF RTL CHALLENGE

DAY 10

Aim:

The primary aim of a magnitude comparator is to compare two binary numbers and determine their
relative sizes. Specifically, it performs the following functions:

1. Comparison: The comparator evaluates two input binary numbers and establishes whether
one number is greater than, less than, or equal to the other.

2. Output Generation: Based on the comparison, the magnitude comparator produces three
output signals:

o A signal indicating if the first number is greater than the second (A > B).

o A signal indicating if the first number is less than the second (A < B).

o A signal indicating if the two numbers are equal (A = B).

RTL DESIGN:

TESTBENCH:
SIMULATION RESULTS:

POWER ANALYSIS:

SCHEMATIC:
 50 DAYS OF RTL CHALLENGE

DAY 11

Aim of a 1-to-8 Router:

The aim of a 1-to-8 router is to direct an input signal to one of eight possible output channels based
on a control signal. The control signal (often called the select signal) determines which of the eight
outputs will receive the input signal, while the others remain inactive or set to a default value.

RTL DESIGN:

TESTBENCH:
SIMULATION RESULTS:

POWER ANALYSIS:

SCHEMATIC:
 50 DAYS OF RTL CHALLENGE

DAY 12

Aim of Booth's Algorithm:

Booth's algorithm is designed to perform fast multiplication of two signed binary numbers (in two's
complement representation). Its primary aim is to minimize the number of additions and
subtractions required, improving the efficiency of the multiplication process, especially when
multiplying large binary numbers.

Operation of Booth's Algorithm:

Booth’s algorithm works by encoding sequences of 0s and 1s in the multiplier to reduce the number
of arithmetic operations needed. The algorithm shifts and adds/subtracts based on the analysis of
the current and previous bits of the multiplier. Here's a step-by-step outline of how it operates:

1. Initialization:

o Set the multiplicand M and multiplier Q.

o Initialize a register A (same size as M) to 0.

o Set a bit Q-1 to 0 (an extra bit for the multiplier).

o Set a counter to the number of bits in the multiplier.

2. Examine the least significant bit (LSB) of the multiplier Q and Q-1:

o If the current least significant bit (Q0) and the previous bit (Q-1) are:

▪ 10: Subtract the multiplicand from the value in A (i.e., A = A - M).

▪ 01: Add the multiplicand to the value in A (i.e., A = A + M).

▪ 00 or 11: No arithmetic operation is performed.

3. Right shift the accumulator (A), the multiplier (Q), and the extra bit Q-1 as a combined unit
(arithmetic shift).

4. Repeat the above steps until the counter reaches zero.

5. Final result:
After the final shift, the concatenated result of A and Q represents the product of the two
numbers.
RTL DESIGN:

TESTBENCH:
SIMULATION RESULTS:

POWER ANALYSIS:

SCHEMATIC:
 50 DAYS OF RTL CHALLENGE

DAY 13

AIM: To implement Flipflops using verilog in vivado

SR FLIPFLOP

RTL DESIGN: TESTBENCH:

SIMULATION:
D – FLIPFLOP;

RTL DESIGN:

TESTBENCH:

SIMULATION:
JK FLIPFLOP:

RTL DESIGN:

TESTBENCH:

SIMULATION:
T FLIPFLOP:

RTL DESIGN:

TESTBENCH:

SIMULATION:
 50 DAYS of RTL CHALLENGE
DAY 14

AIM:

The aim of designing an 8-bit up/down counter is to create a sequential circuit capable of counting
upwards or downwards based on a control signal. The counter operates with a clock signal and can be
reset to its initial state. The design should count from 0 to 255 when counting up, and from 255 to 0
when counting down.

OPERATION:

An 8-bit up/down counter is a digital sequential circuit that changes its count value on each clock pulse,
either incrementing or decrementing based on the control input.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
SCHEMATIC:

POWER ANALYSIS:
 50 DAYS of RTL CHALLENGE
DAY 15
Aim of Serial-In Serial-Out (SISO) Shift Register:

The primary aim of a Serial-In Serial-Out (SISO) shift register is to temporarily store binary data and shift
it one bit at a time, either to the right or to the left, based on a clock pulse. In a SISO shift register, data
is inputted and outputted sequentially, one bit at a time, making it useful for serial communication and
data manipulation tasks where data needs to be processed or transmitted serially.

RTL DESIGN:

TESTBENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
Aim of Serial In-Parallel Out (SIPO) Shift Register:

The primary aim of a Serial In-Parallel Out (SIPO) shift register is to convert serial data input (one bit at a
time) into parallel data output (multiple bits simultaneously). This type of shift register is commonly used
in applications where data needs to be transmitted or stored serially but processed or outputted in
parallel, such as in communication systems, data buffering, or interfacing between serial and parallel
components.

RTL:

TESTBENCH:
SIMULATION:

TCL CONSOLE:

SCHEMATIC:

POWER CONSUMPTION:
 50 DAYS of RTL CHALLENGE
DAY 16
Aim of Parallel-In Serial-Out (PISO) Shift Register:

The PISO shift register aims to convert parallel data inputs into a serial data stream. This is useful when
you need to transfer or transmit multiple data bits sequentially over a single communication line or
channel, thereby saving the number of required physical connections.

RTL DESIGN:
TESTBENCH:

SIMULATION RESULTS:
TCL CONSOLE:

SCHEMATIC:

POWER ANALYSIS:
Aim of Parallel In-Parallel Out (PIPO) Shift Register:

The PIPO shift register is designed to transfer data between parallel input and parallel output. The
primary aim is to capture parallel data at the input and output it directly in parallel, maintaining the
same data format. It's often used when parallel data needs to be temporarily stored before being sent or
processed further.

RTL:

TESTBENCH:
SIMULATION:

TCL CONSOLE:

SCHEMATIC:
POWER CONSUMPTION:
 50 DAYS of RTL CHALLENGE
DAY 17

AIM: Designing a Synchronous Static Random Access Memory (SRAM) . A memory system that operates
in synchronization with a clock signal, allowing reliable and efficient storage and retrieval of data. The
objective is to ensure that the read and write operations happen at predefined clock cycles, providing
predictable and stable memory access times, which is crucial for use in high-speed digital circuits.

Data Storage: To store a defined number of data words

Synchronous Operation: To ensure all read and write operations are controlled by a clock signal (clk),
thereby enabling synchronization with other system components.

Write Control: To write data into the memory when the Write Enable (Wr) signal is active, ensuring
data is stored at the correct address.

Read Control: To read data from the memory when the Wr signal is inactive, providing the stored
data from the specified address.

Reliable Timing: To achieve predictable timing for both reading and writing operations, reducing
complexity in timing analysis and integration into larger systems.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
SCHEMATIC:
POWER ANALYSIS:
 50 DAYS of RTL CHALLENGE
DAY 18
Aim of Dual-Port RAM

The aim of a Dual-Port RAM is to provide simultaneous access to two different memory locations
through two independent ports. This allows read and write operations to occur concurrently without
interference, improving data throughput and access speed in systems where parallelism is essential. It is
commonly used in applications such as high-speed processors, video processing, and communication
systems.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
SCHEMATIC:

POWER ANALYSIS:
 50 DAYS of RTL CHALLENGE
DAY 19
AIM OF RING COUNTER:

The aim of a ring counter is to design and implement a sequential digital circuit that generates a cyclic
pattern of binary states. Each state contains only one high (1) bit, with the rest being low (0), and the
high bit shifts position with every clock pulse.

Ring counters are commonly used in applications such as:

• Sequence generation

• Control logic for finite state machines

• LED chasers or display systems

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
SCHEMATIC:

POWER ANALYSIS:
 50 DAYS of RTL CHALLENGE
DAY 20
AIM OF JOHNSON COUNTER:

The aim of the Johnson counter (also known as a twisted ring counter) is to generate a unique sequence
of bit patterns by circulating and inverting the bits in a shift register. It is commonly used in digital
systems for applications such as:

• Frequency division: It can divide the clock frequency by a factor of 2N, where N is the number of
bits.

• Sequence generation: Johnson counters produce predictable, distinct patterns useful in control
systems or as counters in various applications.

• Digital pattern detection: It’s also used in specific types of synchronous counters and for
generating timing sequences.

By circulating and complementing the MSB (most significant bit), the Johnson counter efficiently utilizes
all 2N states with fewer flip-flops than conventional counters.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
SCHEMATIC:

POWER ANALYSIS:
 50 DAYS of RTL CHALLENGE
DAY 21
AIM:

To implement synchronous FIFO(first in first out) using Verilog in Vivado

RTL DESIGN:
TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:
POWER ANALYSIS:
 50 DAYS of RTL CHALLENGE
DAY 22
AIM OF AN EDGE DETECTOR:

The aim of an edge detector is to detect when a signal transitions from one logical state to another,
typically from low to high (rising edge) or high to low (falling edge). Edge detection is a crucial function
in digital systems, where it is used to identify specific events or changes in a signal.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
SCHEMATIC:

POWER ANALYSIS:
 50 DAYS of RTL CHALLENGE
DAY 23
AIM OF AN CLOCK DIVIDER:

The aim of a clock divider is to take a high-frequency clock signal and generate a slower clock signal by
dividing the input clock frequency by a specified factor. This is essential in digital systems where
different components may need to operate at various clock speeds.

1.Frequency Reduction

2.Synchronization

3.Power saving

4.Timing adjustments

5.Generating multiple clock domains

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:

SCHEMATIC:
POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 24
AIM OF BARREL SHIFTER:

The aim of a barrel shifter is to efficiently perform multi-bit shifting operations on binary data, allowing
for various types of shifts (logical, arithmetic, and rotation) without the need for multiple clock cycles or
complex control logic.

RTL DESIGN:
TEST BENCH:
SIMULATION RESULTS:

TCL CONSOLE:
SCHEMATIC:
POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 25
Ain of Content Addressable Memory (CAM):

A Content Addressable Memory (CAM) is a type of memory where you search for data by its content
rather than by its address. CAM is commonly used in networking hardware (e.g., routers for searching IP
addresses) and for cache implementations in processors.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 26

AIM: To design a BCD to 7 segment display in Verilog using vivado.

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:
POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 27

AIM OF GRAY CODE COUNTER:

Gray Code, also known as Reflected Binary Code, is a binary numeral system where two successive
values differ in only one bit. This property is particularly useful in reducing errors in digital
communications and rotary encoders where minimizing transitions can prevent glitches.

A Gray Code Counter serves specific purposes in digital systems where minimizing errors and
ensuring reliable data transitions are critical. Understanding its aim involves exploring the unique
properties of Gray code and the scenarios where these properties offer significant advantages over
traditional binary counting.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 28

AIM: TO IMPLEMENT 24 HOUR TIMER IN VERILOG USING VIVADO.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 29

AIM: Implementing Moore sequence detector (1101- overlapping) using Verilog in vivado

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
STATE DIAGRAM:

SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 30
Aim of Automatic Door Controller Using Mealy FSM

The aim of the Automatic Door Closing System using a Finite State Machine (FSM) is to design a
reliable and efficient control system that automatically opens and closes a door based on the
presence of a person. The system detects the presence of a person using sensors, opens the door
when a person approaches, keeps the door open for a specified period, and closes it automatically
after a timeout if no one is detected.

Key objectives include:

1. Person Detection: Open the door when the sensor detects a person approaching.

2. Timed Closure: After the door has opened and the person passes, close the door
automatically after a certain timeout period.

3. Safety and Responsiveness: If a person is detected while the door is closing, the door should
reopen to avoid closing on the person.

4. State-Based Control: Use FSM to model and manage the different states of the door (closed,
opening, open, closing), ensuring efficient transitions between these states.

5. Motor Control: Efficiently control the door motor based on the FSM, activating the motor
only when necessary (i.e., during opening or closing).

The system should ensure:

• Energy efficiency by reducing unnecessary motor activity.

• User safety by preventing the door from closing on a person.

• Smooth and responsive door control through the FSM's state transitions.
RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
STATE DIAGRAM:

SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 31
CLOCK GATING USING DUAL LATCH:

Clock gating is a technique used in digital design to reduce dynamic power consumption by
selectively disabling the clock signal to parts of a circuit when they are not in use. The primary aim is
to minimize the unnecessary switching of flip-flops and combinational logic, as clock signals are one
of the most power-hungry elements in a digital system.

The technique involves using a control signal (like an enable or gating signal) that gates the clock
signal based on certain conditions. For example, if a module is not needed in the current operation
cycle, the clock signal to that module is disabled, and no state transitions occur within the flip-flops
of that module.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 32
AIM OF FREQUENCY COUNTER:

A frequency counter typically counts the number of rising (or falling) edges of a clock signal within a
specific time period, usually measured using another clock.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 33
AIM: To implement Logic gates using CMOS logic.

AND GATE:

RTL:

TEST BENCH:
SIMULATION:

OR GATE:

RTL:

TESTBENCH:
SIMULATION:

INVERTER:

RTL:

TESTBENCH:

SIMULATION:
NAND GATE:

RTL:

TESTBENCH:

SIMULATION:
NOR GATE:

RTL:

TESTBENCH;

SIMULATION:
XOR GATE:

RTL:

TESTBENCH:

SIMULATION:
XNOR GATE:

RTL:

TESTBENCH:
SIMULATION:
 50 DAYS OF RTL CHALLENGE
DAY 34
AIM OF PARITY GENERATOR:

A parity generator generates a parity bit based on the number of 1's in a given
data word. There are two types of parity:

1. Even parity: The parity bit is set to ensure the total number of 1's
(including the parity bit) is even.

2. Odd parity: The parity bit is set to ensure the total number of 1's
(including the parity bit) is odd.

EVEN PARITY GENERATOR:

RTL: TESTBENCH:

SIMULATION:
SCHEMATIC:

POWER ANALYSIS:
ODD PARITY GENERATOR USING EVEN PARITY GENERATOR:
RTL:

TESTBENCH:

SIMULATION:
SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 35
BCD ADDER:

A BCD (Binary-Coded Decimal) Adder is a circuit that adds two decimal digits, represented in BCD
format, along with a carry input. BCD uses 4 bits to represent decimal digits 0-9. When the sum of
two BCD digits exceeds 9 (i.e., 1001 in binary), a correction is required to convert the result back
into a valid BCD digit. This correction involves adding 6 (binary 0110) to the result.

A multi-digit BCD adder can be created by cascading multiple single-digit BCD adders. Each BCD
adder handles one digit of the input numbers, and the carry-out from one digit's addition becomes
the carry-in for the next higher digit's addition.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:

TCL CONSOLE:
SCHEMATIC:

16 BIT BCD ADDER:

BCD ADDER:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 36
AIM: TO IMPLEMENT FIBONACCI GENERATOR USING VERILOG IN VIVADO

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 37
AIM: TO IMPLEMENT 2 FLIP FLOP SYNCHRONIZER USING VERILOG IN VIVADO

Key Concepts in Synchronization

1. Clock Domain Crossing (CDC):

o CDC refers to the scenario where data or control signals move from one clock
domain to another. These clock domains can operate at different frequencies or have
completely unrelated clocks.

o Transferring signals between clock domains without proper synchronization can lead
to timing errors and metastability.

2. Metastability:

o Metastability occurs when a flip-flop or latch captures a signal that is transitioning

between logic levels (high or low) at the exact moment the clock edge occurs.

o This can result in an undefined or unstable output, where the flip-flop takes an
indeterminate amount of time to resolve to a valid logic level.

o The key goal of synchronization is to reduce the likelihood of metastability affecting

the system.

3. Synchronization Techniques:

o Various techniques are used to safely transfer data or signals between clock
domains, preventing metastability and data loss.

Two-Flip-Flop Synchronizer (Single-bit Synchronization):

The simplest and most commonly used method for synchronizing a single-bit signal between
different clock domains.

How it works:

• A signal from the source clock domain is passed through two flip-flops, both operating in the
destination clock domain.

• The first flip-flop captures the asynchronous signal, and the second flip-flop provides time for
the signal to stabilize if it encounters metastability.
RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 38
AIM: To Implement n-bit synchronizer (Handshake protocol)

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:

SCHEMATIC:
POWER ANALYSIS:

How the Handshake Protocol Works:

The handshake protocol is a synchronization mechanism often used in digital systems, especially
when transferring data between different clock domains. It ensures that data is transferred reliably
from a sender (source) to a receiver (destination) without any loss, corruption, or timing errors,
especially when the clocks in both domains are asynchronous or have different frequencies.

Basic Concept:

• The sender asserts a signal (req or request) to indicate that it has valid data to send.

• The receiver responds by asserting an acknowledgment signal (ack) once it has received
the data.

• The sender deasserts its request (req) after it detects the acknowledgment (ack), ensuring
that the receiver has processed the data.

• The receiver also deasserts ack once the handshake cycle is complete, preparing for the
next data transfer.

This protocol guarantees that data is correctly synchronized across clock domains before the next
data transaction begins.

Working of the Handshake Protocol:

1. Initial State:

o The sender and receiver are both idle. The req and ack signals are both deasserted
(0).
2. Sender Asserts req (Request):

o When the sender has valid data ready to send, it asserts the req signal. This tells
the receiver that there is data available for transfer.

o The sender holds the req signal high (1) until the receiver acknowledges that it has
received the data.

3. Receiver Detects req and Asserts ack (Acknowledge):

o The receiver, operating in its own clock domain, continuously monitors the req
signal.

o Once the receiver detects the req signal (indicating valid data from the sender), it
latches the data and asserts the ack signal.

o The ack signal indicates to the sender that the data has been successfully received.

4. Sender Detects ack and Deasserts req:

o When the sender detects the ack signal, it knows that the receiver has received the
data. The sender can now deassert the req signal, indicating that the current data
transfer cycle is complete.

o After deasserting req, the sender prepares for the next data transaction.

5. Receiver Deasserts ack:

o Once the receiver detects that the req signal has been deasserted, it deasserts the
ack signal. This prepares the receiver to handle the next data transfer.

6. Cycle Repeats:

o The handshake cycle repeats for each new piece of data. The sender asserts req,
the receiver acknowledges with ack, and the process continues, ensuring reliable
data transfer between the two clock domains.
 50 DAYS OF RTL CHALLENGE
DAY 39
AIM: To Implement Master Slave JK Flipflop (asynchronous reset);

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 40
AIM: To Implement Mod – N counter

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 41
AIM: To Implement multibit(4-bit) JK FlipFlop(asynchronous reset)

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:
POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 42
AIM: To implement Parallel to Serial Converter(8-bit) in vivado using verilog

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:

SCHEMATIC:
POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 43
AIM: To implement Pseudo Random Sequence Generator (Linear Feedback Shift Register) in Vivado
using Verilog

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:

Explanation:

1. Feedback Calculation: feedback is obtained by XORing the output of the 3rd and 4th bits.

2. Shift and Update: At each clock edge, the LFSR shifts left, and the feedback bit is inserted
into the least significant position (bit 0).

3. Initial State: On reset, the LFSR is initialized to 0001, which prevents it from getting stuck in
 50 DAYS OF RTL CHALLENGE
DAY 44
AIM: To implement Clock Phasing in Vivado using Verilog

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 45
AIM: To implement Asynchronous FIFO in Vivado using Verilog

RTL DESIGN:
SIMULATION RESULTS:

POWER ANALYSIS:
SCHEMATIC:
 50 DAYS OF RTL CHALLENGE
DAY 46
AIM: To generate triangle wave in Vivado using Verilog.

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 47
AIM: To Implement Ring oscillator using Verilog

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:
 50 DAYS OF RTL CHALLENGE
DAY 48
AIM: To calculate GCD of 2 N bit numbers in Verilog(Behavioural) using Euclidean Algorithm.

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:

POWER ANALYSIS:
 50 DAYS OF RTL CHALLENGE
DAY 49
AIM: To Implement Fixed Priority Arbiter using verilog

RTL DESIGN:

TEST BENCH:
SIMULATION RESULTS:

SCHEMATIC:
 50 DAYS OF RTL CHALLENGE
DAY 50
AIM: To Implement Round Robin Arbiter using Verilog in Vivado.

RTL DESIGN:
TEST BENCH:

SIMULATION RESULTS:
ELABORATED DESIGN:

POWER ANALYSIS:
Thank You