DS2252T

DS2252T
Secure Microcontroller Module

FEATURES PACKAGE OUTLINE

• 8051 compatible microcontroller for secure/sensitive
applications
– 32K, 64K, or 128K bytes of nonvolatile SRAM
for program and/or data storage
– In–system programming via on–chip serial port 1 20 21 40
– Capable of modifying its own program or data
memory in the end system
40–PIN SIMM
• Firmware Security Features:
– Memory stored in encrypted form
– Encryption using on–chip 64–bit key DESCRIPTION
The DS2252T is an 8051 compatible microcontroller
– Automatic true random key generator
based on nonvolatile RAM technology. It is designed for
– SDI Self Destruct Input systems that need to protect memory contents from dis-
– Improved security over previous generations closure. This includes key data, sensitive algorithms,
– Protects memory contents from piracy and proprietary information of all types. Like other mem-
• Crashproof Operation bers of the Secure Microcontroller family, it provides full
compatibility with the 8051 instruction set, timers, serial
– Maintains all nonvolatile resources for over 10
port, and parallel I/O ports. By using NV RAM instead of
years in the absence of power
ROM, the user can program, then reprogram the micro-
– Power–fail Reset
controller while in–system. This allows frequent chang-
– Early Warning Power–fail Interrupt
ing of sensitive processes with minimal effort. The
– Watchdog Timer DS2252T provides an array of mechanisms to prevent
– Precision reference for power monitor an attacker from examining the memory. It is designed
• Fully 8051 Compatible to resist all levels of threat including observation, analy-
sis, and physical attack. As a result, a massive effort
– 128 bytes scratchpad RAM
would be required to obtain any information about
– Two timer/counters
memory contents. Furthermore, the “Soft” nature of the
– On–chip serial port DS2252T allows frequent modification of secure
– 32 parallel I/O port pins information. This minimizes that value of any informa-
• Permanently powered real time clock tion that is obtained.

021998 1/15
 DS2252T

Using a security system based on the DS5002FP, the Power–fail Reset, Power–fail Interrupt, and Watchdog
DS2252T protects the memory contents from disclo- Timer. All nonvolatile memory and resources are main-
sure. It loads program memory via its serial port and tained for over 10 years at room temperature in the
encrypts it in real–time prior to storing it in SRAM. Once absence of power.
encrypted, the RAM contents and the program flow are
unintelligible. The real data exists only inside the pro- A user loads programs into the DS2252T via its on–chip
cessor chip after being decrypted. Any attempt to dis- Serial Bootstrap Loader. This function supervises the
cover the on–chip data, encryption keys, etc., results in loading of software into NV RAM, validates it, then
its destruction. Extensive use of nonvolatile lithium becomes transparent to the user. It also manages the
backed technology create a microcontroller that retains loading of new encryption keys automatically. Software
data for over 10 years at room temperature, but which is stored in on–board CMOS SRAM. Using its internal
can be erased instantly if tampered with. The DS2252T Partitioning, the DS2252T can divide a common RAM
even interfaces directly to external tamper protection into user selectable program and data segments. This
hardware. Partition can be selected at program loading time, but
can be modified anytime later. The microcontroller will
The DS2252T provides a permanently powered real decode memory access to the SRAM, access memory
time lock with interrupts for time stamp and date. It via its Byte–wide bus and write–protect the memory por-
keeps time to one hundredth of a second using its on– tion designated as program (ROM).
board 32 KHz crystal.
A detailed summary of the security features is provided
Like other Secure Microcontrollers in the family, the in the User’s Guide section of the Secure Microcontrol-
DS2252T provides crashproof operation in portable ler data book. An overview is also available in the
systems or systems with unreliable power. These fea- DS5002FP data sheet.
tures include the ability to save the operating state,

ORDERING INFORMATION
PART NUMBER RAM SIZE MAX CRYSTAL SPEED TIMEKEEPING?
DS2252T–32–16 32K bytes 16 MHz Yes
DS2252T–64–16 64K bytes 16 MHz Yes
DS2252T–128–16 128K bytes 16 MHz Yes

Operating information is contained in the User’s Guide section of the Secure Microcontroller Data Book. This data
sheet provides ordering information, pinout, and electrical specifications.

021998 2/15
 DS2252T

DS2252T BLOCK DIAGRAM Figure 1

DS2252T

+3V

VCC
VCCO

RST

ÏÏÏÏÏÏÏ
BYTE–WIDE
ALE ADDRESS BUS

ÏÏÏÏÏÏÏ
XTAL1 32K OR 128K
SRAM

ÏÏÏÏÏÏÏ
XTAL2
BYTE–WIDE

ÏÏÏÏÏÏÏ
DATA BUS
GND
DS5002FP

PROG

SDI ÏÏÏÏÏÏÏ
CE1

ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏ
R/W

ÏÏÏÏÏÏ ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
P0.0–0.7

ÏÏÏÏÏÏ
ÏÏÏÏÏÏ ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
P1.0–1.7

ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
P2.0–2.7

ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
32K
SRAM
(–64 only)

ÏÏÏÏÏÏ ÏÏÏÏÏÏÏ
P3.0–3.7 CE2

ÏÏÏÏÏÏÏ
PE1

ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ DS1283
REAL TIME
CLOCK

P3.2 INTP

021998 3/15
DS2252T

PIN ASSIGNMENT
1 P1.0 11 P1.5 21 P3.1 TXD 31 P3.6 WR
2 VCC 12 P0.4 22 ALE 32 P2.4
3 P1.1 13 P1.6 23 P3.2 INT0 33 P3.7 RD
4 P0.0 14 P0.5 24 PROG 34 P2.3
5 P1.2 15 P1.7 25 P3.3 INT1 35 XTAL2
6 P0.1 16 P0.6 26 P2.7 36 P2.2
7 P1.3 17 RST 27 P3.4 T0 37 XTAL1
8 P0.2 18 P0.7 28 P2.6 38 P2.1
9 P1.4 19 P3.0 RXD 29 P3.5 T1 39 GND
10 P0.3 20 SDI 30 P2.5 40 P2.0

PIN DESCRIPTION
PIN DESCRIPTION
4, 6, 8, 10, P0.0 – P0.7. General purpose I/O Port 0. This port is open–drain and can not drive a logic 1.
12, 14, 16, 18 It requires external pull–ups. Port 0 is also the multiplexed Expanded Address/Data bus. When
used in this mode, it does not require pull–ups.
1, 3, 5, 7, 9, P1.0 – P1.7. General purpose I/O Port 1.
11, 13, 15
40, 38, 36, P2.0 – P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address bus.
34, 32, 30,
28, 26
19 P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on board
UART. This pin should NOT be connected directly to a PC COM port.
21 P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on board
UART. This pin should NOT be connected directly to a PC COM port.
23 P3.2 INT0. General purpose I/O port pin 3.2. Also serves as the active low External Interrupt
0. This pin is also connected to the INTP output of the DS1283 Real Time Clock.
25 P3.3 INT1. General purpose I/O port pin 3.3. Also serves as the active low External
Interrupt 1.
27 P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input.
29 P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input.
31 P3.6 WR. General purpose I/O port pin. Also serves as the write strobe for Expanded bus opera-
tion.
33 P3.7 RD. General purpose I/O port pin. Also serves as the read strobe for Expanded bus opera-
tion.
17 RST – Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin
is pulled down internally, can be left unconnected if not used. An RC power–on reset circuit is
not needed and is NOT recommended.
22 ALE – Address Latch Enable. Used to de–multiplex the multiplexed Expanded Address/Data
bus on Port 0. This pin is normally connected to the clock input on a ’373 type transparent latch.

021998 4/15
 DS2252T

PIN DESCRIPTION
35, 37 XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is the input
to an inverting amplifier and XTAL2 is the output.
39 GND – Logic ground.
2 VCC – +5V.
24 PROG – Invokes the Bootstrap loader on a falling edge. This signal should be debounced so
that only one edge is detected. If connected to ground, the microcontroller will enter Bootstrap
loading on power up. This signal is pulled up internally.
20 SDI – Self Destruct Input. A logic 1 applied to this input causes a hardware unlock. This involves
the destruction of Encryption Keys, Vector RAM, and the momentary removal of power from
VCCO. This pin should be grounded if not used.

INSTRUCTION SET are available to the Byte–wide bus. This preserves the
The DS2252T executes an instruction set that is object I/O ports for application use. An alternate configuration
code compatible with the industry standard 8051 micro- allows dynamic Partitioning of a 64K space as shown in
controller. As a result, software development packages Figure 3. Any data area not mapped into the NV RAM is
such as assemblers and compilers that have been writ- reached via the Expanded bus on Ports 0 and 2. Off–
ten for the 8051 are compatible with the DS2252T. A board program memory is not available for security rea-
complete description of the instruction set and operation sons. Selecting PES=1 provides access to the Real
are provided in the User’s Guide section of the Secure Time Clock as shown in Figure 4. These selections are
Microcontroller Data Book. made using Special Function Registers. The memory
map and its controls are covered in detail in the User’s
Guide section of the Secure Microcontroller Data Book.
MEMORY ORGANIZATION
Figure 2 illustrates the memory map accessed by the
DS2252T. The entire 64K of program and 64K of data

021998 5/15
DS2252T

DS2252T MEMORY MAP IN NON–PARTITIONABLE MODE (PM=1) Figure 2

ÉÉÉÉÉÉ ÉÉÉÉÉ
PROGRAM MEMORY DATA MEMORY (MOVX)
FFFFh 64K

ÉÉÉÉÉÉ
ÉÉÉÉÉÉ ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
NV RAM
PROGRAM
ÉÉÉÉÉ
ÉÉÉÉÉ
NV RAM
DATA

ÉÉÉÉÉÉ
ÉÉÉÉÉÉ ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ ÉÉÉÉÉ
ÉÉÉÉÉ
0000h
ÉÉÉÉÉÉ ÉÉÉÉÉ
DS2252T MEMORY MAP IN PARTITIONABLE MODE (PM=0) Figure 3

ÎÎÎÎÎ ÉÉÉÉÉ
PROGRAM MEMORY DATA MEMORY (MOVX)

ÎÎÎÎÎ ÉÉÉÉÉ
FFFFh

ÎÎÎÎÎ
ÎÎÎÎÎ ÉÉÉÉÉ
ÉÉÉÉÉ
ÎÎÎÎÎ ÉÉÉÉÉ
NV RAM
DATA

ÎÎÎÎÎ ÉÉÉÉÉ
ÎÎÎÎÎ ÉÉÉÉÉ
ÎÎÎÎÎ
ÉÉÉÉÉ ÉÉÉÉÉ
PARTITION
ÎÎÎÎÎ
ÉÉÉÉÉ ÉÉÉÉÉ
ÉÉÉÉÉ
NV RAM
PROGRAM

0000h ÉÉÉÉÉ
NOTE: PARTITIONABLE MODE IS NOT SUPPORTED ON THE 128KB VERSION OF THE DS2252T.

ÉÉ ÎÎ
LEGEND:

ÉÉ ÎÎ
= NV RAM MEMORY = NOT AVAILABLE

= EXPANDED BUS (PORTS 0 AND 2)

021998 6/15
 DS2252T

DS2252T MEMORY MAP WITH (PES=1) Figure 4

ÎÎÎÎÎÎ ÎÎÎÎÎÎ
PROGRAM MEMORY DATA MEMORY (MOVX)
FFFFh 64K

ÎÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
C000h

ÎÎÎÎÎÎ
ÏÏÏÏÏÏ
ÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÏÏÏÏÏÏ ÎÎÎÎÎÎ
PARTITION

8000h

ÏÏÏÏÏÏ
ÏÏÏÏÏÏ ÎÎÎÎÎÎ
ÏÏÏÏÏÏ
NV RAM
PROGRAM ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÏÏÏÏÏÏ
4000h 16K

ÏÏÏÏÏÏ REAL–TIME

ÏÏÏÏÏÏ
CLOCK

0000h

ÎÎ
ÎÎ NOT ACCESSIBLE

POWER MANAGEMENT performed unless power rises back above VCCMIN. All
The DS2252T monitors VCC to provide Power–fail decoded chip enables and the R/W signal go to an inac-
Reset, early warning Power–fail Interrupt, and switch tive (logic 1) state. VCC is still the power source at this
over to lithium backup. It uses an internal band–gap ref- time. When VCC drops further to below VLI, internal cir-
erence in determining the switch points. These are cuitry will switch to the built–in lithium cell for power. The
called VPFW, VCCMIN, and VLI respectively. When VCC majority of internal circuits will be disabled and the
drops below VPFW, the DS2252T will perform an inter- remaining nonvolatile states will be retained. The
rupt vector to location 2Bh if the power–fail warning was User’s Guide has more information on this topic. The trip
enabled. Full processor operation continues regard- points VCCMIN and VPFW are listed in the electrical spec-
less. When power falls further to VCCMIN, the DS2252T ifications.
invokes a reset state. No further code execution will be

021998 7/15
DS2252T

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground –0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature –40°C to +70°C
Soldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.

DC CHARACTERISTICS (tA=0°C to 70°C; VCC=5V ± 10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Low Voltage VIL –0.3 +0.8 V 1
Input High Voltage VIH1 2.0 VCC+0.3 V 1
Input High Voltage (RST, XTAL1, VIH2 3.5 VCC+0.3 V 1
PROG)
Output Low Voltage VOL1 0.15 0.45 V 1
@ IOL=1.6 mA (Ports 1, 2, 3)
Output Low Voltage VOL2 0.15 0.45 V 1
@ IOL=3.2 mA (Ports 0, ALE)
Output High Voltage VOH1 2.4 4.8 V 1
@ IOH=–80 µA (Ports 1, 2, 3)
Output High Voltage VOH2 2.4 4.8 V 1
@ IOH=–400 µA (Ports 0, ALE)
Input Low Current VIN=0.45V IIL –50 µA
(Ports 1, 2, 3)
Transition Current; 1 to 0 ITL –500 µA
VIN=2.0V (Ports 1, 2, 3)
Input Leakage Current IIL ±10 µA
0.45<VIN<VCC (Port 0)
RST Pulldown Resistor RRE 40 150 KΩ
Power Fail Warning Voltage VPRW 4.25 4.37 4.50 V 1
Minimum Operating Voltage VCCMIN 4.00 4.12 4.25 V 1
Operating Current @ 16 MHz ICC 45 mA 4
Idle Mode Current @ 12 MHz IIDLE 7.0 mA 5
Stop Mode current ISTOP 80 µA 6
Pin Capacitance CIN 10 pF 7
Reset Trip Point in Stop Mode V 1
w/BAT=3.0V 4.0 4.25
w/BAT=3.3V 4.4 4.65
SDI Input Low Voltage VILS 0.4 V 1
SDI Input High Voltage VIHS 2.0 VCC V 1, 2
SDI Input High Voltage VIHS 2.0 3.5 V 1, 2
SDI Pull–Down Resistor RSDI 25 60 KΩ

021998 8/15
 DS2252T

AC CHARACTERISTICS (tA = 0°C to70°C; VCC=0V to 5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
SDI Pulse Reject
(4.5V<VCC<5.5V) tSPR 2 µs 10
(VCC=0V, VBAT=2.9V) 4

SDI Pulse Accept

(4.5V<VCC<5.5V) tSPA 10 µs 10
(VCC=0V, VBAT=2.9V) 50

AC CHARACTERISTICS
EXPANDED BUS MODE TIMING SPECIFICATIONS (tA = 0°C to70°C; VCC = 5V + 10%)
# PARAMETER SYMBOL MIN MAX UNITS
1 Oscillator Frequency 1/tCLK 1.0 16 (–16) MHz
2 ALE Pulse Width tALPW 2tCLK–40 ns
3 Address Valid to ALE Low tAVALL tCLK–40 ns
4 Address Hold After ALE Low tAVAAV tCLK–35 ns
14 RD Pulse Width tRDPW 6tCLK–100 ns
15 WR Pulse Width tWRPW 6tCLK–100 ns
16 RD Low to Valid Data In @12 MHz tRDLDV 5tCLK–165 ns
@16 MHz 5tCLK–105 ns

17 Data Hold after RD High tRDHDV 0 ns

18 Data Float after RD High tRDHDZ 2tCLK–70 ns
19 ALE Low to Valid Data In @12 MHz tALLVD 8tCLK–150 ns
@16 MHz 8tCLK–90 ns
20 Valid Addr. to Valid Data In @12 MHz tAVDV 9tCLK–165 ns
@16 MHz 9tCLK–105 ns
21 ALE Low to RD or WR Low tALLRDL 3tCLK–50 3tCLK+50 ns
22 Address Valid to RD or WR Low tAVRDL 4tCLK–130 ns
23 Data Valid to WR Going Low tDVWRL tCLK–60 ns
24 Data Valid to WR High @12 MHz tDVWRH 7tCLK–150 ns
@16 MHz 7tCLK–90 ns
25 Data Valid after WR High tWRHDV tCLK–50 ns
26 RD Low to Address Float tRDLAZ 0 ns
27 RD or WR High to ALE High tRDHALH tCLK–40 tCLK+50 ns

021998 9/15
DS2252T

EXPANDED DATA MEMORY READ CYCLE

2
27

ALE

19
21 14

RD 16
18

3 26
4 17

A7–A0 DATA IN A7–A0 INSTR

PORT 0 (Rn OR DPL) (PCL) IN

22

20

PORT 2 P2.7–P2.0 OR A15–A8 FROM DPH A15–A8 FROM PCH

EXPANDED DATA MEMORY WRITE CYCLE

27

ALE

21
15

WR

23 25

3 4 24

A7–A0 A7–A0 INSTR

PORT 0 (Rn OR DPL) DATA OUT (PCL) IN

22

PORT 2 P2.7–P2.0 OR A15–A8 FROM DPH A15–A8 FROM PCH

021998 10/15
 DS2252T

AC CHARACTERISTICS (cont’d)
EXTERNAL CLOCK DRIVE (tA = 0°C to70°C; VCC = 5V + 10%)
# PARAMETER SYMBOL MIN MAX UNITS
28 External Clock High Time @12 MHz tCLKHPW 20 ns
@16 MHz 15 ns

29 External Clock Low Time @12 MHz tCLKLPW 20 ns

@16 MHz 15 ns
30 External Clock Rise Time @12 MHz tCLKR 20 ns
@16 MHz 15 ns
31 External Clock Fall Time @12 MHz tCLKF 20 ns
@16 MHz 15 ns

EXTERNAL CLOCK TIMING

28
29

30

31

AC CHARACTERISTICS (cont’d)
POWER CYCLING TIMING (tA = 0°C to70°C; VCC = 5V + 10%)
# PARAMETER SYMBOL MIN MAX UNITS
32 Slew Rate from VCCMIN to 3.3V tF 130 µs
33 Crystal Start–up Time tCSU (note 8)
34 Power–On Reset Delay tPOR 21504 tCLK

021998 11/15
DS2252T

POWER CYCLE TIMING

VCC
VPFW

VCCMIN

VLI

32

INTERRUPT
SERVICE
ROUTINE

33

CLOCK
OSC

34

INTERNAL
RESET

LITHIUM
CURRENT

AC CHARACTERISTICS (cont’d)
SERIAL PORT TIMING – MODE 0 (tA = 0°C to70°C; VCC = 5V + 10%)
# PARAMETER SYMBOL MIN MAX UNITS
35 Serial Port Clock Cycle Time tSPCLK 12tCLK µs
36 Output Data Setup to Rising Clock Edge tDOCH 10tCLK–133 ns
37 Output Data Hold after Rising Clock Edge tCHDO 2tCLK–117 ns
38 Clock Rising Edge to Input Data Valid tCHDV 10tCLK–133 ns
39 Input Data Hold after Rising Clock Edge tCHDIV 0 ns

021998 12/15
 DS2252T

SERIAL PORT TIMING – MODE 0

INSTRUCTION

0 1 2 3 4 5 6 7 8

ALE

35

CLOCK

36
37

DATA OUT 0 1 2 3 4 5 6 7 SET TI

WRITE TO
SBUF REGISTER
39
38

INPUT DATA SET RI

VALID VALID VALID VALID VALID VALID VALID

CLEAR RI

NOTES:
1. All voltage referenced to ground.

2. SDI should be taken to a logic high when VCC=+5V, and to approximately 3V when VCC<3V.

3. SDI is deglitched to prevent accidental destruction. The pulse must be longer than tSPR to pass the deglitcher,
but SDI is not guaranteed unless it is longer than tSPA.

4. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF=10 ns,
VIL = 0.5V; XTAL2 disconnected; RST = PORT0 = VCC.

5. Idle mode IIDLE is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10 ns, VIL = 0.5V;
XTAL2 disconnected; PORT0 = VCC, RST = VSS.

6. Stop mode ISTOP is measured with all output pins disconnected; PORT0 = VCC; XTAL2 not connected; RST =
XTAL1 = VSS.

7. Pin capacitance is measured with a test frequency – 1 MHz, tA = 25°C.

8. Crystal start–up time is the time required to get the mass of the crystal into vibrational motion from the time that
power is first applied to the circuit until the first clock pulse is produced by the on–chip oscillator. The user should
check with the crystal vendor for a worst case specification on this time.

021998 13/15
DS2252T

PACKAGE DRAWING
P

(SIDE B) O

(SIDE A) N

U3 U1B
U1A U2

(SIDE B) C

M D
CL
E

G
I I H

F
PKG INCHES

DIM MIN MAX

A 2.645 2.655

B 2.379 2.389

C 0.995 1.005

D 0.395 0.405

E 0.245 0.255

F 0.050 BSC

G 0.075 0.085

H 0.245 0.255

I 0.950 BSC

J 0.120 0.130

K 1.320 1.330

L 1.445 1.455

M 0.057 0.067

N – 0.300

O – 0.165

P 0.047 0.054

021998 14/15
 DS2252T

DATA SHEET REVISION SUMMARY

The following represent the key differences between 12/13/95 and 08/16/96 version of the DS2252T data sheet.
Please review this summary carefully.

1. Change VCC slew rate specification to reference 3.3V instead of VLI.

2. Add minimum value to PCB thickness.

The following represent the key differences between 08/16/96 and 05/28/97 version of the DS2252T data sheet.
Please review this summary carefully.

1. AC characteristics for battery–backed SDI pulse specification added.

021998 15/15