M29F200BT

M29F200BB
2 Mbit (256Kb x8 or 128Kb x16, Boot Block)
Single Supply Flash Memory
PRELIMINARY DATA

■ SINGLE 5V±10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS
■ ACCESS TIME: 45ns
■ PROGRAMMING TIME
– 8µs per Byte/Word typical
44
■ 7 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 4 Main Blocks 1

■ PROGRAM/ERASE CONTROLLER TSOP48 (N) SO44 (M)

12 x 20mm
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
Figure 1. Logic Diagram
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND VCC
– Faster Production/Batch Programming
■ TEMPORARY BLOCK UNPROTECTION
17 15
MODE
■ LOW POWER CONSUMPTION A0-A16 DQ0-DQ14

– Standby and Automatic Standby

W DQ15A–1
■ 100,000 PROGRAM/ERASE CYCLES per M29F200BT
BLOCK E M29F200BB BYTE

■ 20 YEARS DATA RETENTION G RB

– Defectivity below 1 ppm/year RP
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– M29F200BT Device Code: 00D3h
– M29F200BB Device Code: 00D4h VSS
AI02912

October 1999 1/22

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M29F200BT, M29F200BB

Figure 2A. TSOP Connections Figure 2B. SO Connections

A15 1 48 A16
A14 BYTE NC 1 44 RP
A13 VSS RB 2 43 W
A12 DQ15A–1 NC 3 42 A8
A11 DQ7 A7 4 41 A9
A10 DQ14 A6 5 40 A10
A9 DQ6 A5 6 39 A11
A8 DQ13 A4 7 38 A12
NC DQ5 A3 8 37 A13
NC DQ12 A2 9 36 A14
W DQ4 A1 10 35 A15
RP 12 37 VCC A0 11 M29F200BT 34 A16
M29F200BT
NC 13 M29F200BB 36 DQ11 E 12 M29F200BB 33 BYTE
NC DQ3 VSS 13 32 VSS
RB DQ10 G 14 31 DQ15A–1
NC DQ2 DQ0 15 30 DQ7
NC DQ9 DQ8 16 29 DQ14
A7 DQ1 DQ1 17 28 DQ6
A6 DQ8 DQ9 18 27 DQ13
A5 DQ0 DQ2 19 26 DQ5
A4 G DQ10 20 25 DQ12
A3 VSS DQ3 21 24 DQ4
A2 E DQ11 22 23 VCC
AI02914
A1 24 25 A0
AI02913

Table 1. Signal Names SUMMARY DESCRIPTION

A0-A16 Address Inputs
The M29F200B is a 2 Mbit (256Kb x8 or 128Kb
x16) non-volatile memory that can be read, erased
DQ0-DQ7 Data Inputs/Outputs and reprogrammed. These operations can be per-
formed using a single 5V supply. On power-up the
DQ8-DQ14 Data Inputs/Outputs memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM. The
DQ15A–1 Data Input/Output or Address Input M29F200B is fully backward compatible with the
M29F200.
E Chip Enable
The memory is divided into blocks that can be
G Output Enable
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
W Write Enable be protected independently to prevent accidental
Program or Erase commands from modifying the
RP Reset/Block Temporary Unprotect memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
RB Ready/Busy Output on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
BYTE Byte/Word Organization Select taking care of all of the special operations that are
required to update the memory contents. The end
VCC Supply Voltage of a program or erase operation can be detected
and any error conditions identified. The command
VSS Ground set required to control the memory is consistent
with JEDEC standards.
NC Not Connected Internally

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 M29F200BT, M29F200BB

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit
Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C
TA Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C
Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C
TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage –0.6 to 6 V

VCC Supply Voltage –0.6 to 6 V

VID Identification Voltage –0.6 to 13.5 V
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

The blocks in the memory are asymmetrically ar- sent to the Command Interface of the internal state
ranged, see Tables 3A and 3B, Block Addresses. machine.
The first or last 64 Kbytes have been divided into Data Inputs/Outputs (DQ8-DQ14). The Data In-
four additional blocks. The 16 Kbyte Boot Block puts/Outputs output the data stored at the selected
can be used for small initialization code to start the address during a Bus Read operation when BYTE
microprocessor, the two 8 Kbyte Parameter is High, VIH. When BYTE is Low, VIL, these pins
Blocks can be used for parameter storage and the are not used and are high impedance. During Bus
remaining 32K is a small Main Block where the ap- Write operations the Command Register does not
plication may be stored. use these bits. When reading the Status Register
Chip Enable, Output Enable and Write Enable sig- these bits should be ignored.
nals control the bus operation of the memory. Data Input/Output or Address Input (DQ15A-1).
They allow simple connection to most micropro-
When BYTE is High, V IH, this pin behaves as a
cessors, often without additional logic.
Data Input/Output pin (as DQ8-DQ14). When
The memory is offered in TSOP48 (12 x 20mm) BYTE is Low, VIL, this pin behaves as an address
and SO44 packages. Access times of 45ns, 55ns, pin; DQ15A–1 Low will select the LSB of the Word
70ns and 90ns are available. The memory is sup- on the other addresses, DQ15A–1 High will select
plied with all the bits erased (set to ’1’). the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
SIGNAL DESCRIPTIONS BYTE is High and references to the Address In-
See Figure 1, Logic Diagram, and Table 1, Signal puts to include this pin when BYTE is Low except
Names, for a brief overview of the signals connect- when stated explicitly otherwise.
ed to this device. Chip Enable (E). The Chip Enable, E, activates
Address Inputs (A0-A16). The Address Inputs the memory, allowing Bus Read and Bus Write op-
select the cells in the memory array to access dur- erations to be performed. When Chip Enable is
ing Bus Read operations. During Bus Write opera- High, VIH, all other pins are ignored.
tions they control the commands sent to the Output Enable (G). The Output Enable, G, con-
Command Interface of the internal state machine. trols the Bus Read operation of the memory.
Data Inputs/Outputs (DQ0-DQ7). The Data In- Write Enable (W). The Write Enable, W, controls
puts/Outputs output the data stored at the selected the Bus Write operation of the memory’s Com-
address during a Bus Read operation. During Bus mand Interface.
Write operations they represent the commands

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M29F200BT, M29F200BB

Table 3A. M29F200BT Block Addresses Table 3B. M29F200BB Block Addresses
Size Address Range Address Range Size Address Range Address Range
(Kbytes) (x8) (x16) (Kbytes) (x8) (x16)
16 3C000h-3FFFFh 1E000h-1FFFFh 64 30000h-3FFFFh 18000h-1FFFFh
8 3A000h-3BFFFh 1D000h-1DFFFh 64 20000h-2FFFFh 10000h-17FFFh
8 38000h-39FFFh 1C000h-1CFFFh 64 10000h-1FFFFh 08000h-0FFFFh
32 30000h-37FFFh 18000h-1BFFFh 32 08000h-0FFFFh 04000h-07FFFh
64 20000h-2FFFFh 10000h-17FFFh 8 06000h-07FFFh 03000h-03FFFh
64 10000h-1FFFFh 08000h-0FFFFh 8 04000h-05FFFh 02000h-02FFFh
64 00000h-0FFFFh 00000h-07FFFh 16 00000h-03FFFh 00000h-01FFFh

Reset/Block Temporary Unprotect (RP). The Re- Read/Reset commands or Hardware Resets until
set/Block Temporary Unprotect pin can be used to the memory is ready to enter Read mode.
apply a Hardware Reset to the memory or to tem- The use of an open-drain output allows the Ready/
porarily unprotect all Blocks that have been pro- Busy pins from several memories to be connected
tected. to a single pull-up resistor. A Low will then indicate
A Hardware Reset is achieved by holding Reset/ that one, or more, of the memories is busy.
Block Temporary Unprotect Low, VIL, for at least Byte/Word Organization Select (BYTE). The Byte/
tPLPX. After Reset/Block temporary unprotect goes Word Organization Select pin is used to switch be-
High, VIH, the memory will be ready for Bus Read tween the 8-bit and 16-bit Bus modes of the mem-
and Bus Write operations after tPHEL or tRHEL, ory. When Byte/Word Organization Select is Low,
whichever occurs last. See the Ready/Busy Out- VIL, the memory is in 8-bit mode, when it is High,
put section, Table 14 and Figure 10, Reset/Tem- VIH, the memory is in 16-bit mode.
porary Unprotect AC Characteristics for more
details. VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
Holding RP at V ID will temporarily unprotect the gram, Erase etc.).
protected Blocks in the memory. Program and
The Command Interface is disabled when the VCC
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
tPHPHH.
cidentally damaging the data during power up,
Ready/Busy Output (RB). The Ready/Busy pin power down and power surges. If the Program/
is an open-drain output that can be used to identify Erase Controller is programming or erasing during
when the memory array can be read. Ready/Busy this time then the operation aborts and the memo-
is high-impedance during Read mode, Auto Select ry contents being altered will be invalid.
mode and Erase Suspend mode.
A 0.1µF capacitor should be connected between
After a Hardware Reset, Bus Read and Bus Write the VCC Supply Voltage pin and the VSS Ground
operations cannot begin until Ready/Busy be- pin to decouple the current surges from the power
comes high-impedance. See Table 14 and Figure supply. The PCB track widths must be sufficient to
10, Reset/Temporary Unprotect AC Characteris- carry the currents required during program and
tics. erase operations, I CC4.
During Program or Erase operations Ready/Busy Vss Ground. The VSS Ground is the reference
is Low, VOL. Ready/Busy will remain Low during for all voltage measurements.

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 M29F200BT, M29F200BB

Table 4A. Bus Operations, BYTE = VIL

Address Inputs Data Inputs/Outpu ts
Operation E G W
DQ15A–1, A0-A16 DQ14-DQ8 DQ7-DQ0

Bus Read VIL VIL V IH Cell Address Hi-Z Data Output

Bus Write VIL VIH VIL Command Address Hi-Z Data Input

Output Disable X VIH V IH X Hi-Z Hi-Z

Standby V IH X X X Hi-Z Hi-Z

Read Manufacturer A0 = VIL, A1 = VIL, A9 = VID,

VIL VIL V IH Hi-Z 20h
Code Others VIL or VIH

A0 = VIH, A1 = VIL, A9 = VID, D3h (M29F200BT)

Read Device Code VIL VIL V IH Hi-Z
Others VIL or VIH D4h (M29F200BB)
Note: X = VIL or VIH.

Table 4B. Bus Operations, BYTE = VIH

Address Inputs Data Inputs/Outpu ts
Operation E G W
A0-A16 DQ15A–1, DQ14-DQ0

Bus Read VIL VIL V IH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable X VIH V IH X Hi-Z

Standby V IH X X X Hi-Z

Read Manufacturer A0 = VIL, A1 = VIL, A9 = VID,

VIL VIL V IH 0020h
Code Others VIL or VIH

A0 = VIH, A1 = VIL, A9 = VID, 00D3h (M29F200BT)

Read Device Code VIL VIL V IH
Others VIL or VIH 00D4h (M29F200BB)
Note: X = VIL or VIH.

BUS OPERATIONS Bus Write. Bus Write operations write to the

There are five standard bus operations that control Command Interface. A valid Bus Write operation
the device. These are Bus Read, Bus Write, Out- begins by setting the desired address on the Ad-
put Disable, Standby and Automatic Standby. See dress Inputs. The Address Inputs are latched by
Tables 4A and 4B, Bus Operations, for a summa- the Command Interface on the falling edge of Chip
ry. Typically glitches of less than 5ns on Chip En- Enable or Write Enable, whichever occurs last.
able or Write Enable are ignored by the memory The Data Inputs/Outputs are latched by the Com-
and do not affect bus operations. mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
Bus Read. Bus Read operations read from the
able must remain High, VIH, during the whole Bus
memory cells, or specific registers in the Com-
Write operation. See Figures 8 and 9, Write AC
mand Interface. A valid Bus Read operation in-
Waveforms, and Tables 12 and 13, Write AC
volves setting the desired address on the Address Characteristics, for details of the timing require-
Inputs, applying a Low signal, V IL, to Chip Enable
ments.
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the Output Disable. The Data Inputs/Outputs are in
value, see Figure 7, Read Mode AC Waveforms, the high impedance state when Output Enable is
and Table 11, Read AC Characteristics, for details High, VIH.
of when the output becomes valid.

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M29F200BT, M29F200BB

Standby. When Chip Enable is High, VIH, the COMMAND INTERFACE

Data Inputs/Outputs pins are placed in the high- All Bus Write operations to the memory are inter-
impedance state and the Supply Current is re- preted by the Command Interface. Commands
duced to the Standby level. consist of one or more sequential Bus Write oper-
When Chip Enable is at VIH the Supply Current is ations. Failure to observe a valid sequence of Bus
reduced to the TTL Standby Supply Current, I CC2. Write operations will result in the memory return-
To further reduce the Supply Current to the CMOS ing to Read mode. The long command sequences
Standby Supply Current, ICC3, Chip Enable should are imposed to maximize data security.
be held within VCC ± 0.2V. For Standby current The address used for the commands changes de-
levels see Table 10, DC Characteristics. pending on whether the memory is in 16-bit or 8-
During program or erase operations the memory bit mode. See either Table 5A, or 5B, depending
will continue to use the Program/Erase Supply on the configuration that is being used, for a sum-
Current, ICC4, for Program or Erase operations un- mary of the commands.
til the operation completes. Read/Reset Command. The Read/Reset com-
Automatic Standby. If CMOS levels (VCC ± 0.2V) mand returns the memory to its Read mode where
are used to drive the bus and the bus is inactive for it behaves like a ROM or EPROM. It also resets
150ns or more the memory enters Automatic the errors in the Status Register. Either one or
Standby where the internal Supply Current is re- three Bus Write operations can be used to issue
duced to the CMOS Standby Supply Current, ICC3. the Read/Reset command.
The Data Inputs/Outputs will still output data if a If the Read/Reset command is issued during a
Bus Read operation is in progress. Block Erase operation or following a Programming
Special Bus Operations or Erase error then the memory will take upto 10µs
Additional bus operations can be performed to to abort. During the abort period no valid data can
read the Electronic Signature and also to apply be read from the memory. Issuing a Read/Reset
and remove Block Protection. These bus opera- command during a Block Erase operation will
tions are intended for use by programming equip- leave invalid data in the memory.
ment and are not usually used in applications. Auto Select Command. The Auto Select com-
They require VID to be applied to some pins. mand is used to read the Manufacturer Code, the
Electronic Signature. The memory has two Device Code and the Block Protection Status.
codes, the manufacturer code and the device Three consecutive Bus Write operations are re-
code, that can be read to identify the memory. quired to issue the Auto Select command. Once
These codes can be read by applying the signals the Auto Select command is issued the memory
listed in Tables 4A and 4B, Bus Operations. remains in Auto Select mode until another com-
mand is issued.
Block Protection and Blocks Unprotection. Each
block can be separately protected against acci- From the Auto Select mode the Manufacturer
dental Program or Erase. Protected blocks can be Code can be read using a Bus Read operation
unprotected to allow data to be changed. with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH. The Manufacturer
There are two methods available for protecting
Code for STMicroelectronics is 0020h.
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system The Device Code can be read using a Bus Read
use. For further information refer to Application operation with A0 = VIH and A1 = VIL. The other
Note AN1122, Applying Protection and Unprotec- address bits may be set to either VIL or VIH. The
tion to M29 Series Flash. Device Code for the M29F200BT is 00D3h and for
the M29F200BB is 00D4h.

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 M29F200BT, M29F200BB

Table 5A. Commands, 16-bit mode, BYTE = VIH

Bus Write Operations

Length
Command 1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1 X F0
Read/Reset
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
2 X A0 PA PD
Program
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30

Table 5B. Commands, 8-bit mode, BYTE = VIL

Bus Write Operations
Length

Command 1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1 X F0
Read/Reset
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
2 X A0 PA PD
Program
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A16, DQ8-DQ14 and DQ15 are Don’t Care.
DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase
Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Writ e
Operations until the Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.

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M29F200BT, M29F200BB

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
Typical after
Parameter Min Typ (1) Max Unit
100k W/E Cycles (1)
Chip Erase (All bits in the memory set to ‘0’) 0.8 0.8 sec
Chip Erase 2.5 2.5 10 sec
Block Erase (64 Kbytes) 0.6 0.6 4 sec
Program (Byte or Word) 8 8 150 µs
Chip Program (Byte by Byte) 2.3 2.3 9 sec
Chip Program (Word by Word) 1.2 1.2 4.5 sec
Program/Erase Cycles (per Block) 100,000 cycles
Note: 1. TA = 25°C, VCC = 5V.

The Block Protection Status of each block can be Note that the Program command cannot change a
read using a Bus Read operation with A0 = VIL, bit set at ’0’ back to ’1’ and attempting to do so will
A1 = VIH, and A12-A16 specifying the address of cause an error. One of the Erase Commands must
the block. The other address bits may be set to ei- be used to set all the bits in a block or in the whole
ther VIL or VIH. If the addressed block is protect- memory from ’0’ to ’1’.
ed then 01h is output on Data Inputs/Outputs Unlock Bypass Command. The Unlock Bypass
DQ0-DQ7, otherwise 00h is output. command is used in conjunction with the Unlock
Program Command. The Program command Bypass Program command to program the memo-
can be used to program a value to one address in ry. When the access time to the device is long (as
the memory array at a time. The command re- with some EPROM programmers) considerable
quires four Bus Write operations, the final write op- time saving can be made by using these com-
eration latches the address and data in the internal mands. Three Bus Write operations are required
state machine and starts the Program/Erase Con- to issue the Unlock Bypass command.
troller. Once the Unlock Bypass command has been is-
If the address falls in a protected block then the sued the memory will only accept the Unlock By-
Program command is ignored, the data remains pass Program command and the Unlock Bypass
unchanged. The Status Register is never read and Reset command. The memory can be read as if in
no error condition is given. Read mode.
During the program operation the memory will ig- Unlock Bypass Program Command. The Un-
nore all commands. It is not possible to issue any lock Bypass Program command can be used to
command to abort or pause the operation. Typical program one address in memory at a time. The
program times are given in Table 6. Bus Read op- command requires two Bus Write operations, the
erations during the program operation will output final write operation latches the address and data
the Status Register on the Data Inputs/Outputs. in the internal state machine and starts the Pro-
See the section on the Status Register for more gram/Erase Controller.
details. The Program operation using the Unlock Bypass
After the program operation has completed the Program command behaves identically to the Pro-
memory will return to the Read mode, unless an gram operation using the Program command. A
error has occurred. When an error occurs the protected block cannot be programmed; the oper-
memory will continue to output the Status Regis- ation cannot be aborted and the Status Register is
ter. A Read/Reset command must be issued to re- read. Errors must be reset using the Read/Reset
set the error condition and return to Read mode. command, which leaves the device in Unlock By-
pass Mode. See the Program command for details
on the behavior.

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 M29F200BT, M29F200BB

Unlock Bypass Reset Command. The Unlock erased. If all of the selected blocks are protected
Bypass Reset command can be used to return to the Block Erase operation appears to start but will
Read/Reset mode from Unlock Bypass Mode. terminate within about 100µs, leaving the data un-
Two Bus Write operations are required to issue the changed. No error condition is given when protect-
Unlock Bypass Reset command. ed blocks are ignored.
Chip Erase Command. The Chip Erase com- During the Block Erase operation the memory will
mand can be used to erase the entire chip. Six Bus ignore all commands except the Erase Suspend
Write operations are required to issue the Chip and Read/Reset commands. Typical block erase
Erase Command and start the Program/Erase times are given in Table 6. All Bus Read opera-
Controller. tions during the Block Erase operation will output
If any blocks are protected then these are ignored the Status Register on the Data Inputs/Outputs.
and all the other blocks are erased. If all of the See the section on the Status Register for more
blocks are protected the Chip Erase operation ap- details.
pears to start but will terminate within about 100µs, After the Block Erase operation has completed the
leaving the data unchanged. No error condition is memory will return to the Read Mode, unless an
given when protected blocks are ignored. error has occurred. When an error occurs the
During the erase operation the memory will ignore memory will continue to output the Status Regis-
all commands. It is not possible to issue any com- ter. A Read/Reset command must be issued to re-
mand to abort the operation. Typical chip erase set the error condition and return to Read mode.
times are given in Table 6. All Bus Read opera- The Block Erase Command sets all of the bits in
tions during the Chip Erase operation will output the unprotected selected blocks to ’1’. All previous
the Status Register on the Data Inputs/Outputs. data in the selected blocks is lost.
See the section on the Status Register for more Erase Suspend Command. The Erase Suspend
details. Command may be used to temporarily suspend a
After the Chip Erase operation has completed the Block Erase operation and return the memory to
memory will return to the Read Mode, unless an Read mode. The command requires one Bus
error has occurred. When an error occurs the Write operation.
memory will continue to output the Status Regis- The Program/Erase Controller will suspend within
ter. A Read/Reset command must be issued to re- 15µs of the Erase Suspend Command being is-
set the error condition and return to Read Mode. sued. Once the Program/Erase Controller has
The Chip Erase Command sets all of the bits in un- stopped the memory will be set to Read mode and
protected blocks of the memory to ’1’. All previous the Erase will be suspended. If the Erase Suspend
data is lost. command is issued during the period when the
Block Erase Command. The Block Erase com- memory is waiting for an additional block (before
mand can be used to erase a list of one or more the Program/Erase Controller starts) then the
blocks. Six Bus Write operations are required to Erase is suspended immediately and will start im-
select the first block in the list. Each additional mediately when the Erase Resume Command is
block in the list can be selected by repeating the issued. It will not be possible to select any further
sixth Bus Write operation using the address of the blocks for erasure after the Erase Resume.
additional block. The Block Erase operation starts During Erase Suspend it is possible to Read and
the Program/Erase Controller about 50µs after the Program cells in blocks that are not being erased;
last Bus Write operation. Once the Program/Erase both Read and Program operations behave as
Controller starts it is not possible to select any normal on these blocks. Reading from blocks that
more blocks. Each additional block must therefore are being erased will output the Status Register. It
be selected within 50µs of the last block. The 50µs is also possible to enter the Auto Select mode: the
timer restarts when an additional block is selected. memory will behave as in the Auto Select mode on
The Status Register can be read after the sixth all blocks until a Read/Reset command returns the
Bus Write operation. See the Status Register for memory to Erase Suspend mode.
details on how to identify if the Program/Erase Erase Resume Command. The Erase Resume
Controller has started the Block Erase operation. command must be used to restart the Program/
If any selected blocks are protected then these are Erase Controller from Erase Suspend. An erase
ignored and all the other selected blocks are can be suspended and resumed more than once.

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M29F200BT, M29F200BB

Table 7. Status Register Bits

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 – – 0

Program During Erase

Any Address DQ7 Toggle 0 – – 0
Suspend
Program Error Any Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before Erasing Block 0 Toggle 0 0 Toggle 0

timeout Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Erasing Block 0 Toggle 0 1 Toggle 0
Block Erase
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erasing Block 1 No Toggle 0 1 Toggle 1
Erase Suspend
Non-Erasing Block Data read as normal 1
Good Block Address 0 Toggle 1 1 No Toggle 0
Erase Error
Faulty Block Address 0 Toggle 1 1 Toggle 0
Note: Unspecified data bits should be ignored.

STATUS REGISTER dress is the address being programmed or an

Bus Read operations from any address always address within the block being erased.
read the Status Register during Program and Toggle Bit (DQ6). The Toggle Bit can be used to
Erase operations. It is also read during Erase Sus- identify whether the Program/Erase Controller has
pend when an address within a block being erased successfully completed its operation or if it has re-
is accessed. sponded to an Erase Suspend. The Toggle Bit is
The bits in the Status Register are summarized in output on DQ6 when the Status Register is read.
Table 7, Status Register Bits. During Program and Erase operations the Toggle
Data Polling Bit (DQ7). The Data Polling Bit can Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
be used to identify whether the Program/Erase sive Bus Read operations at any address. After
Controller has successfully completed its opera- successful completion of the operation the memo-
tion or if it has responded to an Erase Suspend. ry returns to Read mode.
The Data Polling Bit is output on DQ7 when the During Erase Suspend mode the Toggle Bit will
Status Register is read. output when addressing a cell within a block being
During Program operations the Data Polling Bit erased. The Toggle Bit will stop toggling when the
outputs the complement of the bit being pro- Program/Erase Controller has suspended the
grammed to DQ7. After successful completion of Erase operation.
the Program operation the memory returns to Figure 4, Data Toggle Flowchart, gives an exam-
Read mode and Bus Read operations from the ad- ple of how to use the Data Toggle Bit.
dress just programmed output DQ7, not its com- Error Bit (DQ5). The Error Bit can be used to
plement. identify errors detected by the Program/Erase
During Erase operations the Data Polling Bit out- Controller. The Error Bit is set to ’1’ when a Pro-
puts ’0’, the complement of the erased state of gram, Block Erase or Chip Erase operation fails to
DQ7. After successful completion of the Erase op- write the correct data to the memory. If the Error
eration the memory returns to Read Mode. Bit is set a Read/Reset command must be issued
In Erase Suspend mode the Data Polling Bit will before other commands are issued. The Error bit
output a ’1’ during a Bus Read operation within a is output on DQ5 when the Status Register is read.
block being erased. The Data Polling Bit will Note that the Program command cannot change a
change from a ’0’ to a ’1’ when the Program/Erase bit set at ’0’ back to ’1’ and attempting to do so will
Controller has suspended the Erase operation. cause an error. One of the Erase commands must
Figure 3, Data Polling Flowchart, gives an exam- be used to set all the bits in a block or in the whole
ple of how to use the Data Polling Bit. A Valid Ad- memory from ’0’ to ’1’.

10/22
 M29F200BT, M29F200BB

Figure 3. Data Polling Flowchart Figure 4. Data Toggle Flowchart

START START

READ DQ5 & DQ7 READ

at VALID ADDRESS DQ5 & DQ6

DQ7 YES DQ6 NO

= =
TOGGLE
DATA
NO YES

NO NO DQ5
DQ5
=1 =1

YES YES

READ DQ7 READ DQ6

DQ7 YES DQ6 NO

= =
DATA TOGGLE

NO YES

FAIL PASS FAIL PASS

AI01369 AI01370

Erase Timer Bit (DQ3). The Erase Timer Bit can within the blocks being erased. Once the operation
be used to identify the start of Program/Erase completes the memory returns to Read mode.
Controller operation during a Block Erase com- During Erase Suspend the Alternative Toggle Bit
mand. Once the Program/Erase Controller starts changes from ’0’ to ’1’ to ’0’, etc. with successive
erasing the Erase Timer Bit is set to ’1’. Before the Bus Read operations from addresses within the
Program/Erase Controller starts the Erase Timer blocks being erased. Bus Read operations to ad-
Bit is set to ’0’ and additional blocks to be erased dresses within blocks not being erased will output
may be written to the Command Interface. The the memory cell data as if in Read mode.
Erase Timer Bit is output on DQ3 when the Status
After an Erase operation that causes the Error Bit
Register is read.
to be set the Alternative Toggle Bit can be used to
Alternative Toggle Bit (DQ2). The Alternative identify which block or blocks have caused the er-
Toggle Bit can be used to monitor the Program/ ror. The Alternative Toggle Bit changes from ’0’ to
Erase controller during Erase operations. The Al- ’1’ to ’0’, etc. with successive Bus Read Opera-
ternative Toggle Bit is output on DQ2 when the tions from addresses within blocks that have not
Status Register is read. erased correctly. The Alternative Toggle Bit does
During Chip Erase and Block Erase operations the not change if the addressed block has erased cor-
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with rectly.
successive Bus Read operations from addresses

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M29F200BT, M29F200BB

Table 8. AC Measurement Conditions

M29F200B
Parameter
45 / 55 70 / 90

AC Test Conditions High Speed Standard

Load Capacitance (CL) 30pF 100pF

Input Rise and Fall Times ≤ 10ns ≤ 10ns

Input Pulse Voltages 0 to 3V 0.45 to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2.0V

Figure 5. AC Testing Input Output Waveform Figure 6. AC Testing Load Circuit

1.3V

High Speed
1N914
3V

1.5V

0V 3.3kΩ

DEVICE
Standard UNDER OUT
TEST
2.4V CL = 30pF or 100pF
2.0V

0.8V
0.45V

AI01275B

CL includes JIG capacitance AI03027

Table 9. Capacitance
(TA = 25 °C, f = 1 MHz)
Symbol Parameter Test Condition Min Max Unit
C IN Input Capacitance V IN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 12 pF
Note: Sampled only, not 100% tested.

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 M29F200BT, M29F200BB

Table 10. DC Characteristics

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
Symbol Parameter Test Condition Min Typ (2) Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ V CC ±1 µA
E = VIL, G = VIH,
ICC1 Supply Current (Read) 6 20 mA
f = 6MHz
ICC2 Supply Current (Standby) TTL E = VIH 1 mA

E = VCC ± 0.2V,
ICC3 Supply Current (Standby) CMOS
RP = VCC ± 0.2V
30 100 µA

Program/Erase
ICC4 (1) Supply Current (Program/Erase)
Controller active
20 mA

V IL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8mA 0.45 V

Output High Voltage TTL IOH = –2.5mA 2.4 V

VOH
Output High Voltage CMOS IOH = –100µA VCC – 0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

Program/Erase Lockout Supply
V LKO (1) 3.2 4.2 V
Voltage
Note: 1. Sampled only, not 100% tested.
2. TA = 25°C, VCC = 5V.

13/22
M29F200BT, M29F200BB

Table 11. Read AC Characteristics

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F200B
Symbol Alt Parameter Test Condition Unit
45 55 70 / 90
E = VIL,
tAVAV tRC Address Valid to Next Address Valid Min 45 55 70 ns
G = VIL

E = VIL,
tAVQV tACC Address Valid to Output Valid Max 45 55 70 ns
G = VIL

Chip Enable Low to Output

tELQX (1) tLZ G = VIL Min 0 0 0 ns
Transition

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 45 55 70 ns

Output Enable Low to Output

tGLQX (1) tOLZ E = VIL Min 0 0 0 ns
Transition
tGLQV tOE Output Enable Low to Output Valid E = VIL Max 25 30 30 ns

tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 15 18 20 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 15 18 20 ns

tEHQX Chip Enable, Output Enable or

tGHQX tOH Address Transition to Output Min 0 0 0 ns
tAXQX Transition

tELBL tELFL
Chip Enable to BYTE Low or High Max 5 5 5 ns
tELBH tELFH

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 15 15 20 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 30 30 ns

Note: 1. Sampled only, not 100% tested.

Figure 7. Read Mode AC Waveforms

tAVAV
A0-A16/
VALID
A–1
tAVQV tAXQX

tELQV tEHQX

tELQX tEHQZ

tGLQX tGHQX

tGLQV tGHQZ
DQ0-DQ7/
VALID
DQ8-DQ15
tBHQV

BYTE

tELBL/tELBH tBLQZ AI02915

14/22
 M29F200BT, M29F200BB

Table 12. Write AC Characteristics, Write Enable Controlled

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M29F200B
Symbol Alt Parameter Unit
45 55 70 / 90
tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 40 40 45 ns

tDVWH tDS Input Valid to Write Enable High Min 25 25 30 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 20 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 40 40 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 30 ns

t VCHEL tVCS V CC High to Chip Enable Low Min 50 50 50 µs

Note: 1. Sampled only, not 100% tested.

Figure 8. Write AC Waveforms, Write Enable Controlled

tAVAV
A0-A16/
VALID
A–1
tWLAX

tAVWL tWHEH

tELWL tWHGL

tGHWL tWLWH

tWHWL

tDVWH tWHDX
DQ0-DQ7/
VALID
DQ8-DQ15

VCC

tVCHEL

RB

tWHRL AI01991

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M29F200BT, M29F200BB

Table 13. Write AC Characteristics, Chip Enable Controlled

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M29F200B
Symbol Alt Parameter Unit
45 55 70 / 90
tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns

t WLEL tWS Write Enable Low to Chip Enable Low Min 0 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 40 40 45 ns

tDVEH tDS Input Valid to Chip Enable High Min 25 25 30 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 20 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 40 40 45 ns

t GHEL Output Enable High Chip Enable Low Min 0 0 0 ns

t EHGL tOEH Chip Enable High to Output Enable Low Min 0 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 30 ns

tVCHWL tVCS V CC High to Write Enable Low Min 50 50 50 µs

Note: 1. Sampled only, not 100% tested.

Figure 9. Write AC Waveforms, Chip Enable Controlled

tAVAV
A0-A16/
VALID
A–1
tELAX

tAVEL tEHWH

tWLEL tEHGL

tGHEL tELEH

tEHEL

tDVEH tEHDX
DQ0-DQ7/
VALID
DQ8-DQ15

VCC

tVCHWL

RB

tEHRL AI01992

16/22
 M29F200BT, M29F200BB

Table 14. Reset/Block Temporary Unprotect AC Characteristics

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M29F200B
Symbol Alt Parameter Unit
45 55 70 / 90

tPHWL (1)
RP High to Write Enable Low, Chip Enable
tPHEL tRH Min 50 50 50 ns
Low, Output Enable Low
(1)
tPHGL

tRHWL (1)
RB High to Write Enable Low, Chip Enable
tRHEL (1) tRB Min 0 0 0 ns
Low, Output Enable Low
(1)
tRHGL

tPLPX tRP RP Pulse Width Min 500 500 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 10 µs

tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 500 ns
Note: 1. Sampled only, not 100% tested.

Figure 10. Reset/Block Temporary Unprotect AC Waveforms

W, E, G

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

tPLPX
RP
tPHPHH

tPLYH

AI02931

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M29F200BT, M29F200BB

Table 15. Ordering Information Scheme

Example: M29F200BB 55 N 1 T

Device Type
M29

Operating Voltage
F = VCC = 5V ± 10%

Device Function
200B = 2 Mbit (256Kb x8 or 128Kb x16), Boot Block

Array Matrix
T = Top Boot
B = Bottom Boot

Speed
45 = 45 ns
55 = 55 ns
70 = 70 ns
90 = 90 ns

Package
N = TSOP48: 12 x 20 mm
M = SO44

Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C

Optio n
T = Tape & Reel Packing

Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed
parts, otherwise devices are shipped from the factory with the memory content erased (to FFFFh).

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.

18/22
 M29F200BT, M29F200BB

Table 16. Revision History

Date Revision Details
July 1999 First Issue

Chip Erase Max. specification added (Table 6)

Block Erase Max. specification added (Table 6)
Program Max. specification added (Table 6)
10/08/99 Chip Program Max. specification added (Table 6)
ICC1 Typ. specification added (Table 10)
ICC3 Typ. specification added (Table 10)
ICC3 Test Condition changed (Table 10)

19/22
M29F200BT, M29F200BB

Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 11.90 12.10 0.469 0.476
e 0.50 – – 0.020 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N 48 48
CP 0.10 0.004

Figure 11. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2

1 N
e

B
N/2

D1 A
D CP

DIE

TSOP-a A1 α L
Drawing is not to scale.

20/22
 M29F200BT, M29F200BB

Table 18. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max

A 2.42 2.62 0.095 0.103

A1 0.22 0.23 0.009 0.010
A2 2.25 2.35 0.089 0.093
B 0.50 0.020
C 0.10 0.25 0.004 0.010
D 28.10 28.30 1.106 1.114
E 13.20 13.40 0.520 0.528

e 1.27 – – 0.050 – –
H 15.90 16.10 0.626 0.634
L 0.80 – – 0.031 – –
α 3° – – 3° – –
N 44 44
CP 0.10 0.004

Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

A2 A
C
B
e CP

E H
1
A1 α L

SO-b

Drawing is not to scale.

21/22
M29F200BT, M29F200BB

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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22/22
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