M29F160BT

M29F160BB
16 Mbit (2Mb x8 or 1Mb x16, Boot Block)
Single Supply Flash Memory
PRELIMINARY DATA

■ SINGLE 5V±10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS
■ ACCESS TIME: 55ns
■ PROGRAMMING TIME
– 8µs per Byte/Word typical
■ 35 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 32 Main Blocks
■ PROGRAM/ERASE CONTROLLER TSOP48 (N)
– Embedded Byte/Word Program algorithm 12 x 20mm

– Embedded Multi-Block/Chip Erase algorithm

– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
Figure 1. Logic Diagram
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND VCC
– Faster Production/Batch Programming
■ TEMPORARY BLOCK UNPROTECTION
20 15
MODE
■ LOW POWER CONSUMPTION A0-A19 DQ0-DQ14

– Standby and Automatic Standby

W DQ15A–1
■ 100,000 PROGRAM/ERASE CYCLES per M29F160BT
BLOCK E M29F160BB BYTE
■ 20 YEARS DATA RETENTION G RB
– Defectivity below 1 ppm/year
RP
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29F160BT: 22CCh
– Bottom Device Code M29F160BB: 224Bh VSS
AI02920

March 2000 1/22

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M29F160BT, M29F160BB

Figure 2. TSOP Connections Table 1. Signal Names

A0-A19 Address Inputs
A15 1 48 A16
A14 BYTE DQ0-DQ7 Data Inputs/Outputs
A13 VSS DQ8-DQ14 Data Inputs/Outputs
A12 DQ15A–1
A11 DQ7 DQ15A–1 Data Input/Output or Address Input
A10 DQ14 E Chip Enable
A9 DQ6
A8 DQ13 G Output Enable
A19 DQ5
W Write Enable
NC DQ12
W DQ4 RP Reset/Block Temporary Unprotect
RP 12 M29F160BT 37 VCC
RB Ready/Busy Output
NC 13 M29F160BB 36 DQ11
NC DQ3 BYTE Byte/Word Organization Select
RB DQ10
VCC Supply Voltage
A18 DQ2
A17 DQ9 VSS Ground
A7 DQ1
A6 DQ8 NC Not Connected Internally
A5 DQ0
A4 G
A3 VSS
A2 E
A1 24 25 A0
AI02921

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit
Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C
TA Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C
Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C
TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage –0.6 to 6 V

VCC Supply Voltage –0.6 to 6 V

VID Identification Voltage –0.6 to 13.5 V

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

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 M29F160BT, M29F160BB

SUMMARY DESCRIPTION The blocks in the memory are asymmetrically ar-

The M29F160B is a 16Mbit (2Mb x8 or 1Mb x16) ranged, see Tables 3 and 4, Block Addresses. The
non-volatile memory that can be read, erased and first or last 64 Kbytes have been divided into four
reprogrammed. These operations can be per- additional blocks. The 16 Kbyte Boot Block can be
formed using a single 5V supply. On power-up the used for small initialization code to start the micro-
memory defaults to its Read mode where it can be processor, the two 8 Kbyte Parameter Blocks can
read in the same way as a ROM or EPROM. be used for parameter storage and the remaining
32K is a small Main Block where the application
The memory is divided into blocks that can be
may be stored.
erased independently so it is possible to preserve
valid data while old data is erased. Each block can Chip Enable, Output Enable and Write Enable sig-
be protected independently to prevent accidental nals control the bus operation of the memory.
Program or Erase commands from modifying the They allow simple connection to most micropro-
memory. Program and Erase commands are writ- cessors, often without additional logic.
ten to the Command Interface of the memory. An The memory is offered in a TSOP48 (12 x 20mm)
on-chip Program/Erase Controller simplifies the package and it is supplied with all the bits erased
process of programming or erasing the memory by (set to ’1’).
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.

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M29F160BT, M29F160BB

Table 3. Top Boot Block Addresses Table 4. Bottom Boot Block Addresses
M29F160BT M29F160BB
Size Address Range Address Range Size Address Range Address Range
# #
(Kbytes) (x8) (x16) (Kbytes) (x8) (x16)
34 16 1FC000h-1FFFFFh FE000h-FFFFFh 34 64 1F0000h-1FFFFFh F8000h-FFFFFh
33 8 1FA000h-1FBFFFh FD000h-FDFFFh 33 64 1E0000h-1EFFFFh F0000h-F7FFFh
32 8 1F8000h-1F9FFFh FC000h-FCFFFh 32 64 1D0000h-1DFFFFh E8000h-EFFFFh
31 32 1F0000h-1F7FFFh F8000h-FBFFFh 31 64 1C0000h-1CFFFFh E0000h-E7FFFh
30 64 1E0000h-1EFFFFh F0000h-F7FFFh 30 64 1B0000h-1BFFFFh D8000h-DFFFFh
29 64 1D0000h-1DFFFFh E8000h-EFFFFh 29 64 1A0000h-1AFFFFh D0000h-D7FFFh
28 64 1C0000h-1CFFFFh E0000h-E7FFFh 28 64 190000h-19FFFFh C8000h-CFFFFh
27 64 1B0000h-1BFFFFh D8000h-DFFFFh 27 64 180000h-18FFFFh C0000h-C7FFFh
26 64 1A0000h-1AFFFFh D0000h-D7FFFh 26 64 170000h-17FFFFh B8000h-BFFFFh
25 64 190000h-19FFFFh C8000h-CFFFFh 25 64 160000h-16FFFFh B0000h-B7FFFh
24 64 180000h-18FFFFh C0000h-C7FFFh 24 64 150000h-15FFFFh A8000h-AFFFFh
23 64 170000h-17FFFFh B8000h-BFFFFh 23 64 140000h-14FFFFh A0000h-A7FFFh
22 64 160000h-16FFFFh B0000h-B7FFFh 22 64 130000h-13FFFFh 98000h-9FFFFh
21 64 150000h-15FFFFh A8000h-AFFFFh 21 64 120000h-12FFFFh 90000h-97FFFh
20 64 140000h-14FFFFh A0000h-A7FFFh 20 64 110000h-11FFFFh 88000h-8FFFFh
19 64 130000h-13FFFFh 98000h-9FFFFh 19 64 100000h-10FFFFh 80000h-87FFFh
18 64 120000h-12FFFFh 90000h-97FFFh 18 64 0F0000h-0FFFFFh 78000h-7FFFFh
17 64 110000h-11FFFFh 88000h-8FFFFh 17 64 0E0000h-0EFFFFh 70000h-77FFFh
16 64 100000h-10FFFFh 80000h-87FFFh 16 64 0D0000h-0DFFFFh 68000h-6FFFFh
15 64 0F0000h-0FFFFFh 78000h-7FFFFh 15 64 0C0000h-0CFFFFh 60000h-67FFFh
14 64 0E0000h-0EFFFFh 70000h-77FFFh 14 64 0B0000h-0BFFFFh 58000h-5FFFFh
13 64 0D0000h-0DFFFFh 68000h-6FFFFh 13 64 0A0000h-0AFFFFh 50000h-57FFFh
12 64 0C0000h-0CFFFFh 60000h-67FFFh 12 64 090000h-09FFFFh 48000h-4FFFFh
11 64 0B0000h-0BFFFFh 58000h-5FFFFh 11 64 080000h-08FFFFh 40000h-47FFFh
10 64 0A0000h-0AFFFFh 50000h-57FFFh 10 64 070000h-07FFFFh 38000h-3FFFFh
9 64 090000h-09FFFFh 48000h-4FFFFh 9 64 060000h-06FFFFh 30000h-37FFFh
8 64 080000h-08FFFFh 40000h-47FFFh 8 64 050000h-05FFFFh 28000h-2FFFFh
7 64 070000h-07FFFFh 38000h-3FFFFh 7 64 040000h-04FFFFh 20000h-27FFFh
6 64 060000h-06FFFFh 30000h-37FFFh 6 64 030000h-03FFFFh 18000h-1FFFFh
5 64 050000h-05FFFFh 28000h-2FFFFh 5 64 020000h-02FFFFh 10000h-17FFFh
4 64 040000h-04FFFFh 20000h-27FFFh 4 64 010000h-01FFFFh 08000h-0FFFFh
3 64 030000h-03FFFFh 18000h-1FFFFh 3 32 008000h-00FFFFh 04000h-07FFFh
2 64 020000h-02FFFFh 10000h-17FFFh 2 8 006000h-007FFFh 03000h-03FFFh
1 64 010000h-01FFFFh 08000h-0FFFFh 1 8 004000h-005FFFh 02000h-02FFFh
0 64 000000h-00FFFFh 00000h-07FFFh 0 16 000000h-003FFFh 00000h-01FFFh

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 M29F160BT, M29F160BB

SIGNAL DESCRIPTIONS tRHEL, whichever occurs last. See the Ready/Busy

See Figure 1, Logic Diagram, and Table 1, Signal Output section, Table 17 and Figure 10, Reset/
Names, for a brief overview of the signals connect- Temporary Unprotect AC Characteristics for more
ed to this device. details.
Address Inputs (A0-A19). The Address Inputs Holding RP at V ID will temporarily unprotect the
select the cells in the memory array to access dur- protected blocks in the memory. Program and
ing Bus Read operations. During Bus Write opera- Erase operations on all blocks will be possible.
tions they control the commands sent to the The transition from VIH to VID must be slower than
Command Interface of the internal state machine. tPHPHH.
Data Inputs/Outputs (DQ0-DQ7). The Data In- Ready/Busy Output (RB). The Ready/Busy pin
puts/Outputs output the data stored at the selected is an open-drain output that can be used to identify
address during a Bus Read operation. During Bus when the memory array can be read. Ready/Busy
Write operations they represent the commands is high-impedance during Read mode, Auto Select
sent to the Command Interface of the internal state mode and Erase Suspend mode.
machine. After a Hardware Reset, Bus Read and Bus Write
Data Inputs/Outputs (DQ8-DQ14). The Data In- operations cannot begin until Ready/Busy be-
puts/Outputs output the data stored at the selected comes high-impedance. See Table 17 and Figure
address during a Bus Read operation when BYTE 10, Reset/Temporary Unprotect AC Characteris-
is High, VIH. When BYTE is Low, VIL, these pins tics.
are not used and are high impedance. During Bus During Program or Erase operations Ready/Busy
Write operations the Command Register does not is Low, VOL. Ready/Busy will remain Low during
use these bits. When reading the Status Register Read/Reset commands or Hardware Resets until
these bits should be ignored. the memory is ready to enter Read mode.
Data Input/Output or Address Input (DQ15A-1). The use of an open-drain output allows the Ready/
When BYTE is High, VIH, this pin behaves as a Busy pins from several memories to be connected
Data Input/Output pin (as DQ8-DQ14). When to a single pull-up resistor. A Low will then indicate
BYTE is Low, VIL, this pin behaves as an address that one, or more, of the memories is busy.
pin; DQ15A–1 Low will select the LSB of the Word Byte/Word Organization Select (BYTE). The Byte/
on the other addresses, DQ15A–1 High will select Word Organization Select pin is used to switch be-
the MSB. Throughout the text consider references tween the 8-bit and 16-bit Bus modes of the mem-
to the Data Input/Output to include this pin when ory. When Byte/Word Organization Select is Low,
BYTE is High and references to the Address In- VIL, the memory is in 8-bit mode, when it is High,
puts to include this pin when BYTE is Low except VIH, the memory is in 16-bit mode.
when stated explicitly otherwise. VCC Supply Voltage. The VCC Supply Voltage
Chip Enable (E). The Chip Enable, E, activates supplies the power for all operations (Read, Pro-
the memory, allowing Bus Read and Bus Write op- gram, Erase etc.).
erations to be performed. When Chip Enable is The Command Interface is disabled when the V CC
High, V IH, all other pins are ignored. Supply Voltage is less than the Lockout Voltage,
Output Enable (G). The Output Enable, G, con- VLKO. This prevents Bus Write operations from ac-
trols the Bus Read operation of the memory. cidentally damaging the data during power up,
Write Enable (W). The Write Enable, W, controls power down and power surges. If the Program/
the Bus Write operation of the memory’s Com- Erase Controller is programming or erasing during
mand Interface. this time then the operation aborts and the memo-
ry contents being altered will be invalid.
Reset/Block Temporary Unprotect (RP). The Re-
set/Block Temporary Unprotect pin can be used to A 0.1µF capacitor should be connected between
apply a Hardware Reset to the memory or to tem- the V CC Supply Voltage pin and the VSS Ground
porarily unprotect all blocks that have been pro- pin to decouple the current surges from the power
tected. supply. The PCB track widths must be sufficient to
carry the currents required during program and
A Hardware Reset is achieved by holding Reset/ erase operations, ICC4.
Block Temporary Unprotect Low, V IL, for at least
tPLPX. After Reset/Block Temporary Unprotect Vss Ground. The VSS Ground is the reference
goes High, V IH, the memory will be ready for Bus for all voltage measurements.
Read and Bus Write operations after tPHEL or

5/22
M29F160BT, M29F160BB

BUS OPERATIONS Enable or Write Enable, whichever occurs last.

There are five standard bus operations that control The Data Inputs/Outputs are latched by the Com-
the device. These are Bus Read, Bus Write, Out- mand Interface on the rising edge of Chip Enable
put Disable, Standby and Automatic Standby. See or Write Enable, whichever occurs first. Output En-
Tables 5 and 6, Bus Operations, for a summary. able must remain High, VIH, during the whole Bus
Typically glitches of less than 5ns on Chip Enable Write operation. See Figures 8 and 9, Write AC
or Write Enable are ignored by the memory and do Waveforms, and Tables 15 and 16, Write AC
not affect bus operations. Characteristics, for details of the timing require-
ments.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com- Output Disable. The Data Inputs/Outputs are in
mand Interface. A valid Bus Read operation in- the high impedance state when Output Enable is
volves setting the desired address on the Address High, V IH.
Inputs, applying a Low signal, V IL, to Chip Enable Standby. When Chip Enable is High, VIH, the
and Output Enable and keeping Write Enable Data Inputs/Outputs pins are placed in the high-
High, VIH. The Data Inputs/Outputs will output the impedance state and the Supply Current is re-
value, see Figure 7, Read Mode AC Waveforms, duced to the Standby level.
and Table 14, Read AC Characteristics, for details When Chip Enable is at V IH the Supply Current is
of when the output becomes valid. reduced to the TTL Standby Supply Current, I CC2.
Bus Write. Bus Write operations write to the To further reduce the Supply Current to the CMOS
Command Interface. A valid Bus Write operation Standby Supply Current, ICC3, Chip Enable should
begins by setting the desired address on the Ad- be held within V CC ± 0.2V. For Standby current
dress Inputs. The Address Inputs are latched by levels see Table 13, DC Characteristics.
the Command Interface on the falling edge of Chip

Table 5. Bus Operations, BYTE = V IL

Address Inputs Data Inputs/Outputs
Operation E G W
DQ15A–1, A0-A19 DQ14-DQ8 DQ7-DQ0
Bus Read VIL VIL VIH Cell Address Hi-Z Data Output

Bus Write VIL VIH VIL Command Address Hi-Z Data Input

Output Disable X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read Manufacturer A0 = VIL, A1 = VIL, A9 = VID,

VIL VIL VIH Hi-Z 20h
Code Others VIL or VIH

A0 = VIH, A1 = VIL, A9 = VID, CCh (M29F160BT)

Read Device Code VIL VIL VIH Hi-Z
Others VIL or VIH 4Bh (M29F160BB)
Note: X = VIL or VIH.

Table 6. Bus Operations, BYTE = V IH

Address Inputs Data Inputs/Outputs
Operation E G W
A0-A19 DQ15A–1, DQ14-DQ0

Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable X VIH VIH X Hi-Z

Standby VIH X X X Hi-Z

Read Manufacturer A0 = VIL, A1 = VIL, A9 = VID,

VIL VIL VIH 0020h
Code Others VIL or VIH

A0 = VIH, A1 = VIL, A9 = VID, 22CCh (M29F160BT)

Read Device Code VIL VIL VIH
Others VIL or VIH 224Bh (M29F160BB)
Note: X = VIL or VIH.

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 M29F160BT, M29F160BB

During program or erase operations the memory be read from the memory. Issuing a Read/Reset
will continue to use the Program/Erase Supply command during a Block Erase operation will
Current, ICC4, for Program or Erase operations un- leave invalid data in the memory.
til the operation completes. Auto Select Command. The Auto Select com-
Automatic Standby. If CMOS levels (VCC ± 0.2V) mand is used to read the Manufacturer Code, the
are used to drive the bus and the bus is inactive for Device Code and the Block Protection Status.
150ns or more the memory enters Automatic Three consecutive Bus Write operations are re-
Standby where the internal Supply Current is re- quired to issue the Auto Select command. Once
duced to the CMOS Standby Supply Current, ICC3. the Auto Select command is issued the memory
The Data Inputs/Outputs will still output data if a remains in Auto Select mode until another com-
Bus Read operation is in progress. mand is issued.
Special Bus Operations From the Auto Select mode the Manufacturer
Additional bus operations can be performed to Code can be read using a Bus Read operation
read the Electronic Signature and also to apply with A0 = V IL and A1 = VIL. The other address bits
and remove Block Protection. These bus opera- may be set to either V IL or VIH. The Manufacturer
tions are intended for use by programming equip- Code for STMicroelectronics is 0020h.
ment and are not usually used in applications. The Device Code can be read using a Bus Read
They require VID to be applied to some pins. operation with A0 = VIH and A1 = VIL. The other
Electronic Signature. The memory has two address bits may be set to either V IL or VIH. The
codes, the manufacturer code and the device Device Code for the M29F160BT is 22CCh and for
code, that can be read to identify the memory. the M29F160BB is 224Bh.
These codes can be read by applying the signals The Block Protection Status of each block can be
listed in Tables 5 and 6, Bus Operations. read using a Bus Read operation with A0 = VIL,
Block Protection and Blocks Unprotection. Each A1 = VIH, and A12-A19 specifying the address of
block can be separately protected against acci- the block. The other address bits may be set to ei-
dental Program or Erase. Protected blocks can be ther VIL or VIH. If the addressed block is protected
unprotected to allow data to be changed. then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro- Program Command. The Program command
gramming equipment and the other for in-system can be used to program a value to one address in
use. For further information refer to Application the memory array at a time. The command re-
Note AN1122, Applying Protection and Unprotec- quires four Bus Write operations, the final write op-
tion to M29 Series Flash. eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
COMMAND INTERFACE troller.
All Bus Write operations to the memory are inter- If the address falls in a protected block then the
preted by the Command Interface. Commands Program command is ignored, the data remains
consist of one or more sequential Bus Write oper- unchanged. The Status Register is never read and
ations. Failure to observe a valid sequence of Bus no error condition is given.
Write operations will result in the memory return- During the program operation the memory will ig-
ing to Read mode. The long command sequences nore all commands. It is not possible to issue any
are imposed to maximize data security. command to abort or pause the operation. Typical
The address used for the commands changes de- program times are given in Table 9. Bus Read op-
pending on whether the memory is in 16-bit or 8- erations during the program operation will output
bit mode. See either Table 7, or 8, depending on the Status Register on the Data Inputs/Outputs.
the configuration that is being used, for a summary See the section on the Status Register for more
of the commands. details.
Read/Reset Command. The Read/Reset com- After the program operation has completed the
mand returns the memory to its Read mode where memory will return to the Read mode, unless an
it behaves like a ROM or EPROM. It also resets error has occurred. When an error occurs the
the errors in the Status Register. Either one or memory will continue to output the Status Regis-
three Bus Write operations can be used to issue ter. A Read/Reset command must be issued to re-
the Read/Reset command. set the error condition and return to Read mode.
If the Read/Reset command is issued during a Note that the Program command cannot change a
Block Erase operation or following a Programming bit set at ’0’ back to ’1’. One of the Erase Com-
or Erase error then the memory will take upto 10µs mands must be used to set all the bits in a block or
to abort. During the abort period no valid data can in the whole memory from ’0’ to ’1’.

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M29F160BT, M29F160BB

Table 7. Commands, 16-bit mode, BYTE = VIH

Bus Write Operations

Length
Command 1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1 X F0
Read/Reset
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
2 X A0 PA PD
Program
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30

Table 8. Commands, 8-bit mode, BYTE = VIL

Bus Write Operations
Length

Command 1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1 X F0
Read/Reset
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
2 X A0 PA PD
Program
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ14 and DQ15 are Don’t Care.
DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH .
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase
Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write
Operations until the Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.

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 M29F160BT, M29F160BB

Unlock Bypass Command. The Unlock Bypass ter. A Read/Reset command must be issued to re-
command is used in conjunction with the Unlock set the error condition and return to Read Mode.
Bypass Program command to program the memo- The Chip Erase Command sets all of the bits in un-
ry. When the access time to the device is long (as protected blocks of the memory to ’1’. All previous
with some EPROM programmers) considerable data is lost.
time saving can be made by using these com-
mands. Three Bus Write operations are required Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
to issue the Unlock Bypass command.
blocks. Six Bus Write operations are required to
Once the Unlock Bypass command has been is- select the first block in the list. Each additional
sued the memory will only accept the Unlock By- block in the list can be selected by repeating the
pass Program command and the Unlock Bypass sixth Bus Write operation using the address of the
Reset command. The memory can be read as if in additional block. The Block Erase operation starts
Read mode. the Program/Erase Controller about 50µs after the
Unlock Bypass Program Command. The Un- last Bus Write operation. Once the Program/Erase
lock Bypass Program command can be used to Controller starts it is not possible to select any
program one address in memory at a time. The more blocks. Each additional block must therefore
command requires two Bus Write operations, the be selected within 50µs of the last block. The 50µs
final write operation latches the address and data timer restarts when an additional block is selected.
in the internal state machine and starts the Pro- The Status Register can be read after the sixth
gram/Erase Controller. Bus Write operation. See the Status Register for
The Program operation using the Unlock Bypass details on how to identify if the Program/Erase
Program command behaves identically to the Pro- Controller has started the Block Erase operation.
gram operation using the Program command. A If any selected blocks are protected then these are
protected block cannot be programmed; the oper- ignored and all the other selected blocks are
ation cannot be aborted and the Status Register is erased. If all of the selected blocks are protected
read. Errors must be reset using the Read/Reset the Block Erase operation appears to start but will
command, which leaves the device in Unlock By- terminate within about 100µs, leaving the data un-
pass Mode. See the Program command for details changed. No error condition is given when protect-
on the behavior. ed blocks are ignored.
Unlock Bypass Reset Command. The Unlock During the Block Erase operation the memory will
Bypass Reset command can be used to return to ignore all commands except the Erase Suspend
Read/Reset mode from Unlock Bypass Mode. and Read/Reset commands. Typical block erase
Two Bus Write operations are required to issue the times are given in Table 9. All Bus Read opera-
Unlock Bypass Reset command. tions during the Block Erase operation will output
Chip Erase Command. The Chip Erase com- the Status Register on the Data Inputs/Outputs.
mand can be used to erase the entire chip. Six Bus See the section on the Status Register for more
Write operations are required to issue the Chip details.
Erase Command and start the Program/Erase After the Block Erase operation has completed the
Controller. memory will return to the Read Mode, unless an
If any blocks are protected then these are ignored error has occurred. When an error occurs the
and all the other blocks are erased. If all of the memory will continue to output the Status Regis-
blocks are protected the Chip Erase operation ap- ter. A Read/Reset command must be issued to re-
pears to start but will terminate within about 100µs, set the error condition and return to Read mode.
leaving the data unchanged. No error condition is The Block Erase Command sets all of the bits in
given when protected blocks are ignored. the unprotected selected blocks to ’1’. All previous
During the erase operation the memory will ignore data in the selected blocks is lost.
all commands. It is not possible to issue any com- Erase Suspend Command. The Erase Suspend
mand to abort the operation. Typical chip erase Command may be used to temporarily suspend a
times are given in Table 9. All Bus Read opera- Block Erase operation and return the memory to
tions during the Chip Erase operation will output Read mode. The command requires one Bus
the Status Register on the Data Inputs/Outputs. Write operation.
See the section on the Status Register for more The Program/Erase Controller will suspend within
details. 15µs of the Erase Suspend Command being is-
After the Chip Erase operation has completed the sued. Once the Program/Erase Controller has
memory will return to the Read Mode, unless an stopped the memory will be set to Read mode and
error has occurred. When an error occurs the the Erase will be suspended. If the Erase Suspend
memory will continue to output the Status Regis- command is issued during the period when the

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M29F160BT, M29F160BB

memory is waiting for an additional block (before are being erased will output the Status Register. It
the Program/Erase Controller starts) then the is also possible to enter the Auto Select mode: the
Erase is suspended immediately and will start im- memory will behave as in the Auto Select mode on
mediately when the Erase Resume Command is all blocks until a Read/Reset command returns the
issued. It will not be possible to select any further memory to Erase Suspend mode.
blocks for erasure after the Erase Resume. Erase Resume Command. The Erase Resume
During Erase Suspend it is possible to Read and command must be used to restart the Program/
Program cells in blocks that are not being erased; Erase Controller from Erase Suspend. An erase
both Read and Program operations behave as can be suspended and resumed more than once.
normal on these blocks. Reading from blocks that

Table 9. Program, Erase Times and Program, Erase Endurance Cycles

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
Typical after
Parameter Min Typ (1) Max Unit
100k W/E Cycles (1)
Chip Erase (All bits in the memory set to ‘0’) 6 6 sec
Chip Erase 16 16 70 sec
Block Erase (64 Kbytes) 0.6 0.6 4 sec
Program (Byte or Word) 8 8 150 µs
Chip Program (Byte by Byte) 18 18 70 sec
Chip Program (Word by Word) 9 9 35 sec
Program/Erase Cycles (per Block) 100,000 cycles
Note: 1. TA = 25°C, VCC = 5V.

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 M29F160BT, M29F160BB

STATUS REGISTER dress is the address being programmed or an

Bus Read operations from any address always address within the block being erased.
read the Status Register during Program and Toggle Bit (DQ6). The Toggle Bit can be used to
Erase operations. It is also read during Erase Sus- identify whether the Program/Erase Controller has
pend when an address within a block being erased successfully completed its operation or if it has re-
is accessed. sponded to an Erase Suspend. The Toggle Bit is
The bits in the Status Register are summarized in output on DQ6 when the Status Register is read.
Table 10, Status Register Bits. During Program and Erase operations the Toggle
Data Polling Bit (DQ7). The Data Polling Bit can Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
be used to identify whether the Program/Erase sive Bus Read operations at any address. After
Controller has successfully completed its opera- successful completion of the operation the memo-
tion or if it has responded to an Erase Suspend. ry returns to Read mode.
The Data Polling Bit is output on DQ7 when the During Erase Suspend mode the Toggle Bit will
Status Register is read. output when addressing a cell within a block being
During Program operations the Data Polling Bit erased. The Toggle Bit will stop toggling when the
outputs the complement of the bit being pro- Program/Erase Controller has suspended the
grammed to DQ7. After successful completion of Erase operation.
the Program operation the memory returns to Figure 4, Data Toggle Flowchart, gives an exam-
Read mode and Bus Read operations from the ad- ple of how to use the Data Toggle Bit.
dress just programmed output DQ7, not its com- Error Bit (DQ5). The Error Bit can be used to
plement. identify errors detected by the Program/Erase
During Erase operations the Data Polling Bit out- Controller. The Error Bit is set to ’1’ when a Pro-
puts ’0’, the complement of the erased state of gram, Block Erase or Chip Erase operation fails to
DQ7. After successful completion of the Erase op- write the correct data to the memory. If the Error
eration the memory returns to Read Mode. Bit is set a Read/Reset command must be issued
In Erase Suspend mode the Data Polling Bit will before other commands are issued. The Error bit
output a ’1’ during a Bus Read operation within a is output on DQ5 when the Status Register is read.
block being erased. The Data Polling Bit will Note that the Program command cannot change a
change from a ’0’ to a ’1’ when the Program/Erase bit set at ’0’ back to ’1’ and attempting to do so,
Controller has suspended the Erase operation. may or may not set DQ5 at ‘1’. In both cases, a
Figure 3, Data Polling Flowchart, gives an exam- successive Bus Read operation will show the bit is
ple of how to use the Data Polling Bit. A Valid Ad- still ‘0’. One of the Erase commands must be used
to set all the bits in a block or in the whole memory
from ’0’ to ’1’.
Table 10. Status Register Bits
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 – – 0
Program During Erase
Any Address DQ7 Toggle 0 – – 0
Suspend
Program Error Any Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before Erasing Block 0 Toggle 0 0 Toggle 0

timeout Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Erasing Block 0 Toggle 0 1 Toggle 0
Block Erase
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erasing Block 1 No Toggle 0 – Toggle 1
Erase Suspend
Non-Erasing Block Data read as normal 1
Good Block Address 0 Toggle 1 1 No Toggle 0
Erase Error
Faulty Block Address 0 Toggle 1 1 Toggle 0
Note: Unspecified data bits should be ignored.

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M29F160BT, M29F160BB

Figure 3. Data Polling Flowchart Figure 4. Data Toggle Flowchart

START
START

READ
READ DQ5 & DQ7
DQ5 & DQ6
at VALID ADDRESS

READ DQ6
DQ7 YES
=
DATA
DQ6 NO
NO =
TOGGLE

YES
NO DQ5
=1
NO DQ5
YES =1
YES
READ DQ7
at VALID ADDRESS READ DQ6
TWICE

DQ7 YES
= DQ6 NO
DATA =
TOGGLE
NO
YES

FAIL PASS FAIL PASS

AI01370B
AI03598

Erase Timer Bit (DQ3). The Erase Timer Bit can within the blocks being erased. Once the operation
be used to identify the start of Program/Erase completes the memory returns to Read mode.
Controller operation during a Block Erase com- During Erase Suspend the Alternative Toggle Bit
mand. Once the Program/Erase Controller starts changes from ’0’ to ’1’ to ’0’, etc. with successive
erasing the Erase Timer Bit is set to ’1’. Before the Bus Read operations from addresses within the
Program/Erase Controller starts the Erase Timer blocks being erased. Bus Read operations to ad-
Bit is set to ’0’ and additional blocks to be erased dresses within blocks not being erased will output
may be written to the Command Interface. The the memory cell data as if in Read mode.
Erase Timer Bit is output on DQ3 when the Status
After an Erase operation that causes the Error Bit
Register is read.
to be set the Alternative Toggle Bit can be used to
Alternative Toggle Bit (DQ2). The Alternative identify which block or blocks have caused the er-
Toggle Bit can be used to monitor the Program/ ror. The Alternative Toggle Bit changes from ’0’ to
Erase controller during Erase operations. The Al- ’1’ to ’0’, etc. with successive Bus Read Opera-
ternative Toggle Bit is output on DQ2 when the tions from addresses within blocks that have not
Status Register is read. erased correctly. The Alternative Toggle Bit does
During Chip Erase and Block Erase operations the not change if the addressed block has erased cor-
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with rectly.
successive Bus Read operations from addresses

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 M29F160BT, M29F160BB

Table 11. AC Measurement Conditions

M29F160B
Parameter
55 / 70

AC Test Conditions High Speed

Load Capacitance (CL) 30pF

Input Rise and Fall Times ≤ 10ns

Input Pulse Voltages 0 to 3V

Input and Output Timing Ref. Voltages 1.5V

Figure 5. AC Testing Input Output Waveform Figure 6. AC Testing Load Circuit

1.3V

High Speed
1N914
3V

1.5V

0V 3.3kΩ

DEVICE
Standard UNDER OUT
TEST
2.4V CL = 30pF or 100pF
2.0V

0.8V
0.45V

AI01275B

CL includes JIG capacitance AI03027

Table 12. Capacitance

(TA = 25 °C, f = 1 MHz)
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 12 pF
Note: Sampled only, not 100% tested.

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M29F160BT, M29F160BB

Table 13. DC Characteristics

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA
ICC1 Supply Current (Read) E = VIL, G = VIH, f = 6MHz 20 mA

ICC2 Supply Current (Standby) TTL E = VIH 2 mA

E = VCC ± 0.2V,
ICC3 Supply Current (Standby) CMOS
RP = VCC ±0.2V
800 µA

Program/Erase
ICC4 (1) Supply Current (Program/Erase)
Controller active
20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8mA 0.45 V

Output High Voltage TTL IOH = –2.5mA 2.4 V

VOH
Output High Voltage CMOS IOH = –100µA VCC – 0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

Program/Erase Lockout Supply
VLKO (1) Voltage
3.2 4.2 V

Note: 1. Sampled only, not 100% tested.

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 M29F160BT, M29F160BB

Table 14. Read AC Characteristics

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F160B
Symbol Alt Parameter Test Condition Unit
55 70
E = VIL,
tAVAV tRC Address Valid to Next Address Valid Min 55 70 ns
G = VIL

E = VIL,
tAVQV tACC Address Valid to Output Valid Max 55 70 ns
G = VIL

tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 55 70 ns

tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 30 ns

tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 18 20 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 18 20 ns

tEHQX
Chip Enable, Output Enable or
tGHQX tOH Min 0 0 ns
Address Transition to Output Transition
tAXQX

tELBL tELFL
Chip Enable to BYTE Low or High Max 5 5 ns
tELBH tELFH

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 15 20 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 30 ns

Note: 1. Sampled only, not 100% tested.

Figure 7. Read Mode AC Waveforms

tAVAV
A0-A19/
VALID
A–1
tAVQV tAXQX

tELQV tEHQX

tELQX tEHQZ

tGLQX tGHQX

tGLQV tGHQZ
DQ0-DQ7/
VALID
DQ8-DQ15
tBHQV

BYTE

tELBL/tELBH tBLQZ AI02922

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M29F160BT, M29F160BB

Table 15. Write AC Characteristics, Write Enable Controlled

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M29F160B
Symbol Alt Parameter Unit
55 70
tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 40 45 ns

tDVWH tDS Input Valid to Write Enable High Min 25 30 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 40 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs

Note: 1. Sampled only, not 100% tested.

Figure 8. Write AC Waveforms, Write Enable Controlled

tAVAV
A0-A19/
VALID
A–1
tWLAX

tAVWL tWHEH

tELWL tWHGL

tGHWL tWLWH

tWHWL

tDVWH tWHDX
DQ0-DQ7/
VALID
DQ8-DQ15

VCC

tVCHEL

RB

tWHRL AI02923

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 M29F160BT, M29F160BB

Table 16. Write AC Characteristics, Chip Enable Controlled

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M29F160B
Symbol Alt Parameter Unit
55 70
tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 40 45 ns

tDVEH tDS Input Valid to Chip Enable High Min 25 30 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 40 45 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs

Note: 1. Sampled only, not 100% tested.

Figure 9. Write AC Waveforms, Chip Enable Controlled

tAVAV
A0-A19/
VALID
A–1
tELAX

tAVEL tEHWH

tWLEL tEHGL

tGHEL tELEH

tEHEL

tDVEH tEHDX
DQ0-DQ7/
VALID
DQ8-DQ15

VCC

tVCHWL

RB

tEHRL AI02924

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M29F160BT, M29F160BB

Table 17. Reset/Block Temporary Unprotect AC Characteristics

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M29F160B
Symbol Alt Parameter Unit
55 70

tPHWL (1)
RP High to Write Enable Low, Chip Enable Low,
tPHEL tRH Min 50 50 ns
(1)
Output Enable Low
tPHGL

tRHWL (1)
RB High to Write Enable Low, Chip Enable Low,
tRHEL (1) tRB Min 0 0 ns
Output Enable Low
(1)
tRHGL

tPLPX tRP RP Pulse Width Min 500 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 µs

tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 ns

Note: 1. Sampled only, not 100% tested.

Figure 10. Reset/Block Temporary Unprotect AC Waveforms

W, E, G

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

tPLPX
RP
tPHPHH

tPLYH

AI02931

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 M29F160BT, M29F160BB

Table 18. Ordering Information Scheme

Example: M29F160BB 70 N 1 T

Device Type
M29

Operating Voltage
F = VCC = 5V ± 10%

Device Function
160B = 16 Mbit (2Mb x8 or 1Mb x16), Boot Block

Array Matrix
T = Top Boot
B = Bottom Boot

Speed
55 = 55 ns
70 = 70 ns

Package
N = TSOP48: 12 x 20 mm

Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C

Option
T = Tape & Reel Packing

Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed
parts, otherwise devices are shipped from the factory with the memory content bits erased to ‘1’.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.

19/22
M29F160BT, M29F160BB

Table 19. Revision History

Date Revision Details
July 1999 First Issue
New document template
Status Register bit DQ5 clarification
Data Polling Flowchart diagram change (Figure 3)
Data Toggle Flowchart diagram change (Figure 4)
03/30/00
Program/Erase Times Maximum specification added (Table 9)
ICC3 Test Condition change (Table 13)
Removed 90ns speed option
TSOP48 Package mechanical data change (Table 20)

20/22
 M29F160BT, M29F160BB

Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A 1.20 0.0472
A1 0.05 0.15 0.0020 0.0059
A2 0.95 1.05 0.0374 0.0413
B 0.17 0.27 0.0067 0.0106
C 0.10 0.21 0.0039 0.0083
D 19.80 20.20 0.7795 0.7953
D1 18.30 18.50 0.7205 0.7283
E 11.90 12.10 0.4685 0.4764
e 0.50 – – 0.0197 – –
L 0.50 0.70 0.0197 0.0279
α 0° 5° 0° 5°
N 48 48
CP 0.10 0.0039

Figure 11. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2

1 N
e

B
N/2

D1 A
D CP

DIE

TSOP-a A1 α L
Drawing is not to scale.

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M29F160BT, M29F160BB

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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