M24256E-F

Datasheet

256-Kbit serial I²C bus EEPROM with configurable and preprogrammed device
address

Features
I²C interface
• Compatible with the following I²C bus modes:
– 1 MHz (Fast-mode Plus)
TSSOP8 SO8N
– 400 kHz (Fast-mode)
(169 mil width) (150 mil width)
– 100 kHz (Standard-mode)

Memory
• 256-Kbit (32-Kbyte) of EEPROM
• Page size: 64-byte
• Additional 64-byte identification page

UFDFPN8 (DFN8) UFDFPN5 (DFN5) Supply voltage

(2 x 3 mm) (1.7 x 1.4 mm) • Wide voltage range: 1.6 V to 5.5 V

Temperature
• Operating temperature range: -40 °C to +85 °C

Fast write cycle time

• Byte and page write within 5 ms (typically 3.2 ms)

Unsawn wafer Performance

• Enhanced ESD/latch-up protection
• More than 4 million write cycles
• More than 200-year data retention
• Fast wake-up time (less than 5 μs)
Product label
Ultralow power current consumption
• 310 nA (typical) in standby mode
• 100 μA (typical) for read current
• 150 μA (typical) for write current

Advanced features
• Configurable device address register
Product status • Preprogrammed device address
M24256E-F • Hardware write protection of the whole memory array
• Random and sequential read modes

Package
• SO8N, TSSOP8, UFDFPN8, and UFDFPN5 (ECOPACK2)
• Unsawn wafer (each die is tested)

DS12687 - Rev 5 - February 2025 www.st.com

For further information, contact your local STMicroelectronics sales office.
 M24256E-F
Description

1 Description

The M24256E-F is a 256-Kbit I²C-compatible EEPROM (electrically erasable programmable memory) organized
as 32 K x 8 bits. It can operate with a supply voltage from 1.65 V to 5.5 V with a clock frequency up to 1 MHz,
over an ambient temperature ranging from -40 °C to +85 °C. It can also operate down to 1.6 V under some
restricting conditions.
The device offers an additional 8-bit register, called the configurable device address (CDA) register. This page
authorizes the user, through software, to configure up to eight possible chip enable address.
The device also offers an additional 64-byte page, called the identification page. This page can be used to store
sensitive application parameters, which can later be permanently locked in read-only mode.
On demand, the EEPROM can be delivered with a preprogrammed and locked device address.

Figure 1. Logic diagram

VCC

SCL
M24256E-F SDA
WC

DT76007V1
VSS

Table 1. Signal names

Signal name Function Direction

SDA Serial data I/O

SCL Serial clock Input
VCC Supply voltage -

VSS Ground -

WC Write control Input

Figure 2. 5-pin package connection

VCC 1 5 WC 5 1
ABCD
VSS 2 2 VSS 2 2
XYZW
SDA 3 4 SCL 4 3

Top view Bottom view

(marking side) (pads side)

DS12687 - Rev 5 page 2/48

 M24256E-F
Description

Figure 3. 8-pin package connections, top view

NC 1 8 VCC

NC 2 7 WC

DT54532V1
NC 3 6 SCL

VSS 4 5 SDA

1. NC: Not connected.

2. See Section 10: Package information for package dimensions and instruction on how to identify pin 1.

DS12687 - Rev 5 page 3/48

 M24256E-F
Signal description

2 Signal description

2.1 Serial clock (SCL)

SCL is an input. The signal applied on it is used to strobe the data available on SDA(in) and to output it on
SDA(out).

2.2 Serial data (SDA)

SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open-drain output that can be
wired-AND with other open-drain or open-collector signals on the bus. A pull‑up resistor must be connected from
serial data (SDA) to VCC (Figure 21 and Figure 22 indicate how to calculate the value of the pull-up resistor).

2.3 Write control (WC)

This input signal is useful for protecting the contents of the memory and the configurable device address register
from inadvertent write operations. All write operations are disabled when the WC is driven high. All write
operations are enabled when WC is either driven low or left floating.
When WC is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged.

2.4 VSS (ground)

VSS is the reference for the VCC supply voltage.

2.5 Supply voltage (VCC)

2.5.1 Operating supply voltage (VCC)

Before selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified
[VCC(min), VCC(max)] range must be applied (see operating conditions in Section 9: DC and AC parameters). To
secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually
from 10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write
instruction, until the completion of the internal write cycle (tW).

2.5.2 Power-up conditions

The VCC voltage must increases from 0 V up to the minimum VCC operating voltage (see Table 9. Operating
conditions).
Once VCC is greater than or equal to the minimum VCC level, the controller must wait for at least tWU before
sending the first command to the device. See Table 15 for the value of the wake-up time parameter.

2.5.3 Device reset

To prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold
voltage. This threshold is lower than the minimum VCC operating voltage (see operating conditions in
Section 9: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the
standby power mode; the device must not be accessed until VCC reaches a valid and stable DC voltage within the
specified [VCC(min), VCC(max)] range (see operating conditions in Section 9: DC and AC parameters).
Similarly, during power-down, when the VCC decreases, the device must not be accessed once VCC drops below
VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any
instruction sent to it.

2.5.4 Power-down conditions

During power-down, when the VCC decreases down to 0 V, the device must be in the standby power mode. This
mode is reached after decoding a stop condition, with no internal write cycle in progress.

DS12687 - Rev 5 page 4/48

 M24256E-F
Memory organization

3 Memory organization

The memory is organized as shown in the following figure.

Figure 4. Block diagram

SENSE AMPLIFIERS
DATA REGISTER
+
ECC
PAGE LATCHES X DECODER

Y DECODER
SCL ARRAY

I/O

SDA
CONTROL CUSTOM AREA(1)
LOGIC
WC START & STOP HV GENERATOR
DETECT +
SEQUENCER

ADDRESS
REGISTER

1. ID page and CDA register area.

DS12687 - Rev 5 page 5/48

 M24256E-F
Device features

4 Device features

4.1 Configurable device address register (CDA)

The CDA is an 8-bit register allowing the user to define a configurable device address (C2, C1, and C0), and
includes a specific bit, named device address lock (DAL), to permanently freeze the configurable device address
register. This register can be read and written by issuing the read or write configurable device address instruction.
These instructions use the same protocol and format as the random address read or page write (from/into
memory array) except for the following differences (refer to Table 5, Table 6, and Table 7):
• Device type identifier = 1011
• MSB address bits A15, A14, and A13 must be equal to 110
• MSB address bits from A12 to A8 are don't care
• LSB address bits from A7 to A0 are don't care
C2, C1, C0, and DAL are defining the chip enable address in the device select code and the device address lock.
These bits can be written and reconfigured with a write command.
At power-up or after reprogramming, the device loads the last configuration of C2, C1, and C0, and DAL values.
To prevent unwanted change of configurable device address bits, the M24256E-F proposes to protect the CDA
register permanently freezing it in read-only mode. The update of the CDA register is disabled (read-only) when
the DAL bit is set to 1 (DAL = 1).
In the same way, the update of the CDA register is enabled when the DAL bit is set to 0 (DAL = 0). Sending more
than one byte during a write configurable device address command aborts the write cycle (CDA register content
does not change).
Note: • Updating the DAL bit from 0 to 1 is an irreversible action: the C2, C1, and C0, and DAL bits cannot be
updated anymore.
• If the write control input (WC) is driven high, or if the DAL bit is set to 1 the write configurable device
address command is not executed, the accompanying data byte is not acknowledged, as shown in
Figure 9, and the write cycle does not start.
The description of the configurable device address register is given in Table 2.

Table 2. Configurable device address register

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

X (1) X X X C2 C1 C0 DAL

1. X = Don’t care bits. Read as 0.

Note: The factory default value is 00000000.

For devices delivered with preprogrammed device address:
• The default value of C2, C1, and C0 are given in Table 4. Preprogrammed device address.
• DAL is set to 1

DS12687 - Rev 5 page 6/48

 M24256E-F
Device features

Table 3. Configurable device address register description

Bit Function

b7 to b4 Don't care bits - Read as 0. (b7, b6, b5, b4) = (0, 0, 0, 0)

C2, C1, C0: Configurable device address bits.
b3, b2, b1 are used to configure up to eight possibilities of chip enable address:
• (b3, b2, b1) = (0, 0, 0): the chip enable address is 000 (factory delivery value)
• (b3, b2, b1) = (0, 0, 1): the chip enable address is 001
b3 to b1 • (b3, b2, b1) = (0, 1, 0): the chip enable address is 010
• (b3, b2, b1) = (0, 1, 1): the chip enable address is 011
• (b3, b2, b1) = (1, 0, 0): the chip enable address is 100
• (b3, b2, b1) = (1, 0, 1): the chip enable address is 101
• (b3, b2, b1) = (1, 1, 0): the chip enable address is 110
• (b3, b2, b1) = (1, 1, 1): the chip enable address is 111
DAL: Device address lock bit.
b0 locks the CDA register in read-only mode:

b0 • b0 = 0: bits b3, b2, b1, b0 can be modified

• b0 = 1: bits b3, b2, b1, b0 cannot be modified and therefore the CDA register is frozen
Note: Bits b3 to b0 can be updated (if b0 = 0) in the same write instruction. Setting b0 from 0
to 1 is an irreversible action.

If the M24256E-F is delivered with the preprogrammed device address, the configurable device address register
becomes locked at factory delivery and can only be read. The C2, C1, and C0 bits are set as specified in Table 4.
Preprogrammed device address, and the DAL bit is set to 1.
The corresponding commercial product number with the preprogrammed device address is given in Table 4.

Table 4. Preprogrammed device address

Chip enable address bits

Commercial product number(1) DAL bit Availability(2)
C2 C1 C0

M24256E-Fxx6T0 0 0 0 1 Yes
M24256E-Fxx6T1 0 0 1 1 Yes
M24256E-Fxx6T2 0 1 0 1 On demand
M24256E-Fxx6T3 0 1 1 1 On demand
M24256E-Fxx6T4 1 0 0 1 Yes
M24256E-Fxx6T5 1 0 1 1 On demand
M24256E-Fxx6T6 1 1 0 1 On demand
M24256E-Fxx6T7 1 1 1 1 On demand

1. 'xx' in the part number varies by package.

2. The product might not be available in all packages. For any information, contact the nearest sales office.

DS12687 - Rev 5 page 7/48

 M24256E-F
Device features

4.2 Identification page

The identification page (64 bytes) is an additional page, which can be read or written and can later permanently
locked in read-only mode. It is read or written by issuing the read or write identification page instruction. These
instructions use the same protocol and format as the random address read or page write (from/into a memory
array) except for the following differences (refer to Table 5, Table 6, and Table 7):
• Device type identifier = 1011
• MSB address bits from A15 to A6 are don't care except for address bit A10 that must be 0
• LSB address bits from A5 to A0 define the byte address inside the identification page
If the identification page is locked, the data bytes transferred during the write identification page instruction are not
acknowledged (NO ACK).
Note: The MSB address bits A15, A14, and A13 with the value 110 are only recognized and decoded only for CDA
management.

DS12687 - Rev 5 page 8/48

 M24256E-F
Device operation

5 Device operation

The device supports the I²C protocol summarized in Figure 5. Any device that sends data onto the bus is defined
as a transmitter, and any device that reads the data is defined as a receiver. The device that controls the data
transfer is known as the bus controller, and the other as the target. A data transfer can only be initiated by the bus
controller, which also provides the serial clock for synchronization. The device is always a target in all
communications.

Figure 5. I²C bus protocol

SCL

SDA

SDA SDA
START STOP
Input Change
Condition Condition

SCL 1 2 3 7 8 9

SDA MSB ACK

START
Condition

SCL 1 2 3 7 8 9

SDA MSB ACK

DT00792D_V1

STOP
Condition

DS12687 - Rev 5 page 9/48

 M24256E-F
Device operation

5.1 Start condition

The start condition is identified by a falling edge of serial data (SDA) while the serial clock (SCL) is stable in the
high state. This condition must precede any data transfer instruction. The device continuously monitors the SDA
and SCL for a start signal, except during a write cycle.

5.2 Stop condition

The stop condition is identified by a rising edge of serial data (SDA) while the serial clock (SCL) is stable in the
high state. This condition terminates the communication between the device and the bus controller. A read
instruction is followed by NO ACK followed by a stop condition to force the device into the standby mode.
A stop condition at the end of a write instruction triggers the internal write cycle.

5.3 Data input

During data input, the device samples serial data (SDA) on the rising edge of the serial clock (SCL). For proper
device operation, the SDA must be stable during the rising edge of the SCL, and the SDA signal must change
only when the SCL is driven low.

5.4 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether a bus controller
or target device, releases serial data (SDA) after sending eight bits of data. During the ninth clock pulse period,
the receiver pulls SDA low to acknowledge the receipt of the eight data bits.

DS12687 - Rev 5 page 10/48

 M24256E-F
Device operation

5.5 Device addressing

To start communication between the bus controller and the target device, the bus controller must initiate a start
condition. Following this, and unless the product is delivered with the preprogrammed device address, the bus
controller sends the device select code and byte address as specified in Table 5, Table 6, and Table 7. When the
device select code is received, the device responds only if the bits b3, b2, and b1 values match the values of the
C2, C1, and C0 bits programmed in the configurable device address register.
If a match occurs, the corresponding device gives an acknowledgment on serial data (SDA) during the ninth bit
time. If the device does not acknowledge the device select code, it deselects itself from the bus and goes into
standby mode after a stop condition.
The eighth bit is the read/write bit (RW). This bit is set to 1 for read and 0 for write operations.

Table 5. Device select code

Device type identifier bits Chip enable address bits(1) RW

Features
Bit 7 (MSB)(2) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

Memory 1 0 1 0 C2 C1 C0 RW
Identification page 1 0 1 1 C2 C1 C0 RW
Identification page lock 1 0 1 1 C2 C1 C0 RW
Configurable device address 1 0 1 1 C2 C1 C0 RW

1. C0, C1 and C2 are compared with the value read on bits b1, b2, and b3 of the CDA register.
2. The most significant bit, b7, is sent first.

Table 6. First byte address

Features Bit 7 (MSB)(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

Memory X(2) A14 A13 A12 A11 A10 A9 A8

Identification page X(3) X(3) X(3) X X 0 X X

Identification page lock X(3) X(3) X(3) X X 1 X X

Configurable device address 1 1 0 X X X X X

1. The most significant bit, b7, is sent first.

2. X = Don't care bit.
3. For the identification page, do not use A15, A14 and A13 equal to 110.

Table 7. Second byte address

Features Bit 7 (MSB)(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

Memory A7 A6 A5 A4 A3 A2 A1 A0

Identification page X(2) X A5 A4 A3 A2 A1 A0

Identification page lock X X X X X X X X

Configurable device address X X X X X X X X

1. The most significant bit, b7, is sent first.

2. X = Don't care bit

DS12687 - Rev 5 page 11/48

 M24256E-F
Instructions

6 Instructions

6.1 Write operations on memory array

Following a start condition the bus controller sends a device select code with the R/W bit (RW) set to 0. The
device acknowledges this, as shown in Figure 6, and waits for two address bytes. The device responds to each
address byte with an acknowledge bit, and then waits for the data byte. See in Table 5, Table 6, and Table 7 how
to address the memory array.
When the bus controller generates a stop condition immediately after a data byte ACK bit (in the tenth bit time
slot), either at the end of a byte write or a page write, the internal write cycle tW is triggered. A stop condition at
any other time slot does not trigger the internal write cycle.
After the stop condition and the successful completion of an internal write cycle (tW), the device internal address
counter is automatically incremented to point to the next byte after the last modified byte.
During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any
requests.
If the addressed area is write protected through WC pin driven high, the write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 7.

DS12687 - Rev 5 page 12/48

 M24256E-F
Instructions

6.1.1 Byte write

After the device select code and the address bytes, the bus controller sends one data byte. If the addressed
location is write-protected, by write control WC being driven high, the device replies with NO ACK, and the
location is not modified, as shown in Figure 7. If, instead, the addressed location is not write-protected, the device
replies with ACK. The bus controller terminates the transfer by generating a stop condition, as shown in Figure 6.

Figure 6. Write mode sequence without write protection (data write enabled)

WC

ACK ACK ACK ACK

Byte write Dev sel Byte addr Byte addr Data in

Start

Stop
RW

WC

ACK ACK ACK ACK

Page write Dev sel Byte addr Byte addr Data in 1 Data in 2
Start

RW

WC (cont’d)

ACK ACK

Page write (cont’d) Data in N

DT01106dV2
Stop

DS12687 - Rev 5 page 13/48

 M24256E-F
Instructions

6.1.2 Page write

Using this mode it is possible to write up to 64 bytes in a single write cycle, provided they are all located in the
same page in the memory. This means that the most significant memory address bits, from A14 to A6, are the
same. If more bytes are sent than fit up to the end of the page, a roll-over occurs: the bytes exceeding the page
end are written on the same page, from location 0.
The bus controller sends from 1 to 64 bytes of data, each of which is acknowledged by the device if the write
control (WC) is low. In the opposite case, when the addressed bytes are write-protected by the WC pin (driven
high), the contents of the addressed memory location are not modified, and each data byte is followed by a NO
ACK, as shown in Figure 7. After each transferred byte, the internal page address counter is incremented.
The transfer is terminated when the bus controller generates a stop condition.

Figure 7. Write mode sequence with write protection (data write inhibited)

WC

Byte write

WC

Page write

Page write (cont’d)

DT01120dV2

DS12687 - Rev 5 page 14/48

 M24256E-F
Instructions

6.2 Write operations on register and identification page

6.2.1 Write operation on CDA register

Write operations on the configurable device address register are performed according to the state of the device
address lock bit (DAL) or the status of the WC line.
If the configurable device address register is write protected by software with DAL = 1 or hard protected with WC
line driven high, the write operation on this register is not executed and the accompanying data byte is not
acknowledged as shown in Figure 9.
Following a start condition the bus controller sends a device select code with the R/W bit (RW) set to 0. The
device acknowledges this, as shown in Figure 8, and waits for the address bytes where the register is located.
The device responds to each address byte with an acknowledge bit, and then waits for the data byte. See in
Table 5, Table 6, and Table 7 how to address the configurable device address register.
When the bus controller generates a stop condition immediately after the data byte ACK bit (in the tenth bit time
slot), the internal write cycle tW is triggered. A stop condition at any other time slot does not trigger the internal
write cycle.
During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any
requests (NO ACK).
If the three-bit C2, C1, and C0 have been reconfigured with a correct write command, the device acknowledges if
the chip enable address of the device select code is equal to the new values of C2, C1, and C0, otherwise NO
ACK. Sending more than one byte aborts the write cycle (configurable device address content does not change).
Bits (C2, C1, C0, and DAL) can be updated (DAL = 0 to 1) in the same program instruction. For devices delivered
with the preprogrammed device address, the configurable device address register is in read‑only mode.

Figure 8. Write CDA register (data write enabled)

ACK ACK ACK ACK

Dev sel Byte addr Byte addr Data in

Start

DT67285V1
Stop
RW

Figure 9. Write CDA register (data write inhibited by software or hardware)

ACK ACK ACK NO ACK

Dev sel Byte addr Byte addr Data in

Stop

DT67286V1
Start

R/W

DS12687 - Rev 5 page 15/48

 M24256E-F
Instructions

6.2.2 Write operation on identification page

Following a start condition the bus controller sends a device select code with the R/W bit (RW) set to 0. The
device acknowledges this, as shown in Figure 10, and waits for the address bytes where the identification page is
located. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. See
in Table 5, Table 6, and Table 7 how to address the identification page.
When the bus controller generates a stop condition immediately after the data byte ACK bit (in the tenth bit time
slot), the internal write cycle tW is triggered. The device internal address counter is automatically incremented to
point to the next byte after the last modified byte.
A stop condition at any other time slot does not trigger the internal write cycle.
During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any
requests (NO ACK).
If the identification page is already locked or hard write protected with WC line driven high, the write operation is
not executed and the accompanying data bytes are not acknowledged as shown in Figure 11.

Figure 10. Write identification page (page unlocked)

ACK ACK ACK ACK

Byte Write Dev sel Byte addr Byte addr Data in

Start

Stop
R/W

ACK ACK ACK ACK

Page Write Dev sel Byte addr Byte addr Data in 1

Start

R/W

ACK ACK

Page Write
Data in N
(cont'd)
DT73085V1
Stop

DS12687 - Rev 5 page 16/48

 M24256E-F
Instructions

Figure 11. Write identification page (page locked or hard protected)

ACK ACK ACK NO ACK

Byte Write Dev sel Byte addr Byte addr Data in

Start

Stop
R/W

ACK ACK ACK NO ACK

Page Write Dev sel Byte addr Byte addr Data in 1 Data in 2
Start

R/W

NO ACK NO ACK

Page Write
Data in N
(cont'd)

DT73086V1
Stop

DS12687 - Rev 5 page 17/48

 M24256E-F
Instructions

6.2.3 Lock operation on identification page

The lock identification page instruction (lock ID) permanently locks the identification page in read-only mode.
Following a start condition the bus controller sends a device select code with the R/W bit (RW) set to 0. The
device acknowledges this, as shown in Figure 12, and waits for the address bytes where the identification page is
located. The device responds to each address byte with an acknowledge bit, and then waits for a specific data
byte value. See in Table 5, Table 6, and Table 7 how to address the identification page.
The data byte must be equal to the binary value xxxx xx1x, where x is don't care.
When the bus controller generates a stop condition immediately after the data byte ACK bit (in the tenth bit time
slot), the internal write cycle tW is triggered. A stop condition at any other time slot does not trigger the internal
write cycle.
During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any
requests (NO ACK).
If the identification page is already locked or hard write protected with WC line driven high, the write operation is
not executed and the accompanying data bytes are not acknowledged as shown in Figure 13.

Figure 12. Lock operation on identification page (unlocked or data write enabled)

ACK ACK ACK ACK

Dev sel Byte addr Byte addr Data in

Start

DT67285V1
Stop
RW

Figure 13. Lock operation on identification page (already locked or data write inhibited by hardware)

ACK ACK ACK NO ACK

Dev sel Byte addr Byte addr Data in

Stop

DT67286V1
Start

R/W

DS12687 - Rev 5 page 18/48

 M24256E-F
Instructions

6.3 Minimizing write delays by polling on ACK

During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its
internal latches to the memory cells. The maximum write time (tw) is shown in Table 15. AC characteristics, but
the typical time is shorter. The bus controller can implement a polling sequence to utilize this feature
The sequence, as shown in Figure 14, is:
• Initial condition: a write cycle is in progress.
• Step 1: the bus controller issues a start condition followed by a device select code (the first byte of the new
instruction).
• Step 2: if the device is busy with the internal write cycle, NO ACK is returned and the bus controller goes
back to step 1. If the device has terminated the internal write cycle, it responds with an ACK, indicating that
the device is ready to receive the second part of the instruction (the first byte of this instruction having been
sent during step 1).
Note: When writing a write command to the configurable device address register, when C2, C1, and C0 are
reconfigured, the device returns an ACK only if:
• The chip enable address of the device select code is equal to the new C2, C1, and C0 values.
• An internal write cycle is completed (the new C2, C1, and C0 values have been programmed in the chip
enable register).

Figure 14. Write cycle polling flowchart using ACK

Write cycle
in progress

Start condition

Device select
with RW = 0

NO ACK
returned

First byte of instruction YES

with RW = 0 already
decoded by the device

Next
NO operation is YES
addressing the
memory
Send address
Restart and receive ACK

Stop NO YES
StartCondition

Data for the Device select

write operation with RW = 1
DT01847eV1

Continue the Continue the

write operation random read operation

Note: The seven most significant bits of the device select code of a random read (bottom-right box in the Figure 14)
must match those of the device select code of the write operation (polling instruction in the Figure 14).

DS12687 - Rev 5 page 19/48

 M24256E-F
Instructions

6.4 ECC (error correction code) and write cycling

The error correction code (ECC) is an internal logic function transparent for the I²C communication protocol.
The ECC logic is implemented on each group of four bytes (located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3],
where N is an integer). Within a group, if a single bit happens to be erroneous during a read operation, the ECC
detects and replaces it with the correct value. The read reliability is therefore much improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently.
In this case, the ECC function also writes/cycles the three other bytes located in the same group. As a
consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the
four bytes of the group: the sum of the cycles seen by byte 0, byte 1, byte 2 and byte 3 of the same group must
remain below the maximum value defined in Table 12. Cycling performance by groups of four bytes.

DS12687 - Rev 5 page 20/48

 M24256E-F
Instructions

6.5 Read operations on memory array

Following a start condition the bus controller sends a device select code with the R/W bit (R/W) set to 0. The
device acknowledges this and waits for the two-byte address. The device responds to each address byte with an
acknowledge bit. Then, the bus controller sends another start condition, and repeats the device select code, with
the RW bit set to 1. The device acknowledges this, and outputs the contents of the data. See in Table 5, Table 6,
and Table 7 how to address the memory array.
After each byte read (data out), the device waits for an acknowledgment (data in) during the ninth bit time. If the
bus controller does not acknowledge during this interval, the device terminates the data transfer and switches to
its standby mode after a stop condition.
After the successful completion of a read operation, the internal address counter is incremented by one, to point
to the next byte address.

Figure 15. Read mode sequences

ACK NO ACK
Current
address Dev sel Data out
read
Start

Stop
RW

ACK ACK ACK ACK NO ACK

Random
address Dev sel * Byte addr Byte addr Dev sel * Data out
read
Start

Start

Stop
RW RW

ACK ACK ACK NO ACK

Sequential
current Dev sel Data out 1 Data out N
read
Start

Stop

RW

ACK ACK ACK ACK ACK

Sequential
random Dev sel * Byte addr Byte addr Dev sel * Data out1
read
Start

Start

RW RW

ACK NO ACK

Data out N
DT01105dV1
Stop

Note: The seven most significant bits of the first device select code of a random read must match those of the device
select code in the write operation.

DS12687 - Rev 5 page 21/48

 M24256E-F
Instructions

6.5.1 Random address read

A dummy write is first performed to load the address into this address counter (as shown in Figure 15) but without
sending a stop condition. Then, the bus controller sends another start condition, and repeats the device select
code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte.
The bus controller must not acknowledge the byte, and terminates the transfer with a stop condition.

6.5.2 Current address read

For the current address read operation, following a start condition, the bus controller sends only a device select
code with the RW bit set to 1. The device acknowledges this and outputs the byte addressed by the internal
address counter. The counter is then incremented. The bus controller terminates the transfer with a stop
condition, as shown in Figure 15, without acknowledging the byte.
Note: The address counter value is defined by instructions accessing either the memory, the register, or the
identification page. When accessing the register or the identification page, the address counter value is loaded
with the register or the identification page byte location, therefore the next current address read in the memory
uses this new address counter value. When accessing the memory, it is safer to always use the random address
read instruction (this instruction loads the address counter with the byte location to read in the memory) instead
of the current address read instruction.

6.5.3 Sequential read

This operation can be used after a current address read or a random address read. The bus controller does
acknowledge the data byte output and sends additional clock pulses so that the device continues to output the
next byte in sequence. To terminate the stream of bytes, the bus controller must not acknowledge the last byte,
and must generate a stop condition, as shown in Figure 15.
The output data comes from consecutive addresses, with the internal address counter automatically incremented
after each byte is output. After reaching the last memory address, the address counter rolls over, and the device
continues to output data from the memory address 00h.

DS12687 - Rev 5 page 22/48

 M24256E-F
Instructions

6.6 Read operations on register and identification page

Only the random address read or sequential random read commands are authorized to access the CDA register.
The address counter contains a meaningful address value only after these authorized commands have been
performed.

6.6.1 Read operation on CDA address register

Following a start condition the bus controller sends a device select code with the RW bit (RW) set to 0. The
device acknowledges this and waits for the address bytes where the CDA register is located. The device
responds to each address byte with an acknowledge bit. Then, the bus controller sends another start condition,
and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the
contents of the CDA register. See in Table 5, Table 6, and Table 7 how to address the configurable device address
register.
After the successful completion of a read configurable device address, the device internal address counter is not
incremented by one, to point to the next byte address. Reading more than one-byte loops on reading the
configurable device address register value.
To terminate the stream of data byte, the bus controller must not acknowledge the byte, and must generate a stop
condition, as shown in Figure 16.
The configurable device address register cannot be read while a write cycle (tW) is ongoing.
The value of the configurable device address bits (C2, C1, and C0) can be checked by sending the device select
code.
• If the chip enable address bit3, bit2, and bit1 sent in the device select code is matching with the C2, C1,
and C0 values, the device sends an ACK
• Otherwise, the device answers NO ACK

Figure 16. Random read on configuration device address register

ACK ACK ACK ACK NO ACK

Dev sel* Byte addr Byte addr Dev sel* Data out

DT51972V1
Start
Start

Stop
RW RW

*.: The seven most significant bits of the first device select code in a random read must match those of the device
select code in the write operation.

DS12687 - Rev 5 page 23/48

 M24256E-F
Instructions

6.6.2 Read operation on identification page

Following a start condition the bus controller sends a device select code with the RW bit (RW) set to 0. The
device acknowledges this and waits for the address bytes where the identification page is located. The device
responds to each address byte with an acknowledge bit. Then, the bus controller sends another start condition,
and repeats the same device select code with the RW bit set to 1. The device acknowledges this, and outputs the
contents of the identification page. See in Table 5, Table 6, and Table 7 how to address identification page.
Note: The bits from A6 to A0 define the byte address inside the identification page.
The number of bytes to read in the ID page must not exceed the page boundary. For instance when reading the
identification page from location 10d, the number of bytes must be less than or equal to 54, as the ID page
boundary is 64 bytes. After the 64th byte of the identification page, there is no roll-over to the beginning of the
page.
To terminate the stream of data byte, the bus controller must not acknowledge the byte, and must generate a stop
condition, as shown in Figure 16.
If the bus controller does not acknowledge during this ninth time, the device terminates the data transfer as shown
in Figure 17. Random read identification page and switches to its standby mode.

Figure 17. Random read identification page

ACK ACK ACK ACK NO ACK

Random
address Dev sel * Byte addr Byte addr Dev sel * Data out
read
Start

Start

Stop
RW RW

ACK ACK ACK ACK ACK

Sequential
random Dev sel * Byte addr Byte addr Dev sel * Data out1
read
Start

Start

RW RW

ACK NO ACK

Data out N

DT54535V2
Stop

*: The seven most significant bits of the first device select code in a random read must match those of the device
select code in the write operation.

DS12687 - Rev 5 page 24/48

 M24256E-F
Instructions

6.6.3 Read lock status on identification page

The lock or unlock status of the identification page can be checked by transmitting a specific truncated command.
Following a start condition the bus controller sends a device select code with the R/W bit (RW) set to 0. The
device acknowledges this and waits for the address bytes where the identification page is located. The device
responds to each address byte with an acknowledge bit, and then waits for the data byte. See in Table 5, Table 6,
and Table 7 how to address the identification page.
The device returns an acknowledge bit after the data byte if the identification page is unlocked (unlock status) as
shown in Figure 18, otherwise a NO ACK bit as shown in Figure 19, if the identification page is locked (lock
status).
Right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that:
• Start: the truncated command is not executed because the start condition resets the device internal logic
• Stop: the device is then set back into standby mode by the stop condition

Figure 18. Read lock status (identification page unlocked)

ACK ACK ACK ACK

Dev sel Byte addr Byte addr Data in

DT54538V1
Stop
Start

Start
RW

Figure 19. Read lock status (identification page locked)

ACK ACK ACK NO ACK

Dev sel Byte addr Byte addr Data in

DT54539V1
Stop
Start

Start
RW

DS12687 - Rev 5 page 25/48

 M24256E-F
Initial delivery state

7 Initial delivery state

At factory delivery, unless a device-specific address has been preprogrammed, the device is delivered with:
• All the memory array bits set to 1 (each byte contains FFh)
• The CDA register set to 00000000 (00h)
• All the identification page bits set to 1 (each byte contains FFh)

DS12687 - Rev 5 page 26/48

 M24256E-F
Maximum ratings

8 Maximum ratings

Stressing the device outside the ratings listed in Table 8 may permanently damage it. These are stress ratings
only, and operation of the device at these, or any other conditions outside those indicated in the operating
sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Table 8. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

- Ambient operating temperature -40 130 °C

TSTG Storage temperature -65 150 °C

TLEAD Lead temperature during soldering See note (1) °C

IOL DC output current (SDA = 0) - 5 mA

VIO Input or output range -0.50 6.5 V

VCC Supply voltage -0.50 6.5 V

VESD Electrostatic pulse (human body model) (2) - 4000 V

1. Compliant with JEDEC standard J-STD-020 (for small-body, Sn-Pb or Pb free assembly), the ST ECOPACK 7191395
specification, and the European directive on restrictions on hazardous substances (RoHS directive 2011/65/EU of July
2011).
2. Positive and negative pulses applied on different combinations of pin connections, according to ANSI/ESDA/JEDEC JS-001
(C1=100 pF, R1=1500 Ω, R2 = 500 Ω).

DS12687 - Rev 5 page 27/48

 M24256E-F
DC and AC parameters

9 DC and AC parameters

Table 9. Operating conditions

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.6 1.65 5.5 V

Ambient operating temperature: READ -40 -40 85

TA °C
Ambient operating temperature: WRITE 0 -40 85
fC Operating clock frequency - 1 MHz

Table 10. AC measurement conditions

Symbol Parameter Min. Max. Unit

Cbus Load capacitance - 100 pF

- SCL input rise/fall time, SDA input fall time - 50 ns

- Input levels 0.2 VCC to 0.8 VCC V

- Input and output timing reference levels 0.3 VCC to 0.7 VCC V

Figure 20. AC measurement I/O waveform

Input and output

Input voltage levels timing reference levels

0.8 x Vcc
0.7 x Vcc

DT54878V1
0.3 x Vcc
0.2 x Vcc

Table 11. Input parameters

Symbol Parameter Test condition Min. Max. Unit

CIN (1) Input capacitance (SDA) - - 8 pF

CIN (1) Input capacitance (other pins) - - 6 pF

ZL (2) VIN < 0.3 VCC 30 - kΩ

Input impedance (WC)(3)
ZH(2) VIN > 0.7 VCC 500 - kΩ

1. Specified by design - Not tested in production.

2. Evaluated by characterization – Not tested in production.
3. The memory is selected after a start condition.

DS12687 - Rev 5 page 28/48

 M24256E-F
DC and AC parameters

Table 12. Cycling performance by groups of four bytes

Symbol Parameter Test condition Max. Unit

TA ≤ 25 °C, VCC(min) < VCC < VCC(max) 4 000 000

Ncycle Write cycle endurance(1) Write cycle(2)
TA = 85°C, VCC(min) < VCC < VCC(max) 1 200 000

1. The write cycle endurance is defined by characterization and qualification. For devices embedding the ECC functionality, the
write cycle endurance is defined for group of four bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an
integer.
2. A write cycle is executed when either a write CDA register, a page write, a byte write , a write identification page or a lock
identification page instruction is decoded. When using the byte write, the page write, or the write identification page, refer
also to Section 6.4: ECC (error correction code) and write cycling.

Table 13. Memory cell data retention

Parameter Test condition Min. Unit

Data retention (1) TA = 55 °C 200 Year

1. The data retention behaviour is checked in production, while the data retention limit defined in this table is extracted from
characterization and qualification results.

DS12687 - Rev 5 page 29/48

 M24256E-F
DC and AC parameters

Table 14. DC characteristics

Symbol Parameter Test conditions Min. Max. Unit

Input leakage current VIN = VSS or VCC

ILI - ±2 µA
(SCL, SDA) device in standby mode
ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA

fC = 400 kHz - 0.5(1)

ICC Supply current (read) mA
fC = 1 MHz - 1(2)

ICC0 Supply current (write) Value averaged over tW - 1 (3)(4) mA

Device not selected, (5)

- 1(6)
VIN = VSS or VCC, VCC < 2.5 V
ICC1 Standby supply current µA
Device not selected, (5)
- 2
VIN = VSS or VCC, VCC ≥ 2.5 V

Input low voltage 1.6 ≤ VCC < 2.5 V –0.45 0.25 VCC V
VIL
(SCL, SDA, WC) 2.5 ≤ VCC ≤ 5.5 V –0.45 0.3 VCC V

Input high voltage 1.6 ≤ VCC < 2.5 V 0.75 VCC 6 V

(SCL, SDA) 2.5 ≤ VCC ≤ 5.5 V 0.7 VCC 6 V
VIH
1.6 ≤ VCC < 2.5 V 0.75 VCC VCC + 0.6 V
Input high voltage
(WC) 2.5 ≤ VCC ≤ 5.5 V 0.7 VCC VCC + 0.6 V

IOL = 1 mA, VCC = 1.6 V - 0.2 V

VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or
- 0.4 V
IOL = 3 mA, VCC = 5.5 V

1. The typical value at 1.8 V is 80 μA. It is evaluated by characterization - Not tested in production.
2. The typical value at 1.8 V is 100 μA. It is evaluated by characterization - Not tested in production.
3. Evaluated by characterization – Not tested in production.
4. The typical value at 1.8 V is 150 μA. It is evaluated by characterization - Not tested in production.
5. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the
internal write cycle tW (tW is triggered by the correct decoding of a write instruction).
6. The typical value at 1.8 V is 310 nA. It is evaluated by characterization - Not tested in production.

DS12687 - Rev 5 page 30/48

 M24256E-F
DC and AC parameters

Table 15. AC characteristics

Standard mode Fast-mode Fast-mode plus

Symbol Alt. Parameter Unit
Min. Max. Min. Max. Min. Max.

fC fSCL Clock frequency - 100 - 400 - 1000 kHz

tCHCL tHIGH Clock pulse width high 4000 - 600 - 260 - ns

tCLCH tLOW Clock pulse width low 4700 - 1300 - 500 - ns

tQL1QL2 (1) tF SDA (out) fall time - 300 20(2) 300 20(2) 120 ns

tXH1XH2 (1) tR Input signal rise time - 1000 (3) (3) (4) (4) ns

tXL1XL2(1) tF Input signal fall time - 300 (3) (3) (4) (4) ns

tDVCH tSU:DAT Data in setup time 250 - 100 - 50 - ns

tCLDX tHD:DAT Data in hold time 0 - 0 - 0 - ns

tCLQX (5) tDH Data out hold time 100 - 100 - 100 - ns

tCLQV (6) tAA Clock low to next data valid (access time) - 4500 - 900 - 450 ns

tCHDL tSU:STA Start condition setup time 4700 - 600 - 250 - ns

tDLCL tHD:STA Start condition hold time 4000 - 600 - 250 - ns

tCHDH tSU:STO Stop condition setup time 4000 - 600 - 250 - ns

Time between stop condition and next start

tDHDL tBUF 4700 - 1300 - 500 - ns
condition

tWLDL(1)(7) tSU:WC WC setup time (before the Start condition) 0 - 0 - 0 - µs

tDHWH (1)(8) tHD:WC WC hold time (after the Stop condition) 1 - 1 - 1 - µs

tW tWR Write time - 5 - 5 - 5 ms

Pulse width ignored (input filter on SCL and

tNS - - 50 - 50 - 50 ns
SDA) - single glitch

tWU(1)(9) - Wake-up time - 5 - 5 - 5 μs

1. Evaluated by characterization - Not tested in production.

2. With CL = 10 pF.
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification
that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz
4. There are no minimum or maximum values for the input signal rise and fall times. However, it is recommended by the I²C
specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when fC < 1 MHz.
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of
SDA.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming
that Rbus × Cbus time constant is within the values specified in Figure 21 and Figure 22.
7. WC = 0 setup time condition to enable the execution of a write command.
8. WC = 0 hold time condition to enable the execution of a write command.
9. Wake-up time: Delay between the VCC(min) stable and the first accepted command.

DS12687 - Rev 5 page 31/48

 M24256E-F
DC and AC parameters

Figure 21. Rbus value versus bus parasitic capacitance (Cbus) for an I2Cbus (fC = 400 kHz)

100 VCC
The Rbus x Cbus time
constant must be below
Bus line Pull up resistor (kΩ)

the 400 ns time constant

line displayed on the left Rbus

Rb
10 us
xC I²C bus SCL
bu
M24xxx
s =4 controller
Here Rbus x Cbus = 120 ns
00 SDA
4
ns
Cbus

DT37916V5
10 30 100 1000

Bus line capacitor (pF)

Figure 22. Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus (fC = 1 MHz)

100
VCC
The Rbus x Cbus time
Bus line pull-up resistor (kΩ)

constant must be below

the 150 ns time Rbus
constant line displayed
Rbu
10 s xC
bus on the left
= 15
0 ns I²C bus SCL
M24xxx
controller
4
Here Rbus x Cbus = 120 ns SDA

Cbus

DT19745V8
1
10 30 100

Bus line capacitor (pF)

DS12687 - Rev 5 page 32/48

 M24256E-F
DC and AC parameters

Figure 23. AC waveforms

Start Stop Start

condition condition condition

tXL1XL2 tCHCL
tXH1XH2 tCLCH

SCL
tDLCL

tXL1XL2

SDA In

SDA
tCHDL tXH1XH2 Input tCLDX SDA tDXCH tCHDH tDHDL
Change
WC

tWLDL tDHWH

Stop
Start
condition
condition

SCL

SDA In
tW
tCHDH tCHDL
Write cycle

tCHCL

SCL
tCLQV tCLQX tQL1QL2

DT00795iV1
SDA Out Data valid Data valid

DS12687 - Rev 5 page 33/48

 M24256E-F
Package information

10 Package information

To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product
status are available at: www.st.com. ECOPACK is an ST trademark.
For die information concerning the M24256E-F delivered in unsawn wafer, contact your nearest Sales office.

10.1 SO8N package information

This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mil body width package.

Figure 24. SO8N - Outline

h x 45˚

A2 A
c
b ccc
e

0.25 mm
D SEATING GAUGE PLANE
PLANE
C k
8

O7_SO8_ME_V2
E1 E
1 L
A1
L1

1. Drawing is not to scale.

DS12687 - Rev 5 page 34/48

 M24256E-F
Package information

Table 16. SO8N - Mechanical data

millimeters inches (1)

Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 1.750 - - 0.0689
A1 0.100 - 0.250 0.0039 - 0.0098
A2 1.250 - - 0.0492 - -
b 0.280 - 0.480 0.0110 - 0.0189
c 0.170 - 0.230 0.0067 - 0.0091

D(2) 4.800 4.900 5.000 0.1890 0.1929 0.1969

E 5.800 6.000 6.200 0.2283 0.2362 0.2441

E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575

e - 1.270 - - 0.0500 -
h 0.250 - 0.500 0.0098 - 0.0197
k 0° - 8° 0° - 8°
L 0.400 - 1.270 0.0157 - 0.0500
L1 - 1.040 - - 0.0409 -
ccc - - 0.100 - - 0.0039

1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 mm per side
3. Dimension E1 does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per
side.

Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the
outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interleads flash, but
including any mismatch between the top and bottom of the plastic body. The measurement side for mold flash,
protusions, or gate burrs is the bottom side.

Figure 25. SO8N - Footprint example

0.6 (x8)
3.9
6.7

O7_SO8N_FP_V2

1.27

1. Dimensions are expressed in millimeters.

DS12687 - Rev 5 page 35/48

 M24256E-F
Package information

10.2 TSSOP8 package information

This TSSOP is an 8-lead, 3 x 6.4 mm, 0.65 mm pitch, thin shrink small outline package.

Figure 26. TSSOP8 – Outline

D
8 5

Seating
plane
C
k
E1 E
A1 L
Pin 1 identification
L1

1 4

DT_6P_A_TSSOP8_ME_V4
D E1

A2 A
c
A1
b
aaa C e

1. Drawing is not to scale.

Table 17. TSSOP8 - Mechanical data

millimeters inches (1)

Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079

D(2) 2.900 3.000 3.100 0.1142 0.1181 0.1220

e - 0.650 - - 0.0256 -
E 6.200 6.400 6.600 0.2441 0.2520 0.2598

E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -
k 0° - 8° 0° - 8°
aaa - - 0.100 - - 0.0039

1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 mm per side.
3. Dimension E1 does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per
side.

DS12687 - Rev 5 page 36/48

 M24256E-F
Package information

Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the
outermost extremes of the plastic body exclusive of the mold flash, tie bar burrs, gate burrs, and interleads flash,
but including any mismatch between the top and bottom of the plastic body. The measurement side for the mold
flash, protrusions, or gate burrs is the bottom side.

Figure 27. TSSOP8 – Footprint example

1.55

0.40

0.65

2.35

DT_6P_TSSOP8_FP_V2
5.80
7.35

1. Dimensions are expressed in millimeters.

DS12687 - Rev 5 page 37/48

 M24256E-F
Package information

10.3 UFDFPN8 (DFN8) package information

This UFDFPN is an 8-lead, 2 x 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package.

Figure 28. UFDFPN8 - Outline

D A B
N
A
ccc C
A1
Pin #1 C
ID marking
E eee C
Seating plane
Side view

1 2 2x aaa C
2x aaa C

Top view

D2 Datum A
e b
1 2
L1
L3
L L3

Pin #1
ID marking E2
e/2 L1
e Terminal tip
K

ZWb_UFDFN8_ME_V2
L
Detail “A”
Even terminal
ND-1 x e
See Detail “A”
Bottom view

1. The maximum package warpage is 0.05 mm.

2. Exposed copper is not systematic and can appear partially or totally according to the cross section.
3. Drawing is not to scale.
4. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating
(not connected) in the end application.

DS12687 - Rev 5 page 38/48

 M24256E-F
Package information

Table 18. UFDFPN8 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.450 0.550 0.600 0.0177 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020

b(2) 0.200 0.250 0.300 0.0079 0.0098 0.0118

D 1.900 2.000 2.100 0.0748 0.0787 0.0827

D2 1.200 - 1.600 0.0472 - 0.0630
E 2.900 3.000 3.100 0.1142 0.1181 0.1220
E2 1.200 - 1.600 0.0472 - 0.0630
e - 0.500 - - 0.0197 -
K 0.300 - - 0.0118 - -
L 0.300 - 0.500 0.0118 - 0.0197
L1 - - 0.150 - - 0.0059
L3 0.300 - - 0.0118 - -
aaa - - 0.150 - - 0.0059
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020

eee(3) - - 0.080 - - 0.0031

1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension b applies to the plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip.
3. Applied for exposed die paddle and terminals. Exclude embedding part of the exposed die paddle from measuring.

Figure 29. UFDFPN8 - Footprint example

1.600
0.500 0.300

0.600 ZWb_UFDFN8_FP_V2

1.600

1.400

1. Dimensions are expressed in millimeters.

DS12687 - Rev 5 page 39/48

 M24256E-F
Package information

10.4 UFDFPN5 (DFN5) package information

UFDFPN5 is a 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultrathin fine-pitch dual flat package.

Figure 30. UFDFPN5 - Outline

D k L

Pin 1
Pin 1
b
X
E E1

Y e

D1 L1

Top view Bottom view

(marking side) (pads side)

A0UK_UFDFN5_ME_V4
A

A1

Side view

1. The maximum package warpage is 0.05 mm.

2. Exposed copper is not systematic and can appear partially or totally according to the cross section.
3. Drawing is not to scale.
4. On the bottom side, pin 1 is identified by the specific pad shape and, on the top side, pin 1 is defined from the
orientation of the marking. When reading the marking, pin 1 is below the upper left package corner.

Table 19. UFDFPN5 - Mechanical data

millimeters inches
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 - 0.050 0.0000 - 0.0020

b(1) 0.175 0.200 0.225 0.0069 0.0079 0.0089

D 1.600 1.700 1.800 0.0630 0.0669 0.0709

D1 1.400 1.500 1.600 0.0551 0.0591 0.0630
E 1.300 1.400 1.500 0.0512 0.0551 0.0591
E1 0.175 0.200 0.225 0.0069 0.0079 0.0089
X - 0.200 - - 0.0079 -
Y - 0.200 - - 0.0079 -
e - 0.400 - - 0.0157 -
L 0.500 0.550 0.600 0.0197 0.0217 0.0236
L1 - 0.100 - - 0.0039 -
k - 0.400 - - 0.0157 -

1. Dimension b applies to the plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip.

DS12687 - Rev 5 page 40/48

 M24256E-F
Package information

Figure 31. UFDFPN5 - Footprint example

Pin 1 0.400 0.600

0.200
0.200
0.200

A0UK_UFDFN5_FP_V1
0.200 0.400

1.600

1. Dimensions are expressed in millimeters.

DS12687 - Rev 5 page 41/48

 M24256E-F
Ordering information

11 Ordering information

Table 20. Ordering information scheme

Example: M24 256E - F MH 6 T 1

Device type

M24 = I2C serial access EEPROM

Device function
256E = 256 Kbit (32 K x 8 bit)
Operating voltage
F = VCC = 1.6 V to 5.5 V

Package (1)
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (DFN8)
MH = UFDFPN5 (DFN5)
Device grade
6 = Industrial device tested with standard test flow over -40 to 85 °C
Option
T = Tape and reel packing
Blank = Tube packing

Plating technology and device address (2)

P or G: ECOPACK2 and device address 000 unlocked
0 to 7: ECOPACK2 and preprogrammed locked device address

1. ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimony oxide flame retardants).
2. See Table 4.

Note: For a list of available options, such as memory and package types, or for further information on any aspect of
this device, contact your nearest Sales office.
Note: Parts marked as “ES” or “E” are not yet qualified and therefore not approved for use in production. ST is not
responsible for any consequences resulting from such use. In no event will ST be liable for the customer using
any of these engineering samples in production. ST’s Quality department must be contacted prior to any
decision to use these engineering samples to run a qualification activity.

DS12687 - Rev 5 page 42/48

 M24256E-F

Revision history
Table 21. Document revision history

Date Revision Changes

01-Mar-2022 1 Initial release

31-Aug-2022 2 Added description in pdf properties.
Updated:
• Title of document
07-Feb-2023 3 • Section Features, Section 1: Description, Section 2.2: Serial data
(SDA), Configurable device address register (CDA), Write operations
on configurable device address register, Section 7: Initial delivery state
• Table 20. Ordering information scheme
Unsawn wafer added.
Updated:
• Section Features
• Section 1: Description
03-Oct-2024 4 • Table 4. Preprogrammed device address
• Section 4.1: Configurable device address register (CDA)
• Section 6.6.2: Read operation on identification page
• Section 6.6.3: Read lock status on identification page
• Section 6.5: Read operations on memory array
• Table 20. Ordering information scheme
Updated:
• Section 4.1: Configurable device address register (CDA)
• Figure 6. Write mode sequence without write protection (data write
enabled)
• Section 6.1.2: Page write
25-Feb-2025 5
• Section 6.6.2: Read operation on identification page
• Section 6.6.3: Read lock status on identification page
• Section 7: Initial delivery state
• Section 8: Maximum ratings
• Table 15. AC characteristics

DS12687 - Rev 5 page 43/48

 M24256E-F
Contents

Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Write control (WC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.5 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.5.1 Operating supply voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.5.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.5.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.5.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.1 Configurable device address register (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.5 Device addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
6.1 Write operations on memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1.2 Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Write operations on register and identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2.1 Write operation on CDA register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2.2 Write operation on identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2.3 Lock operation on identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Minimizing write delays by polling on ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read operations on memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5.1 Random address read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5.2 Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DS12687 - Rev 5 page 44/48

 M24256E-F
Contents

6.5.3 Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.6 Read operations on register and identification page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6.1 Read operation on CDA address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6.2 Read operation on identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.6.3 Read lock status on identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
10.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.2 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.3 UFDFPN8 (DFN8) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.4 UFDFPN5 (DFN5) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

DS12687 - Rev 5 page 45/48

 M24256E-F
List of tables

List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Configurable device address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Configurable device address register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Preprogrammed device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. First byte address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Second byte address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Input parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 16. SO8N - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. TSSOP8 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 18. UFDFPN8 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. UFDFPN5 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

DS12687 - Rev 5 page 46/48

 M24256E-F
List of figures

List of figures
Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. 5-pin package connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3. 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. I²C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Write mode sequence without write protection (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Write mode sequence with write protection (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Write CDA register (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Write CDA register (data write inhibited by software or hardware) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Write identification page (page unlocked) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Write identification page (page locked or hard protected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Lock operation on identification page (unlocked or data write enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Lock operation on identification page (already locked or data write inhibited by hardware) . . . . . . . . . . . . . . . 18
Figure 14. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Random read on configuration device address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. Random read identification page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18. Read lock status (identification page unlocked) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. Read lock status (identification page locked) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 21. Rbus value versus bus parasitic capacitance (Cbus) for an I2Cbus (fC = 400 kHz) . . . . . . . . . . . . . . . . . . . . . . 32
Figure 22. Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus (fC = 1 MHz). . . . . . . . . . . . . . . . . . . . . . . 32
Figure 23. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 24. SO8N - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 25. SO8N - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 26. TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27. TSSOP8 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28. UFDFPN8 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 29. UFDFPN8 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 30. UFDFPN5 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 31. UFDFPN5 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DS12687 - Rev 5 page 47/48

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IMPORTANT NOTICE – READ CAREFULLY

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