ST24/25C02, ST24C02R

ST24/25W02

SERIAL 2K (256 x 8) EEPROM

NOT FOR NEW DESIGN

1 MILLION ERASE/WRITE CYCLES with

40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x02 versions
– 2.5V to 5.5V for ST25x02 versions
– 1.8V to 5.5V for ST24C02R version only
HARDWARE WRITE CONTROL VERSIONS: 8 8
ST24W02 and ST25W02
TWO WIRE SERIAL INTERFACE, FULLY I2C 1 1
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4 PSDIP8 (B) SO8 (M)
BYTES) 0.25mm Frame 150mil Width
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE Figure 1. Logic Diagram
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH-UP
PERFORMANCES
ST24C/W02 are replaced by the M24C02
ST25C/W02 are replaced by the M24C02-W
ST24C02R is replaced by the M24C02-R
VCC
DESCRIPTION
This specification covers a range of 2K bits I2C bus
EEPROM products, t he ST24/25C02, the 3
ST24C02R and ST24/25W02. In the text, products E0-E2 SDA
are referred to as ST24/25x02, where "x" is: "C" for
Standard version and "W" for hardware Write Con- ST24x02
trol version. SCL ST25x02
ST24C02R
MODE/WC*
Table 1. Signal Names
E0-E2 Chip Enable Inputs

SDA Serial Data Address Input/Output VSS

AI00788D
SCL Serial Clock

Multibyte/Page Write Mode

MODE
(C version)

WC Write Control (W version)

VCC Supply Voltage

VSS Ground
Note: WC signal is only available for ST24/25W02 products.

November 1997 1/16

This is information on a product still in production but not recommended for new design
ST24/25C02, ST24C02R, ST24/25W02

Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections

ST24x02 ST24x02
ST25x02 ST25x02
ST24C02R ST24C02R

E0 1 8 VCC E0 1 8 VCC
E1 2 7 MODE/WC E1 2 7 MODE/WC
E2 3 6 SCL E2 3 6 SCL
VSS 4 5 SDA VSS 4 5 SDA
AI00789D AI00790E

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit
TA Ambient Operating Temperature –40 to 125 °C
TSTG Storage Temperature –65 to 150 °C
TLEAD Lead Temperature, Soldering (SO8 package) 40 sec 215
°C
(PSDIP8 package) 10 sec 260
VIO Input or Output Voltages –0.6 to 6.5 V
VCC Supply Voltage –0.3 to 6.5 V
(2)
Electrostatic Discharge Voltage (Human Body model) 4000 V
VESD
(3)
Electrostatic Discharge Voltage (Machine model) 500 V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

DESCRIPTION (cont’d) tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
The ST24/25x02 are 2K bit electrically erasable code (1010) corresponding to the I2C bus defini-
programmable memories (EEPROM), organized tion. This is used together with 3 chip enable inputs
as 256 x 8 bits. They are manufactured in SGS- (E2, E1, E0) so that up to 8 x 2K devices may be
THOMSON’s Hi-Endurance Advanced CMOS attached to the I2C bus and selected individually.
technology which guarantees an endurance of one The memories behave as a slave device in the I2C
million erase/write cycles with a data retention of protocol with all memory operations synchronized
40 years. The memories operate with a power by the serial clock. Read and write operations are
supply value as low as 1.8V for the ST24C02R only. initiated by a START condition generated by the
bus master. The START condition is followed by a
Both Plastic Dual-in-Line and Plastic Small Outline
stream of 7 bits (identification code 1010), plus one
packages are available.
read/write bit and terminated by an acknowledge
The memories are compatible with the I 2C stand- bit.
ard, two wire serial interface which uses a bi-direc-

2/16
 ST24/25C02, ST24C02R, ST24/25W02

Table 3. Device Select Code

Device Code Chip Enable RW
Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 E2 E1 E0 RW
Note: The MSB b7 is sent first.

Table 4. Operating Modes (1)

Mode RW bit MODE Bytes Initial Sequence
Current Address Read ’1’ X 1 START, Device Select, RW = ’1’
’0’ START, Device Select, RW = ’0’, Address,
Random Address Read X 1
’1’ reSTART, Device Select, RW = ’1’
Sequential Read ’1’ X 1 to 256 Similar to Current or Random Mode
Byte Write ’0’ X 1 START, Device Select, RW = ’0’
(2)
Multibyte Write ’0’ VIH 4 START, Device Select, RW = ’0’
Page Write ’0’ VIL 8 START, Device Select, RW = ’0’
Notes: 1. X = VIH or VIL
2. Multibyte Write not available in ST24/25W02 versions.

When writing data to the memory it responds to the Serial Data (SDA). The SDA pin is bi-directional
8 bits received by asserting an acknowledge bit and is used to transfer data in or out of the memory.
during the 9th bit time. When data is read by the It is an open drain output that may be wire-OR’ed
bus master, it acknowledges the receipt of the data with other open drain or open collector signals on
bytes in the same way. Data transfers are termi- the bus. A resistor must be connected from the SDA
nated with a STOP condition. bus line to VCC to act as pull up (see Figure 3).
Power On Reset: VCC lock out write protect. In Chip Enable (E2 - E0). These chip enable inputs
order to prevent data corruption and inadvertent are used to set the 3 least significant bits (b3, b2,
write operations during power up, a Power On b1) of the 7 bit device select code. These inputs
Reset (POR) circuit is implemented. Until the VCC may be driven dynamically or tied to VCC or VSS to
voltage has reached the POR threshold value, the establish the device select code.
internal reset is active, all operations are disabled Mode (MODE). The MODE input is available on pin
and the device will not respond to any command. 7 (see also WC feature) and may be driven dynami-
In the same way, when VCC drops down from the cally. It must be at VIL or VIH for the Byte Write
operating voltage to below the POR threshold mode, VIH for Multibyte Write mode or VIL for Page
value, all operations are disabled and the device Write mode. When unconnected, the MODE input
will not respond to any command. A stable VCC is internally read as a VIH (Multibyte Write mode).
must be applied before applying any logic signal. Write Control (WC). An hardware Write Control
feature (WC) is offered only for ST24W02 and
ST25W02 versions on pin 7. This feature is usefull
SIGNAL DESCRIPTIONS to protect the contents of the memory from any
Serial Clock (SCL). The SCL input pin is used to erroneous erase/write cycle. The Write Control sig-
synchronize all data in and out of the memory. A nal is used to enable (WC = VIH) or disable (WC =
resistor can be connected from the SCL line to VCC VIL) the internal write protection. When uncon-
to act as a pull up (see Figure 3). nected, the WC input is internally read as VIL and
the memory area is not write protected.

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ST24/25C02, ST24C02R, ST24/25W02

SIGNAL DESCRIPTIONS (cont’d) Stop Condition. STOP is identified by a low to high

transition of the SDA line while the clock SCL is
The devices with this Write Control feature no stable in the high state. A STOP condition termi-
longer support the Multibyte Write mode of opera- nates communication between the ST24/25x02
tion, however all other write modes are fully sup- and the bus master. A STOP condition at the end
ported. of a Read command, after and only after a No
Refer to the AN404 Application Note for more de- Acknowledge, forces the standby state. A STOP
tailed information about Write Control feature. condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
DEVICE OPERATION is used to indicate a successfull data transfer. The
I2C Bus Background bus transmitter, either master or slave, will release
The ST24/25x02 support the I2C protocol. This the SDA bus after sending 8 bits of data. During the
protocol defines any device that sends data onto 9th clock pulse period the receiver pulls the SDA
the bus as a transmitter and any device that reads bus low to acknowledge the receipt of the 8 bits of
the data as a receiver. The device that controls the data.
data transfer is known as the master and the other Data Input. During data input the ST24/25x02
as the slave. The master will always initiate a data sample the SDA bus signal on the rising edge of
transfer and will provide the serial clock for syn- the clock SCL. Note that for correct device opera-
chronisation. The ST24/25x02 are always slave tion the SDA signal must be stable during the clock
devices in all communications. low to high transition and the data must change
Start Condition. START is identified by a high to ONLY when the SCL line is low.
low transition of the SDA line while the clock SCL Memory Addressing. To start communication be-
is stable in the high state. A START condition must tween the bus master and the slave ST24/25x02,
precede any command for data transfer. Except the master must initiate a START condition. Follow-
during a programming cycle, the ST24/25x02 con- ing this, the master sends onto the SDA bus line 8
tinuously monitor the SDA and SCL signals for a bits (MSB first) corresponding to the device select
START condition and will not respond unless one code (7 bits) and a READ or WRITE bit.
is given.

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

20

VCC

16

RL RL
12
RL max (kΩ)

SDA

MASTER CBUS
SCL
8

CBUS

4
VCC = 5V

0
100 200 300 400

CBUS (pF) AI01100

4/16
 ST24/25C02, ST24C02R, ST24/25W02

Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )

Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance (SDA) 8 pF
CIN Input Capacitance (other pins) 6 pF
ZWCL WC Input Impedance (ST24/25W02) VIN ≤ 0.3 VCC 5 20 kΩ
ZWCH WC Input Impedance (ST24/25W02) VIN ≥ 0.7 VCC 500 kΩ

Low-pass filter input time constant

tLP 100 ns
(SDA and SCL)
Note: 1. Sampled only, not 100% tested.

Table 6. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2 µA
0V ≤ VOUT ≤ VCC
ILO Output Leakage Current ±2 µA
SDA in Hi-Z
VCC = 5V, fC = 100kHz
Supply Current (ST24 series) 2 mA
ICC (Rise/Fall time < 10ns)
Supply Current (ST25 series) VCC = 2.5V, fC = 100kHz 1 mA
VIN = VSS or VCC,
100 µA
Supply Current (Standby) VCC = 5V
ICC1
(ST24 series)
VIN = VSS or VCC,
300 µA
VCC = 5V, fC = 100kHz
VIN = VSS or VCC,
5 µA
Supply Current (Standby) VCC = 2.5V
ICC2
(ST25 series)
VIN = VSS or VCC,
50 µA
VCC = 2.5V, fC = 100kHz
VIN = VSS or VCC,
20 µA
Supply Current (Standby) VCC = 3.6V
ICC3
(ST24C02R)
VIN = VSS or VCC,
60 µA
VCC = 3.6V, fC = 100kHz
VIN = VSS or VCC,
10 µA
Supply Current (Standby) VCC = 1.8V
ICC4
(ST24C02R)
VIN = VSS or VCC,
20 µA
VCC = 1.8V, fC = 100kHz
VIL Input Low Voltage (SCL, SDA) –0.3 0.3 VCC V
VIH Input High Voltage (SCL, SDA) 0.7 VCC VCC + 1 V
Input Low Voltage
VIL –0.3 0.5 V
(E0-E2, MODE, WC)
Input High Voltage
VIH VCC – 0.5 VCC + 1 V
(E0-E2, MODE, WC)
Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V
VOL Output Low Voltage (ST25 series) IOL = 2.1mA, VCC = 2.5V 0.4 V
Output Low Voltage
IOL = 1mA, VCC = 1.8V 0.3 V
(ST24C02R)

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ST24/25C02, ST24C02R, ST24/25W02

Table 7. AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol Alt Parameter Min Max Unit
tCH1CH2 tR Clock Rise Time 1 µs
tCL1CL2 tF Clock Fall Time 300 ns
tDH1DH2 tR Input Rise Time 1 µs
tDL1DL1 tF Input Fall Time 300 ns
(1)
tCHDX tSU:STA Clock High to Input Transition 4.7 µs
tCHCL tHIGH Clock Pulse Width High 4 µs
tDLCL tHD:STA Input Low to Clock Low (START) 4 µs
tCLDX tHD:DAT Clock Low to Input Transition 0 µs
tCLCH tLOW Clock Pulse Width Low 4.7 µs
tDXCX tSU:DAT Input Transition to Clock Transition 250 ns

tCHDH tSU:STO Clock High to Input High (STOP) 4.7 µs

tDHDL tBUF Input High to Input Low (Bus Free) 4.7 µs
(2)
tCLQV tAA Clock Low to Next Data Out Valid 0.3 3.5 µs
tCLQX tDH Data Out Hold Time 300 ns
fC fSCL Clock Frequency 100 kHz
(3)
tW tWR Write Time 10 ms
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.

AC MEASUREMENT CONDITIONS DEVICE OPERATION (cont’d)

Input Rise and Fall Times ≤ 50ns

The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
Input Pulse Voltages 0.2VCC to 0.8VCC I2C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 3 bits identify the
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
2K memories can be connected on the same bus
giving a memory capacity total of 16K bits. After a
Figure 4. AC Testing Input Output Waveforms START condition any memory on the bus will iden-
tify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.
0.8VCC
0.7VCC The 8th bit sent is the read or write bit (RW), this
bit is set to ’1’ for read and ’0’ for write operations.
0.3VCC
0.2VCC If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
AI00825
during the 9th bit time.

6/16
 ST24/25C02, ST24C02R, ST24/25W02

Figure 5. AC Waveforms

tCHCL tCLCH

SCL

tDLCL tDXCX tCHDH

SDA IN

tCHDX tCLDX tDHDL

START SDA SDA STOP &

CONDITION INPUT CHANGE BUS FREE

SCL

tCLQV tCLQX

SDA OUT DATA VALID

DATA OUTPUT

tDHDL

SCL

tW

SDA IN

tCHDH tCHDX

STOP WRITE CYCLE START

CONDITION CONDITION

AI00795

7/16
ST24/25C02, ST24C02R, ST24/25W02

Figure 6. I2C Bus Protocol

SCL

SDA

START SDA SDA STOP

CONDITION INPUT CHANGE CONDITION

SCL 1 2 3 7 8 9

SDA MSB ACK

START
CONDITION

SCL 1 2 3 7 8 9

SDA MSB ACK

STOP
CONDITION

AI00792

Write Operations For the ST24/25W02 versions, any write command

with WC = 1 will not modify the memory content.
The Multibyte Write mode (only available on the
ST24/25C02 and ST24C02R versions) is selected Byte Write. In the Byte Write mode the master
when the MODE pin is at VIH and the Page Write sends one data byte, which is acknowledged by the
mode when MODE pin is at VIL. The MODE pin may memory. The master then terminates the transfer
be driven dynamically with CMOS input levels. by generating a STOP condition. The Write mode
is independant of the state of the MODE pin which
Following a START condition the master sends a could be left floating if only this mode was to be
device select code with the RW bit reset to ’0’. The used. However it is not a recommended operating
memory acknowledges this and waits for a byte mode, as this pin has to be connected to either VIH
address. The byte address of 8 bits provides ac- or VIL, to minimize the stand-by current.
cess to 256 bytes of the memory. After receipt of
the byte address the device again responds with
an acknowledge.

8/16
 ST24/25C02, ST24C02R, ST24/25W02

Multibyte Write. For the Multibyte Write mode, the Page Write. For the Page Write mode, the MODE
MODE pin must be at VIH. The Multibyte Write pin must be at VIL. The Page Write mode allows up
mode can be started from any address in the to 8 bytes to be written in a single write cycle,
memory. The master sends from one up to 4 bytes provided that they are all located in the same ’row’
of data, which are each acknowledged by the mem- in the memory: that is the 5 most significant mem-
ory. The transfer is terminated by the master gen- ory address bits (A7-A3) are the same. The master
erating a STOP condition. The duration of the write sends from one up to 8 bytes of data, which are
cycle is tW = 10ms maximum except when bytes each acknowledged by the memory. After each
are accessed on 2 rows (that is have different byte is transfered, the internal byte address counter
values for the 6 most significant address bits A7- (3 least significant bits only) is incremented. The
A2), the programming time is then doubled to a transfer is terminated by the master generating a
maximum of 20ms. Writing more than 4 bytes in the STOP condition. Care must be taken to avoid ad-
Multibyte Write mode may modify data bytes in an dress counter ’roll-over’ which could result in data
adjacent row (one row is 8 bytes long). However, being overwritten. Note that, for any write mode,
the Multibyte Write can properly write up to 8 the generation by the master of the STOP condition
consecutive bytes only if the first address of these starts the internal memory program cycle. All inputs
8 bytes is the first address of the row, the 7 following are disabled until the completion of this cycle and
bytes being written in the 7 following bytes of this the memory will not respond to any request.
same row.

Figure 7. Write Cycle Polling using ACK

WRITE Cycle
in Progress

START Condition

DEVICE SELECT
with RW = 0

NO ACK
Returned

First byte of instruction YES

with RW = 0 already
decoded by ST24xxx

Next
NO Operation is YES
Addressing the
Memory
Send
Byte Address
ReSTART

STOP

Proceed Proceed
WRITE Operation Random Address
READ Operation

AI01099B

9/16
ST24/25C02, ST24C02R, ST24/25W02

Figure 8. Write Modes Sequence (ST24/25C02 and ST24C02R)

ACK ACK ACK

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

STOP
R/W

ACK ACK ACK

MULTIBYTE
AND DEV SEL BYTE ADDR DATA IN 1 DATA IN 2
PAGE WRITE
START

R/W

ACK ACK

DATA IN N
STOP

AI00793

Minimizing System Delays by Polling On ACK. Read Operations

During the internal write cycle, the memory discon- Read operations are independent of the state of the
nects itself from the bus in order to copy the data MODE pin. On delivery, the memory content is set
from the internal latches to the memory cells. The at all "1’s" (or FFh).
maximum value of the write time (tW) is given in the
AC Characteristics table, since the typical time is Current Address Read. The memory has an inter-
shorter, the time seen by the system may be re- nal byte address counter. Each time a byte is read,
duced by an ACK polling sequence issued by the this counter is incremented. For the Current Ad-
master. The sequence is as follows: dress Read mode, following a START condition,
the master sends a memory address with the RW
– Initial condition: a Write is in progress (see Fig- bit set to ’1’. The memory acknowledges this and
ure 7). outputs the byte addressed by the internal byte
– Step 1: the master issues a START condition address counter. This counter is then incremented.
followed by a device select byte (1st byte of The master does NOT acknowledge the byte out-
the new instruction). put, but terminates the transfer with a STOP con-
– Step 2: if the memory is busy with the internal dition.
write cycle, no ACK will be returned and the Random Address Read. A dummy write is per-
master goes back to Step 1. If the memory formed to load the address into the address
has terminated the internal write cycle, it will counter, see Figure 10. This is followed by another
respond with an ACK, indicating that the mem- START condition from the master and the byte
ory is ready to receive the second part of the address is repeated with the RW bit set to ’1’. The
next instruction (the first byte of this instruc- memory acknowledges this and outputs the byte
tion was already sent during Step 1). addressed. The master have to NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.

10/16
 ST24/25C02, ST24C02R, ST24/25W02

Figure 9. Write Modes Sequence with Write Control = 1 (ST24/25W02)

WC

ACK ACK ACK

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

STOP
R/W

WC

ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

START

R/W

WC (cont'd)

ACK ACK

PAGE WRITE DATA IN N

(cont'd)
STOP

AI01101B

Sequential Read. This mode can be initiated with ically incremented after each byte output. After a
either a Current Address Read or a Random Ad- count of the last memory address, the address
dress Read. However, in this case the master counter will ’roll- over’ and the memory will continue
DOES acknowledge the data byte output and the to output data.
memory continues to output the next byte in se- Acknowledge in Read Mode. In all read modes
quence. To terminate the stream of bytes, the the ST24/25x02 wait for an acknowledge during the
master must NOT acknowledge the last byte out- 9th bit time. If the master does not pull the SDA line
put, but MUST generate a STOP condition. The low during this time, the ST24/25x02 terminate the
output data is from consecutive byte addresses, data transfer and switches to a standby state.
with the internal byte address counter automat-

11/16
ST24/25C02, ST24C02R, ST24/25W02

Figure 10. Read Modes Sequence

ACK NO ACK
CURRENT
ADDRESS DEV SEL DATA OUT
READ START

STOP
R/W

ACK ACK ACK NO ACK

RANDOM
ADDRESS DEV SEL * BYTE ADDR DEV SEL * DATA OUT
READ
START

START

STOP
R/W R/W

ACK ACK ACK NO ACK

SEQUENTIAL
CURRENT DEV SEL DATA OUT 1 DATA OUT N
READ
START

STOP
R/W

ACK ACK ACK ACK

SEQUENTIAL
RANDOM DEV SEL * BYTE ADDR DEV SEL * DATA OUT 1
READ
START

START

R/W R/W

ACK NO ACK

DATA OUT N
STOP

AI00794C

Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

12/16
 ST24/25C02, ST24C02R, ST24/25W02

ORDERING INFORMATION SCHEME

Example: ST24C02 M 1 TR

Operating Voltage Range

ST24C02 3V to 5.5V Standard
ST24W02 3V to 5.5V Hardware Write Control
ST25C02 2.5V to 5.5V Standard
ST25W02 2.5V to 5.5V Hardware Write Control
ST24C02R 1.8V to 5.5V Standard

Package Temperature Range Option

B PSDIP8 1 0 to 70 °C TR Tape & Reel
0.25mm Frame Packing
5* –20 to 85 °C
M SO8 150mil Width
6 –40 to 85 °C
3* –40 to 125 °C

Notes: 3 * Temperature range on special request only.

5 * Temperature range for ST24C02R only.

Parts are shipped with the memory content set at all "1’s" (FFh).
For a list of available options (Operating Voltage, Range, Package, etc...) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.

13/16
ST24/25C02, ST24C02R, ST24/25W02

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

mm inches
Symb
Typ Min Max Typ Min Max
A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209
B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065
C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390
E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394
L 3.00 3.80 0.118 0.150
N 8 8
PSDIP8

A2 A

A1 L
B e1 C
B1 eA
D eB

E1 E

1
PSDIP-a

Drawing is not to scale

14/16
 ST24/25C02, ST24C02R, ST24/25W02

SO8 - 8 lead Plastic Small Outline, 150 mils body width

mm inches
Symb
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N 8 8
CP 0.10 0.004
SO8

h x 45˚

A
C
B
e CP

E H
1

A1 α L

SO-a

Drawing is not to scale

15/16
ST24/25C02, ST24C02R, ST24/25W02

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.

© 1997 SGS-THOMSON Microelectronics - All Rights Reserved

Purchase of I2C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.

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