28C17A

16K (2K x 8) CMOS EEPROM

FEATURES PACKAGE TYPES

2 RDY/BSY
• Fast Read Access Time—150 ns RDY/BSY •1 28 Vcc

32 Vcc
31 WE
3 NC

1 NU

30 NC
NC 2 27 WE

4 A7
• CMOS Technology for Low Power Dissipation A7 3 26 NC
- 30 mA Active A6 4 25 A8 A6 5 29 A8

- 100 µA Standby

DIP/SOIC
A5 5 24 A9 A5 6 28 A9
A4 6 23 NC A4 7 27 NC
• Fast Byte Write Time—200 µs or 1 ms

PLCC
A3 7 22 OE A3 8 26 NC
A2 8 21 A10 A2 9 25 OE
• Data Retention >200 years A1 9 20 CE A1 10 24 A10

• High Endurance - Minimum 104 Erase/Write Cycles A0 10 19 I/O7

A0 11 23 CE
NC 12 22 I/O7
11 18
• Automatic Write Operation I/O0 I/O6
I/O0 13 21 I/O6
I/O1 12 17 I/O5

14
15
16
17
18
19
20
- Internal Control Timer I/O2 13 16 I/O4

I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
- Auto-Clear Before Write Operation VSS 14 15 I/O3

- On-Chip Address and Data Latches • Pin 1 indicator on PLCC on top of package
• Data Polling; Ready/Busy OE 1 28 A10
• Chip Clear Operation NC 2 27 CE
A9 3 26 I/07
• Enhanced Data Protection A8 4 25 I/06
NC 5 24 I/05
- VCC Detector WE 6 23 I/04

TSOP
- Pulse Filter Vcc 7 22 I/03

- Write Inhibit RDY/BSY 8 21 Vss

NC 9 20 I/02
• Electronic Signature for Device Identification A7 10 19 I/01
• 5-Volt-Only Operation A6 11 18 I/00
A5 12 17 A0
• Organized 2Kx8 JEDEC Standard Pinout A4 13 16 A1
A3 14 15 A2
- 28 Pin Dual-In-Line Package
- 32-Pin PLCC Package OE 22 21 A10
- 28-Pin Thin Small Outline Package (TSOP) NC
A9
23
24
20
19
CE
I/O7
8x20mm A8 25 18 I/O6
NC 26 17 I/O5
- 28-Pin Very Small Outline Package (VSOP)
VSOP
WE 27 16 I/O4
VCC 28 15 I/O3
8x13.4mm RDY/BSY 1 14 VSS
• Available for Extended Temperature Ranges: NC
A7
2
3
13
12
I/O2
I/O1
- Commercial: 0˚C to +70˚C A6 4 11 I/O0
A5 5 10 A0
- Industrial: -40˚C to +85˚C A4 6 9 A1
A3 7 8 A2

DESCRIPTION
BLOCK DIAGRAM
The Microchip Technology Inc. 28C17A is a CMOS 16K non-
I/O0 I/O7
volatile electrically Erasable PROM. The 28C17A is
accessed like a static RAM for the read or write cycles without
VSS
the need of external components. During a “byte write”, the VCC Data Protection
Circuitry
address and data are latched internally, freeing the micropro- Chip Enable/
CE
cessor address and data bus for other operations. Following Output Enable
OE Control Logic
the initiation of write cycle, the device will go to a busy state WE Input/Output
Auto Erase/Write Data
and automatically clear and write the latched data using an Rdy/ Timing Poll Buffers
internal control timer. To determine when the write cycle is Busy
Program Voltage
complete, the user has a choice of monitoring the Ready/ Generation
Busy output or using Data polling. The Ready/Busy pin is an A0
Y Y Gating
open drain output, which allows easy configuration in wired- L
Decoder
or systems. Alternatively, Data polling allows the user to read a
t
the location last written to when the write operation is com- c
h
plete. CMOS design and processing enables this part to be e X 16K bit
s Decoder Cell Matrix
used in systems where reduced power consumption and reli-
ability are required. A complete family of packages is offered A10
to provide the utmost flexibility in applications.

 1996 Microchip Technology Inc. DS11127G-page 1

This document was created with FrameMaker 4 0 4

28C17A
1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PIN FUNCTION TABLE

1.1 MAXIMUM RATINGS* Name Function

VCC and input voltages w.r.t. VSS ....... -0.6V to + 6.25V A0 - A10 Address Inputs
Voltage on OE w.r.t. VSS ..................... -0.6V to +13.5V CE Chip Enable
Voltage on A9 w.r.t. VSS ...................... -0.6V to +13.5V
OE Output Enable
Output Voltage w.r.t. VSS ................ -0.6V to VCC+0.6V
WE Write Enable
Storage temperature .......................... -65˚C to +125˚C
I/O0 - I/O7 Data Inputs/Outputs
Ambient temp. with power applied ....... -50˚C to +95˚C
*Notice: Stresses above those listed under “Maximum Ratings” RDY/Busy Ready/Busy
may cause permanent damage to the device. This is a stress rat-
VCC +5V Power Supply
ing only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of VSS Ground
this specification is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability. NC No Connect; No Internal Connec-
tion
NU Not Used; No External Connection
is Allowed

TABLE 1-2: READ/WRITE OPERATION DC CHARACTERISTICS

VCC = +5V ±10%

Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C

Parameter Status Symbol Min Max Units Conditions

Input Voltages Logic ‘1’ VIH 2.0 Vcc+1 V

Logic ‘0’ VIL -0.1 0.8 V
Input Leakage — ILI -10 10 µA VIN = -0.1V to Vcc +1
Input Capacitance — CIN — 10 pF VIN = 0V; Tamb = 25˚C;
f = 1 MHz
Output Voltages Logic ‘1’ VOH 2.4 V IOH = -400 µA
Logic ‘0’ VOL 0.45 V IOL = 2.1 mA
Output Leakage — ILO -10 10 µA VOUT = -0.1V to VCC
+0.1V
Output Capacitance — COUT — 12 pF VIN = 0V; Tamb = 25˚C;
f = 1 MHz
Power Supply Current, Active TTL input ICC — 30 mA f = 5 MHz (Note 1)
VCC = 5.5V;
Power Supply Current, Standby TTL input ICC(S)TTL — 2 mA CE = VIH (0˚C to +70˚C)
TTL input ICC(S)TTL 3 mA CE = VIH (-40˚C to +85˚C)
CMOS input ICC(S)CMOS 100 µA CE = VCC-0.3 to Vcc +1
Note 1: AC power supply current above 5MHz: 1mA/MHz.

DS11127G-page 2  1996 Microchip Technology Inc.

 28C17A
TABLE 1-3: READ OPERATION AC CHARACTERISTICS

AC Testing Waveform: VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V
Output Load: 1 TTL Load + 100 pF
Input Rise and Fall Times: 20 ns
Ambient Temperature: Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C

28C17A-15 28C17A-20 28C17A-25

Parameter Symbol Units Conditions
Min Max Min Max Min Max

Address to Output Delay tACC — 150 — 200 — 250 ns OE = CE = VIL

CE to Output Delay tCE — 150 — 200 — 250 ns OE = VIL
OE to Output Delay tOE — 70 — 80 — 100 ns CE = VIL
CE or OE High to Output tOFF 0 50 0 55 0 70 ns
Float
Output Hold from Address, tOH 0 — 0 — 0 — ns
CE or OE, whichever occurs
first.
Endurance — 1M — 1M — 1M — cycles 25°C, Vcc =
5.0V, Block
Mode (Note)
Note: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-1: READ WAVEFORMS

VIH
Address Address Valid
VIL

VIH
CE
VIL

VIH
OE
VIL t OFF(1,3)
t OH
VOH
Data High Z High Z
Valid Output
VOL
t ACC

VIH
WE
VOL

(1) tOFF is specified for OE or CE, whichever occurs first

(2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested

 1996 Microchip Technology Inc. DS11127G-page 3

28C17A
TABLE 1-4: BYTE WRITE AC CHARACTERISTICS

AC Testing Waveform: VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V
Output Load: 1 TTL Load + 100 pF
Input Rise/Fall Times: 20 ns
Ambient Temperature: Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C

Parameter Symbol Min Max Units Remarks

Address Set-Up Time tAS 10 — ns

Address Hold Time tAH 50 — ns
Data Set-Up Time tDS 50 — ns
Data Hold Time tDH 10 — ns
Write Pulse Width tWPL 100 — ns Note 1
Write Pulse High Time tWPH 50 — ns
OE Hold Time tOEH 10 — ns
OE Set-Up Time tOES 10 — ns
Data Valid Time tDV — 1000 ns Note 2
Time to Device Busy tDB 2 50 ns
Write Cycle Time (28C17A) tWC — 1 ms 0.5 ms typical
Write Cycle Time (28C17AF) tWC — 200 µs 100 µs typical
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the pos-
itive edge of CE or WE, whichever occurs first
2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH after
the positive edge of WE or CE, whichever occurs first.

FIGURE 1-2: PROGRAMMING WAVEFORMS

VIH
Address
VIL
t AS t AH
VIH
CE, WE t WPL
VIL t DH
t DV t DS
VIH
Data In
VIL
t OES
VIH
OE
VIL
t OEH

VOH
Rdy/Busy Busy Ready
VOL t DB
t WC

DS11127G-page 4  1996 Microchip Technology Inc.

 28C17A
FIGURE 1-3: DATA POLLING WAVEFORMS

VIH Last Written

Address Address Valid
Address Valid
VIL
t ACC
VIH t CE
CE
VIL
t WPH
VIH t WPL
WE
VIL
t OE
VIH
OE
VIL
t DV
VIH
Data Data In True Data Out
Valid I/O7 Out
VIL
t WC

FIGURE 1-4: CHIP CLEAR WAVEFORMS

VIH
CE
VIL

VH
OE
VIH
tS tH
tW
VIH
WE
VIL tW = 10ms
tS = tH = 1µs
VH = 12.0V ±0.5V

TABLE 1-5: SUPPLEMENTARY CONTROL

Mode CE OE WE A9 Vcc I/OI

Chip Clear VIL VH VIL X VCC

Extra Row Read VIL VIL VIH A9 = VH VCC Data Out
Extra Row Write * VIH * A9 = VH VCC Data In
Note 1: VH = 12.0V ±0.5V * Pulsed per programming waveforms.

 1996 Microchip Technology Inc. DS11127G-page 5

28C17A
2.0 DEVICE OPERATION 2.4 Write Mode
The Microchip Technology Inc. 28C17A has four basic The 28C17A has a write cycle similar to that of a Static
modes of operation—read, standby, write inhibit, and RAM. The write cycle is completely self-timed and ini-
byte write—as outlined in the following table. tiated by a low going pulse on the WE pin. On the fall-
ing edge of WE, the address information is latched. On
Operation Rdy/Busy rising edge, the data and the control pins (CE and OE)
CE OE WE I/O
Mode (1) are latched. The Ready/Busy pin goes to a logic low
level indicating that the 28C17A is in a write cycle which
Read L L H DOUT H
signals the microprocessor host that the system bus is
Standby H X X High Z H free for other activity. When Ready/Busy goes back to
a high, the 28C17A has completed writing and is ready
Write Inhibit H X X High Z H
to accept another cycle.
Write Inhibit X L X High Z H
2.5 Data Polling
Write Inhibit X X H High Z H
The 28C17A features Data polling to signal the comple-
Byte Write L H L DIN L tion of a byte write cycle. During a write cycle, an
Byte Clear Automatic Before Each “Write” attempted read of the last byte written results in the
data complement of I/O7 (I/O0 to I/O6 are indetermin-
Note 1: Open drain output. able). After completion of the write cycle, true data is
2: X = Any TTL level. available. Data polling allows a simple read/compare
operation to determine the status of the chip eliminat-
2.1 Read Mode ing the need for external hardware.
The 28C17A has two control functions, both of which 2.6 Electronic Signature for Device
must be logically satisfied in order to obtain data at the
Identification
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable An extra row of 32 bytes of EEPROM memory is avail-
(OE) is the output control and is used to gate data to able to the user for device identification. By raising A9
the output pins independent of device selection. to 12V ±0.5V and using address locations 7EO to 7FF,
Assuming that addresses are stable, address access the additional bytes can be written to or read from in the
time (tACC) equal to the delay from CE to output (tCE). same manner as the regular memory array.
Data is available at the output tOE after the falling edge
of OE, assuming that CE has been low and addresses 2.7 Chip Clear
have been stable for at least tACC-tOE.
All data may be cleared to 1's in a chip clear cycle by
2.2 Standby Mode raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.
The 28C17A is placed in the standby mode by applying
a high signal to the CE input. When in the standby
mode, the outputs are in a high impedance state, inde-
pendent of the OE input.

2.3 Data Protection

In order to ensure data integrity, especially during criti-
cal power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
First, an internal VCC detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation
when VCC is less than the VCC detect circuit trip.
Second, there is a WE filtering circuit that prevents WE
pulses of less than 10 ns duration from initiating a write
cycle.
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (VCC).

DS11127G-page 6  1996 Microchip Technology Inc.

28C17A
28C17A Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

28C17A F T – 15 I /P
Package: L = Plastic Leaded Chip Carrier (PLCC)
P = Plastic DIP (600 mil)
TS = Thin Small Outline Package (TSOP) 8x20mm
VS = Very Small Outline Package (VSOP) 8x13.4mm
Temperature Blank = 0°C to +70°C
Range: I = -40°C to +85°C

Access Time: 15 150 ns

20 200 ns
25 250 ns
Shipping: Blank Tube
T Tape and Reel “L” and “SO”

Option: Blank = twc = 1ms

F = twc = 200 µs

Device: 28C17A 2K x 8 CMOS EEPROM

 1996 Microchip Technology Inc. DS11127G-page 7

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All rights reserved.  1996, Microchip Technology Incorporated, USA. 9/96

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DS11127G-page 8  1996 Microchip Technology Inc.