UMC Confidential - Do Not Copy 40nm LOGIC/MIXED_MODE Low Power High Threshold Voltage 1.
1V MOSFET Thermal
Noise SPICE Model Document. This document is the property of UMC. Its use is authorized only for design of
products manufactured by UMC
UMC 40nm LOGIC/MIXED_MODE
Low Power High Threshold Voltage 1.1V
MOSFET SPICE Model with Thermal Noise
Enhancement Document.
Version 1.4 Phase 2
2013/12/05
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UMC Confidential - Do Not Copy 40nm LOGIC/MIXED_MODE Low Power High Threshold Voltage 1.1V MOSFET Thermal
Noise SPICE Model Document. This document is the property of UMC. Its use is authorized only for design of
products manufactured by UMC
Table of Contents
1 INTRODUCTION ................................................................... 3
1.1 General information ................................................................................................. 4
1.2 Model Usage ............................................................................................................ 4
2 SIMULATION RESULTS FOR CHANNEL THERMAL
NOISE ............................................................................................. 7
2.1 1.1V LP-HVT NMOS (n_11_lphvt) ...................................................................... 7
2.2 1.1V LP-HVT PMOS (p_11_lphvt) ....................................................................... 9
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UMC Confidential - Do Not Copy 40nm LOGIC/MIXED_MODE Low Power High Threshold Voltage 1.1V MOSFET Thermal
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1 Introduction
Table 1-1 Revision history
Version Date Author Remark
Original release of thermal noise model for
the following base-band model,
1.3_P1 2012/01/12 Annie Kuo
l40lp_hvt1p1_v131
Original release of thermal noise model for
Ryan LK the following base-band model,
1.4_P1 2013/06/24 Chen l40lp_hvt1p1_v141
1.4_P2 2013/12/05 Amer Kang 1.Update 1.2V BB Model simulation table
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1.1 General information
This document describes MOSFET model with thermal noise model enhancement for
L40 Logic/Mixed-Mode Low-Power (l40lp_hvt) process. At the current release, Spectre,
Hspice and Eldo models are supported.
This model is an enhancement of thermal noise for the following Logic/MM spice model:
G-05-LOGIC/MIXED_MODE40N-LP-SPICE-A Version 1.4 Phase2
Usually BSIM4 built-in thermal model can model the channel thermal noise reasonably
well for longer channel devices, however it is difficult to predict the channel thermal
noise for shorter channel device over different dimensions and biasing conditions.
In this thermal noise model enhancement, we use a propriety method to compensate the
excess channel thermal noise of short channel devices for BSIM4 built-in thermal noise
model. The simulated channel thermal noise is compared to the thermal noise extracted
from high frequency noise measurement for different device sizes and basing conditions,
to make sure the model scalabilities for device dimension and biasing conditions.
Except noise behavior, the models with and without thermal noise enhancement have
exact same electrical behaviors.
However, the simulation using the model with the thermal noise enhancement generally
needs more simulation time than the simulation using the original model without
THERMAL noise enhancement, since Verilog-A code is used in the thermal noise
enhancement model. It is recommended to use the model without thermal noise
enhancement for simulations other than noise analysis, and use the model with thermal
noise enhancement for noise analysis to get more accurate noise results.
Please note that the models with thermal noise enhancement need Verilog-A licenses
from the simulators.
1.2 Model Usage
1.2.1 Model Files
The following model files are included in the model packages,
HSPICE
l40lp_hvt1p1_v142.lib - 5-libs w/o TN enhancement, 5-libs with TN enhancement
l40lp_hvt1p1_v142.mdl - model parameter file w/o TN enhancement
l40lp_hvt1p1_v142_tn.mdl - model parameter file with TN enhancement
h1p1142h.va - Verilog-A code
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SPECTRE
l40lp_hvt1p1_v142.lib.scs - 5-libs w/o TN enhancement, 5-libs with TN enhancement
l40lp_hvt1p1_v142.mdl.scs - model parameter file w/o TN enhancement
l40lp_hvt1p1_v142_tn.mdl.scs - model parameter file with TN enhancement
h1p1142s.va - Verilog-A code
ELDO
l40lp_hvt1p1_v142.lib.eldo -5-libs w/o TN enhancement, 5-libs with TN enhancement
l40lp_hvt1p1_v142.mdl.eldo - model parameter file w/o TN enhancement
l40lp_hvt1p1_v142_tn.mdl.eldo - model parameter file with TN enhancement
h1p1142e.va - Verilog-A code
As below, 5 libraries without thermal noise enhancement are TT, SS, FF, SNFP, FNSP,
and 5 libraries with thermal noise enhancement are TT_TN, SS_TN, FF_TN, SNFP_TN,
FNSP_TN,
TT: Typical n-ch MOSFET and Typical p-ch MOSFET
FF: Fast n-ch MOSFET and Fast p-ch MOSFET
SS: Slow n-ch MOSFET and Slow p-ch MOSFET
FNSP: Fast n-ch MOSFET and Slow p-ch MOSFET
SNFP: Slow n-ch MOSFET and Fast p-ch MOSFET
TT_TN: Typical n-ch MOSFET and Typical p-ch MOSFET with thermal noise enhancement
FF_TN: Fast n-ch MOSFET and Fast p-ch MOSFET with thermal noise enhancement
SS_TN: Slow n-ch MOSFET and Slow p-ch MOSFET with thermal noise enhancement
FNSP_TN: Fast n-ch MOSFET and Slow p-ch MOSFET with thermal noise enhancement
SNFP_TN: Slow n-ch MOSFET and Fast p-ch MOSFET with thermal noise enhancement
Simulator Versions:
Synopsys HSPICE release 2012.06
Cadence Spectre version 10.1.1.111.isr8 32 bit
Mentor Graphics Eldo version 6.11_1.1
1.2.2 The definitions of sub-circuit model parameters
After invoking thermal noise enhancement, the compact transistor models evolve to sub-
circuit models. The input parameters for the sub-circuit model are the same as the
compact model, except the input parameter “mf” for Hspice and Eldo.
The following is the parameter list:
- nf: number of gate fingers
- w: total gate width (gate finger width * number of gate fingers)
- l: gate finger length
- as: source area per finger
- ad: drain area per finger
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- ps: source periphery per finger
- pd: drain periphery per finger
- sa: distance between OD edge to poly from one side
- sb: distance between OD edge to poly from other side
- sd: poly space for multiple finger device
- sca: integral of the first distribution function for scattered well dopant
- scb: integral of the second distribution function for scattered well dopant
- scc: integral of the third distribution function for scattered well dopant
- mf: multiple factor used for thermal noise simulator (for HSPICE and Eldo only,
not required by Spectre). Its value should be always equal to instant multiple
factor parameter “m”
1.2.3 Multiple Factor “mf” for Hspice and Eldo
Due to the fact that Verilog-A codes in Hspice and Eldo don’t support multiple factor that
is inherited from the netlist, an additional model input parameter “mf” has to be defined
in order to accurately simulate the High Frequency noise for multiple devices connected
in parallel. mf will not affect the simulation results other than thermal noise behavior. The
value of mf should be always be equal to the value of instant multiple factor parameter m.
Please refer to the following example:
If 4 devices are connected in parallel, the netlist for Hspice and Eldo should be:
x1 (d g s b) n_11_lphvt l=0.04u w=4u nf=8 m=24 mf=24
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2 Simulation Results for Channel Thermal Noise
In this section, the simulation results for channel thermal noise against measured channel
thermal noise extracted from high frequency noise figure measurement for MOSFET are
demonstrated.
Channel thermal noise extracted from measurement
Simulated channel thermal noise with thermal noise enhancement
Simulated channel thermal noise w/o thermal noise enhancement
Please note in the following figures:
lf=l is the gate finger length
wf=w/nf is the gate finger width
2.1 1.1V LP-HVT NMOS (n_11_lphvt)
NMOS Vd=0.5V wf=9e-7 lf=1.08e-7 nf=8 m=24
3.00E-21
Chennel Thermal Noise (A^2/Hz)
2.50E-21
2.00E-21
1.50E-21
1.00E-21
5.00E-22
0.00E+00
0.2 0.4 0.6 0.8 1 1.2 1.4
Vg
Figure 2-1a Vd=0.5V
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NMOS Vd=0.8V wf=9e-7 lf=1.08e-7 nf=8 m=24
3.00E-21
Chennel Thermal Noise (A^2/Hz)
2.50E-21
2.00E-21
1.50E-21
\
1.00E-21
5.00E-22
0.00E+00
0.2 0.4 0.6 0.8 1 1.2 1.4
Vg
Figure 2-1b Vd=0.8V
NMOS Vd=1.1V wf=9e-7 lf=1.08e-7 nf=8 m=24
3.50E-21
Chennel Thermal Noise (A^2/Hz)
3.00E-21
2.50E-21
2.00E-21
1.50E-21
1.00E-21
5.00E-22
0.00E+00
0.2 0.4 0.6 0.8 1 1.2 1.4
Vg
Figure 2-1c Vd=1.1V
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L40LP HVT NFET Sid(A^2/Hz)
WF/NF/M=0.9um/8/24, LF=0.036/0.072/0.108/0.324(um)
1E-19
Channel Thermal Noise(A^2/Hz)
1E-20
1E-21
1E-22
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
LF(um)
sim: Vg/Vd=0.55V/0.5V mea: Vg/Vd=0.55V/0.5V
sim: Vg/Vd=0.85V/0.8V mea: Vg/Vd=0.85V/0.8V
sim: Vg=Vd=1.1V mea: Vg=Vd=1.1V
Figure 2-1d Thermal noise fitting results
2.2 1.1V LP-HVT PMOS (p_11_lphvt)
PMOS Vd=-0.5V wf=9e-7 lf=1.08e-7 nf=8 m=24
Chennel Thermal Noise (A^2/Hz)
1.00E-21
8.00E-22
6.00E-22
4.00E-22
2.00E-22
0.00E+00
-0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4
Vg
Figure 2-2a : Vd=-0.5V
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UMC Confidential - Do Not Copy 40nm LOGIC/MIXED_MODE Low Power High Threshold Voltage 1.1V MOSFET Thermal
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PMOS Vd=-0.8V wf=9e-7 lf=1.08e-7 nf=8 m=24
1.00E-21
Chennel Thermal Noise (A^2/Hz)
8.00E-22
6.00E-22
4.00E-22 \
2.00E-22
0.00E+00
-0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4
Vg
Figure 2-2b Vd=-0.8V
PMOS Vd=-1.1V wf=9e-7 lf=1.08e-7 nf=8 m=24
1.00E-21
Chennel Thermal Noise (A^2/Hz)
8.00E-22
6.00E-22
4.00E-22
2.00E-22
0.00E+00
-0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4
Vg
Figure 2-2c Vd=-1.1V
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L40LP HVT PFET Sid(A^2/Hz)
WF/NF/M=0.9um/8/24, LF=0.036/0.072/0.108/0.324(um)
1E-19
Channel Thermal Noise(A^2/Hz)
1E-20
1E-21
1E-22
1E-23
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
LF(um)
sim: Vg/Vd=-0.55V/-0.5V mea: Vg/Vd=-0.55V/-0.5V
sim: Vg/Vd=-0.85V/-0.8V mea: Vg/Vd=-0.85V/-0.8V
sim: Vg=Vd=-1.1V mea: Vg=Vd=-1.1V
Figure 2-2d Thermal noise fitting results
< End of Document >
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