Features

• Fast Read Access Time - 70 ns

• 5-volt Only Reprogramming
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– Internal Address and Data Latches for 64 Bytes
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Fast Program Cycle Times
– Page (64 Byte) Program Time - 10 ms

•
– Chip Erase Time - 10 ms
DATA Polling for End of Program Detection
256K (32K x 8)
• Low-power Dissipation
– 50 mA Active Current 5-volt Only
– 300 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles Flash Memory
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
AT29C256
Description
The AT29C256 is a five-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 70 ns with power dissipation of just 275 mW. When the device is
deselected, the CMOS standby current is less than 300 µA. The device endurance is
such that any sector can typically be written to in excess of 10,000 times.
(continued)
Pin Configurations DIP Top View
Pin Name Function
WE 1 28 VCC
A12 2 27 A14
A0 - A14 Addresses
A7 3 26 A13
A6 4 25 A8
CE Chip Enable
A5 5 24 A9
A4 6 23 A11
OE Output Enable
A3 7 22 OE
A2 8 21 A10
WE Write Enable A1 9 20 CE
A0 10 19 I/O7
I/O0 - I/O7 Data Inputs/Outputs I/O0 11 18 I/O6
I/O1 12 17 I/O5
NC No Connect I/O2 13 16 I/O4
GND 14 15 I/O3
DC Don’t Connect

PLCC and LCC Top View

TSOP Top View
VCC
A12

A14
A13
WE
DC
A7

Type 1
4
3
2
1
32
31
30

A6 5 29 A8
A5 6 28 A9 OE 22 21 A10
A4 7 27 A11 A11 23 20 CE
A3 8 26 NC A9 24 19 I/O7
A2 9 25 OE
A8 25 18 I/O6
A1 10 24 A10
A13 26 17 I/O5
A0 11 23 CE
NC 12 22 I/O7
A14 27 16 I/O4
I/O0 13 21 I/O6 VCC 28 15 I/O3
14
15
16
17
18
19
20

WE 1 14 GND
A12 2 13 I/O2
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5

A7 3 12 I/O1
A6 4 11 I/O0
A5 5 10 A0
Note: PLCC package pins 1 and 17
A4 6 9 A1
are DON’T CONNECT. Rev. 0046N–08/99
A3 7 8 A2

This datasheet has been downloaded from http://www.digchip.com at this page

To allow for simple in-system reprogrammability, the During a reprogram cycle, the address locations and 64
AT29C256 does not require high input voltages for pro- bytes of data are internally latched, freeing the address and
gramming. Five-volt-only commands determine the opera- data bus for other operations. Following the initiation of a
tion of the device. Reading data out of the device is similar program cycle, the device will automatically erase the page
to reading from a static RAM. Reprogramming the and then program the latched data using an internal control
AT29C256 is performed on a page basis; 64 bytes of data timer. The end of a program cycle can be detected by
are loaded into the device and then simultaneously pro- DATA polling of I/O7. Once the end of a program cycle has
grammed. The contents of the entire device may be erased been detected a new access for a read, program or chip
by using a six-byte software code (although erasure before erase can begin.
programming is not needed).

Block Diagram

Device Operation
READ: The AT29C256 is accessed like a static RAM. period will end and the internal programming period will
When CE and OE are low and WE is high, the data stored start. A6 to A14 specify the page address. The page
at the memory location determined by the address pins address must be valid during each high-to-low transition of
is asserted on the outputs. The outputs are put in the WE (or CE). A0 to A5 specify the byte address within the
high impedance state whenever CE or OE is high. This page. The bytes may be loaded in any order; sequential
dual-line control gives designers flexibility in preventing bus loading is not required. Once a programming operation has
contention. been initiated, and for the duration of tWC, a read operation
BYTE LOAD: A byte load is performed by applying a low will effectively be a polling operation.
pulse on the WE or CE input with CE or WE low (respec- SOFTWARE DATA PROTECTION: A software controlled
tively) and OE high. The address is latched on the falling data protection feature is available on the AT29C256. Once
edge of CE or WE, whichever occurs last. The data is the software protection is enabled a software algorithm
latched by the first rising edge of CE or WE. Byte loads are must be issued to the device before a program may be per-
used to enter the 64 bytes of a page to be programmed or formed. The software protection feature may be enabled or
the software codes for data protection and chip erasure. disabled by the user; when shipped from Atmel, the soft-
PROGRAM: The device is reprogrammed on a page ware data protection feature is disabled. To enable the soft-
basis. If a byte of data within a page is to be changed, data ware data protection, a series of three program commands
for the entire page must be loaded into the device. Any byte to specific addresses with specific data must be performed.
that is not loaded during the programming of its page will After the software data protection is enabled the same
be indeterminate. Once the bytes of a page are loaded into three program commands must begin each program cycle
the device, they are simultaneously programmed during the in order for the programs to occur. All software program
internal programming period. After the first data byte has commands must obey the page program timing specifica-
been loaded into the device, successive bytes are entered tions. Once set, the software data protection feature
in the same manner. Each new byte to be programmed remains active unless its disable command is issued.
must have its high-to-low transition on WE (or CE) within Power transitions will not reset the software data protection
150 µs of the low-to-high transition of WE (or CE) of the feature, however the software feature will guard against
preceding byte. If a high-to-low transition is not detected inadvertent program cycles during power transitions.
within 150 µs of the last low-to-high transition, the load

2 AT29C256
 AT29C256

Once set, software data protection will remain active unless filter—pulses of less than 15 ns (typical) on the WE or CE
the disable command sequence is issued. inputs will not initiate a program cycle.
After setting SDP, any attempt to write to the device without PRODUCT IDENTIFICATION: The product identification
the three-byte command sequence will start the internal mode identifies the device and manufacturer and may be
write timers. No data will be written to the device; however, accessed by a hardware operation. For details, see Oper-
for the duration of tWC, a read operation will effectively be a ating Modes or Product Identification.
polling operation. DATA POLLING: The AT29C256 features DATA polling
After the software data protection’s three-byte command to indicate the end of a program cycle. During a program
code is given, a byte load is performed by applying a low cycle an attempted read of the last byte loaded will result in
pulse on the WE or CE input with CE or WE low (respec- the complement of the loaded data on I/O7. Once the pro-
tively) and OE high. The address is latched on the falling gram cycle has been completed, true data is valid on all
edge of CE or WE, whichever occurs last. The data is outputs and the next cycle may begin. DATA polling may
latched by the first rising edge of CE or WE. The 64 bytes begin at any time during the program cycle.
of data must be loaded into each sector by the same proce- TOGGLE BIT: In addition to DATA polling the AT29C256
dure as outlined in the program section under device provides another method for determining the end of a pro-
operation. gram or erase cycle. During a program or erase operation,
HARDWARE DATA PROTECTION: Hardware features successive attempts to read data from the device will result
protect against inadvertent programs to the AT29C256 in in I/O6 toggling between one and zero. Once the program
the following ways: (a) V CC sense—if V CC is below 3.8V cycle has completed, I/O6 will stop toggling and valid data
(typical), the program function is inhibited; (b) VCC power on will be read. Examining the toggle bit may begin at any time
delay—once V CC has reached the V CC sense level, the during a program cycle.
device will automatically time out 5 ms (typical) before pro- OPTIONAL CHIP ERASE MODE: The entire device can
gramming; (c) Program inhibit—holding any one of OE low, be erased by using a six-byte software code. Please see
CE high or WE high inhibits program cycles; and (d) Noise Software Chip Erase application note for details.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
All Input Voltages (including NC Pins) other conditions beyond those indicated in the
with Respect to Ground ...................................-0.6V to +6.25V operational sections of this specification is not
implied. Exposure to absolute maximum rating
All Output Voltages conditions for extended periods may affect
with Respect to Ground .............................-0.6V to VCC + 0.6V device reliability.

Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V

3
DC and AC Operating Range
AT29C256-70 AT29C256-90 AT29C256-12 AT29C256-15

Operating Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C
Temperature (Case) Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C
VCC Power Supply 5V ± 5% 5V± 10% 5V± 10% 5V± 10%

Operating Modes
Mode CE OE WE Ai I/O
Read VIL VIL VIH Ai DOUT
(2)
Program VIL VIH VIL Ai DIN
5V Chip Erase VIL VIH VIL Ai
Standby/Write Inhibit VIH X(1) X X High Z
Write Inhibit X X VIH
Write Inhibit X VIL X
Output Disable X VIH X High Z
High Voltage Chip Erase VIL VH(3) VIL X High Z
Product Identification
A1-A14 = VIL, A9 = VH, A0 = VIL Manufacturer Code(4)
Hardware VIL VIL VIH
A1-A14 = VIL, A9 = VH, A0 = VIH Device Code(4)
A0 = VIL Manufacturer Code(4)
Software(5)
A0 = VIH Device Code(4)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1F, Device Code: DC.
5. See details under Software Product Identification Entry/Exit.

DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC 300 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3 mA
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

4 AT29C256
 AT29C256

AC Read Characteristics
AT29C256-70 AT29C256-90 AT29C256-12 AT29C256-15
Symbol Parameter Min Max Min Max Min Max Min Max Units
tACC Address to Output Delay 70 90 120 150 ns
(1)
tCE CE to Output Delay 70 90 120 150 ns
(2)
tOE OE to Output Delay 0 40 0 40 0 50 0 70 ns
tDF(3)(4) CE or OE to Output Float 0 25 0 25 0 30 0 40 ns
Output Hold from OE, CE or Address,
tOH 0 0 0 0 ns
whichever occurred first

AC Read Waveforms(1)(2)(3)(4)

Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and Output Test Load

Measurement Level

tR, tF < 5 ns

Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 4 6 pF VIN = 0V
COUT 8 12 pF VOUT = 0V
Note: 1. This parameter is characterized and is not 100% tested.

5
AC Byte Load Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 90 ns
tDS Data Set-up Time 35 ns
tDH,tOEH Data, OE Hold Time 0 ns
tWPH Write Pulse Width High 100 ns

AC Byte Load Waveforms

WE Controlled

CE Controlled

6 AT29C256
 AT29C256

Program Cycle Characteristics

Symbol Parameter Min Max Units
tWC Write Cycle Time 10 ms
tAS Address Set-up Time 0 ns
tAH Address Hold Time 50 ns
tDS Data Set-up Time 35 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 90 ns
tBLC Byte Load Cycle Time 150 µs
tWPH Write Pulse Width High 100 ns

Program Cycle Waveforms(1)(2)(3)

Notes: 1. A6 through A14 must specify the page address during each high-to-low transition of WE (or CE).
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the page being programmed will be indeterminate.

7
Software Data Protection Software Data Protection
Enable Algorithm(1) Disable Algorithm(1)
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555

LOAD DATA 55 LOAD DATA 55

TO TO
ADDRESS 2AAA ADDRESS 2AAA

LOAD DATA A0 LOAD DATA 80

TO TO
ADDRESS 5555 WRITES ENABLED(2) ADDRESS 5555

LOAD DATA LOAD DATA AA

TO ENTER DATA TO
PAGE (64 BYTES)(4) PROTECT STATE ADDRESS 5555

Notes for software program code:

1. Data Format: I/O7 - I/O0 (Hex); LOAD DATA 55
Address Format: A14 - A0 (Hex). TO
ADDRESS 2AAA
2. Data Protect state will be re-activated at end of pro-
gram cycle.
3. Data Protect state will be deactivated at end of pro- LOAD DATA 20
gram period. TO
ADDRESS 5555 EXIT DATA
4. 64 bytes of data MUST BE loaded. PROTECT STATE(3)

LOAD DATA
TO
PAGE (64 BYTES)(4)

Software Protected Program Cycle Waveform(1)(2)(3)

Notes: 1. A6 through A14 must specify the page address during each high-to-low transition of WE (or CE) after the software code has
been entered.
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the page being programmed will be indeterminate.

8 AT29C256
 AT29C256

Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 0 ns
tOEH OE Hold Time 10 ns
(2)
tOE OE to Output Delay ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Data Polling Waveforms

Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 0 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.

9
Software Product Identification Entry(1) Software Product Identification Exit(1)
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555

LOAD DATA 55 LOAD DATA 55

TO TO
ADDRESS 2AAA ADDRESS 2AAA

LOAD DATA 90 LOAD DATA F0

TO TO
ADDRESS 5555 ADDRESS 5555

PAUSE 10 mS ENTER PRODUCT PAUSE 10 mS EXIT PRODUCT

IDENTIFICATION IDENTIFICATION
MODE(2)(3)(5) MODE(4)

Notes for software product identification:

1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A14 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is DC.

10 AT29C256
 AT29C256

NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT

vs. TEMPERATURE vs. SUPPLY VOLTAGE
1.4 1.4
N N
O O
1.3
R R
M M 1.2
A 1.2 A
L L
I I
1.1 1.0
Z Z
E E
D 1.0 D
0.8
I I
0.9 C
C
C C
0.8 0.6
-55 -25 5 35 65 95 125 4.50 4.75 5.00 5.25 5.50
TEMPERATURE (C) SUPPLY VOLTAGE (V)

NORMALIZED SUPPLY CURRENT

vs. ADDRESS FREQUENCY
1.1
N
O
R
M 1.0
A
L
I
0.9
Z
E VCC = 5V
D T = 25C
0.8
I
C
C
0.7
0 1 2 3 4 5 6 7
FREQUENCY (MHz)

11
Ordering Information
tACC ICC (mA)
(ns) Active Standby Ordering Code Package Operation Range
70 50 0.3 AT29C256-70JC 32J Commercial
AT29C256-70PC 28P6 (0° to 70°C)
AT29C256-70TC 28T
AT29C256-70JI 32J Industrial
AT29C256-70TI 28T (-40° to 85°C)
90 50 0.3 AT29C256-90JC 32J Commercial
AT29C256-90PC 28P6 (0° to 70°C)
AT29C256-90TC 28T
AT29C256-90JI 32J Industrial
AT29C256-90PI 28P6 (-40° to 85°C)
AT29C256-90TI 28T
120 50 0.3 AT29C256-12JC 32J Commercial
AT29C256-12PC 28P6 (0° to 70°C)
AT29C256-12TC 28T
AT29C256-12JI 32J Industrial
AT29C256-12PI 28P6 (-40° to 85°C)
AT29C256-12TI 28T
150 50 0.3 AT29C256-15JC 32J Commercial
AT29C256-15PC 28P6 (0° to 70°C)
AT29C256-15TC 28T
AT29C256-15JI 32J Industrial
AT29C256-15PI 28P6 (-40° to 85°C)
AT29C256-15TI 28T

Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28T 28-lead, Plastic Thin Small Outline Package (TSOP)

12 AT29C256
 AT29C256

Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28P6, 28-lead, 0.600" Wide, Plastic Dual Inline
Dimensions in Inches and (Millimeters) Package (PDIP)
JEDEC STANDARD MS-016 AE Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AB

1.47(37.3)
1.44(36.6) PIN
.045(1.14) X 45˚ .025(.635) X 30˚ - 45˚ 1
PIN NO. 1
.012(.305)
IDENTIFY
.008(.203)
.566(14.4)
.530(13.5)
.553(14.0) .530(13.5)
.490(12.4)
.032(.813) .547(13.9)
.595(15.1) .021(.533)
.026(.660)
.585(14.9) .013(.330)
.090(2.29)
1.300(33.02) REF MAX
.050(1.27) TYP .030(.762) .220(5.59)
.300(7.62) REF .005(.127)
.015(.381) MAX
.430(10.9) MIN
.095(2.41)
.390(9.90) .060(1.52)
AT CONTACT SEATING
.140(3.56) PLANE
POINTS .120(3.05) .065(1.65)
.161(4.09) .015(.381)
.125(3.18)
.022(.559)
.065(1.65) .014(.356)
.022(.559) X 45˚ MAX (3X) .110(2.79) .041(1.04)
.090(2.29)
.630(16.0)
.453(11.5)
.590(15.0)
.447(11.4)
.495(12.6) 0 REF
.485(12.3) .012(.305) 15
.008(.203)
.690(17.5)
.610(15.5)

28T, 28-lead, Plastic Thin Small Outline Package

(TSOP)
Dimensions in Millimeters and (Inches)*

INDEX
MARK
AREA
11.9 (0.469) 13.7 (0.539)
11.7 (0.461) 13.1 (0.516)

0.55 (0.022) 0.27 (0.011)

BSC 0.18 (0.007)

7.15 (0.281)
REF

8.10 (0.319) 1.25 (0.049)

7.90 (0.311) 1.05 (0.041)

0.20 (0.008)
0.10 (0.004)
0
5 REF 0.20 (0.008)
0.15 (0.006)

0.70 (0.028)
0.30 (0.012)

*Controlling dimension: millimeters

13
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© Atmel Corporation 1999.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
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® ™
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0046N–08/99/xM