Microcontrollers And Embedded Systems
Unit 2 :8051 Programming
Faculty Name : Ms. Lavanya.V.Joshi
Unit No: 2 8051 Programming
Lecture No: 11
Instruction Set
Instruction Types
• The 8051 instructions are divided into five functional
groups:
• Arithmetic operations
• Logical operations
• Data transfer operations
• Boolean variable operations
• Program branching operations
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Lecture 11 – Instruction Set
Arithmetic Operations
• With arithmetic instructions, the C8051F020 CPU has no special knowledge of
the data format (e.g. signed binary, unsigned binary, binary coded decimal,
ASCII, etc.)
• The appropriate status bits in the PSW are set when specific conditions are met,
which allows the user software to manage the different data formats
[@Ri] implies contents of
memory location pointed to by
R0 or R1
Rn refers to registers R0-R7 of
the currently selected register
bank
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Lecture 11 – Instruction Set
Logical Operations
• Logical instructions
perform Boolean
operations (AND, OR, XOR,
and NOT) on data bytes on
a bit-by-bit basis
• Examples:
ANL A, #02H ;Mask bit 1
ORL TCON, A ;TCON=TCON-OR-A
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Lecture11 – Instruction Set
Data Transfer Instructions
• Data transfer instructions can be used to Mnemonic Description
transfer data between an internal RAM MOV @Ri, direct [@Ri] = [direct]
location and an SFR location without MOV @Ri, #data [@Ri] = immediate data
going through the accumulator
MOV DPTR, #data 16 [DPTR] = immediate data
• It is also possible to transfer data
between the internal and external RAM MOVC A,@A+DPTR A = Code byte from [@A+DPTR]
by using indirect addressing
MOVC A,@A+PC A = Code byte from [@A+PC]
• The upper 128 bytes of data RAM are
accessed only by indirect addressing and MOVX A,@Ri A = Data byte from external ram [@Ri]
the SFRs are accessed only by direct
MOVX A,@DPTR A = Data byte from external ram [@DPTR]
addressing
MOVX @Ri, A External[@Ri] = A
MOVX @DPTR,A External[@DPTR] = A
PUSH direct Push into stack
POP direct Pop from stack
XCH A,Rn A = [Rn], [Rn] = A
XCH A, direct A = [direct], [direct] = A
XCH A, @Ri A = [@Rn], [@Rn] = A
XCHD A,@Ri Exchange low order digits
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Lecture 11 – Instruction Set
Boolean Variable Instructions
Mnemonic Description
• The 8051 processor can perform single
CLR C Clear C
bit operations
CLR bit Clear direct bit
• The operations include set, clear, and, or SETB C Set C
and complement instructions
SETB bit Set direct bit
• Also included are bit–level moves or CPL C Complement c
conditional jump instructions CPL bit Complement direct bit
• All bit accesses use direct addressing ANL C,bit AND bit with C
ANL C,/bit AND NOT bit with C
ORL C,bit OR bit with C
• Examples: ORL C,/bit OR NOT bit with C
MOV C,bit MOV bit to C
MOV bit,C MOV C to bit
SETB TR0 ;Start Timer0. JC rel Jump if C set
POLL: JNB TR0, POLL ;Wait JNC rel Jump if C not set
till timer overflows. JB bit,rel Jump if specified bit set
JNB bit,rel Jump if specified bit not set
if specified bit set then clear it and
JBC bit,rel
jump
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Lecture 11 – Instruction Set
Program Branching Instructions
Mnemonic Description
• Program branching instructions ACALL addr11 Absolute subroutine call
are used to control the flow of LCALL addr16 Long subroutine call
program execution RET Return from subroutine
RETI Return from interrupt
AJMP addr11 Absolute jump
• Some instructions provide LJMP addr16 Long jump
decision making capabilities SJMP rel Short jump
before transferring control to JMP @A+DPTR Jump indirect
JZ rel Jump if A=0
other parts of the program
JNZ rel Jump if A NOT=0
(conditional branches).
CJNE A,direct,rel
CJNE A,#data,rel
Compare and Jump if Not Equal
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
DJNZ Rn,rel
Decrement and Jump if Not Zero
DJNZ direct,rel
NOP No Operation
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Lecture 11 – Instruction Set
