Schem, MLB, PB 17": MAP17/MAP31
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Edovan soto lizcanoSchem, MLB, PB 17": MAP17/MAP31
Uploaded by
Edovan soto lizcanoCR-1
8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
F 316881 PRODUCTION RELEASED 03/05/04 ?
D PAGE CONTENTS PAGE CONTENTS D
VIDEO CONNECTORS - INVERTER, DVI, S-VIDEO
1
2
TITLE PAGE AND CONTENTS
SYSTEM BLOCK DIAGRAM
22
23
DUAL-CHANNEL LVDS
LMU, LIGHT SENSOR, BOOTBANGER, SLEEP LED
SPIDEY - KBD,TPAD,HALL EFFECT,PWR BUTTON
SCHEM,MLB,PB 17"
3 POWER BLOCK DIAGRAM 24 INTERNAL CONNECTORS - DVD,
CARDSLOT, HARD DRIVE, LEFT USB/BLUETOOTH
03/01/2004
FAN CONTROLLER, MODEM, SOUND
4 PCB NOTES AND HOLES 25 SERIAL DEBUG (JOLLY ROGER, PWR/NMI/RESET) BOM OPTIONS STUFF NO STUFF
D3_HOT
5 MPC7450 MAXBUS INTERFACE 26 USB 2.0
D3_COLD
6 MPC7450 DATA / L3 CACHE INTERFACES/L3 LDO 27 MARVELL GIGABIT ETHERNET PHY GPU_SS
GPU_SWITCH
7 CPU PLL AND CONFIGURATION STRAPS 28 FIREWIRE A/B PHY
SERIAL_DEBUG
C 8 DDR L3 CACHE 29 FIREWIRE A/B CONNECTORS, PORT POWER LIMITER VCORE_OFFSET
C
1_8V_MAXBUS
9 INTREPID MAXBUS AND BOOT STRAPS 30 PMU (POWER MANAGEMENT UNIT)
1_5V_MAXBUS
10 INTREPID MEMORY INTERFACE / BOOT ROM 31 BATTERY CHARGER AND CONNECTOR NEC_USB
INTREPID_USB
11 DDR MEMORY MUXES 32 12.8V SYSTEM POWER SUPPLY / PMU POWER SUPPLY
BBANG
12 200PIN DDR MEMORY SODIMM CONNECTORS 33 3.3V / 5V SYSTEM POWER SUPPLIES
NO_BBANG
13 INTREPID AGP 4X/PCI 34 CPU CORE VOLTAGE POWER SUPPLY MAP31
MAP17
14 INTREPID ENET/FW/UATA/EIDE INTERFACES 35 1.5V/ 1.8V / 2.5V SYSTEM POWER SUPPLIES
SSCG
15 INTREPID GPIOS/SERIAL/USB INTERFACES/SSCG 36 SIGNAL CONSTRAINTS (1 OF 3) - DIGITAL/CLK NO_SSCG
5V_HD_LOGIC
B 16 INTREPID POWER RAILS/1.5V LDO 37 SIGNAL CONSTRAINTS (2 OF 3) - DIGITAL/DIFF B
3V_HD_LOGIC
17 INTREPID DECOUPLING 38 SIGNAL CONSTRAINTS (3 OF 3) - POWER NETS NO_4XVCORE
4X_VCORE
18 CARDBUS CONTROLLER (PCI1510) 39 FUNCTIONAL TEST POINTS
19 MAP17/31 AGP & FRAME BUFFER 40 REVISION HISTORY (1 OF 1)
20 MAP17/31 LVDS/TMDS/GPIO & GPU VCORE 41-42 SIGNAL NAMES
21 MAP17/31 ANALOG, DVO INTERFACE, GND 43-44 COMPONENT LOCATIONS
DIMENSIONS ARE IN MILLIMETERS
METRIC Apple Computer Inc.
XX
A X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
MAP17/MAP31 ANGLES
ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TABLE_5_HEAD
TABLE_5_HEAD
QA APPD DESIGNER TITLE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM
DO NOT SCALE DRAWING
SCHEM,MLB,PB 17"
TABLE_5_ITEM
051-6469 1 SCHEM,MLB,PB 17 SCH1 338S0076 1 IC,ASSP,MAP17-464,GRPHCS CTLR,548 BGA U43 CRITICAL MAP17
TABLE_5_ITEM
RELEASE SCALE
TABLE_5_ITEM
820-1502 1 PCBF,MLB,PB 17 PCB1 338S0094 1 IC,ASSP,MAP31-464,GRPHCS CTLR,548 BGA U43 CRITICAL MAP31 NONE
SIZE DRAWING NUMBER REV.
MATERIAL/FINISH
NOTED AS D 051-6469 F
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 44
8 7 6 5 4 3 2 1
CR-2
8 7 6 5 4 3 2 1
J18 J24 J22
Ethernet FW - A FW - B
Connector Connector Connector SLEEP
P.29 P.29 LED LMU
P.27 J25 J19
P.25
2 DATA PAIRS
2 DATA PAIRS Battery Power Supply SUTRO (PWR)
4 DATA PAIRS @ 200MHz Connector & Charger
@ 400MHZ Connector
D U49
U28
J11 P.31 P.31-35 P.31
D
FireWire OPTICAL DRIVE
Ethernet PHY J14
PHY Connector U36
P.28 TUBA (SOUND) SMBUS
P.27 P.24
G/MII J13
Connector
P.25
3.3V LMU I2C
3.3V 1394 OHCI ULTRA ATA/100 U39
10/100/1000 3.3V Connector P.23
8BIT TX 8BIT TX/RX
50MHZ P.24
EIDE
I2S I2C
U48/J2/J4
Fan
PMU
8BIT RX
125MHZ I2C Circuit P.30 J10
UIDE P.25 CARDBUS
SERIAL
NOT USED Connector
J3 (SHARE WITH BLUETOOTH) 5V
ETHERNET FIREWIRE P.18
LEFT USB 10/100/1000 400 MB/S
UATA 100 EIDE CARDSLOT I2S I2C J15
P.14 P.14 P.14 P.15 P.14 J5
P.24 USB 2.0 P.14 P.14 P.15 TRACKPAD Keyboard 33MHZ
C USB PORT A SCCA
Serial Debug
Connector Connector 16/32 BITS C
J12 Connector 3.3V/5V
P.15 P.15
RIGHT USB P.25 KB LED U26
NOT USED USB PORT B LIGHT SENSOR
BACKUP BATTERY P.15 VIA/PMU P.23 TI PCI1510
USB 2.0
P.32 USB PORT C
P.15 U17 CardBus
P.15 U52
J3 (SHARE WITH LEFT USB)
BlueTooth NOT USED USB PORT D
INTREPID BOOTROM
P.14
BOOT ROM
1M X 8 USB 2.0
CONTROLLER
Controller
P.18
P.15 P.10
P.24 P.26
USB PORT E PCI
J9 P.15 64BITS PCI BUS
33MHZ 32BITS
Modem Board USB PORT F 33MHZ
P.15 P.13
Connector AGP BUS 3.3V
1.5V/3.3V U43
P.25
32BITS MEMORY MEMORY
MAXBUS J21
B INTRPEID P.9 4X AGP
66MHZ NVIDIA CH. A CH. C
AIRPOPT B
I2C MAXBUS
1.8V
DDR MEMORY
P.10
P.13
MAP17 (INTERNAL MEM) (INTERNAL MEM)
MEMORY MEMORY
Connector
167MHZ
32BIT ADDRESS MEMORY BUS
64MB CH. B CH. D
P.24
64BIT DATA 2.5V P.19-21 (INTERNAL MEM) (INTERNAL MEM)
167MHZ J8
U42 U11/U12/U13/U14 64BITS
EDID (I2C)
COMPOSITE
Inverter
S-VIDEO
CPU PLL 2:1 DDR MUXES Connector
APOLLO
(DDC TOO)
Config P.22
LVDS
TMDS
RGB
P.11
CPU P.7
J7 J17 J16
(MPC7455) PMU
P.5-6 LCD Panel S-Video DVI-I
J20/J23 Connector Connector Connector
L3 BUS
1.5V DDR SDRAM DIMM 0 P.22 P.22 P.22 SYSTEM BLOCK DIAGRAM
A 250/300 MHZ NOTICE OF PROPRIETARY PROPERTY
A
18BIT ADDRESS
U6/U7 64BIT DATA DDR SDRAM DIMM 1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
SO-DIMM Connector I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
L3 Cache P.12 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
P.8 D 051-6469 F
APPLE COMPUTER INC.
SCALE SHT OF
NONE 2 44
8 7 6 5 4 3 2 1
CR-3
8 7 6 5 4 3 2 1
POWER SYSTEM ARCHITECTURE
+5V_MAIN
1V20_REF -
U21
MAP17 DDR CORE
>~13.44V TURNS-ON PG 31
+
BACKLIGHT VCC MAP17 DDR I/O DCDC_EN
<~13.44V SHUTS-OFF
INVERTER L3 CORE SLEEP
MAIN 2.5V/1.5V DDR POWER
+PBUS
D AC RUN/SS D
DC/DC +2.5V_MAIN
ADAPTER INRUSH BUCK MAXBUS
LIMITER +24V_PBUS REGULATOR (MAX1715) SEQUENCING
VCC
IN PG 30
+PBUS (12.8V) PG 35 PGOOD 1_5V_2_5V_OK
(LTC1625)
PG 31 PG 32 SHUTDOWN: STOPPED
14V_PBUS +5V_MAIN SLEEP: RUNNING +1.5V_MAIN
AC: 12.8V RUN: RUNNING
NO AC: BATTERY VOLTAGE INTREPID CORE
1625 NOT RUNNING TURNS ON OUTPUT @ 2.4V AGP I/O +5V_MAIN
ON1/ON2
SHUTDOWN: RUNNING L3 I/O
SLEEP: RUNNING VCC SHDN
RUN: RUNNING
+5V_MAIN
DCDC_EN_L
AFTER PMU IS UP AND RUNNING
DCDC_EN_L WILL PULL ON1/ON2
DC/DC
RC AT 1M*0.047UF @ 24V (MAX1717)
+3V_PMU STARTS 2.0MSEC AFTER DCDC_EN_L BECOMES LOW
LOW IN SHUTDOWN
+BATT
+5V_MAIN
PG 34
LDO +3V_PMU
RUN/SS - 5V EXT_VCC
+4_6V_BU TURNS ON AT >1V +5V_MAIN +PBUS (12.8V) SHUTDOWN: STOPPED
C PG 32
<100UA ALLOWED
INTERNAL ZENER CLAMP TO 6V
VCC DC/DC SLEEP: STOPPED C
MAIN 3V/5V PGOOD 3V_5V_OK (LTC1778) GPU_VCORE RUN: RUNNING
PG 20
DC/DC SHUTDOWN: STOPPED +1.35V/+1.2V
(LTC3707) HOLDS BOTH RUN/SS AT GND
DCDC_EN SLEEP: D3HOT/D3COLD CPU_VCORE
VCC PG 33 STBYMD
WHEN IT’S CONNECTED TO GND
RUN: RUNNING (+1.4V/+1.5V)
TURNS CONTROL TO RUN/SS SLEEP
+PBUS WHEN IT’S OPEN
D3_COLD
TURNS ON AS LOW AS 0.8V/TYP 1.5V
SHUTDOWN: STOPPED INTERNAL 1.2UA CURRENT SOURCE
SLEEP: RUNNING GPU_VCORE RUN/SS
1_5V_2_5V_OK WILL NOT PULL LOW UNTIL
RUN: RUNNING SEQUENCING
BACKUP 12.8V CHARGES BACKUP BATTERY
INTERNAL ZENER CLAMP TO 6V
+3.3V_MAIN
+5V_MAIN TURNS ON
HOWEVER, 5V SHOULD TURN ON ~2.23MS AFTER
<100UA ALLOWED 1M & 0.1UF @14V, IT TAKES DCDC_EN_L OR PMU_POWERUP_L
BATTERY TURNS ON AT >1V
RUN/SS - 3V
~5.88MS TO START SWITCHER 1_5V_2_5V_OK
D3_HOT
BECOMES ’1’; MUCH LESS THAN THE
RC CHARGING AT INT_VCC (5V)
DCDC_EN_L
D3_HOT
24V IS OUTPUT ONLY FROM
BACKUP BATTERY
RC AT 1M*0.1UF @ 24V
CHARGER INPUT STARTS ~4.25MSEC AFTER DCDC_EN_L BECOMES LOW
SHUT-DOWN RUN SLEEP RUN SHUT-DOWN
NO INRUSH PROTECTION
& BOOST OUTPUT WHEN ONLY BATTERY IS CONNECTED SLEEP
B PG 32 +24V_PBUS SLEEP_L_LS5 B
BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS
DCDC_EN
AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V DC/DC DCDC_EN_L
(UNTIL DRAINED)
(LTC3411) +5V_MAIN ~11MS
+1.8V_MAIN
BATTERY PG 35 +5V_SLEEP
MAXBUS +3V_MAIN ~13.5MS
CHARGER SHUTDOWN: STOPPED BROADCOM
SLEEP: STOPPED +3V_SLEEP
(MAX1772) RUN: RUNNING 3V_5V_OK 2.4V - ??? MS
PG 31 +2_5V_MAIN 2.6 MS
+2_5V_SLEEP
+BATT +1_5V_MAIN 2.6 MS
NO INRUSH PROTECTION +1_5V_SLEEP
3S 3P PRISMATIC CELLS WHEN ONLY BATTERY IS CONNECTED
1_5V_2_5V_OK
(MAX1715 OUTPUT)
BATTERY VOLTAGE 1_5V_2_5V_OK POWER BLOCK DIAGRAM
A +PBUS
(AT LTC1778 RUN/SS)
A
GPU_VCORE ~???MS NOTICE OF PROPRIETARY PROPERTY
FEED-IN PATH (D3HOT)
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
GPU_VCORE AGREES TO THE FOLLOWING
PG 31 (D3COLD) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
+1_8V_MAIN III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1.9 MS
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 3 44
8 7 6 5 4 3 2 1
CR-4
8 7 6 5 4 3 2 1
BOARD HOLES
CHASSIS MOUNTS
ASICS HEATSINK MOUNTS I/O AREA INVERTER
ZT6 ZT1
255R158 146R126
1 1 1
D
PCB SPECS 1
ZT3
255R158
CHGND5
BS1
2
3
SH1
OG-503040
SHLD-SM
D
ZT7 STDOFF-217ODX150IDX35H-TH CHGND2
255R158 1
1
THICKNESS : 1.2 MM / 0.047 IN CHGND1
1/2 OZ CU THICKNESS: 0.7 MILS 1
ZT5
235R126 ZT14
146R126
1.0 OZ CU THICKNESS: 1.4 MILS ZT8
1
235R126 CHGND6
1
SPEAKER CLIPS
IMPEDANCE : 50 OHMS +/- 10% SP1 SP2 SP3 SP4 SP5
DIELECTRIC: FR-4 SPKR_CLIP_P84 SPKR_CLIP_P84 SPKR_CLIP_P84 SPKR_CLIP_P84 SPKR_CLIP_P84
LAYER COUNT: 12 CONDUCTIVE MOUNTS
1 1 1 1 1
SIGNAL TRACE WIDTH: 4 MILS ZT4
235R126
SIGNAL TRACE SPACING: 4 MILS 1
SP6
SPKR_CLIP_P84
C PREPREG THICKNESS: 2-3 MILS 1
C
SEE PCB CAD FILES FOR MORE SPECIFIC INFO.
GROUND VIAS
ZT48 ZT63 ZT101
BOARD STACK-UP AND CONSTRUCTION ZT18
HOLE-VIA-20R10
1
ZT33
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
20R10 TH VIA OR VIA IN PAD
ZT19 ZT34 ZT49 ZT64 ZT102
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
HOLE-VIA-20R10 HOLE-VIA-20R10
1 SIGNAL (1/3 OZ + COPPER PLATING) 1 1 1 1 1
ZT20 ZT35 ZT50 ZT65 ZT103
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
PREPREG (3MIL) HOLE-VIA-20R10 HOLE-VIA-20R10 1 1 1
2 GROUND (1/2 OZ) 1 1
ZT21 ZT36 ZT51 ZT66 ZT104
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
HOLE-VIA-20R10 HOLE-VIA-20R10 1 1 1
LAMINATE (4MIL) 1 1
3 SIGNAL (1/2 OZ) ZT22 ZT37 ZT52 ZT67 ZT105
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
HOLE-VIA-20R10 HOLE-VIA-20R10 1 1 1
1 1
PREPREG (3MIL) ZT68
4 SIGNAL (1/2 OZ) ZT23 ZT38 ZT53 ZT106
B HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1 HOLE-VIA-20R10
1
B
LAMINATE (4MIL) ZT54 ZT69
5 GROUND (1/2 OZ) ZT24 ZT39 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT107
HOLE-VIA-20R10 HOLE-VIA-20R10 1 1 HOLE-VIA-20R10
1 1 1
ZT55 ZT70
6 PREPREG (2MIL) CUT POWER PLANE(1 OZ) ZT25
HOLE-VIA-20R10
ZT40
HOLE-VIA-20R10 HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
ZT108
HOLE-VIA-20R10
1 1 1
ZT26 ZT41 ZT56 ZT71
LAMINATE (3MIL) HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT109
7 CUT POWER PLANE(1 OZ) 1 1 1 1 HOLE-VIA-20R10
1
ZT27 ZT42 ZT57 ZT72
HOLE-VIA-20R10 ZT110
8 PREPREG (2MIL) HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 1 HOLE-VIA-20R10
GROUND (1/2 OZ) 1 1 1
1
ZT28 ZT43 ZT58 ZT73
HOLE-VIA-20R10 HOLE-VIA-20R10 ZT111
HOLE-VIA-20R10 HOLE-VIA-20R10
LAMINATE (4MIL) 1 1 1 1
HOLE-VIA-20R10
9 SIGNAL (1/2 OZ) 1
ZT29 ZT44 ZT59 ZT74
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT112
10 PREPREG (3MIL) 1 1 1 1 HOLE-VIA-20R10
SIGNAL (1/2 OZ) ZT75
1
ZT30 ZT45 ZT60 HOLE-VIA-20R10 ZT114
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 1 HOLE-VIA-20R10
LAMINATE (4MIL) 1 1 1
1
11 GROUND (1/2 OZ) ZT61 ZT76
ZT31 ZT46 ZT115
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1
HOLE-VIA-20R10
1 HOLE-VIA-20R10 BOARD INFORMATION
A 12
PREPREG (3MIL)
SIGNAL (1/3 OZ + COPPER PLATING) ZT32 ZT47 ZT62 ZT100
1
NOTICE OF PROPRIETARY PROPERTY
A
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 ZT116
1 1 1 1 HOLE-VIA-20R10
1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 4 44
8 7 6 5 4 3 2 1
CR-5
8 7 6 5 4 3 2 1
1_5V_MAXBUS
MAXBUS_SLEEP 5 7 9 16 17 23 34 38 +1_5V_SLEEP
R606 MPC7450 PULL-UPS
CPU_VCORE DECOUPLING NETWORK CPU_OVDD DECOUPLING NETWORK 1
0 2
39 38 34 5 CPU_VCORE_SLEEP 5%
1/16W
C153 C141 C108 C200 C173 C140 C31 C73 C51 C203 CPU INTERNAL PLL FILTERING MF
603 MAXBUS_SLEEP
R1751 10UF 10UF
1
0.1UF
1
0.1UF
1
0.1UF
1
0.1UF
R501 1
0.1UF
1
0.1UF
1
0.1UF
1
0.1UF +1_8V_SLEEP 1_8V_MAXBUS
38 34 23 17 16 9 7 5
470 470 CPU_VCORE_SLEEP
5%
1/16W
20%
6.3V
20%
6.3V
20%
2 10V
20%
10V
2 CERM
20%
2 10V
20%
2 10V
5%
1/16W
20%
10V
2 CERM
20%
2 10V
20%
2 10V
20%
10V
2 CERM
5 34 38 39
R602 R39
MF CERM CERM CERM CERM CERM MF CERM CERM 0
805 805 402 402 402 402 402 402 402 402 2 1 2 10K
402 2 402 2 R5 5%
9 5 CPU_TBEN 1 2
10 1/16W 5%
5%
1/16W
MF
MF
603
1/16W
MF R90
402 10K
1 402 1 2
D
1 C239
10UF
1 C255
10UF
1 C138
0.1UF
1 C109
0.1UF
1 C201
0.1UF
1 C174
0.1UF
1 C74
0.1UF
1 C76
0.1UF
1 C111
0.1UF
1 C238
0.1UF
38 CPU_AVDD 5 CPU_CHKS_L
5% D
20%
6.3V
2 CERM
20%
6.3V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
R518 1/16W
MF
10K 402
805 805 402 402 402 402 402 402 402 402 1 C29 1 C9 5 CPU_SHD0_L 1 2
0.1UF 2.2UF 5%
20%
10V
20%
10V
1/16W
MF R66
2 CERM 2 CERM 402
1
10K 2
402 805 5 CPU_SHD1_L
1 C204 1 C180 1 C172 1 C139 1 C110 1 C202 1 C30 1 C45 1 C95 1 C75 5%
2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF R73 1/16W
MF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
10K
TABLE_ALT_HEAD
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 402
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 5 CPU_MCP_L 1 2
805 805 402 402 402 402 402 402 402 402 PART NUMBER
TABLE_ALT_ITEM
5%
1/16W
337S2887 337S2775 ? U42 1.0GHZ SICOH APOLLO 5 MF RP11
402
1
10K 8
5 CPU_LSSD_MODE
5%
R24 1/16W
10K
AA15
SM1
MORE 0805 10UF CAPS ON VCORE POWER SUPPLY PAGE (PG 32)
J11
J13
J15
K10
K12
K14
L11
L13
L15
M10
M12
M14
N11
N13
N15
P10
P12
P14
C10
U11
U15
V13
Y10
Y17
Y19
AA4
CPU_L2TSTCLK 1 2
J9
L9
N9
B3
C5
C7
D2
E3
E9
F5
G3
G9
H7
J5
K3
L7
M5
N3
P7
R4
T3
U5
U7
V3
V9
Y2
Y5
Y7
B2
5
5%
VDD OVDD
AVDD 1/16W
MF R38
BVSEL G6 CPU_BUS_VSEL 7
402
1
1K 2
39 5 CPU_CHKSTP_OUT_L
CPU_BR_L K1 D6 SYSCLK_CPU 5%
BR SYSCLK
36 9
CPU_BG_L R3 BG CLK_OUT N1 CPU_CLKOUT_SPN
9 36
R84 1/16W
MF
36 9
1
10K 2
402
F2 NC12 A2 CPU_PLL_CFG<0> 5 CPU_SRWX_L
NC CRITICAL PLL_CFG0 7
CPU_TS_L P5 TS F7 CPU_PLL_CFG<1> 5%
36 9 PLL_CFG1 7 1/16W
R55
5 CPU_PULLDOWN E10 A0
U42 PLL_CFG2
PLL_CFG3
C2
D4
CPU_PLL_CFG<2>
CPU_PLL_CFG<3>
7
7
RC GLITCH FILTER
PLACE CLOSE TO PIN
5 CPU_PMONIN_L
MF
402
1
10K 2
N4
E8
A1
A2
APOLLO PLL_EXT
DBG
H8
V1
CPU_PLL_CFGEXT
CPU_DBG_L
7
R51 R44
5%
1/16W
MF
9 36 10K 402
C N5 A3 1GHZ-1.32V DRDY T6 36 CPU_DRDY_L_UF 1
0 2 CPU_DRDY_L 9 36
5 CPU_EMODE1_L 1
5%
2
C
36 9
36 9
CPU_ADDR<0>
CPU_ADDR<1>
C8
R2
A4
A5
R3.3-NDE5-85C-BGA (1 OF 3)
DTI0
DTI1
P2
T5
CPU_EDTI
CPU_DTI<0>
5
9 36
5%
1/16W
MF
1/16W
MF
402
R56
1K
402 1 2
36 9 CPU_ADDR<2> A7 A6 DTI2 U3 CPU_DTI<1> 9 36
1 C77 5 CPU_PULLUP
36 9 CPU_ADDR<3> M2 A7 DTI3 P6 CPU_DTI<2> 9 36
10PF 5%
1/16W
5%
36 9 CPU_ADDR<4> A6 A8 50V
2 CERM R37 MF
402
36 9 CPU_ADDR<5> M1 A9 402
1
10K 2
39 23 7 5 CPU_HRESET_L
36 9 CPU_ADDR<6> A10 A10 TDI E4 JTAG_CPU_TDI 5 23 39 5%
CPU_ADDR<7> U2 H1 JTAG_CPU_TDO_TP 1/16W
A11 TDO
36 9
CPU_ADDR<8> N2 A12 TMS K4 JTAG_CPU_TMS
39 MF
402 R74
36 9 5 23 39
1
10K 2
CPU_ADDR<9> P8 J7 JTAG_CPU_TCK 30 5 CPU_SMI_L
36 9 A13 TCK 5 23 39
M8 C1 5%
36 9 CPU_ADDR<10> A14 TRST JTAG_CPU_TRST_L 5 23 39 1/16W
36 9 CPU_ADDR<11> W4 A15 LSSD_MODE F6 CPU_LSSD_MODE 5 R13 MF
402
36 9 CPU_ADDR<12> N6 A16 L1_TSTCLK H4 CPU_L1TSTCLK 5 1
470 2
470OHM FOR BOOT BANGER 39 23 5 JTAG_CPU_TMS
36 9 CPU_ADDR<13> U6 A17 L2_TSTCLK J2 CPU_L2TSTCLK 5 5%
CPU_ADDR<14> R5 1/16W
36 9 A18 MF
36 9 CPU_ADDR<15> Y4 A19 TA N8 CPU_TA_L 9 36
402 R12
P1
470
36 9 CPU_ADDR<16> A20 TEA T1 CPU_TEA_L 9 36 470OHM FOR BOOT BANGER 39 23 5 JTAG_CPU_TDI 1 2
36 9 CPU_ADDR<17> P4 A21 5%
1/16W
CPU_ADDR<18> R6 A22 MF
36 9
M7 L3
RP11 402
36 9 CPU_ADDR<19> A23 TBEN CPU_TBEN 59 10K
N7 Y1 15 5 MPIC_CPU_INT_L 4 5
36 9 CPU_ADDR<20> A24 QREQ CPU_QREQ_L 9 36
36 9 CPU_ADDR<21> AA3 A25 QACK K7 CPU_QACK_L 9 36
5%
1/16W
36 9 CPU_ADDR<22> U4 A26 CKSTP_IN F3 SM1
RP11
36 9 CPU_ADDR<23> W2 A27 CKSTP_OUT K6 CPU_CHKSTP_OUT_L 5 39
10K
39 5 CPU_SRESET_L 2 7
36 9 CPU_ADDR<24> W1 A28
5%
B 36 9
36 9
CPU_ADDR<25>
CPU_ADDR<26>
W3
V4
A29
A30
TEST0 B10 CPU_CHKS_L 5
RP11
1/16W
SM1 B
CPU_ADDR<27> AA1 10K
36 9 A31 J6 5 CPU_L1TSTCLK 3 6
INT MPIC_CPU_INT_L 5 15
36 9 CPU_ADDR<28> D10 A32
SMI G8 CPU_SMI_L 5 30
5%
J4 1/16W
36 9 CPU_ADDR<29> A33
MCP B8 CPU_MCP_L 5 SM1 R32
36 9 CPU_ADDR<30> G10 A34 G1 CPU_SRESET_L CPU_EDTI 1
10K 2
D9 SRESET 5 39 5
36 9 CPU_ADDR<31> A35
HRESET A3 CPU_HRESET_L 5 7 23 39 5%
1/16W
NC L5 AP0
R65 MF
402
PMON_IN E6 CPU_PMONIN_L 5 1
10K 2
L6 39 23 5 JTAG_CPU_TCK
NC AP1
J1 PMON_OUT B4 NC 5%
NC AP2 1/16W
NC H2 AP3 MF
402
R91
G5 AP4 BMODE0 C6 CPU_EMODE0_L 7
1
470 2
NC 5 CPU_PULLDOWN
BMODE1 C4 CPU_EMODE1_L 5
5%
1/16W
36 9 CPU_TT<0> F1 TT0 MF
TEST6 A9 CPU_PULLDOWN 5 402
36 9 CPU_TT<1> F4 TT1
EXT_QUAL B9 MAXBUS_SLEEP 5 7 9 16 17 23 34 38
36 9 CPU_TT<2> K8 TT2
TEST1 H6 CPU_PULLUP 5 BBANG
36 9 CPU_TT<3> A5 TT3
TEST2 H10 1
36 9 CPU_TT<4> E1 TT4
NC13 B6 NC
R19
36 9 CPU_TBST_L B7 TBST 470
TEST3 D8 CPU_SRWX_L 5
470OHM FOR BOOT BANGER 5%
36 9 CPU_TSIZ<0> L1 TSIZ0 1/16W
TEST4 F9 MF
36 9 CPU_TSIZ<1> H3 TSIZ1 2 402
TEST5 F8
36 9 CPU_TSIZ<2> D1 TSIZ2
39 23 5 JTAG_CPU_TRST_L
36 9 CPU_GBL_L M4 GBL
SPARE0 A8 NC NO_BBANG
A
36 9
36 9
CPU_WT_L
CPU_CI_L
L2
R1
WT
CI
SPARE1
SPARE2
SPARE3
NC1
D3
H9
J8
A11
NC
NC
NC
NC
1
R23
200
MPC7450 MAXBUS
36 9
36 9
CPU_AACK_L
CPU_ARTRY_L
U1
T2
AACK
ARTRY
NC2
NC3
NC4
B11
C11
D5
NC
NC
NC
5%
1/16W
MF NOTICE OF PROPRIETARY PROPERTY
A
NC5 NC 2 402
D11
5 CPU_SHD0_L L4 SHD0 NC6 E7 NC
L8 NC7 E11 NC THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
5 CPU_SHD1_L SHD1 NC8 F11 NC PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
NC9 G2 NC AGREES TO THE FOLLOWING
36 9 CPU_HIT_L K2 HIT NC10 G11 NC
NC11 H11 NC I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
GND III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
J10
J12
J14
K9
K11
K13
K15
L10
L12
L14
M9
M11
M13
N10
N12
N14
P9
P11
P13
P15
B1
B5
C3
C9
D7
E2
E5
F10
G4
G7
H5
J3
K5
M3
M6
P3
T4
T7
T9
T13
V2
V5
V8
V12
V15
W7
Y3
Y9
Y13
Y15
Y20
AA5
AA17
AB1
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 5 44
8 7 6 5 4 3 2 1
CR-6
8 7 6 5 4 3 2 1
B13
B15
B17
B19
B21
D12
D14
D16
D18
D21
E19
F13
F15
F17
F21
G19
H12
H14
H17
H21
J19
K17
K21
L19
M17
M21
N19
P17
P21
R15
R19
T17
T21
U19
V17
V21
W19
Y21
GVDD
36 8
36 8
L3_ADDR<0>
L3_ADDR<1>
L18
K22
L3A0
L3A1
CRITICAL L3 DECOUPLING CAPS
36 8
36 8
L3_ADDR<2>
L3_ADDR<3>
L16
K20
L3A2
L3A3 U42
36 8
36 8
L3_ADDR<4>
L3_ADDR<5>
K18
J22
L3A4
L3A5
APOLLO PLACE 1 EACH NEAR PINS B15, D12, E19, F15, H17, K17, M19, R15, T17, AND V21 OF CPU
L3_ADDR<6> J20 L3A6 1GHZ-1.32V 38 8 6 L3_OVDD
D
D 36 8
36 8 L3_ADDR<7> H22
J18
L3A7 R3.3-NDE5-85C-BGA
36 9 CPU_DATA<0> AB15 D0 36 8 L3_ADDR<8> L3A8 (3 OF 3)
CRITICAL
36 9 CPU_DATA<1> T14 D1 36 8 L3_ADDR<9> K16 L3A9 1 C237 1 C297 1 C290 1 C265 1 C236
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
36 9
36 9
CPU_DATA<2>
CPU_DATA<3>
R14 D2
AB13 D3 U42 36 8
36 8
L3_ADDR<10>
L3_ADDR<11>
H20
G22
L3A10
L3A11
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
36 9 CPU_DATA<4>
CPU_DATA<5>
V14 D4
U14 D5
APOLLO 36 8
36 8
L3_ADDR<12>
L3_ADDR<13>
F22
G20
L3A12
L3A13
402 402 402 402 402
36 9
36 9 CPU_DATA<6> AB14 D6 1GHZ-1.32V 36 8 L3_ADDR<14> H18 L3A14
36 9 CPU_DATA<7> W16 D7
AA11 D8
R3.3-NDE5-85C-BGA
(2 OF 3)
36 8
36 8
L3_ADDR<15>
L3_ADDR<16>
E22
J16
L3A15
L3A16
36 9 CPU_DATA<8>
Y11 D9 36 8 L3_ADDR<17> F20 L3A17
CPU_DATA<9>
36 9
CPU_DATA<10> U12 D10
1 C296 1 C179 1 C266 1 C171 1 C295
36 9
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
36 9 CPU_DATA<11> W13 D11 20% 20% 20% 20% 20%
10V 10V 10V 10V 10V
Y14 D12 36 8 L3_DATA<0> AA19 L3D0 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
36 9 CPU_DATA<12>
AB20 402 402 402 402 402
36 9 CPU_DATA<13> U13 D13 36 8 L3_DATA<1> L3D1
T12 D14 36 8 L3_DATA<2> U16 L3D2
36 9 CPU_DATA<14>
W12 D15 36 8 L3_DATA<3> W18 L3D3
36 9 CPU_DATA<15>
AB12 D16 36 8 L3_DATA<4> AA20 L3D4
36 9 CPU_DATA<16>
R12 D17 36 8 L3_DATA<5> AB21 L3D5
36 9 CPU_DATA<17>
AA13 D18 36 8 L3_DATA<6> AA21 L3D6
36 9 CPU_DATA<18>
AB11 D19 36 8 L3_DATA<7> T16 L3D7
36 9 CPU_DATA<19>
Y12 D20 36 8 L3_DATA<8> W20 L3D8
36 9 CPU_DATA<20>
V11 D21 36 8 L3_DATA<9> U18 L3D9
36 9 CPU_DATA<21>
T11 D22 36 8 L3_DATA<10> Y22 L3D10
36 9 CPU_DATA<22>
R11 D23 36 8 L3_DATA<11> R16 L3D11
36 9 CPU_DATA<23>
CPU_DATA<24> W10 D24 36 8 L3_DATA<12> V20 L3D12 L3VSEL A4 CPU_L3_VSEL 7
C
36 9
36 9 CPU_DATA<25> T10 D25
W11 D26
36 8
36 8
L3_DATA<13>
L3_DATA<14>
W22
T18
L3D13
L3D14
C
36 9 CPU_DATA<26>
36 9 CPU_DATA<27> V10 D27 36 8 L3_DATA<15> U20 L3D15 L3CLK0 V22 L3_CLK<0> 8 36
36 9 CPU_DATA<28> R10 D28 36 8 L3_DATA<16> N18 L3D16 L3CLK1 C17 L3_CLK<1> 8 36
U10 D29 36 8 L3_DATA<17> N20 L3D17
36 9 CPU_DATA<29>
AA10 D30 36 8 L3_DATA<18> N16 L3D18
36 9 CPU_DATA<30>
U9 D31 36 8 L3_DATA<19> N22 L3D19
L3CNTL0* L20 L3_CNTL<0> 8 36
36 9 CPU_DATA<31>
V7 D32 36 8 L3_DATA<20> M16 L3D20
L3CNTL1* L22 L3_CNTL<1> 8 36
36 9 CPU_DATA<32>
T8 D33 36 8 L3_DATA<21> M18 L3D21
36 9 CPU_DATA<33>
AB4 D34 36 8 L3_DATA<22> M20 L3D22
36 9 CPU_DATA<34>
Y6 D35 36 8 L3_DATA<23> M22 L3D23
36 9 CPU_DATA<35>
36 9 CPU_DATA<36> AB7 D36 36 8 L3_DATA<24> R18 L3D24 L3ECHO_CLK0 V18 L3_ECHO_CLK<0> 8 36
36 9 CPU_DATA<37> AA6 D37 36 8 L3_DATA<25> T20 L3D25 L3ECHO_CLK1 P20 L3_ECHO_CLK<1> 8 36
36 9 CPU_DATA<38> Y8 D38 36 8 L3_DATA<26> U22 L3D26 L3ECHO_CLK2 E18 L3_ECHO_CLK<2> 8 36
36 9 CPU_DATA<39> AA7 D39 36 8 L3_DATA<27> T22 L3D27 L3ECHO_CLK3 E14 L3_ECHO_CLK<3> 8 36
W8 D40 36 8 L3_DATA<28> R20 L3D28
36 9 CPU_DATA<40>
AB10 D41 36 8 L3_DATA<29> P18 L3D29
36 9 CPU_DATA<41>
AA16 D42 36 8 L3_DATA<30> R22 L3D30 +1_5V_SLEEP
36 9 CPU_DATA<42>
AB16 D43 36 8 L3_DATA<31> M15 L3D31
36 9 CPU_DATA<43>
36 9
36 9
CPU_DATA<44>
CPU_DATA<45>
AB17 D44
Y18 D45
36 8
36 8
L3_DATA<32>
L3_DATA<33>
G18
D22
L3D32
L3D33
L3_OVDD GENERATOR
AB18 D46 L3_DATA<34> E20 L3D34 1
36 9 CPU_DATA<46> 36 8
L3_DATA<35> H16 L3D35 THIS LDO WAS ADDED TO SUPPORT SCHMOO’ING OF L3_OVDD VOLTAGE
R649
36 9 CPU_DATA<47> Y16 D47 36 8 0
AA18 D48 36 8 L3_DATA<36> C22 L3D36 5%
36 9 CPU_DATA<48> 1/16W
F18 +1_8V_SLEEP +2_5V_SLEEP MF
CPU_DATA<49> W14 D49 36 8 L3_DATA<37> L3D37 NO STUFF
36 9
D20 2 603
36 9 CPU_DATA<50> R13 D50 36 8 L3_DATA<38> L3D38 LDO OUTPUTS 1.41V (SAME AS P59) R640
B 36 9
36 9
CPU_DATA<51>
CPU_DATA<52>
W15 D51
AA14 D52
36 8
36 8
L3_DATA<39>
L3_DATA<40>
B22
G16
L3D39
L3D40 NO STUFF NO STUFF
38 LTC1962_L3_VOUT 1
0 2 L3_OVDD 6 8 38 B
5%
A21 L3D41 1 1
36 9 CPU_DATA<53> V16 D53 36 8 L3_DATA<41>
G15
R609 R627 NO STUFF
1/16W
MF
CPU_DATA<54> W6 D54 36 8 L3_DATA<42> L3D42 0 0 NO STUFF NO STUFF 1
603
36 9
AA12 D55 L3_DATA<43> E17 L3D43
5%
1/16W
5%
1/16W R639
36 9 CPU_DATA<55>
V6 D56
36 8
L3_DATA<44> A20 L3D44
MF MF U47 C679 1 10.7K
36 9 CPU_DATA<56> 36 8
2 603 2 603 LT1962-ADJ 0.01UF 1%
1/16W
AB9 D57 L3_DATA<45> C19 L3D45 20% MF
36 9 CPU_DATA<57> 36 8 MSOP 16V
C18 38 LTC1962_L3_VIN 8 IN OUT 1 CERM 2 2 402 NO STUFF
CPU_DATA<58> AB6 D58 36 8 L3_DATA<46> L3D46 402
36 9
CPU_DATA<59> R7 D59 36 8 L3_DATA<47> A19 L3D47 NC 7 NC
1 C673
36 9
A18 10UF
36 9 CPU_DATA<60> R9 D60 36 8 L3_DATA<48> L3D48 ADJ 2 39 LT1962_L3_ADJ 20%
6.3V
G14 NO STUFF NC 6 NC 2 CERM
CPU_DATA<61> AA9 D61 36 8 L3_DATA<49> L3D49
36 9
CPU_DATA<62> AB8 D62 36 8 L3_DATA<50> E15 L3D50
1 C659 BYP 3 LT1962_L3_BYP 1
NO STUFF 805
36 9
C16 1UF R644
36 9 CPU_DATA<63> W9 D63 36 8 L3_DATA<51> L3D51 20% 5 SHDN GND 4 68.1K
36 8 L3_DATA<52> A17 L3D52 2 10V
CERM 1%
603 1/16W
L3_DATA<53> A16 L3D53
NC AA2 DP0 36 8 MF
L3_DATA<54> C15 L3D54 2 402
NC AB3 DP1 36 8
AB2 DP2 36 8 L3_DATA<55> G13 L3D55
NC
AA8 DP3 36 8 L3_DATA<56> C14 L3D56
NC
R8 DP4 36 8 L3_DATA<57> A14 L3D57
NC
W5 DP5 36 8 L3_DATA<58> E13 L3D58
NC
U8 DP6 36 8 L3_DATA<59> C13 L3D59
NC
AB5 DP7 36 8 L3_DATA<60> G12 L3D60
NC
36 8 L3_DATA<61> A13 L3D61
36 8 L3_DATA<62> E12 L3D62
36 8 L3_DATA<63> C12 L3D63
MPC7450 - L3
A NC AB19
NC AA22
L3DP0
L3DP1 NOTICE OF PROPRIETARY PROPERTY
A
NC P22 L3DP2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
NC P16 L3DP3 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
NC C20 L3DP4
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NC E16 L3DP5
II NOT TO REPRODUCE OR COPY IT
NC A15 L3DP6
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
NC A12 L3DP7
SIZE DRAWING NUMBER REV.
GND
D 051-6469 F
A22
B12
B14
B16
B18
B20
C21
D13
D15
D17
D19
E21
F12
F14
F16
F19
G17
G21
H13
H15
H19
J17
J21
K19
L17
L21
M19
N17
N21
P19
R17
R21
T15
T19
U17
U21
V19
W17
W21
AB22
APPLE COMPUTER INC.
SCALE SHT OF
NONE 6 44
8 7 6 5 4 3 2 1
CR-7
8 7 6 5 4 3 2 1
CPU FREQUENCY CONFIGURATION
CPU PLL CONFIG CIRCUITRY
APOLLO REV 3.0
38 34 23 17 16 9 7 5 MAXBUS_SLEEP PLL SPEED BASED ON 167MHZ - 1GHZ/667MHZ
CORE FREQUENCY
MULTIPLIER (AT BUS FREQUENCY) CPU_PLL_CFG
1
R527 1
R513 1
R523 1
R514 1
R508 167MHZ 133MHZ
10K 10K 10K 10K 10K
D 5%
1/16W
MF
5%
1/16W
MF
5%
1/16W
MF
5%
1/16W
MF
5%
1/16W
MF
(Bus-to-Core) (MHZ) E ABCD HEX D
2 402 2 402 2 402 2 402 2 402
CPU_PLL_CFG<0> 5
0.0X PLL OFF 0 1111 0F
CPU_PLL_CFG<1>
CPU_PLL_CFG<2>
5
5
1.0X PLL BYPASS 0 0011 03
CPU_PLL_CFG<3>
CPU_PLL_CFGEXT
5
5
2.0X 333 267 0 0100 04
R01A R00A R10A R01B R00B R10B R01C R00C R10C R01D R00D R10D R01E R00E R10E 3.0X 500 400 0 1000 08
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4.0X 667 533 0 1010 0A
R526 R525 R524 R510 R511 R512 R522 R521 R520 R515 R517 R516 R505 R506 R507
+3V_SLEEP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5.0X 833 667 0 1011 0B
5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF
2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 5.5X 917 733 0 1001 09
CPU_PLL_FS01
1
R535 R538 1 1
R536Q26 6.0X 1000 800 0 1101 0D
47K 47K 10K
5% 5% 5% 2N7002 3
1/16W
MF
1/16W
MF
1/16W
MF
SM
D
6.5X 1083 867 0 0101 05
2 402 402 2 2 402
1 G S
7.0X 1167 933 0 0010 02
2 7.5X 1250 1000 0 0001 01
CPU_PLL_FS00
8.0X 1333 1067 0 1100 0C
6
8.5X 1417 1133 0 0110 06 C
C PLL_STOP_L
D
Q28
2N7002DW
2 G S
SOT-363 9.0X 1500 1200 1 0111 17
Q28
2N7002DW
SOT-363 3 1 9.5X 1583 1267 0 0111 07
D CPU_PLL_FS10
10.0X 1667 1333 1 1010 1A
CPU_PLL_STOP_OC 5 G S CPU_PLL_STOP_BASE
30
3 10.5X 1750 1400 1 1000 18
4 R541
360K 2
1 1 Q25 STATE ENCODING CPU_PLL_STOP_OC CPU_VCORE_HI_OC 11.0X 1833 1467 1 1001 19
5% 2N3904
1/16W SM
MF
402
2 LOW SPEED 0 0 11.5X 1917 1533 0 0000 00
HIGH SPEED 0 1 12.0X 2000 1600 1 1011 1B
PLL DISABLE 1 X
34 30 CPU_VCORE_HI_OC
12.5X 2083 1667 1 1111 1F
13.0X 2167 1733 1 0101 15
CPU CONFIGURATION 13.5X
14.0X
2250
2333
1800
1867
0
1
1110 0E
1100 1C
MAXBUS VSEL 15.0X 2500 2000 1 0001 11
BUSTYPE SELECT
16.0X 2667 2133 1 1101 1D
B 1_5V_MAXBUS
R6 R519 B
22 2
22 1
17.0X 2833 2267 1 0000 10
2 1 CPU_HRESET_INV 5 CPU_EMODE0_L CPU_HRESET_L 5 7 23 39
7
5%
1/16W 1.5V INTERFACE
5%
1/16W 18.0X 3000 2400 1 0010 12
MF MF
402 402
20.0X 3333 2667 1 0011 13
APOLLO ONLY SUPPORTS MAXBUS
21.0X 3500 2800 1 0100 14
INVERTED HRESET_L 5 CPU_BUS_VSEL
24.0X 4000 3200 1 0110 16
38 34 23 17 16 9 7 5 MAXBUS_SLEEP
1_8V_MAXBUS
28.0X 4667 3733 1 1110 1E
R5091
10
NO STUFF 5% 1.8V INTERFACE
1/16W
MF
5
U1 402 2
SN74AUC1G04
39 23 7 5 CPU_HRESET_L 2 4 CPU_HRESET_INV 7
04
SC70-5
3 SIGNAL TIED APPLICATION
L3 VSEL CPU_EMODE0_L HIGH 60X BUS MODE
(PROCESSOR)
NO STUFF CPU_HRESET_L MAX BUS MODE
R14 CPU_HRESET_L 2.5V INTERFACE
22
DESKTOP HAD PROBLEM USING 2
5%
1 CPU_HRESET_INV
1.5V INTERFACE
7
CPU_BUS_VSEL
(PROCESSOR)
LOW 1.8V INTERFACE CPU CONFIGURATION
A INVERTER TO INVERT HRESET_L 1/16W
MF
402
CPU_HRESET_INV 1.5V INTERFACE
NOTICE OF PROPRIETARY PROPERTY
A
NEED TO CHARACTERIZE NO STUFF CPU_HRESET_L or INT. PU 2.5V INTERFACE
CPU_L3_VSEL THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
R529 (PROCESSOR) LOW 1.8V INTERFACE PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
2
22 1
AGREES TO THE FOLLOWING
6 CPU_L3_VSEL CPU_HRESET_L 5 7 23 39
CPU_HRESET_INV 1.5V INTERFACE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5%
1/16W 2.5V INTERFACE II NOT TO REPRODUCE OR COPY IT
MF
1 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
R528 402
10 SIZE DRAWING NUMBER REV.
5%
1/16W
MF
402 2 1.8V INTERFACE D 051-6469 F
APPLE COMPUTER INC.
SCALE SHT OF
NONE 7 44
8 7 6 5 4 3 2 1
CR-8
8 7 6 5 4 3 2 1
+2_5V_SLEEP +2_5V_SLEEP
L3_OVDD L3_OVDD 6 8 38
6 8 38
F5
F7
G5
G7
H5
H7
J5
J7
K5
K7
E4
E8
F4
F8
G4
G8
H3
H4
H8
H9
J4
J8
K4
K8
L4
L8
RP45
F5
F7
G5
G7
H5
H7
J5
J7
K5
K7
E4
E8
F4
F8
G4
G8
H3
H4
H8
H9
J4
J8
K4
K8
L4
L8
10K VDD VDDQ
VDD VDDQ 36 8 6 L3_ADDR<0> C6 SA0 K B6 L3_CLK<1> 6 36
5% C6 B6
1 8 L3_DQPA<0> 8
36 8 6 L3_ADDR<0> SA0 K L3_CLK<0> 6 36
36 8 6 L3_ADDR<1> C7 SA1 CRITICAL
K* A6 L3_CLK_REF 8 38
L3_ADDR<1> C7 SA1 CRITICAL K* A6 L3_CLK_REF B4 H11
2 7 36 8 6 8 38 L3_ADDR<12> SA2 ZQ L3_ZQ<1>
4 5
L3_DQPB<0>
L3_DQPC<0>
8
8
36 8 6 L3_ADDR<12> B4 SA2
U7 ZQ H11 L3_ZQ<0>
36 8
36 8
6
6 L3_ADDR<11> B8 SA3
U6 P10
DQ0
D 3 6 L3_DQPD<0> 8
36 8
36 8
6
6
L3_ADDR<11>
L3_ADDR<13>
B8
C5
SA3
SA4
300MHZ-128KX36 DQ0 P10 L3_DATA<5> 6 36
1
R616 36 8 6 L3_ADDR<13>
L3_ADDR<10>
C5
N6
SA4
SA5
300MHZ-128KX36
BGA DQ1 P11
L3_DATA<35>
L3_DATA<40>
6
6
36
36
1
R617
249
D
1/16W
N6
BGA DQ1 P11 L3_DATA<1> 6 36 249 36 8 6
DQ2 N11 L3_DATA<42> 6 36 1%
SM1 36 8 6 L3_ADDR<10> SA5 N11
1% 36 8 6 L3_ADDR<7> P4 SA6 1/16W
P4 DQ2 L3_DATA<0> 6 36 1/16W
DQ3 M10 L3_DATA<49> 6 36 MF
36 8 6 L3_ADDR<7> SA6 MF L3_ADDR<6> P5 SA7
DQ3 M10 L3_DATA<6> 6 36
2 402
36 8 6
M11 2 402
36 8 6 L3_ADDR<6> P5 SA7 P7 DQ4 L3_DATA<55> 6 36
DQ4 M11 L3_DATA<4> 6 36
36 8 6 L3_ADDR<8> SA8 L11
L3_ADDR<8> P7 SA8 DQ5 L3_DATA<60> 6 36
RP46 36 8 6
P8 DQ5 L11 L3_DATA<3> 6 36
36 8 6 L3_ADDR<16> P8 SA9
DQ6 K10 L3_DATA<43> 6 36
10K Addr lines swappable 36 8 6 L3_ADDR<16> SA9 K10 36 8 6 L3_ADDR<14> A9 SA10
A9 DQ6 L3_DATA<9> 6 36
DQ7 K11 L3_DATA<50>
5% within a SRAM (except 36 8 6 L3_ADDR<14> SA10 K11 36 8 6 L3_ADDR<5> R4 SA11
6 36
1 8 R4 DQ7 L3_DATA<2> 6 36
DQ8 J11 L3_DATA<62> 6 36
L3_DQPA<1> 8 ADDR<0..1>) 36 8 6 L3_ADDR<5> SA11 J11 36 8 6 L3_ADDR<3> R5 SA12
2 7 R5 DQ8 L3_DATA<7> 6 36
DQ9 J10 L3_DATA<58> 6 36
L3_DQPB<1> 8 36 8 6 L3_ADDR<3> SA12 J10 36 8 6 L3_ADDR<4> R7 SA13
4 5 R7 DQ9 L3_DATA<14> 6 36
DQ10 G11 L3_DATA<51> 6 36
L3_DQPC<1> 8 36 8 6 L3_ADDR<4> SA13 G11 L3_ADDR<9> R8 SA14
3 6 R8 DQ10 L3_DATA<11> 6 36
36 8 6
DQ11 F11 L3_DATA<54> 6 36
L3_DQPD<1> 8 36 8 6 L3_ADDR<9> SA14 F11 36 8 6 L3_ADDR<2> R9 SA15
1/16W R9 DQ11 L3_DATA<24> 6 36
DQ12 E10 L3_DATA<56> 6 36
36 8 6 L3_ADDR<2> SA15 E10 Data lines swappable 36 8 6 L3_ADDR<15> A3 SA16
SM1 A3 DQ12 L3_DATA<29> 6 36
DQ13 E11 L3_DATA<59> 6 36
36 8 6 L3_ADDR<15> SA16 E11 within a SRAM 36 8 6 L3_ADDR<17> R3 NC/SA17 BALL R3 IS NC ON 4MBIT PART Data lines swappable
R3 DQ13 L3_DATA<16> 6 36
DQ14 D11 L3_DATA<63>
36 8 6 L3_ADDR<17> NC/SA17 BALL R3 IS NC ON 4MBIT PART
D11
HAVE TO CONNECT L3_ADDR17 TO THIS PIN 6 36
within a SRAM
HAVE TO CONNECT L3_ADDR17 TO THIS PIN DQ14 L3_DATA<18> 6 36 L3_PULLDOWN<1> R6 LBO* DQ15 C10 L3_DATA<53>
R624 8 L3_PULLDOWN<0> R6 LBO* DQ15 C10 L3_DATA<21> 6 36
8
DQ16 C11 L3_DATA<57>
6 36
1
470 2 C11 36 8 6 L3_CNTL<0> A4 B1
6 36
L3_PULLDOWN<0> 8
A4 DQ16 L3_DATA<20> 6 36
DQ17 B11 L3_DATA<61> 6 36
36 8 6 L3_CNTL<0> B1 B11 L3_CNTL<1> A8 B2
5%
A8 DQ17 L3_DATA<31> 6 36
36 8 6
DQ18 B3 L3_DATA<52>
1/16W
MF R625 36 8 6 L3_CNTL<1> B2
DQ18 B3 L3_DATA<22> 6 36
8 L3_PULLDOWN<1> P6 B3
DQ19 B2 L3_DATA<48>
6 36
402
1
470 2
8 L3_PULLDOWN<0> P6 B3 B2
6 36
L3_PULLDOWN<1> 8 DQ19 L3_DATA<23> 6 36
8 L3_PULLDOWN<1> H1 G* DQ20 C3 L3_DATA<47> 6 36
5% 8 L3_PULLDOWN<0> H1 G* DQ20 C3 L3_DATA<17> 6 36 D3
DQ21 L3_DATA<44>
R641 1/16W
MF DQ21 D3 L3_DATA<30> 6 36
36 6 L3_ECHO_CLK<2> M2 CQ1
DQ22 D2 L3_DATA<41>
6 36
1
1K 2
402 36 6 L3_ECHO_CLK<0> M2 CQ1 D2 E2 CQ1*
6 36
JTAG_L3_TCK 8 39 DQ22 L3_DATA<19> 6 36 NC DQ23 E3 L3_DATA<39>
NC E2 CQ1* L10
6 36
5% DQ23 E3 L3_DATA<28> 6 36
36 6 L3_ECHO_CLK<3> CQ2 F3
1/16W 36 6 L3_ECHO_CLK<1> L10 CQ2 D10 DQ24 L3_DATA<46> 6 36
MF DQ24 F3 L3_DATA<25> 6 36 NC CQ2* F2
402 NC D10 CQ2* DQ25 L3_DATA<45> 6 36
DQ25 F2 L3_DATA<27> 6 36 H2 G2
38 8 L3_VREF VREF1 DQ26 L3_DATA<36> 6 36
H2 G2
C 38 8 L3_VREF
H10
VREF1
VREF2
DQ26
DQ27 G3
L3_DATA<26>
L3_DATA<15>
6
6
36
36
H10 VREF2 DQ27
DQ28
G3
J3
L3_DATA<33>
L3_DATA<38>
6
6
36
36
C
J3 39 8 JTAG_L3_TMS R10 TMS
R10 DQ28 L3_DATA<12> 6 36
DQ29 K3 L3_DATA<34> 6 36
39 8 JTAG_L3_TMS TMS K3 8 JTAG_L3_SRAM2_TDIR11 TDI
R11 DQ29 L3_DATA<8> 6 36
DQ30 L3 L3_DATA<37> 6 36
39 JTAG_L3_TDI_TP TDI L3 39 JTAG_L3_TDO_TP R1 TDO
JTAG_L3_SRAM2_TDI R1
DQ30 L3_DATA<13> 6 36
DQ31 L2 L3_DATA<32> 6 36
8 TDO L2 JTAG_L3_TCK R2 TCK
R2 DQ31 L3_DATA<10> 6 36
39 8
DQ32 M3 L3_DQPA<1> 8
39 8 JTAG_L3_TCK TCK M3
DQ32 L3_DQPA<0> 8
DQ33 N3 L3_DQPB<1> 8
DQ33 N3 L3_DQPB<0> 8 N2
A1 DQ34 L3_DQPC<1> 8
DQ34 N2 L3_DQPC<0> NC NC_A1 P3
L3 REFERENCE VOLTAGE NC
NC
A1
A2
NC_A1
NC_A2
DQ35 P3 L3_DQPD<0>
8
8 NC
A2
A5
NC_A2
DQ35
P9
L3_DQPD<1> 8
NC NC_A5 NC_P9 NC
NC A5 NC_A5 NC_P9 P9 NC A7 P2
NC NC_A7 NC_P2 NC
NC A7 NC_A7 NC_P2 P2 NC A10 P1
L3_OVDD NC NC_A10 NC_P1 NC
38 8 6 L3_OVDD 38 8 6
NC A10 NC_A10 NC_P1 P1 NC A11 N10
NC NC_A11 NC_N10 NC
NC A11 NC_A11 NC_N10 N10 NC B1 N9
NC NC_B1 NC_N9 NC
NC B1 NC_B1 NC_N9 N9 NC B5 N7
1 NC NC_B5 NC_N7 NC
R645 1
R628 NC B5 NC_B5 NC_N7 N7 NC
NC
B7 NC_B7 NC_N5 N5
NC
1K 1K NC B7 NC_B7 NC_N5 N5 NC B9 NC_B9 NC_N1 N1
1% 1% NC NC
1/16W NC B9 NC_B9 NC_N1 N1 NC B10 M9
MF 1/16W
MF NC NC_B10 NC_M9 NC
2 402 NC B10 NC_B10 NC_M9 M9 NC C1 M1
2 402 NC NC_C1 NC_M1 NC
NC C1 NC_C1 NC_M1 M1 NC C2 L9
NC NC_C2 NC_L9 NC
NC C2 NC_C2 NC_L9 L9 NC C9 L1
L3_VREF 8 38 L3_CLK_REF NC NC_C9 NC_L1 NC
8 38
NC C9 NC_C9 NC_L1 L1 NC D1 K9
NC NC_D1 NC_K9
NC D1 NC_D1 NC_K9 K9 D9 K2
1 SAMSUNG VERIFIED THAT ALL NC PINS ARE NC NC_D9 NC_K2 NC
R646 1 C685 1
R636 1 C660
NC D9 NC_D9 NC_K2 K2 NC
NOT CONNECTED IN THE SUBSTRATE NC
E1 NC_E1 NC_K1 K1
NC
1K 0.1UF 1K NC E1 NC_E1 NC_K1 K1 NC E9 NC_E9 NC_J9 J9
1% 20% 1% 0.1UF E9 J9
BALL F9, K9 CONNECTED TO GND NC NC
1/16W
MF
10V
2 CERM 1/16W 20%
10V
NC NC_E9 NC_J9 NC
SO BYPASS CAP CAN BE PLACED NC
F1 NC_F1 NC_J2 J2
NC
B 2 402 402
MF
2 402
2 CERM
402
NC F1
F9
NC_F1
NC_F9
NC_J2
NC_J1
J2
J1
NC
NC
DIRECTLY UNDERNEATH THE CHIPS F9
F10
NC_F9
NC_F10
NC_J1
NC_G10
J1
G10
NC B
NC NC
NC F10 NC_F10 NC_G10 G10 NC G1 G9
NC NC_G1 NC_G9 NC
NC G1 NC_G1 NC_G9 G9 NC
VSS
VSS
C4
C8
D4
D5
D6
D7
D8
E5
E6
E7
F6
G6
H6
J6
K6
L5
L6
L7
M4
M5
M6
M7
M8
N4
N8
C4
C8
D4
D5
D6
D7
D8
E5
E6
E7
F6
G6
H6
J6
K6
L5
L6
L7
M4
M5
M6
M7
M8
N4
N8
38 8 6 L3_OVDD Split caps of same value evenly between SRAM chips
Split caps of same value evenly between SRAM chips
38 8 6 L3_OVDD
+2_5V_SLEEP 1 C655 1 C650 1 C644 1 C671 1 C672
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
Split caps of same value evenly between SRAM chips 20% 20% 20% 20% 20%
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM C661 C642 1 C687 1 C684
+2_5V_SLEEP 402 402 402 402 402 10UF 10UF 2.2UF 2.2UF
20% 20% 20% 20%
6.3V 6.3V 10V 10V
2 CERM 2 CERM
1 C654 1 C663 1 C662 1 C645 1 C648 Split caps of same value evenly between SRAM chips
CERM
805
CERM
805 805 805
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
1 C649 1 C669 1 C674 1 C640 1 C641
402 402 402 402 402
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20%
C636 C686 1 C635 1 C639 10V
2 CERM 2 10V
CERM
10V
2 CERM 10V
2 CERM 10V
2 CERM
10UF 10UF 2.2UF 2.2UF 402 402 402 402 402
20% 20% 20% 20%
6.3V 6.3V 2 10V 2 10V
1 C651 1 C666 1 C664 1 C667 1 C665 CERM
805
CERM
805
CERM
805
CERM
805
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
20%
10V
2 CERM
402
20%
10V
2 CERM
402
20%
10V
2 CERM
402
1 C675 1 C630 1 C631 1 C638 1 C670 L3 CACHE
A 20%
10V
0.1UF
2 CERM
0.1UF
20%
2 10V
0.1UF
20%
10V
2 CERM
0.1UF
20%
10V
2 CERM
0.1UF
20%
10V
2 CERM NOTICE OF PROPRIETARY PROPERTY
A
CERM
402 402 402 402 402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1 C653 1 C637 1 C647 1 C652 1 C646 II NOT TO REPRODUCE OR COPY IT
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
10V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 8 44
8 7 6 5 4 3 2 1
CR-9
8 7 6 5 4 3 2 1
THE FOLLOWING STRAP BITS CAN BE
CHANGED BY SOFTWARE:
INTREPID BOOT STRAPS R178
4.7
1/
2/
3/
D47 - SELAGPSPREADCLK - SLEEP/WAKE CYCLE REQUIRED
D46 - SELPCI1SPREADCLK - SLEEP/WAKE CYCLE REQUIRED
D44 - PLL4MODESEL_NXT<0> - SLEEP/WAKE CYCLE REQUIRED
+1_5V_INTREPID_PLL 1 2 38 +1_5V_INTREPID_PLL7
38 15 13
4/ D43 - PLL4MODESEL_NXT<1> - SLEEP/WAKE CYCLE REQUIRED
MAXBUS_SLEEP 5% 5/ D42 - PLL4MODESEL_NXT<2> - SLEEP/WAKE CYCLE REQUIRED
38 34 23 17 16 9 7 5
BIT 32 TO 39 C291 1
1/16W
MF 6/ D33 - ANALYZERCLK_EN_H - IMMEDIATE EFFECT MAXBUS PULL-UPS MAXBUS_SLEEP 5 7 9 16 17 23 34 38
402
0.22UF IF A STRAP IS NOT LISTED, THEN
20%
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
6.3V 2
CERM H26 IT CANNOT BE CHANGED BY SOFTWARE RP22
402
VDD15A_7 10K
R5571 R96 1
R87 R1111 R1211 R1341 R5651 R1331
1
(PLL6) 36 9 5 CPU_TS_L 2 7
10K 10K 10K 10K 10K 10K 10K 10K 5%
RP22
5% 5% 5% 5% 5% 5% 5% 5% CRITICAL 1/16W
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W D10 SM1 10K
D MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
CPU_BR_L E29
U44 D_0
D_1 G12
CPU_DATA<0>
CPU_DATA<1>
6
6
36
36
36 9 5 CPU_TA_L 1 8
D
CPU_DATA<32>
36 9 5
E26
BR INPUT
INTREPID-REV2.1 D_2 E11 CPU_DATA<2> 6 36 RP22 5%
1/16W
36 9 6
36 9 5 CPU_BG_L BG NO BUS KEEPER BGA H11 CPU_DATA<3>
10K SM1
36 9 6 CPU_DATA<33> D_3 6 36
36 9 5 CPU_ARTRY_L 4 5
B9 CPU_DATA<4>
CPU_DATA<34> D_4 6 36
36 9 6
D_5 B8 CPU_DATA<5> 6 36
5%
1/16W RP24
36 9 6 CPU_DATA<35>
36 9 5 CPU_TS_L B27 TS NO BUS KEEPER A9
SM1 10K
CPU_DATA<6> CPU_BR_L 1 8
36 9 6 CPU_DATA<36> (1 OF 9)
D_6 6 36 36 9 5
CPU_ADDR<0> D24 A8 CPU_DATA<7>
CPU_DATA<37> 36 5 A_0 D_7 6 36 5%
36 9 6
36 5 CPU_ADDR<1> D25
A_1 D_8 E12 CPU_DATA<8> 6 36
RP25 1/16W
SM1
36 9 6 CPU_DATA<38>
A27
10K
36 5 CPU_ADDR<2> A_2 D_9 D11 CPU_DATA<9> 6 36 36 9 5 CPU_HIT_L 3 6
36 9 6 CPU_DATA<39>
CPU_ADDR<3> E24 B10 CPU_DATA<10>
36 5
G23
A_3 D_10
J13
6 36 5%
1/16W RP24
R971 R5581 R5541 R5711 R5781 R5861 R1031 R5871 36 5 CPU_ADDR<4> A_4 D_11 CPU_DATA<11> 6 36 SM1 10K
B26 A10 36 9 5 CPU_DRDY_L 3 6
10K 10K 10K 10K 10K 10K 10K 10K 36 5 CPU_ADDR<5> A_5 D_12 CPU_DATA<12> 6 36
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W 36 5 CPU_ADDR<6> A26
A_6 D_13 D12 CPU_DATA<13> 6 36 RP24 5%
1/16W
MF MF MF MF MF MF MF MF 36 5 CPU_ADDR<7> D23
A_7 D_14 E13 CPU_DATA<14> 6 36 10K SM1
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 36 9 5 CPU_TEA_L 4 5
CPU_ADDR<8> A25 G13 CPU_DATA<15>
36 5 A_8 D_15 6 36
36 5 CPU_ADDR<9> E23 A_9 D_16 B11 CPU_DATA<16> 6 36
5%
1/16W RP24
10K
1: TDI output
0: TDI input (JTAG)
DDR_TPDModeEnable_h
SM1
1: Active
0: Inactive
AnalyzerClk_En_h
1: Active low
0: Active high
DDR_TPDEn_Pol
1: Active low
0: Active high
ExtPLL_SDwn_Pol
Spare
Spare
Spare
Spare
CPU_ADDR<10> J22 D13 CPU_DATA<17>
36 5 A_10 D_17 6 36
36 9 5 CPU_AACK_L 2 7
CPU_ADDR<11> B25 A11 CPU_DATA<18>
36 5 A_11 D_18 6 36
5%
36 5 CPU_ADDR<12> H22
A_12
MAXBUS
D_19 G14 CPU_DATA<19> 6 36 RP25 1/16W
SM1
CPU_ADDR<13> G22 INTERFACE H14 CPU_DATA<20>
10K
36 5 A_13 D_20 6 36
36 9 5 CPU_DBG_L 4 5
CPU_ADDR<14> D22 E14 CPU_DATA<21>
36 5 A_14 D_21 6 36
5%
36 5 CPU_ADDR<15> B24
A_15 D_22 B12 CPU_DATA<22> 6 36
1/16W
SM1
RP22
CPU_ADDR<16> B23 G15 CPU_DATA<23>
10K
36 5 A_16 D_23 6 36
36 9 5 CPU_BG_L 3 6
CPU_ADDR<17> E22 B13 CPU_DATA<24>
36 5 A_17 D_24 6 36
5%
38 34 23 17 16 9 7 5 MAXBUS_SLEEP
BIT 40 TO 47 36 5 CPU_ADDR<18> J21
A_18 D_25 H15 CPU_DATA<25> 6 36 RP25 1/16W
SM1
CPU_ADDR<19> G21 D14 CPU_DATA<26>
10K
36 5 A_19 D_26 6 36
36 9 5 CPU_QREQ_L 2 7
C NO STUFF
1
NO STUFF
1
NO STUFF
1
NO STUFF
1
NO STUFF
1
NO_SSCG
1 1 1
36 5 CPU_ADDR<20>
CPU_ADDR<21>
E21
A24
A_20
A_21
D_27
D_28
B14
A12
CPU_DATA<27>
CPU_DATA<28>
6 36
5%
1/16W
C
R86 R102 R119 R95 R139 R132 R110 R120 36 5
CPU_ADDR<22> D21 G16 CPU_DATA<29>
6 36
SM1
10K 10K 10K 10K 10K 10K 10K 10K 36 5 A_22 D_29 6 36
5% 5% 5% 5% 5% 5% 5% 5% 36 5 CPU_ADDR<23> A23 A_23 D_30 E15 CPU_DATA<30> 6 36
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
MF MF MF MF MF MF MF MF CPU_ADDR<24> H20 J16 CPU_DATA<31>
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 36 5 A_24 D_31 6 36
CPU_ADDR<25> B22 D15 CPU_DATA<32>
36 5 A_25 D_32 6 9 36
36 9 6 CPU_DATA<40> CPU_ADDR<26> H21 A14 CPU_DATA<33>
36 5 A_26 D_33 6 9 36
36 9 6 CPU_DATA<41> CPU_ADDR<27> A22 A13 CPU_DATA<34>
36 5 A_27 D_34 6 9 36
36 9 6 CPU_DATA<42> CPU_ADDR<28> E20 D16 CPU_DATA<35>
36 5 A_28 D_35 6 9 36
CPU_DATA<43> B21 E16
36 9
36 9
36 9
6
6
CPU_DATA<44>
CPU_DATA<45>
36 5
36 5
CPU_ADDR<29>
CPU_ADDR<30> D20
A21
A_29
A_30
D_36
D_37 G17
B15
CPU_DATA<36>
CPU_DATA<37>
6
6
9
9
36
36
38 34 23 17 16 9 7 5 MAXBUS_SLEEP
INTREPID BOOT STRAPS
36 5 CPU_ADDR<31> A_31 D_38 CPU_DATA<38> 6 9 36
36 9 6 CPU_DATA<46>
CPU_DATA<47> 36 5 CPU_CI_L G26
CI
D_39 H17 CPU_DATA<39> 6 9 36 BIT 56 TO 63
36 9 6 A15 CPU_DATA<40>
CPU_GBL_L A29 D_40 6 9 36
SSCG NO STUFF NO STUFF 36 5 GBL B16 CPU_DATA<41>
CPU_TBST_L A28 D_41 6 9 36
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
TBST
R5551 R5661 R5791 R5591 R5951 R5881 R572 R580 1 1 36 5
CPU_TSIZ<0> G24 TSIZ_0
D_42 E17 CPU_DATA<42> 6 9 36
R1001 R1161 R1301 R93 1
R92 R1081 R1291 R1371
1
10K 10K 10K 10K 10K 10K 10K 10K 36 5
D_43 A16 CPU_DATA<43>
5% 5% 5% 5% 5% 5% 5% 5% 36 5 CPU_TSIZ<1> H24
TSIZ_1
6 9 36 10K 10K 10K 10K 10K 10K 10K 10K
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W J18 CPU_DATA<44> 5% 5% 5% 5% 5% 5% 5% 5%
MF MF MF MF MF MF MF MF CPU_TSIZ<2> D26 D_44 6 9 36
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 36 5 TSIZ_2 H18 CPU_DATA<45> MF MF MF MF MF MF MF MF
CPU_TT<0> E25 D_45 6 9 36
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2
36 5 TT_0 D17 CPU_DATA<46>
CPU_TT<1> G25 D_46 6 9 36
36 5 TT_1 G18 CPU_DATA<47> 36 9 6 CPU_DATA<56>
BIT2 BIT1 BIT0 D_47 6 9 36
Spare
Spare
1: Active
0: Inactive
InternalSpreadEn
0: PLL5 (NO SPREAD)
1: PLL4
PCI1 Source Clock
0: PLL5 (NO SPREAD)
1: PLL4
PCI0 Source Clock
CPU_TT<2> B28
36 5 TT_2 A17 CPU_DATA<48> 36 9 6 CPU_DATA<57>
CPU_TT<3> D27 D_48 6 9 36
PLL4MODESEL_NXT[2:0] 36 5 TT_3 B17 CPU_DATA<49> 36 9 6 CPU_DATA<58>
CPU_TT<4> J25 D_49 6 9 36
000: 166.4MHZ (2.5X) 36 5 TT_4 E18 CPU_DATA<50> 36 9 6 CPU_DATA<59>
001: 149.76MHZ CPU_WT_L D28 D_50 6 9 36
36 5 WT B18 CPU_DATA<51> 36 9 6 CPU_DATA<60>
010: 133.12MHZ (2.0X) D_51 6 9 36
011: 99.84MHZ (1.5X) CPU_AACK_L B29 D18 CPU_DATA<52> 36 9 6 CPU_DATA<61>
36 9 5 AACK NO BUS KEEPER - PU D_52 6 9 36
100: 83.20MHZ H23 ARTRY A18 CPU_DATA<62>
B MODE A (2.5X) IS FOR STATIC OPERATION
MODE C (2.0X) IS FOR CLOCK SLEW OPERATION
36 9
36 9
5
5
CPU_ARTRY_L
CPU_HIT_L B31
HIT
NO BUS KEEPER - PU
INPUT - PU
D_53
D_54 A19
CPU_DATA<53>
CPU_DATA<54>
6
6
9
9
36
36
36 9
36 9
6
6 CPU_DATA<63> B
H19 CPU_DATA<55> NO STUFF
D_55 6 9 36
1 1 1 1 1 1 1 1
CPU_QREQ_L A32 QREQ
D_56 B19 CPU_DATA<56> 6 9 36 R568 R583 R590 R561 R562 R574 R591 R597
36 9 5 INPUT - PD
D_57 J19 CPU_DATA<57> 6 9 36
10K 10K 10K 10K 10K 10K 10K 10K
38 34 23 17 16 9 7 5 MAXBUS_SLEEP 5% 5% 5% 5% 5% 5% 5% 5%
A20 CPU_DATA<58> 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
D_58
BIT 48 TO 55 36 5 CPU_QACK_L G27
QACK NO BUS KEEPER - ?
D_59 D19 CPU_DATA<59>
6
6
9
9
36
36
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
MF
402 2
INT_SUSPEND_REQ_L AK9
30 SUSPENDREQ E19 CPU_DATA<60>
INT_SUSPEND_ACK_L AM8 D_60 6 9 36
SSCG SSCG NO STUFF NO STUFF NO STUFF NO STUFF 30 SUSPENDACK G19
1: GPIOs
0: REQ/GNT
PCI1_REQ2_L / PCI1_GNT2_L
1: GPIOs
0: REQ/GNT
PCI1_REQ1_L / PCI1_GNT1_L
1: GPIOs
0: REQ/GNT
PCI1_REQ0_L / PCI1_GNT0_L
D_61 CPU_DATA<61> 6 9 36
Spare
Spare
Spare
1: B-mode interface
0: Legacy interface
FireWire PHY interface
1: 60x bus (G3)
0: Max Bus (G4)
Processor Bus Mode
1
R94 R851 R1181 R109 R117 R101 R1381 R131 1 1 1 1
FB BUFFER HAS 50 OHM OUTPUT IMPEDANCE Vin = Intrepid Vcore (1.5V) D_62 B20 CPU_DATA<62> 6 9 36
10K 10K 10K 10K 10K 10K 10K 10K G20 CPU_DATA<63>
5% 5% 5% 5% 5% 5% 5% 5%
INT_CPUFB_IN J24 Vout = MaxBus rail (1.8V) D_63 6 9 36
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 36 9 CPU_FB_IN
MF MF MF MF MF MF MF MF H16 A30
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 INT_CPUFB_OUT CPU_FB_OUT DBG CPU_DBG_L
R1521 36 9
SYSCLK_LA_TP G8
NO BUS KEEPER - PU 5 9 36
CPU_DATA<48> 511 ANALYZER_CLK
36 9 6
1% G28 CPU_DRDY_L
CPU_DATA<49> 1/16W INPUT - PU DRDY 5 9 36
36 9 6
MF CPU_CLK_EN AH9
CPU_DATA<50> 402 2 30 STOPCPUCLK
36 9 6
K25 CPU_DTI<0>
CPU_DATA<51>
NO BUS KEEPER - ? DTI_0 5 36
36 9 6
INTREPID_ACS_REF H13 D29 CPU_DTI<1>
ACS_REF NO BUS KEEPER - ? DTI_1 5 36
36 9 6 CPU_DATA<52>
R104 NO BUS KEEPER - ? DTI_2 B30 CPU_DTI<2> 5 36
36 9 6 CPU_DATA<53>
SYSCLK_CPU 1
0 2 SYSCLK_CPU_UF J15
CPU_DATA<54>
36 5 36 CPU_CLK NO BUS KEEPER - PU E27 CPU_TA_L
36 9 6
5%
TA 5 9 36
CPU_DATA<55> 1/16W NO BUS KEEPER - PU E28 CPU_TEA_L
36 9 6
MF
TEA 5 9 36
INTREPID OUTPUTS HIGH BY DEFAULT
NO_SSCG NO_SSCG NO STUFF NO STUFF 402
CPU_TBEN A31 VSSA_7
1 1 1 1 1 1 1 1 1 5 TBEN
R560 R556 R582 R573 R581 R567 R596 R589 R98 NO BUS KEEPER - PU (PLL6)
10K 10K 10K 10K 10K 10K 10K 10K 1K H25
5% 5% 5% 5% 5% 5% 5% 5% 1%
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2
1/16W
MF
402 2 Intrepid MaxBus
A SHORT = 1" SHORTER THAN MATCHED LENGTH
LONG = 1" LONGER THAN MATCHED LENGTH
NO STUFF NOTICE OF PROPRIETARY PROPERTY
A
1: Active
0: Inactive
BUF_REF_CLK_OUTEnable_h
1: External source
0: PLL5
SelPLL4ExtSrc
Spare
1: TI PHY workaround
0: Normal 1394b
TI 1394b workaround
Spare
BIT2 BIT1 BIT0
R122 R168 R161 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MaxBus output impedance 2
0 1 1
0 2 1
0 2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
36 9 INT_CPUFB_OUT 36 INT_CPUFB_OUT_SHORT 36 INT_CPUFB_OUT_NORM 36 INT_CPUFB_LONG
AGREES TO THE FOLLOWING
111: 28.6 ohm 5% 5% 5%
1/16W 1/16W 1/16W I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
011: 33.3 ohm MF NO STUFF MF MF
101: 40 ohm
402
R1761 402 R1621 402 II NOT TO REPRODUCE OR COPY IT
0 0 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
001: 50 ohm 5% 5% NO STUFF
1/16W 1/16W
110: 66.6 ohm MF SIZE DRAWING NUMBER REV.
MF R177 402 2 R151
010: 100 ohm
100: 200 ohm 36 9 INT_CPUFB_IN
402 2
1
0 2 36 INT_CPUFB_IN_NORM 1
0 2
APPLE COMPUTER INC.
D 051-6469 F
5% 5%
000: 200 ohm 1/16W 1/16W SCALE SHT OF
MF
402
MF
402 NONE 9 44
8 7 6 5 4 3 2 1
CR-10
8 7 6 5 4 3 2 1
SERIES RESISTORS FOR CLOCK/CONTROL SIGNALS RP31
4
22 5
36 10 SYSCLK_DDRCLK_A1_UF SYSCLK_DDRCLK_A1 12 36
RP31 5%
1/16W
22
PINS ARE SWAPABLE FOR RPAKS 36 10 SYSCLK_DDRCLK_A1_L_UF 3 6
SM1
SYSCLK_DDRCLK_A1_L 12 36
5%
1/16W RP32
DDR_A_0 H35 MEM_ADDR<0> 10 36
36 10 SYSCLK_DDRCLK_A0_UF
SM1
RP32
1
22
5%
8 SYSCLK_DDRCLK_A0 12 36
1MB BOOT ROM
CLOCKS
MEM_DATA<0> AK32 1/16W
36 11 DDR_DATA_0 G35 SM1
MEM_DATA<1> AK33 DDR_A_1 MEM_ADDR<1> 10 36 22
36 11 DDR_DATA_1 2 7
D 36 11 MEM_DATA<2> AK31
DDR_DATA_2
CRITICAL DDR_A_2
DDR_A_3
G36
F36
MEM_ADDR<2>
MEM_ADDR<3>
10 36
36 10 SYSCLK_DDRCLK_A0_L_UF
5%
SYSCLK_DDRCLK_A0_L 12 36
+3V_MAIN D
36 11 MEM_DATA<3> AK35
DDR_DATA_3 U44 F35 MEM_ADDR<4>
10 36
1/16W
SM1 RP31
DDR_DATA_4INTREPID-REV2.1
MEM_DATA<4> AK36 DDR_A_4 10 36
22
36 11
BGA E35 MEM_ADDR<5> SYSCLK_DDRCLK_B1_UF 2 7 SYSCLK_DDRCLK_B1
MEM_DATA<5> AJ32 DDR_A_5 10 36 36 10 12 36
36 11 DDR_DATA_5 (2 OF 9) E36 MEM_ADDR<6>
36 11 MEM_DATA<6> AJ35
DDR_DATA_6
DDR_A_6
G32
10 36
RP31 5%
1/16W
DDR_A_7 MEM_ADDR<7> 22 SM1
36 11 MEM_DATA<7> AJ36
DDR_DATA_7
DDR_A_8 D36 MEM_ADDR<8>
10 36
36 10 SYSCLK_DDRCLK_B1_L_UF 1 8 SYSCLK_DDRCLK_B1_L 12 36
1 C441 1 C451 1 C459
36 11 MEM_DATA<8> AG33
DDR_DATA_8
10 36
2.2UF 0.1UF 0.1UF
DDR_A_9 H36 MEM_ADDR<9> 5% 20% 20% 20%
36 11 MEM_DATA<9> AG35
DDR_DATA_9 G33
10 36
1/16W
SM1
RP32 10V
2 CERM
10V
2 CERM
10V
2 CERM
MEM_DATA<10> AH35 DDR_A_10 MEM_ADDR<10> 10 36 22 805 402 402
36 11 DDR_DATA_10 H33 MEM_ADDR<11> 36 10 SYSCLK_DDRCLK_B0_UF 3 6 SYSCLK_DDRCLK_B0 12 36
MEM_DATA<11> AG36 DDR_A_11 10 36
36 11 DDR_DATA_11 D35 MEM_ADDR<12> 5%
36 11 MEM_DATA<12> AH36 DDR_DATA_12
DDR_A_12
L30
10 36
RP32 1/16W
SM1
MEM_DATA<13> AH32 DDR_BA_0 MEM_BA<0> 10 36 22
36 11 DDR_DATA_13 M29 MEM_BA<1> 36 10 SYSCLK_DDRCLK_B0_L_UF 4 5 SYSCLK_DDRCLK_B0_L 12 36
MEM_DATA<14> AG32 DDR_BA_1 10 36
36 11 DDR_DATA_14
36 11 MEM_DATA<15> AG31
DDR_DATA_15 DDRCS_0 AN34 MEM_CS_L<0> 10 36
5%
1/16W RP34
AE32
SM1 22 11 30 31
MEM_DATA<16> AN36 MEM_CS_L<1> MEM_CS_L<0> 1 8 RAM_CS_L<0>
36 11 DDR_DATA_16 DDRCS_1 10 36 ’0’ & ’1’ GO TO SLOT A 36 10 12 36
AF35 AL35 ’2’ & ’3’ GO TO SLOT B
36 11 MEM_DATA<17> DDR_DATA_17 DDRCS_2 MEM_CS_L<2> 10 36
RP34 5% VPP VCC
1/16W
36 11 MEM_DATA<18> AF36
DDR_DATA_18 DDRCS_3 AL33 MEM_CS_L<3> 10 36
3
22 6
SM1 U17
FEPR-1MX8
MEM_DATA<19> AE36 36 10 MEM_CS_L<1> RAM_CS_L<1> 12 36
36 11 DDR_DATA_19 DDR AJ31 3.3V
MEMORY DDR_DQS_0 MEM_DQS<0> 21 25
CS
11 36 PCI_AD<0> PCI_AD<24>
AE35 5% 39 37 26 24 18 13 13 18 24 26 37 39
36 11 MEM_DATA<20> DDR_DATA_20 INTERFACE AH31 MEM_DQS<1> 1/16W RP33 A0 TSOP DQ0
AE33 DDR_DQS_1 11 36
SM1 PCI_AD<1> 20 26 PCI_AD<25>
36 11 MEM_DATA<21> DDR_DATA_21 AD32 MEM_DQS<2>
22 39 37 26 24 18 13
A1 OMIT DQ1 13 18 24 26 37 39
AD36 DDR_DQS_2 11 36
36 10 MEM_CS_L<2> 4 5 RAM_CS_L<2> 12 36 39 37 26 24 18 13 PCI_AD<2> 19 27 PCI_AD<26> 13 18 24 26 37 39
36 11 MEM_DATA<22> DDR_DATA_22 AB30 MEM_DQS<3>
A2 DQ2
AD35 DDR_DQS_3 11 36
5% 39 37 26 24 18 13 PCI_AD<3> 18 28 PCI_AD<27> 13 18 24 26 37 39
36 11 MEM_DATA<23> DDR_DATA_23 V30 MEM_DQS<4> RP33 1/16W A3 DQ3
AA36 DDR_DQS_4 11 36
SM1 39 37 26 24 18 13 PCI_AD<4> 17 32 PCI_AD<28> 13 18 24 26 37 39
36 11 MEM_DATA<24> DDR_DATA_24 P32 MEM_DQS<5>
22 A4 DQ4
AA35 DDR_DQS_5 11 36
36 10 MEM_CS_L<3> 2 7 RAM_CS_L<3> 12 36 39 37 26 24 18 13 PCI_AD<5> 16 33 PCI_AD<29> 13 18 24 26 37 39
36 11 MEM_DATA<25> DDR_DATA_25 N29 MEM_DQS<6>
A5 DQ5
AA33 DDR_DQS_6 11 36
5% PCI_AD<6> 15 34 PCI_AD<30>
36 11 MEM_DATA<26> DDR_DATA_26 39 37 26 24 18 13
A6 DQ6 13 18 24 26 37 39
36 11 MEM_DATA<27> AB36
DDR_DATA_27
DDR_DQS_7 L32 MEM_DQS<7> 11 36
1/16W
SM1 RP34 39 37 26 24 18 13 PCI_AD<7> 14
A7 DQ7
35 PCI_AD<31> 13 18 24 26 37 39
22 PCI_AD<8> 8
AB35 AJ33 2 7
C 36 11
36 11
MEM_DATA<28>
MEM_DATA<29> AC36
DDR_DATA_28
DDR_DATA_29
DDR_DM_0
DDR_DM_1 AH33
MEM_DQM<0>
MEM_DQM<1>
11 36
11 36
36 10 MEM_CKE<0>
RP34 5%
1/16W
RAM_CKE<0> 10 12 36
39 37 26 24 18 13
39 37 26 24 18 13 PCI_AD<9> 7
A8
A9 C
AA32 AD33 PCI_AD<10> 36
36 11 MEM_DATA<30> DDR_DATA_30 DDR_DM_2 MEM_DQM<2> 11 36
4
22 5
SM1 39 37 26 24 18 13
A10
AB33 AC35 36 10 MEM_CKE<1> RAM_CKE<1> 10 12 36 39 37 26 24 18 13 PCI_AD<11> 6
36 11 MEM_DATA<31> DDR_DATA_31 DDR_DM_3 MEM_DQM<3> 11 36 A11
CKE
+3V_MAIN 5
V36 T35 5% 39 37 26 24 18 13 PCI_AD<12>
36 11 MEM_DATA<32> DDR_DATA_32 DDR_DM_4 MEM_DQM<4> 11 36
1/16W RP33 A12
U33 T33 SM1 PCI_AD<13> 4
36 11 MEM_DATA<33> DDR_DATA_33 DDR_DM_5 MEM_DQM<5> 11 36
1
22 8
39 37 26 24 18 13
A13
U32 N32 36 10 MEM_CKE<2> RAM_CKE<2> 10 12 36 39 37 26 24 18 13 PCI_AD<14> 3
36 11 MEM_DATA<34> DDR_DATA_34 DDR_DM_6 MEM_DQM<6> 11 36 A14
V35 L33 5% 39 37 26 24 18 13 PCI_AD<15> 2
36 11 MEM_DATA<35> DDR_DATA_35 DDR_DM_7 MEM_DQM<7> 11 36
RP33 1/16W A15
T30 1 1 PCI_AD<16> 1
36 11 MEM_DATA<36>
U36
DDR_DATA_36
DDRRAS L29 MEM_RAS_L 10 36 MEM_CKE<3> 3
22 6
SM1
RAM_CKE<3>
R268 R312 39 37 26 24 18 13
PCI_AD<17> 40
A16
36 11 MEM_DATA<37> DDR_DATA_37 H32 MEM_CAS_L
36 10 10 12 36
10K 10K 39 37 26 24 18 13
A17
U35 DDRCAS 10 36
5% 5% 5% 39 37 26 24 18 13 PCI_AD<18> 13
36 11 MEM_DATA<38> DDR_DATA_38 K30 MEM_WE_L 1/16W 1/16W 1/16W A18
36 11 MEM_DATA<39> T36
DDR_DATA_39
DDRWE
AN35
10 36
SM1 RP30 MF
402 2
MF
402 2 39 37 26 24 18 13 PCI_AD<19> 37
A19
P33 DDRCKE0 MEM_CKE<0> 10 36 22 PCI_AD<20> 38
36 11 MEM_DATA<40> DDR_DATA_40 AM35 MEM_CKE<1> 36 10 MEM_ADDR<0> 1 8 RAM_ADDR<0> 12 36
R280
39 37 26 24 18 13
A20
MEM_DATA<41> R30 DDRCKE1 10 36 ’0’ & ’1’ GO TO SLOT A
36 11 DDR_DATA_41 1K
MEM_DATA<42> P35 DDR_DATA_42
DDRCKE2 AM36 MEM_CKE<2> 10 36
’2’ & ’3’ GO TO SLOT B
RP26 5%
1/16W 39 24 13 ROM_CS_L 1 2 39 24 ROM_ONBOARD_CS_L 22
CE
36 11
P36 DDRCKE3 AL36 MEM_CKE<3> 10 36
1
22 8
SM1
5% ROM_OE_L 24
39 24 13
36 11 MEM_DATA<43> DDR_DATA_43 36 10 MEM_ADDR<1> RAM_ADDR<1> 12 36 1/16W OE
R36 AB32 MF 39 24 13 ROM_RW_L 9
36 11 MEM_DATA<44> DDR_DATA_44 DDR_SELHI_0 MEM_MUXSEL_H<0> 11 36 5% 402 WE
36 11 MEM_DATA<45> R35
DDR_DATA_45 DDR_SELHI_1 AE29 MEM_MUXSEL_H<1> 11 36 ’0’S ARE SAME POLARITY (ACTIVE-LO)
1/16W
SM1
RP26 ROM_WP_L 12
WP
R33 N30 ’1’S ARE SAME POLARITY (ACTIVE-HI) 2
22 7 INT_RESET_L 10
30 14
36 11 MEM_DATA<46> DDR_DATA_46 DDR_SELLO_0 MEM_MUXSEL_L<0> 11 36 36 10 MEM_ADDR<2> RAM_ADDR<2> 12 36 PWD
36 11 MEM_DATA<47> R32
DDR_DATA_47 DDR_SELLO_1 T32 MEM_MUXSEL_L<1> 11 36 5% GND
36 11 MEM_DATA<48> N35
DDR_DATA_48
RP26 1/16W
SM1
OVERRIDE ROM MODULE
INTERCEPTS ROM CHIP SELECT
DDR_MCLK_0_P Y32 SYSCLK_DDRCLK_A0_UF 10 36 22 23 39
36 11 MEM_DATA<49> M36 DDR_DATA_49 36 10 MEM_ADDR<3> 4 5 RAM_ADDR<3> 12 36
Y33 SYSCLK_DDRCLK_A0_L_UF
MEM_DATA<50> L35 DDR_MCLK_0_N 10 36
36 11 DDR_DATA_50 Y35 SYSCLK_DDRCLK_A1_UF
5%
MEM_DATA<51> M35 DDR_MCLK_1_P 10 36 1/16W
RP26
36 11 DDR_DATA_51 Y36 SM1
MEM_DATA<52> M33 DDR_MCLK_1_N SYSCLK_DDRCLK_A1_L_UF 10 36 22
36 11 DDR_DATA_52 Y30 INT_DDRCLK2_P_TP 36 10 MEM_ADDR<4> 3 6 RAM_ADDR<4> 12 36
MEM_DATA<53> L36 DDR_MCLK_2_P
36 11 DDR_DATA_53
MEM_DATA<54> N33
DDR_DATA_54
DDR_MCLK_2_N W30 INT_DDRCLK2_N_TP RP29 5%
1/16W
22
B
36 11
36 11 MEM_DATA<55> M30
J32
DDR_DATA_55
DDR_MCLK_3_P
DDR_MCLK_3_N
W32
W33
SYSCLK_DDRCLK_B0_UF
SYSCLK_DDRCLK_B0_L_UF
10 36
10 36
36 10 MEM_ADDR<5> 1 8
SM1
RAM_ADDR<5> 12 36
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD
B
36 11 MEM_DATA<56> DDR_DATA_56 5%
36 11 MEM_DATA<57> J33
DDR_DATA_57
DDR_MCLK_4_P V33 SYSCLK_DDRCLK_B1_UF 10 36 1/16W
SM1
RP29 341S1241 1 BOOTROM,P84 U17 CRITICAL ?
TABLE_5_ITEM
J35 DDR_MCLK_4_N V32 SYSCLK_DDRCLK_B1_L_UF 10 36
2
22 7
ADDR
36 11 MEM_DATA<58> DDR_DATA_58 36 10 MEM_ADDR<6> RAM_ADDR<6> 12 36
W35 INT_DDRCLK5_P_TP
MEM_DATA<59> K32 DDR_MCLK_5_P
36 11 DDR_DATA_59 5%
36 11 MEM_DATA<60> K33
DDR_DATA_60
DDR_MCLK_5_N W36 INT_DDRCLK5_N_TP RP30 1/16W
SM1
J36 AA22 3
22 6
36 11 MEM_DATA<61> DDR_DATA_61 DDR_REF INT_MEM_REF_H 38 36 10 MEM_ADDR<7> RAM_ADDR<7> 12 36
MEM_DATA<62> K36
36 11 DDR_DATA_62 5%
MEM_DATA<63> K35 DDR_DATA_63
DDR_VREF_0 Y22 INT_MEM_VREF 10 38 1/16W
SM1
RP29
36 11
DDR_VREF_1 T22
4
22 5
36 10 MEM_ADDR<8> RAM_ADDR<8> 12 36
RP30 5%
1/16W
1 22 SM1
R154 36 10 MEM_ADDR<9> 2 7 RAM_ADDR<9> 12 36
1K 5%
1%
1/16W 1/16W RP30
MF SM1 22 PULL-DOWN RESISTORS TO ENSURE
MEM_VREF 2 402 36 10 MEM_ADDR<10> 4 5 RAM_ADDR<10> 12 36
CKE STAYS LOW AFTER INTREPID
5%
RP27 1/16W
SM1 2.5V I/O SHUTS OFF
4
22 5
38 17 16 11 +2_5V_INTREPID 36 10 MEM_ADDR<11> RAM_ADDR<11> 12 36
36 12 10 RAM_CKE<0>
5%
1/16W
SM1 RP29 36 12 10 RAM_CKE<1>
3
22 6 RAM_CKE<2>
MEM_ADDR<12> RAM_ADDR<12> 12 36 36 12 10
1
R153 36 10
RAM_CKE<3>
10K
1%
RP27 5%
1/16W
36 12 10
1/16W 22 SM1
MF
402 2
36 10 MEM_BA<0> 2
5%
7 RAM_BA<0> 12 36 R7701 R7711 R7721
10K 10K 10K
R7731
10K
INT - DDR/BOOTROM
BA
A INT_MEM_VREF 10 38
1/16W
SM1
1
RP27
22 8
5%
1/16W
MF
5%
1/16W
MF
5%
1/16W
MF
5%
1/16W
MF NOTICE OF PROPRIETARY PROPERTY
A
36 10 MEM_BA<1> RAM_BA<1> 12 36 402 2 402 2 402 2 402 2
R1441 C224 1 5%
10K 0.1UF RP27 1/16W
SM1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1% 20%
10V
22 AGREES TO THE FOLLOWING
1/16W MEM_WE_L 3 6 RAM_WE_L
MF CERM 2 36 10 12 36
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
402 2 402
5%
CNTL
1/16W R199 II NOT TO REPRODUCE OR COPY IT
SM1
1
22 2
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
36 10 MEM_CAS_L RAM_CAS_L 12 36
5% SIZE DRAWING NUMBER REV.
R188 1/16W
36 10 MEM_RAS_L 1
22 2
MF
402 RAM_RAS_L 12 36
APPLE COMPUTER INC.
D 051-6469 F
5%
1/16W SCALE SHT OF
MF
402 NONE 10 44
8 7 6 5 4 3 2 1
CR-11
8 7 6 5 4 3 2 1
38 17 16 11 10 +2_5V_INTREPID
BIT 0..15 38 17 16 11 10 +2_5V_INTREPID
BIT 16..31 38 17 16 11 10 +2_5V_INTREPID
BIT 32..47 38 17 16 11 10 +2_5V_INTREPID
BIT 48..63
D D
1 C698 1 C691 1 C707 1 C699 1 C701 1 C700
1 C705 1 C711 1 C716 1 C717 1 C706 1 C712 20%
0.1UF 0.1UF
20% 20%
0.1UF 0.1UF
20% 20%
0.1UF 0.1UF
20%
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10V 10V 10V 10V 10V 10V
20% 20% 20% 20% 20% 20% 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
10V
2 CERM 2 10V 10V
2 CERM 2 10V 2 10V 10V
2 CERM 402 402 402 402 402 402
CERM CERM CERM
402 402 402 402 402 402
CRITICAL CRITICAL
E8
F3
F8
E8
F3
F8
CRITICAL
E8
F3
F8
CRITICAL
E8
F3
F8
VDD VDD
VDD 36 12 RAM_DATA_B<32> G1 DB0* DA11 C10 RAM_DATA_A<41> 12 36 36 12 RAM_DATA_B<48> G1 DB0* DA11 C10 RAM_DATA_A<57> 12 36
VDD 36 12 RAM_DATA_B<16> G1 DB0* DA11 C10 RAM_DATA_A<25> 12 36
36 12 RAM_DATA_B<0> G1 DB0* DA11 C10 RAM_DATA_A<9> 12 36 36 12 RAM_DATA_B<33> J1 DB1* DA12 A10 RAM_DATA_A<42> 12 36 36 12 RAM_DATA_B<49> J1 DB1* DA12 A10 RAM_DATA_A<58> 12 36
RAM_DATA_B<17> J1 DB1* DA12 A10 RAM_DATA_A<26>
36 12 RAM_DATA_B<1> J1 DB1* DA12 A10 RAM_DATA_A<10> 12 36
36 12
RAM_DATA_B<18> K2 DB2* U13 DA13 A8 RAM_DATA_A<27>
12 36
36 12 RAM_DATA_B<34> K2 DB2* U12 DA13 A8 RAM_DATA_A<43> 12 36 36 12 RAM_DATA_B<50> K2 DB2* U11 DA13 A8 RAM_DATA_A<59> 12 36
36 12 RAM_DATA_B<2> K2 DB2* U14 DA13 A8 RAM_DATA_A<11> 12 36
36 12
RAM_DATA_B<19> J4
CBTV4020
A7 RAM_DATA_A<28>
12 36
36 12 RAM_DATA_B<35> J4 DB3*
CBTV4020
BGA DA14 A7 RAM_DATA_A<44> 12 36 36 12 RAM_DATA_B<51> J4 DB3*
CBTV4020
BGA DA14 A7 RAM_DATA_A<60> 12 36
J4 CBTV4020 36 12 DB3* BGA DA14 12 36
36 12 RAM_DATA_B<3> DB3* BGA DA14 A7 RAM_DATA_A<12> 12 36
K5 36 12 RAM_DATA_B<36> K5 DB4* DA15 A5 RAM_DATA_A<45> 12 36 36 12 RAM_DATA_B<52> K5 DB4* DA15 A5 RAM_DATA_A<61> 12 36
K5 36 12 RAM_DATA_B<20> DB4* DA15 A5 RAM_DATA_A<29> 12 36
36 12 RAM_DATA_B<4> DB4* DA15 A5 RAM_DATA_A<13> 12 36
K7 B4 36 12 RAM_DATA_B<37> K7 DB5* DA16 B4 RAM_DATA_A<46> 12 36 36 12 RAM_DATA_B<53> K7 DB5* DA16 B4 RAM_DATA_A<62> 12 36
36 12 RAM_DATA_B<21> DB5* DA16 RAM_DATA_A<30> 12 36
36 12 RAM_DATA_B<5> K7 DB5* DA16 B4 RAM_DATA_A<14> 12 36 36 12 RAM_DATA_B<38> K8 DB6* DA17 A2 RAM_DATA_A<47> 12 36 36 12 RAM_DATA_B<54> K8 DB6* DA17 A2 RAM_DATA_A<63> 12 36
36 12 RAM_DATA_B<22> K8 DB6* DA17 A2 RAM_DATA_A<31> 12 36
36 12 RAM_DATA_B<6> K8 DB6* DA17 A2 RAM_DATA_A<15> 12 36 36 12 RAM_DATA_B<39> K10 DB7* DA18 B1 RAM_DQS_A<5> 12 36 36 12 RAM_DATA_B<55> K10 DB7* DA18 B1 RAM_DQS_A<7> 12 36
36 12 RAM_DATA_B<23> K10 DB7* DA18 B1 RAM_DQS_A<3> 12 36
36 12 RAM_DATA_B<7> K10 DB7* DA18 B1 RAM_DQS_A<1> 12 36 36 12 RAM_DQS_B<4> H10 DB8* DA19 D1 RAM_DQM_A<5> 12 36 36 12 RAM_DQS_B<6> H10 DB8* DA19 D1 RAM_DQM_A<7> 12 36
36 12 RAM_DQS_B<2> H10 DB8* DA19 D1 RAM_DQM_A<3> 12 36
36 12 RAM_DQS_B<0> H10 DB8* DA19 D1 RAM_DQM_A<1> 12 36 36 12 RAM_DQM_B<4> F10 DB9* 36 12 RAM_DQM_B<6> F10 DB9*
36 12 RAM_DQM_B<2> F10 DB9*
36 12 RAM_DQM_B<0> F10 DB9* 36 12 RAM_DATA_B<40> D10 DB10* 36 12 RAM_DATA_B<56> D10 DB10*
36 12 RAM_DATA_B<24> D10 DB10*
36 12 RAM_DATA_B<8> D10 DB10* 36 12 RAM_DATA_B<41> B10 DB11* 36 12 RAM_DATA_B<57> B10 DB11*
36 12 RAM_DATA_B<25> B10 DB11* DH0 F2 MEM_DATA<32> 10 36 DH0 F2 MEM_DATA<48> 10 36
36 12 RAM_DATA_B<9> B10 DB11* DH0 F2 MEM_DATA<16> 10 36 36 12 RAM_DATA_B<42> A9 DB12* 36 12 RAM_DATA_B<58> A9 DB12*
A9 DH0 F2 MEM_DATA<0> 10 36 36 12 RAM_DATA_B<26> A9 DB12* DH1 H2 MEM_DATA<33> 10 36 DH1 H2 MEM_DATA<49> 10 36
36 12 RAM_DATA_B<10> DB12* DH1 H2 MEM_DATA<17> 10 36 36 12 RAM_DATA_B<43> B7 DB13* 36 12 RAM_DATA_B<59> B7 DB13*
B7
DH1 H2 MEM_DATA<1> 10 36 36 12 RAM_DATA_B<27> B7 DB13* DH2 J2 MEM_DATA<34> 10 36 DH2 J2 MEM_DATA<50> 10 36
36 12 RAM_DATA_B<11> DB13* DH2 J2 MEM_DATA<18> 10 36 36 12 RAM_DATA_B<44> A6 DB14* 36 12 RAM_DATA_B<60> A6 DB14*
A6 DH2 J2 MEM_DATA<2> 10 36 36 12 RAM_DATA_B<28> A6 DB14* DH3 J3 MEM_DATA<35> 10 36 DH3 J3 MEM_DATA<51> 10 36
36 12 RAM_DATA_B<12> DB14* DH3 J3 MEM_DATA<19> 10 36 36 12 RAM_DATA_B<45> A4 DB15* 36 12 RAM_DATA_B<61> A4 DB15*
DH3 J3 A4 DH4 J5 DH4 J5
C 36 12
36 12
RAM_DATA_B<13>
RAM_DATA_B<14>
A4
A3
DB15*
DB16*
DH4 J5
MEM_DATA<3>
MEM_DATA<4>
10 36
10 36
36 12
36 12
RAM_DATA_B<29>
RAM_DATA_B<30> A3
DB15*
DB16*
DH4 J5
DH5 J6
MEM_DATA<20>
MEM_DATA<21>
10 36
10 36
36 12
36 12
RAM_DATA_B<46>
RAM_DATA_B<47>
A3
A1
DB16*
DB17*
DH5 J6
MEM_DATA<36>
MEM_DATA<37>
10 36
10 36
36 12
36 12
RAM_DATA_B<62>
RAM_DATA_B<63>
A3
A1
DB16*
DB17*
DH5 J6
MEM_DATA<52>
MEM_DATA<53>
10 36
10 36
C
A1 DH5 J6 MEM_DATA<5> 10 36 36 12 RAM_DATA_B<31> A1 DB17* DH6 J8 MEM_DATA<38> 10 36 DH6 J8 MEM_DATA<54> 10 36
36 12 RAM_DATA_B<15> DB17* DH6 J8 MEM_DATA<22> 10 36 36 12 RAM_DQS_B<5> C1 DB18* 36 12 RAM_DQS_B<7> C1 DB18*
C1
DH6 J8 MEM_DATA<6> 10 36 36 12 RAM_DQS_B<3> C1 DB18* DH7 J9 MEM_DATA<39> 10 36 DH7 J9 MEM_DATA<55> 10 36
36 12 RAM_DQS_B<1> DB18* DH7 J9 MEM_DATA<23> 10 36 36 12 RAM_DQM_B<5> E1 DB19* 36 12 RAM_DQM_B<7> E1 DB19*
E1 DH7 J9 MEM_DATA<7> 10 36 36 12 RAM_DQM_B<3> E1 DB19* DH8 H9 MEM_DQS<4> 10 36 DH8 H9 MEM_DQS<6> 10 36
36 12 RAM_DQM_B<1> DB19* DH8 H9 MEM_DQS<2> 10 36
DH8 H9 MEM_DQS<0> 10 36 DH9 F9 MEM_DQM<4> 10 36 DH9 F9 MEM_DQM<6> 10 36
DH9 F9 MEM_DQM<2> 10 36
DH9 F9 MEM_DQM<0> 10 36 DH10 E9 MEM_DATA<40> 10 36 DH10 E9 MEM_DATA<56> 10 36
DH10 E9 MEM_DATA<24> 10 36
DH10 E9 MEM_DATA<8> 10 36 DH11 C9 MEM_DATA<41> 10 36 DH11 C9 MEM_DATA<57> 10 36
DH11 C9 MEM_DATA<25> 10 36 36 12 RAM_DATA_A<32> F1 DA0 36 12 RAM_DATA_A<48> F1 DA0
F1 DA0
DH11 C9 MEM_DATA<9> 10 36 36 12 RAM_DATA_A<16> F1 DA0 DH12 B9 MEM_DATA<42> 10 36 DH12 B9 MEM_DATA<58> 10 36
36 12 RAM_DATA_A<0> DH12 B9 MEM_DATA<26> 10 36 36 12 RAM_DATA_A<33> H1 DA1 36 12 RAM_DATA_A<49> H1 DA1
H1 DA1 DH12 B9 MEM_DATA<10> 10 36 36 12 RAM_DATA_A<17> H1 DA1 DH13 B8 MEM_DATA<43> 10 36 DH13 B8 MEM_DATA<59> 10 36
36 12 RAM_DATA_A<1> DH13 B8 MEM_DATA<27> 10 36 36 12 RAM_DATA_A<34> K1 DA2 36 12 RAM_DATA_A<50> K1 DA2
K1 DA2
DH13 B8 MEM_DATA<11> 10 36 36 12 RAM_DATA_A<18> K1 DA2 DH14 B6 MEM_DATA<44> 10 36 DH14 B6 MEM_DATA<60> 10 36
36 12 RAM_DATA_A<2> DH14 B6 MEM_DATA<28> 10 36 36 12 RAM_DATA_A<35> K3 DA3 36 12 RAM_DATA_A<51> K3 DA3
K3 DA3 DH14 B6 MEM_DATA<12> 10 36 36 12 RAM_DATA_A<19> K3 DA3 DH15 B5 MEM_DATA<45> 10 36 DH15 B5 MEM_DATA<61> 10 36
36 12 RAM_DATA_A<3> DH15 B5 MEM_DATA<29> 10 36 36 12 RAM_DATA_A<36> K4 DA4 36 12 RAM_DATA_A<52> K4 DA4
K4 DA4
DH15 B5 MEM_DATA<13> 10 36 36 12 RAM_DATA_A<20> K4 DA4 DH16 B3 MEM_DATA<46> 10 36 DH16 B3 MEM_DATA<62> 10 36
36 12 RAM_DATA_A<4> DH16 B3 MEM_DATA<30> 10 36 36 12 RAM_DATA_A<37> K6 DA5 36 12 RAM_DATA_A<53> K6 DA5
K6 DA5 DH16 B3 MEM_DATA<14> 10 36 36 12 RAM_DATA_A<21> K6 DA5 DH17 B2 MEM_DATA<47> 10 36 DH17 B2 MEM_DATA<63> 10 36
36 12 RAM_DATA_A<5> DH17 B2 MEM_DATA<31> 10 36 36 12 RAM_DATA_A<38> J7 DA6 36 12 RAM_DATA_A<54> J7 DA6
J7 DA6
DH17 B2 MEM_DATA<15> 10 36 36 12 RAM_DATA_A<22> J7 DA6 DH18 C2 MEM_DQS<5> 10 36 DH18 C2 MEM_DQS<7> 10 36
36 12 RAM_DATA_A<6> DH18 C2 MEM_DQS<3> 10 36 36 12 RAM_DATA_A<39> K9 DA7 36 12 RAM_DATA_A<55> K9 DA7
K9 DA7 DH18 C2 MEM_DQS<1> 10 36 36 12 RAM_DATA_A<23> K9 DA7 DH19 E2 MEM_DQM<5> 10 36 DH19 E2 MEM_DQM<7> 10 36
36 12 RAM_DATA_A<7> DH19 E2 MEM_DQM<3> 10 36 36 12 RAM_DQS_A<4> J10 DA8 36 12 RAM_DQS_A<6> J10 DA8
J10 DA8
DH19 E2 MEM_DQM<1> 10 36 36 12 RAM_DQS_A<2> J10 DA8
G10 DA9 G10 DA9
36 12 RAM_DQS_A<0> 36 12 RAM_DQM_A<4> 36 12 RAM_DQM_A<6>
36 12 RAM_DQM_A<2> G10 DA9
36 12 RAM_DQM_A<0> G10 DA9 36 12 RAM_DATA_A<40> E10 DA10 SEL E3 RAM_MUXSEL_H 11 36 36 12 RAM_DATA_A<56> E10 DA10 SEL E3 RAM_MUXSEL_H 11 36
36 12 RAM_DATA_A<24> E10 DA10 SEL E3 RAM_MUXSEL_L 11 36
36 12 RAM_DATA_A<8> E10 DA10 SEL E3 RAM_MUXSEL_L 11 36 GND GND
GND
C5
C6
D2
D9
G2
G9
H5
H6
C5
C6
D2
D9
G2
G9
H5
H6
GND
C5
C6
D2
D9
G2
G9
H5
H6
C5
C6
D2
D9
G2
G9
H5
H6
B B
SEL = LOW; HOST = B PORT; A PORT = 100OHM TO GND
SEL = HIGH; HOST = A PORT; B PORT = 100OHM TO GND
MEM_MUXSEL_H<0> AND MEM_MUXSEL_L<0> ARE ACTIVE LOW
MEM_MUXSEL_H<1> AND MEM_MUXSEL_L<1> ARE ACTIVE HIGH
ADDED 0 OHM RESISTORS IN CASE POLARITY IS WRONG
NO STUFF
R192 R193
1
0 2 1
0 2
MEM_MUXSEL_L<0> RAM_MUXSEL_L MEM_MUXSEL_L<1> RAM_MUXSEL_L
36 10
5%
1/16W
11 36 36 10
5%
1/16W
11 36
16BIT 2:1 DDR MUXES
A MF
402
MF
402
NOTICE OF PROPRIETARY PROPERTY
A
NO STUFF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
R202 R189 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1
0 2 1
0 2
36 10 MEM_MUXSEL_H<0> RAM_MUXSEL_H 11 36 36 10 MEM_MUXSEL_H<1> RAM_MUXSEL_H 11 36
II NOT TO REPRODUCE OR COPY IT
5% 5%
1/16W 1/16W III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MF MF
402 402
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 11 44
8 7 6 5 4 3 2 1
CR-12
8 7 6 5 4 3 2 1
+2_5V_MAIN +2_5V_MAIN +2_5V_MAIN 201 CRITICAL +2_5V_MAIN
201 CRITICAL
DDR_VREF 2 1 DDR_VREF +2_5V_MAIN
DDR_VREF 1 2 DDR_VREF
38 12 VREF1 VREF0 12 38
38 12 VREF0 VREF1 12 38
4 3
3 4 VSS1 VSS0
VSS0 VSS1 6 J23 5
36 11 RAM_DATA_A<0> 5
7
DQ0 J20
AS0A42-D2S DQ4
6
8
RAM_DATA_A<4> 11 36
36 11
36 11
RAM_DATA_B<4>
RAM_DATA_B<5> 8
DQ4
DQ5
AS0A42-D2R DQ0
F-RT-SM DQ1
7
RAM_DATA_B<0>
RAM_DATA_B<1>
11 36
11 36
DDR VREF
36 11 RAM_DATA_A<1> DQ1 F-RT-SM DQ5 RAM_DATA_A<5> 11 36
10 9 1
R372 ONE 0.1UF PER SLOT
9 10 VDD1 VDD0
VDD0 VDD1
36 11 RAM_DQM_B<0> 12
DQS0
11 RAM_DQS_B<0> 11 36
1K
RAM_DQS_A<0> 11 12 RAM_DQM_A<0> DM0 1%
36 11 DQS0 DM0 11 36
RAM_DATA_B<6> 14 13 RAM_DATA_B<2> 1/16W
RAM_DATA_A<2> 13 14 RAM_DATA_A<6>
36 11
DQ6 DQ2 11 36
MF
36 11 DQ2 DQ6 11 36
16 15
15 16 VSS3 VSS2 2 402
VSS2 VSS3 RAM_DATA_B<7> 18 17 RAM_DATA_B<3> DDR_VREF
RAM_DATA_A<3> 17 18 RAM_DATA_A<7>
36 11
DQ7 DQ3 11 36 12 38
36 11 DQ3 DQ7 11 36
RAM_DATA_B<12> 20 19 RAM_DATA_B<8>
19 20 36 11
DQ12 DQ8 11 36
1
36 11 RAM_DATA_A<8> DQ8 DQ12 RAM_DATA_A<12> 11 36
22 21 R359 1 C509 1 C460
D RAM_DATA_A<9>
21
23
VDD2 VDD3
22
24 RAM_DATA_A<13>
36 11 RAM_DATA_B<13> 24
VDD3
DQ13
VDD2
DQ9
23 RAM_DATA_B<9> 11 36 1%
1K
1/16W
0.1UF
20%
0.1UF
20%
D
36 11 DQ9 DQ13 11 36
RAM_DQM_B<1> 26 25 RAM_DQS_B<1> 10V 10V
25 26 36 11 DM1 DQS1 11 36 MF 2 CERM 2 CERM
RAM_DQS_A<1> RAM_DQM_A<1>
36 11 DQS1 DM1 11 36
28 27 2 402 402 402
27 28 VSS5 VSS4
VSS4 VSS5 RAM_DATA_B<14> 30 29 RAM_DATA_B<10>
RAM_DATA_A<10> 29 30 RAM_DATA_A<14>
36 11 DQ14 DQ10 11 36
36 11 DQ10 DQ14 11 36
RAM_DATA_B<15> 32 31 RAM_DATA_B<11>
RAM_DATA_A<11> 31 32 RAM_DATA_A<15>
36 11
DQ15 DQ11 11 36
36 11 DQ11 DQ15 11 36
34 33
33 34 VDD5 VDD4
VDD4 VDD5 36 35 SYSCLK_DDRCLK_B0
SYSCLK_DDRCLK_A0 35 36 VDD6 CK0 10 36
36 10 CK0 VDD6 38 37 SYSCLK_DDRCLK_B0_L
SYSCLK_DDRCLK_A0_L 37 38 VSS6 CK0* 10 36
36 10 CK0* VSS6 40 39
39 40 VSS8 VSS7
VSS7 VSS8 KEY
KEY RAM_DATA_B<20> 42 41 RAM_DATA_B<16>
36 11 RAM_DATA_A<16>
RAM_DATA_A<17>
41
43
DQ16 DQ20
42
44
RAM_DATA_A<20>
RAM_DATA_A<21>
11 36
36 11
36 11 RAM_DATA_B<21> 44
DQ20
DQ21
DQ16
DQ17
43 RAM_DATA_B<17>
11 36
11 36
DDR BYPASS CAPS
36 11 DQ17 DQ21 11 36
46 45
45 46 VDD8 VDD7 +2_5V_MAIN
36 11 RAM_DQS_A<2> 47
VDD7
DQS2
VDD8
DM2
48 RAM_DQM_A<2> 11 36
36 11 RAM_DQM_B<2> 48
50
DM2 DQS2
47
49
RAM_DQS_B<2> 11 36 SLOT "A"
36 11 RAM_DATA_B<22> DQ18 RAM_DATA_B<18> 11 36
RAM_DATA_A<18> 49 50 RAM_DATA_A<22> DQ22
36 11 DQ18 DQ22 11 36
52 51
51 52 VSS10 VSS9
VSS9 VSS10 RAM_DATA_B<23> 54 53 RAM_DATA_B<19>
RAM_DATA_A<19> 53 54 RAM_DATA_A<23>
36 11
DQ23 DQ19 11 36
36 11 DQ19 DQ23 11 36
56 55
36 11 RAM_DATA_A<24> 55
DQ24 DQ28
56 RAM_DATA_A<28> 11 36
36 11 RAM_DATA_B<28>
58
DQ28 DQ24
57
RAM_DATA_B<24> 11 36 1 C553 1 C552
57 58 VDD10 VDD9 10UF 10UF
VDD9 VDD10 60 59 20% 20%
36 11 RAM_DATA_B<29> DQ25 RAM_DATA_B<25> 11 36 6.3V 6.3V
RAM_DATA_A<25> 59 60 RAM_DATA_A<29> DQ29 2 CERM 2 CERM
36 11 DQ25 DQ29 11 36
RAM_DQM_B<3> 62 61 RAM_DQS_B<3> 805 805
RAM_DQS_A<3> 61 62 RAM_DQM_A<3>
36 11
DM3 DQS3 11 36
36 11 DQS3 DM3 11 36
64 63
63 64 VSS12 VSS11
VSS11 VSS12 RAM_DATA_B<30> 66 65 RAM_DATA_B<26>
RAM_DATA_A<26> 65 66 RAM_DATA_A<30>
36 11
DQ30 DQ26 11 36
36 11 DQ26 DQ30 11 36
RAM_DATA_B<31> 68 67 RAM_DATA_B<27>
RAM_DATA_A<27> 67 68 RAM_DATA_A<31>
36 11
DQ31 DQ27 11 36
36 11 DQ27 DQ31 11 36
70 69
69 70 VDD12 VDD11
VDD11 VDD12 72 71
NC
71
RFU0 RFU1
72 NC NC
74
RFU1 RFU0
73
NC 1 C804 1 C808 1 C812 1 C816 1 C820
NC 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
C NC
73
75
RFU2
VSS13
RFU3
VSS14
74
76
NC NC
76
RFU3
VSS14
RFU2
VSS13
75 20%
10V
2 CERM
20%
10V
2 CERM
20%
2 10V
CERM
20%
2 10V
CERM
20%
10V
2 CERM
C
STANDARD NC
NC
77
79
81
RFU4
RFU6
RFU5
RFU7
78
80
82
NC
NC
REVERSED NC
NC
78
80
82
RFU5
RFU7
VDD14
RFU4
RFU6
VDD13
77
79
81
NC
NC
402 402 402 402 402
SLOT "A" NC
NC
83
85
VDD13
RFU8
RFU10
VDD14
RFU9
RFU11
84
86
NC
NC
SLOT "B" NC
NC
84
86
88
RFU9
RFU11
RFU8
RFU10
83
85
87
NC
NC
1 C805 1 C809 1 C813 1 C817 1 C821
VSS16 VSS15
FACTORY SLOT NC
NC
87
89
91
VSS15
RFU12
RFU13
VSS16
VSS17
VDD15
88
90
92
CUSTOMER SLOT 90
92
94
VSS17
VDD15
RFU12
RFU13
89
91
93
NC
NC
0.1UF
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
93 94 VDD17 VDD16
VDD16 VDD17 RAM_CKE<2> 96 95 RAM_CKE<3>
RAM_CKE<1> 95 96 RAM_CKE<0>
36 10
CKE0 CKE1 10 36
36 10 CKE1 CKE0 10 36
98 97
97 98 NC RFU15 RFU14 NC
NC RFU14 RFU15 NC 100 99
36 12 10 RAM_ADDR<11> A12 RAM_ADDR<12> 10 12 36
RAM_ADDR<12> 99 100 RAM_ADDR<11> A11
36 12 10 A12 A11 10 12 36
RAM_ADDR<8> 102 101 RAM_ADDR<9>
101 102 36 12 10 A8 A9 10 12 36
36 12 10 RAM_ADDR<9>
103
A9 A8
104
RAM_ADDR<8> 10 12 36
104
VSS19 VSS18
103 FOR RETURN CURRENT
VSS18 VSS19 RAM_ADDR<6> 106 105 RAM_ADDR<7>
RAM_ADDR<7> 105 106 RAM_ADDR<6>
36 12 10 A6 A7 10 12 36
36 12 10 A7 A6 10 12 36
RAM_ADDR<4> 108 107 RAM_ADDR<5>
RAM_ADDR<5> 107 108 RAM_ADDR<4>
36 12 10
A4 A5 10 12 36
36 12 10 A5 A4 10 12 36
RAM_ADDR<2> 110 109 RAM_ADDR<3>
109 110 36 12 10 A2 A3 10 12 36 +2_5V_MAIN
36 12 10
36 12 10
RAM_ADDR<3>
RAM_ADDR<1> 111
A3
A1
A2
A0
112
RAM_ADDR<2>
RAM_ADDR<0>
10 12 36
10 12 36
36 12 10 RAM_ADDR<0> 112
114
A0 A1
111
113
RAM_ADDR<1> 10 12 36 SLOT "B"
113 114 VDD19 VDD18
VDD18 VDD19 RAM_BA<1> 116 115 RAM_ADDR<10>
RAM_ADDR<10> 115 116 RAM_BA<1>
36 12 10 BA1 A10_AP 10 12 36
36 12 10 A10_AP BA1 10 12 36
RAM_RAS_L 118 117 RAM_BA<0>
RAM_BA<0> 117 118 RAM_RAS_L
36 12 10
RAS* BA0 10 12 36
36 12 10 BA0 RAS* 10 12 36
120 119
36 12 10 RAM_WE_L 119
WE* CAS*
120 RAM_CAS_L 10 12 36
36 12 10 RAM_CAS_L
122
CAS* WE*
121
RAM_WE_L 10 12 36 1 C543 1 C498
RAM_CS_L<0> 121 122 RAM_CS_L<1>
36 10 RAM_CS_L<3>
S1* S0* RAM_CS_L<2> 10 36 10UF 10UF
36 10 S0* S1* 10 36
124 123 20% 20%
RFU17 RFU16 NC 6.3V 6.3V
123 124 NC NC 2 CERM 2 CERM
NC RFU16 RFU17 126 125 805 805
125 126 VSS21 VSS20
B 36 11 RAM_DATA_A<32> 127
VSS20
DQ32
VSS21
DQ36
128 RAM_DATA_A<36> 11 36
36 11 RAM_DATA_B<36>
RAM_DATA_B<37>
128
130
DQ36 DQ32
127
129
RAM_DATA_B<32>
RAM_DATA_B<33>
11 36 B
RAM_DATA_A<33> 129 130 RAM_DATA_A<37>
36 11 DQ37 DQ33 11 36
36 11 DQ33 DQ37 11 36
132 131
131 132 VDD21 VDD20
VDD20 VDD21 RAM_DQM_B<4> 134 133 RAM_DQS_B<4> 11 36
RAM_DQS_A<4> 133 134 RAM_DQM_A<4>
36 11 DM4 DQS4
36 11 DQS4 DM4 11 36
136 135
36 11 RAM_DATA_A<34> 135
DQ34 DQ38
136 RAM_DATA_A<38> 11 36
36 11 RAM_DATA_B<38>
138
DQ38 DQ34
137
RAM_DATA_B<34> 11 36 1 C806 1 C810 1 C814 1 C818 1 C822
137 138 VSS23 VSS22 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
VSS22 VSS23 140 139 20% 20% 20% 20% 20%
36 11 RAM_DATA_B<39> DQ35 RAM_DATA_B<35> 11 36 10V 10V 10V 10V 10V
RAM_DATA_A<35> 139 140 RAM_DATA_A<39> DQ39 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
36 11 DQ35 DQ39 11 36
RAM_DATA_B<44> 142 141 RAM_DATA_B<40>
141 142 36 11
DQ44 DQ40 11 36 402 402 402 402 402
36 11 RAM_DATA_A<40> DQ40 DQ44 RAM_DATA_A<44> 11 36
144 143
143 144 VDD23 VDD22
VDD22 VDD23 RAM_DATA_B<45> 146 145 RAM_DATA_B<41>
RAM_DATA_A<41> 145 146 RAM_DATA_A<45>
36 11
DQ45 DQ41 11 36
36 11 DQ41 DQ45 11 36
RAM_DQM_B<5> 148 147 RAM_DQS_B<5> 11 36
RAM_DQS_A<5> 147 148 RAM_DQM_A<5>
36 11 DM5 DQS5
36 11 DQS5 DM5 11 36
150 149
149 150 VSS25 VSS24
151
VSS24 VSS25
152 36 11 RAM_DATA_B<46> 152
DQ46 DQ42
151 RAM_DATA_B<42> 11 36
1 C807 1 C811 1 C815 1 C819 1 C823
36 11 RAM_DATA_A<42> DQ42 DQ46 RAM_DATA_A<46> 11 36
RAM_DATA_B<47> 154 153 RAM_DATA_B<43>
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
153 154 36 11
DQ47 DQ43 11 36 20% 20% 20% 20% 20%
36 11 RAM_DATA_A<43> DQ43 DQ47 RAM_DATA_A<47> 11 36 10V 10V 10V 10V 10V
156 155 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
155 156 VDD25 VDD24 402 402 402 402 402
VDD24 VDD25 SYSCLK_DDRCLK_B1_L 158 157
157 158 SYSCLK_DDRCLK_A1_L
36 10 CK1* VDD26
VDD26 CK1* 10 36
SYSCLK_DDRCLK_B1 160 159
159 160 SYSCLK_DDRCLK_A1
36 10
CK1 VSS26
VSS26 CK1 10 36
162 161
161 162 VSS28 VSS27
VSS27 VSS28 RAM_DATA_B<52> 164 163 RAM_DATA_B<48>
RAM_DATA_A<48> 163 164 RAM_DATA_A<52>
36 11
DQ52 DQ48 11 36
36 11 DQ48 DQ52 11 36
RAM_DATA_B<53> 166 165 RAM_DATA_B<49>
RAM_DATA_A<49> 165 166 RAM_DATA_A<53>
36 11 DQ53 DQ49 11 36
36 11 DQ49 DQ53 11 36
168 167
167 168 VDD28 VDD27
VDD27 VDD28 RAM_DQM_B<6> 170 169 RAM_DQS_B<6> 11 36
RAM_DQS_A<6> 169 170 RAM_DQM_A<6>
36 11
DM6 DQS6
36 11 DQS6 DM6 11 36
RAM_DATA_B<54> 172 171 RAM_DATA_B<50>
RAM_DATA_A<50> 171 172 RAM_DATA_A<54>
36 11 DQ54 DQ50 11 36
36 11 DQ50 DQ54 11 36
174 173
173 174 VSS30 VSS29
36 11 RAM_DATA_A<51> 175
VSS29
DQ51
VSS30
DQ55
176 RAM_DATA_A<55> 11 36
36 11
36 11
RAM_DATA_B<55>
RAM_DATA_B<60>
176
178
DQ55 DQ51
DQ56
175
177
RAM_DATA_B<51>
RAM_DATA_B<56>
11 36
11 36
DDR SODIMM CONNS
A 36 11 RAM_DATA_A<56> 177
179
DQ56
VDD29
DQ60
VDD30
178
180
RAM_DATA_A<60> 11 36
180
182
DQ60
VDD30 VDD29
179
181 NOTICE OF PROPRIETARY PROPERTY
A
36 11 RAM_DATA_B<61> DQ57 RAM_DATA_B<57> 11 36
RAM_DATA_A<57> 181 182 RAM_DATA_A<61> DQ61
36 11 DQ57 DQ61 11 36
RAM_DQM_B<7> 184 183 RAM_DQS_B<7> 11 36
RAM_DQS_A<7> 183 184 RAM_DQM_A<7>
36 11
DM7 DQS7 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
36 11 DQS7 DM7 11 36
186 185 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
185 186 +3V_MAIN VSS32 VSS31 AGREES TO THE FOLLOWING
VSS31 VSS32 RAM_DATA_B<62> 188 187 RAM_DATA_B<58>
RAM_DATA_A<58> 187 188 RAM_DATA_A<62>
36 11
DQ62 DQ58 11 36
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
36 11 DQ58 DQ62 11 36
190 189 +3V_MAIN
36 11 RAM_DATA_B<63> DQ59 RAM_DATA_B<59> 11 36
+3V_MAIN RAM_DATA_A<59> 189 190 RAM_DATA_A<63> DQ63 II NOT TO REPRODUCE OR COPY IT
36 11 DQ59 DQ63 11 36
192 191
191 192 VDD32 VDD31 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
VDD31 VDD32 194 193 INT_I2C_DATA0
INT_I2C_DATA0 193 194 SA0 SDA 12 14 23 39
39 23 14 12 SDA SA0 196 195 INT_I2C_CLK0 SIZE DRAWING NUMBER REV.
195 196 SA1 SCL 12 14 23 39
39 23 14 12 INT_I2C_CLK0
197
SCL SA1
198 ADDR=0XA0(WR)/0XA1(RD) ADDR=0XA2(WR)/0XA3(RD) 198
SA2 VDDSPD
197
D 051-6469 F
VDDSPD SA2 200 199
199 200 NC RFU19 RFU18 NC APPLE COMPUTER INC.
NC RFU18 RFU19 NC SCALE SHT OF
202
202
NONE 12 44
8 7 6 5 4 3 2 1
CR-13
8 7 6 5 4 3 2 1
AGP PULL-UPS/PULL DOWNS
R106
1
4.7 2
38 15 13 9 +1_5V_INTREPID_PLL +1_5V_INTREPID_PLL5 38
5% +3V_GPU 15 19 20 21 38
R77 C144 1 1/16W
MF
1
4.7 2 0.22UF 402
38 15 13 9 +1_5V_INTREPID_PLL +1_5V_INTREPID_PLL6 38
38 20 19 17 16 13 +1_5V_AGP 20%
5% 6.3V 2
1/16W CERM
C87 1 MF 402 RP20
0.22UF 402 10K
D 20%
6.3V 2
CERM
19 13 AGP_BUSY_L 2
5%
7
D
402 1/16W
R146 NOTE: Designs using AGP slot should RP20 SM1
33
1
R163 10K
CLK33M_AIRPORT 1 2
use 52-ohm a resistor here. 19 13 STOP_AGP_L 1 8
39 36 24
J11 60.4
5% 1% V14 5%
1/16W VDD15A_6 1/16W 1/16W
MF 39 24 13 AIRPORT_PCI_REQ_L AR17 PCI_REQ_0 (PLL4)
PCIAD_0 AM10 PCI_AD<0> 10 18 24 26 37 39
MF VDD15A_5 SM1
402
AR8 2 402 (PLL5)
18 13 CBUS_PCI_REQ_L AR16 PCI_REQ_1 PCIAD_1 PCI_AD<1> 10 18 24 26 37 39
R107 26 13 USB2_PCI_REQ_L AT17 PCI_REQ_2 CRITICAL PCIAD_2 AK12 PCI_AD<2> 10 18 24 26 37 39
AN19
U44 +1_5V_AGP 13 16 17 19 20 38
19 13 STP_AGP INTREPID-REV2.1 AGPREQ AT33
STOP_AGP_L AGP_REQ_L 13 19 37
33 PCIAD_3 AJ8 PCI_AD<3> 10 18 24 26 37 39
AJ24
36 18 CLK33M_CBUS 1 2 39 24 AIRPORT_PCI_GNT_L AT16 PCI_GNT_0 U44 AN10 PCI_AD<4>
INT_AGPPVT
AGPPVT BGA AGPGNT AM29 AGP_GNT_L 13 19 37
AN18 PCIAD_4 10 18 24 26 37 39
AB20 (3 OF 9)
5%
1/16W
18 CBUS_PCI_GNT_L INTREPID-REV2.1
PCI_GNT_1
PCIAD_5 AT8 PCI_AD<5> 10 18 24 26 37 39
38 13 INT_AGP_VREF AGPVREF0
AGPAD0 AR19 AGP_AD<0> 19 37
MF USB2_PCI_GNT_L AN17 PCI_GNT_2 BGA AB21
26
AN11 AGPVREF1 CRITICAL
402 (7 OF 9) PCIAD_6 PCI_AD<6> 10 18 24 26 37 39 AGPAD1 AM19 AGP_AD<1> 19 37
NEC_USB 36 CLK33M_AIRPORT_UF AR18 PCI_CLK0 PCIAD_7 AH13 PCI_AD<7> 10 18 24 26 37 39 AGPAD2 AT20 AGP_AD<2> 19 37 RP23
R1350 36 CLK33M_CBUS_UF AH18 PCI_CLK1 PCI/ROM PCIAD_8 AK13 PCI_AD<8> 10 18 24 26 37 39 19 13 AGP_BUSY_L
AT19
AGP_BUSY AGPAD3 AR20 AGP_AD<3> 19 37 AGP_REQ_L 4
10K 5
22 AT18 AR9 AK28
37 19 13
36 26 CLK33M_USB2 1 2 36 CLK33M_USB2_UF PCI_CLK2 INTERFACE PCIAD_9 PCI_AD<9> 10 18 24 26 37 39 CLK66M_AGP_15V_TP AGP_CLK AGPAD4 AT21 AGP_AD<4> 19 37
5%
5% 36 INT_PCI_FB_OUT AM18 PCI_CLK_OUT PCIAD_10 AR10 PCI_AD<10> 10 18 24 26 37 39 36 INT_AGP_FB_IN AK27 AGP_FB_IN Vin = Vcore (1.5V) AGPAD5 AN20 AGP_AD<5> 19 37
1/16W
SM1
RP21
1/16W
AJ19 VOUT = 3.3V AT9 AK25 10K
MF
402
36INT_PCI_FB_IN PCI_CLK_IN PCIAD_11 PCI_AD<11> 10 18 24 26 37 39 36 INT_AGP_FB_OUT AGP_FB_OUT Vout = AGPIO (1.5V) AGPAD6 AR21 AGP_AD<6> 19 37
37 19 13 AGP_GNT_L 4 5
OUTPUT IMPEDANCE IS ABOUT 20OHM VIN = 1.5V (CORE) AR11
AT14 PCIAD_12 PCI_AD<12> 10 18 24 26 37 39
Need divider for 3.3V slot! AGPAD7 AN21 AGP_AD<7> 19 37
5%
39 37 26 24 18 PCI_PAR PCI_PAR
R126 PCI_FRAME_L AN16 PCI_FRAME
PCIAD_13 AM12 PCI_AD<13> 10 18 24 26 37 39
R170 AGPAD8 AM21 AGP_AD<8> 19 37 RP21 1/16W
SM1
33
37 26 24 18 13
39 PCIAD_14 AN12 PCI_AD<14> 10 18 24 26 37 39
0 2 AGPAD9 AT22 AGP_AD<9> 19 37
3
10K 6
1 2 37 26 24 18 13 PCI_TRDY_L AT15 PCI_TRDY 1 37 19 13 AGP_FRAME_L
AK11
5%
39
PCI_IRDY_L AH16 PCIAD_15 PCI_AD<15> 10 18 24 26 37 39 AGPAD10 AR22 AGP_AD<10> 19 37
37 26 24 18 13 PCI_IRDY AT11 5% 5%
1/16W
MF
39
PCI_STOP_L AR15
PCIAD_16 PCI_AD<16> 10 18 24 26 37 39 1/16W AGPAD11 AN22 AGP_AD<11> 19 37 1/16W
RP20
37 26 24 18 13 PCI_STOP AT10 MF SM1
402 39
PCI_DEVSEL_L AM17 PCIAD_17 PCI_AD<17> 10 18 24 26 37 39 402 AGPAD12 AM22 AGP_AD<12> 19 37 10K
37 26 24 18 13 PCI_DEVSEL AN13 AGP_DEVSEL_L 4 5
39 PCIAD_18 PCI_AD<18> 10 18 24 26 37 39 AGP AGPAD13 AN23 AGP_AD<13> 19 37
37 19 13
PCI_CBE<0> AR14 PCI_CBE_0 PCIAD_19 AM13 PCI_AD<19> INTERFACES AGPAD14 AR23 AGP_AD<14> 5%
39 37 26 24 18 10 18 24 26 37 39
AGP_FB_CLK IS ROUTED THE SAME LENGTH AS CLK66M_GPU_AGP 19 37
1/16W
1
R141 39 37 26 24 18 PCI_CBE<1> AK16 PCI_CBE_1 PCIAD_20 AR12 PCI_AD<20> 10 18 24 26 37 39 AGPAD15 AT24 AGP_AD<15> 19 37 RP23 SM1
47 10K
C 5%
1/16W
MF
39 37 26 24 18
39 37 26 24 18
PCI_CBE<2>
PCI_CBE<3>
AM16
AJ15
PCI_CBE_2
PCI_CBE_3
PCIAD_21
PCIAD_22
AJ11
AT12
PCI_AD<21>
PCI_AD<22>
18 24 26 37 39
18 24 26 37 39
AGPAD16 AM23
AGPAD17 AR24
AGP_AD<16>
AGP_AD<17>
19 37
19 37
37 19 13 AGP_IRDY_L 2
5%
7
C
2 402
36 CLK66M_GPU_AGP_UF AK17 ROM_OVRLY_EN
PCIAD_23 AM11 PCI_AD<23> 18 24 26 37 39 AGPAD18 AT25 AGP_AD<18> 19 37
1/16W
SM1 RP23
AM9 PCIAD_24 AR13 PCI_AD<24> 10 18 24 26 37 39 AGPAD19 AR25 AGP_AD<19> 19 37
3
10K 6
13 INT_ROM_CS_L
INT_ROM_OE_L AR7
ROM_CS
PCIAD_25 AK15 PCI_AD<25> 10 18 24 26 37 39
AGP I/O REFERENCE AGPAD20 AM24 AGP_AD<20> 19 37
37 19 13 AGP_TRDY_L
13 ROM_OE AH15 (PLACE CLOSE TO INTREPID AGP BALLS) 5%
INT_ROM_RW_L AN9 PCIAD_26 PCI_AD<26> 10 18 24 26 37 39 AGPAD21 AN25 AGP_AD<21> 19 37
RP21 1/16W
13 ROM_WE AN14 SM1
PCIAD_27 PCI_AD<27> 10 18 24 26 37 39 AGPAD22 AL24 AGP_AD<22> 19 37 10K
38 20 19 17 16 13 +1_5V_AGP AGP_STOP_L 2 7
PCI FEEDBACK CLOCK MATCHES LONGEST PCI CLOCK ROUTE AT13
PCIAD_28 PCI_AD<28> 10 18 24 26 37 39 AGPAD23 AR26 AGP_AD<23> 19 37
37 19 13
AK14
PCIAD_29 PCI_AD<29> 10 18 24 26 37 39 AGPAD24 AT26 AGP_AD<24> 19 37
5%
AN15
AGPAD25 AM25
1/16W
SM1 RP20
R1399 PCIAD_30 PCI_AD<30> 10 18 24 26 37 39 AGP_AD<25> 19 37
10K
33 (PLL4) PCIAD_31 AM15 PCI_AD<31> 10 18 24 26 37 39 R140 1 AGPAD26 AN26 AGP_AD<26> 19 37 37 19 13 AGP_RBF_L 3 6
36 19 CLK66M_GPU_AGP 1 2
VSSA_6 4.99K AGPAD27 AM26 AGP_AD<27> 19 37 5%
5%
1/16W
J10 1%
1/16W AGPAD28 AR27 AGP_AD<28> 19 37 RP23 1/16W
SM1
MF MF 10K
402 402 2 AGPAD29 AT27 AGP_AD<29> 19 37
19 13 AGP_WBF_L 1 8
INT_AGP_VREF 13 38
AGPAD30 AR28 AGP_AD<30> 19 37
5%
AGPAD31 AN27 AGP_AD<31> 19 37
1/16W
SM1 RP21
R1351 10K
4.99K
1 C226 AGPCBE_0 AM20 AGP_CBE<0> 19 37 19 13 AGP_PIPE_L 1 8
1% 0.22UF AGPCBE_1 AT23 AGP_CBE<1> 19 37 5%
1/16W 20% 1/16W
MF 2 6.3V
CERM AGPCBE_2 AN24 AGP_CBE<2> 19 37
R147 SM1
402 2 402 AL25
AGPCBE_3 AGP_CBE<3> 19 37
AGP_AD_STB<0> 1
10K 2
37 19 13
AT29 AGP_PAR 5%
AGPPAR 19 37
1/16W
PCI PULL-UPS AGPFRAME AN28 AGP_FRAME_L 13 19 37 MF
402
R145
AGPTRDY AR29 AGP_TRDY_L 13 19 37 1
10K 2
37 19 13 AGP_AD_STB<1>
AT28 AGP_IRDY_L
+3V_SLEEP SIMPLY PROVIDING REFERENCE TO CHIP AGPIRDY 13 19 37 5%
BECAUSE SINGLE AGP PWR PLANE AND CLOSE PROXIMITY OF CHIPS AM28 AGP_STOP_L 1/16W
RP18 AGPSTOP
AM27
13 19 37
R181 MF
402
10K
B 39 37 26 24 18 13 PCI_FRAME_L 3 6
AGPDEVSEL
AGP_SBA0 AT32
AGP_DEVSEL_L
AGP_SBA<0>
13 19 37
19 37
37 19 13 AGP_SB_STB 1
10K 2 B
5% 5%
1/16W
SM1
RP19 AGP_SBA1 AR32 AGP_SBA<1> 19 37
1/16W
MF
10K AM31 AGP_SBA<2> 402
PCI_DEVSEL_L 1 8 AGP_SBA2 19 37
39 37 26 24 18 13
5%
SERIES RESISTORS FOR BOOTROM CONTROL SIGNALS AGP_SBA3 AN31 AGP_SBA<3> 19 37
RP18 1/16W
SM1 AGP_SBA4 AR31 AGP_SBA<4> 19 37
10K PLACE CLOSE TO INTREPID SIDE AT31 AGP_SBA<5>
39 37 26 24 18 13 PCI_IRDY_L 1 8 AGP_SBA5 19 37
AM30 AGP_SBA<6>
AGP_SBA6
5%
1/16W RP18 AGP_SBA7 AN30 AGP_SBA<7>
19 37
R148
SM1 10K
19 37
AGP_AD_STB_L<0> 1
10K 2
39 37 26 24 18 13 PCI_TRDY_L 2 7 R71 AGP_SB_STB_P AH25 AGP_SB_STB 13 19 37
37 19 13
5%
5%
22 1/16W
RP18 1/16W 13 INT_ROM_CS_L 1 2 ROM_CS_L 10 24 39 AGP_SB_STB_N AG25 AGP_SB_STB_L 13 19 37 MF R125
SM1 402 10K
10K 5%
39 37 26 24 18 13 PCI_STOP_L 4 5 1/16W
MF R49 AGP_ST0 AN29 AGP_ST<0> 19 37 19 13 AGP_AD_STB_L<1> 1 2
5% INT_ROM_OE_L
402
1
22 2 ROM_OE_L
AGP_ST1 AT30 AGP_ST<1> 19 5%
1/16W
13 10 24 39
1/16W
SM1 RP19 5%
AGP_ST2 AR30 AGP_ST<2> 19
R169 MF
402
10K 1/16W 10K
39 24 13 AIRPORT_PCI_REQ_L 2 7 R54 MF
402
AGP_AD_STB0_P AK20 AGP_AD_STB<0> 13 19 37 37 19 13 AGP_SB_STB_L 1 2
5% 1
22 2 AGP_AD_STB0_N AK19 AGP_AD_STB_L<0> 13 19 37 5%
13 INT_ROM_RW_L ROM_RW_L 10 24 39 1/16W
1/16W AK30 AK21
SM1 5% 19 13 AGP_WBF_L AGP_WBF AGP_AD_STB1_P AGP_AD_STB<1> 13 19 37 MF
1/16W 402
AK22 AGP_AD_STB_L<1>
MF AGP_AD_STB1_N 13 19 37
402
AJ29 AGP_PIPE_L
AGPPIPE 13 19
AK24 AGP_RBF_L
AGPRBF 13 19 37
VSSA_5
(PLL5)
+3V_MAIN V13
RP19
10K
INTREPID AGP/PCI
A 26 13 USB2_PCI_REQ_L 4
5%
5
NOTICE OF PROPRIETARY PROPERTY
A
RP19 1/16W
SM1
3
10K 6
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
18 13 CBUS_PCI_REQ_L
AGREES TO THE FOLLOWING
5% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W
SM1 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
USB2 AND CBUS REQ REMAINS ON
SIZE DRAWING NUMBER REV.
+3V_MAIN BECAUSE THESE CHIPS
ARE POWERED IN SLEEP APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 13 44
8 7 6 5 4 3 2 1
CR-14
8 7 6 5 4 3 2 1
CLKENET_LINK_TX
TEST PULL-UPS/DOWNS
36 27
V5 UIDE_DATA<0>
ATA_D0
CRITICAL 24 37
T1
U44 ATA_D1
U1
UIDE_DATA<1> 24 37
R548 +3V_MAIN
UIDE_DATA<2> 10 RP17
INTREPID-REV2.1 ATA_D2
24 37
37 27 ENET_PHY_TX_EN 1 2 37 ENET_LINK_TX_EN
U2
BGA ATA_D3 UIDE_DATA<3> 24 37
5% 3
10K 6
(5 OF 9) V4 UIDE_DATA<4> 1/16W 39 14 JTAG_ASIC_TDI
ATA_D4 24 37
MF
ATA_D5 V2 UIDE_DATA<5> 402 5%
W1
24 37
R543 CRITICAL RP17 1/16W
SM1
ATA_D6 UIDE_DATA<6> 24 37
10 H9
TX_CLK U44 1
10K 8
V1 37 27 ENET_PHY_TX_ER 1 2 37 ENET_LINK_TX_ER 39 27 14 JTAG_ASIC_TMS
UIDE_DATA<7>
ATA_D7
W2
24 37
5%
A7
TX_EN INTREPID-REV2.1 5%
ATA_D8 UIDE_DATA<8> 24 37 A5 BGA
D ATA_D9 W8
W4
UIDE_DATA<9> 24 37
1/16W
MF
402
ENET_LINK_TXD<0> H10
TX_ER
TXD_0
(4 OF 9)
1/16W
SM1 R1402
10K
D
ATA_D10 UIDE_DATA<10> 24 37
37 14
27 14 JTAG_ENET_TDI 2 1
UATA100 W5 UIDE_DATA<11> 37 14 ENET_LINK_TXD<1> E9
TXD_1 5%
ATA_D11 24 37
ENET_LINK_TXD<2> D8 1/16W
ATA_D12 Y2 UIDE_DATA<12> 24 37
37 14 TXD_2 MF
ENET_LINK_TXD<3> A6 RESET U5 INT_RESET_L 402
Y1 TXD_3
ATA_D13 UIDE_DATA<13> 24 37
37 14
ENET_LINK_TXD<4> B7 TXD_4
MISC 10 30
R547
ATA_D14 W7 UIDE_DATA<14> 24 37
37 14
PURESET T2 INT_PU_RESET_L 25 30 1
10K 2
ENET_LINK_TXD<5> G10 14 INT_TST_PLLEN_PD
ATA_D15 Y8 UIDE_DATA<15> 24 37
37 14 TXD_5
ENET_LINK_TXD<6> D9 5%
37 14 TXD_6 1/16W
ATA_A0 Y5 UIDE_ADDR<0> 24 37
37 14 ENET_LINK_TXD<7> E10
TXD_7
PHY_DATA0 L4 FW_LINK_DATA<0> 28 37 MF RP17
PHY_DATA1 M4 FW_LINK_DATA<1> 402 10K
ATA_A1 AB1 UIDE_ADDR<1> 24 37
28 37
39 27 14 JTAG_ASIC_TCK 2 7
CLKENET_LINK_RX J12 P7 FW_LINK_DATA<2>
ATA_A2 Y7 UIDE_ADDR<2> 24 37
36 27 RX_CLK PHY_DATA2 28 37
C4 N5 5%
ENET_RX_DV RX_DV PHY_DATA3 FW_LINK_DATA<3> 1/16W
ATA_VREF Y15 UIDE_REF 38
37 27
ENET_RX_ER D2
RX_ER PHY_DATA4 K1 FW_LINK_DATA<4>
28 37
R544 SM1
Y4
37 27 28 37
1
1K 2
ATA_RST UIDE_RST_L 24 37
PHY_DATA5 K2 FW_LINK_DATA<5> 28 37
39 27 14 JTAG_ASIC_TRST_L
ENET_LINK_RXD<0> D3
UDMA - STOP ATA_WR AA1 UIDE_DIOW_L 24 37
37 27 RXD_0 GB ETHERNET L2 FW_LINK_DATA<6> 5%
PHY_DATA6
UDMA - HOSTDMARDY/HSTROBE ATA_RD AA2 UIDE_DIOR_L 24 37
R26 37 27 ENET_LINK_RXD<1> E7
RXD_1
PHY_DATA7 N4 FW_LINK_DATA<7>
28 37 1/16W
MF RP17
AA5 1
82 2 37 27 ENET_LINK_RXD<2> D6
RXD_2
28 37 402
10K
UDMA - DEVICEDMARDY/DSTROBE ATA_CHRDY UIDE_IOCHRDY HD_DMARQ
ATA_CS0 AA4 UIDE_CS0_L
24 37
5%
24 37
37 27 ENET_LINK_RXD<3> B4
RXD_3 FIREWIRE PHY_LPS M1 FW_PHY_LPS 28
R15 14 INT_JTAG_TEI 4 5
24 37
1/16W A4 P5 1
22 2 5%
AB2 ENET_LINK_RXD<4> RXD_4 PHY_CTL0 FW_LINK_CNTL<0> FW_PHY_LREQ
ATA_CS1
AC1
UIDE_CS1_L 24 37 MF
402
37 27
ENET_LINK_RXD<5> D7
RXD_5 PHY_CTL1 L1 FW_LINK_CNTL<1>
28 37
5%
28 37
R549 1/16W
SM1
ATA_DMACK UIDE_DMACK_L 24 37
37 27 28 37
1/16W 1
1K 2
ATA_DMARQ AC2 37 UIDE_DMARQ R61 37 27 ENET_LINK_RXD<6> G9 RXD_6 PHY_LREQ M2 37 FW_LINK_LREQ MF
402
14 INT_TST_MONIN_PD
AA8 1
82 2 37 27 ENET_LINK_RXD<7> E8
RXD_7 FWR_PCLK T7 CLKFW_LINK_PCLK 28 36
5%
ATA_INTRQ 37 UIDE_INTRQ HD_INTRQ 24 37 1/16W
5%
R88 36 27 CLKENET_LINK_GBE_REF L13
GBE_REFCLK R105 MF
402
1/16W 10 H12 22
MF 36 27 CLKENET_PHY_GTX 1 2 36 CLKENET_LINK_GTX GTX_CLK FWR_LCLK U14 36 CLKFW_LINK_LCLK 1 2 CLKFW_PHY_LCLK 28 36
+3V_MAIN 402 E6
NO_TEST=TRUE CS_CE1 AD1 CSLOT_CE1_L_SPN 5%
1/16W
37 27 ENET_CRS CRS FW_LINKON N2 FW_LKON 28 5%
1/16W
C5
NO_TEST=TRUE CS_CE2 AB4 CSLOT_CE2_L_SPN MF 37 27 ENET_COL COL FW_PINT N1 FW_PINT 28 37 MF
AB5 1
402
ENET_MDIO B5
MDIO
402
I2C PULL-UPS
NO_TEST=TRUE CS_IORD CSLOT_IORD_L_SPN
R27 37 27
ENET_MDC B6 MDC
+3V_MAIN
AD2 10K
C NO_TEST=TRUE
CARDSLOT
NO_TEST=TRUE
CS_IOWR
CS_OE AC4
CSLOT_IOWR_L_SPN
CSLOT_OE_L_SPN
5%
1/16W
MF
37 27
RP13
2
10K 7
C
AE1 CSLOT_WE_L_SPN 39 23 14 12 INT_I2C_CLK0
NO_TEST=TRUE CS_WE 2 402 39 14 JTAG_ASIC_TDI AK8
TDI
CS_WAIT AE2 CSLOT_IOWAIT_L_PU AT5 5%
27 14 JTAG_ENET_TDI TDO 1/16W
CS_WAIT IS AN INPUT 39 27 14 JTAG_ASIC_TCK AP5
TCK
SM1 RP13
10K
JTAG_ASIC_TMS AR5 INT_I2C_DATA0 1 8
39 27 14 TMS 39 23 14 12
IDEDD0 AC5 EIDE_DATA<0> 24 37
39 27 14 JTAG_ASIC_TRST_L AN6
TRSTN TEST IICCLK_0 AN2 INT_I2C_CLK0 12 14 23 39 5%
IDEDD1 AD4 EIDE_DATA<1> 24 37
14 INT_JTAG_TEI AH10
TEI IICDATA_0 AN1 INT_I2C_DATA0 12 14 23 39
RP13 1/16W
SM1
AF1 EIDE_DATA<2>
10K
IDEDD2 24 37
14 INT_TST_MONIN_PD AM7
TST_MONIN 39 25 15 14 INT_I2C_CLK1 4 5
IDEDD3 AG1 EIDE_DATA<3> AK10
24 37 INT_TST_MONOUT_TP TST_MONOUT IICCLK_1 AK5 INT_I2C_CLK1 14 15 25 39 5%
IDEDD4 AF2 EIDE_DATA<4> 1/16W
AH1
24 37
14 INT_TST_PLLEN_PD AR6 TST_PLLEN IICDATA_1 AM3 INT_I2C_DATA1 14 15 25 39 SM1 RP13
IDEDD5 EIDE_DATA<5> 24 37
3
10K 6
AD5 EIDE_DATA<6> 39 25 15 14 INT_I2C_DATA1
IDEDD6 24 37
IDEDD7 AG2 EIDE_DATA<7> 24 37
5%
1/16W
IDEDD8 AE4 EIDE_DATA<8> SM1
IDEDD9 AE5 EIDE_DATA<9>
24 37
24 37
ENET_TXD SERIES TERMINATION
AF4
IDEDD10
IDEDD11 AH2
EIDE_DATA<10>
EIDE_DATA<11>
24 37
24 37
ADDR
BUS I2C-0 I2C-1 I2C-2 PMU
IDEDD12 AD7 EIDE_DATA<12> 24 37
RP16 (MAIN) (MAIN) (SLEEP) (SLEEP)
AG4 2
22 7 A0-WR RAM - STANDARD
IDEDD13 EIDE_DATA<13> ENET_PHY_TXD<0> ENET_LINK_TXD<0>
IDEDD14 AJ1 EIDE_DATA<14>
24 37
24 37
37 27
5%
14 37
A1-RD J20 - PG 12 N/A N/A N/A
IDEDD15 AJ2 EIDE_DATA<15> 24 37
1/16W
SM1 RP15 A2-WR RAM - REVERSED
4
22 5 N/A N/A N/A
IDE IDEA0 AF5 EIDE_ADDR<0> 24 37
37 27 ENET_PHY_TXD<1> ENET_LINK_TXD<1> 14 37
A3-RD J23 - PG 12
AE7 5%
IDEA1 EIDE_ADDR<1> 24 37
RP15 1/16W AC-WR DASH MODEM
N/A
IDEA2 AK1 EIDE_ADDR<2> 24 37
ENET_PHY_TXD<2> 3
22 6
SM1
ENET_LINK_TXD<2> AD-RD N/A N/A J9 - PG 25
AG5 CSLOT_ADDR3_SPN 37 27 14 37
NO_TEST=TRUE IDEA3
AE-WR BOOTBANG E2PROM
B
B NO_TEST=TRUE
NO_TEST=TRUE
IDEA4
IDEA5
AH4
AL1
CSLOT_ADDR4_SPN
CSLOT_ADDR5_SPN
5%
1/16W
SM1 RP15
22 AF-RD U37 - PG 23 N/A N/A N/A
NO_TEST=TRUE IDEA6 AK2 CSLOT_ADDR6_SPN NOT USING CARDSLOT INTERFACE 37 27 ENET_PHY_TXD<3> 1 8 ENET_LINK_TXD<3> 14 37
84-WR LMU
NO_TEST=TRUE IDEA7 AH5 CSLOT_ADDR7_SPN 5% N/A N/A N/A
NO_TEST=TRUE IDEA8 AF7 CSLOT_ADDR8_SPN RP15 1/16W
SM1
85-RD U36 - PG 23
NO_TEST=TRUE IDEA9 AG7 CSLOT_ADDR9_SPN 2
22 7 58-WR FAN CONTROLLER
N/A
37 27 ENET_PHY_TXD<4> ENET_LINK_TXD<4> 14 37
59-RD N/A U48 - PG 25 N/A
IDECHRDY AK4 EIDE_IOCHRDY 24 37
5%
IDECS0 AB7
1/16W
RP16 6A-WR SNAPPER SOUND
EIDE_CS0_L 24 37 SM1
22 N/A N/A N/A
IDECS1 AM1 EIDE_CS1_L 24 37 37 27 ENET_PHY_TXD<5> 3 6 ENET_LINK_TXD<5> 14 37 6B-RD J14 - PG 25
IDERST AJ4 EIDE_RST_L RP16 5%
1/16W D0-WR CLOCK SLEW SSCG
N/A
IDEWR AM2 EIDE_WR_L
24 37
24 37 22 SM1
D1-RD N/A U56 - PG 15 N/A
37 27 ENET_PHY_TXD<6> 1 8 ENET_LINK_TXD<6> 14 37
IDERD AL2 EIDE_RD_L 24 37
5%
IDEDMACK AG8 EIDE_DMACK_L 24 37 1/16W
RP16 ADDR LSB INDICATES READ (’1’) OR WRITE (’0’) MODES
AH7 SM1
IDEDMARQ EIDE_DMARQ 24 37
4
22 5
AA7 EIDE_INT 37 27 ENET_PHY_TXD<7> ENET_LINK_TXD<7> 14 37
IDEINTRQ 24 37
5%
1/16W
SM1
JTG_RSTN_L TST_TEI_H JTG_TDO_H JTG_TDI_H TST_PLLEN_H ANALYZER_CLK
(I/O) (I/O) DESCRIPTION
1
R112 1 X X X X X JTAG MODE
1K
1% EXTPLL DDR_
1/16W
MF
2 402
0 0 SHUTDOWN
(OUTPUT)
TPDENABLE
(OUTPUT)
0 (OUTPUT) NORMAL OPERATION INT - ENET/FW/UATA
SELECTED
0 0 (OUTPUT) 0(I) 1 PLL OUTPUTS VIEW PLLS (SOFTWARE) EIDE/I2C
A 0 0
HWPLL_
TESTSEL5
(INPUT)
1(I) 1 SELECTED
PLL OUTPUTS VIEW PLLS (HARDWARE) NOTICE OF PROPRIETARY PROPERTY
A
SYNC/MEM DATA
0 1 0(I) 0(I) MEMWE BYPASS ATPG NORMAL THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
0 1 0(I) 1(I) 0 X(I) ATPG IDDQ I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
0 1 0(I) 1(I) 1 X(I) TEST TRI-STATE III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
FUNCTIONAL TEST WITHOUT
0 1 1(I) 0(I) 0 X(I) POSTSCALAR BYPASS SIZE DRAWING NUMBER REV.
0 1 1(I) 0(I) 1 X(I) FUNCTIONAL
POSTSCALAR
TEST WITH
BYPASS
APPLE COMPUTER INC.
D 051-6469 F
0 1 1(I) 1(I) X X(I) FUNCTIONAL TEST IDDQ SCALE SHT OF
NONE 14 44
8 7 6 5 4 3 2 1
CR-15
8 7 6 5 4 3 2 1
+2_5V_MAIN +1_5V_INTREPID_PLL 9 13 38
R194
NO STUFF 4.7
R242 1 2 +1_5V_INTREPID_PLL8 38
USB PORT ASSIGNMENTS
1
0 2
5%
1/16W
5%
U10 C404 1 R226 1 C331 1 MF
402 PORT A - RIGHT USB 1
1/16W LT1962-ADJ 15.8K 0.22UF
MF MSOP 0.01UF 1% 20%
8 20% 6.3V 2 INTREPID_USB
+1_8V_MAIN
603 38 LTC1962_INT_VIN IN OUT 1 16V 1/16W CERM R123
CERM 2 MF
402 2
402 4.7 R58
R207 NC 7 NC 402 1 C399 1 2 +1_5V_INTREPID_PLL4 38
USB_DAP 1
24 2 USB_D2P
0 ADJ 2 LT1962_INT_ADJ 10UF 5%
26 15 26 39
1 2 C411 1 NC 6 NC 20%
2 6.3V C178 1
1/16W INTREPID_USB 5%
5% 1UF CERM
805 0.22UF
MF
402 R52 1/16W
MF
+3V_SLEEP
1/16W 20%
10V BYP 3 LT1962_INT_BYP
R2251 20% 1
24 2
402
MF USB_DAM USB_D2M
CERM 2 5 68.1K 6.3V 2 26 15 26 39
603 SHDN GND 4 R114
D
603
1%
1/16W
CERM
402
1
4.7 2 +1_5V_INTREPID_PLL3
5%
1/16W
MF
PORT B - UNUSED
D
RP28 MF
402 2
38 +3V_MAIN
402
10K 5%
1/16W
4 5 AIRPORT_PCI_INT_L 15 24 39
C166 1 MF
402
RP42
5% 0.22UF 10K
1/16W 20% 15 USB_DBP 6 3
SM1 6.3V
CERM 2
402
R89 2 5%
+3V_MAIN 4.7 1/16W
1 2 +1_5V_INTREPID_PLL2 38 SM1 RP7
5% L1 10K
R2 C137 1
1/16W
MF FERR-EMI-100-OHM 15 USB_DBM 5 4
10K 402 SM 5%
2 1 USB_PWREN_EF_L 15 0.22UF 1/16W
20%
5% 6.3V SM1
R78 1/16W CERM 2 R113 1
PORT C - LEFT USB
MF 402 INTREPID_USB
2
10K 1 402 1
4.7 2
USB_OC_EF_L +1_5V_INTREPID_PLL1
5%
15
5%
38
R504
1/16W RP41 1/16W 38 +3V_INTREPID_USB
1
24 2
MF
402 8
10K
1
C176 1 MF
402
26 15 USB_DCP
INTREPID_USB
USB_D1P 26 39
USB_OC_AB_L 0.22UF 5%
15
USB POWER FAULT SIGNALS 20% 1 C88 1 C89 1 C99 R532 1/16W
RP41 5%
1/16W
6.3V
CERM 2 0.01UF 0.1UF 10UF 24
MF
402
6
10K 3 SM1 +3V_MAIN +2_5V_MAIN 402 20%
16V
20%
10V
20%
6.3V 26 15 USB_DCM 1 2 USB_D1M 26 39
USB_PWREN_CD_L 15 2 CERM 2 CERM 2 CERM
5%
RP7 402 402 805
VDD15A_1 AA16
VDD15A_2 AJ12
VDD15A_3 AJ17
VDD15A_4 AJ18
VDD15A_8 AG29
5% 1/16W
1/16W MF PORT D - UNUSED
VDDU33_1 T8
VDDU33_2 U8
SM1 10K 402
1 8 USB_PWREN_AB_L 15 1 1
RP40
PCI_
(PLL1)
PCI_
(PLL2)
PCI_
(PLL3)
PCI_
(PLL7)
(PLL9)
SSCG
RP41 5% SSCG SSCG 10K
7
10K
2
1/16W
SM1
C839 1
L49 L50 15 USB_DDP 7 2
USB_OC_CD_L 15 0.1UF FOR D3COLD SUPPORT
20% 400-OHM-EMI 400-OHM-EMI 5%
5%
1/16W RP42
10V
CERM 2
SM-1 SM-1 38 21 20 19 13 +3V_GPU RP40 1/16W
SM1
SM1 402 CRITICAL 10K
10K 15 USB_DDM 8 1
1 8 USB2_PCI_INT_L 15 26
2 2 R599 1 U44 SCCTXDA AF9 COMM_TXD_L 25 39
5%
RP6 5% 10K INTREPID-REV2.1 SCCRTSA AN3 COMM_RTS_L 1/16W
C 4
10K 5
1/16W
SM1
INT_EXTINT14_PU 15
+3V_CG_PLL_MAIN 38
SSCG SSCG
5%
1/16W
BGA
(6 OF 9) SCCDTRA AF10 COMM_DTR_L
25 39
25 39
SM1
C
C840 C841
MF
SCCRXDA AG11 COMM_RXD PORT E - BLUETOOTH
5% RP28 30 15 SYSTEM_CLK_EN
NO STUFF
1 1 402 2 25 39
1/16W
SM1 10K 1 1UF 0.1UF SCCGPIOA AG9 COMM_GPIO_L 25 39 R4
2 7 INT_EXTINT8_PU 15 R888 20%
2 10V
20%
10V
2 CERM 15 CG_FSEL G5
GPIO0 VIA SCCTRXCA AT4 COMM_TRXC 25 39 USB_DEP 1
22 2 BT_USB_DP
10K CERM GENERAL 37 15 24 37 39
RP6 5%
1/16W
NO STUFF
SSCG 5%
1/16W
603 402 34 15 INT_GPIO1_PU E1 GPIO1 VCORE_A/B PURPOSE
SEL
MISO SCCTXDB AR4 PMU_FROM_INT 5%
2
10K 7
SM1
INT_GPIO1_PU R759 1
R758 1 MF 39 25 COMM_SHUTDOWN J7
GPIO2 I/O’S
SCCRTSB AL5 PMU_REQ_L
30
R45 1/16W
MF
15 34
0 2 402 COMM_RESET_L F2
GPIO3
REQ* 15 30 22 402
5% RP47 5% 10K 38 +2_5V_CG_MAIN
39 25
MOSI SCCRXDB AG10 PMU_TO_INT 30
37 15 USB_DEM 1 2 BT_USB_DM 24 37 39
5% FW_PHY_PD J8
1/16W
10K 1/16W 1/16W 28 GPIO4 5%
SM1 2 7 COMM_RING_DET_L
MF MF SSCG SND_HP_MUTE_L H5 ACK* SCCGPIOB AP4 PMU_ACK_L 30 1/16W
15 25 30 39 402 2 402 2 39 25 GPIO5 MF
1 C842 SCK SCCTRXCB AM5 PMU_CLK 30 402
RP41 5%
1/16W 1
NO STUFF
0.1UF
39 25 SND_AMP_MUTE_L L9
GPIO6
10K SM1 R886 20% 15 INT_GPIO9_PU H4
GPIO9 USB_VD0_P L8 USB_DAP 15 26
PORT F - MODEM
VDD1 10
VDDA 12
VDDQ 18
5 4 INT_GPIO15_PU 10V
10K
VDD0 1
VDDC 5
15
2 CERM J5 USB_VD0_N L7
5% RP40 5%
1/16W 402
39 25 15 SND_HW_RESET_L
K8
GPIO11 USB_DAM 15 26
R60
1/16W
10K MF 15 INT_GPIO12_PU GPIO12 22
SM1 3 6 USB_VD1_P G2 USB_DBP 15 37 15 USB_DFP 1 2 MODEM_USB_DP 25 37 39
INT_MOD_CLKOUT_PU 15 2 402 15 INT_GPIO15_PU F1 GPIO15
CRITICAL K7 USB_VD1_N G1 USB_DBM 15 5%
RP47 5%
1/16W U56 SSCG 27 INT_ENET_RST_L GPIO16 R59 1/16W
MF
10K SM1 USB_PRTPWR0 J4 USB_PWREN_AB_L 22 402
4 5 PMU_INT_L 15 30 CY28512B R890 39 30 25 15 COMM_RING_DET_L F33
EXTINT0
USB_PWRFLT0 K4 USB_OC_AB_L
15
37 15 USB_DFM 1 2 MODEM_USB_DM 25 37 39
36 15 INT_REF_CLK_OUT 20 CLKIN TSSOP 33 2 PMU_INT_L E34 EXTINT1
15
5%
5%
1/16W
RP47 SSCG CPU0 16 CG_CLKOUT 1 INT_REF_CLK_IN 15 36
30 15
C33 H2
1/16W
1 1
SM1 1
10K
8 CBUS_INT_L 15
15 CG_FSEL 3 FSEL OUTPUT IMPEDANCE ~18-20OHM 5%
1/16W
19 AGP_NV_INT_L EXTINT2 USB_VD2_P USB_DCP 15 26 MF
402 R79 R80
18 INTERNAL 250K PULL-UP
MF 15 INT_EXTINT3_PU D34
EXTINT3 USB_VD2_N H1 USB_DCM 15 26 15K 15K
RP28 5%
1/16W
39 25 14 INT_I2C_CLK1 9 SCLK 402
39 25 SND_LIN_SENSE_L B33
EXTINT4
5%
1/16W
5%
1/16W
10K SM1 ENET_ENERGY_DET A33 USB_VD3_P M7 USB_DDP 15 MF MF
1 8 PMU_INT_NMI INT_I2C_DATA1 8 SDATA 27 EXTINT5 402 2 2 402
15 30 39 25 14
AIRPORT_PCI_INT_L E31 USB USB_VD3_N M8 USB_DDM 15
5% RP1 39 24 15 EXTINT6
1/16W CG_ADDRSEL 14 ADDRSEL INTERNAL 250K PULL-DOWN G30 INTERRUPTS J2
SM1 1
10K 8 SSCG
18 15 CBUS_INT_L EXTINT7 USB_PRTPWR1 USB_PWREN_CD_L 15
PMU_REQ_L 15 30 INT_EXTINT8_PU D31 J1 USB_OC_CD_L
CG_RESET_L 17 RESET* 15 EXTINT8 POWERBOOK SPARE USB_PWRFLT1 15
RP40 5%
1/16W
R891 30 15 PMU_INT_NMI C32
EXTINT9
10K 13 PD* 0 USB_VD4_P K5 USB_DEP
B 4 5
SM1
INT_MOD_DTO_PU 15
30 15 SYSTEM_CLK_EN
CG_LOCK 2 LOCK SSCG
38 34 15 VCORE_VGATE 1
5%
2 15
15
INT_EXTINT10_PU
INT_EXTINT11_PU
B32
E30
EXTINT10
EXTINT11
VGATE/LOCK INTERRUPT
CBUS_IREQ_L
USB_VD4_N L5 USB_DEM
15 37
15 37 RP8
47
B
5%
1/16W
RP42 OPEN-DRAIN OUTPUT
2
R68
1/16W
MF 15 INT_EXTINT12_PU J9
EXTINT12 FAN PWM USB_VD5_P P8 USB_DFP 15 37
2 7 SND_TO_AUDIO 25 39
SM1 10K SSCG
4 402
4 5 INT_GPIO12_PU 15 ODSEL INTERNAL 250K PULL-UP 75 INT_EXTINT13_PU F4
EXTINT13 BRIGHTNESS PWM USB_VD5_N N8 USB_DFM 5%
R889 15 15 37
RP8
VSS0
VSS1
VSSA
VSSC
VSSQ
NO STUFF 5% D1 1/16W
INT_EXTINT14_PU
RP47 5%
1/16W VCORE_VGATE 1
0 2
1
R887 1/16W
MF
15
E2
EXTINT14 CONTRAST PWM
USB_PRTPWR2 M5 USB_PWREN_EF_L 15
SM1
3
47
6
10K SM1
38 34 15
10K 1 402 39 25 SND_HP_SENSE_L EXTINT15 N7 USB_OC_EF_L
SND_SYNC 25 39
3 6 INT_EXTINT3_PU 15 5% 5% INT_EXTINT16_PU H7 USB_PWRFLT2 15
1/16W PLACE R68 CLOSE TO INTREPID SIDE 15 EXTINT16 5%
7
19
11
15
5% RP6 MF
1/16W
MF OTHERWISE A LOT OF OVERSHOOT/UNDERSHOOT USB2_PCI_INT_L G4
EXTINT17
RP8 1/16W
SM1
1/16W
10K 402
2 402
26 15
D30 AUD_DTO R4 INT_SND_TO_AUDIO 47
SM1 MPIC_CPU_INT_L 4 5 SND_SCLK
3 6 INT_EXTINT13_PU 15
5 CPU_INT R7 INT_AUDIO_TO_SND
25 36 39
AUD_DTI 25 39
5%
RP42 5%
1/16W 30 26 PMU_PME_L PCIPME AJ7
AUD_SYNC T5 INT_SND_SYNC 1/16W
SM1 RP8
10K SM1 NO STUFF INT_PROC_SLEEP_REQ_L AT6 PROCSLEEPREQ AUD_BITCLK P2 INT_SND_SCLK
2 7 INT_EXTINT16_PU 15
30
47
AN8 R5 1 8
5%
RP28 R25 30 INT_PEND_PROC_INT PENDPROCINT AUD_CLKOUT INT_SND_CLKOUT SND_CLKOUT 25 36 39
1/16W
1
0 2 U4 AUDIO/I2S R2 5%
SM1 10K 36 CLK18M_INT_EXT 36 CLK18M_INT_XIN XTAL_IN MOD_DTO INT_MOD_DTO_PU 15 1/16W
3 6 INT_EXTINT11_PU NO STUFF V15 T4 SM1 HWPLL_
15 5%
1/16W
36 CLK18M_INT_XOUT XTAL_OUT MOD_DTI INT_MOD_DTI_PD 15
TESTMUXSEL SIGNAL NAME
RP25 5%
1/16W
MF
402
R540 30 15 SYSTEM_CLK_EN AN7
STOPXTAL CLOCKS MOD_SYNC R1 INT_MOD_SYNC_PD 15
5 MOD_BITCLK_B_H
10K SM1
2
10M 1 MOD_BITCLK V8 INT_MOD_BITCLK_PD 15
1 8 INT_EXTINT10_PU NO STUFF
15
INT_WATCHDOG_L AT7
WATCHDOG MOD_CLKOUT P1 INT_MOD_CLKOUT_PU 4 MOD_CLKOUT_B_H
5% J1 5%
1/16W 1
R550
30 15
3
1/16W
SM1
RP7 U.FL-R_SMT NO STUFF
MF
0 +3V_SLEEP
MOD_DTO_B_H
10K F-ST-SM 402
2 MOD_SYNC_B_H
3 6 3 1 5% U15
INT_EXTINT12_PU 15 R7 CRITICAL 1/16W 36 15 INT_REF_CLK_OUT BUF_REF_CLK_OUT
RP6 5%
1/16W
51
5%
Y1 MF
2 402
36 15 INT_REF_CLK_IN K9
SS_REF_CLK_IN 1 MOD_DTI_B_H
10K 1 18.432M
1 8
SM1
INT_GPIO9_PU 15
1/16W
MF 1 2
IICCLK_2 AL4 0 JTG_TDO_H
CLK18M_XTAL_IN IIC
2 402 36
5% 2 SM IICDATA_2 AH8 2
R8 2
R70
1/16W
SM1
3
RP1
10K
6
C16
22PF
1 1 C129
22PF
5%
4.7K
1/16W
4.7K
5%
1/16W
INT - USB/GPIOS/I2S
A INT_MOD_DTI_PD MF MF
(PLL1)
(PLL2)
(PLL3)
(PLL7)
VSSA_8
(PLL9)
VSSU_1
VSSU_2
15
5% 5%
A
VSSA1
VSSA2
VSSA3
VSSA4
5%
50V 50V 1 402 1 402
CERM 2 2 CERM
RP1 1/16W
SM1
402 402 NOTICE OF PROPRIETARY PROPERTY
10K
2 7 INT_MOD_BITCLK_PD 15 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
INT_I2C_CLK2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AA15
AJ13
AJ16
AK18
AH29
R9
R8
25 39
5%
1/16W
RP1 AGREES TO THE FOLLOWING
SM1 4
10K 5
INT_I2C_DATA2 25 39
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
INT_MOD_SYNC_PD 15 CRYSTAL LOAD CAPACITANCE IS 16PF
II NOT TO REPRODUCE OR COPY IT
5%
R76 1/16W III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1
100K 2 SM1 TABLE_5_HEAD
SND_HW_RESET_L 15 25 39
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION SIZE DRAWING NUMBER REV.
5%
1/16W
MF
402
116S1104 1 RES,METAL FILM,10 K OHM,5,1/16W,0402,SM R68 NO_SSCG
TABLE_5_ITEM
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 15 44
8 7 6 5 4 3 2 1
CR-16
8 7 6 5 4 3 2 1
+2_5V_MAIN
38 +2_5V_SLEEP
NO STUFF
R7641 1
R765 38 20 19 17 13 +1_5V_AGP
0 0
5% 5%
1/10W 1/10W
FF FF +1_5V_MAIN +3V_MAIN
805 2 2 805
38 34 23 17 9 7 5 MAXBUS_SLEEP
38 17 11 10 +2_5V_INTREPID
D D
AD20
AE20
AE23
AF22
AH19
AH22
AH28
AJ21
AJ23
AL19
AL22
AL28
AL30
AN32
AP19
AP22
AP25
AP28
AP31
AR33
AR34
AA11
AA12
AC12
AC13
AC14
AD21
AE15
AE17
AF25
AL10
AB3
AB6
F30
AE3
AE6
AH3
AH6
AK6
F7
F9
G3
G6
AA25 AGP_IO_VDD VDD3.3 AL13
C12 AA29 AL16
C15 AB25 AL3
C18 AB27 AL7
C21 U44 AB31 AM4
C24
INTREPID-REV2.1 AB34
BGA AN5
C27 (8 OF 9) AC25 AA21 AP10
C30 AC27 AA24
U44 AP13
C9 AC28 AB13
INTREPID-REV2.1 AP16
BGA
F12 AE31 AB15 (9 OF 9) K3
F15 AE34 AB17 K6
F18 AF28 AB19 N24
F21 AH30 AC17 N3
F24 AH34 AC19 N6
F27 VDD1.8/CPUVIO AK34 AC23 P13
M15 AP35 AD13 P14
M16 C35 AD15 POWER R22
M19 G31 AD22 T12
M22 G34 P15 T18
M23 K31 P18 T3
N18 K34 P20 VDD3.3 T6
N21 VDD2.5 N28 P21 U12
N23 N31
VDD1.5
R17 W12
P16 N34
C P19 N36
R20
T13
W13
W3
C
P25 U17 W6
P28
POWER/GROUND U18 AP2
R25 U24 AP7
R27 V16 AR3
T25 V19 B3
T28 V20 C2
T29 V22 C6
T31 W16 D32
T34 W24 D5
U25 Y13 B34
U28 Y18 E4
L24
M14
V25
V29 1.5V LDO GENERATOR
M17 W25 THIS LDO WAS ADDED IN CASE INTREPID CORE DOES NOT RUN AT 1.5V
M18 W31 NO STUFF
M20 W34
M21 Y27
+1_8V_MAIN R1603
AD28 LTC1962_1V5_VOUT 1
0 2
M24 Y29 38 +1_5V_LDO 19 35 38
NO STUFF
M28 E33 AD3 5%
1
M3 AD31 R1600 NO STUFF
1/16W
MF
AD34
0 NO STUFF 1
603
M31 AN33 5%
1/16W
NO STUFF R1601
M32 AN4 AD6
GROUND MF U1600 C1601 1 15.8K
M34 AP1 AE14 2 603 LT1962-ADJ 0.01UF 1%
1/16W
20% MF
AE16 MSOP 16V
M6 AP12 8 OUT 1 CERM 2 2 402 NO STUFF
AE18
38 LTC1962_1V5_VIN IN 402
M9 AP15 1 C1602
B N15
N25
AP18
AP21
AE19
AE21 U19
NC 7
6
NC
ADJ 2 LT1962_1V5_ADJ
10UF
20%
6.3V
B
AE22 U22
NO STUFF NC NC 2 CERM
NO STUFF
P12 AP24 1 C1600 1
805
P17 AP27 AE28 U27
20%
1UF BYP 3 LT1962_1V5__BYP R1602
P22 AP3 AG21 U29 10V
5 SHDN GND 4 68.1K
2 CERM 1%
P29 AP30 AG23 V10 603 1/16W
MF
P4 AP33 AG24 V12 2 402
R14 AP34 AG3 V17
VSS AG30 V18
R16 AP36
R18 AP6 AG34 VSS V21
R19 AP9 AG6 V24
VSS AH20 V3
R21 AR2
R23 AR35 AH21 V31
R24 AT3 AH23 V34
R26 AT34 AH27 V6
R29 B2
VSS W11
R3 B35 AK3 W14
R31 C1 AK7 W23
R34 C10 AL12 W26
R6 C13 AL15 Y11
T11 C16 AL18 Y12
T14 C19 AL21 Y14
T23 C22 AL27 Y16
T24 C25 AL31 Y19
T27
U10
C28
C3
AL34
AL6
Y23
Y24 Intrepid Power
A U16 C31 AL9 Y25
NOTICE OF PROPRIETARY PROPERTY
A
C34
AGP_IO_VSS
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
A3
A34
AA20
AA27
AA3
AA31
AA34
AA6
AB11
AB12
AB14
AB16
AB18
AB24
AB28
AB29
AC11
AC15
AC16
AC18
AC20
AC22
AC26
AD12
AD23
AD25
J6
J34
J31
J3
G7
F6
F34
F31
F3
F28
F25
F22
F19
F16
F13
F10
D4
D33
C7
C36
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 16 44
8 7 6 5 4 3 2 1
CR-17
8 7 6 5 4 3 2 1
+1_5V_MAIN
24 Balls 30 Balls
MAXBUS_SLEEP
23 16 9 7 5
INTREPID MAXBUS DECOUPLING 4 X 10UF (0805) 4 X 10UF (0805)
38 34
32 X 0.22UF (0402) INTREPID CORE DECOUPLING 29 X 0.22UF (0402)
C11 1 C326 1 1 C218 1 C219 1 C328 1 C298 1 C160 1 C269 1 C299 1 C96 1 C267 1 C142 C124 1 C103 1 1 C136 1 C222 1 C243 1 C221 1 C206 1 C165 1 C131 1 C192 1 C259 1 C245
10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 402 402 402 402 402 402 402 402 402 402 805 805 402 402 402 402 402 402 402 402 402 402
D C215 1 C181 1 1 C158 1 C183 1 C240 1 C216 1 C217 1 C97 1 C113 1 C220 1 C241 1 C300 C154 1 C301 1 1 C223 1 C189 1 C162 1 C163 1 C161 1 C143 1 C145 1 C146 1 C261 1 C260 D
10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
805 805 402 402 402 402 402 402 402 402 402 402 805 805 402 402 402 402 402 402 402 402 402 402
1 C157 1 C155 1 C159 1 C205 1 C156 1 C184 1 C114 1 C268 1 C115 1 C327 1 C133 1 C225 1 C188 1 C244 1 C164 1 C190 1 C175 1 C185 1 C191
0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
+3V_MAIN
1 C182 1 C186
0.22uF 0.22uF 57 Balls
20% 20%
6.3V 6.3V
4 X 10UF (0805)
2 CERM
402
2 CERM
402 INTREPID 3.3V DECOUPLING 72 X 0.22UF (0402)
38 20 19 16 13 +1_5V_AGP C148 1 C377 1 1 C355 1 C329 1 C56 1 C46 1 C23 1 C169 1 C38 1 C132 1 C119 1 C117
21 Balls 10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
INTREPID AGP I/O DECOUPLING 4 X 10UF (0805) 6.3V 2
CERM
6.3V 2
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
805 805 402 402 402 402 402 402 402 402 402 402
24 X 0.22UF (0402)
C336 1 C210 1 1 C334 1 C279 1 C249 1 C194 1 C333 1 C248 1 C229 1 C280 1 C357 1 C193 C12 1 C10 1 1 C40 1 C168 1 C47 1 C42 1 C242 1 C63 1 C55 1 C177 1 C60 1 C21 C
C 10uF
20%
10uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
10uF
20%
10uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 402 402 402 402 402 402 402 402 402 402 805 805 402 402 402 402 402 402 402 402 402 402
C262 1 C374 1 1 C207 1 C209 1 C246 1 C358 1 C335 1 C208 1 C311 1 C373 1 C310 1 C309 1 C17 1 C106 1 C58 1 C39 1 C121 1 C49 1 C79 1 C258 1 C35 1 C33
10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
1 C230 1 C247 1 C228 1 C41 1 C26 1 C116 1 C135 1 C130 1 C37 1 C134 1 C98 1 C57 1 C53
0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402 402 402 402
1 C78 1 C118 1 C54 1 C62 1 C147 1 C122 1 C100 1 C107 1 C59 1 C34
38 16 11 10 +2_5V_INTREPID 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
44 Balls 20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
INTREPID DDR DECOUPLING 4 X 10UF (0805)
51 X 0.22UF (0402)
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
C403 1 C397 1 1 C389 1 C371 1 C293 1 C303 1 C272 1 C370 1 C350 1 C306 1 C345 1 C346 1 C278 1 C227 1 C187 1 C61 1 C25 1 C22 1 C64 1 C48 1 C36 1 C27
B 10uF
20%
6.3V
10uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
0.22uF
20%
6.3V
B
CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
C398 1 C402 1 1 C347 1 C274 1 C277 1 C385 1 C273 1 C330 1 C308 1 C372 1 C365 1 C356 1 C167 1 C19 1 C52 1 C43 1 C18 1 C101 1 C378 1 C120 1 C123 1 C102
10uF 10uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V
2 CERM
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
805 805 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
1 C307 1 C304 1 C381 1 C392 1 C321 1 C349 1 C364 1 C276 1 C388 1 C387
0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
1 C386 1 C382 1 C366 1 C270 1 C367 1 C383 1 C332 1 C369 1 C292 1 C380
0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402
1 C323 1 C271 1 C384 1 C379 1 C348 1 C320 1 C368 1 C275 1 C305 1 C322
Intrepid Decoupling
A 0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20%
0.22uF
20% NOTICE OF PROPRIETARY PROPERTY
A
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 C302 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
0.22uF
20%
2 6.3V
CERM SIZE DRAWING NUMBER REV.
402
D 051-6469 F
APPLE COMPUTER INC.
SCALE SHT OF
NONE
17 44
8 7 6 5 4 3 2 1
CR-18
8 7 6 5 4 3 2 1
PCI1510 PULL-UPS +3V_MAIN
39 30 26 24 21 19 18 MAIN_RESET_L
THIS PROPERLY SHUTS DOWN
CARDBUS POWER FOR PSUEDO-D3COLD
+3V_MAIN
+3V_MAIN
1 C579 1 C761 1 C764 1 C755 1
R774
10UF 0.22UF 0.22UF 0.22UF 47
20% 20% 20% 20%
R670 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
5%
1/16W
+5V_MAIN MAKE SURE VCC AND VPP ARE WIDE PLANE/TRACES
10K
D
1
5%
2 CBUS_PCI_PERR_L 18
805 402 402 402 MF
2 402
U20 TO MINIMIZE INDUCTANCE! D
R669 1/16W
MF NO STUFF TPS2211
10K 402 NC 9
V_12 SSOI AVPP
10 +VPP_CBUS_SW 18 38
1 2 CBUS_PCI_SERR_L 18
R2991 5
5% 1 C762 1 C763 1 C756 10K 6
V_5_1
11
1/16W
MF R662 0.22UF 0.22UF 0.22UF 5%
1/16W V_5_2 AVCC0 38 18 +VCC_CBUS_SW
402 10K 20% 20% 20% MF 3
V_3_1 AVCC1
12
1 2 CBUS_SUSPEND_PU 18
2 6.3V 2 6.3V 2 6.3V
CERM 402 2
CERM CERM 4 13
5% 402 402 402 V_3_2 AVCC2
1/16W
MF
402 R676 1 1
VCCD0 C739 1 1 C448
10K 2 0.1UF 0.1UF
5% VCCD1 20%
10V
20%
10V
1/16W 15
VPPD0 CERM 2 2 CERM
MF 402 402
+2_5V_MAIN 402 2 14
VPPD1
TPS2211_SHDN_L_PU 16
SHTDWN
A7 C13 D5 E1 M1 N7 N11
7 8 NC
GND OC
1 C754 VCC
0.22UF H10 CRITICAL B11 0.1UF ARE USED TO INCREASE ESD DISCHARGES OF UP TO 10KV
20% NC CLK_48_RSVD/NC CLAMP FOR PC-CARD VCCCB
2 6.3V CLAMP FOR PCI VCCP L3
CERM
402 PCI1510_VR_EN_L D4
VR_EN* U26
L8 VR_PORT PCI1510GGU VCCD0* N13 CBUS_VCCD0_L
BGA
VCCD1* L12 CBUS_VCCD1_L
39 37 26 24 13 10 PCI_AD<0> N8 AD0
39 37 26 24 13 10
39 37 26 24 13 10
PCI_AD<1>
PCI_AD<2>
M7
L7
AD1
AD2
VPPD0
VPPD1
K9
M11 CBUS_VPPD1
CBUS_VPPD0
PC CARD/CARDBUS CONNECTOR
39 37 26 24 13 10 PCI_AD<3> N6 AD3 CRITICAL
CD1*/CCD1* L13 CBUS_DET_1_L 18 39
39 37 26 24 13 10 PCI_AD<4> K4 AD4 B5 J10
PCI_AD<5> M6 AD5 CD2*/CCD2* CBUS_DET_2_L 18 39
QT500806-L111
39 37 26 24 13 10
IORD*/CAD13 F12 CBUS_IORD_L 18 M-ST-SM
39 37 26 24 13 10 PCI_AD<6> L6 AD6 C11 84 81
IOWR*/CAD15
C 39 37 26 24 13 10
39 37 26 24 13 10
PCI_AD<7>
PCI_AD<8>
N5
N4
AD7
AD8
OE*/CAD11 G10
CBUS_IOWR_L
CBUS_OE_L
18
18
C
CE1*/CC/BE0* H13 CBUS_CE1_L 18 2 1 CBUS_DATA<3> 18
39 37 26 24 13 10 PCI_AD<9> M2 AD9 B2 4 3
M5 VS1*/CVS1 CBUS_VS1 18 39 18 CBUS_DET_1_L CBUS_DATA<4> 18
39 37 26 24 13 10 PCI_AD<10> AD10 VS2*/CVS2 A9 CBUS_VS2 18 18 CBUS_DATA<11> 6 5 CBUS_DATA<5> 18
L4
39 37 26 24 13 10 PCI_AD<11> AD11 WE*/CGNT* D13 CBUS_WE_L 18 18 CBUS_DATA<12> 8 7 CBUS_DATA<6> 18
39 37 26 24 13 10 PCI_AD<12> N3 AD12 RDY/IREQ*/CINT* A6 CBUS_READY 18 18 CBUS_DATA<13> 10 9
K5
39 37 26 24 13 10 PCI_AD<13> AD13 RESET/CRST* D8 CBUS_RESET_L 18 12 11 CBUS_DATA<7> 18
39 37 26 24 13 10 PCI_AD<14> L5 AD14 REG*/CC/BE3* A8 CBUS_REG_L 18 18 CBUS_DATA<14> 14 13 CBUS_CE1_L 18
M4
39 37 26 24 13 10 PCI_AD<15> AD15 BVD1/CSTSCHG/STSCHG*/RI* C6 CBUS_BVD1_L 18 18 CBUS_DATA<15> 16 15 CBUS_ADDR<10> 18
39 37 26 24 13 10 PCI_AD<16> J4 AD16 BVD2/SPKR*/CAUDIO D6 CBUS_BVD2_L 18 18 CBUS_CE2_L 18 17 CBUS_OE_L 18
H1
39 37 26 24 13 10 PCI_AD<17> AD17 INTEGRATED PULL-UP WP/IOIS16*/CCLKRUN* A5 CBUS_WP_L 18 18 CBUS_VS1 20 19
H3
39 37 26 24 13 10 PCI_AD<18> AD18 CE2/CAD10* G13 CBUS_CE2_L 18 22 21 CBUS_ADDR<11> 18
PCI_AD<19> H2 AD19
G2
INPACK/CREQ* B8 CBUS_INPACK_L 18 18 CBUS_IORD_L 24 23 CBUS_ADDR<9> 18
39 37 26 24 13 10 PCI_AD<20> AD20 WAIT/CSERR* B6 CBUS_WAIT_L 18 18 CBUS_IOWR_L 26 25 CBUS_ADDR<8> 18
39 37 26 24 13 PCI_AD<21> G4 AD21 18 CBUS_ADDR<17> 28 27 CBUS_ADDR<13> 18
F1 A0/CAD26 C7 CBUS_ADDR<0>
39 37 26 24 13 PCI_AD<22> AD22 18
18 CBUS_ADDR<18> 30 29
39 37 26 24 13 PCI_AD<23> C3 AD23 A1/CAD25 D7 CBUS_ADDR<1> 18
32 31 CBUS_ADDR<14> 18
F3 A2/CAD24 B7 CBUS_ADDR<2>
39 37 26 24 13 10 PCI_AD<24> AD24 18
18 CBUS_ADDR<19> 34 33 CBUS_WE_L 18
39 37 26 24 13 10 PCI_AD<25> E2 AD25 A3/CAD23 D10 CBUS_ADDR<3> 18
18 CBUS_ADDR<20> 36 35 CBUS_READY 18
PCI_AD<26> F4 A4/CAD22 B12 CBUS_ADDR<4>
39 37 26 24 13 10 AD26 18
18 CBUS_ADDR<21> 38 37 +VCC_CBUS_SW 18 38
B1 A5/CAD21 C8 CBUS_ADDR<5> TI REFERENCE SCHEMATIC DID NOT HAVE BULK ON +VCC_CBUS_SW
39 37 26 24 13 10 PCI_AD<27> AD27 18
38 18 +VCC_CBUS_SW 40 39
39 37 26 24 13 10 PCI_AD<28> D2 AD28 A6/CAD20 C9 CBUS_ADDR<6> 18
42 41 +VPP_CBUS_SW 18 38
E4 A7/CAD18 A12 CBUS_ADDR<7>
39 37 26 24 13 10 PCI_AD<29> AD29 18
+VPP_CBUS_SW 44 43 CBUS_ADDR<16>
39 37 26 24 13 10 PCI_AD<30> D3 AD30 A8/CC/BE1* E11 CBUS_ADDR<8> 18
1 C748 1 C742 38 18
CBUS_ADDR<22> 46 45 CBUS_ADDR<15>
18
R6841 39 37 26 24 13 10 PCI_AD<31> E3
AD31 A9/CAD14 F11 CBUS_ADDR<9> 18
2.2UF 2.2UF 18 18
20% 20% 18 CBUS_ADDR<23> 48 47 CBUS_ADDR<12> 18
22 10V 2 10V
K6 A10/CAD9 G11 CBUS_ADDR<10> 18 2 CERM CERM 50 49
5% PCI_CBE<0> C/BE0* CBUS_ADDR<24>
B 1/16W
MF
402 2
39 37 26 24 13
39 37 26 24 13 PCI_CBE<1> M3
J2
C/BE1*
A11/CAD12 G12
A12/CC/BE2* D9
CBUS_ADDR<11>
CBUS_ADDR<12>
18
18
805 805 18
52
54
51
53
CBUS_ADDR<7> 18 B
39 37 26 24 13 PCI_CBE<2> C/BE2* A13/CPAR E12 CBUS_ADDR<13> 18
18 CBUS_ADDR<25> CBUS_ADDR<6> 18
39 37 26 24 13 PCI_CBE<3> A1 C/BE3* 18 CBUS_VS2 56 55 CBUS_ADDR<5> 18
A14/CPERR* D12 CBUS_ADDR<14> 18
58 57
39 37 26 24 13 PCI_PAR N1 PAR A15/CIRDY* C10 CBUS_ADDR<15> 18
R661 18 CBUS_RESET_L CBUS_ADDR<4> 18
K1
47 18 CBUS_WAIT_L 60 59
39 37 26 24 13 PCI_IRDY_L IRDY A16/CCLK B13 CBUS_ADDR_16_UF 1 2 CBUS_ADDR<16> 18
62 61 CBUS_ADDR<3> 18
18 CBUS_PCI_SERR_L L2 SERR A17/CAD16 F10 CBUS_ADDR<17> 18 5%
1/16W 18 CBUS_INPACK_L 64 63 CBUS_ADDR<2> 18
CBUS_PCI_IDSEL F2 IDSEL A18/RSVD E13 CBUS_ADDR<18> 18 MF
402 18 CBUS_REG_L 66 65 CBUS_ADDR<1> 18
18 CBUS_PCI_PERR_L K3 PERR A19/CBLOCK* A13 CBUS_ADDR<19> 18
18 CBUS_BVD2_L 68 67 CBUS_ADDR<0> 18
39 37 26 24 13 PCI_FRAME_L J1 FRAME A20/CSTOP* E10 CBUS_ADDR<20> 18
CBUS_BVD1_L 70 69
18
39 37 26 24 13 PCI_STOP_L L1 STOP A21/CDEVSEL* D11 CBUS_ADDR<21> 18
NO STUFF 72 71 CBUS_DATA<0> 18
39 37 26 24 13 PCI_TRDY_L J3 TRDY A22/CTRDY* C12 CBUS_ADDR<22> 18
74 73
R675 39 37 26 24 13 PCI_DEVSEL_L K2 DEVSEL A23/CFRAME* A10 CBUS_ADDR<23> 18
18 CBUS_DATA<8> CBUS_DATA<1> 18
47 18 CBUS_DATA<9> 76 75 CBUS_DATA<2> 18
30 27 26 23 19 IO_RESET_L 1 2 CBUS_PCI_RESET_L G3 PRST A24/CAD17 B10 CBUS_ADDR<24> 18
78 77
18 CBUS_DATA<10> CBUS_WP_L 18
5% 13 CBUS_PCI_REQ_L C2 REQ A25/CAD19 B9 CBUS_ADDR<25> 18
1/16W 39 18 CBUS_DET_2_L 80 79
MF 13 CBUS_PCI_GNT_L C1 GNT
402 D0/CAD27 A4 CBUS_DATA<0> 18
36 13 CLK33M_CBUS G1 PCLK C4 83 82
D1/CAD29 CBUS_DATA<1> 18
D2/RSVD A3
R763 CBUS_DATA<2> 18
RP38 MAIN_RESET_L 1
47 2
NC M9 SPKROUT D3/CAD0 K11 CBUS_DATA<3> 18
10K 39 30 26 24 21 19 18
NC M8 RI_OUT/PME D4/CAD1 K12 CBUS_DATA<4> 18
5% 5%
1/32W N10 SUSPEND J13
25V 1/16W
MF
18 CBUS_SUSPEND_PU D5/CAD3 CBUS_DATA<5> 18
402
CBUS_INT_L K7 MFUNC0 D6/CAD5 J10 CBUS_DATA<6> 18
5 6 CBUS_MFUNC1_PD 15
18
D7/CAD7 H12 CBUS_DATA<7> 18
10 4 CBUS_MFUNC2_PD 18 CBUS_MFUNC1_PD N9 MFUNC1 C5
18
D8/CAD28 CBUS_DATA<8> 18
A
7
3
CBUS_MFUNC3_PD
CBUS_MFUNC4_PD
18
18
18
18
CBUS_MFUNC2_PD
CBUS_MFUNC3_PD
L9
K10
MFUNC2
MFUNC3
D9/CAD30
D10/CAD31
B4
B3
CBUS_DATA<9>
CBUS_DATA<10>
18
CARDBUS
9
8
CBUS_MFUNC5_PD
CBUS_MFUNC6_PD
18
18
18
CBUS_MFUNC4_PD
CBUS_MFUNC5_PD
M10
N12
MFUNC4
MFUNC5
D11/CAD2 M12 CBUS_DATA<11>
18
18
NOTICE OF PROPRIETARY PROPERTY
A
18
D12/CAD4 J11 CBUS_DATA<12> 18
2 18 CBUS_MFUNC6_PD L10 MFUNC6
D13/CAD6 K13 CBUS_DATA<13> 18 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
D14/RSVD J12 CBUS_DATA<14> 18 AGREES TO THE FOLLOWING
L11 GRST H11
SM D15/CAD8 CBUS_DATA<15> 18 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
GND II NOT TO REPRODUCE OR COPY IT
A2 A11 D1 F13 H4 K8 M13 N2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6469 F
APPLE COMPUTER INC.
SCALE SHT OF
NONE 18 44
8 7 6 5 4 3 2 1
CR-19
8 7 6 5 4 3 2 1
MEMORY CORE - 2.5V +2_5V_GPU_FB 19 38
IMPORTANT NOTES ON MAP17
NEED TO RESET GRAPHIC CHIP DURING RESTARTS
1 C264 1 C289 1 C283 1 C288 1 C104 1 C93 1 C84 1 C251 1 C94
10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM
10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM
805 402 402 402 402 402 402 402 402
AGP 4X I/O - 1.5V 38 19 +2_5V_GPU_FB
MEMORY I/O - 2.5V U43
U43 U43 MAP31-64MB D
D MAP31-64MB 38 20 19 17 16 13 +1_5V_AGP
AB27
MAP31-64MB AB25
BGA L26
BGA BGA (4 OF 5) L29
BULK CAP ON INTREPID SIDE (3 OF 5) AB6 L5
(1 OF 5) L7
37 13 AGP_AD<0> AD30
PCIAD0 VDDAGP0 AF30 1 C170 1 C80 1 C67 1 C81 AD27 AD25
OMIT
37 13 AGP_AD<1> AE30
PCIAD1 VDDAGP1 AG14 10UF 0.1UF 0.1UF 0.1UF AD4 OMIT AD6 M12
20% 20% 20% 20% M13
37 13 AGP_AD<2> AD29
PCIAD2 OMIT VDDAGP2 AG17 1 C44 1 C92 1 C125 1 C150 6.3V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM AE26 AE22 M14
M15
37 13 AGP_AD<3> AE29
PCIAD3 VDDAGP3 AG20 0.1UF 0.1UF 0.1UF 0.1UF 805 402 402 402 AE5 AE24 M16
20% 20% 20% 20% M17
AD28 AK14 2 10V 10V 2 10V 10V AF25 AE7 AB24 M18
37 13 AGP_AD<4> PCIAD4 VDDAGP4 CERM 2 CERM CERM 2 CERM AB26 M19
AG30 AK17 402 402 402 402 AF27 AE9 AB5
37 13 AGP_AD<5> PCIAD5 VDDAGP5 VDDFBC AB7
AF28 VDDAGP6 AK20 AF4 F22 AC2
37 13 AGP_AD<6> PCIAD6
AGP_AD<7> AG29
PCIAD7 VDDAGP7 AK23
1 C317 1 C85 1 C72 AF6 F24
AC29
AD11 N12
37 13
0.1UF 0.1UF 0.1UF AD14 N13
AH30 VDDAGP8 AK26 20% 20% 20% F7 N14
37 13 AGP_AD<8> PCIAD8 10V
2 CERM
10V 10V AD20 N15
2 CERM 2 CERM
37 13 AGP_AD<9> AC28
PCIAD9 VDDAGP9 AK29 1 C65 1 C149 1 C196 1 C28 402 402 402
AG24 F9 AD22
AD24
N16
N17
37 13 AGP_AD<10> AH29
PCIAD10 0.01UF 0.01UF 0.01UF 0.01UF AG26 G25 AD26 N18
20% 20% 20% 20% AD5 N19
AE28 2 16V 16V 2 16V 16V AG5 G6 AD7
37 13 AGP_AD<11> PCIAD11 CERM 2 CERM CERM 2 CERM AD9
AJ30 402 402 402 402 AG7 J25 AE25
37 13 AGP_AD<12> PCIAD12 AE27
37 13 AGP_AD<13> AG28
PCIAD13 1 C282 1 C318 1 C254 1 C313 VDDFBIO0
J6 AE4
AE6
P12
P13
37 13 AGP_AD<14> AK30
PCIAD14 0.1UF 0.1UF 0.1UF 0.1UF D22 AF11 P14
20% 20% 20% 20% AF14 P15
AG27 10V 10V 2 10V 10V D24 AF17 P16
37 13 AGP_AD<15> PCIAD15 2 CERM 2 CERM CERM 2 CERM AF2 P17
AH23 402 402 402 402 D26 AF20 P18
37 13 AGP_AD<16> PCIAD16 HARDWARE DEBUG PORT AF22 P19
AJ24 D5 AF24
37 13 AGP_AD<17> PCIAD17 K4 GPU_VIPD0_TP AF26
AH22 D7 AF29 P24
37 13 AGP_AD<18> PCIAD18 J3 AF5 P26
37 13 AGP_AD<19> AK24
AH21
PCIAD19 AGP I/O REFERENCE E25
D9
H3
GPU_VIPD1_TP
GPU_VIPD2_ROMTYPE<1> 21
AF7
AF9
AG25
P29
P7
37 13 AGP_AD<20> PCIAD20 (PLACE CLOSE TO NV17M AGP BALLS) 1 C105 1 C314 1 C294 1 C66 K5 AG6
GPU_VIPD3_PCI_DEVID<2> 21
AJ22 0.01UF 0.01UF 0.01UF 0.01UF E27 VIPD AH12 R12
37 13 AGP_AD<21> PCIAD21 20% 20% 20% 20% G2 GPU_VIPD4_PCI_DEVID<0> 21
R13
AH20 E4 AJ11 R14
37 13 AGP_AD<22> PCIAD22 38 20 19 17 16 13 +1_5V_AGP 16V
2 CERM
16V
2 CERM
16V
2 CERM
16V
2 CERM G1 GPU_VIPD5_PCI_DEVID<1> AJ14 R15
C 37 13
37 13
AGP_AD<23>
AGP_AD<24>
AK22
AG21
PCIAD23
PCIAD24
402 402 402 402
F26
E6
F1
G3
GPU_VIPD6_CRYSTAL<1>
21
21
AJ17
AJ2
AJ20
AJ23
R16
R17
R18
R19
C
GPU_VIPD7_TP
AJ19 F5 AJ26
37 13 AGP_AD<25> PCIAD25 1 AJ29
37 13 AGP_AD<26> AG18 PCIAD26 R22 G27 VIPHAD0 C8 GPU_VIPHAD0_TP AJ5
B11
AK19 4.99K G4 C7 B14
37 13 AGP_AD<27> PCIAD27 1% VIPHAD1 GPU_VIPHAD1_TP B17 GND GND T12
T13
AG19 1/16W J27 B2 T14
37 13 AGP_AD<28> PCIAD28 MF
402 2 VIPHCLK A5 GPU_VIPHCLK_TP +2_5V_GPU_FB 19 38 B20 T15
AJ18 J4 B23 T16
37 13 AGP_AD<29> PCIAD29 B6 B26 T17
AF19 VIPHCTL GPU_VIPHTCL_TP T18
37 13 AGP_AD<30> PCIAD30 A24 B7 MAP31 B5 T19
AK18
GPU_AGP_VREF 19 38
FB SIGNALS USED FOR INTERNAL TESTING ONLY NC FBAA0_0 VIPPCLK VIPPCLK_PD
2 B8
D3COLD 37 13 AGP_AD<31> PCIAD31
CHANGE TO NC FOR NEXT SYMBOL UPDATE NC B10
FBAA0_1 R31 D25
D6
49.9
R601 R28 1
C21 FBCLK0
1%
E11
E14 U12
MAIN_RESET_L 1
47 2 37 13 AGP_CBE<0> AH28
PCICBE0* A1 4.99K
1 C13 36 19 GPU_FBCLK0
C20
1/16W
MF
E17
E2
U13
U14
39 30 26 24 21 18
AJ27 NC 1% 0.22UF 36 19 GPU_FBCLK0_L FBCLK0* 1 402 E20 U15
5% 37 13 AGP_CBE<1> PCICBE1* A10 NC 1/16W 20% B4 E22 U16
1/16W AK25 MF 6.3V
2 CERM 38 19 +2_5V_GPU_FB 36 19 GPU_FBCLK1 FBCLK1 E24 U17
MF 37 13 AGP_CBE<2> PCICBE2* A11 NC 402 2 A4 G30 E26 U18
402 AF21 402 36 19 GPU_FBCLK1_L FBCLK1* MEM_CAL_PD MEM_CAL_PD E29 U19
37 13 AGP_CBE<3> PCICBE3* N28 J30 E5
D3HOT GPU_FBACKE FBACKE MEM_CAL_PU MEM_CAL_PU E7
A13 NC FBACKE PULL-DOWN IS NEEDED D28 K30 E9 U24
R155 AJ12 NC FBD1 MEM_CAL_CLK MEM_CAL_CLK F25 U26
47
36 13 CLK66M_GPU_AGP PCICLK A14 NC R1900 1 D13 F27 U29
1 2 AH11 NC FBD33 MAP31 F4 U7
30 27 26 23 18 IO_RESET_L AGP_GPU_RESET_L PCIRST* A15 NC 10K MAP31
5%
A16 NC USE SIMPLE REFERENCE TO CHIP 5%
1/16W
R1731 R301 1
R29 F6
G11
G14 V12
1/16W
AG12 BECAUSE SINGLE AGP PWR PLANE AND CLOSE PROXIMITY OF CHIPS MF NC AA27 FBD8_0 10K 49.9 G17 V13
MF 37 13 AGP_GNT_L PCIGNT* A17 NC 402 2 J28 5% 49.9 1% G20 V14
402
AK12 NC FBD8_1 1/16W 1% 1/16W G22 V15
MAIN_RESET_L IS TOGGLED FOR SLEEP
37 13 AGP_REQ_L PCIREQ* GPU_FB_VREF A18 FBVREF
MF
402 2
1/16W
MF
MF G24 V16
2 402
38
G26 V17
A2 402 2 G5 V18
IO_RESET_L IS NOT TOGGLED FOR SLEEP AH24 NC THERE’S NO ON-CHIP VOLTAGE DIVIDER G7 V19
37 13 AGP_FRAME_L PCIFRAME* A20 NC G9
37 13 AGP_IRDY_L AJ25 PCIIRDY* A21 NC FRAME BUFFER CLOCK TERMINATION R19011 R351 H2
H29
37 13 AGP_TRDY_L AH25
PCITRDY* 10K 10K NC C11 FBAWE* FBDQS0 F28 NC
J24
A22 NC 5% 5%
J26 W12
AK27 1/16W AA26 J5 W13
37 13 AGP_DEVSEL_L PCIDEVSEL* A23 NC +2_5V_GPU_FB 19 38 MF 1/16W
MF
FBDQS1 NC J7 W14
AH26 402 2 J1 ROMA14 K28 W15
37 13 AGP_STOP_L PCISTOP* A25 NC 402 2 GPU_ROMA14_TP FBDQS2 NC W16
B R115
0
37 13 AGP_PAR AH27
PCIPAR A26 NC
NO STUFF
GPU_ROMA15_TP
GPU_ROMCS_TP AH2
F2 ROMA15
ROMCS*
FBDQS3 E12 NC
W17
W18
W19
B
AGP_WBF_L 1 2 A27 NC
13
5%
15 AGP_NV_INT_L AK11
PCIINTA* A28 NC R72
1/16W 37 13 AGP_RBF_L AJ13 AGPRBF* 1
120 2 GPU_FBCLK0 19 36
R99 MF
402 AGP_NV_WBF_L AG15
AGPWBF* A3 5%
1
0 2 AF18 NC 1/16W NO STUFF
13 AGP_PIPE_L AGP_NV_PIPE_L AGPPIPE* MF
1
5%
1/16W
13 AGP_ST<0> AF12
AGPST0 AA28 NC
402
R82
MF AGP_ST<1> AF13
AGPST1 100
402
13
13 AGP_ST<2> AG13
AGPST2 NC
AA29 NC
AA30 NC
NO STUFF
R83
5%
1/16W
MF
2 402
D3HOT VS. D3COLD POWER INTAKE Y24
Y26
AA4 NC Y29
37 13 AGP_AD_STB<1> AK21 AGPADSTB1 1
120 2
Y5
AA5 NC GPU_FBCLK0_L 19 36 Y7
AJ21 +1_5V_MAIN +1_5V_SLEEP L24
38 20 19 17 16 13 +1_5V_AGP 37 13 AGP_AD_STB_L<1> AGPADSTB1* AB28 NC 5% 38 35 16 +1_5V_LDO
MAP31 AK28 1/16W +3V_MAIN +3V_SLEEP
37 13 AGP_AD_STB<0> AGPADSTB0 AB29 NC MF
1
R128
49.9
37 13 AGP_AD_STB_L<0> AJ28
AGPADSTB0* AB30 NC
B1
402
D3HOT D3COLD
1.5V 1
NO STUFF
1
D3HOT
1
D3COLD
R634
1%
1/16W 13 AGP_BUSY_L AF10
AGPBUSY*
NC 1
R245 1
R244 R1605 R635 0
B13 NC 0 0
MF
2 402 13 STOP_AGP_L AG10
AH15
AGPSTOP* B15 NC
B16 NC
3V 5%
0
1/10W
5%
0
1/10W
5%
1/16W
MF
5%
1/16W
MF
5%
1/16W
MF
AGP_CAL_PD AGP_CAL_PD +2_5V_GPU_FB 19 38 FF FF 2 603 2 603 2 603
AH14 B18 NC 2 805 2 805
AGP_CAL_PU AGP_CAL_PU
MAP31 +1_5V_AGP
NC AH19 AGP_DBI_LO B19 NC
+3V_GPU 13 15 20 21 38
13 16 17 19 20 38
1
R136 FOR AGP 8X NC AK13 AGP_MB_DET* B21 NC NO STUFF
INTREPID AGP IS ALSO CONNECTED TO +1_5V_AGP
1%
49.9 B22 NC R186
1/16W AC30 B24 NC 1
120 2
MF 38 19 GPU_AGP_VREF AGPVREF GPU_FBCLK1 19 36
2 402 B25 NC 5%
37 13
37 13
AGP_SBA<0>
AGP_SBA<1>
AJ15
AF15
AGPSBA0
AGPSBA1
B27 NC
1/16W
MF
402 1
R185
NO STUFF
MAP17 AGP/DDR RAM
A 37 13 AGP_SBA<2> AK15
AG16
AGPSBA2
B28 NC
B3 NC 5%
100
+2_5V_MAIN +2_5V_SLEEP NOTICE OF PROPRIETARY PROPERTY
A
37 13 AGP_SBA<3> AGPSBA3 NO STUFF 1/16W
AK16 MF
37 13 AGP_SBA<4>
AF16
AGPSBA4 C1 NC R191 2 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
37 13 AGP_SBA<5> AGPSBA5 C10 NC 1
120 2
D3HOT D3COLD AGREES TO THE FOLLOWING
GPU_FBCLK1_L 19 36
AJ16
37 13 AGP_SBA<6> AGPSBA6 C13 NC 5%
1
R648 1
R647 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
AGP_SBA<7> AH18 AGPSBA7 1/16W 0 0
37 13
37 13 AGP_SB_STB AH16
AGPSBSTB
C14 NC
C15 NC
MF
402 2.5V 5%
1/10W
FF
5%
1/10W
FF
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
AH17 C16 NC 2 805 2 805
37 13 AGP_SB_STB_L AGPSBSTB* SIZE DRAWING NUMBER REV.
+2_5V_GPU_FB 19 38
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 19 44
8 7 6 5 4 3 2 1
CR-20
8 7 6 5 4 3 2 1
+5V_MAIN
39 38 20 GPU_VCORE
38 19 17 16 13 +1_5V_AGP
R20021 R20031 1 C213 1 C212 1 C234 1 C126 1 C83 1 C71 1 C69 1 C82 TMDS TERMINATION
100K 100K 10UF 10UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
20% 20% 20% 20% 20% 20% 20% 20% TERMINATION NETWORK SHOULD BE CONNECTED AS SHOWN
5%
1/16W
5%
1/16W DP20 DP20 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM CMF LINE SHOULD BE ROUTED AS 4MIL SURFACE
MF MF BAS16TW BAS16TW 805 805 402 402 402 402 402 402
R20041 402 2 402 2 SOT-363 SOT-363 TRACE SO THAT IT MAY BE CUT BETWEEN CAPS
10K GPU_VCORE_PWR_SEQ 6 1 2 5 SLEEP_L_LS5 27 33 34 35
5% TMDS_D0_CMF
1/16W
MF
402 2
3 1 C286 1 C127 1 C197 1 C50 1 C128 1 C199 1 C284 1 C70
GPU_VCORE_SEQ_L
DP20 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF R236 R237
1 Q2000 20% 20% 20% 20% 20% 20% 20% 20% 49.9 1 49.9 1
D 3 2N3904
SM
BAS16TW
SOT-363
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402 I2C1 PULL-UP
39 37 22 21 TMDS_DP<0> 2
1%
2
1%
TMDS_DN<0> 21 22 37 39 D
2 3 4 DCDC_EN 1/16W 1/16W
GPU_VCORE_SEQ 1 Q2001 29 32 33 34 39
+3V_GPU 13 15 19 20 21 38
MF
402
MF
402
2N3904
SM
1 C151 C407 1 1 C406
2 1 C235 1 C198 1 C287 0.22UF
1 C233 1 C152 1 C285 1 C68 470PF
10%
470PF
10%
0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 2 1
1778_SHDN_L_D3COLD 20%
6.3V
20%
6.3V
20%
6.3V
20%
2 6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
R227 R218 50V
CERM 2 2 50V
CERM
2 CERM 2 CERM 2 CERM CERM 2 CERM 2 CERM 2 CERM 2 CERM 10K 10K 402 402
D3COLD 402 402 402 402 402 402 402 402 5% 5%
1/16W 1/16W
R20011 +PBUS
MF
402 1
MF
2 402
0
AE11
AE14
AE17
AE20
D11
D14
D17
D20
F11
F14
F17
F20
L25
L27
P25
P27
U25
U27
Y25
Y27
5%
L6
P6
U6
Y6
1/16W
MF VDDCORE
38 35 1_5V_2_5V_OK 402 2
38 21 20 19 15 13 +3V_GPU
D3HOT
’1’ DURING SHUTDOWN
’0’ DURING SLEEP/RUN R2000 U43 ADDR X36
0 MAP31-64MBTMDS I2C0SDA AJ4 GPU_DVI_DDC_DATA
35 33 DCDC_EN_L 2 1
1
R347
1 C728 1 C733 BGA I2C0SCL AK4
22
1 D3HOT
5%
1/16W 1 5 6 7 8 20%
4.7UF 4.7UF
20%
R1871 R1981 (5 OF 5)
VGA
ADDR X3E
GPU_DVI_DDC_CLK 22
R378 MF 5% 25V 25V 10K 10K AH4
2 CERM 2 CERM 5% 5% I2C1SDA GPU_I2C1SDA
5%
0 402 1/16W
MF CRITICAL 1206 1206 1/16W
MF
1/16W
MF
OMIT UNUSED
I2C1SCL AH5 GPU_I2C1SCL
1/16W 3 2 603 402 2 402 2
MF
402 2
Q42 ADDR X50
I2C2SDA AJ6 LVDS_DDC_DATA
TMDS_D1_CMF
D
Q12 4
IRF7805
GPU_SSCLK_S0 C6
GPIOD0
LVDS
I2C2SCL AK6 LVDS_DDC_CLK
22 39
2N7002DW 38 1778_VIN SM 21 22 39
R158 R157
5 SOT-363 ALL I2C ARE 5V TOLERANT
LTC1778_SHDN G S GPU_HPD A6 GPIOD1 49.9 1 49.9 1
GPU_VCORE 20 38 39
22
39 37 22 21 TMDS_DP<1> 2 2 TMDS_DN<1> 21 22 37 39
1 TXD0* P4 LVDS_L0N
D3HOT 4
C467 1 R281 1 2 3 CRITICAL 22 INV_ON_PWM A7 GPIOD2 ACTIVE HIGH
TXD0 P5 LVDS_L0P
22 37 39 1%
1/16W
1%
1/16W
C510 1 576K 22 37 39 MF MF
0.01UF
0.1UF 1% L25 22 27 26 FP_PWR_EN A8 GPIOD3 ACTIVE HIGH TXD1* R4 LVDS_L1N 22 37 39
402 402
1 20% 1/16W 3.8UH
20% R340 25V
CERM 2
MF TXD1 R5 LVDS_L1P C253 1 1 C252
C 16V
CERM 2
402
1M
5%
1/16W
603 2 402 38 GPU_VCORE_SW 1
SM
2 22 HPD_PWR_SNS_EN C9 GPIOD4 ONLY "GPIO"
TXD2* P3 LVDS_L2N
22 37 39
22 37 39
470PF
10%
50V
470PF
10%
50V
C
GPU_SSCLK_S1 B9 GPIOD5 TXD2 R3 LVDS_L2P
MF 21 22 37 39
CERM 2 2 CERM
2 402 P1 402 402
C5 TXD3* LVDS_L3N_SPN
C658 1 GPU_SUS_STAT_L_PU GPIOD6 P2
5 6 7 8 C682 1 TXD3 LVDS_L3P_SPN
22UF F3 K1
38 1778_VCC 20%
10V
330UF 20 GPU_VCORE_CNTL_L GPIOD7 TXC0* CLKLVDS_LN 22 37 39
CRITICAL 20%
1 CERM 2 6.3V 2 TXC0 K2 CLKLVDS_LP 22 37 39
B12 GPIOD8
+5V_MAIN D5 Q39 1210 POLY
SMD
GPU_GPIO8
NO STUFF 1 C453 1N914 IRF7811W GPU_GPIO9 C12 GPIOD9
SOT23 4
1
R283 4.7UF 3 SO-8 2 1
C680 C681 1 TXD4* U4 LVDS_U0N 22 37 39
0
20%
10V
2 CERM
D24 330UF 330UF MAP31 MAP31
GPIOS HAVE CLAMP TO 5V
TXD4 U5 LVDS_U0P
5%
38
SM 20% 20% R1671 1
R174 GPIOS ARE PLACED IN TRISTATE DURING SLEEP 22 37 39
R339 1778_BST_RC
1/16W 1206
1 2 3 MBRS130LT3 2 6.3V 6.3V 2
1 1 TXD5* T3 LVDS_U1N TMDS_D2_CMF
MF POLY POLY
R142 R150 10K 10K ONLY GPIO6 IS ENABLED 22 37 39
2 402
1778_GND 20 38 15 1 SMD SMD 5% 5% TXD5 U3 LVDS_U1P
NO STUFF 9 11 10
1 2 10K 10K 1/16W 1/16W 22 37 39
1
R284 EXT INT VIN 1%
5%
1/16W
5%
1/16W
MF
402 2
MF
2 402
TXD6* V4 LVDS_U2N 22 37 39 R241 R240
VCC VCC 1/16W MF MF TXD6 V5 LVDS_U2P 49.9 1 49.9 1
63.4K MF 402 2 2 402
22 37 39
39 37 22 21 TMDS_DP<2> 2 2 TMDS_DN<2> 21 22 37 39
1%
1/16W
U19 603
TXD7* W4 LVDS_U3N_SPN 1% 1%
MF
LTC1778 W5 LVDS_U3P_SPN 1/16W 1/16W
SSOP C481 1 TXD7 MF MF
2 402 1778_SHDN_L 1 RUN/SS ION 7 38 1778_ION 402 402
0.1UF TXC1* T4 CLKLVDS_UN 22 37 39
CRITICAL 20%
38 1778_ITH 5 ITH B00ST 16 38 1778_BST 25V
CERM 2 1 TXC1 T5 CLKLVDS_UP 22 37 39 C409 1 1 C410
TG 15 1778_TG 603 R276 470PF 470PF
1 38 1778_VRNG 3 VRNG
38
10K +3V_GPU 13
10%
50V
10%
50V
R282 SW 14 1%
1/16W
15 19 20 21 38
CERM 2
402
2 CERM
402
20K 38 1778_FCB 4 FCB 57.6K IN PARALLEL => VOUT = 1.338V MF CHANGE TO FERRITE IF NECESSARY
1% 2 402
1/16W TXD8* M3 GPU_TMDS_DN<0>
BG 12 38 1778_BG 53.6K IN PARALLEL => VOUT = 1.35V 1 21
MF
402 2 2 49.9K IN PARALLEL => VOUT = 1.36V R219 TXD8 N3 GPU_TMDS_DP<0>
C442 1 1
R271 R277 1 1 C461 PGOOD
VFB 8 38 1778_VFB 0
5% TXD9* M4 GPU_TMDS_DN<1>
21
38 1778_ITH_RC 220PF 0 0 0.1UF SGND PGND 1/16W
21
5% 5% 5% 20% GPU_SWITCH MF TXD9 M5 GPU_TMDS_DP<1> 21
25V 1/16W 1/16W 10V
2 CERM 6 13
CERM 2 1 2 603 N4
MF MF 402 R374 TXD10* GPU_TMDS_DN<2> 21 +3V_GPU 13 15 19 20 21 38
B C432 1
470PF
10%
402
2 402 2 402
OMIT VOUT = 0.8V * (1 + UPPER R / LOWER R)
49.9K
1%
1/16W
TXD10
TXC2*
N5
K3
GPU_TMDS_DP<2>
GPU_TMDS_CLKN 21
21 B
1
50V
CERM 2
MF
2 402
1
R275 38 +3V_GPU_AVDD0 TXC2 L3 GPU_TMDS_CLKP 21 R217
402 XW4
SM
20K NVIDIA CONFIRMED NO CONNECT ON BUFRST* 5%
0
GPU_SWITCH HIGH_VCORE 1%
1/16W THIS IS A BUFFERED VERSION OF PCI RESET 1/16W
38 20 1778_GND 1 2
R333 MF 1 C393 1 C339 1 C340 BUFRST* A9 GPU_BUFRST_TP MF
2 603
6 2 402 10UF 0.1UF 0.01UF
1
10K 2
20% 20% 20% T1 IFP0IOAVDD M1
20 GPU_VCORE_CNTL_L GPU_VCORE_CNTL_L_RC D Q12 6.3V
2 CERM
10V
2 CERM
16V
2 CERM IFP1IOVDD 38 +3V_GPU_AVDD1
5% T2 IFP0IOAGND
2N7002DW 805 402 402
GPU VCORE SUPPLY 1/16W
MF
402 1
GPU_SWITCH
C482
0.1UF
20%
2 G S
1
SOT-363
U1
U2
IFP0IOBVDD
IFP1IOGND M2
1 C363
0.01UF
20%
16V
2 CERM
1
20%
10V
C362
2 CERM
0.1UF
1 C391
10UF
20%
6.3V
2 CERM
TMDS_CLK_CMF
2 10V IFP0IOBGND 402 402 805
WHEN LOW => 1.2V CERM
402 R215 R216
49.9 1 49.9 1
WHEN HIGH => 1.36V 2.8V IS DEPENDENT ON CORE VOLTAGE
37 22 21 TMDS_CLKP 2 2 TMDS_CLKN 21 22 37
1% 1%
1/16W 1/16W
38 20 +2_8V_IFP_PLLVDD V1 IFP0PLLVDD IFP1PLLVDD N1 +2_8V_IFP_PLLVDD 20 38 MF MF
402 402
2.8V IFP PLL SUPPLY V2 IFP0PLLGND IFP1PLLGND N2 C376 1 1 C375
+3V_GPU
38 21 20 19 15 13
470PF 470PF
10% 10%
PLACE VREF AND RSET DISCRETE CLOSE TO PIN 50V 50V
CERM 2 2 CERM
CRITICAL 402 402
VOUT = 1.22(1 + R2/R1) + IADJ*R2 ONE SET OF ,0.1UF,0.01UF
GPU_IFP0VREF R2 IFP0VREF IFP1VREF L2 GPU_IFP1VREF
U8 IADJ = 30NA AT 25C FOR IFP0 AND IFP1
LTC1761ES5-BYP +2_8V_IFP_PLLVDD
SOT-23-1 SHARES 10UF 20 38
R1
GPU_IFP0RSET IFP0RSET IFP1RSET L1 GPU_IFP1RSET
SYM_VER2
IN OUT AJ3
GPU_XOR_TESTMODE_ENABLE TESTMODE
2_8V_BYP BYP ADJ 2_8V_ADJ1
1
R220 1
R229 1
R201
MAP17 PWR/LVDS/TMDS
A GND 1%
16.2K
1/16W
1 C341
1
R206
1K 10K
5%
1K
1%
1 C343
0.047UF NOTICE OF PROPRIETARY PROPERTY
A
MF 0.047UF 1% 1/16W 1/16W 10%
C408 1 1 C400 2 402 1 C390 1 C360 1 C361 1 C342 1 C354 10%
2 16V
1/16W
MF MF MF 16V
2 CERM
2.2UF 0.1UF 10UF 0.1UF 0.1UF 0.01UF 0.01UF CERM 2 402 2 402 2 402 402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
20% 20% 20% 20% 20% 402
20% 20% 6.3V 10V 10V 16V 16V AGREES TO THE FOLLOWING
10V 2 10V 1 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
CERM 2
805
CERM
402
R230 805 402 402 402 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
12.7K II NOT TO REPRODUCE OR COPY IT
1%
1/16W III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MF
2 402
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 20 44
8 7 6 5 4 3 2 1
CR-21
8 7 6 5 4 3 2 1
3.3V IO SUPPLY 38 21 20 19 15 13 +3V_GPU L4 L53 +3V_GPU 13 15 19 20 21 38
38 21 20 19 15 13 +3V_GPU 400-OHM-EMI 400-OHM-EMI
1 2 38 +3V_SI_AVCC 38 +3V_SI_VCC 1 2
SM-1 SM-1
+3V_GPU
1 C394 1 C344 1 C316 1 C338 1 C315 1 C319 1 C232 C844 1
C846 1 C848 1 1 C850 1 C851 1 C852
38 21 20 19 15 13
10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF 100PF 100PF
20%
6.3V
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
20%
6.3V 5% 5% 100PF 100PF 10UF
1 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 50V 50V 5% 5% 20%
R183 CERM 2 CERM 2 CERM 2 50V
2 CERM 50V
2 CERM 2 6.3V
805 402 402 402 402 402 402 805 402 402 CERM
0 402 402 805
5%
REPLACE WITH FERRITE IF NECESSARY 1/16W
MF
2 603
R166 L5
2
33 1
400-OHM-EMI
VGA_VSYNC 22 39
D 38 +3V_GPU_PLLVDD 5% +3V_GPU 13 15 19 20 21 38
1 2 38 +3V_SI_PLLVCC D
AD17
AG22
AH13
AG11
+3V_GPU 1/16W SM-1
AC1
AF1
A12
A19
M30
W30
38 21 20 19 15 13 MF
E1
H1
L4
Y4
D4
1 C324 1 C325 1 C312 402
C24 1 C845 1 C847 1 C849 1
R156 1 10UF 100PF 100PF
1 10UF 0.1UF 0.01UF VDD VDD(MAP31) VDD
33
R127 10UF 20% 5% 5%
R228 20%
2 6.3V
20%
2 10V
20%
2 16V
3.3V 3.3V 5V 2 1 VGA_HSYNC 22 39
5%
0 20%
6.3V 2
6.3V
CERM 2
50V
CERM 2
50V
CERM 2
0 CERM CERM CERM
1/16W
CERM 805 402 402
5% 805 402 402 5% 805
REPLACE WITH FERRITE IF NECESSARY 1/16W
MF AK5
U43 1/16W
MF
MF
2 603
2 603 PLLVDD MAP31-64MB 402 REPLACE WITH FERRITE IF NECESSARY
38 +3V_DAC1VDD PLL NOISE SHOULD BE LESS THAN 100MV PEAK-TO-PEAK 1
38 +3V_DAC2VDD
BGA PLACE SERIES R CLOSE TO GPU R752
Y3 (2 OF 5) AH9
330
GPU_CRT2VSYNC_TP CRT2VSYNC CRTVSYNC GPU_VSYNC 5%
1 C395 1 C359 1 C352 AA3 CRT2HSYNC CRTHSYNC AH10 GPU_HSYNC
1 C211 1 C231 1 C250 NO STUFF NO STUFF 1/16W
10UF 0.1UF 0.01UF GPU_CRT2HSYNC_TP
OMIT 10UF 0.1UF 0.01UF 1 1 1
MF
2 402
20%
2 6.3V
20%
10V
2 CERM
20%
16V
2 CERM
20%
2 6.3V
20%
10V
2 CERM
20%
2 16V
R748 R749 R750
CERM AA1 DAC2VDD DACVDD AK10 CERM CERM 10K 10K 10K
28
46
PVCC2 40
AVCC 34
AVCC 22
805 402 402 805 402 402 5% 5% 5%
VCC 3
W1 DAC2GND AK8 1/16W 1/16W 1/16W
DACGND
PVCC1
VCC
MF MF MF
402 2 402 2 2 402
22 GPU_COMP W3 DAC2BLUE DACBLUE AH8 22 GPU_B
AA2 DACGREEN AJ10 27 SCL/DK1 IPD MSEN 48
22 GPU_Y DAC2GREEN 22 GPU_G SI_DK<1> NC
22 GPU_C Y2 DAC2RED DACRED AJ9 22 GPU_R SI_DK<0> 26 SDA/DK0 IPD
DVO VREF W2 AJ8 GPU_RSET1
NC 24
25
CTL3/A2 IPD
PLACE CLOSE TO PIN
GPU_RSET2 DAC2RSET DACRSET SI_I2C_OFF ISEL/RST*
Y1 DAC2VREF AK9 GPU_DACVREF1
GPU_DACVREF2 DACVREF 47
39 30 26 24 19 18 MAIN_RESET_L PD*
2 SI_EDGE 44 EDGE/HTPLG TXC+ 33 SI_TMDS_CLKP
38 21 20 19 15 13 15 13 +3V_GPU 1
R204 1R203 1R205 1R196 AB1 DVOVREF C263 1
R164 1R605 1R149 1R165 TXC- 32
21
75 75 75 63.4 1 C353 21 GPU_DVO_VREF
AK1 0.22UF
113
1%
75
1% 75 75 37 21 GPU_DVOD<0> 18 D0 U55
SI_TMDS_CLKN 21
1% 1% 1% 1% 0.01UF 21 GPU_DVO_DE DVODE 20% 1/16W 1/16W 1% 1%
1/16W 1/16W 1/16W 1/16W 20% 6.3V 1/16W 1/16W 37 21 GPU_DVOD<1> 17 D1 SIL1162 TX0+ 36 SI_TMDS_DP<0> 21
R6311 MF
2 402
MF
2 402
MF
2 402
MF
2 402
16V
2 CERM 36 21 GPU_DVO_CLKP AD2
DVOCLKOUT CERM 2
402
MF
1 402
MF
2 402
MF
2 402
MF
2 402 37 21 GPU_DVOD<2> 16 D2 TSSOP TX0- 35 SI_TMDS_DN<0> 21
10K 402 GPU_DVO_CLKN_TP AD1 DVOCLKOUT* DVOCLKOUT* NOT USED IN HIGH SWING
5% GPU_DVOD<3> 15 D3
C 1/16W
MF
402 2
21
37 21
GPU_DVO_CLKIN
GPU_DVO_HSYNC
AB2
AB3
DVOCLKIN
DVOHSYNC
DVOCLKIN IS USED ONLY
FOR EXTERNAL TV OUT SUPPORT
37 21
37 21 GPU_DVOD<4> 14 D4
TX1+ 39
TX1- 38
SI_TMDS_DP<1>
SI_TMDS_DN<1>
21
21
C
37 21 GPU_DVOD<5> 13 D5
AC3
37 21 21 GPU_DVO_VSYNC DVOVSYNC 37 21 GPU_DVOD<6> 10 D6 TX2+ 42 SI_TMDS_DP<2> 21
GPU_DVO_VREF 21
GPU_DVO_CLKIN DVO<7..0> HARDWARE DEBUG PORT 37 21 GPU_DVOD<7> 9 D7 TX2- 41 SI_TMDS_DN<2> 21
21
D3 8
AK2 THERMDC GPU_THERMDC_TP 37 21 GPU_DVOD<8> D8
38 21 20 19 15 13 +3V_GPU 37 21 GPU_DVOD<0> DVOD0 E3 7 D9
AK3 THERMDA GPU_THERMDA_TP 37 21 GPU_DVOD<9>
R6331 37 21 GPU_DVOD<1> DVOD1
10K
R6321 1
R760 37 21 GPU_DVOD<2> AH3
DVOD2 MSTRAPSEL0 B30 GPU_MSTRAPSEL<0> 21
37 21 GPU_DVOD<10> 6 D10
5% 10K AJ1 B29 37 21 GPU_DVOD<11> 5 D11
1/16W 5% 0 37 21 GPU_DVOD<3> DVOD3 MSTRAPSEL1 GPU_MSTRAPSEL<1> 21
19
MF 1/16W 5% AG1 A30 21 GPU_DVO_DE DE
402 2 MF
402 2
1/16W
MF
37 21 GPU_DVOD<4> DVOD4 MSTRAPSEL2 GPU_MSTRAPSEL<2> 21
37 21 21 GPU_DVO_HSYNC 20 HSYNC
GPU_DVOD<5> AG2 DVOD5 MSTRAPSEL3 A29 GPU_MSTRAPSEL<3> EXT_SWING 30 SI_EXT_SWING_SET
2 603 37 21 21
37 21 21 GPU_DVO_VSYNC 21 VSYNC
AD3
37 21 GPU_DVOD<6> DVOD6 XTALSSIN AH7GPU_SSCLK_IN 21 36 36 21 GPU_DVO_CLKP 12 IDCK+ VREF 2 SET TO HIGH SWING MODE
AE1
37 21 GPU_DVOD<7> DVOD7 EXTERNAL SPREAD SPECTRUM CLOCK INPUT 11 IDCK-
AE3
GPU_DVOD<8> DVOD8
THRML
37 21 TESTCTL0_TP NO STUFF
1 C337 XTALIN AJ7 36 CLK27M_GPU_XIN
PGND
PGND
AGND
AGND
AGND
AE2
0.1UF GPU_DVOD<9> DVOD9 TESTCTL1_TP
R7571 R7511
PAD
37 21
GND
GND
GND
20% AG3
10V 37 21 GPU_DVOD<10> DVOD10 TESTCTL2_TP 10K 10K
MAP17 BOOT STRAPS 2 CERM
37 21 GPU_DVOD<11> AH1
DVOD11 TESTCTL3_TP XTALOUT AK7 36 CLK27M_GPU_XOUT 5% 5%
29
45
31
43
37
1
23
4
402 1/16W 1/16W
49
GPU_SS MF MF
402 2 402 2
+3V_GPU AF3
R179
38 21 20 19 15 13 15 13 38 +3V_GPU_DVO VDDDVO_0 AH6
33
XTALOUTBUFF 36 GPU_CLK27M_UF 1 2 GPU_CLK27M_OUT 21 36
AG4 VDDDVO_1 5%
MAP TMDS
XTALOUTBUFF GENERATED INTERNALLY
NO STUFF 1/16W SILICON IMAGE 1162 TMDS
NC C17 J2 NC R172 MF
402
RP55 RP57 NO STUFF
NC C18 J29 NC 10M 0K
NC C19
1 2 22 5%
1 NC C2 K26 NC
R210 R2131 NC C22 K27 NC 5%
5%
21 20 GPU_TMDS_CLKN 1 8 TMDS_CLKN 20 21 22 37
10K NC C23 K29 NC
R1711 1/16W 21 SI_TMDS_DP<0> 1 8 TMDS_DP<0> 20 21 22 37 39
R2331 5%
1/16W
10K
5%
NC
NC
NC
C24
C25 L28 NC
NC 0
MF
402 21 SI_TMDS_DN<0> 2 7 TMDS_DN<0> 20 21 22 37 39
21 20 GPU_TMDS_CLKP 2
3
7
6
TMDS_CLKP 20 21 22 37
10K MF 1/16W
C26 L30
5% GPU_TMDS_DN<0> TMDS_DN<0>
B 5%
1/16W
MF 1
402 2
1
MF
402 2 NO STUFF
R211 1 1
R234
NC
NC
NC
C27
C28
C29
M26
M27
M28
NC
NC
NC
1/16W
MF
402 2
Y2 21 SI_TMDS_CLKP
SI_TMDS_CLKN
3
4
6
5
TMDS_CLKP
TMDS_CLKN
20 21 22 37
21 20
21 20 GPU_TMDS_DP<0> 4 5 TMDS_DP<0>
20 21 22 37 39
20 21 22 37 39 B
402 2 R200 R238 1
R184 10K
5% 10K
NC
NC
C3
C30
M29 NC
NC CLK27M_XTAL_IN 1
SM-3
3
21
1/16W
20 21 22 37
1/16W
10K 10K 10K 1/16W 5% NC C4 N26 NC 36
SM1
SM1
5% 5% 5% MF 1/16W NC D1 N27 NC
1/16W 1/16W NC D10
MF MF 1/16W
MF
402 2 MF
2 402
NO STUFF GPU_FBACAS_TP D12 PTREEOUT N29 NC 1 C281
27.000M 1 C351 RP56 RP58 NO STUFF
2 402 2 402 1 NC NC
D15 N30
21 GPU_MSTRAPSEL<3> 2 402 R222 NC
NC
D16
D18
P28
R26
NC
NC
27PF
5%
CRITICAL
5%
27PF
OKAY PER ICT
22 0K
GPU_MSTRAPSEL<2> 10K NC NC 50V 2 5% 5%
NC NC +3V_SLEEP 2 50V
21 D19 R27
5% NC D2 R28 NC CERM CERM 1 8 21 20 GPU_TMDS_DN<1> 1 8 TMDS_DN<1> 20 21 22 37 39
GPU_MSTRAPSEL<1> 1/16W 402 402 NO_TEST=TRUE 21 SI_TMDS_DP<2> TMDS_DP<2> 20 21 22 37 39
21
MF NC D21 R29 NC 2 7
NC D27 R30 NC SI_TMDS_DN<2> 2 7 TMDS_DN<2> 21 20 GPU_TMDS_DP<1> TMDS_DP<1> 20 21 22 37 39
21 GPU_MSTRAPSEL<0>
NO STUFF 2 402 NC D29 T26 NC 21 20 21 22 37 39
3 6
NC D30 T27 NC SI_TMDS_DP<1> 3 6 TMDS_DP<1> 21 20 GPU_TMDS_DN<2> TMDS_DN<2> 20 21 22 37 39
GPU_VIPD6_CRYSTAL<1> CRYSTAL<1> 1 NC E10 T28 NC 1 21 20 21 22 37 39
19
GPU_DVOD<6> CRYSTAL<0> R159 NC
NC
E13 T29 NC
NC GPU_SS Y2 LOAD CAPACITANCE IS 18PF 21 SI_TMDS_DN<1> 4 5 TMDS_DN<1> 20 21 22 37 39
21 20 GPU_TMDS_DP<2> 4 5 TMDS_DP<2> 20 21 22 37 39
37 21
10K E15 T30
19 GPU_VIPD2_ROMTYPE<1> 5%
1/16W
R2231 R195 1 NC
NC
E16
E18
U28
U30
NC
NC L19
1/16W 1/16W
SM1
ROMTYPE<0> MF 10K 10K NC E19 V26 NC SM1
37 21 GPU_DVOD<10>
402 2 5% 5% NC E21 V27 NC FERR-EMI-100-OHM
BUSTYPE 1/16W 1/16W NC E28 V28 NC SM
37 21 GPU_DVOD<11> MF MF NC E30 V29 NC SI_TMDS_CLKN GPU_TMDS_CLKN
402 2 402 2 NC F29 V3 NC SI_CLKTMDS SI_TMDS:::50 8 MIL SPACING 21 GPU_CLKTMDS GPU_TMDS:::50 10 MIL SPACING 20 21
37 21 GPU_DVO_HSYNC DEVID<3> NC F30 V30 NC SI_TMDS_CLKP GPU_TMDS_CLKP
19 GPU_VIPD3_PCI_DEVID<2> DEVID<2> NC
NC
G28
G29
W26
W27
NC
NC 2 SPREAD SPECTRUM SUPPORT SI_CLKTMDS SI_TMDS:::50 8 MIL SPACING 21 GPU_CLKTMDS GPU_TMDS:::50 10 MIL SPACING 20 21
SI_TMDS_DN<0> SI_TMDS_D0 SI_TMDS:::50 8 MIL SPACING 21 GPU_TMDS_DN<0> GPU_TMDS_D0 GPU_TMDS:::50 10 MIL SPACING 20 21
DEVID<1>
W28 NC
19 GPU_VIPD5_PCI_DEVID<1> NC H28 W29 NC 38 +3V_GPU_SS
SI_TMDS_DP<0> SI_TMDS_D0 GPU_TMDS_DP<0> GPU_TMDS_D0
NC H30 SI_TMDS:::50 8 MIL SPACING 21 GPU_TMDS:::50 10 MIL SPACING 20 21
19 GPU_VIPD4_PCI_DEVID<0> DEVID<0> NC P30 Y28 NC GPU_SS GPU_SS SI_TMDS_DN<1> SI_TMDS_D1 SI_TMDS:::50 8 MIL SPACING 21 GPU_TMDS_DN<1> GPU_TMDS_D1 GPU_TMDS:::50 10 MIL SPACING 20 21
NC AB4 Y30 NC
37 21 GPU_DVOD<1> SUBVENDOR NC AG9 1 C629 1 C634 SI_TMDS_DP<1> SI_TMDS_D1 SI_TMDS:::50 8 MIL SPACING 21 GPU_TMDS_DP<1> GPU_TMDS_D1 GPU_TMDS:::50 10 MIL SPACING 20 21
37 21 GPU_DVOD<0> PCI_AD 10UF 0.1UF SI_TMDS_DN<2> SI_TMDS_D2 GPU_TMDS_DN<2> GPU_TMDS_D2
20% 20% SI_TMDS:::50 8 MIL SPACING 21 GPU_TMDS:::50 10 MIL SPACING 20 21
NO STUFF GPU_SS 2 6.3V
CERM 2 10V
CERM SI_TMDS_DP<2> SI_TMDS_D2 SI_TMDS:::50 8 MIL SPACING 21 GPU_TMDS_DP<2> GPU_TMDS_D2 GPU_TMDS:::50 10 MIL SPACING 20 21
NO STUFF NO STUFF 1
1 R2091 1 1 R614 1
R623 805 402
7 GPU_SS SHOULD BE 10MIL SPACING
R232 10K R214 R1971 R235 1
R221 5%
0 0 VDD CHANGED TO 8MIL BECAUSE OF PACKAGE PWR PINS
10K 5% 10K 10K 5%
5%
1/16W
1/16W
MF
5%
1/16W
10K
5%
5%
1/16W 5%
10K 1/16W
MF 1/16W
MF
U46
MF 402 2 MF 1/16W MF 1/16W 402 2
2 402
CY25811 GPU_SS
402 2 402 2 MF 2 402 MF SOI
402 2 2 402 NO STUFF 36 21 GPU_CLK27M_OUT 1 XIN/CLKIN R620 MAP17 ANALOG DAC/BOOT STRAPS
33
A 1
R212
1
R239
1
R190
10K
1
R243 R1601
NO STUFF
1
1
R208
10K
R613
0
NC 8 XOUT
CRITICAL
SSCLK 5 36 GPU_SSCLK_UF 1 2 GPU_SSCLK_IN 21 36
A
10K 10K 5% 10K 10K R224 5% 20 GPU_SSCLK_S1 1 2 5%
1/16W
NOTICE OF PROPRIETARY PROPERTY
5% 5%
1/16W 1/16W 5% 5% 10K 1/16W NO STUFF 5% NC 6 FRSEL MF
1/16W MF 1/16W 5% MF 1/16W 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MF 1/16W
MF
2 402 2 402 2 402 MF MF
402 2
1/16W
MF 2 402 R180 MF
402 CY25811_S1 3 S1
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
2 402 402 2 0 4
20 GPU_SSCLK_S0 1 2 CY25811_S0 S0 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
RAMCFG<3>
5% VSS II NOT TO REPRODUCE OR COPY IT
GPU_DVOD<5> 1/16W NO STUFF NO STUFF
37 21
ROM TYPE <1..0> = 00: ONLY (NVIDIA CONFIRMED OKAY) MF 2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
RAMCFG<2> 1 1
37 21 GPU_DVOD<4>
RAMCFG<1>
BUS TYPE = 1: AGP 402 R615 R619
37 21 GPU_DVOD<3>
PCI_DEVID<3..0> = 1001: MAP17(464) 0 0 SIZE DRAWING NUMBER REV.
5% 5%
37 21 GPU_DVOD<2>
MSTRAPSEL WILL BE CONNECTED
RAMCFG<0>
RAM CONFIG<3..0> = 1101: 4MX32, 1 DQS PER BYTE, LOW DRIVE STRENGTH
SUBVENDOR = 0: NO VIDEO BIOS ROM
1/16W
MF
402 2
1/16W
MF
2 402
THERE’S 20K (10K/10K) RESISTOR
APPLE COMPUTER INC.
D 051-6469 F
TO GND OR UNCONNECTED ON SUBSTRATE DIVIDER ON CHIP - SO M IS TO FLOAT THE LINES SCALE SHT OF
PCI_AD = 1: NORMAL AGP PIN OUT
CRYSTAL = 2: 27MHZ CRYSTAL S0=1;S1=M => -1.5% DOWN-SPREAD NONE 21 44
8 7 6 5 4 3 2 1
CR-22
8 7 6 5 4 3 2 1
Power key detect path when
system is shutdown or asleep..
DDC_CLK is isolated from
NV17M DURING SHUTDOWN. WHEN
ANALOG FILTERING EXTERNAL VIDEO (DVI) INTERFACE power key on remote device
is pressed, 5V will be driven
into DDC_CLK. Since host rails
will be low, TP0610 will turn
on, driving SOFT_PWR_ON_L low.
DVI POWER SWITCH
PLACE CLOSE TO CONNECTOR As host rails rise, TP0610
will turn off, as will remote
DVI DDC CURRENT LIMIT device path into DDC_CLK.
SOFT_PWR_ON_L
Isolation will be disabled as well. 34 30 23
L16 L15 (55mA requirement per DVI spec)
Q32 DVI_TURN_ON_BASE
0.068uH 0.068uH
TP0610 R603 R604 3
21 GPU_B 1 2 GPU_B_FILTR 1 2 VGA_B 22 39 +5V_SLEEP
F1 L18 +5V_DDC_SLEEP
SM
680 10K
SM SM 0.5AMP-13.2V 400-OHM-EMI 22 38 39
39 22 DVI_DDC_CLK_UF 2 3 DVI_TURN_ON 2 1 DVI_TRUN_ON_ILIM 1 2 1 Q34
C618 1 1 C616 1 2 38 +5V_DDC_SLEEP_UF 1 2 Isolation required for DVI power switch S D
5% 5% 2N3904
4.7PF 1/16W 1/16W SM
5%
50V
3.3PF
0.25% SM
SM-1 D21
SM
3V LEVEL SHIFTERS G MF
402 R600 1 MF
402
2
D L11
0.068uH
CERM 2
402 L10
0.068uH
50V
2 CERM
402
CRITICAL
J16
1 2 DDC_CLK_ISO
+3V_SLEEP
1
330
5%
1/16W
Pulldown prevents
3904 from turning
D
MF on when DVI monitor
GPU_G 1 2 GPU_G_FILTR 1 2 VGA_G 22 QH1112 39 38 22 +5V_DDC_SLEEP 402 2 has active, self-
21 39
F-RT-TH 36
MBR0530 1
R570 powered DDC clock
SM SM pullup.
33 31
4.7K
R5751 5%
1/16W
1
R576 Power key detect path
when system is running.
C609 1 4.7K
5%
MF 10K HPD normally driven to
3.3V. When power key +3V_SLEEP
4.7PF 1 C608 1/16W 2 402 Q29 5 5%
1/16W on remote device pressed,
5% TMDS_DN<0> 17 1 TMDS_DN<2> MF MF HPD will be driven to 5V.
50V 3.3PF 39 37 21 20 20 21 37 39
2N7002DW G COMPARATOR ENABLED BY NV17MAP
L13 CERM 2
402 L12 0.25%
50V
9 TMDS_DN<1> 20 21 37 39
402 2 R584 SOT-363 2 402 GPIO.
0.068uH 0.068uH 2 CERM 18 2 100
402 39 37 21 20 TMDS_DP<0> TMDS_DP<2> 20 21 37 39 1 2 DVI_DDC_CLK 3 D S 4 GPU_DVI_DDC_CLK 20
21 GPU_R 1 2 GPU_R_FILTR 1 2 VGA_R 22 39
10 TMDS_DP<1> 20 21 37 39 5% 1 C625
SM SM 19 3
1/16W
MF 1
R585 R5931 0.1UF
C617 1 1 C615 11
1 C633 402
10K
68.1K
1%
20%
10V
2 CERM
100pF 2 5% 1/16W
4.7PF 3.3PF (TMDS_DN<5>) NC 20 4 NC (TMDS_DN<4>) 5% Q29 1/16W MF
402
5% 0.25% 50V
2 CERM MF 402 2
50V 2 50V 12 2N7002DW G
CERM 2
402
CERM
402 21 5
NC (TMDS_DN<3>) 402 R563 SOT-363 2 402
(TMDS_DP<5>) NC NC (TMDS_DP<4>) 100 DVI_DDC_DATA 6 D S 1
13 NC (TMDS_DP<3>)
1 2 GPU_DVI_DDC_DATA 20 HPD_4V_REF
4
2 U45 HPD_PWR_SW
22 6 39
22 DVI_DDC_CLK_UF
5%
1/16W
LMC7211
1 SM
14 (+5V_DDC SLEEP) 1 C604 MF
402 R607 R577 1 3 4 HPD_ON
23 7 100pF 100K D S
39 37 22 TMDS_CONN_CLKP 39 DVI_DDC_DATA_UF 5 5% 10K Q33
15
5%
50V
2 CERM
Q68 1/16W
MF
39 22 DVI_HPD_UF 1 2 DVI_HPD_DIV 3
2N7002DW 1
R755
TMDS FILTERING 24 8 402 R564 2N7002DW G
2 402
1% 5
G
SOT-363
330
39 37 22 TMDS_CONN_CLKN
16 39
VGA_VSYNC 21 39
100
SOT-363
3 D S 4
1/16W
MF +PBUS Q70 5 5%
1/16W
PLACE CLOSE TO CONNECTOR 22 DVI_HPD_UF 1 2 DVI_HPD GPU_HPD 20 402
1
TP0610 MF
OMIT VGA_B C3 C1 VGA_R
5%
1/16W NOTE: Pulldown for DVI_HPD provided by DVI power switch interface
R5981 R594 2
SM
3
2 402 HPD_BASE
39 22 22 39
1 C657 10K 100K COMP_ENABLE 3
L17 C5B C5A
0.01UF
1 C603 MF
402 1% 1% S D R610
100pF 1/16W 1/16W 20K
165-OHM
SM 39 21 VGA_HSYNC C4 C2 VGA_G 22 39
20%
2 50V 5% NOTE: DVI_HPD SHARES Q68 WITH ALS MF
402 2
MF
402 2 R611 1 G HPD_ON_RC 1 2 1 Q36
SYM_VER-1 CERM
603
50V
2 CERM 100K 5% 2N3904
C 37 21 20 TMDS_CLKP 1 4 TMDS_CONN_CLKP 22 37 39
34 32
402 BECAUSE OF BOARD REAL ESTATE 5%
1/16W
MF
1
R7541
1/16W
MF
402
2
SM
C
35 402 2 100K
37 21 20 TMDS_CLKN 2 3 TMDS_CONN_CLKN 22 37 39
5%
COMP_DISABLE 1/16W
MF
6 402 2 1
CHGND5 NEED PULL-DOWN BECAUSE THIS C853 1 R756
TABLE_5_HEAD
SIGNAL IS TRISTATED INITIALLY
D
Q33 47UF 68K
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 20% 5%
1 1
R500 2N7002DW 6.3V 1/16W
R618 CERM 2
LCD INTERFACE SOT-363 MF
TABLE_5_ITEM
155S0147 1 CHOKE,COMM MODE 370OHM,2-LINE,SMD L17 CRITICAL 0 CHGND1 HPD_PWR_SNS_EN 2 G S 1210
0 5%
20
2 402
5% 1/16W
1/16W
MF
402 2
MF
2 402
R6711 1
PLACE NEAR C5A & C5B
100K
PLACE NEAR 3, 11 & 19 5%
LVDS INTERFACE 1/16W
MF
402 2
100K pull-ups are for
INVERTER INTERFACE
S-VIDEO/COMP OUT INTERFACE no-panel case (development)
Panel has 2K pull-ups
C405 1
0.001uF
20%
50V
CERM 2
CHGND4
CRITICAL +PBUS
Place GND shorts at +3V_SLEEP
402 J7
G-501973
graphics controller F-RT-SM
34 L26
XW14 L21 FERR-1K-OHM-EMI
SM
FERR-10-OHM-500MA 2 1 39 38 +12_8V_INV
1 2 1
1 2 GPU_TV_GND1 TV_GND1
38
SM
38 39
R2721 R2671 38 +3V_LCD 2
+5V_MAIN
Q1
SM
100K 100K 3
+5V_INV_UF_SW 38
5% 5% FDG6324L
C656 1 1/16W
MF
1/16W
MF (LVDS DDC POWER) 4 SC70-6
L28
0.01UF 402 2 402 2 5 3 400-OHM-EMI CRITICAL
20% NC
L20 50V
CERM 2 LVDS_DDC_CLK 6 R2561 4 S2 D2 2 1 2 1 C709 J8
B GPU_Y 1
3.3UH
2
603
39 20
39 20 LVDS_DDC_DATA 7
8
100K
5%
1/16W
SM-1 0.001UF
20% 5
SM-2MT
B
21
0603 NO STUFF 39 37 20 LVDS_L0N
9
MF
402 2
G2
6
1 C418 50V
2 CERM
39 37 20 LVDS_L0P 10UF 402
CRITICAL TV_C C865 1 C433 1
10 20% 1
C643 1 C632 1
J17
39
0.001uF 0.001uF
20% 11
FP_PWR_EN_L 6.3V
2 CERM 2
560PF 560PF MINIDIN
20% 50V 39 37 20 LVDS_L1N 6 805 39
+5V_INV_SW 3
10% 50V CERM 2 38
10% CERM 2 12
50V
CERM 2
L24 50V
CERM 2
RT-TH
MH1177 402 402 39 37 20 LVDS_L1P
D1 4
3.3UH 402 13
Q1
402
1 2 4 3 CHGND4 LVDS_L2N 14 FDG6324L
1 C713
21 GPU_C TV_Y 39
39 37 20
FP_PWR_EN 5 G1 0.001UF 6
0603 2 1 39 37 20 LVDS_L2P 15 24 20
22
S1
SC70-6
L29 20%
50V
5 16 400-OHM-EMI 2 CERM
C690 1
C688 1 TV_COMP 39
CLKLVDS_LN 17
1
1 39 2 BRIGHT_PWM
402
560PF 560PF 8 9
39 37 20
10% 10% CLKLVDS_LP 18 SM-1
50V 39 37 20 +3V_PMU
CERM 2 L22 50V
CERM 2
10 11 19
402 3.3UH 402 20
1 C721
21 GPU_COMP 1
0603
2
CHGND1
LCD POWER SWITCHES 39 37 20
39 37 20
LVDS_U0N
LVDS_U0P 21
22
20%
50V
0.001UF
2 CERM
+3V_MAIN 23
C594 1 402
C678 1 C677 1 39 37 20 LVDS_U1N 0.1UF
24 20%
560PF 560PF 39 37 20 LVDS_U1P 10V
10% 10% +3V_LCD_SW 25 CERM 2 14
XW15
50V
CERM 2 L23 50V
CERM 2
38
402
1
74LVC32 CHGND2
SM 402 FERR-10-OHM-500MA 402 1
R320 C462 39 37 20 LVDS_U2N 26 20 INV_ON_PWM TSSOP
3
2200pF 27
U32 BRIGHT_PWM_UF
1 2 38 GPU_TV_GND2 1 2 TV_GND2 38 39 100K 1 2 4
L2 39 37 20 LVDS_U2P
2
SM
5%
1/16W
FERR-250-OHM 28 32 INVERTER EXPECTS ACTIVE HIGH SIGNAL
MF 5% 3 6 1 2 39 37 20 CLKLVDS_UN 29 7
C676 1 2 402 50V 30
CERM 5 SM 39 37 20 CLKLVDS_UP
0.01UF R313 603
Place GND shorts at
20%
50V
CERM 2
1
100K 2 LCD_PWREN_L
2 C443 1
0.001uF 33 VIDEO CONNECTORS
A graphics controller
603 LCD_DIGON_L 5%
1/16W
SI3443DV
TSOP
1
20%
50V
CERM 2
C473
0.001uF
SHARES LOGIC WITH KB RESET SIGNALS (PG 28)
NOTICE OF PROPRIETARY PROPERTY
A
MF 402
3
402
Q5 2 1
R2200 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
CHGND1 0 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
D Q2 CHGND4 20%
50V
1 2 AGREES TO THE FOLLOWING
2N7002 CERM CHGND4
5% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SM 402 1/16W
22 20 24 FP_PWR_EN 1 G S MF II NOT TO REPRODUCE OR COPY IT
402
2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
C601 SIZE DRAWING NUMBER REV.
0.01uF
1 2
APPLE COMPUTER INC.
D 051-6469 F
20%
50V SCALE SHT OF
CERM
603 CHGND2 NONE 22 44
8 7 6 5 4 3 2 1
CR-23
8 7 6 5 4 3 2 1
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM BOOT BANGER E2PROM
+3V_MAIN 341S1194 1 IC,LMU,P84 U36 CRITICAL ?
+3V_MAIN
MLB - ALS SENSOR 1 C602
0.1UF
LMU +3V_MAIN
BBANG BBANG
1
20%
10V
2 CERM
R495 1 C600
10K
402 30 27 26 19 18 IO_RESET_L
1 B4
1 C788
0.1UF
5%
1/16W
MF
2 402
VCC
U37
8 0.1UF
20%
10V
2 CERM
SLEEP LED
R459 VDD
20%
16KX8_M24128B
402
D MLB_ALS_OP_COMP 4
V+
6 MAX4236EUTT
SOT23-6
R537
1K
47
5%
1/16W
U36
10V
2 CERM
402 EEPROM_ADDR 1 E0
SOI
SDA 5 INT_I2C_DATA0 12 14 23 39 +5V_MAIN
D
R531 1 MLB_ALS_OUT_FB 1 2 MLB_ALS_OUT ST72264G2H1 2 E1 SCL 6 INT_I2C_CLK0
1K
U40 1%
23 MF
2 402 256KX8 3 E2 BBANG
12 14 23 39
MLB_PHOTODIODE 1 2 MLB_ALS_OP_IN 3 5 1/16W BGA CRITICAL
V- 7
1% 2
MF
402 23 ST7_ICP_SEL_PD B5 TEST OMIT PA7/TDO E4 ST7_SENSOR4_SCK_PD 23 WC* EEPROM_WP_PD
1/16W SHDN_L ST7_RESET_L A3 RESET* PA6/SDAI F5 INT_I2C_DATA0
VSS 1
BBANG
MF
402
12 14 23 39
4 R493 R4691
CRITICAL
ST7_OSC1 C4 OSC1 XIN PA5/RDI F6 ST7_SENSOR4_SDA_PD 23 10K 2.2K R470 1
ST7_OSC2 B3 OSC2 XOUT PA4/SCLI E6 INT_I2C_CLK0 12 14 23 39
5%
1/16W 5% 100
1
1 1/16W 5%
PD1 R530 1 C605 R534 PA3 C6 JTAG_CPU_TDI 5 39
MF
2 402
MF 1/16W
BS520 5.1M 0.01UF 1
120K 2 1 C789 PA2 D4 JTAG_CPU_TRST_L 5 39
402 2 MF
402 2
5% 20%
TH 1/16W 16V
2 CERM 1 0.1UF PA1/ICCDATA A6 ST7_SENSOR5_SCK_PU SLEEP_LED_L SLEEP_LED_I
MF
2 402
402
5%
1/16W R262 20%
10V NC C1
PA0/ICCCLK A5
23
0 2 CERM ST7_SENSOR5_SDA_PU 23
Q18
2
MF C2
R5011 1
R533 402
CRITICAL
5%
1/16W
402 NC
NC D1 R468 2N3906
SM
2
15K 1K MF PB7/SS* A2 4.7K 2
1% 1% C606 2 402 NC E5
SLEEP 30 33 35
SLEEP_LED_SW_L 1 1
1/16W
MF
1/16W
MF 0.22UF Y4 NC D6 NC
PB6/SCK A1 ST7_PB6_PD 23
5%
402 2 2 402 1 2 8.000M PB5/MISO B1 SUTRO_ALS_GAIN_SW 24 39 +3V_MAIN 1/16W
1 2 ST7_XTAL_IN NC D5 MF
PB4/MOSI B2 BBANG_HRESET_L 23 39 402 3
GAIN_SETTING2 20% C5 6
6.3V SM NC
PB3/OCMP2_A C3 PMU_CPU_HRESET_L 23 30 SLEEP_LED_UF
6
CERM
402 C777 1 1 C778 NC B6
PB2/ICAP2_A D2 BBANG_JTAG_TCK
D Q20
27PF 27PF 23
5 2N7002DW
5% 5% PB1/OCMP1_A E1 ST7_KBD_LED_OUT SOT-363 1
D Q68 50V
CERM 2
50V
2 CERM
PB0/ICAP1_A F1 MLB_ALS_GAIN_SW
23
RP51 23 ST7_SLEEP_LED_H 2 G S
2N7002DW 402 402 23
10K
SOT-363
23 MLB_ALS_GAIN_SW 2 G S 5%
1/16W +3V_PMU 1
R451
1 L39
PC5/EXTCLK_A/AIN5 F2 SUTRO_ALS_OUT 24 39 SM1 400-OHM-EMI
1 4
10K SM-1
PC4/OCMP2_B/AIN4 E2 PMU_LID_CLOSED_L 23 30 5%
LOAD CAPACITANCE = 16PF (PMU_PWM) 1/16W
PC3/ICAP2_B/AIN3 F3 PMU_SLEEP_LED MF NOTE: KEEP L39 CLOSE TO C781
PC2/MCO/AIN2 E3 23 MLB_ALS_OUT 2 402 2
1
PC1/OCMP1_B/AIN1 F4 ST7_SLEEP_LED_H 23
R753
100K
C PC0/ICAP1_B/AINO D3 JTAG_CPU_TMS 5 39
3
5%
1/16W
MF
SLEEP_LED 25
C
VSS
Q20 D 2 402 C781 1
SPIDEY FLEX R692
+3V_PMU A4 1 C470
0.1UF
20%
10V
2 CERM
402
1 C494
0.1UF
20%
10V
2 CERM
402
2N7002DW
SOT-363
S G 5 PMU_SLEEP_LED_L 30
470pF
10%
50V
CERM 2
603
+5V_SLEEP +3V_HALL_EFFECT 2
22 1
4
39 38
5%
BOOT BANGING SIGNAL DEFINITION
L45 1 C803 1/16W
MF
1/ BBANG_HRESET_L (OPEN COLLECTOR OUTPUT - 10K PULLUP ON MLB)
400-OHM-EMI J15 0.001UF 402 2/ PMU_HRESET_L (3V INPUT INTO LMU)
40FLH-SM1-TB 20%
50V 3/ BBANG_JTAG_TCK (REGULAR OUTPUT)
2 1 +5V_TPAD_SLEEP F-RT-SM 2 CERM
SM-1
39 38
41 402 KEYBOARD PULLUPS 4/ JTAG_CPU_TMS (OPEN COLLECTOR OUTPUT - 470OHM PULLUP ON MLB)
5/ JTAG_CPU_TDI (OPEN COLLECTOR OUTPUT - 470OHM PULLUP ON MLB)
KBD_Y<7> 1 6/ JTAG_CPU_TRST_L (OPEN COLLECTOR OUTPUT - 470OHM PULLUP ON MLB)
1 C799 39 30
2
+3V_PMU
0.001UF
20%
39 30 KBD_Y<6>
3
R693
50V 1
100K 2
2 CERM 39 30 23 KBD_ID
39 30 KBD_Y<5> 4
402 5% 38 34 23 17 16 9 7 5 MAXBUS_SLEEP +3V_MAIN
39 30 KBD_Y<4> 5 1/16W
MF
6 BBANG
39 30
39 30
KBD_Y<3>
KBD_Y<2> 7
402
RP50 R331 LMU PULL-DOWNS
KBD_Y<1> 8 10K 10K
+3V_MAIN 39 30
9
5% 5%
1/16W
RP48
39 30 KBD_Y<0> 1/32W
25V MF 10K
10 402 2 ST7_SENSOR5_SDA_PU 1 8
Q63 39 30 23 KBD_X<9>
5 SN74AUC1G08
23
2N3906 2 39 30 23 KBD_X<8> 11 39 30 23 KBD_X<6> 3 5 PULL-UP FOR I2C (IN-CIRCUIT PROGRAMMING) 5%
SM
39 30 23 KBD_X<7> 12 39 30 23 KBD_X<7> 7 10
BBANG_TCK_EN 1
A
SC70-5
RP48 1/16W
SM1
1 4 10K
30 NUMLOCK_LED_L
39 30 23 KBD_X<6> 13 39 30 23 KBD_X<8> 4
2
U3 Y JTAG_CPU_TCK 5 39
23 ST7_SENSOR5_SCK_PU 2 7
23 BBANG_JTAG_TCK B BBANG
KBD_X<5> 14 KBD_X<9> 6 5%
B 3 R691
200
39 30 23
39 30 23 KBD_X<4> 15
16
39 30 23
39 30 23 KBD_X<2> 1
2
3
INPUTS ARE 3V TOLERANT
1/16W
SM1
RP51
2
10K
7
B
NUMLOCK_LED 2 1 39 KBD_NUMLOCK_LED 39 30 23 KBD_X<4> 23 ST7_SENSOR4_SDA_PD
5% 17 39 30 23 KBD_X<3> 9 5%
1/16W
MF 39 30 23 KBD_X<3> 18 39 30 23 KBD_X<5> 8 RP51 1/16W
SM1
402
39 30 23 KBD_X<2> 19 38 34 23 17 16 9 7 5 MAXBUS_SLEEP
1
10K 8
SM 23 ST7_SENSOR4_SCK_PD
39 30 23 KBD_X<1> 20 +3V_SLEEP
5%
+3V_MAIN
39 30 23 KBD_X<0> 21
RP53 1/16W
SM1
RP48
KBD_SHIFT_L 22 10K 10K
3 6
Q64 39 30 23
23
5% NO_BBANG 23 ST7_PB6_PD
2N3906 2 1/32W
25V
BBANG BBANG R1 5%
SM
CAPSLOCK_LED_L 1
39 30 23 KBD_OPTION_L 24
R20 1
R21 1
1
0 2 RP48 1/16W
SM1
30
39 30 23 KBD_COMMAND_L 25 39 30 23 KBD_FUNCTION_L 1 5 10K 10K 10K
5% 5% 5% 23 ST7_ICP_SEL_PD 4 5
39 30 23 KBD_CONTROL_L 26 39 30 23 KBD_CONTROL_L 2 10 1/16W 1/16W 1/16W
3 R702 39 30 23 KBD_FUNCTION_L 27 39 30 23 KBD_SHIFT_L 8 MF
402 2
MF
402 2
MF
402
5%
1/16W
2
200 1 28 9 SM1
CAPSLOCK_LED 39 KBD_CAPSLOCK_LED 39 30 23 KBD_COMMAND_L 5 SN74AUC1G08
1 SC70-5
5%
1/16W
L44 39 30 23 KBD_ID 29 NC 6 30 23 PMU_CPU_HRESET_L A
MF 400-OHM-EMI 30 39 30 23 KBD_OPTION_L 3 U2 Y
4 CPU_HRESET_L 5 7 39
402 BBANG_HRESET_L 2
34 30 22 SOFT_PWR_ON_L 2 1 39 25 PWR_BUTTON_L 31 39 30 23 KBD_X<1> 7 39 23 B BBANG
SM-1 39 38 23 KBD_LED2_OUT 32 39 30 23 KBD_X<0> 4 3 INPUTS ARE 3V TOLERANT
39 38 23 KBD_LED1_OUT 33
SM
L43 34
400-OHM-EMI 35
30 23 PMU_LID_CLOSED_L 2 1 39 LID_CLOSED_L 36
SM-1 37
L46 39 TPAD_F_RXD 38 KB LED DRIVER R690
400-OHM-EMI
1 2
39
40
17.4K2
1 ST7_KBD_LED_OUT 23
LMU/BOOTBANGER/SPIDEY
A 30 TPAD_RXD
SM-1
39 TPAD_F_TXD
CRITICAL
U50
1%
1/16W
NOTICE OF PROPRIETARY PROPERTY
A
L42 42
MAX1916
MF
402
400-OHM-EMI SOT23-6
6 LED1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
39 38 23 KBD_LED1_OUT SET 3 KBD_LED_SET
R708 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
TPAD_TXD 1 2
30
39 38 23 KBD_LED2_OUT 5 LED2 2.2K 2 AGREES TO THE FOLLOWING
SM-1 EN 1 KBD_LED_EN 1
C800 1 1 C802 1 C801 NC 4 LED3
5%
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0.001UF 0.001UF GND 1/16W 1 II NOT TO REPRODUCE OR COPY IT
0.001UF 20% 20%
50V 2 MF R608
20% 50V 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
50V 2 CERM 2 CERM 10K
CERM 2 402 402 5%
402 1/16W SIZE DRAWING NUMBER REV.
MF
2 402
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 23 44
8 7 6 5 4 3 2 1
CR-24
8 7 6 5 4 3 2 1
HARD DRIVE INTERFACE (UATA100)
+3V_SLEEP
EIDE SERIES TERMINATION WIRELESS INTERFACE +5V_HD_SLEEP 33 38
PLACE SERIES R CLOSE TO INTERPID
PLACE TERMINATORS NEAR INTREPID +3V_SLEEP
3V_HD_LOGIC 5V_HD_LOGIC
CRITICAL RP2 R4991 1
R498
33 0 0
RP44 J21 37 14 UIDE_DATA<11> 4 5 HD_DATA<11> 24 37
5%
1/16W
5%
1/16W CRITICAL
33 MF MF
37 14 EIDE_DATA<8> 1 8 EIDE_OPTICAL_DATA<8> 24 37 39 QT510806-L111 RP9 5% 402 2 2 402 J13 D
D RP14
33
5%
1/16W
F-ST-SM1
84 81 37 14 UIDE_DATA<3> 2
33 7
1/16W
SM1
HD_DATA<3> 24 37
1
M-ST-SM
50
SM1 HD_RESET_L
37 14 EIDE_DATA<10> 1 8 EIDE_OPTICAL_DATA<10> 24 37 39 5%
1/16W
RP9 37 24
2 49
5% RP14 39 30 26 21 19 18 MAIN_RESET_L 2 1 SM1 1
33 8
1/16W UIDE_DATA<1> HD_DATA<1> 24 37 3 48
SM1 2
33 7 39 RF_DISABLE_L_SPN 4 3 CLK33M_AIRPORT 13 36 39
37 14
37 24 HD_DATA<7> HD_DATA<8> 24 37
EIDE_DATA<9> EIDE_OPTICAL_DATA<9>
37 14 24 37 39
39 13 AIRPORT_PCI_REQ_L 6 5 RP9 5%
1/16W 37 24 HD_DATA<6> 4 47 HD_DATA<9> 24 37
RP43 5%
8 7 AIRPORT_PCI_GNT_L
PCI_AD<18> 10 13 18 24 26 37 39 33 SM1 5 46
1/16W 13 39
37 14 UIDE_DATA<2> 3 6 HD_DATA<2> 24 37
33 SM1
PCI_AD<31> 10 9 AIRPORT_PME_L_TP 37 24 HD_DATA<5> 6 45 HD_DATA<10> 24 37
37 14 EIDE_DATA<11> 3 6 EIDE_OPTICAL_DATA<11> 24 37 39
39 37 26 18 13 10
12 11
5%
1/16W
RP2 37 24 HD_DATA<4> 7 44 HD_DATA<11> 24 37
5% RP14 AIRPORT_PCI_INT_L 15 39 2
R658 SM1 1
33 8 8 43
1/16W 14 13 UIDE_DATA<0> HD_DATA<0> 24 37
SM1 33 39 37 26 18 13 10 PCI_AD<29> PCI_AD<30> 10 13 18 26 37 39
22 37 14
37 14 EIDE_DATA<12> 4 5 EIDE_OPTICAL_DATA<12> 24 37 39
39 37 26 18 13 10 PCI_AD<27> 16 15 5%
1/16W
RP9 5%
1/16W
37 24 HD_DATA<3> 9 42 HD_DATA<12> 24 37
RP10 5% PCI_AD<25> 18 17 PCI_AD<28> MF 4
33 5 SM1 37 24 HD_DATA<2> 10 41 HD_DATA<13> 24 37
39 37 26 18 13 10 10 13 18 26 37 39 UIDE_DATA<7> HD_DATA<7> 24 37
1/16W 1 402
37 14
33 SM1 20 19 PCI_AD<26>
11 40
37 14 EIDE_DATA<14> 3 6 EIDE_OPTICAL_DATA<14> 24 37 39
22 21
10 13 18 26 37 39
5%
1/16W
RP2 37 24 HD_DATA<1> 12 39 HD_DATA<14> 24 37
5% RP44 39 37 26 18 13 PCI_CBE<3> PCI_AD<24> 10 13 18 26 37 39 33
1/16W 33 24 23 39 AIRPORT_IDSEL R31 37 14 UIDE_DATA<5>
SM1 3 6 HD_DATA<5> 24 37 37 24 HD_DATA<0> 13 38 HD_DATA<15> 24 37
EIDE_DATA<13>
SM1 3 6 EIDE_OPTICAL_DATA<13> 10K 14 37
37 14 24 37 39
39 37 26 18 13 PCI_AD<23> 26 25 5%
1/16W
RP2 5%
1/16W 15 36
RP10 5%
1/16W 39 37 26 18 13 PCI_AD<21> 28 27 PCI_AD<22> 13 18 26 37 39 MF 2
33 7
SM1 37 14 HD_DMARQ HD_DIOW_L 24 37
402 2 37 14 UIDE_DATA<4> HD_DATA<4> 24 37 16 35
33 SM1 39 37 26 18 13 10 PCI_AD<19> 30 29 PCI_AD<20> 10 13 18 26 37 39
37 24 HD_DIOR_L HD_IOCHRDY 24 37
37 14 EIDE_DATA<15> 1 8 EIDE_OPTICAL_DATA<15> 24 37 39
32 31 PCI_PAR 13 18 26 37 39
5%
1/16W
RP3 17 34
5% RP10 SM1 1
33 8 HD_DMACK_L 18 33 HD_INTRQ
1/16W PCI_AD<17> 34 33 PCI_AD<18> UIDE_DATA<6> HD_DATA<6> 24 37 37 24 14 37
SM1 33 39 37 26 18 13 10 10 13 18 24 26 37 39 37 14
HD_ADDR<1> 19 32 HD_ADDR<2> 24
37 14 EIDE_DATA<2> 7 2 EIDE_OPTICAL_DATA<2> 24 37 39 36 35 PCI_AD<16> 10 13 18 26 37 39 RP3 5%
1/16W
37 24
20 31
37
RP44 5% 39 37 26 18 13 PCI_CBE<2> 38 37
2
33 7 SM1
1/16W 37 14 UIDE_DATA<8> HD_DATA<8> 24 37 21 30
33 SM1 39 37 26 18 13 PCI_IRDY_L 40 39 PCI_FRAME_L 13 18 26 37 39
37 24 HD_ADDR<0> HD_CS1_L 24 37
37 14 EIDE_DATA<1> 5 4 EIDE_OPTICAL_DATA<1> 24 37 39
42 41 PCI_TRDY_L 13 18 26 37 39
5%
1/16W
RP4 37 24 HD_CS0_L 22 29
5% RP44 SM1 4
33 5 23 28
1/16W AIRPORT_CLKRUN_L 44 43 PCI_STOP_L UIDE_DATA<9> HD_DATA<9> 24 37
SM1 33 39 13 18 26 37 39 37 14
24 27
EIDE_DATA<0> 7 2 EIDE_OPTICAL_DATA<0> 46 45 PCI_DEVSEL_L
37 14 24 37 39
48 47
13 18 26 37 39
RP3 5%
1/16W +HD_LOGIC_SLEEP 25 26
RP10 5% PCI_CBE<1> 33 SM1 38
C 33
1/16W
SM1
39 37 26 18 13
39 37 26 18 13 10 PCI_AD<14> 50 49 PCI_AD<15> 10 13 18 26 37 39
37 14 UIDE_DATA<10> 3 6 HD_DATA<10> 24 37 C
37 14 EIDE_DATA<3> 5 4 EIDE_OPTICAL_DATA<3> 24 37 39 52 51 PCI_AD<13> 10 13 18 26 37 39
5%
1/16W
RP4 R171 1
R69
5% RP14 PCI_AD<12> 54 53 PCI_AD<11> SM1 2
33 7
1/16W 33
39 37 26 18 13 10 10 13 18 26 37 39
37 14 UIDE_DATA<14> HD_DATA<14> 24 37 20K 10K
SM1 PCI_AD<10> 56 55 5% 5%
37 14 EIDE_DATA<6> 6 3 EIDE_OPTICAL_DATA<6> 24 37 39
39 37 26 18 13 10
58 57
RP4 5%
1/16W
1/16W
MF
1/16W
MF
RP43 5% 39 13 10 ROM_RW_L PCI_AD<9> 10 13 18 26 37 39 33 402 2
1/16W 60 59 37 14 UIDE_ADDR<0> 3 6 SM1
HD_ADDR<0> 24 37
2 402
33 SM1
39 37 26 18 13 10 PCI_AD<8> PCI_CBE<0> 13 18 26 37 39
37 14 EIDE_DATA<7> 8 1 EIDE_OPTICAL_DATA<7> 24 37 39
39 37 26 18 13 10 PCI_AD<7> 62 61 ROM_OE_L 10 13 39
5%
1/16W
RP5
5% RP43 64 63 PCI_AD<6> 10 13 18 26 37 39 SM1 2
33 7
1/16W 37 14 UIDE_CS0_L HD_CS0_L 24 37
SM1 33 PCI_AD<5> 66 65
EIDE_DATA<4> 7 2 EIDE_OPTICAL_DATA<4> 39 37 26 18 13 10
37 14 24 37 39
39 10 ROM_ONBOARD_CS_L 68 67 PCI_AD<4> 10 13 18 26 37 39
RP5 5%
1/16W
RP43 5% 33 SM1
1/16W PCI_AD<3> 70 69 PCI_AD<2> UIDE_ADDR<1> 1 8 HD_ADDR<1>
37 14 EIDE_DATA<5> 5
33 4
SM1
EIDE_OPTICAL_DATA<5> 24 37 39
39 37 26 18 13 10
72 71 PCI_AD<0>
10 13 18 26 37 39
10 13 18 26 37 39
37 14
5% RP5
24 37
ANY SEQUENCING REQUIREMENT BETWEEN
1/16W
5%
1/16W
RP12 39 37 26 18 13 10 PCI_AD<1> 74 73
37 14 UIDE_DATA<15>
SM1 4
33 5 HD_DATA<15> 24 37
+5V_HD_SLEEP AND +3V_SLEEP?
SM1 33 39 13 10 ROM_CS_L 76 75 NC
37 14 EIDE_CS0_L 3 6 EIDE_OPTICAL_CS0_L 24 37 39
NC 78 77 NC
RP3 5%
1/16W
RP12 5% R6641 4
33 5 SM1
1/16W NC 80 79 UIDE_DATA<13> HD_DATA<13>
33 SM1 10K 37 14 24 37
RP4
37 14 EIDE_ADDR<1> 1
5%
1/16W
8
RP12
33
EIDE_OPTICAL_ADDR<1> 24 37 39 5%
1/16W
MF
402 2
83 82
37 14 UIDE_DATA<12>
5%
1/16W
SM1 1
33 8 HD_DATA<12> 24 37
BLUETOOTH/LEFT-SIDE USB
SM1 4 5
EIDE_ADDR<2> EIDE_OPTICAL_ADDR<2>
37 14 24 37 39
RP5 5%
1/16W CRITICAL
RP12 5% 33 SM1
33
1/16W
SM1 37 14 UIDE_ADDR<2> 3 6 HD_ADDR<2> 24 37
+5V_MAIN +3V_MAIN J3
37 14 EIDE_ADDR<0> 2 7 EIDE_OPTICAL_ADDR<0> 24 37 39 5% 54550-1490
5%
1/16W
SM1 R47 F-RT-SM
15
1 1/16W 33
R18 SM1 37 14 UIDE_CS1_L 2 1 HD_CS1_L 24 37
10K
5%
1/16W
OPTICAL DRIVE INTERFACE (EIDE) 5%
1/16W
MF
1
2
B MF
2 402
+5V_SLEEP
402 39 37 15
39 37 15
BT_USB_DP
BT_USB_DM 3 B
4
5
NO STUFF NO STUFF
PLACE PULLUP RESISTORS CLOSE TO INTREPID 39 37 26 LEFT_USB_DP 6
R10 1 1 1
39 37 26 LEFT_USB_DM 7
EIDE_CS1_L 1
33 2 EIDE_OPTICAL_CS1_L R375 R362 R334 +3V_SLEEP 8
37 14 24 37 39
100K 10K 10K 39 26 NEC_LEFT_USB_PWREN 9
5% 5% CRITICAL 5% 5%
1/16W
MF R81 1/16W
MF J11 1/16W
MF
1/16W
MF 39 23 SUTRO_ALS_OUT 10
EIDE_DMARQ
402
1
82 2 EIDE_OPTICAL_DMA_RQ
402 2 M-ST-SM 2 402 2 402 39 26 NEC_LEFT_USB_OVERCURRENT 11
37 14 24 37 38
39 12
5% 1 50 EIDE_OPTICAL_RST_L 39 23 SUTRO_ALS_GAIN_SW
NC 24 37 39
R64 1/16W
MF 2 49
R341
1
R502 13
EIDE_DMACK_L 1
22 2
402
EIDE_OPTICAL_DMAACK_L EIDE_OPTICAL_DATA<8> 3 48 EIDE_OPTICAL_DATA<7> 10K 100K R631 14
37 14 24 37 38
39
39 37 24 24 37 39
5% 5% 10K
5% EIDE_OPTICAL_DATA<9> 4 47 EIDE_OPTICAL_DATA<6> 1/16W 1/16W 5% 1 1
1/16W
MF R9
39 37 24
EIDE_OPTICAL_DATA<10> 5 46 EIDE_OPTICAL_DATA<5>
24 37 39
MF
402 2
MF
2 402
1/16W
MF
R43 R36 16
402 22 39 37 24 24 37 39
402 2 15K 15K
37 14 EIDE_RD_L 1 2 EIDE_OPTICAL_RD_L 24 37 38 39 37 24 EIDE_OPTICAL_DATA<11> 6 45 EIDE_OPTICAL_DATA<4> 24 37 39
5% 5%
1/16W 1/16W
5%
39
7 44 R46 MF MF
R11 1/16W
8 43 33 2 402 2 402
MF 39 37 24 EIDE_OPTICAL_DATA<12> EIDE_OPTICAL_DATA<3> 24 37 39 37 14 UIDE_RST_L 1 2 HD_RESET_L 24 37
1
22 2
402
9 42
37 14 EIDE_WR_L EIDE_OPTICAL_WR_L 24 37 39 39 37 24 EIDE_OPTICAL_DATA<13> EIDE_OPTICAL_DATA<2> 24 37 39 5%
5% 39 37 24 EIDE_OPTICAL_DATA<14> 10 41 EIDE_OPTICAL_DATA<1> 24 37 39
1/16W
MF R503
1/16W
MF R48 EIDE_OPTICAL_DATA<15> 11 40 EIDE_OPTICAL_DATA<0> UIDE_DMACK_L
402
1
22 2 HD_DMACK_L
39 37 24 24 37 39 37 14 24 37
402
1
82 2 12 39
37 14 EIDE_IOCHRDY EIDE_OPTICAL_IOCHRDY 24 37 39 5%
5% 38 24 EIDE_OPTICAL_DMA_RQ 13 38 EIDE_OPTICAL_WR_L 24 37 39
R16 1/16W
MF
R53 1/16W
MF
39 37
EIDE_OPTICAL_RD_L 14 37 EIDE_OPTICAL_IOCHRDY UIDE_DIOR_L 1
22 2
402
HD_DIOR_L
38 24 24 37 39 37 14 24 37
1
82 2
402 39 37
15 36
37 14 EIDE_INT EIDE_OPTICAL_INT 24 37 39 38 24 EIDE_OPTICAL_DMAACK_L EIDE_OPTICAL_INT 24 37 39 5%
5%
R42
39 37
16 35 EIDE_OPTICAL_ADDR<1> 24 37 39
1/16W
MF R41
22
INTERNAL I/O CONNECTORS
A 37 14 EIDE_RST_L
1/16W
MF
402
1
33 2 EIDE_OPTICAL_RST_L 24 37 39
39 37 24
39 37 24
EIDE_OPTICAL_ADDR<2>
EIDE_OPTICAL_CS1_L
17
18
34
33
EIDE_OPTICAL_ADDR<0>
EIDE_OPTICAL_CS0_L 24
24 37 39
37 39
37 14 UIDE_DIOW_L
402
1
5%
2 HD_DIOW_L 24 37
NOTICE OF PROPRIETARY PROPERTY
A
1/16W
5% 19 32 MF
1/16W
MF R3611 20 31 1
R381 R62 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402
21 30
82 AGREES TO THE FOLLOWING
20K 10K 37 14 UIDE_IOCHRDY 1 2 HD_IOCHRDY 24 37
5% 22 29 5% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W NC NC 1/16W 5%
MF MF 1/16W II NOT TO REPRODUCE OR COPY IT
23 28
402 2
24 27
2 402 1 C90 MF
402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
10PF
25 26 5%
50V
2 CERM SIZE DRAWING NUMBER REV.
402
D 051-6469 F
APPLE COMPUTER INC.
SCALE SHT OF
IOCHRDY - UATA100 REQUIRES PULL-UP TO 3.3V NONE 24 44
8 7 6 5 4 3 2 1
CR-25
8 7 6 5 4 3 2 1
+5V_MAIN
SERIAL DEBUG INTERFACE
+5V_MAIN
C857
0.1UF
SOUND BOARD (TUBA) 2
RP59 +5V_MAIN
1 2 AUDIO - SNAPPER 100K
5%
1/16W
20%
10V
SND - INTREPID 7
SM1
CERM SERIAL_DEBUG
402
CRITICAL
6 J5
D 33 SLEEP_LS5
R761
1
100K 2
5%
1/16W
5V_SND_PWREN
4
3 6
5
+5V_SOUND_SLEEP 25 38
Q69
2N7002DW
SOT-363
D
S G 2 SND_AMP_MUTE_L 15 39
MODEM 39 15 COMM_TXD_L
COMM_TRXC
M-ST-5087
1
2
SM
10
9
COMM_DTR_L
COMM_RTS_L
15 39 D
39 15 15 39
MF +3V_MAIN +5V_MAIN
402 1 C858 2
1 5
3 8
10UF TSOP 1 +5V_MAIN +3V_SLEEP 39 15 COMM_GPIO_L 4 7 COMM_RXD 15 39
20%
2 6.3V
CERM
SI3443DV AMP_CONTROL
RP59 NO STUFF 5 6
805 Q49 100K NO STUFF
3 5%
1/16W 1 C450 1 C458 1 C734 1 C480
Q69 D SM1 10UF 0.1UF
2N7002DW 4 10UF
20%
0.1UF
20%
R3251 20% 20%
10V
SOT-363 2 6.3V 10V
2 CERM 10K 2 6.3V
CERM
2 CERM
CRITICAL S G 5 INT_PU_RESET_L CERM 5% 805 402
14 25 30 805 402 1/16W
J14 4 CRITICAL
MF
402 2
QT510306-L111
F-ST-SM J9
2 QT510166-L010
1
3 4
SND_AMP_MUTE
SND_HP_SENSE_L
F-ST-SM DEBUG POWER BUTTON
15 39 1 2
5 6 SND_HP_MUTE +5V_SOUND_SLEEP 25 38
39 25 15 INT_I2C_CLK2 3 4
8 NO STUFF
7 5 6
1 39 25 15 INT_I2C_DATA2 COMM_RESET_L 15 39
9 10 INT_AUDIO_TO_SND 15 39
RP59 7 8 COMM_SHUTDOWN 15 39
R261
11 12 9 10
0
100K MODEM_I2C_A1 39 23 PWR_BUTTON_L 1 2
39 15 SND_LIN_SENSE_L 13 14 SND_SCLK 15 36 39 5% 11 12
1/16W MODEM_I2C_A0 MODEM_USB_DM 15 37 39 5%
SND_HW_RESET_L 15 16 SM1 1/16W
39 15 13 14 MODEM_USB_DP 15 37 39 MF
18 8 603
17 SND_TO_AUDIO 15 39 15 16
39 30 15 COMM_RING_DET_L
19 20
21 22 SND_CLKOUT 15 36 39
23 24 SND_SYNC 15 39 6
25 26
27 28 INT_I2C_DATA2 15
Q67 D
25 39 2N7002DW
SLEEP_LED 29 30 INT_I2C_CLK2 SOT-363
2
C
23 15 25 39 S G SND_HP_MUTE_L 15 39
DEBUG JUMPERS C
XW17
SM
NO STUFF NO STUFF
1
1 2 38 SND_AGND
1 C866 1 C867 6 NO STUFF
0.001UF 0.001UF HP_CONTROL
20%
50V
20% RP59 R2500
2 CERM 2 50V
CERM 3 100K 0
5% 30 PMU_NMI_BUTTON_L 1 2
402 402
1/16W
PLACE XW17 CLOSE TO 5V SWITCHER (U27) Q67 D SM1 5%
1/16W
2N7002DW 3 MF
SOT-363 603
S G 5 INT_PU_RESET_L 14 25 30
CAPS FOR EMI EXPERIMENTATION ONLY
4
FAN CONTROLLER +5V_SLEEP
NO STUFF
R2501
0
PLACE IN BETWEEN 3/5/1.5/2.5V PWR SUPPLY FAN INTERFACE +3V_MAIN 30 PMU_RESET_BUTTON_L 1
5%
1/16W
MF
603
2
MAIN1 CRITICAL CRITICAL
THERM1_M_DP C668 1 6 R5421 1
R539 J2
37 25
0.1UF VCC 10K 10K
20% 5% 5% SM-2MT
3 10V
CERM 2
U48 1/16W
MF
1/16W
MF 4
402 ADM1031 402 2 2 402
QSOP
1 Q56 KEEP STUFFING RESISTORS CLOSE TO ADM1031 CONTROLLER 13 ADD PWM_OUT11 FAN1_PWM 39 38 FAN1_GND 1
2N3904 2
SM
R637 39 15 14 INT_I2C_DATA1 15 SDA TACH/AIN12 39 FAN1_TACH
2 3
1
0 2
39 15 14 INT_I2C_CLK1 16 SCL PWM_OUT2 3
37 25 THERM1_M_DM 37 25 THERM1_M_DP THERM1_DP 25 37 FAN2_PWM 25
5% 37 25 THERM1_DP 10 D1+ TACH/AIN2 4 FAN2_TACH 25 39
5
B R642
0
1/16W
MF
402
37 25 THERM1_DM 9 D1-
INT 14 NC
B
1
2
5
6
THERM1_M_DM 1 2 THERM1_DM 12
37 25 25 37
37 25 THERM2_DP D2+ THERM 7 THERM_L_OC 30
PLACE CLOSE TO CPU
SI3446DV
5%
1/16W 37 25 THERM2_DM 11 D2- FAN_FAULT 8 NC 1 C856
MAIN2 MF R626 4.7UF
Q27
402
0 GND
TSOP
20% PLACE CLOSE TO CONNECTOR
37 25 THERM2_M_DP 1 2 THERM2_DP 25 37 5 10V
37 25 THERM2_M_DP 2 CERM
5% 1206
1/16W
3 R629 MF
402
1
0 2
4
37 25 THERM2_M_DM THERM2_DM 25 37
1 Q31 5%
2N3904 1/16W
SM MF
2 402
37 25 THERM2_M_DM
+5V_SLEEP
PLACE UNDERNEATH UPPER RAM CRITICAL
ALTERNATE1 1 1
J4
R569 R592 4
SM-2MT
37 25 THERM1_A_DP KEEP STUFFING RESISTORS CLOSE TO ADM1031 CONTROLLER 10K 10K
5% 5%
1/16W 1/16W
3 NO STUFF MF MF 1
NO STUFF 402 2 402 2
2
1 Q38 R638
2N3904 THERM1_A_DP 1
0 2 THERM1_DP
39 25 FAN2_TACH 3
37 25 25 37
SM FAN2_GND
5% 39 38
2 NO STUFF 1/16W 5 FAN/MODEM/SOUND/SLEEP LED/DEBUG
37 25 THERM1_A_DM
R643 MF
A 37 25 THERM1_A_DM 1
0 2
402
THERM1_DM 25 37
NOTICE OF PROPRIETARY PROPERTY
A
1
2
5
6
5%
1/16W NO STUFF
PLACE CLOSE TO BATTERY CHARGER/VCORE
SI3446DV
MF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
402 R622 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
C855
Q30
ALTERNATE2 0 1 AGREES TO THE FOLLOWING
TSOP
THERM2_A_DP 1 2 THERM2_DP
37 25 25 37
4.7UF PLACE CLOSE TO CONNECTOR I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5% 20%
37 25 THERM2_A_DP 1/16W 10V II NOT TO REPRODUCE OR COPY IT
NO STUFF 2 CERM
MF
1206 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
3 NO STUFF R630 402
0
4
37 25 THERM2_A_DM 1 2 THERM2_DM 25 37
SIZE DRAWING NUMBER REV.
1 Q53
2N3904
SM
5%
1/16W
MF
25 FAN2_PWM
APPLE COMPUTER INC.
D 051-6469 F
2 402
SCALE SHT OF
37 25 THERM2_A_DM
NONE 25 44
8 7 6 5 4 3 2 1
CR-26
8 7 6 5 4 3 2 1
+3V_NEC_VDD 26 38
NEC_USB NEC_USB NEC_USB NEC_USB
1 C495 1 C517 1 C824 1 C827
0.1uF 0.1uF 0.1uF 0.1uF
20% 20% 20% 20% NEC_USB
10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM +3V_MAIN
402 402 402 402 L48
FERR-EMI-100-OHM
NEC_USB NEC_USB NEC_USB NEC_USB
1 2
1 C496 1 C703 1 C825 1 C828 SM
38 NEC_AVDD
0.1uF 0.1uF 0.1uF 0.1uF NEC_USB NEC_USB NEC_USB
20% 20% 20% 20%
10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM
1 C830 1 C831 C832
402 402 402 402 NEC_USB 0.1uF 0.1uF 10uF Y7 LOAD CAPACITANCE IS 16PF
1 20% 20% 20%
R711 2 10V 2 10V 6.3V
D 1
NEC_USB
C516
NEC_USB
C730 1
NEC_USB
C826 1
NEC_USB
C829 5%
0
1/16W
CERM
402
CERM
402
CERM
805 CRITICAL
NEC_USB
D
0.1uF 10uF 0.1uF 0.1uF
20%
10V
20%
6.3V
20%
10V
20%
10V
MF
2 603
Y7
2 CERM CERM 2 CERM 2 CERM 30.0000M +3V_MAIN
402 805 402 402 1 2 NEC_XT2_R
38
26 +3V_NEC_VDD SM-1 NEC_USB NEC_USB
1 C833 1 C834 1R713 7 NEC_USB 8 NEC_USB
27PF 27PF 100
P12
A13
A12
L13
J13
H13
F13
D13
G12
N10
N12
RP54 RP54
H3
M4
C8
P2
P3
A3
E2
N8
H4
D7
5% 5% 5%
2 50V
CERM 2 50V
CERM 1/16W 10K 10K
M5 402 402 MF
PCI_AD<0> AD0 5% 5%
39 37 24 18 13 10
2 402 1/16W 1/16W
VDD_PCI
VDD
AVDD
PCI_AD<1> P5 XT1/SCLK L9 NEC_XT1 NEC_USB SM1 SM1
39 37 24 18 13 10 AD1 36
N5 2 1
39 37 24 18 13 10 PCI_AD<2> AD2 XT2 P8 36 NEC_XT2
39 37 24 18 13 10 PCI_AD<3> P4
AD3 R717 NEC_USB
39 37 24 18 13 10 PCI_AD<4> N4
AD4 Low/Full/High Speed (External) RSDM1 M1437 NEC_USB_RSDM1 1 2 NEC_USB_DAM 26 37
R728
PCI_AD<5> M3 CRITICAL M13 (NEC_USB_DAM) 1
15K 2
39 37 24 18 13 10 AD5 DM1 1% 402 26 NEC_OCI<1> NEC_LEFT_USB_OVERCURRENT 24 39
PCI_AD<6> N3 NEC_USB L14 (NEC_USB_DAP) 36 5%
39 37 24 18 13 10 AD6 DP1 NEC_USB
39 37 24 18 13 10 PCI_AD<7> M1
AD7 U52 RSDP1 K13 37 NEC_USB_RSDP1 NEC_USB_DAP 26 37
1/16W
MF
402
NEC_USB
SERR_L AND PERR_L 39 37 24 18 13 10 PCI_AD<8> L2
AD8 NEC_UPD720101_USB2 R716 R729
HAS DEDICATED PULL-UP PCI_AD<9> L1 FBGA RSDM2 K1437 NEC_USB_RSDM2 15K
39 37 24 18 13 10 AD9 NEC_OCI<2> 1 2 NEC_RIGHT_USB_OVERCURRENT
FOR BOTH CBUS AND USB2 K2 K12 (NEC_USB_DBM) 1 2 26 32 39
39 37 24 18 13 10 PCI_AD<10> AD10 DM2
+3V_MAIN 1% 5%
39 37 24 18 13 10 PCI_AD<11> L3
AD11 DP2 J14 (NEC_USB_DBP) 36402 1/16W
Low/Full/High Speed (External) NEC_USB MF
39 37 24 18 13 10 PCI_AD<12> K1 AD12 RSDP2 J12 37 NEC_USB_RSDP2 402
NEC_USB NEC_USB
PCI_AD<13> K3
39 37 24 18 13 10 AD13
PCI_AD<14> J2
AD14 RSDM3 H11 NC R714 1 C835 1 C836
NEC_USB
39 37 24 18 13 10
1 2 NEC_USB_DBM 26 37
0.1uF 0.1uF
PCI_AD<15> J1 DM3 G11 20% 20%
6 1 39 37 24 18 13 10 AD15 10V 10V
R741 PCI_AD<16> F2
AD16 DP3 G13
1% 36402 2 CERM 2 CERM
RP51 5%
10K
39 37 24 18 13 10
PCI_AD<17> E3
AD17 RSDP3 G14 NC
NEC_USB 402 402
10K 39 37 24 18 13 10
C 5%
1/16W
SM1
1/16W
MF
2 402
39 37 24 18 13 10 PCI_AD<18> E1
D3
AD18
F12 NC
NEC_USB_DBP 26 37
C
3
39 37 24 18 13 10 PCI_AD<19>
D1
AD19 RSDM4
F14
R715
39 37 24 18 13 10 PCI_AD<20> AD20 DM4 1 2
PCI_AD<21> D2 DP4 E12
NEC_PCI_SERR_L
39 37 24 18 13 AD21 1% 402
26
PCI_AD<22> C2 RSDP4 E14 NC 36
39 37 24 18 13 AD22
26 NEC_PCI_PERR_L PCI_AD<23> C1 NEC_USB
39 37 24 18 13 AD23
B4 E13 NC +3V_MAIN
39 37 24 18 13 10 PCI_AD<24> AD24 RSDM5
PCI_AD<25> A4 DM5 D14
39 37 24 18 13 10 AD25
39 37 24 18 13 10 PCI_AD<26> B5 AD26 DP5 C13
(PCI_AD<27>) C4 C14 NC NEC_USB
39 37 24 18 13 10 PCI_AD<27> AD27 RSDP5
39 37 24 18 13 10 PCI_AD<28> A5
AD28 R712 INTREPID_USB INTREPID_USB 5 NEC_USB 6 NEC_USB NEC_USB
C5 9.09K2
PCI_AD<29> AD29 RREF P11 NEC_RREF 1
39 37 24 18 13 10
PCI_AD<30> B6 1%
1
R666 1
R667 RP54 RP54 2R718
39 37 24 18 13 10 AD30 10K 10K 10K
PCI_AD<31> A6
1/16W
MF
10K 10K 5% 5% 5%
39 37 24 18 13 10 AD31 402
5% 5%
1/16W 1/16W 1/16W
1/16W 1/16W MF
Tie to GND at ball N11 MF MF SM1 SM1
M2 2 402 2 402 4 3 1 402
39 37 24 18 13 PCI_CBE<0> CBE0
NEC_USB
R7101 39 37 24 18 13 PCI_CBE<1> J3
CBE1 LEFT PORT OCI1 B12 NEC_OCI<1> 26
22 39 37 24 18 13 PCI_CBE<2> F1 CBE2 RIGHT PORT OCI2 B11 NEC_OCI<2> 26
NEC_USB
5% C3 B10 NEC_USB
1/16W 39 37 24 18 13 PCI_CBE<3> CBE3 OCI3 NEC_OCI<3>
1
MF
402 2 OCI4 A10 NEC_OCI<4>
1
R124 R182
PCI_PAR J4 B9 NEC_OCI<5> 1.5K 1.5K
39 37 24 18 13 PAR OCI5 5% 5%
F3 1/16W 1/16W
39 37 24 18 13 PCI_FRAME_L FRAME MF
MF
PCI_IRDY_L F4 PPON1 C1239 24 NEC_LEFT_USB_PWREN 2 402 2 402
39 37 24 18 13 IRDY OUT
PCI_TRDY_L G1 OUT PPON2 A11
39 32 NEC_RIGHT_USB_PWREN
39 37 24 18 13 TRDY
39 37 24 18 13 PCI_STOP_L G3 STOP OUT PPON3 C11 NEC_PPON3_TP NEED PULL-UP RESISTORS IN CASE USB 1.0 IS USED FOR PORT POWER
NEC_IDSEL B3 OUT PPON4 C10 NEC_PPON4_TP
IDSEL
B NEC_USB
39 37 24 18 13
13
PCI_DEVSEL_L
USB2_PCI_REQ_L
G2
C6
DEVSEL
REQ
OUT PPON5 A9 NEC_PPON5_TP
B
RP37 D6 NC1 P6 NEC_NC1_TP
13 USB2_PCI_GNT_L GNT
47 H2 NC2 M6 NEC_NC2_TP
26 NEC_PCI_PERR_L PERR
5%
NEC_PCI_SERR_L H1
30 27 23 19 18 IO_RESET_L 1 8 NEC_IO_RESET_L 26
26 SERR OD NEC_USB
2 7 NEC_PCI_INTA_L C7 INTA OD
30 15 PMU_PME_L
3 6
NEC_PME_L 26
26
NEC_PCI_INTB_L B7
INTB OD
R719
39 30 24 21 19 18 MAIN_RESET_L NEC_MAIN_RESET_L 26
26
1
0 2
NEC_PCI_INTC_L A7 37 26 NEC_USB_DAM LEFT_USB_DM 24 37 39
4 5 26 INTC OD
A8 5% INTREPID_USB
1/16W 36 13 CLK33M_USB2 PCLK IPD NTEST1 M8 NC 1/16W
SM1 MF
402
R725
B8 0
NEC_IO_RESET_L VBBRST IPD SMC M7 NC USB_D1M 1 2
26
NEC_CRUN_L N6
CRUN
39 26 15
NEC_USB
5%
1/16W
PLACE NEAR J3
NEC_USB NEC_PME_L D9 PME OD MF
R709 1
26
NEC_MAIN_RESET_L C9
VCCRST IPD TEB N7 NC
R720 402
Series Rpaks required to 26
0
facilitate NAND-tree testing
4.7K NEC_SMI_L_TP L6
SMI OD IPD AMC P7 NEC_AMC_TP 37 26 NEC_USB_DAP 1 2 LEFT_USB_DP 24 37 39
5%
1/16W
MF
402 2 NEC_USB L8
5%
1/16W
MF
INTREPID_USB SUTRO CONNECTOR
RP39 L7
IPD TEST NC 402 R723
47 LEGC 1
0 2
39 26 15 USB_D1P
5%
5%
15 USB2_PCI_INT_L 1 8 NEC_PCI_INTA_L 26 NANDTEST M10 NEC_NANDTESTEN_TP 1/16W
MF
2 7 NEC_PCI_INTB_L SRCLK M9 NC 402
AVSS(R)
26
NEC_USB
3 6 NEC_PCI_INTC_L SRDTA N9 NEC_NANDTESTOUT_TP
4 5 NEC_LEGC
26
IPD SRMOD P9 NC
R721
VSS 1
0 2
1/16W 37 26 NEC_USB_DBM RIGHT_USB_DM 32 37 39
AVSS
SM1 5% INTREPID_USB
USB 2.0
P10
N14
H14
B14
N13
B13
M11
L12
H12
D12
J11
F11
N11
P13
M12
1/16W
B1
N1
A2
B2
N2
G4
D8
MF
402
R726
0
A 39 26 15 USB_D2M 1
5%
2
PLACE NEAR J12 NOTICE OF PROPRIETARY PROPERTY
A
NEC_USB 1/16W
MF
INTREPID USB CONSTRAINTS R722 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1
0 2 AGREES TO THE FOLLOWING
37 26 NEC_USB_DBP RIGHT_USB_DP 32 37 39
USB_DAM USB_DA USB_DA:::200 5 MIL SPACING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
USB_DAP USB_DA USB_DA:::200 5 MIL SPACING
15
15
5%
1/16W
MF
INTREPID_USB BUBBA CONNECTOR II NOT TO REPRODUCE OR COPY IT
USB_DCM USB_DC USB_DC:::200 5 MIL SPACING 15
402 R724 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
USB_DCP USB_D2P 1
0 2
USB_DC USB_DC:::200 5 MIL SPACING 15 39 26 15
SIZE DRAWING NUMBER REV.
USB_D1M USB_D1 USB_D1:::200 5 MIL SPACING 15 26 39 5%
1/16W
USB_D1P USB_D1 USB_D1:::200 5 MIL SPACING 15 26 39 MF
402
D 051-6469 F
USB_D2M USB_D2 USB_D2:::200 5 MIL SPACING 15 26 39
APPLE COMPUTER INC.
SCALE SHT OF
USB_D2P USB_D2 USB_D2:::200 5 MIL SPACING 15 26 39
NONE 26 44
8 7 6 5 4 3 2 1
CR-27
8 7 6 5 4 3 2 1
+3V_MAIN
Ethernet routing priority:
1. Decoupling caps
2. TX SERIES TERMINATION - LOCATE NEAR LINK
3. RX SERIES TERMINATION - LOCATE NEAR PHY
C427 1
10uF LTC3405_SW 38
NO STUFF 20% All differential signals should be close,
6.3V
1 CERM 2 4
R703 805
VIN CRITICAL
parallel, matched lengths, with minimum
0 via count, and short if possible
5%
1/16W U51 L47
MF
402 2
LTC3405 3.3uH Must maintain 50-ohms trace impedance on all
SOT23-6
1 2 MDI pairs and all RJ45 pairs
3405_MODE
1 RUN CRITICAL SW 3 +1_0V_MARVELL 38
D 6 MODE VFB 5
1
R705 C456
SM1
1
1
R706
Sandwich each RJ54 pair between chassis grounds D
GND 665K 49.9K
R704 1
2 1% 22pF 1%
1/16W 5% 1/16W
0
5%
MF
50V
CERM 2 MF 1 C464
1/16W 2 402 R2A 402 2 402 10uF
MF R2B 20%
3405_VFB 6.3V
402 2 2 CERM
805
1
VOUT = 0.8V*(1+R2EQV/R1) R707
PLACE ALL SERIES RES CLOSE TO PHY 182K
R331 R2EQV = R2A||R2B 1%
1/16W
MF
1
0 2 2 402
36 14 CLKENET_LINK_TX 36 CLKENET_PHY_TX
R1
5%
1/16W
MF R288 4
TX_CLK CTRL10 51 NC
402
1
0 2
36 14 CLKENET_LINK_RX 36 CLKENET_PHY_RX
5% 2 1
RX_CLK
R278 1/16W
MF 6
0 402
36 14 CLKENET_LINK_GBE_REF 1 2 36 CLKENET_PHY_GBE_REF 22
125CLK
10 1 C452 1 C455 1 C710 1 C483 1 C484 1 C438 +2_5V_MAIN
5% 15 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF
1/16W 20% 20% 20% 20% 20% 20%
MF 57 10V 16V 10V 16V 10V 16V
402 DVDD 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
ENET_PHY_TXD<0> 11 CRITICAL 62 402 402 402 402 402 402
37 14
TXD0 1
37 14 ENET_PHY_TXD<1> 12
TXD1 U49 67
PLACE CAPS (IN ORDER) ON PINS 1, 6, 10/15, 57/62, 67/71, 85
R259
ENET_PHY_TXD<2> 14 71 0
37 14 TXD2 88E1111 5%
ENET_PHY_TXD<3> 16 85 1/16W
37 14 TXD3 BCC MF
ENET_PHY_TXD<4> 17 2 603
37 14 TXD4
ENET_PHY_TXD<5> 18 5 38 27 +2_5V_MARVELL
37 14 TXD5
ENET_PHY_TXD<6> 19 21
37 14 TXD6
C 37 14 ENET_PHY_TXD<7> 20
TXD7
VDDO 88
96
1 C485
0.1UF
1 C428
0.01UF
1 C435
0.1UF
1 C466
0.01UF
1 C486
0.1UF
1 C479
10uF
C
20% 20% 20% 20% 20% 20%
37 14 ENET_PHY_TX_EN 9
TX_EN 2 10V
CERM
16V
2 CERM 2 10V
CERM 2 16V
CERM
10V
2 CERM 2 6.3V
CERM
37 14 ENET_PHY_TX_ER 7
TX_ER 52 402 402 402 402 402 805 1 C457 1 C447 1 C474 1 C487
66 0.1UF 0.1UF 0.1UF 0.1UF
VDDOH PLACE CAPS (IN ORDER) ON PINS 5, 21/26, 48/52, 66/72, 88, 96
20%
10V
20%
10V
20%
10V
20%
10V
CLKENET_PHY_GTX 8 72 2 CERM 2 CERM 2 CERM 2 CERM
36 14 GTX_CLK 402 402 402 402
26
L27
FERR-EMI-600-OHM PLACE CAPS AT TRANSFORMER PINS 1, 4, 7 & 10
ENET_LINK_RXD<0> 95 VDDOX 48 38 +2_5V_MARVELL_AVDD CRITICAL
37 14 RXD0 2 1
37 14 ENET_LINK_RXD<1> 92
RXD1 SM
J18
93 32 RJ45
ENET_LINK_RXD<2>
37 14 RXD2 1 C719 1 C727 1 C702 1 C726 1 C718 39
11 RT-TH
ENET_LINK_RXD<3> 91 35 12 13 37 RJ45_DP<0>
37 14 RXD3 0.1UF 0.01UF 0.1UF 0.01UF 10uF 9
ENET_LINK_RXD<4> 90 36 20% 20% 20% 20% 20%
37 14 RXD4 AVDD 2 10V 16V
2 CERM 2 10V 2 16V 2 6.3V
ENET_LINK_RXD<5> 89 40 CERM CERM CERM CERM 10 15 RJ45_C0_PD
37 14 RXD5 402 402 402 402 805
ENET_LINK_RXD<6> 87 45 1
38 27 +2_5V_MARVELL 37 14 RXD6 39
ENET_LINK_RXD<7> 86 78 PLACE CAPS (IN ORDER) ON PINS 32/35, 36/40, 45 & 78 11 14 37 RJ45_DN<0> 2
37 14
RXD7 39
9 16 37 RJ45_DP<1> 3
ENET_RX_DV 94 29 MDI_P<0> 4
37 14 RX_DV MDI0+ 37
ENET_RX_ER 3 31 MDI_M<0> 7 18 RJ45_C1_PD 5
37 14 RX_ER MDI0- 37
33 MDI_P<1> 6
1 1 MDI1+ 37
R311 1 R377 R263 37 14 ENET_CRS 84
CRS MDI1- 34 37 MDI_M<1> 8 17 39
RJ45_DN<1>
37 7
10K 10K 1.5K 83 39 6 39
19 37 8
5% 5% ENET_COL MDI2+ 37 MDI_P<2> RJ45_DP<2>
5% 1/16W 1/16W
37 14 COL
1/16W 41 MDI_M<2>
MF MF
402 2
MF
402 2
MDI2- 37
402 2 ENET_MDC 25 42 MDI_P<3> 4 21 RJ45_C2_PD
37 14 MDC MDI3+ 37
10
24 43
R287 37 14 ENET_MDIO
MDIO MDI3- 37 MDI_M<3>
5 39
20 37
12
1
1K 2
RJ45_DN<2>
INT_ENET_RST_L
B
15
5%
1/16W
D1 15 ENET_ENERGY_DET 23 INT-/
LED_LINK10
LED_LINK100
76
74
LED_LINK10
LED_LINK100
R289
49.9
1
R305
49.9
1
R315
49.9
1
R327
49.9
1 3 39
22 37 RJ45_DP<3>
CHGND1
Short shielded RJ-45
B
MF INT+ 73 NC 1% 1% 1% 1% 1 24
402 1N914 LED_LINK1000 1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
RJ45_C3_PD
IO_RESET_L 3 1 ENET_RST_L 28 70 NC
30 26 23 19 18
RESET LED_DUPLEX 402 2 402 2 402 2 402 2
39
69 LED_RX_SPN 2 23 37 RJ45_DN<3>
SOT23
LED_RX SM
27 68 NC 1 1 1 1
ENET_COMA
COMA LED_TX R297 R298 R323 R326 XFR-ENET-1000BT
49.9 49.9 49.9 49.9 T1
1% 1% 1% 1%
6 C425 1
CONFIG0 65 (000) 1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF CRITICAL
2.2uF 82 64 1 1 1 1
D Q65 20%
10V
NC S_IN+ CONFIG1 (000) 2 402 2 402 2 402 2 402 R345 R328 R307 R290
2N7002DW CERM 2 NC 81
S_IN- CONFIG2 63 (111) 75 75 75 75
AC_IN 2 G S
SOT-363 3 805 61 SEE CONFIG TABLES MDI0_PD MDI1_PD MDI2_PD MDI3_PD 5% 5% 5% 5%
31 30 29 CONFIG3 (110)
(BELOW)
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
77 60
1
D
Q65 NC S_OUT+ CONFIG4 (111) 1 C426 1 C465 1 C431 1 C434 2 402 2 402 2 402 2 402
2N7002DW NC 75
S_OUT- CONFIG5 59 (101) 0.01UF 0.01UF 0.01UF 0.01UF
SOT-363 ENET_CTAP_CHGND 38
SLEEP_L_LS5 5 G S 58 20% 20% 20% 20%
35 34 33 20 CONFIG6 (000) 16V
2 CERM
16V
2 CERM
16V
2 CERM
16V
2 CERM
NC 79
4 S_CLK+ 402 402 402 402 1 C725
NC 80 44 JTAG_ENET_TDI
S_CLK- TDI 14
100pF
50 JTAG_ASIC_TDO_TP PLACE RESISTORS CLOSE TO PHY 10%
TDO 39 3KV
2 CERM
PLACES PHY IN "COMA" MODE WHEN ENET_HSDACP 37 49 JTAG_ASIC_TCK
HSDAC+ TCK 14 39 1808
ASLEEP ON BATTERY (SAVES POWER) ENET_HSDACM 38 46 JTAG_ASIC_TMS
HSDAC- TMS 14 39
47 JTAG_ASIC_TRST_L CHGND1
TRST 14 39
36
36
CLK25M_ENET_XIN
CLK25M_ENET_XOUT
55
54
XTAL1
XTAL2
RSET 30 ENET_RSET
MARVELL 88E1111
NO STUFF 56 NC
SEL_OSC CONFIG DEFINITIONS
R342 ENET_VSSC 53
VSSC SEL_2.5V 13
20K
1 2
GND PIN BIT[2:0] CONFIG INPUTS
10/100/1000 ETHERNET
A PUT CRYSTAL CIRCUIT CLOSE TO PHY 5%
1/16W
1
NO STUFF NO STUFF 97 VDDO 111 PIN BIT[2] BIT[1] BIT[0] A
MF
402 R344 R2531 R2541 1
R343 1
R438
LED_LINK10 110 CONFIG<0> PHYADR[2] PHYADR[1] PHYADR[0] NOTICE OF PROPRIETARY PROPERTY
0 LED_LINK100 101 CONFIG<1> ENA_PAUSE PHYADR[4] PHYADR[3]
5% 49.9 49.9 10K 4.99K THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
CRITICAL 1/16W 1% 1% 5% 1% LED_LINK1000 100 CONFIG<2> ANEG[3] ANEG[2] ANEG[1] PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
MF 1/16W 1/16W 1/16W 1/16W AGREES TO THE FOLLOWING
Y3 2 402 MF
402 2
MF
402 2
MF MF LED_DUPLEX 011 CONFIG<3> ANEG[0] ENA_XC DIS_125
25.0000M 2 402 2 402 LED_RX 010
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1 2 CLK25M_XTAL_IN CONFIG<4> MODE[2] MODE[1] MODE[0] II NOT TO REPRODUCE OR COPY IT
LED_TX 001 CONFIG<5> DIS_FC DIS_SLEEP MODE[3]
SM-2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
VSS 000 CONFIG<6> SEL_BDT INT_POL 75/50 OHM
C430 1 C429 1
SIZE DRAWING NUMBER REV.
33pF 33pF
5%
50V
CERM 2
5%
50V
CERM 2 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
APPLE COMPUTER INC.
D 051-6469 F
402 402 PART NUMBER
SCALE SHT OF
Y3’S LOAD CAPACITANCE IS 20PF 197S0703 197S0603 Y3
TABLE_ALT_ITEM
NONE 27 44
8 7 6 5 4 3 2 1
CR-28
8 7 6 5 4 3 2 1
LM2594_IN
38
165MA MAX LOAD
D27
SC-59 CRITICAL
38 29 28 +3V_FW
+1_95V_FW_DVDD 28 38
CRITICAL
38 29 28 +FW_PWR_OR 1 U31 L41 1
LM2594
+5V_SLEEP 3 7 SM 4 220uH
VIN FB 1
R369
2 VOUT
8 1 2 L3 1 C758 1 C745 1 C513
SM-3
400-OHM-EMI 10 0.1UF 0.1UF 2.2UF
GND ON/OFF SM-1 5% 20% 20% 20%
1/16W 10V
MF 2 10V 2 10V 2 CERM
SDM20E40C 6 5 +3V_FW_UF 38
2 402
CERM
402
CERM
402 805
2
C779 1 2 C783 1 38 +1_95V_FW_DVDD_PORT1 PHY PINS 72,76
10UF D20 100UF
N20P20% 20%
50V SM 10V 2 1 C514 1 C508 +1_95V_FW_PLLVDD 28 38
D CERM 2
2320 1
MBR0540 POLY
SMD-3
20%
2.2UF
20%
0.1UF D
10V
2 CERM
10V
2 CERM R6721 1
R461
805 402 3.3 3.3
5% 5%
1/16W 1/16W
MF MF
PHY PIN 64 603 2 2 603
R392
1
1 2 38 +3V_FW_AVDD_PORT2 +1_95V_FW_PLL500VDD
CRITICAL 38
U33 VOUT = 1.22*(1+R2/R1)+ IADJ*R2
5%
1/16W C531 +1_95V_FW_PLL400VDD 38
1UF
PHY PIN 61
LTC1761ES5-BYP MF
IADJ = 30NA AT 25C 603
SOT-23-1 1 2
SYM_VER2
1 OUT 5
IN 38 28 +1_95V_FW_PLLVDD
20%
10V
2 C775 1 C576
CERM 1UF 1UF
FWPLL_BYP 3 BYP ADJ 4 R409 603 20%
10V
1 CERM
20%
10V
1 1 2 CERM
GND R482 1 2 38 +3V_FW_AVDD_PORT1 603 603
C587 1 16.2K 5% C546 +1_95V_FW_DVDD 28 38
R404
FW_PLL_ADJ
2.2UF 1 C591 2 1% 1 C590 1/16W
1UF 22
PHY PIN 50
1/16W MF
20% 0.01UF MF 10UF FW_PHY_CNTL<0> 1 2 FW_LINK_CNTL<0> 14
10V
CERM 2 20% 2 402 20%
603 1 2 PHY PIN 25 PHY PIN 28 R462 37 28
5%
37
805 2 16V 2 6.3V
CERM 1 1/16W
1 2
CERM
402 R2 805 20%
10V
38 +1_95V_FW_DVDD_RX0
R403 MF
402
R463 CERM 5% 22
603 1/16W 37 28 FW_PHY_CNTL<1> 1 2 FW_LINK_CNTL<1> 14 37
R483 1
1 2
MF
38 +3V_FW_AVDD_PORT0 603 5%
1
27.4K2 1/16W
5%
1/16W C578 R1000 MF
402 R396
PHY PIN 40
1%
1/16W
MF
603
1UF 38 +1_95V_FW_DVDD_TX0 1
1 2 CLKFW_PHY_PCLK 1
22 2 CLKFW_LINK_PCLK
36 28 14 36
MF 1 2
402 R1 1 C577 5%
1/16W
5%
1/16W
20%
10V 20%
0.1UF 1 C1000 MF
603
MF
402
R460 CERM 0.1UF
603 2 10V
CERM 20%
1 402 10V
2 CERM
C +1_95V_FW_DVDD 28 38
1
5%
1/16W
2 38 +3V_FW_AVDD
C575 402 C
1UF
PHY PIN 21
U34 1 C595 1
R485 MF
603 1 2
PHY PIN 38
DSX STRAP OPTIONS
LT1962-ADJ
MSOP
0.01UF
20%
16.2K 1 C593
1% 10UF
8 IN OUT 1 16V
2 CERM 1/16W
MF
20%
6.3V
20%
10V 1 C519 1 C507 1 C769 1 C749 1 C506 0 -> BILINGUAL PORT
402 2 CERM CERM 10UF 0.1UF 0.1UF 0.1UF 0.1UF
7 2 402 603 20%
NC NC R2
805 20%
6.3V
20%
10V
20%
10V
20%
10V 10V
2 CERM 1 -> A-ONLY PORT
ADJ 2 2 CERM 2 CERM 2 CERM 2 CERM
C588 1
NC 6 NC
FW_CORE_ADJ
805 402 402 402 402
2.2UF 1
20%
10V BYP 3 FW_CORE_BYP 1
R484 R366 1
R367 PHY PINS 4,14
CERM 2 1K 0
805 5 SHDN GND 4 27.4K 5% 5%
1% 1/16W
1/16W MF 1/16W
MF PLACE NEAR PHY
RX0
MF 2 402 SPEC SAID TO USE 10K
2 402
31 TX0
2 402
R1 R4722 2
R388
1K 10K
24
39
44
51
57
63
37
65
71
18
69
70
29
30
8
6
VOUT = 1.22*(1+R2/R1)+ IADJ*R2
R3641 R3681 5%
1/16W
MF
5%
1/16W
MF 1 C523 C556 1
IADJ = 30NA AT 25C 1K 1K 402 1 AVDD DVDD DVDD PLL PLL
5% 5% 1 402 1UF 1UF R4251 1
R419
1/16W 1/16W
33
3.3 1.8 3.3 VDD VDD R4051 1
R397 20% 20%
56.2 56.2
MF
402 2
MF
402 2
DS0 CRITICAL 1.8 3.3 56.2 56.2 10V
2 CERM 10V
CERM 2 1% 1%
FW_PORT1_SEL 32 DS1 5 CLKFW_PHY_PCLK 28 36
1% 1% 603 603 1/16W 1/16W
PCLK 1/16W 1/16W
36 14 CLKFW_PHY_LCLK 7
LCLK U28 1 FW_PINT
MF
402 2
MF
2 402
MF
402 2
MF
2 402
PINT 14 37
80
TSB81BA3A
14 FW_PHY_LPS
LPS PQFP 79 NC FW_TPA0P (TXD-FWB)
(SYM_VER1)
CNA 29 37
FW_PHY_LREQ 3 FW_TPA0N (TXD-FWB)
37 14
LREQ 9 FW_PHY_CNTL<0> 29 37
PWR CLASS = 100 SN0201029PFP CTL0
10 FW_PHY_CNTL<1>
28 37
28 37 FW_TPA1P (TXD-FWA)
38 29 28 +FW_PWR_OR
(MAY PROVIDE POWER, OR FW_PC_PU 66 CTL1 29 37
MAY REQUIRE UP TO 3W)
PC0
FW_PC_PD 67 FW_TPA1N (TXD-FWA)
(PC0 IS MSB, PC2 IS LSB) PC1 1MA(MAX) BUS HOLDER EACH 2 FW_LKON 14 29 37
C/LKON
B R456
402K
1 68
PC2
46
B
FW_TPA0P
1% 15 FW_PHY_PD 77 (TXD-FWB) TPA0+
1/16W PD 45 FW_TPA0N FW_TPB0P (RXD-FWB)
MF (TXD-FWB) TPA0-
402 2 FW_TPB0N (RXD-FWB)
FW_BMODE 74 53 FW_TPA1P
BMODE (TXD-FWA) TPA1+
52 FW_TPA1N FW_TPB1P (RXD-FWA) 29 37
(TXD-FWA) TPA1-
FW_CPS 34 FW_TPB1N (RXD-FWA)
CPS 59 NC 29 37
1 8
TPA2+
FW_LINK_DATA<0> 37 FW_PHY_DATA<0> 11 58 NC
37 14
37 14 FW_LINK_DATA<1> 2
RP36
22 7 37 FW_PHY_DATA<1> 12
D0 TPA2-
5% D1 42 37 29 FW_TPB0P
R4201 1
R410
37 14 FW_LINK_DATA<2> 3 1/16W 6 37 FW_PHY_DATA<2> 13 (RXD-FWB) TPB0+
SM1 D2 41 37 29 FW_TPB0N 56.2 56.2
37 14 FW_LINK_DATA<3> 4 5 37 FW_PHY_DATA<3> 15 (RXD-FWB) TPB0- 1% 1%
1 8
D3 1/16W 1/16W
FW_LINK_DATA<4> FW_PHY_DATA<4> 16 49 FW_TPB1P MF MF
37 14
FW_LINK_DATA<5> 2
RP35
22 7
37
37 FW_PHY_DATA<5> 17
D4 (RXD-FWA) TPB1+
48 FW_TPB1N
402 2 2 402 1 1
37 14
FW_LINK_DATA<6> 3 5% 6 FW_PHY_DATA<6> 19
D5 (RXD-FWA) TPB1- R432 R429
37 14 1/16W
SM1
37
D6 56 FW_TPB2_PD FWB_TPB1 56.2 56.2
37 14 FW_LINK_DATA<7> 4 5 37 FW_PHY_DATA<7> 20 TPB2+ 1% 1%
D7 55 1/16W 1/16W
TPB2- 1 MF MF
75 47
R411 2 402 2 402
FW_PHY_RESET_L
RESETZ TPBIAS0 FW_BIAS0
C542 1%
4.99K
TPBIAS1
54 FW_BIAS1 220PF 1/16W
5% MF FWB_TPB0
FW_INPUT_PD 35 60 NC 25V
SE TPBIAS2 2 402
R440 CERM
402
1 47 1
R391 36
SM XI
27 36 FW_XI 1 2
C563 R433
1K XO
26 NC 5%
1/16W +3V_FW
220PF 4.99K
5% 28 29 38 5% 1%
1/16W FW_TESTM 78 MF 25V 1/16W
MF TESTM 402 CERM MF
23 FW_R0 402
2 402 R0 2 402
A
FW_VREG_PD 73 VREG_PD
THRML
R1
22 FW_R1
1 C584
FIREWIRE
C505 1 R3651
1K
PAD
AGND DGND PLLGND R471
6.34K1
1
R673
100
0.22UF NO STUFF
NOTICE OF PROPRIETARY PROPERTY
A
0.22UF R6591 R6501 2 20%
81
21
40
43
50
61
62
4
14
38
64
72
76
25
28
20%
6.3V 2
5%
1/16W 470 1K
R3931 1%
5%
1/16W
6.3V
2 CERM
4
R6741
CERM MF 5% 5% 1K 1/16W MF 402 100K THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
402 402 2 1/16W
MF
1/16W
MF
5%
1/16W
MF
402
2 402 VCC
5%
1/16W PLACE NEAR PHY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
402 2 402 2 MF MF
402 2 402 2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
G1 II NOT TO REPRODUCE OR COPY IT
98.304M
OSC III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
36 FW_OSC 3 SM-A
OE 1 FW_OSC_EN
CAPACITOR IN CONJUCTION WITH OUT
INTERNAL PULLUP PROVIDES CRITICAL SIZE DRAWING NUMBER REV.
RESET PULSE WHEN PHY FIRST
GND
RECEIVES POWER
D 051-6469 F
2 APPLE COMPUTER INC.
28 44
SCALE SHT OF
NONE
8 7 6 5 4 3 2 1
CR-29
8 7 6 5 4 3 2 1
PORT POWER SWITCH 38 28 +3V_FW
R762
L54
400-OHM-EMI
+PBUS
1
10K 2 1 2
38 +3V_FW_ESD_ILIM +3V_FW_ESD 29 38
CRITICAL
5% SM-1
Q7 1/16W
MF
NDS9407 402 1 C860 1 C861 3 D6 D8
F2 SOI
D31 0.1UF 0.001UF
SOT23
1N5227B
BAV99DW
SOT-363
BAV99DW
SOT-363
1.5AMP-33V 8 20% 20%
2 1 38 +FW_FUSE 3
7 1
B240
2
10V
2 CERM 50V
2 CERM 1DZ2 5 5
38 +FW_SW 38 28 +FW_PWR_OR 402
2 402 3 3
SM 6
D 1
R265
1
5 SM
4 4 D
470K
1 C738
0.01UF 1 C864
5%
1/16W 20% 4 C863 1
0.01UF
MF
2 402
16V
2 CERM
402
0.01UF
20%
D6 D8 20%
16V
+3V_PMU 16V BAV99DW BAV99DW 2 CERM
CERM 2 SOT-363 SOT-363 402
FW_PWR_GATE 402
2 2
F3 6 6
R654 1 1.5AMP-33V
1
R653 2 1
100K
5%
1/16W
330K
5% SM
1 1
PORT 0
MF
DP4 1/16W
402 2
BAS16TW
SOT-363
MF
2 402 1 514S0024
POWER_UP 1 6
FW_PWREN_L L34 FIREWIRE B - BILINGUAL CRITICAL
FERR-250-OHM
6 SM J22
D
Q17 3 38 +FW_PWR_PORTA 1394B
F-RT-SM
2N7002DW 2 11
33 30 PMU_POWER_UP_L 2 G S
SOT-363 D Q71
2N7002DW 1
SOT-363 FW_TPA0P 4
1 RUN_OR_AC 5 G S 37 28 TPA
4 L37 37 28 FW_TPA0N
AREF 39 38 FW_TPO0R 5
3
TPA(R)
TPA*
OUTPUT
DP4 FERR-250-OHM FW_VGND0 6
SM 38 VG
BAS16TW NC 7 SC
SOT-363
4 3 38 +FW_VP0 8 VP
39 34 33 32 20 DCDC_EN 2
37 28 FW_TPB0P 2 TPB
C DP4
BAS16TW 37 28 FW_TPB0N
BREF (TPI0R) 9
1
TPB(R)
TPB*
INPUT C
R656 SOT-363
AC_IN 2
10K 1 AC_IN_FW_CNTL 2 5
31 30 27 10
5%
1/16W
MF NO STUFF
1
402 R655 CLEAR OUT ALL PLANES UNDER TRANSFORMERS
C549 1 1 C740
470K
5% 0.01UF 0.01UF
1/16W 20% 20%
MF NO STUFF 16V 16V
CERM 2 2 CERM
2 402 1 402 402
R668 1 C751 1 C746 CHGND1
1M 0.1UF 0.01UF
5% 20% 20%
1/16W 50V
2 CERM 16V
2 CERM
MF
805 402
2 402
+3V_FW_ESD 29 38 2 CHGND6
CHGND1 R376
0
5%
ENABLES PORT POWER WHEN MACHINE IS D13 D15
1/10W
FF
1 805
BAV99DW BAV99DW AREF NEEDS TO BE ISOLATED FROM
RUNNING OR WHEN ASLEEP ON AC 5
SOT-363 SOT-363
5 ALL LOCAL GROUNDS PER 1394B SPEC
3 3 SO WHEN A BILINGUAL DEVICE
IS PLUGGED TO BETA-ONLY DEVICE,
STATE PMU_POWER_UP_L POWER_UP DCDC_EN AC_IN Q7_ON_OFF 4 4 THERE’S NO DC PATH BETWEEN
SHUTDOWN C859 1 THEM (TO AVOID GROUND OFFSET ISSUE)
(AC) 1 0 0 1 OFF 0.01UF
20%
1 C862
0.01UF
16V
CERM 2
D13 D15 20% BREF SHOULD BE HARD CONNECTED TO
SLEEP 1 0 1 1 BAV99DW BAV99DW 16V
B (AC) ON 402
2
SOT-363 SOT-363
2
2 CERM
402 LOGIC GROUND FOR SPEED SIGNALING B
RUN 0 1 1 1 AND CONNECTION DETECTION CURRENTS
(AC) ON 6 6
PER 1394B V1.33
SHUTDOWN 1 1 1
(BATT) 0 0 0 OFF
SLEEP 1 0 1 0 OFF
(BATT) (PULL-DOWN RESISTOR) CLEAR OUT ALL PLANES UNDER TRANSFORMERS
FIREWIRE A
RUN 0 1 1 0 ON CRITICAL
(BATT) L51
260-OHM-330MA
SM1
PORT 1
2.99V +3V_PMU +4_6V_BU +3V_PMU FW_TPA1P 3 SYM_VER-2 4
37 28
514-0057
37 28 FW_TPA1N 2 1 CRITICAL
CRITICAL
J24
1394A
L52
260-OHM-330MA
F-RT-TH
SM1 39 37 FW_TPO1P 6
37 28 FW_TPB1N 3 SYM_VER-2 4 TPO
39 37 FW_TPO1N 5
TPO#
FW_TPB1P 2 1 39 37 FW_TPI1P 4
37 28
TPI
39 37 FW_TPI1N 3
TPI#
A 38 FW_VGND1
38 +FW_VP1 1
2
VP
FIREWIRE PORTS
VGND
NOTICE OF PROPRIETARY PROPERTY
A
1 C772 1 C770 7 8 9 10
1 0.01UF
R434 20%
16V
0.01UF
20%
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
0 2 CERM 16V
2 CERM AGREES TO THE FOLLOWING
5% 402
1/10W 402 CHGND6 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
FF
2 805 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
CHGND6 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 29 44
8 7 6 5 4 3 2 1
CR-30
8 7 6 5 4 3 2 1
+3V_PMU +3V_PMU
R450 R696
10K
1
470K 2 30 PMU_EPM 2 1
CHARGE_LED_L 30 31 39
5%
+3V_PMU
R478
5%
1/16W
R686
1/16W
MF R699
MF +3V_PMU_AVCC 30 38 402 10K
1
10K 2
402
1
4.7 2
30 25 PMU_RESET_BUTTON_L 2 1
PMU_POWER_UP_L 29 30 33
5%
5% 5% TABLE_5_HEAD
1/16W
1/16W
MF R481 C589 1 C798 1 C797 1
1/16W
MF C791 1 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
R442 MF
402
402
1
10K 2 SOFT_PWR_ON_L 10UF 0.1UF 0.1UF 402
0.1UF
TABLE_5_ITEM
100K 1
22 23 30 34
20% 20% 20% 20% 341S1008 1 IC,PMU,V81B U39 30 PMU_POWERUP_OK 2
5% 6.3V 10V 10V 10V
1/16W CERM 2 CERM 2 CERM 2 CERM 2 5%
MF 805 402 402 402 1/16W
D
402
CPU_VCORE_HI_OC/PMU_AP should
MF
402 D
R695 14 60 97 have a pulldown for coming out of
reset. MLB will have a pull-up
100K 2 to +3V_MAIN or +3V_SLEEP, which
1 MAIN_RESET_L 18 19 21 24 26 30 39 VCC AVCC will act as our pulldown since
both are off during PMU reset.
R477
5% PMU_BATT1_DET_L_PU 2
470K 1
1/16W 30
RP52 MF
OMIT 44
(PMU_AP)
5%
100K 402
39 23 KBD_Y<0> 86 CPU_VCORE_HI_OC 7 34 1/16W
4 5 IO_RESET_L 18 19 23 26 27 30 P00_D0 P50_WRL_WR 43 MF
R480
5%
39 23 KBD_Y<1> 85
P01_D1 U39 P51_WRH_BHE 42
INT_RESET_L 10 14 30 402
470K 1
1/16W
SM1
RP52 39 23 KBD_Y<2> 84
P02_D2 M16C62 P52_RD 41
MAIN_RESET_L 18 19 21 24 26 30 39 39 31 30 PMU_BATT_DET_L 2
100K 39 23 KBD_Y<3> 83 FLAS NC 5%
3 6 SLEEP P03_D3 P53_BCLK 1/16W
23 30 33 35
39 23 KBD_Y<4> 82
P04_D4 P54_HLDA
40
PMU_INT_NMI 15 RP49 MF
5% 39 10K 402
RP52 1/16W
SM1
R448 39 23 KBD_Y<5> 81
P05_D5 P55_HOLD 38
PMU_EPM 30
30 25 PMU_NMI_BUTTON_L 2 7
100K 2.2K 2 KBD_Y<6> 80 INT_PU_RESET_L
1 8 INT_RESET_L 10 14 30 23 NUMLOCK_LED_L 1
39 23
P06_D6 P56_ALE 37
14 25 30
5%
5% 5%
39 23 KBD_Y<7> 79
P07_D7 P57_RDY_CLKOUT PMU_CPU_HRESET_L 23
1/16W
SM1 RP49
1/16W RP52 1/16W 36 1
10K 8
SM1 MF PMU_NUMLOCK_LED_L 78 PMU_ACK_L 15 30 PMU_NMI_L
2
100K 7
402 P10_D8 P60_CTS0_RTS0 35
INT_SUSPEND_REQ_L PMU_CAPSLOCK_LED_L 77 PMU_CLK 5%
9 30
R449 P11_D9 P61_CLK0 34
15
1/16W
5% 39 31 30 CHARGE_LED_L 76 PMU_FROM_INT 15
R446 SM1
2.2K 2 P12_D10 P62_RXD0
R689 1/16W
SM1 23 CAPSLOCK_LED_L 1 33 30 29 PMU_POWER_UP_L 75
P13_D11 P63_TXD0
33
PMU_TO_INT 15 7.15K1
2
1K 1 PMU_BYTE 5% 74 32
PMU_REQ_L
31 30 PMU_SMB_DATA 2
30 NC P14_D12 P64_CTS1_RTS1_CTS0_CLKS1 15
1/16W 31 1%
5% MF 34 30 23 22 SOFT_PWR_ON_L 73 PMU_LID_CLOSED_L 23 30 1/16W
1/16W
R490 402 P15_D13_INT3 P65_CLK1 30 MF
R447
MF 39 25 15 COMM_RING_DET_L 72 PMU_RESET_BUTTON_L 25 30 402
402 10K P16_D14_INT4 P66_RXD1 29 7.15K1
2 1 PMU_CNVSS 30 15 INT_WATCHDOG_L 71 PMU_NMI_BUTTON_L 25 30 31 30 PMU_SMB_CLK 2
P17_D15_INT5 P67_TXD1
5% 28 1%
1/16W 39 23 KBD_X<0> 70 TPAD_RXD 23 30 1/16W
MF P20_A0_D0 P70_TXD2_SDA_TA0OUT 27 MF +3V_SLEEP
402 39 23 KBD_X<1> 69 TPAD_TXD 23 30 402
P21_A1_D1_D0 P71_RXD2_SCL_TA0IN_TB5IN 26
KBD_X<2> 68 SYSTEM_CLK_EN
39 23
67
P22_A2_D2_D1 P72_CLK2_TA1OUT_V 25
CPU_CLK_EN
15
RP49
39 23 KBD_X<3>
P23_A3_D3_D2 P73_CTS2_RTS2_TA1IN_V 9 10K
C 39 23
39 23
KBD_X<4>
KBD_X<5>
66
65
P24_A4_D4_D3 P74_TA2OUT_W
24
23
PMU_CHARGE_V
PMU_CHRG_BATT_0
31
31
30 PMU_I2C_DATA 4
5%
5
C
P25_A5_D5_D4 P75_TA2IN_W 22
1/16W
KBD_X<6> 64 NC SM1
39 23
63
P26_A6_D6_D5 P76_TA3OUT 21
(CHARGE_I)
RP49
39 23 KBD_X<7>
P27_A7_D7_D6 P77_TA3IN NC
3
10K 6
30 PMU_I2C_CLK
61 20
UNDERVOLTAGE RESET CIRCUIT 39 23
39 23
KBD_X<8>
KBD_X<9> 59
P30_A8_D7
P31_A9
P80_TA4OUT_U
P81_TA4IN_U
19
PMU_SLEEP_LED_L
CPU_SMI_L
23
5
5%
1/16W
SM1
+3V_PMU 58 18
30 27 26 23 19 18 IO_RESET_L POWER_VALID 30
P32_A10 P82_INT0 17 +5V_SLEEP
57
39 23 KBD_COMMAND_L
P33_A11 P83_INT1 16
PMU_PME_L 15 26 30
R700
39 30 23 KBD_CONTROL_L 56
P34_A12 P84_INT2 INT_PEND_PROC_INT 15
TPAD_RXD 2
10K 1
1 15 30 23
R492 39 30 23 KBD_SHIFT_L 55
P35_A13 P85_NMI 9
PMU_NMI_L 30 Keep crystal subcircuit close to PMU.
5%
1K 39 30 23 KBD_OPTION_L 54
P36_A14 P86_XCOUT CLK32K_PMU_XOUT 1/16W
MF R701
5% 8
1/16W 39 23 KBD_FUNCTION_L 53
P37_A15 P87_XCIN CLK32K_PMU_XIN 402
2
10K 1
MF 30 23 TPAD_TXD
2 402 15 PMU_INT_L 52
P40_A16 P90_TB0IN_CLK3
5
PMU_BATT0_DET_L R479 NO STUFF
5%
51 4
1
1K 2 R688 1/16W
34 +3V_PMU_RESET 39 23 KBD_ID PMU_BATT1_DET_L_PU 30 PMU_BATT_DET_L 30 31 39 MF
P41_A17 P91_TB1IN_SIN3 3 10M 402
CPU_PLL_STOP_OC 50 NC 5% 1 2
7
P42_A18 P92_TB2IN_SOUT3 2 1/16W
C597 1 NC 49
P43_A19 P93_DA0_TB3IN NC MF 5% +3V_MAIN
0.1UF
20% CRITICAL 35 33 30 23 SLEEP 48
P44_CS0 P94_DA1_TB4IN
1
INT_PROC_SLEEP_REQ_L 15
402 1/16W
MF 1
R687 R497
10V 100 402 100K 1
CERM 2
4 47
P45_CS1 P95_ANEX0_CLK4 PMU_POWERUP_OK 30 0 30 POWER_VALID 2
402 VCC 9 INT_SUSPEND_ACK_L 46
P46_CS2 P96_ANEX1_SOUT4
99
NC R444 5%
1/16W 5%
U38 INT_SUSPEND_REQ_L 45 98
PMU_OOPS 1
1K 2 AC_IN
CRITICAL MF 1/16W
MF R496
30 9
P47_CS3 P97_ADTRG_SIN4 30 27 29 31
2 402 10K
MAX6804
SOT143 95 5% Y6 30 26 15 PMU_PME_L
402
2 1
THERM_L_OC 25 30 1/16W SM-1 CLK32K_PMU_XOUT_UF
39 30 PMU_KB_RESET_L 3 MR* RSET* 2 P100_AN0 93 MF 5%
P101_AN1 92
PMU_AC_IN 402 1 4 R698 1/16W
MF
GND 30 PMU_BYTE 6
BYTE P102_AN2 PMU_AC_DET 30
PMU_LID_CLOSED_L 2
100K 1 402
11 91 32.768K 30 23
CLK10M_PMU_XOUT NC
1 XOUT P103_AN3 90 5%
CLK10M_PMU_XIN 13
XIN P104_AN4_KI0 PMU_I2C_CLK 1 C796 1 C794 1/16W
B NO STUFF PMU_RESET_L 10
96
RESET P105_AN5_KI1
89
88
PMU_I2C_DATA
30
30
5%
12PF
50V
5%
12PF
50V
MF
402 38 30 +3V_PMU_AVCC B
R491 38 30 +3V_PMU_AVCC
VREF P106_AN6_KI2 87
PMU_SMB_CLK 30 31 2 CERM
402
2 CERM
402
R436
1
10M 2
30 PMU_CNVSS 7 CNVSS P107_AN7_KI3 PMU_SMB_DATA 30 31
2
100K 1
30 25 THERM_L_OC
5% VSS AVSS 5%
1/16W 1/16W
R4891 MF
402
12 62 94
MF
402
0 Y6’S LOAD CAPACITANCE IS 12.5PF
5%
1/16W R443
MF Keep crystal subcircuit close to PMU. 1
10K 2
402 2 CRITICAL +3V_PMU 30 PMU_OOPS
Y5 Y5’S LOAD CAPACITANCE IS 12PF 5%
CLK10M_PMU_XOUT_UF
10.00M
1 2 38 32 +4_85V_RAW A29 DETECT CIRCUIT 1/16W
MF
402
R697
100K 2
30 25 14 INT_PU_RESET_L 1
1
SM
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
R430 5%
1/16W
C592 1 C598 1 PART NUMBER 100K MF
1% 402
PMU KEYBOARD RESET CIRCUIT 12PF
5%
12PF
5% 197S0704 197S0604 Y5 Alt crystal size
TABLE_ALT_ITEM 1/16W
MF
1 C257 R3241
50V 50V 2 402 1 0.1UF 10K
CERM 2
402
CERM 2
402
R266 20%
10V
5%
1/16W
+3V_PMU ADAPTER_DET 31 39
5.23K 2 CERM MF
1% 402 402 2
1/16W
1 MF
R445 2 402 A29_DETECT 31
100K
34 30 23 22 SOFT_PWR_ON_L13
14
74LVC32
TSSOP
Q11 ADAPTER DETECTION SCHEME 1%
1/16W
MF 3
11 PMU_KB_RESET_IN1 2 402 U53
U32 +3V_PMU
ID VOLT PMU_AC_DET 4
2
LMC7211
D
Q57
39 30 23 KBD_CONTROL_L12 32 CASE ADAPTER PIN VOLT RANGE
SYSTEM STATUS 30
SM
2N7002
SM
7
14
74LVC32
1 Q11 (65W)
2.007V-
2.066V
1.65V-
2.31V
RECOGNIZES AS Q11
FULL FUNCTIONS
1
R902
402K 2_34V_REF 3
1 A29_DET_L 1 G S
2
PMU
A 4 TSSOP
6 PMU_KB_RESET_L 2.558V- 2.31V- RECOGNIZES AS A29
1%
1/16W
MF 5
NOTICE OF PROPRIETARY PROPERTY
A
+3V_PMU U32 30 39
2 A29 (45W) 2 402
5 32 2.661V 2.97V LIMITED FUNCTIONS R270 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
499K 2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
7
14 0.589V- 0.33V- FULL FUNCTIONS AGREES TO THE FOLLOWING
10
74LVC32 3 AIRLINE 0.663V 0.99V NO BATTERY CHARGING
1%
1/16W I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
KBD_SHIFT_L TSSOP 1 MF
39 30 23
8 PMU_KB_RESET_IN2
R269 402 II NOT TO REPRODUCE OR COPY IT
U32 3.19V- 2.97V- RECOGNIZES AS HOOPER 12.7K III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
39 30 23 KBD_OPTION_L 9 32 4 HOOPER 3.28V 3.30V LIMITED FUNCTIONS
1%
1/16W
50MV OF HYSTERSIS
MF SIZE DRAWING NUMBER REV.
7 2 402
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 30 44
8 7 6 5 4 3 2 1
CR-31
8 7 6 5 4 3 2 1
1MSEC INTEGRATION TIME
PLACE U24 NEXT TO R382 BATTERY SWITCH-OVER CIRCUIT
DC POWER INPUT DC INRUSH LIMITER U24 SENSE VOLTAGE DROP ACROSS R382 R744 C757
0.1UF
+BATT
(POWER JACK, ETC. ON SEPARATE BOARD) 1
1K 2 1 2
38 +ADAPTER_SW IAC_RC_COMP
CRITICAL
1%
1/16W 20% 1 1
J19 Q8 Q10 MF
402
10V
CERM F5 F4
87438-0833 SI4435DY SI4435DY 402 +24V_PBUS
5AMP-125V
M-RT-SM
SOI SOI 1 C532 +3V_PMU 5AMP-125V
SM-2 SM-2
1 CHARGE_LED_L 30 39 0.01UF
8 8 20%
2 38 32 +ADAPTER 3 S3 D4
7 7
D4 S3 3 38 +ADAPTER_SENSE 2 50V
CERM 38 31 +BATT_24V_FUSE 2 38 +BATT_14V_FUSE 2
3 2 S2 D3 D3 S2 2 603
D2 6 6
D2
1 C472 D30 +PBUS
D28
4
R3362 C439 1 1
S1 5 5 S1 1 0.1UF RS3AB RS3AB D
D 5
6
330K
5%
1/16W
0.1UF
20%
50V
GATE
D1 D1
GATE
1
R7451
42.2K
20%
10V
2 CERM
402
PLACE R383 CLOSE TO LTC1625 2 1 2 1
7
MF
402 1
CERM 2
805
4 4 R394 8
0.1%
1/16W ROUTE LTC1625_ITH CAREFULLY SM SM
47K FF
8 ADAPTER_DET 5% +24V_PBUS 603 2 LTC1625_ITH
30 39
AC_ENABLE_GATE
1/16W
MF V+ U54 DP3 Q16 Q60
2 +3V_PMU
2 402 U24 2 LMC7111 SI4435DY IRF7416
R473 MAX4172 IAC_FB 4
SOT23-5
BAS16TW
SOT-363 R383 SOI SOI
20K BCKFD_PROT_GATE
TSSOP 150
1% 2 1 2 1 6 1 2 1 1625_COMP 8 8
1/16W
MF R300 RS+ RS-
1%
32
3 S3 D4
D3 7
3 S3 D4
D3 7
1 402
470K C843 1 1 3 2 S2 2 S2
1
5%
1/16W 0.1UF
R414 NC 3 NC1 PG
7
NC R742 1/16W
MF
1 D2 6
1 D2 6
C449 1 R291 MF 20% 68K 4 6
10K 5 ADAPTER_I_REG 402 S1 5 S1 5
MAX4172_OUT 1 2 D1 D1
R3092 R2921 0.01UF 10K 1 402
50V
CERM 2
5%
1/16W
NC
NC2 OUT
GATE GATE
102K 100K 20% 5% 805 MF GND 1%
1 R660 1
1% 1% 16V
CERM 2
1/16W
MF
AC_ENABLE_L 2 402
1/16W
MF R407 4 47K 4
1/16W 1/16W 402 BCKFD_PROT_EN_L 402 CURRENT_THRESHOLD 47K
MF MF 2 402 5 5%
402 1 402 2 3 R3841 1
5%
1/16W 1/16W
MF
2 U16 6 2.21K R7431 1
+3V_PMU R746 MF
402 2 402 2
1V20_REF 4
LMC7211
D
Q4 0.1%
1/16W 42.2K R371 51.1K BATT_14V_GATE
38 32
SM
2N7002DW D Q14 MF 0.1% 82.5K 0.1%
1/16W IF ADAPTER IS OVER 18V, BATT_24V_GATE
1 31 30 29 27 AC_IN 5 G S
SOT-363 2N7002DW 603 2 1/16W
FF
0.1%
1/16W FF ADJUST CURRENT SETTING
SOT-363
31 30 29 27 AC_IN 2 G S 603 2 FF 2 603 R6571
3 2 603 R4221
AC_DIV 4 A29_CURRENT_ADJ R7471 OVER_18V_ADJ
10K
10K
5%
5 R316 1 100K 5% 1/16W
R301 2
R293 2
1
1M 2
AC_IN_L 31
3 5%
1/16W 6
31 AC_IN_L
1/16W
MF
DP3 MF
402 2
10K
1%
57.6K
1%
D Q3100 MF
402 2 D
Q3100
1 C838 402 2
SOT-363
BAS16TW
5% 2N7002DW 1UF
BAS16TW
1/16W 1/16W 1/16W 2N7002DW 20% 1 BATT_24PBUS_EN 5 2
MF MF 6 SOT-363 R415 BATT_14PBUS_EN
4
SOT-363
MF A29_DETECT 5 SOT-363 10V
DP3
402 1 402 1 402 31 30 G S AC_GTR_18V 2 G S 2 CERM
2 470K
Q4 D
R308 603 5% 3
2N7002DW 470K 4 1 1/16W
MF
R382
3
SOT-363 5%
S G 2 1/16W
0.0252 6 2 402
D
Q14
MF 2N7002DW
C 1 1 402
1
1%
IF A29 ADAPTER USED,
ADJUST CURRENT SETTING
D
Q66
2N7002DW
AC_IN_L_RC 5 G S
SOT-363 C
1W
1 1 SOT-363
1 R406 MF
2512 R413 31 1772_ACOK_L 2 G S
C551 1 4
R6631 D10 4.7
5% 5%
4.7
10UF
GREATER THAN 13.5V DETECT 100K
1%
1N914
SOT23
1/16W
MF 1772_CSSP 37
1/16W
MF
1 20%
6.3V
1/16W 3 402 2 CERM 2
MF 37 1772_CSSN 2 402 805
402 2 WHEN AC IS IN, P-CHANNEL FETS ARE QUICKLY (DIODE) TURNED OFF
R678 D11 WHEN AC IS NOT PLUGGED, P-CHANNEL FETS ARE ON
33 1N914 1772_BST_ESR
+3V_PMU SWITCHER VOLTAGE CONTROL SWITCHER CURRENT CONTROL 1 C550 C534 1 1 C535 38 1772_LDO 1 2 1 3 RC TIME IS 480K*10UF @ +3V_PMU
0.47UF 0.47UF
PMU SELECTS BETWEEN TWO VOLTAGES CHARGE DISABLED BY PMU OR INPUT VOLTAGE <18V R6651 20%
1UF 20%
50V
20%
50V 1
5%
1/8W SOT23 1
+24V_PBUS
CHARGE THROTTLED BY LOW BATTERY VOLTAGE 12.7K 2 50V CERM 2 2 CERM R458 FF
1206 R685
1% CERM1 1206 1206
1/16W 1210 100K 4.7
MF 5% 5%
1 1 1 402 2 1/16W C490 1 1/16W
R476 R464 R457 27 26 MF
402 2 0.1UF MF
2 603
27.4K 10K 10K CSSP CSSN
20%
25V
1% 1% 1% CERM 2
1/16W 1/16W 1/16W 38 1772_DCIN 1 DCIN CELLS 16 1772_CELLS
MF
402 2
MF
402 2
MF
U30 LDO 2
603
C557 1 5 6 7 8 1 C515 1 C524 1 C525 1 C526 1 C527
2 402 1772_ACIN 11 ACIN 0.1UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
OD OUTPUT LOW - WHEN AC GREATER THAN 18V 1772_ACOK_L 12 ACOK MAX1772 DLOV 22 1772_DLOV
20%
50V CRITICAL
20%
50V
20%
50V
20%
50V
20%
50V
20%
50V
CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
31 38
QSOP
(+3V_PMU) 13 RFIN BST 25 1772_BST 805
Q54 1812 1812 1812 1812 1812
15 VCTL CRITICAL IRF7805
1772_VCTL DHI 24 1772_DHI 4
SM
1772_ICTL 14 ICTL +BATT_RSNS 38
CRITICAL
LX 23 38 1772_LX
R4661 1 1
1772_ICHG 10 ICHG DLO 21 1772_DLO
1 2 3
L36 +BATT_24V_FUSE 31 38
4.12K R474 R475 28 IINP 10uH R677
1% 1772_IINP PGND 20 (GND)
1/16W 48.7K 1K 0.05 2
MF
402 2
1%
1/16W
1%
1/16W R4551 7 CCV CSIP 19 37 1772_CSIP
1 2 1
MF MF 1K 1772_CCV SM1 1%
CSIN 18
B R4671
BATTV_HIGH
402 2
BATT_LOW_L
402 2 1%
1/16W
MF
402 2
1772_CCI
1772_CCS
6 CCI
5 CCS BATT 17
37 1772_CSIN
5 6 7 8
2
1W
MF
2512
1 C568
4.7UF
1 C582 1 C566
B
100K C782 1 1 C768 D29 20% 4.7UF 1
C795
5% 6 REF = 4.096V 1 C773 CRITICAL 25V 20% 4.7UF
1 REF CLS GND 0.1UF 0.1UF SM 2 25V 33UF
1/16W
MF D Q19 R488 6 3 R4351 C570 1 1 C565 4 3 8 9
1UF
20%
20%
25V
20%
25V Q55 MBRS140T3
2 CERM
1206 CERM
1206
20%
25V
2 CERM 20%
402 2
2N7002DW 5.23K 1K 0.01UF 0.01UF 10V CERM 2 2 CERM 1206 2 25V
1% D
Q22 D
Q22 1% 2 CERM IRF7811W 1 ELEC
BATTV_LOW 2 G S
SOT-363 1/16W
MF 2N7002DW 2N7002DW 1/16W
MF
20%
16V
20%
16V 603
603 603 4
SO-8 R441 1
R421 1
C581 1 C583 1
C567 1
SM1
SOT-363 SOT-363 CERM 2 2 CERM
1 1 4.7UF 4.7UF
2 402 2 G S 5 G S
402 2 402 402 5% 5% 20% 20% 4.7UF
25V
3 1
1772_CCV_RC 1772_REF R6831 1 2 3
1/16W
MF
1/16W
MF
25V
CERM 2 CERM 2
20%
25V
CERM 2
1 4 1 10K 1 XW20 603 2 603 2 1206 1206
1206
D Q19 R412 1%
1/16W
R465 SM
2N7002DW
SOT-363
1K
1%
1 C569 C580 1 MF
402 2
100K
5%
1 2
30 PMU_CHARGE_V 5 G S 1/16W 0.1UF 1UF 1/16W
MF 20% 20% 1772_CLS MF
2 402 2 10V
CERM 10V 402 2
4 +3V_PMU
402 CERM 2
603 R6791
4.12K
1%
1/16W
R4861 +3V_PMU
MF
402 2
100K 6
5% 38 1772_GND
1/16W +BATT
MF
402 2
D Q23 38 +BATT_VSNS
2N7002DW
CHARGE_DISABLE 2 G S
SOT-363
1 C564 R6801 1
R487 BATTERY 2
3 1
0.1UF
20%
100K
1%
499K
1%
R3321 CONNECTOR L7
2 10V 1/16W 1/16W 6.34K L40
CERM MF MF 1% CRITICAL FERR-EMI-100-OHM FERR-50-OHM
D Q23 402
402 2 2 402
1/16W
MF J25
SM
2N7002DW
SOT-363
U35 2
4
402 2
87438-0833
1 2
5 LMC7211
30 PMU_CHRG_BATT_0 G S
1
SM BATT_DIV
A29_CLS_ADJ M-RT-SM 1
L8
SM
BATTERY CHARGER
A 4
BATT_LOW
3
1V65_REF 3 1
2 39 38 +BATT_POS
FERR-EMI-100-OHM A
D
Q66 3 (BATT_IN_PD) 1 2 PMU_SMB_CLK 30
NOTICE OF PROPRIETARY PROPERTY
5 2N7002DW SM
SOT-363 4 BATT_CLK THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
R6821 1
R681 1 C774 31 30 A29_DETECT 5 G S
5
39
39 BATT_DATA
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
V = CELLS X (4.096 + (0.4096 * V / V )) 100K 100K 0.047uF
BATT VCTL REFIN 1%
1/16W
1%
1/16W 10%
16V
4 6 PMU_BATT_DET_L 30 39 L6 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
For 4.15V cells, VCTL = 0.123 REFIN MF MF 2 CERM 7 39 38 BATT_NEG FERR-EMI-100-OHM II NOT TO REPRODUCE OR COPY IT
402 2 2 402
For 4.20V cells, VCTL = 0.245 REFIN
402
8 L9 1 2 PMU_SMB_DATA 30
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
FERR-50-OHM SM
I = (0.2048/R ) * (V / V ) 1 2 SIZE DRAWING NUMBER REV.
CHG _62 ICTL REFIN
SM
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 31 44
8 7 6 5 4 3 2 1
CR-32
8 7 6 5 4 3 2 1
CRITICAL
Q9
FDG6324L
+5V_MAIN SC70-6
3
4 S2 D2 2 1625_EXTVCC 38
1
R341 G2
6
470K
5%
1/16W
MF
402 2
D 1625_ENABLE_L
D
6 CRITICAL
1625_ENABLE 5 G1
D1
S1
Q9
FDG6324L
SC70-6
1 C469
0.1UF
12.8V PBUS SUPPLY +24V_PBUS
20%
10V
1 2 CERM
402
PBUS HOLD-UP CAPS
CONNECT LTC1625 TK PIN AT TOP-SIDE FET
KEEP VIN/TK LOOP SHORT
5 6 7 8
+3V_PMU
1625_INTVCC 38
C572 1 C752 1 C522 1 C555 1
C714 1 C765 1
2.2UF 2.2UF 2.2UF 2.2UF 22uF 22uF
R3352 NO STUFF 20%
50V
CERM 2
20%
50V
CERM 2
20%
50V
CERM 2
20%
50V
CERM 2
20%
35V 2
20%
35V 2
5%
1 1
R322 Q50 1812 1812 1812 1812
ELEC
SM-1
ELEC
SM-1
1/16W 0 1 IRF7805
R3631 C504 1 MF 5% 1625_TG 4
SM 1 C767 1 C586 1 C541 1 1 1
102K 0.1UF 603 1 1/16W
MF EXTVCC D3 CRITICAL 2.2UF 2.2UF 2.2UF
C785 C786 C784
1% 20%
10V 2 402 U18 SM 20% 20% 20%
22uF 22uF 22uF
1/16W 20% 20% 20%
MF CERM 2 LTC1625 1 2 1625_BST_ESR 50V
2 CERM 50V
2 CERM 2 50V 2 35V 2 35V 2 35V
402 2
402 38 1625_VIN 16 VIN SSOP BG 10 1 2 3 CERM ELEC ELEC ELEC
1812 1812 1812
4
2 U22 15 TK CRITICAL TG 13 1
R321
SM-1 SM-1 SM-1
1V20_REF LMC7211 MBR0540 1 C477
38 31
SM D4 2 SYNC VOSENSE 7 2.2
5% 0.22UF
1 3 1 1625_RUNSS 3 RUN/SS INTVCC 11 1/16W
MF
20%
25V
L32 +PBUS
1625_COMP 5 ITH 2 CERM
1625_DIV 3 1N914
31
2 603 805 3 CRITICAL
SOT23 1625_FCB 4 FCB BOOST 12 1625_BST
C R3571
5 R356
1
1M 2 C463 1
8 VPROG SW 14 38 1625_VSW 2 1
C
10K R3042 4700pF SGND PGND 8.0UH-6.8A
1 1 1
1%
1/16W
1%
1/16W C478 1 4.99K 5%
25V 6 9 5 6 7 8
SM1
R285 C732 C736
MF MF
0.1UF
1%
1/16W
CERM 2 158K 33UF 33UF 1
C760
402 2 402
20%
50V
MF
402 1
603
1 CRITICAL
1 C502 1%
1/16W
20%
25V 2
20%
2 25V 33UF
CERM 2
805
R314 Q51 20%
4.7UF MF
2 402
ELEC
SM1
ELEC
SM1
20%
2 25V
0 25V
2 CERM
ELEC
5% IRF7811W SM1
COMP_RC
1 C445 1/16W
MF
1625_BG 4
SO-8 2
1206
470pF
10%
50V
2 402 NO STUFF D26
SM
WHEN +24V_PBUS IS BELOW ~13.44V, 2 CERM
1 C741 1 2 3 MBRS140T3
1
C722
C446 1
603 1 C444 C503
1
R286 C787 1 33UF
1625 IS SHUT-OFF
4700pF 4.7UF 0.0047UF
10%
1
4.7UF
1
16.2K 33UF
C759 1 20%
2 25V
5% OMIT 20%
10V 25V
2 CERM 20% 1% 20%
33UF ELEC
25V 2 CERM 25V 1/16W 25V 2 20% SM1
CERM 2 402 CERM 2 MF 25V 2
603 XW6
SM
1206
1206 2 402
ELEC
SM1 ELEC
SM1
38 1625_SGND 1 2
1625_VFB
BACKUP BATTERY / USB CONNECTOR
B +5V_MAIN
B
CRITICAL
J12
54550-1490
F-RT-SM
BOOTSTRAP SYSTEM FROM
ADAPTER OR BATTERY
PMU SUPPLY
15
R418 D17
SM +5V_MAIN
38 31 +ADAPTER 1
390 2 38 +ADAPTER_ILIM 1 2 D9
SM 3V_PMU_VTAP
1 NC
5% 1 2
2 1/4W
+PBUS
3
FF MBR0540 6 6
1210
4 PLUS5VTAP MBR0520LT VTAP +3V_PMU
DCDC_EN 20 29 33 34 39
+BATT
5 D18 U29 D12 (+4_6V_BU) U25
6 SM LP2951 +4_85V_RAW 30 38 SM +4_6V_BU 33 38 LP2951
RIGHT_USB_DM 26 37 39 SOI SOI-3.3V
+24V_PBUS 1 2 38 +ADAPTER_OR_BATT 8 1 1 2 8 1
7 RIGHT_USB_DP 26 37 39
IN OUT IN OUT
2 5 2 5
8 2 SENSE ERR 1
R402 SENSE ERR
9 NEC_RIGHT_USB_PWREN
MBR0540 D19 3
SHUT FDBK 7
R428 1
1
MBR0520LT 3
SHUT FDBK 7 1
R390
10
26 39
SM
MBR0540 GND 294K
1%
1 C562 5%
1/16W GND 1
5%
1/16W 470pF MF 1/16W
11 NEC_RIGHT_USB_OVERCURRENT 1 4 MF 10%
26 39
402 2
50V
2 CERM 2 603 4 MF
12 2 603
13 NC
1 C574 C548 1
FB_4_85V_BU
603
+4_85V_ESR
3V_PMU_SENSE
0.1UF 0.1UF 38
+3V_PMU_ESR
14 20%
2 50V
20%
10V
1 C518 38
CERM CERM 2 0.1UF
+PBUS IS BOTH AN INPUT AND OUTPUT TO BUBBA
805 402 R4541 1 C530 20%
16 100K
1% 2.2UF
10V
2 CERM 1 C540
20% 402 10UF
24V IS AN OUTPUT FROM BUBBA 1/16W
MF
10V
2 CERM 20%
402 2 805 2 6.3V
CERM
805
12.8V REGULATOR
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 32 44
8 7 6 5 4 3 2 1
CR-33
8 7 6 5 4 3 2 1
3.3V/5V MAIN SUPPLY
+24V_PBUS
C492 1 C468 1 C729 1 C737 1 8 7 6 5 5 6 7 8 1 C771 1 C766 1 C743 1 C750
D 2.2UF
20%
50V
2.2UF
20%
50V
2.2UF
20%
50V
2.2UF
20%
50V CRITICAL CRITICAL
2.2UF
20%
50V
2.2UF
20%
50V
2.2UF
20%
50V
2.2UF
20%
50V
D
CERM 2 CERM 2 CERM 2 CERM 2 38 3707_INTVCC
2 CERM 2 CERM 2 CERM 2 CERM
1812 1812 1812 1812
Q52 Q61 1812 1812 1812 1812
SI4888DY SI4888DY
CRITICAL
SOI
4
R3791 1
R395 1 C529 3V_TG 4
SOI
CRITICAL
+5V_MAIN 38 5V_RSNS 0 47K 4.7UF 3V_RSNS 38 +3V_MAIN
L33 1 R3601
5%
1/16W
5%
1/16W
20%
10V
2 CERM 1
R427 1
L35
MF MF
R651 3 3 2 1 D7
SM 5%
1M 402 2 2 402
1206
5%
1M D14
SM
1 2 3 3
R424
0.0052
1 1 2 MBR0540 1/16W
+5V_MAIN
1/16W
MBR0540 1 2 0.0052
1
MF MF
2 402 2 2 402 2
1% 1%
1/4W 4.8UH 4.8UH 1/4W
C723 1 FF
1206
SM1 2 8 7 6 5 5V_BOOST_ESR NC 3V_BOOST_ESR 5 6 7 8
2
SM1 FF
1206
1 C780
C720 1 22UF D22 22UF 1
C790
330UF
20%
10V SM
CRITICAL
1
22 21 24 10 D33 20%
10V 330UF
20% CERM 2 MBRS140T3 C512 1 R380 EXT INT VIN 3.3
VCC VCC VOUT
R4011 1 C547
CRITICAL SM
MBRS140T3
2 CERM
20%
6.3V 2
TANT
1210
1 Q43 0.22UF 2.2 2.2 0.22UF Q62 1210 2 6.3V
POLY
CASE-D4
1 1
SI4888DY 4
20%
25V
5%
1/16W U27 5%
1/16W 20%
25V 4
SI4888DY 1
SMD
R303 R296 SOI CERM 2 MF
2 603
LTC3707 MF
603 2
2 CERM SOI R4391 R4531
1 C724 5%
10
5%
10 805 5V_TG 27 TG1 SSOP TG2 16 805 10
5% 5%
10 C793 1
22UF 1/16W 1/16W 5V_BOOST 25 BOOST1 BOOST2 18 3V_BOOST 1/16W 1/16W 22UF
20% MF MF MF MF 20%
10V 3 2 1 5V_SW 26 SW1 17 3V_SW 1 2 3 10V
2 CERM 2 402 2 402
38 SW2 38 402 2 402 2 CERM 2
1210 5V_BG 23 BG1 CRITICAL BG2 19 3V_BG 1210
2 SNS1+ SNS2+ 14
37 5V_SNSP 37 3V_SNSP
37 5V_SNSM 3 SNS1- SNS2- 13 37 3V_SNSM
C454 5V_VOSNS 4 VOSNS1 VOSNS2 12 3V_VOSNS C573
0.001uF 8 0.001uF
1 2
5V_ITH ITH1 ITH2 11 3V_ITH
1 2
5V_RUNSS 1 RUN/ RUN/ 15
SS1 SS2
C R3871 1 C528
20%
50V 3707_FCB 7 FCB
3V_RUNSS
1 C560
20%
50V C545 1
1
R417 C
113K
1% 180pF
CERM
402 C539 1 C500 1
3707_FSET 5 FREQSET
PGOOD 28 0.001uF
CERM
402 180pF 1%
63.4K
1/16W 5% 0.001uF 0.047UF 1 C561 20% 5% 1/16W
MF 50V
2 CERM 20% 10% 6 STBYMD 50V
2 CERM 50V
50V 16V 0.1UF CERM 2 MF
402 2 402 CERM 2 CERM 2 20% 402 402 2 402
402 402 SGND PGND 10V
2 CERM
5V_ITH_RC 402 3V_ITH_RC
3707_STBY 9 20
R3861 R4001 1 C533 C521 1
1
R389 C559 1
1
R426 1
R423
21.5K 4.99K 270PF 0.01UF 20K 270PF 4.99K 20K
1% 1% 5% 20% 5% 5% 1% 1%
1/16W 1/16W 25V 16V 1/16W 25V 1/16W 1/16W
MF MF 2 CERM CERM 2 MF CERM 2 MF MF
402 2 402 2 402 402 2 402 402 2 402 2 402
38 3707_SGND
3
3V_5V_OK 35
R431
D Q15 2
2N7002DW XW11 1 C501 THIS SIGNAL IS OPEN COLLECTOR TO GND WHEN POWER IS NOT GOOD
1M 5
SOT-363
SM 220PF IS USED TO QUIET NOISE ON PGOOD ONCE INTERNAL OPEN DRAIN IS DISENGAGED
35 33 20 DCDC_EN_L 1 2 LTC3707_START_RC G S 220PF
5%
5% 1 25V
2 CERM
1/16W
MF
402
4
402 THERE’S NO 10UF INPUT CAP
BECAUSE Q21 IS PLACED AT
5V START TO TURN ON ~12.5MS AFTER DCDC_EN_L
OUTPUT OF +3V_MAIN SWITCHER
D16 1 C558
3V START TO TURN ON ~25MS AFTER DCDC_EN_L 3 1 0.01UF
20% +3V_MAIN +3V_SLEEP
DIODE WILL ENSURE DCDC_EN_L IS QUICKLY DISCHARGED DURING SHUT-DOWN
1N914 2 16V
CERM
SOT23 402
POWERDOWN DELAY IS AROUND 4MS-15.6MS
+4_6V_BU 32 38
DCDC_EN TRUTH TABLE
B 1
R416 PMU_POWER_UP_L SLEEP DCDC_EN DCDC_EN_L State R452 4 +3V_SLEEP LOADS B
470K SLEEP 1
100K 2 3 6
5% 0 0 1 0 Run 35 33 30 23 1) CPU PLL Config Control
1/16W 5
MF 5% 2) INTREPID - IIC AND PCI PULL-UPS
1/16W
2 402 1 (2.99V) 1 1 0 Sleep MF 2 3) MAP17 - 3V RAIL (IF USING D3COLD)
402
DCDC_EN 20 29 32 34 39
1 4) GRAPHIC CHIP SPREAD SPECTRUM CHIP
1 0 0 1 Shutdown TSOP
R437 6 +3V_PMU +3V_PMU +4_6V_BU +3V_PMU VOLTAGE
SI3443DV 5) LVDS DDC PULL-UPS
100K 2 Q21 6) DVI LEVEL SHIFTERS & PULL-UPS & HPD
30 29 PMU_POWER_UP_L 1 35 33 20 DCDC_EN_L
+5V_MAIN 5%
D Q15 7) SOUND BOARD
1/16W 2N7002DW 8) BOOT BANGER
C599 MF
402 3 2 G S
SOT-363
C585 9) HARD DRIVE (IF USING 3V LOGIC)
0.01UF 2200pF
1 2 D Q17 1 3V_SLEEP_PWREN_L 2 1 10) WIRELESS (IF POWERING OFF IN SLEEP)
2N7002DW 1 C571 11) PMU - IIC Pull-ups
20%
16V 35 33 30 23 SLEEP 5 G S
SOT-363 0.01UF
20%
SLEEP LEVEL SHIFTER (3V -> 5V) 5%
50V 12) PCI PULL-UPS
CERM 16V CERM
402 4 2 CERM +5V_MAIN
R494 +5V_HD_SLEEP 24 38
4 402
603
1
100K 2 3 6
33 25 SLEEP_LS5 5V_HD_PWREN
5% 5
1/16W
MF 1 C596 2 1
C792
402
10UF
20%
1 100UF R3021 R2741
TSOP 20% 100K 100K
2 6.3V
CERM SI3443DV 2 10V 5% 5%
POLY 1/16W 1/16W
805 SMD-3
Q24 MF
402 2
MF
402 2
SLEEP_LS5
C628 SLEEP_L_LS5 20 27 34 35
25 33
0.1UF
1 2 SLEEP_L_LS5_EN_L 6 SLEEP_LS5_EN_L 3 3.3V/5V REGULATOR
A 20%
R295
D
Q3 R294
D
Q3 NOTICE OF PROPRIETARY PROPERTY
A
10V 2N7002DW 2N7002DW
CERM
402 4
+5V_SLEEP +5V_SLEEP LOADS 100K 2 2
SOT-363 100K 2 5
SOT-363
R612 35 33 30 23 SLEEP 1 G S 1 G S
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1
100K 2 5V_SLEEP_PWREN 3 6 1) OPTICAL DRIVE 5% 5%
AGREES TO THE FOLLOWING
1/16W 1 1/16W 4
5% 5 2) DVI MF
402
MF
402
1 C437 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W 3) TRACKPAD 0.01UF
MF
402
1 C626 2 1
C623 4) FANS
20%
16V
2 CERM
II NOT TO REPRODUCE OR COPY IT
10UF 1 100UF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
20% 20% 402
TSOP 5) FIREWIRE PHY
2 6.3V
CERM SI3443DV 2 10V SIZE DRAWING NUMBER REV.
POLY
805 SMD-3
Q35 D 051-6469 F
APPLE COMPUTER INC.
SCALE SHT OF
NONE 33 44
8 7 6 5 4 3 2 1
CR-34
8 7 6 5 4 3 2 1
+3V_MAIN
NEW 1.35V->1.30V 1GHZ@1.32V->667MHZ@1.145V
VCORE_FAST<1>
VCORE POWER SEQUENCING 4XVCORE
34
CPU core follows CPU I/O voltage NO STUFF 4XVCORE 4XVCORE NO STUFF
1 1 1 1 1 1 1
4XVCORE 1 C837 NO_4XVCORE
VCORE_FAST<2> 34
(approx. 7ms delay)
R731 R733
1
470K
R735 R737
470K 0
R258
0
R251 R249
470K 470K
R740
10K 16
0.1UF
20% 1
R766 39 38 34 5 CPU_VCORE_SLEEP
+5V_MAIN 470K 5% 5% 5% 5% 5% 5% 5%
10V
2 CERM
VCORE_FAST<3> 34
5% 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 0 NO_4XVCORE
1/16W MF MF MF MF MF MF MF VCC 402 5% 1
MF
2 402 2 402 2 402 2 402 2 402 2 402 2 402
4XVCORE 1/16W R767 VCORE_FAST<4> 34
C3 1
C614 C622 1
2 402 U41 MF
2 402 0 NO_4XVCORE 10UF
1
C611 1
PI3B3257 5% 1 20% 10UF 10UF 10UF
1 1 1
R279 VCORE_SLOW<1> 2
A1 QSOP Y1
4 34 VCORE_VID<1> 1/16W
MF R768 NO_4XVCORE 6.3V 2 20%
6.3V 2
20%
6.3V 2 20%
R330 R319 100K 34 VCORE_FAST<1> 3
B1
SYM_VER-2
2 402
0 1
R769 CERM
805 CERM
805
CERM
805
6.3V 2
CERM
100K 100K 1% 5 7
5%
1/16W 0 805
5% 5% VCORE_SLOW<2>
A2 Y2 34 VCORE_VID<2>
1/16W 1/16W DP1 1/16W MF 5%
D 38 23 17 16 9 7 5 MAXBUS_SLEEP MF
402 2
MF
402 2 BAS16TW
SOT-363
MF
2 402
VCORE_SLOW<3>
34 VCORE_FAST<2> 6
11
B2
A3 Y3
9 34 VCORE_VID<3>
2 402 1/16W
MF
2 402
D
CPU_VCORE_PWR_SEQ 6 1 34 VCORE_FAST<3> 10
B3 C621 1 C6 1 C627 1 C32 1
NO STUFF VCORE_SLOW<4> 14 12 34 VCORE_VID<4>
A4 Y4 10UF 10UF 10UF 10UF
13
3
R730 34 VCORE_FAST<4>
B4 20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
0 CERM CERM CERM CERM
R3381 CPU_VCORE_SEQ_L 30 7
34
CPU_VCORE_HI_OC 1 2 VCORE_MUX_SEL 1
SEL PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD
805 805 805 805
10K
5%
1 Q6 5%
1/16W
VCORE_MUX_EN 15
OE CAP,AL CAP,AL,POLY,8.2UF,20,16V,V CASE,SMD CRITICAL TABLE_5_ITEM
1/16W 2N3904 MF 126S0036 7
MF 3
SM 402 4XVCORE NO STUFF NO STUFF 4XVCORE NO STUFF NO STUFF NO STUFF GND C412,C414,C415,C416,C417,C419,C420
402 2 2 1 1 1 1 1 1 1 1 4XVCORE
R732 R734 R736 R738 R260 R257 R255 R248 1
R739 8
+PBUS C607 1 C2 1 C8 1 C612 1
CPU_VCORE_SEQ 1 Q11 0 0 470K 470K 470K 0 470K 0 10UF 10UF 10UF 10UF
5% 5% 5% 5% 5% 5% 5% 5% 1K SEL = 0; Y1=A1 20% 20% 20% 20%
2N3904 1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
5%
1/16W SEL = 1; Y1=B1 6.3V 2 6.3V 2 6.3V 2 6.3V 2
SM CERM CERM CERM CERM
2 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 MF 805 805 805 805
<D4> <D3> <D2> <D1> <D4> <D3> <D2> <D1> 2 402 OMIT OMIT OMIT OMIT
1
C419 1
C420 1
C413 1
C415
+5V_MAIN 22UF 22UF 22UF 22UF
DP1 20%
2 20V
20%
2 20V
20%
2 20V
20%
2 20V KEEP TRACE FAT (40-100 MILS) C14 1 C112 1 C7 1 C624 1
BAS16TW TANT-D2
SMD
TANT-D2
SMD
TANT-D2
SMD
TANT-D2
SMD AND SHORT!! 10UF 10UF 10UF 10UF
SOT-363 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V
35 33 27 20 SLEEP_L_LS5 5 2 CERM 2 CERM 2 CERM 2 CERM 2
805 805 805 805
38 VCORE_VCC PLACE C423 CLOSE 1 OMIT OMIT OMIT
DP1 TO PINS 15 & 13!! D2 OMIT
1 1 1
BAS16TW
SM 1
C417 C412 C414 C416
SOT-363 R273 1 1 C471 MBR0530 22UF 22UF 22UF 22UF
DCDC_EN 4 3 20 1UF
20%
2 20%
2 20V
20%
2 20V
20%
2 20V
20%
2 20V C1 1 C5 1 C4 1 C620 1
39 33 32 29 20
5% TANT-D2 TANT-D2 TANT-D2 TANT-D2 10UF 10UF 10UF 10UF
2 10V
VCORE_BOOST
1/16W SMD SMD SMD SMD 20% 20% 20% 20%
MF CERM 6.3V 6.3V 6.3V 6.3V
603 CERM 2 CERM 2 CERM 2 CERM 2
402 2
805 805 805 805
C 38
5 6 7 8 5 6 7 8 C
+3V_MAIN R3291 C475 1 7 15 CRITICAL CRITICAL
R727 0 VCC VDD
0 R3171 5%
1/16W
1UF
20% Q41 Q40 CPU_VCORE_SLEEP 5 34 38 39
34 30 7 CPU_VCORE_HI_OC 1 2
27.4K MF 10V
CERM 2
U21 IRF7805 IRF7805 XW18
5%
1/16W
1%
1/16W
402 2
603 MAX1717 VCORE_VPLUS
4
SM 4
SM
SM
MF MF QSOP NO STUFF CRITICAL 1 2
402 2
402 VCORE_SHDN_L 2 SKP/SDN V+ 1
R346 1C436 L31 Keep trace fat and short!!
(VCORE_SNS) 5 FBS 2.2 0.0047uF 1 2 3 Keep trace fat and short!!
3
NO STUFF 38 BST 22 VCORE_BST 2 1 10% 1 2 3
10 25V
38 VCORE_ILIM ILIM DH 24
2 CERM
R694 5%
402
1
(VCORE_GNDSNS) 11 GNDS 1/16W
1
0 2 16
MF
15 INT_GPIO1_PU MAX1717_AB_SEL A/B 603
1.2UH-18.3A
5% NO STUFF CRITICAL 38 VCORE_DH
1 C488 5 6 7 8 5 6 7 8 5 6 7 8 SM1
1/16W
1 0.1UF
MF
402 R246 38 VCORE_REF 9 REF 20%
25V
2 CERM CRITICAL CRITICAL CRITICAL
0 CRITICAL CRITICAL CRITICAL CRITICAL
5% 603
1/16W
MF
38 VCORE_TON 8 TON LX 23 38 VCORE_LX Q45 Q46 Q44 1
C854 1
C697 1
C696 1
C695
2 402 4
IRF7822 4
IRF7822 4
IRF7822 CRITICAL 1000UF 1000UF 1000UF 1000UF
38 VCORE_CC 6 CC DL 14 38 VCORE_DL SM SM SM 2 20% 20% 20% 20%
2 2.5V 2 2.5V 2 2.5V
VCORE_VID<0>
<D0> MIN_LINE_WIDTH=10 21 D0 GND 13 VCORE_GND
R6521 D25 POLY
SM
POLY
SM
POLY
SM
2 2.5V
POLY
34 38
2.2 B540C SM
34 VCORE_VID<1> MIN_LINE_WIDTH=10 20 D1 XW7 1 2 3 1 2 3 1 2 3
5%
NO STUFF 1/4W 1
SM
CRITICAL
VCORE_VID<2> MIN_LINE_WIDTH=10 19 D2 FB 4 VCORE_FB
SM C735 1 MF CRITICAL CRITICAL
34
MIN_LINE_WIDTH=10 18
39 38
1 2 0.0047uF 1210 2
C694 1 C693 1 C692 1
34 VCORE_VID<3> D3 TIME 3 VCORE_TIME 38 10%
1000UF 1000UF 1000UF
34 VCORE_VID<4> MIN_LINE_WIDTH=10 17 D4 VGATE 12 VCORE_VGATE 15 38
R337 25V
CERM 2
CPU_VCORE_SNUB 20% 20%
2.5V 2 20%
1
100 2
402 2.5V 2
POLY POLY 2.5V 2
POLY
MAX1717 VID CAN TAKE 3.3V TO 5.5V INPUTS SM SM SM
1
R247 C497 1 R370 1
R318 1 1 C440 C489 1 5%
C731
0 0.01UF 66.5K 12.7K 1UF 220PF
5%
R3581 C493 1
1/16W
MF
0.0022uF
1
5% 20% 1% 1% 20% 25V 390K 0.001UF 402
1/16W 16V 1/16W 1/16W 2 10V CERM 2 5% NO STUFF 10%
50V
MF CERM 2 MF MF CERM 1/16W 20%
B 2 402
402 402 2 402 2 603 402
MF
402 2
50V
CERM 2 XW9
SM
CERM
603 2 XW2
SM B
402
VCORE_GNDA 1 2 1 2
VCORE_OFFSET Connect MAX1717 GND pin 13
1
R310 to GND at bottom-side FET Keep trace fat and short!!
OUTPUT VOLTAGE 162K
1%
1/16W R2 GROUND SENSE VOLTAGE DIVIDER PLACE THIS SHORT AT
PIN OF 1000uF CAP
MF
2 603 This allows for an offset to the ground sense to adjust the output voltage. CLOSEST TO CPU
VDAC VCORE_GNDDIV
VREF = 2.0V, HENCE VOFFSET = 2.0V * (R1/(R1+R2)) AND VCORE = VDAC + VOFFSET.
D3 D2 D1 D0 +20MV OFFSET 34 38
TABLE_11_HEAD
D4=0 D4=1 1
VCORE_OFFSET
R306
PART # QTY DEVICE PACKAGE DESCRIPTION
0
VALUE VOLT. WATT. TOL. REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_11_HEAD
116S1000 1 RES 0402 RES,MTL FILM,1/16W,0 OHM,5%,0402,SMD 1/16W 5% R306 VCORE_NO_OFFSET
2.00 1.275 0 0 0 0 2K
1% R1
1/16W NOTE: R310 (R2) NO STUFFED FOR NO OFFSET CASE
1.95 1.250 0 0 0 1 MF
2 402
1.90 1.225 0 0 1 0 38 34 VCORE_GNDSNS
1.85 1.200 0 0 1 1 FOR V-STEP: ROUTE AS DIFFERENTIAL PAIR
38 VCORE_SNS
1.80 1.175 0 1 0 0
A/B_ =
1.75 1.150 0 1 0 1
D<4..0> Hi/Fast Lo/Slow NO STUFF
1.70 1.125 0 1 1 0 <= 1K PU 1 0
R250
1.65 1.100 0 1 1 1 >= 100K PU
>= 100K PD
1
0
1
1 38 34 VCORE_GNDDIV 1
2.05K2 FMAX CONNECTOR
1.60 1.075 1 0 0 0 <= 1K PD 0 0
1%
NO STUFF
1/16W
A
1.55 1.050 1 0 0 1 MF
402
M-ST-SM-52465-1217
J6 VCORE SUPPLY
1.50 1.025 1 0 1 0 When A/B_ is high (fast): D4-D0 read as-is NO STUFF 1 12 VCORE_VID<0> 34
NOTICE OF PROPRIETARY PROPERTY
A
1.45 1.000 1 0 1 1 When A/B_ is low (slow): <=1K-ohm -> 0 R252 VCORE_GNDDIV_TEST 2 11 VCORE_VID<1> 34
100 3 10 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1.40 0.975 1 1 0 0 >=100K-ohm -> 1
38 34 VCORE_GNDSNS 1 2 VCORE_GNDSNS_TEST
4 9
VCORE_VID<2> 34
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
1% 30 +3V_PMU_RESET VCORE_VID<3> 34
1.35 0.950 1 1 0 1 1/16W
MF 30 23 22 SOFT_PWR_ON_L 5 8 VCORE_VID<4> 34
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
402
6 7 II NOT TO REPRODUCE OR COPY IT
1.30 0.925 1 1 1 0 If all pull-ups are >=100K and all NC (RFU)
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
NO CPU NO CPU 1 1 1 1 pull-downs are <=1K, V A = V B . SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 34 44
8 7 6 5 4 3 2 1
CR-35
8 7 6 5 4 3 2 1
+1_5V_SLEEP LOADS
1) L3 I/O
+1_5V_MAIN
R1606
0
1) AGP I/O - IF USING D3COLD
1) MAXBUS I/O - IF 1.5V INTERFACE
+1_5V_SLEEP
1.5V/2.5V SWITCHER
1 2 +1_5V_SLEEP_VIN
5%
1/16W
MF Q37 +1_5V_MAIN LOADS +5V_MAIN +2_5V_SLEEP LOADS
603 SI3446DV 1) L3 CORE
NO STUFF 1 TSOP 1) INTREPID CORE 2) FBCORE/FBIO IF USING D3COLD
38 19 16 +1_5V_LDO 2) AGP I/O IF USING D3HOT 3) L3 I/O IF L3_OVDD EXCEEDS 1.5V
R1607 2
D 1
0 2
5 THERE’S 100K PULL-UP ON PG 31 ALREADY
+2_5V_MAIN LOADS
4) INTREPID MEMORY I/O
D
6 3 SLEEP_L_LS5 20 27 33 34
5%
BAS16TW
1/16W
R385 1 R399
2
1) MAP17 - FBCORE/FBIO IF USING D3HOT
SOT-363
MF 4 20
DP2
603 100K 2 1 38 MAX1715_VCC 2) GIGABIT ETHERNET - AVDDL
+2_5V_MAIN +2_5V_SLEEP
5%
C683 1 1 C689 1/16W
MF
5% 3) DDR SODIMMS - CORE/IO
10UF 2200pF 1/16W 1 C554
5
20%
6.3V 2
5%
50V
402 2 NO STUFF MF
402
1 C544 2.2UF
4) DDR MUXES R231 4
CERM 2 CERM 1 2.2UF 20% 5) CLOCK SLEWING I/O
100K 2
805 603
3V_5V_OK
R351 20% 10V
2 CERM
35 33 30 23 SLEEP 1
3 6
33 0 2 10V 6) PCI1510 CORE 5%
DP2 5%
1/16W
CERM
805
NO STUFF 805 1/16W
MF
5
BAS16TW MF 1
R349 402 2
SOT-363
2 402 0 TSOP 1
6 1
3 5%
1/16W
C401 1 SI3447DV
10UF
BAS16TW
D
Q13 38 MAX1715_TON MF 20% U9
3
2 402
SOT-363
6.3V 2
DP2
R373 2N7002 CERM
805
330K 2 1
SM
33 20 DCDC_EN_L 1 MAX1715_ON_RC G S
38 2_5V_ILIM 38 1_5V_ILIM +PBUS C396
4
5%
1/16W
MF
1 C499 2 2200pF
1 1
402 0.01UF R348 R353 +PBUS 2_5V_SLEEP_PWREN_L 1 2
20% 158K 158K
DIODE PROVIDE PROVIDE QUICK SHUT-DOWN 2 16V
CERM 1% 1% 5%
POWER DOWN DELAY 1.5MS TO 3.5MS 402 1/16W 1/16W 50V
MF MF 21 20 CERM
402 2 2 402 603
VCC VDD
+PBUS
MAX1715_GND 35 38
U23 MAX1715_SKIP 38
CRITICAL CRITICAL
MAX1715
QSOP 1 C520 1 C538
3 ILIM1 V+ 4 +2_5V_MAIN 4.7UF 4.7UF
CRITICAL CRITICAL 20% 20%
12 ILIM2 NC_15 15 NC 25V
2 CERM 25V
2 CERM
C511 1 C491 1
10 ON1 NC_23 23 NC 1206 1206
4.7UF 4.7UF
C 20%
25V
CERM 2
20%
25V
CERM 2
R408
4.7
11 ON2 NC_28 28 NC R398
4.7
C
1206 1206 38 1_5V_BOOST 1 2 38 1_5V_BST 25 BST1 BST2 18 38 2_5V_BST 1 2 38 2_5V_BOOST
5% 5%
1/16W
MF
26 DH1 CRITICAL DH2 17 1/16W
MF
8 7 6 5 1 C537 603
27 LX1 LX2 16
603
1 C536
5 6 7 8
0.1UF
CRITICAL 20% 0.1UF CRITICAL
25V
2 CERM
24 DL1 DL2 19 20%
25V
Q48 603 +1_5V_MAIN 5 TON PGND 22 MAX1715_GND
2 CERM
603
Q59
+1_5V_MAIN IRF7805 IRF7805
4 38 1_5V_DH 38 2_5V_DH 4 +2_5V_MAIN
SM 1 SM
CRITICAL OUT1 OUT2 14 CRITICAL
1_5V_2_5V_OK 7 PGOOD
L30 38 20
MAX1715_REF 9 REF SKIP 6 L38
4.7UH 3 2 1
38
1 2 3 4.7UH
1 2 2 FB2 13
38 1_5V_LX 35
38
1_5V_FB FB1 38 2_5V_LX 1 2
SM4 SM4
1 NO STUFF AGND THRML
R355 R3521
8 29
5.11K 8 7 6 5 5 6 7 8
1% 0 1
POSCAPS POSCAPS
1/16W
MF
CRITICAL 5%
1/16W
R350 CRITICAL POSCAPS POSCAPS POSCAPS
1 C704 1 1 2 402
Q47 MF
402 2 5%
0
Q58 1 C776 1
C747
1
C744 1
C753
C715 C708 1_5V_FB 35 38 1/16W
2
10UF 150UF 150UF 150UF
10UF
20%
150UF
20%
150UF
20% 2
IRF7811W
SO-8
4 38 1_5V_DL
MF
2 402
38 2_5V_DL 4
IRF7811W
SO-8
D32
SM
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
6.3V CERM TANT
2 CERM
805
2 6.3V
TANT
2 6.3V
TANT
1
R354 D23
SM
1 C476 MBRS130LT3 805
TANT
SMD-1 SMD-1 TANT
SMD-1
SMD-1 SMD-1 10K 1UF 1
1% MBRS130LT3 3 2 1 OMIT 20% 1 2 3
1/16W 1 10V
MF
2 402
XW8
SM
2 CERM
603
1 238 35 MAX1715_GND
B CHANGE R354 BACK TO 10K, 1%, AND STUFF 5.11K FOR 1.5V OPERATION B
CONNECTING 1_5V_FB TO GND, FORCES 1.8V OUTPUT
+1_8V_MAIN +1_8V_SLEEP
+1_8V_MAIN LOADS
+3V_MAIN
1.8V SWITCHER 1) INTREPID PLLS
2) +1_5V_LDO
35 33 30 23 SLEEP 1
R143
100K 2
4
3 6
5
5%
+1_8V_MAIN 1/16W
CRITICAL MF
402
2 +1_8V_SLEEP LOADS
1
L14 C256 1 TSOP 1) MPC7450 - MAXBUS I/O - IF 1.8V INTERFACE
2.2UH 10UF SI3447DV
R40 20%
6.3V 2 U5
2) CPU JTAG & MaxBus Pull-ups
C86 1
1
10 2 38 1_8V_SW 1 2 CERM 3) CPU PLL Config Straps
38 LTC3411_VCC 805
10UF SM1 4) L3_OVDD (IF NOT USING 1.5V)
20%
6.3V NO STUFF
5%
1/16W C214
CERM 2
805 1
1
R552 MF
402
7 6
C613 1 R5461 2200pF
R67 1M SVIN PVIN 10PF 887K 1_8V_SLEEP_PWREN_L 2 1
1%
5%
10K 5%
1/16W U4 5%
50V 1/16W
1/16W MF LTC3411 CERM 2 MF
402 2
5%
50V
MF 2 402 MSOP 402 CERM
BURST MODE 2 402 38 LTC3411_SHDN 1 SHDN/RT SW 4 603
CRITICAL
38 LTC3411_SYNC 2 SYNC/MODE VFB 9 38 1_8V_VFB
8 PGOOD ITH 10 38 LTC3411_ITH
PGND SGND 1
R545 1 C610
NO STUFF CONTINOUS MODE
5 3
16.2K
1%
22UF
20% 1.5V/1.8V/2.5V SUPPLIES
A PULSE MODE 1
R75
1
R553 C15 1 1
R57
1/16W
MF
2 402
R5511
698K
10V
2 CERM
1210
NOTICE OF PROPRIETARY PROPERTY
A
10K 1M 1UF 324K 1%
5% 5% 20% 1% LTC3411_ITH_RC 38 1/16W
1/16W 1/16W 10V 1/16W
MF MF CERM 2 MF MF
402 2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
603
2 402 2 402 2 402 1 C619 AGREES TO THE FOLLOWING
1000PF OMIT I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5%
25V II NOT TO REPRODUCE OR COPY IT
2 CERM
603 XW1
SM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
38 LTC3411_GND 1 2 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 35 44
8 7 6 5 4 3 2 1
CR-36
8 7 6 5 4 3 2 1
GROUP SIG_NAME DELAY_RULE MAX_VIAS MAX_EXPOSED_LENGTH STUB_LENGTH NET_SPACING_TYPE NO_TEST PULSE_PARAM GROUP SIG_NAME DELAY_RULE MATCHED_DELAY MAX VIAS MAX EXPOSED LENGTH STUB_LENGTH NET_SPACING_TYPE PULSE PARAM
CPU_AACK_L ::1500:2500 5 250 10 MIL SPACING 5 9
INTREPID SYSCLK_CPU_UF :::150 10 MIL SPACING 167 MHZ 9
CPU_ADDR<0..31> ::1500:3100 5 250 83 MHZ SYSCLK_CPU ::2650:2750 3 250 200 10 MIL SPACING 167 MHZ
MAXBUS CPU_ARTRY_L ::1500:2500 5 250 10 MIL SPACING
5 9
5 9
CLOCKS INT_CPUFB_OUT :::150 3 250 10 MIL SPACING 167 MHZ
5 9
CPU_BG_L ::1500:2500 5 250 10 MIL SPACING 5 9 INT_CPUFB_OUT_SHORT ::700:850 3 250 10 MIL SPACING 167 MHZ 9
CPU_BR_L ::1500:2500 5 250 10 MIL SPACING 5 9 INT_CPUFB_OUT_NORM ::500:600 3 250 10 MIL SPACING 167 MHZ 9
CPU_CI_L ::1500:2700 5 250 5 9 INT_CPUFB_IN_NORM ::500:600 3 250 10 MIL SPACING 167 MHZ 9
CPU_DATA<0..31> ::1100:2500 5 250 83 MHZ 6 9 INT_CPUFB_LONG ::1050:1150 3 250 10 MIL SPACING 167 MHZ 9
CPU_DATA<32..63> ::1100:2500 5 250 83 MHZ 6 9 INT_CPUFB_IN ::700:800 3 250 200 10 MIL SPACING 167 MHZ 9
CPU_DBG_L ::1500:2500 5 250 10 MIL SPACING 5 9 SYSCLK_DDRCLK_A0_UF ::475:575 3 250 200 10 MIL SPACING 167 MHZ
CLOCK LINE CONSTRAINTS
10
D
CPU_DTI<0..2>
CPU_DRDY_L_UF
::1500:2950
:::500
5 250
250 10 MIL SPACING
5 9
5
SYSCLK_DDRCLK_A0_L_UF
SYSCLK_DDRCLK_A1_UF
::475:575
::300:400
3
3
250
250
200
200
10 MIL SPACING
10 MIL SPACING
167 MHZ
167 MHZ
10
10
D
CPU_DRDY_L ::1500:2500 5 250 10 MIL SPACING 5 9 SYSCLK_DDRCLK_A1_L_UF ::300:400 3 250 200 10 MIL SPACING 167 MHZ
DIGITAL SIGNALS
10
CPU_GBL_L ::1500:2500 5 250 5 9 SYSCLK_DDRCLK_B0_UF ::430:530 3 250 200 10 MIL SPACING 167 MHZ 10
CPU_HIT_L ::1500:2800 5 250 10 MIL SPACING 5 9 SYSCLK_DDRCLK_B0_L_UF ::430:530 3 250 200 10 MIL SPACING 167 MHZ 10
CPU_QACK_L ::1500:2500 5 250 10 MIL SPACING 5 9 SYSCLK_DDRCLK_B1_UF ::400:510 3 250 200 10 MIL SPACING 167 MHZ 10
CPU_QREQ_L ::1500:2600 5 250 10 MIL SPACING 5 9 SYSCLK_DDRCLK_B1_L_UF ::400:510 3 250 200 10 MIL SPACING 167 MHZ 10
CPU_TA_L ::1500:2500 5 250 10 MIL SPACING 5 9 SYSCLK_DDRCLK_A0 ::1850:1950 DDRCLK_A0 SYSCLK_DDRCLK_A0:::25 3 250 200 10 MIL SPACING 167 MHZ 10 12
CPU_TBST_L ::1500:2600 5 250 10 MIL SPACING 5 9 SYSCLK_DDRCLK_A0_L ::1850:1950 DDRCLK_A0 SYSCLK_DDRCLK_A0:::25 3 250 200 10 MIL SPACING 167 MHZ 10 12
CPU_TEA_L ::1500:3000 5 250 5 9 SYSCLK_DDRCLK_A1 ::1925:2025 DDRCLK_A1 SYSCLK_DDRCLK_A1:::25 3 250 200 10 MIL SPACING 167 MHZ 10 12
CPU_TS_L ::1500:2500 5 250 10 MIL SPACING 5 9 SYSCLK_DDRCLK_A1_L ::1925:2025 DDRCLK_A1 SYSCLK_DDRCLK_A1:::25 3 250 200 10 MIL SPACING 167 MHZ 10 12
CPU_TSIZ<0..2> ::1500:3500 5 250 5 9 SYSCLK_DDRCLK_B0 ::2375:2475 DDRCLK_B0 SYSCLK_DDRCLK_B0:::25 3 250 200 10 MIL SPACING 167 MHZ 10 12
CPU_TT<0..4> ::1500:3400 5 250 5 9 SYSCLK_DDRCLK_B0_L ::2375:2475 DDRCLK_B0 SYSCLK_DDRCLK_B0:::25 3 250 200 10 MIL SPACING 167 MHZ 10 12
CPU_WT_L ::1500:3100 5 250 5 9 SYSCLK_DDRCLK_B1 ::2450:2550 DDRCLK_B1 SYSCLK_DDRCLK_B1:::25 3 250 200 10 MIL SPACING 167 MHZ 10 12
SYSCLK_DDRCLK_B1_L ::2450:2550 DDRCLK_B1 SYSCLK_DDRCLK_B1:::25 3 250 200 10 MIL SPACING 167 MHZ 10 12
L3_DATA<31..0>
L3 ::750:1250 4 200 6 8
L3_DATA<63..32>
CACHE ::750:1250 4 200 6 8 INT_REF_CLK_OUT ::1250:1400 3 250 200 10 MIL SPACING 49.92 MHZ 15
L3_CNTL<1..0> ::1200:1800 4 200 6 8 INT_REF_CLK_IN ::1900:2000 4 250 200 10 MIL SPACING 167 MHZ 15
L3_ADDR<17..0> ::1200:1800 4 200 6 8 CLK66M_GPU_AGP_UF :::150 200 10 MIL SPACING 66 MHz 13
CLK66M_GPU_AGP ::1400:1500 4 400 200 10 MIL SPACING 66 MHz 13 19
MEM_DATA<7..0>
GROUP 0 :::1600 4 200 167 MHZ 10 11
INT_AGP_FB_OUT :::150 200 10 MIL SPACING 66 MHz 13
RAM_DATA_A<7..0> :::1550 4 RAM_GROUP0_A:::450 200 167 MHZ 11 12
INT_AGP_FB_IN ::1400:1500 4 500 200 10 MIL SPACING 66 MHz 13
RAM_DATA_B<7..0> :::2150 4 RAM_GROUP0_B:::600 200 167 MHZ 11 12
TOTAL LENGTH CONTROLLED BY SPREADSHEET CLK33M_CBUS_UF :::250 200 10 MIL SPACING 33 MHz 13
MEM_DQS<0> :::1600 4 200 167 MHZ 10 11
CLK33M_CBUS ::5000:6000 SHOULD BE AT MOST 4 VIAS FOR CLK 6 500 200 10 MIL SPACING 33 MHz 13 18
RAM_DQS_A<0> :::1550 4 RAM_GROUP0_A:::450 200 167 MHZ 11 12
CLK33M_AIRPORT_UF :::250 200 10 MIL SPACING 33 MHz 13
RAM_DQS_B<0> :::2150 4 RAM_GROUP0_B:::600 200 167 MHZ 11 12
CLK33M_AIRPORT ::11000:12000 SHOULD BE AT MOST 4 VIAS FOR CLK 6 500 200 10 MIL SPACING 33 MHz 13 24 39
MEM_DQM<0> :::1600 4 200 167 MHZ 10 11
CLK33M_USB2_UF :::250 200 10 MIL SPACING 33 MHz 13
RAM_DQM_A<0> :::1550 4 RAM_GROUP0_A:::450 200 167 MHZ
C RAM_DQM_B<0> :::2150 4 RAM_GROUP0_B:::600 200 167 MHZ
11 12
11 12
CLK33M_USB2
INT_PCI_FB_OUT
::4000:6000
:::300
SHOULD BE AT MOST 4 VIAS FOR CLK 6 500 200
200
10 MIL SPACING
10 MIL SPACING
33 MHz
33 MHz
13 26
13
C
MEM_DATA<15..8>
GROUP 1 :::1500 4 200 167 MHZ 10 11
INT_PCI_FB_IN ::6500:7500 3 500 200 10 MIL SPACING 33 MHz 13
RAM_DATA_A<15..8> :::1550 4 RAM_GROUP1_A:::700 200 167 MHZ 11 12
RAM_DATA_B<15..8> :::2100 4 RAM_GROUP1_B:::700 200 167 MHZ 11 12 L3_CLK<0>
TOTAL LENGTH CONTROLLED BY SPREADSHEET ::900:1100 3 250 200 10 MIL SPACING 250 MHZ 6 8
MEM_DQS<1> :::1500 4 200 167 MHZ 10 11
L3 CACHE L3_ECHO_CLK<0..1> ::900:1100 3 250 200 10 MIL SPACING 250 MHZ 6 8
RAM_DQS_A<1> :::1550 4 RAM_GROUP1_A:::700 200 167 MHZ 11 12 L3_CLK<1> ::900:1100 3 250 200 10 MIL SPACING 250 MHZ 6 8
RAM_DQS_B<1> :::2100 4 RAM_GROUP1_B:::700 200 167 MHZ 11 12 L3_ECHO_CLK<2..3> ::900:1100 3 250 200 10 MIL SPACING 250 MHZ 6 8
MEM_DQM<1> :::1500 4 200 167 MHZ 10 11
RAM_DQM_A<1> GPU_CLK27M_OUT :::400 3 200 10 MIL SPACING 21
:::1550 4 RAM_GROUP1_A:::700 200 167 MHZ
RAM_DQM_B<1> :::2100 4 RAM_GROUP1_B:::700 200 167 MHZ
11 12
11 12
MAP17 GPU_CLK27M_UF :::250 3 200 10 MIL SPACING 21
MEM_DATA<31..16> GPU_SSCLK_UF :::200 200 10 MIL SPACING 21
GROUP 2/3 :::1650 4 200 167 MHZ 10 11
GPU_SSCLK_IN :::920 3 500 200 10 MIL SPACING 21
RAM_DATA_A<31..16> :::1700 4 RAM_GROUP23_A:::850 200 167 MHZ 11 12
RAM_DATA_B<31..16> GPU_FBCLK0 :::250 3 200 10 MIL SPACING 19
:::2200 4 RAM_GROUP23_B:::850 200 167 MHZ 11 12
TOTAL LENGTH CONTROLLED BY SPREADSHEET GPU_FBCLK0_L :::250 3 200 10 MIL SPACING 19
MEM_DQS<3..2> :::1650 4 200 167 MHZ 10 11
RAM_DQS_A<3..2> GPU_FBCLK1 :::250 3 200 10 MIL SPACING 19
:::1700 4 RAM_GROUP23_A:::850 200 167 MHZ 11 12
GPU_FBCLK1_L
DDR RAM_DQS_B<3..2> :::2200 4 RAM_GROUP23_B:::850 200 167 MHZ 11 12
:::250 3 200 10 MIL SPACING 19
GPU_DVO_CLKP
RAM MEM_DQM<3..2> :::1650 4 200 167 MHZ 10 11
::600:1300 3 250 200 10 MIL SPACING 21
RAM_DQM_A<3..2> :::1700 4 RAM_GROUP23_A:::850 200 167 MHZ
RAM_DQM_B<3..2> :::2200 4 RAM_GROUP23_B:::850 200 167 MHZ
11 12
11 12
CRYSTALS CLK27M_GPU_XOUT :::150 10 MIL SPACING 21
CLK27M_XTAL_IN :::250 10 MIL SPACING 21
MEM_DATA<47..32>
GROUP 4/5 :::1500 4 200 167 MHZ 10 11
CLK27M_GPU_XIN ::300:400 10 MIL SPACING 21
RAM_DATA_A<47..32> :::1850 4 RAM_GROUP45_A:::900 200 167 MHZ 11 12
CLK18M_INT_XIN ::1400:1500 10 MIL SPACING 15
RAM_DATA_B<47..32> :::2350 4 RAM_GROUP45_B:::950 200 167 MHZ 11 12
TOTAL LENGTH CONTROLLED BY SPREADSHEET CLK18M_INT_XOUT ::1300:1400 10 MIL SPACING 15
MEM_DQS<5..4> :::1500 4 200 167 MHZ 10 11
CLK18M_XTAL_IN :::300 10 MIL SPACING 15
RAM_DQS_A<5..4> :::1850 4 RAM_GROUP45_A:::900 200 167 MHZ 11 12
CLK18M_INT_EXT :::400 10 MIL SPACING 15
RAM_DQS_B<5..4> :::2350 4 RAM_GROUP45_B:::950 200 167 MHZ 11 12
CLK25M_ENET_XIN :::650 10 MIL SPACING 27
MEM_DQM<5..4> :::1500 4 200 167 MHZ 10 11
B RAM_DQM_A<5..4>
RAM_DQM_B<5..4>
:::1850
:::2350
4
4
RAM_GROUP45_A:::900
RAM_GROUP45_B:::950
200
200
167 MHZ
167 MHZ
11 12
11 12
CLK25M_ENET_XOUT
NEC_XT1
:::400
::600:700
10 MIL SPACING
10 MIL SPACING
27
26
B
NEC_XT2 ::300:400 THERE’S ANOTHER 280MIL LEG 10 MIL SPACING 26
MEM_DATA<55..48>
GROUP 6 :::1650 4 200 167 MHZ 10 11
RAM_DATA_A<55..48> :::1800 4 RAM_GROUP6_A:::800 200 167 MHZ 11 12 SND_SCLK 5 500 200 10 MIL SPACING 15 25 39
RAM_DATA_B<55..48> :::2400 4 RAM_GROUP6_B:::800 200
TOTAL LENGTH CONTROLLED BY SPREADSHEET
167 MHZ 11 12 SOUND SND_CLKOUT 5 500 200 10 MIL SPACING 15 25 39
MEM_DQS<6> :::1650 4 200 167 MHZ 10 11
RAM_DQS_A<6> CLKENET_PHY_RX :::300 200 125 MHZ 27
:::1800 4 RAM_GROUP6_A:::800 200 167 MHZ 11 12
RAM_DQS_B<6> :::2400 4 RAM_GROUP6_B:::800 200 167 MHZ 11 12
ETHERNET CLKENET_LINK_RX ::8000:9000 3 500 200 10 MIL SPACING 125 MHz 14 27
MEM_DQM<6> :::1650 4 200 167 MHZ 10 11
MARVELL CLKENET_PHY_GBE_REF :::300 200 125 MHz 27
RAM_DQM_A<6> CLKENET_LINK_GBE_REF ::8000:9000 3 500 200 10 MIL SPACING 125 MHz 14 27
:::1800 4 RAM_GROUP6_A:::800 200 167 MHZ 11 12
RAM_DQM_B<6> CLKENET_PHY_TX :::300 200 25 MHz 27
:::2400 4 RAM_GROUP6_B:::800 200 167 MHZ 11 12
MEM_DATA<63..56> CLKENET_LINK_TX ::8000:9000 4 500 200 10 MIL SPACING 25 MHz 14 27
GROUP 7 :::1600 4 200 167 MHZ 10 11
CLKENET_LINK_GTX :::300 200 125 MHz 14
RAM_DATA_A<63..56> :::1600 4 RAM_GROUP7_A:::500 200 167 MHZ 11 12
RAM_DATA_B<63..56> CLKENET_PHY_GTX ::8000:9000 3 500 200 10 MIL SPACING 125 MHz 14 27
:::2200 4 RAM_GROUP7_B:::500 200 167 MHZ 11 12
TOTAL LENGTH CONTROLLED BY SPREADSHEET
MEM_DQS<7> :::1600 4 200 167 MHZ 10 11
CLKFW_PHY_PCLK :::300 200 49.152 MHz 28
RAM_DQS_A<7> :::1600 4 RAM_GROUP7_A:::500 200 167 MHZ 11 12
FIREWIRE CLKFW_LINK_PCLK ::7500:8000 3 500 200 10 MIL SPACING 49.152 MHz 14 28
RAM_DQS_B<7> :::2200 4 RAM_GROUP7_B:::500 200 167 MHZ 11 12
MEM_DQM<7> CLKFW_PHY_LCLK ::7500:8000 3 500 200 10 MIL SPACING 49.152 MHz 14 28
:::1600 4 200 167 MHZ 10 11
RAM_DQM_A<7> CLKFW_LINK_LCLK :::300 200 49.152 MHz 14
:::1600 4 RAM_GROUP7_A:::500 200 167 MHZ 11 12
RAM_DQM_B<7> FW_XI :::520 200 10 MIL SPACING 98.034 MHZ 28
:::2200 4 RAM_GROUP7_B:::500 200 167 MHZ 11 12
MEM_ADDR<12..0> FW_OSC :::300 200 10 MIL SPACING 98.034 MHZ 28
ADDR :::500 4 83 MHZ 10
RAM_ADDR<12..0> ::2000:3000 6 200 10 12
MEM_BA<1..0> :::500 4 10
RAM_BA<1..0> ::2000:3300 6 200 10 12
MEM_CS_L<3..0> :::500 4 10
CONTROL RAM_CS_L<3..0> ::1800:2500 6 200 10 12
SIGNAL CONSTRAINTS - PAGE 1
A MEM_CKE<3..0> :::500 4 10
NOTICE OF PROPRIETARY PROPERTY
A
RAM_CKE<3..0> ::1800:2500 6 200 10 12
MEM_RAS_L :::500 4 10
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
RAM_RAS_L ::2000:4100 6 200 10 12
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
MEM_CAS_L :::500 4 10
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
RAM_CAS_L ::2000:4100 6 200 10 12
II NOT TO REPRODUCE OR COPY IT
MEM_WE_L :::500 4 10
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
RAM_WE_L ::2000:3100 6 200 10 12
MEM_MUXSEL_H<1..0> :::500 3 10 11
SIZE DRAWING NUMBER REV.
MEM_MUXSEL_L<1..0> :::500 3 10 11
D 051-6469 F
RAM_MUXSEL_H ::1800:2600 5 11 APPLE COMPUTER INC.
RAM_MUXSEL_L SCALE SHT OF
::1800:2600 5 11
NONE 36 44
8 7 6 5 4 3 2 1
CR-37
8 7 6 5 4 3 2 1
GROUP SIG_NAME DELAY_RULE MAX_VIAS MAX_EXPOSED_LENGTH STUB_LENGTH NET_SPACING_TYPE NO_TEST PULSE_PARAM Differential Signals
GROUP SIG_NAME DIFFERENTIAL_PAIR MATCHED_DELAY MAX_EXPOSED_LENGTH NET_SPACING_TYPE MAX_VIAS
AGP_AD<15..0>
AGP ::1350:1650 5 100 66 MHz 13 19
MDI_M<0> ENET_MDI0 ENET_MDI0:U49.31:T1.11:100 27
AGP_CBE<1..0> ::1350:1650 5 100 66 MHz 13 19 ETHERNET
AGP BYTES 0-1
MDI_P<0> ENET_MDI0 ENET_MDI0:U49.29:T1.12:100 27
Digital Signals (cont’d)
AGP_AD_STB<0> ::1500:1600 4 100 250 8 MIL SPACING 133 MHZ 13 19
MDI_M<1> ENET_MDI1 ENET_MDI1:U49.34:T1.8:100 SPACING DELETED BECAUSE 27
AGP_AD_STB_L<0> ::1500:1600 4 100 250 8 MIL SPACING 133 MHZ 13 19
MDI_P<1> ENET_MDI1 ENET_MDI1:U49.33:T1.9:100 OF PHYSICAL CONSTRAINTS 27
AGP BYTES 2-3 AGP_AD<31..16> ::1350:1650 5 100 66 MHz 13 19
MDI_M<2> ENET_MDI2 ENET_MDI2:U49.41:T1.5:100 AROUND MARVELL PHY 27
AGP_CBE<3..2> ::1350:1680 5 100 66 MHz 13 19
AGP_AD_STB<1> MDI_P<2> ENET_MDI2 ENET_MDI2:U49.39:T1.6:100 27
::1500:1600 4 100 250 8 MIL SPACING 133 MHZ 13 19
AGP_AD_STB_L<1> MDI_M<3> ENET_MDI3 ENET_MDI3:U49.43:T1.2:100 27
::1500:1600 4 100 250 8 MIL SPACING 133 MHZ 13 19
AGP_SBA<7..0> MDI_P<3> ENET_MDI3 ENET_MDI3:U49.42:T1.3:100 27
AGP SIDEBAND ::1100:1700 5 100 66 MHz 13 19
RJ45_DN<0> RJ45_DP0 RJ45_DP0:T1.14:J18.2:100 10 MIL SPACING 27 39
D
AGP_SB_STB
AGP_SB_STB_L
::1500:1700
::1500:1700
4
4
100
100
350
350
8 MIL SPACING
8 MIL SPACING
66 MHz
66 MHz
13 19
13 19
RJ45_DP<0> RJ45_DP0 RJ45_DP0:T1.13:J18.1:100 10 MIL SPACING 27 39 D
AGP_FRAME_L RJ45_DN<1> RJ45_DP1 RJ45_DP1:T1.17:J18.6:100 10 MIL SPACING 27 39
AGP CONTROL ::1200:1900 6 250 66 MHz 13 19
AGP_IRDY_L RJ45_DP<1> RJ45_DP1 RJ45_DP1:T1.16:J18.3:100 10 MIL SPACING 27 39
::1200:1900 6 250 66 MHz 13 19
AGP_TRDY_L RJ45_DN<2> RJ45_DP2 RJ45_DP2:T1.20:J18.5:100 10 MIL SPACING 27 39
::1200:1900 6 250 66 MHz 13 19
AGP_DEVSEL_L RJ45_DP<2> RJ45_DP2 RJ45_DP2:T1.19:J18.4:100 10 MIL SPACING 27 39
::1200:1900 6 250 66 MHz 13 19
AGP_STOP_L RJ45_DN<3> RJ45_DP3 RJ45_DP3:T1.23:J18.8:100 10 MIL SPACING 27 39
::1200:1900 6 250 66 MHz 13 19
AGP_PAR RJ45_DP<3> RJ45_DP3 RJ45_DP3:T1.22:J18.7:100 10 MIL SPACING 27 39
::1200:1900 6 250 66 MHz
AGP_REQ_L ::1200:1900 6 250 66 MHz
13 19
13 19 FIREWIRE
FW_TPA0N FW_TPA0 FW_TPA0:::4%
MIN_LINE_WIDTH=3.4
10 MIL SPACING 28 29
INTERNAL LAYER
MIN_LINE_WIDTH=3.4
AGP_GNT_L FW_TPA0P FW_TPA0 FW_TPA0:::4% 10 MIL SPACING 28 29
::1200:1900 6 250 66 MHz 13 19
FW_TPB0N FW_TPB0 FW_TPB0:::4%
MIN_LINE_WIDTH=3.4
10 MIL SPACING 28 29
ER = 4.3 (DIELECTRIC CONSTANT)
AGP_RBF_L ::1200:1900 6 250 66 MHz 13 19
MIN_LINE_WIDTH=3.4
DVO GPU_DVOD<0..11> ::600:1300 5 250 21
FW_TPB0P FW_TPB0 FW_TPB0:::4% 10 MIL SPACING
MIN_LINE_WIDTH=3.4
28 29 W = 4MIL (TRACE WIDTH)
GPU_DVO_HSYNC FW_TPI0N FW_TPI0 FW_TPI0:::4% 10 MIL SPACING
::600:1300 5 250 21
FW_TPI0P FW_TPI0 FW_TPI0:::4%
MIN_LINE_WIDTH=3.4
10 MIL SPACING
B = 12.2MIL (DIST BETW 2 GND PLANES)
GPU_DVO_VSYNC ::600:1300 5 250 21
MIN_LINE_WIDTH=3.4
FW_TPO0N FW_TPO0 FW_TPO0:::4% 10 MIL SPACING
MIN_LINE_WIDTH=3.4 T = 0.7MIL (TRACE THICKNESS)
PCI_AD<31..0> ::8000:13500 MIN_DAISY_CHAIN 33 MHz 10 13 18 24 26 39 FW_TPO0P FW_TPO0 FW_TPO0:::4% 10 MIL SPACING
PCI PCI_CBE<3..0> ::8000:13500 MIN_DAISY_CHAIN 33 MHz 13 18 24 26 39 FW_TPA1N FW_TPA1 FW_TPA1:::4% 500
MIN_LINE_WIDTH=3.4
10 MIL SPACING 28 29
S = 10MIL (SEPERATION OF DIFF TRACES)
MIN_LINE_WIDTH=3.4
PCI_FRAME_L FW_TPA1P
::8000:13500 MIN_DAISY_CHAIN 33 MHz 13 18 24 26 39 FW_TPA1 FW_TPA1:::4% 500 10 MIL SPACING
MIN_LINE_WIDTH=3.4
28 29
ZSINGLE = 51.57OHM
PCI_IRDY_L ::8000:13500 MIN_DAISY_CHAIN 33 MHz 13 18 24 26 39 FW_TPB1N FW_TPB1 FW_TPB1:::4% 500 10 MIL SPACING 28 29
PCI_TRDY_L ::8000:13500 MIN_DAISY_CHAIN 33 MHz 13 18 24 26 39 FW_TPB1P FW_TPB1 FW_TPB1:::4% 500
MIN_LINE_WIDTH=3.4
10 MIL SPACING 28 29
ZDIFF = 99.8OHM
MIN_LINE_WIDTH=3.4
PCI_DEVSEL_L ::8000:13500 MIN_DAISY_CHAIN 33 MHz 13 18 24 26 39 FW_TPI1N FW_TPI1 FW_TPI1:::4% 10 MIL SPACING 29 39
MIN_LINE_WIDTH=3.4
PCI_STOP_L ::8000:13500 MIN_DAISY_CHAIN 33 MHz 13 18 24 26 39 FW_TPI1P FW_TPI1 FW_TPI1:::4% 10 MIL SPACING 29 39
MIN_LINE_WIDTH=3.4
PCI_PAR ::8000:13500 MIN_DAISY_CHAIN 33 MHz 13 18 24 26 39 FW_TPO1N FW_TPO1 FW_TPO1:::4% 10 MIL SPACING 29 39
MIN_LINE_WIDTH=3.4
FW_TPO1P FW_TPO1 FW_TPO1:::4% 10 MIL SPACING 29 39
ULTRA ATA-100 UIDE_DATA<15..8> :::710 200
NEED TO MATCH DELAY TO 250
100 MHZ 14 24 CLKLVDS_LN CLKLVDS_L LVDS:::110 500 10 MIL SPACING 4 20 22 39
FOR FIREWIRE
UIDE_DATA<7> U44.V1:RP9.4::600 200 100 MHZ 14 24
LVDS CLKLVDS_LP CLKLVDS_L LVDS:::110 500 10 MIL SPACING 4 20 22 39
UIDE_DATA<6..0> :::600 200 100 MHZ 14 24
LOWER
LVDS_L0N LVDS_L0 LVDS:::110 10 MIL SPACING 20 22 39
ER = 4.3 (DIELECTRIC CONSTANT)
UIDE_ADDR<2..0> :::650 200 100 MHZ W = 3.4MIL (TRACE WIDTH)
C UIDE_RST_L :::400 200 100 MHZ
14 24
14 24
LVDS_L0P
LVDS_L1N
LVDS_L0
LVDS_L1
LVDS:::110
LVDS:::110
10 MIL SPACING
10 MIL SPACING
20 22 39
20 22 39
B = 12.2MIL (DIST BETW 2 GND PLANES)
C
UIDE_DIOW_L :::400 200 100 MHZ 14 24 LVDS_L1P LVDS_L1 LVDS:::110 10 MIL SPACING 20 22 39
UIDE_DIOR_L :::600 10 MIL SPACING 200 100 MHZ 14 24 LVDS_L2N
UIDE_DMACK_L :::400 200 100 MHZ 14 24
LVDS_L2 LVDS:::110 10 MIL SPACING 20 22 39
T = 0.7MIL (TRACE THICKNESS)
LVDS_L2P LVDS_L2 LVDS:::110 10 MIL SPACING 20 22 39
UIDE_CS0_L :::500 200 100 MHZ 14 24 UPPER CLKLVDS_UN CLKLVDS_U LVDS:::110 500 10 MIL SPACING 4 20 22 39
S = 10MIL (SEPERATION OF DIFF TRACES)
UIDE_CS1_L :::500 200 100 MHZ 14 24 CLKLVDS_UP
UIDE_DMARQ :::400 200 100 MHZ 14
CLKLVDS_U LVDS:::110 500 10 MIL SPACING 4 20 22 39
ZSINGLE = 53.37OHM
LVDS_U0N LVDS_U0 LVDS:::110 10 MIL SPACING 20 22 39
UIDE_IOCHRDY :::600 10 MIL SPACING 200 100 MHZ 14 24 LVDS_U0P LVDS_U0 LVDS:::110 10 MIL SPACING 20 22 39
ZDIFF = 107.17OHM
UIDE_INTRQ :::400 200 100 MHZ 14 LVDS_U1N LVDS_U1 LVDS:::110 10 MIL SPACING 20 22 39
HD_DATA<15..0> ::8000:9500 5 200 MATCHED_DELAY=HD_DATA:::1000 100 MHZ 24 LVDS_U1P
TOTAL UIDE+HD SKEW <500MIL LVDS_U1 LVDS:::110 10 MIL SPACING 20 22 39
HD_ADDR<2..0> ::8000:9500 5 200 100 MHZ 24 LVDS_U2N LVDS_U2 LVDS:::110 10 MIL SPACING 20 22 39
HD_RESET_L ::5000:7000 5 200 100 MHZ 24 LVDS_U2P LVDS_U2 LVDS:::110 10 MIL SPACING 20 22 39
HD_DIOW_L ::6000:8000 5 200 100 MHZ 24
TMDS TMDS_CONN_CLKN CLKCONN_TMDS TMDS_CONN:::50 500 10 MIL SPACING 4 22 39
HD_DIOR_L ::8000:9500 5 10 MIL SPACING 200 MATCHED_DELAY=HD_DATA:::1000 100 MHZ 24 TMDS_CONN_CLKP CLKCONN_TMDS TMDS_CONN:::50 500 10 MIL SPACING 4 22 39
HD_DMACK_L ::7500:9000 5 200 100 MHZ 24 TMDS_CLKN CLKTMDS TMDS:::50 500 10 MIL SPACING 4 20 21 22
HD_CS0_L ::6000:9000 5 200 100 MHZ 24 TMDS_CLKP CLKTMDS TMDS:::50 500 10 MIL SPACING 4 20 21 22
HD_CS1_L ::6000:9000 5 200 100 MHZ 24 TMDS_DN<0> TMDS_D0 TMDS:::50 10 MIL SPACING 20 21 22 39
HD_DMARQ ::7500:9000 5 200 100 MHZ 14 24 TMDS_DP<0> TMDS_D0 TMDS:::50 10 MIL SPACING 20 21 22 39
HD_IOCHRDY ::8000:9500 5 10 MIL SPACING 200 MATCHED_DELAY=HD_DATA:::1000 100 MHZ 24 TMDS_DN<1> TMDS_D1 TMDS:::50 10 MIL SPACING 20 21 22 39
HD_INTRQ ::6000:8000 5 100 MHZ 14 24 TMDS_DP<1> TMDS_D1 TMDS:::50 10 MIL SPACING 20 21 22 39
EIDE_DATA<15..0> TMDS_DN<2> TMDS_D2 TMDS:::50 10 MIL SPACING 20 21 22 39
EIDE EIDE_ADDR<2..0>
:::855
:::900
33 MHZ
33 MHZ
14 24
14 24
TMDS_DP<2> TMDS_D2 TMDS:::50 10 MIL SPACING 20 21 22 39
INTREPID EIDE_CS0_L :::850 33 MHZ 14 24 USB NEC_USB_DAM NEC_USB_DA NEC_USB_DA:::20 MIN_LINE_WIDTH=5 10 MIL SPACING 26
EIDE_CS1_L NEC_USB_DAP NEC_USB_DA NEC_USB_DA:::20 MIN_LINE_WIDTH=5 10 MIL SPACING 26
:::850 33 MHZ 14 24
EIDE_RD_L USB_DEM USB_DE USB_DE:::200 5 MIL SPACING 15
:::500 33 MHZ 14 24
USB_DEP USB_DE USB_DE:::200 5 MIL SPACING
B EIDE_WR_L
EIDE_IOCHRDY
:::500
:::500
33 MHZ
33 MHZ
14 24
14 24
NEC_USB_DBM NEC_USB_DB NEC_USB_DB:::20 MIN_LINE_WIDTH=5 10 MIL SPACING
15
26
INTERNAL LAYER (USB1.1/USB 2.0) B
EIDE_INT NEC_USB_DBP NEC_USB_DB NEC_USB_DB:::20 MIN_LINE_WIDTH=5 10 MIL SPACING 26
:::500 33 MHZ 14 24
USB_DFM USB_DF USB_DF:::200 5 MIL SPACING 15
ER = 4.3 (DIELECTRIC CONSTANT)
EIDE_RST_L :::500 33 MHZ 14 24
EIDE_DMACK_L :::500 33 MHZ 14 24
USB_DFP USB_DF USB_DF:::200 5 MIL SPACING 15 W = 4MIL(USB 1.1)/ 5MIL(USB 2.0) (TRACE WIDTH)
EIDE_DMARQ BT_USB_DM BT_USB_D BT_USB_D:::200 5 MIL SPACING 15 24 39
:::500 33 MHZ 14 24
BT_USB_DP BT_USB_D BT_USB_D:::200 5 MIL SPACING 15 24 39
B = 12.2MIL (DIST BETW 2 GND PLANES)
EIDE_OPTICAL_DATA<15..0>
::4500:6500 33 MHZ 24 39
OPTICAL NEC_USB_RSDM1
EIDE_OPTICAL_ADDR<2..0>::4500:6500 33 MHZ 24 39
NEC_USB_RSD1 NEC_USB_RSD1:::20 MIN_LINE_WIDTH=5 10 MIL SPACING 26
T = 0.7MIL (TRACE THICKNESS)
EIDE_OPTICAL_CS0_L NEC_USB_RSDP1 NEC_USB_RSD1 NEC_USB_RSD1:::20 MIN_LINE_WIDTH=5 10 MIL SPACING 26
::5000:7000 33 MHZ 24 39
EIDE_OPTICAL_CS1_L ::5000:7000 33 MHZ 24 39
NEC_USB_RSDM2 NEC_USB_RSD2 NEC_USB_RSD2:::20 MIN_LINE_WIDTH=5 10 MIL SPACING 26
S = 5MIL (USB 1.1) (SEPERATION OF DIFF TRACES)
EIDE_OPTICAL_RD_L ::5000:7000 33 MHZ 24 39
NEC_USB_RSDP2 NEC_USB_RSD2 NEC_USB_RSD2:::20 MIN_LINE_WIDTH=5 10 MIL SPACING 26 S = 10MIL (USB 2.0) (SEPERATION OF DIFF TRACES)
EIDE_OPTICAL_WR_L MODEM_USB_DM MODEM_USB_D MODEM_USB:::200 5 MIL SPACING 15 25 39
::5000:7000 33 MHZ 24 39
MODEM_USB_DP MODEM_USB_D MODEM_USB:::200 5 MIL SPACING 15 25 39
ZSINGLE = 51.5OHM (USB 1.1)/ 46.2OHM (USB 2.0)
EIDE_OPTICAL_IOCHRDY ::5000:7000 33 MHZ 24 39
EIDE_OPTICAL_INT ::5500:7500 33 MHZ 24 39
LEFT_USB_DM LEFT_USB LEFT_USB:::20 MIN_LINE_WIDTH=5 10 MIL SPACING 24 26 39
ZDIFF = 89.3OHM (USB 1.1)/ 89.4OHM (USB 2.0)
EIDE_OPTICAL_RST_L LEFT_USB_DP LEFT_USB LEFT_USB:::20 MIN_LINE_WIDTH=5 10 MIL SPACING 24 26 39
::5000:7000 33 MHZ 24 39
EIDE_OPTICAL_DMAACK_L RIGHT_USB_DM RIGHT_USB RIGHT_USB:::20 MIN_LINE_WIDTH=5 10 MIL SPACING 26 32 39
::5000:7000 33 MHZ 24 39
EIDE_OPTICAL_DMA_RQ RIGHT_USB_DP RIGHT_USB RIGHT_USB:::20 MIN_LINE_WIDTH=5 10 MIL SPACING 26 32 39
::5000:7000 33 MHZ 24 39
POWER 1772_CSSN 1772_CSS 1772_CSS:::100 31
ENET_LINK_RXD<7..0> ::8000:9000 5 14 27
ETHERNET MII SUPPLIES
ENET_RX_DV 1772_CSSP 1772_CSS 1772_CSS:::100 31
::8000:9000 14 27
ENET_RX_ER 1772_CSIN 1772_CSI 1772_CSI:::100 31
::8000:9000 14 27
ENET_PHY_TXD<7..0> 1772_CSIP 1772_CSI 1772_CSI:::100 31
::8300:9300 5 14 27
ENET_LINK_TXD<7..0> 3V_SNSM 3V_SNS 3V_SNS:::100 33
:::600 14
ENET_PHY_TX_ER 3V_SNSP 3V_SNS 3V_SNS:::100 33
::8000:9200 5 14 27
ENET_LINK_TX_ER 5V_SNSM 5V_SNS 5V_SNS:::100 33
:::400 14
ENET_PHY_TX_EN 5V_SNSP 5V_SNS 5V_SNS:::100 33
::8000:9200 5 14 27
THERMOSTAT THERM1_DM THERM1 THERM1:::100 25
SIGNAL CONSTRAINTS - PAGE 2
A ENET_LINK_TX_EN
ENET_MDIO
:::400
::8000:9000
14
14 27
THERM1_DP THERM1 THERM1:::100 25
NOTICE OF PROPRIETARY PROPERTY
A
ENET_MDC THERM2_DM THERM2 THERM2:::100 25
::8000:9000 14 27
ENET_COL THERM2_DP THERM2 THERM2:::100 25
::7500:9000 14 27 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
THERM1_M_DM THERM1_MAIN THERM1_MAIN:::100 25
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
ENET_CRS ::7500:9000 14 27 AGREES TO THE FOLLOWING
THERM1_M_DP THERM1_MAIN THERM1_MAIN:::100 25
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
FIREWIRE MII FW_LINK_DATA<7..0> ::2700:3500 5 14 28 THERM2_M_DM THERM2_MAIN THERM2_MAIN:::100 25
II NOT TO REPRODUCE OR COPY IT
FW_PHY_DATA<7..0> ::4700:5500 5 28 THERM2_M_DP THERM2_MAIN THERM2_MAIN:::100 25
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
FW_LINK_CNTL<1..0> ::9000:10000 14 28 THERM1_A_DM THERM1_ALT THERM1_ALT:::100 25
FW_PHY_CNTL<1..0> :::300 28 THERM1_A_DP SIZE DRAWING NUMBER REV.
THERM1_ALT THERM1_ALT:::100 25
FW_LINK_LREQ
FW_PHY_LREQ
:::300
::8500:9500
14 THERM2_A_DM THERM2_ALT THERM2_ALT:::100 25
D 051-6469 F
14 28 THERM2_A_DP THERM2_ALT THERM2_ALT:::100 25 APPLE COMPUTER INC.
FW_PINT ::8500:9500 14 28 SCALE SHT OF
NONE 37 44
8 7 6 5 4 3 2 1
CR-38
8 7 6 5 4 3 2 1
POWER NET CONSTRAINTS GROUP SIG_NAME VOLTAGE MIN_LINE_WIDTH MIN_NECK_WIDTH GROUP SIG_NAME
1625_VIN
VOLTAGE
VOLTAGE=24V
MIN_LINE_WIDTH
MIN_LINE_WIDTH=10
MIN_NECK_WIDTH
32
GROUP SIG_NAME VOLTAGE MIN_LINE_WIDTH MIN_NECK_WIDTH CPU CPU_VCORE_SLEEP VOLTAGE=1.4V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 5 34 39
LTC1625 1625_VSW VOLTAGE=12.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 32
CPU_AVDD VOLTAGE=1.4V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 5
14V SWITCHER
MAXBUS_SLEEP 1625_EXTVCC VOLTAGE=5V MIN_LINE_WIDTH=10 32
VOLTAGE=1.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 5 7 9 16 17 23 34
+24V_PBUS VOLTAGE=24V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 1625_INTVCC VOLTAGE=5V MIN_LINE_WIDTH=10
MAIN/SLEEP +BATT VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
39
1625_SGND VOLTAGE=0V MIN_LINE_WIDTH=10
32
32
+PBUS VOLTAGE=12.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39
L3 CACHE L3_VREF VOLTAGE=0.75V MIN_LINE_WIDTH=10 8
1V20_REF VOLTAGE=1.2V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 31 32
+5V_MAIN VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+5V_SLEEP L3_CLK_REF VOLTAGE=0.75V MIN_LINE_WIDTH=10 8
VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+3V_MAIN VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
L3_OVDD VOLTAGE=1.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 6 8 LTC3707 3707_INTVCC VOLTAGE=5V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 33
5V_SW VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+3V_SLEEP VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=6 5V SWITCHER 33
D +3V_PMU VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 39
DDR RAM DDR_VREF VOLTAGE=1.25V MIN_LINE_WIDTH=10 12 5V_RSNS VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 33
D
+2_5V_MAIN VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+2_5V_INTREPID VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 10 11 16 17 3V SWITCHER 3V_SW VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 33
+2_5V_SLEEP VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 16
INTREPID +3V_INTREPID_USB VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 15 3V_RSNS VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 33
+1_8V_MAIN VOLTAGE=1.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=6 39
+1_5V_INTREPID_PLL VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 9 13 15 3707_SGND VOLTAGE=0V MIN_LINE_WIDTH=10 33
+1_8V_SLEEP VOLTAGE=1.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 PLLS
+1_5V_INTREPID_PLL1 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 15
+1_5V_MAIN VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+1_5V_SLEEP VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
+1_5V_INTREPID_PLL2 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 15 MAX1715 2_5V_LX VOLTAGE=2.5V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 35
+1_5V_LDO
+1_5V_INTREPID_PLL3 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 15 2.5V SWITCHER 2_5V_BST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 35
VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 16 19 35
+1_5V_INTREPID_PLL4 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=5 15 2_5V_BOOST
+1_5V_SLEEP_VIN VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 35
VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 35
+1_5V_INTREPID_PLL5 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=5 13 2_5V_DH VOLTAGE=2.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 35
+1_5V_INTREPID_PLL6 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 13 2_5V_DL VOLTAGE=2.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 35
ADAPTER +ADAPTER VOLTAGE=24V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 31 32 +1_5V_INTREPID_PLL7 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 9
+ADAPTER_SW VOLTAGE=24V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 31 +1_5V_INTREPID_PLL8 VOLTAGE=1.5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=6 15
+ADAPTER_SENSE VOLTAGE=24V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 31
MIN_NECK_WIDTH REDUCED FOR TESTPOINTS
1_5V_FB VOLTAGE=1.5V MIN_LINE_WIDTH=8
INT_MEM_VREF VOLTAGE=1.25V MIN_LINE_WIDTH=10 10
1.5V SWITCHER 35
REFERENCE 1_5V_LX VOLTAGE=1.5V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10 35
+BATT_POS INT_AGP_VREF VOLTAGE=1.25V MIN_LINE_WIDTH=10 13
VOLTAGE=16.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 31 39
BATTERY BATT_NEG VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 31 39
INT_MEM_REF_H VOLTAGE=0V MIN_LINE_WIDTH=10 10
1_5V_BST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 35
1_5V_BOOST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 35
CHARGER 1772_DCIN VOLTAGE=24V MIN_LINE_WIDTH=10 31
UIDE_REF VOLTAGE=0V MIN_LINE_WIDTH=8 14
1_5V_DH VOLTAGE=1.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 35
1772_LX VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 31 1_5V_DL VOLTAGE=1.5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 35
+BATT_14V_FUSE VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 31 1_5V_ILIM
CONTROL MIN_LINE_WIDTH=8 35
+BATT_24V_FUSE VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 31 +VCC_CBUS_SW 2_5V_ILIM
VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 18 MIN_LINE_WIDTH=8 35
+BATT_RSNS VOLTAGE=12.6V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 31
CARDBUS +VPP_CBUS_SW VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 18 MAX1715_TON MIN_LINE_WIDTH=8 35
+BATT_VSNS VOLTAGE=12.6V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 31 MAX1715_SKIP MIN_LINE_WIDTH=8 35
1772_LDO VOLTAGE=5.4V MIN_LINE_WIDTH=10 GPU_VCORE VOLTAGE=1.2V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
1772_DLOV VOLTAGE=5.4V MIN_LINE_WIDTH=10
31
31
NVIDIA +2_5V_GPU_FB VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
20 39
19
MAX1715_REF VOLTAGE=2.0V MIN_LINE_WIDTH=8 35
MAX1715_VCC VOLTAGE=5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 35
1772_GND VOLTAGE=0V MIN_LINE_WIDTH=10 31 NV17MAP +3V_GPU VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 13 15 19 20 21 MAX1715_GND VOLTAGE=0V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 35
+3V_GPU_DVO VOLTAGE=3.3V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=8 21
C PMU +ADAPTER_ILIM VOLTAGE=24V MIN_LINE_WIDTH=10 32
+1_5V_AGP VOLTAGE=1.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 13 16 17 19 20 C
+ADAPTER_OR_BATT VOLTAGE=24V MIN_LINE_WIDTH=10 32 +3V_DAC1VDD VOLTAGE=3.3V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21
MAX1717 VCORE_VCC VOLTAGE=5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 34
+4_85V_RAW VOLTAGE=4.85V MIN_LINE_WIDTH=10 30 32 +3V_DAC2VDD VOLTAGE=3.3V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21 VCORE_LX VOLTAGE=1.4V MIN_LINE_WIDTH=200 MIN_NECK_WIDTH=10 34
+4_6V_BU VOLTAGE=4.6V MIN_LINE_WIDTH=10 32 33 +3V_GPU_AVDD1 VOLTAGE=3.3V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 20 VCORE_DH MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 34
+4_85V_ESR VOLTAGE=4.85V MIN_LINE_WIDTH=10 32 +3V_GPU_AVDD0 VOLTAGE=3.3V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 20 VCORE_DL MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 34
+3V_PMU_ESR VOLTAGE=3.3V MIN_LINE_WIDTH=10 32 +3V_GPU_PLLVDD VOLTAGE=3.3V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 21 VCORE_BOOST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 34
+3V_PMU_AVCC VOLTAGE=3.3V MIN_LINE_WIDTH=10 30 +3V_GPU_SS VOLTAGE=3.3V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 21 VCORE_BST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 34
+2_8V_IFP_PLLVDD VOLTAGE=2.8V MIN_LINE_WIDTH=10 MIN_NECK_WIDTH=10 20 VCORE_ILIM MIN_LINE_WIDTH=8 34
MISC GPU_AGP_VREF VOLTAGE=0.75V MIN_LINE_WIDTH=10 19 VCORE_REF MIN_LINE_WIDTH=8 34
+5V_HD_SLEEP VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
HD 24 33
GPU_FB_VREF VCORE_TON
+HD_LOGIC_SLEEP VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 24
VOLTAGE=1.25V MIN_LINE_WIDTH=10 19 VOLTAGE=5V MIN_LINE_WIDTH=8 34
VCORE_CC MIN_LINE_WIDTH=8 34
+5V_TPAD_SLEEP VOLTAGE=5V MIN_LINE_WIDTH=10 23 39 VCORE_FB
TRACKPAD +3V_SI_PLLVCC VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8 VOLTAGE=1.4V MIN_LINE_WIDTH=8 34 39
SILICON +3V_SI_AVCC VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8
21
21
VCORE_TIME MIN_LINE_WIDTH=8 34
+3V_HALL_EFFECT VOLTAGE=3.3V MIN_LINE_WIDTH=10 23 39
IMAGE +3V_SI_VCC VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8 21
VCORE_VGATE MIN_LINE_WIDTH=8 15 34
HALL EFFECT VCORE_GND VOLTAGE=0V MIN_LINE_WIDTH=30 34
VCORE_GNDSNS VOLTAGE=0V MIN_LINE_WIDTH=8 34
+12_8V_INV VOLTAGE=12.8V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 +2_5V_MARVELL VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
VIDEO
+5V_INV_UF_SW VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10
22 39
22
88E1111 +2_5V_MARVELL_AVDD VOLTAGE=2.5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8
27
27
VCORE_SNS VOLTAGE=1.4V MIN_LINE_WIDTH=8 34
VCORE_GNDDIV VOLTAGE=0V MIN_LINE_WIDTH=8 34
+5V_INV_SW VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 22 39 +1_0V_MARVELL VOLTAGE=1.0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8 27
+5V_DDC_SLEEP VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 22 39 LTC3405_SW VOLTAGE=1.0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=8 27
+5V_DDC_SLEEP_UF VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10 22
LTC1778 1778_VIN VOLTAGE=14V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 20
1778_VCC VOLTAGE=5V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 20
+3V_LCD VOLTAGE=3.3V MIN_LINE_WIDTH=12 MIN_NECK_WIDTH=10 22
1778_GND VOLTAGE=0V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 20
+3V_LCD_SW VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 22
1778_BST VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10
GPU_TV_GND1 VOLTAGE=0V MIN_LINE_WIDTH=25 22 FW LM2594_IN VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
1778_BST_RC VOLTAGE=5V MIN_LINE_WIDTH=15 MIN_NECK_WIDTH=10
20
20
GPU_TV_GND2 +3V_FW_ESD_ILIM VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 29
VOLTAGE=0V MIN_LINE_WIDTH=25 22
+3V_FW_ESD 1778_TG MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 20
TV_GND1 VOLTAGE=0V MIN_LINE_WIDTH=25 22 39
VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 29
1778_BG MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
B TV_GND2 VOLTAGE=0V MIN_LINE_WIDTH=25 22 39
+FW_FUSE
+FW_SW
VOLTAGE=12.8V
VOLTAGE=12.8V
MIN_LINE_WIDTH=100
MIN_LINE_WIDTH=100
MIN_NECK_WIDTH=12
MIN_NECK_WIDTH=12
29
29
GPU_VCORE_SW VOLTAGE=1.2V MIN_LINE_WIDTH=50 MIN_NECK_WIDTH=10
20
20 B
+FW_PWR_OR 1778_ION MIN_LINE_WIDTH=8 20
VOLTAGE=33V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 28 29
KB LED KBD_LED1_OUT VOLTAGE=0V MIN_LINE_WIDTH=10 23 23 39
+FW_VP0 1778_ITH MIN_LINE_WIDTH=8 20
VOLTAGE=33V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29
KBD_LED2_OUT VOLTAGE=0V MIN_LINE_WIDTH=10 23 23 39 1778_ITH_RC
+FW_PWR_PORTA VOLTAGE=33V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29
MIN_LINE_WIDTH=8 20
+FW_VP1 1_5V_2_5V_OK MIN_LINE_WIDTH=8 20 35
FAN GND FAN1_GND VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 23 25 39
VOLTAGE=33V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29
+3V_FW 1778_VFB MIN_LINE_WIDTH=8 20
FAN2_GND VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 23 25 39
VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28 29
+3V_FW_UF 1778_FCB MIN_LINE_WIDTH=8 20
VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
SOUND +5V_SOUND_SLEEP +3V_FW_AVDD_PORT2 1778_VRNG MIN_LINE_WIDTH=8 20
VOLTAGE=5V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 25 VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
SND_AGND VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=15 25 +3V_FW_AVDD_PORT1 VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=6 28
LTC3411_VCC VOLTAGE=3.3V MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 35
+3V_FW_AVDD_PORT0 VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
LTC3411 LTC3411_GND VOLTAGE=0V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 35
+3V_FW_AVDD VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
+1_95V_FW_DVDD 1_8V_SW VOLTAGE=1.8V MIN_LINE_WIDTH=30 MIN_NECK_WIDTH=10 35
VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
+1_95V_FW_DVDD_RX0 1_8V_VFB MIN_LINE_WIDTH=8 35
VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
+1_95V_FW_DVDD_TX0 LTC3411_ITH_RC MIN_LINE_WIDTH=8 35
VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
+1_95V_FW_DVDD_PORT1 LTC3411_ITH MIN_LINE_WIDTH=8 35
VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
+1_95V_FW_PLLVDD LTC3411_SYNC MIN_LINE_WIDTH=8 35
VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=6 GND LTC3411_SHDN
+1_95V_FW_PLL400VDD VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
MIN_LINE_WIDTH=8 35
+1_95V_FW_PLL500VDD VOLTAGE=1.95V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 28
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 CHGND1
I/O AREA CHGND1
FW_VGND0 VOLTAGE=0V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29 LTC1962 LTC1962_INT_VIN
LTC1962_L3_VIN
MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 15
FW_VGND1 VOLTAGE=0V MIN_LINE_WIDTH=100 MIN_NECK_WIDTH=12 29 INT PLLS MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10 6
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 CHGND2 LTC1962_L3_VOUT MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
INVERTER CHGND2
FW_TPO0R VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 29 39
LTC1962_1V5_VIN MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
6
16
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 CHGND3 LTC1962_1V5_VOUT MIN_LINE_WIDTH=20 MIN_NECK_WIDTH=10
TRACKPAD CHGND3
USB 2.0 NEC_AVDD VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 26
16
+3V_NEC_VDD VOLTAGE=3.3V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=10 26
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 CHGND4
LVDS SIGNAL CONSTRAINTS - PAGE 3
A CHGND4
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 CHGND5
INTREPID +3V_CG_PLL_MAIN
+2_5V_CG_MAIN
VOLTAGE=3.3V
VOLTAGE=2.5V
MIN_LINE_WIDTH=15
MIN_LINE_WIDTH=15
MIN_NECK_WIDTH=8
MIN_NECK_WIDTH=8
15
NOTICE OF PROPRIETARY PROPERTY
A
I/O AREA CHGND5 SSCG 15
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 CHGND6 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I/O AREA CHGND6
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
ENET_CTAP_CHGND VOLTAGE=0V MIN_LINE_WIDTH=25 MIN_NECK_WIDTH=12 27
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6469 F
APPLE COMPUTER INC.
SCALE SHT OF
NONE 38 44
8 7 6 5 4 3 2 1
CR-39
8 7 6 5 4 3 2 1
FUNCTIONAL TEST POINTS FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_X<9> 23 30
+5V_INV_SW 22 38
PCI_AD<7> PCI_PAR EIDE_OPTICAL_CS0_L 24 37
JTAG_ASIC_TMS TMDS_CONN_CLKP TV_C 10 13 18 24 26 37 13 18 24 26 37
14 27 22 37 22
FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_Y<0> 23 30
LEFT_USB_DM 24 26 37
PCI_AD<8> PCI_CBE<0> 13 18 24 26 37
EIDE_OPTICAL_CS1_L 24 37
JTAG_ASIC_TDI VGA_R TV_Y 10 13 18 24 26 37
14 22 22
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_Y<1> 23 30 FW_TPO1P LEFT_USB_DP 24 26 37
EIDE_OPTICAL_RST_L 24 37 29 37
PCI_AD<9> 10 13 18 24 26 37 PCI_CBE<1> 13 18 24 26 37
D
JTAG_ASIC_TDO_TP 27 VGA_G 22 TV_COMP 22
FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES
D
FUNC_TEST=TRUE FUNC_TEST=TRUE RIGHT_USB_DM
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_Y<2> 23 30 FW_TPO1N 29 37
26 32 37
PCI_AD<10> 10 13 18 24 26 37 PCI_CBE<2> 13 18 24 26 37
EIDE_OPTICAL_WR_L 24 37
JTAG_ASIC_TCK 14 27 VGA_B 22 SND_TO_AUDIO 15 25
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_Y<3> 23 30 FW_TPI1P RIGHT_USB_DP 26 32 37
EIDE_OPTICAL_IOCHRDY 24 37 29 37
JTAG_ASIC_TRST_L VGA_VSYNC SND_SYNC PCI_AD<11> 10 13 18 24 26 37 PCI_CBE<3> 13 18 24 26 37
14 27 21 22 15 25
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_Y<4> 23 30 FW_TPI1N NEC_LEFT_USB_PWREN 24 26
EIDE_OPTICAL_INT 24 37 29 37
CPU_CHKSTP_OUT_L VGA_HSYNC SND_CLKOUT PCI_AD<12> 10 13 18 24 26 37 AIRPORT_PCI_REQ_L 13 24
5 21 22 15 25 36
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_Y<5> 23 30 CHARGE_LED_L NEC_LEFT_USB_OVERCURRENT 24 26
TPAD_F_TXD 30 31
PCI_AD<13> 10 13 18 24 26 37 AIRPORT_PCI_GNT_L 23
CPU_SRESET_L DVI_DDC_CLK_UF SND_HP_MUTE_L 13 24
5 22 15 25
FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES KBD_Y<6> 23 30 ADAPTER_DET NEC_RIGHT_USB_PWREN 26 32
TPAD_F_RXD 30 31
PCI_AD<14> 10 13 18 24 26 37 AIRPORT_PCI_INT_L 23
CPU_HRESET_L DVI_DDC_DATA_UF SND_AMP_MUTE_L 15 24
5 7 23 22 15 25
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_Y<7> 23 30 SUTRO_ALS_GAIN_SW NEC_RIGHT_USB_OVERCURRENT 26 32
LID_CLOSED_L 23 24
PCI_AD<15> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<0> 23
JTAG_CPU_TMS DVI_HPD_UF INT_AUDIO_TO_SND 24 37
5 23 22 15 25
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES KBD_NUMLOCK_LED SUTRO_ALS_OUT DCDC_EN 20 29 32 33 34
COMM_RESET_L 23 23 24
PCI_AD<16> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<1> 15 25
JTAG_CPU_TDI LVDS_L0N SND_SCLK 24 37
5 23 20 22 37 15 25 36
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES +BATT_POS KBD_LED1_OUT BBANG_HRESET_L 23
COMM_SHUTDOWN 31 38 23 38
PCI_AD<17> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<2> 15 25
JTAG_CPU_TDO_TP LVDS_L0P SND_HW_RESET_L 24 37
5 20 22 37 15 25
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES BATT_CLK KBD_LED2_OUT LT1962_L3_ADJ 6
COMM_RING_DET_L 31 23 38
C JTAG_CPU_TCK 5 23 LVDS_L1N 20 22 37 SND_HP_SENSE_L 15 25
PCI_AD<18> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<3> 24 37
15 25 30
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
C
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=YES MAIN_RESET_L 18 19 21 24 26 30
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES BATT_DATA 31 COMM_TXD_L 15 25
PCI_AD<19> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<4> KBD_ID 23 30
JTAG_CPU_TRST_L LVDS_L1P SND_LIN_SENSE_L 15 25 24 37
5 23 20 22 37
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE RF_DISABLE_L_SPN 24
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES BATT_NEG 31 38 COMM_TRXC 15 25
PCI_AD<20> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<5> +5V_TPAD_SLEEP 23 38
JTAG_L3_TMS LVDS_L2N INT_I2C_DATA2 24 37
8 20 22 37 15 25
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE AIRPORT_CLKRUN_L 24
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES PMU_BATT_DET_L 30 31 COMM_GPIO_L 15 25
PCI_AD<21> 13 18 24 26 37 EIDE_OPTICAL_DATA<6> +3V_HALL_EFFECT 23 38
JTAG_L3_TDI_TP LVDS_L2P INT_I2C_CLK2 24 37
8 20 22 37 15 25
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE ROM_RW_L 10 13 24
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FAN1_GND 25 38 COMM_DTR_L 15 25
PCI_AD<22> 13 18 24 26 37 EIDE_OPTICAL_DATA<7> KBD_CAPSLOCK_LED 23
JTAG_L3_TDO_TP CLKLVDS_LN USB_D1M 24 37
8 20 22 37 15 26
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE ROM_ONBOARD_CS_L 10 24
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FAN1_TACH 25 COMM_RTS_L 15 25
PCI_AD<23> 13 18 24 26 37 EIDE_OPTICAL_DATA<8> KBD_FUNCTION_L 23 30
JTAG_L3_TCK CLKLVDS_LP USB_D1P 24 37
8 20 22 37 15 26
FUNC_TEST=YES
NO LONGER NEED BY TEST GROUP FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE ROM_CS_L 10 13 24
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FAN2_GND 25 38 COMM_RXD 15 25
PCI_AD<24> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<9> KBD_CONTROL_L 23 30
INT_I2C_CLK0 LVDS_U0N USB_D2M 15 26 24 37
12 14 23 20 22 37
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE CLK33M_AIRPORT 13 24 36
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FAN2_TACH 25 PMU_KB_RESET_L 30
PCI_AD<25> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<10> 24 37
KBD_COMMAND_L 23 30
INT_I2C_DATA0 12 14 23 LVDS_U0P 20 22 37 USB_D2P 15 26
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE AIRPORT_IDSEL 24
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES RJ45_DP<0> 27 37 PWR_BUTTON_L 23 25
PCI_AD<26> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<11> 24 37
KBD_OPTION_L 23 30
INT_I2C_CLK1 14 15 25 LVDS_U1N 20 22 37 BT_USB_DM 15 24 37
FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=TRUE FUNC_TEST=TRUE
FUNC_TEST=TRUE FUNC_TEST=TRUE ROM_OE_L
B FUNC_TEST=YES
INT_I2C_DATA1 14 15 25
FUNC_TEST=YES
LVDS_U1P 20 22 37
FUNC_TEST=YES
BT_USB_DP 15 24 37
PCI_AD<27> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<12> 24 37
KBD_SHIFT_L 23 30
RJ45_DN<0> 27 37 +PBUS 38
10 13 24
B
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE
FUNC_TEST=TRUE FUNC_TEST=TRUE
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES RJ45_DP<1> 27 37 +24V_PBUS 38
PCI_AD<28> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<13> 24 37
KBD_X<0> 23 30
CBUS_DET_1_L 18 LVDS_U2N 20 22 37 MODEM_USB_DM 15 25 37
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES RJ45_DN<1> 27 37 GPU_VCORE 20 38
PCI_AD<29> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<14> 24 37
KBD_X<1> 23 30
CBUS_DET_2_L 18 LVDS_U2P 20 22 37 MODEM_USB_DP 15 25 37
FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=TRUE RJ45_DP<2> 27 37 CPU_VCORE_SLEEP 5 34 38
PCI_AD<30> 10 13 18 24 26 37 EIDE_OPTICAL_DATA<15> 24 37
KBD_X<2> 23 30
TMDS_DN<0> 20 21 22 37 CLKLVDS_UN 20 22 37 PCI_AD<0> 10 13 18 24 26 37
FUNC_TEST=TRUE FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=TRUE
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=TRUE RJ45_DN<2> 27 37 VCORE_FB 34 38
PCI_AD<31> 10 13 18 24 26 37 EIDE_OPTICAL_DMA_RQ 24 37
KBD_X<3> 23 30
TMDS_DP<0> 20 21 22 37 CLKLVDS_UP PCI_AD<1> 10 13 18 24 26 37 24 36
20 22 37
FUNC_TEST=TRUE FUNC_TEST=TRUE
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=TRUE
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=TRUE RJ45_DP<3> 27 37 +1_8V_MAIN 38
PCI_FRAME_L EIDE_OPTICAL_RD_L 24 36 24 37
KBD_X<4> 23 30
TMDS_DN<1> 20 21 22 37 LVDS_DDC_CLK PCI_AD<2> 10 13 18 24 26 37 13 18 24 26 37
20 22
FUNC_TEST=TRUE FUNC_TEST=TRUE
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=TRUE
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=TRUE RJ45_DN<3> 27 37 +3V_PMU 38
PCI_TRDY_L EIDE_OPTICAL_DMAACK_L 24 37
KBD_X<5> 23 30
TMDS_DP<1> 20 21 22 37 LVDS_DDC_DATA PCI_AD<3> 10 13 18 24 26 37 13 18 24 26 37 24 36
20 22
FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE
FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=TRUE +5V_DDC_SLEEP 22 38
PCI_IRDY_L EIDE_OPTICAL_ADDR<0> KBD_X<6> 23 30
TMDS_DN<2> 20 21 22 37 BRIGHT_PWM PCI_AD<4> 10 13 18 24 26 37 13 18 24 26 37 24 37
22
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=TRUE
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=TRUE FW_TPO0R 29 38 +12_8V_INV 22 38
PCI_DEVSEL_L EIDE_OPTICAL_ADDR<1> KBD_X<7> 23 30
TMDS_DP<2> 20 21 22 37 TV_GND1 PCI_AD<5> 10 13 18 24 26 37 13 18 24 26 37 24 37
22 38
A FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=TRUE
FUNC_TEST=YES FUNC_TEST=TRUE FUNC_TEST=TRUE
NOTICE OF PROPRIETARY PROPERTY
A
PCI_STOP_L EIDE_OPTICAL_ADDR<2> KBD_X<8> 23 30
TMDS_CONN_CLKN TV_GND2 PCI_AD<6> 10 13 18 24 26 37 13 18 24 26 37 24 37
22 37 22 38
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 39 44
8 7 6 5 4 3 2 1
CR-40
8 7 6 5 4 3 2 1
263/ PULLED DS2 HIGH TO SHUT-OFF PORT 3 ON FIREWIRE PHY COMPLETELY (PG 28)
REVISION HISTORY 264/
265/
266/
ADDED ONE MORE 1000UF POSCAP ON CPU_VCORE_SLEEP TO REDUCE RIPPLE BY ANOTHER 10MV, AND CHANGED OFFSET TO +30MV (PG 34)
FINE TUNED PCI SERIES RESISTOR R VALUES FOR EMI AND DIVIDED CY28512 OUTPUT FROM 2.5V TO 1.5V (PG 13,15)
CY28512 NOW RUNS ON 3V_MAIN AND 2.5V_MAIN... UPDATED THE STRAPS TOO (PG 15)
BOM UPDATE FOR PRODUCTION
REV D (051-6469) - 07/22/03
267/ ALS SENSOR IS NOW RUNNING DURING SLEEP PER THAI’S REQUEST (PG 23, 24)
356/ CHANGED J21 TO NEW GOLD PLATE 80PIN CONNECTOR 516S0142 (PG 24)
RELEASED FOR PROTO 1 RELEASED FOR PROTO 1 268/
269/
CHGND1 NOW SPLITS INTO CHGND1 AND CHGND6 BECAUSE OF FIREWIRE B ROUTING ON THE SURFACE (PG 29)
SEPARATED 0 OHM RESISTORS FOR EACH FIREWIRE GROUND PINS (PG 29)
REV 1.1 - 08/14/02 270/ CY28512 RESET PIN NOW GOES TO +3V_MAIN - INT_RESET_L WILL NOT WORK (PG 15)
149/ UPDATED SOME NETS FOR CONCEPT 14.2 COMPLIANCE (PG 30,36) 271/
272/
CHANGED PULL-UPS FOR FAN CONTROL SIGNALS TO +3V_SLEEP - LEAKAGE PROBLEM THROUGH THE FAN (PG 25)
NO STUFFED PULL-UP RESISTORS FOR EIDE_RESET AND EIDE_DMAACK_L - PER MKE DRIVE SPEC (PG 24)
BOM UPDATE FOR PRODUCTION
150/ CORRECTED PMU PART NUMBER (PG 28)
151/ DELETED 4 0805 BULK CAPS AND ADDED 20 0402 BYPASS CAPS ON DDR SODIMM CONNECTOR (PG 12) REV E (051-6469) - 08/07/03
152/ REPINNED OUT J13 (HARD DRIVE) CONNECTOR FOR BETTER FLEX ROUTING (PG 24) RELEASED FOR EVT RELEASED FOR EVT 357/ DISQUALIFIED AND REMOVED KEMET POLYMER CAPS FOR CPU_VCORE(PG 34)
153/ ADDED A FEW MORE COMPONENTS TO ALS CIRCUIT BASED ON THAI’S RECOMMENDATIONS (PG 23) LAST MINUTE BOM CHANGES FOR PROTO2 (10/29/02)
154/ REMOVED PROTO1 CONNECTOR OPTIONS (PG 1, 22, 26, 27) 273/ UPDATED BOMOPTION "NO SSCG" TO "NO_SSCG" (PG 9)
155/ ADDED USB 2.0 CONTROLLER (PG 26) 274/ FIXED SYSTEM BUS TO 167MHZ OPERATION BECAUSE WE ARE USING INTREPID 2.0 (PG 15)
D
156/
157/
158/
CHANGED TO SPIDEY 39PIN ZIF CONNECTOR AND PINOUT (PG 23)
ADDED INTREPID SSCG CHIP SUPPORT (PG 15)
CONSOLIDATED BOMS
REV 5.0 - 12/03/02 D
159/ UPDATED USB 2.0 SIGNAL CONSTRAINTS (PG 26) 275/ P50 IS ONLY POWERED BY +3V_SLEEP NOW (PG 24)
160/ CHANGED CPU CORE VOLTAGE TO 1.45V FAST/1.40V SLOW (PG 33) 276/ CHANGED TO ONE 1.5A FIREWIRE FUSE (PG 29)
161/ ADDED +3V_SLEEP TO TUBA CONNECTOR (PG 25) 277/ ADDED PULL-DOWN TO P50’S CLKRUN_L SIGNAL AND NO CONNECTED P50’S PME SIGNAL (PG 24)
162/ MERGED MAXBUS_MAIN WITH MAXBUS_SLEEP BECAUSE INTREPID MAXBUS I/O CAN BE POWERED DOWN IN SLEEP (PG 16,17) 278/ CHANGED PCI PULL-UP RESISTORS TO +3V_SLEEP TO SUPPORT P50 D3COLD (PG 13)
163/ DELETED ZT17 AND ZT2 BECAUSE THEY ARE NO LONGER NEEDED (PG 4) 279/ ADDED TWO 4.7UF BULK CAPS NEAR THE FAN CONNECTORS (PG 25)
164/ CHANGED FL1 TO NEW COMMON MODE CHOKES FOR FIREWIRE A (PG 28) 280/ FAN POWER GOES BACK TO +5V_SLEEP (PG 25)
165/ CHANGED CRYSTAL VOLTAGE DIVIDER FOR FIREWIRE PHY TO 50/100 (BILL’S RECOMMENDATION) (PG 28) 281/ NEW PART NUMBERS FOR INTREPID 2.1, ZEBRA-17, BS520, 50&80PIN CONNECTORS, NEW CPU DESC.
166/ ADDED 2N7002 TO PREVENT PMU_SLEEP_LED_L FROM PUMPING UP +3V_MAIN DURING SHUTDOWN (PG 23) 282/ NEW BOOT ROM AND LMU PART NUMBERS (PG 11, 23)
283/ FIXED DRCS AROUND SIL1162 BY CHANGING CONSTRAINTS (PG 21)
284/ ADDED SLEEP FET FOR +5V_SOUND (PG 25)
REV 2.0 - 08/26/02 285/ ADDED 5A FUSE FOR FIREWIRE PORT POWER - FOR SAFETY COMPLIANCE (PG 29)
167/ DELETED USB POWER FET (PG 23) 286/ ADDED ESD AND LATE VG PROTECTION FOR FIREWIRE (PG 29)
168/ CHANGED 14PIN ZIF CONNECTORS AND PINOUT (PG 24,31) 287/ CHANGED NOMINAL VCORE VOLTAGE TO 1.36V BECAUSE OF +/-50 MV REQUIREMENT ON GPU_VCORE (PG 20)
169/ CONNECTED VGATE TO EXTINT10 BECAUSE NEED INTERRUPT CONTROL (PG 15) 288/ CHANGED SIL1162 TO RISING CLOCK EDGE - STUFFING CHANGE (PG 21)
170/ UPDATED A FEW CONSTRAINTS 289/ ADDED DUAL SCHOTTKY FOR FIREWIRE PHY POWER (PG 28)
171/ ADDED NEW QUAD-VCORE CONTROL CIRCUITRY (PG 33) 290/ ADDED STUFFING OPTION TO FEED MAIN_RESET_L TO PCI1510 (PG 18)
172/ CHANGED OPTICAL CONNECTOR PINOUT (PG 24) 291/ LOADED IN NEW MECHANICAL SYMBOLS FOR WIRELESS,CARDBUS, AND HARD/OPTICAL DRIVES
173/ ADDED PMU_LID_CLOSED_L SIGNAL TO LMU (PG 23) 292/ NO STUFFED R888 BECAUSE THERE’S A WEAK INTERNAL PULL-UP ALREADY (PG 15)
174/ ADDED Q11 ADAPTER DETECTION SCHEME (PG 29) 293/ ADDED TWO 0805 ZERO OHM RESISTORS TO FEED IN EITHER +2_5V_SLEEP OR +2_5V_MAIN TO INTREPID (PG 16)
175/ ADDED DEDICATED RC FILTERING FOR PORT0 TX 0 (PG 28) 294/ CHANGED GPU_VCORE SWITCHER BOM OPTIONS TO REDUCE JITTER ON SUPPLY (PG 20)
176/ ADDED STUFFING OPTION FOR DS1 PIN ON FIREWIRE PHY (PG 28) 295/ CONNECTED MAX4172 POWER TO +ADAPTER_SW TO SAVE 1MA WHEN RUNNING ON BATTERY ONLY (PG 31)
177/ CHANGED STUFFING OPTION TO RAISE PLL VOLTAGE TO 1.95V FOR FW (PG 28) 296/ CHANGED Q47 AND Q58 TO 7811W FOR BOM CONSOLIDATION - ALSO CHANGED R348 AND R353 TO 113K TO ADJUST CURRENT LIMIT (PG 35)
178/ DELETED C741 (100UF INPUT CAP TO +3V_SLEEP) (PG 32) 297/ UPDATED BOM OPTION FOR SSCG (PG 9, 15)
179/ DELETED C757 (0.22UF BYPASS CAP FOR PCI1510) TO EASE TESTPOINT CONSTRAINTS (PG 18) 298/ CHANGED RESET CAP TO 0.22UF ON TI PHY PER TI’S RECOMMENDATION (PG 28)
180/ SEPERATED PULL-UP FOR PCI_SERR_L AND PCI_PERR_L (PG 18,26) 299/ UPDATED TO NEW TUBA CONNECTOR PINOUT (PG 25)
181/ CHANGED SYSCLK_CPU, INT_PCI_FB_OUT, AND INT_AGP_FB_OUT SERIES RESISTOR VALUE (PG 9, 13) 300/ CHANGED BOOTROM RESET TO INT_RESET_L FOR ICT (PG 10)
182/ CHANGED C533, C539 TO 270PF AND CHANGED CONNECTIONS (PG 32) 301/ ADDED 4 ZERO OHM RESISTORS TO NO STUFF THE QUAD_VCORE OPTION (PG 34)
183/ ADDED 4.7NF CAP ON Q51 GATE (PG 31) 302/ CHANGED ALL 132S1061 (0805 PACKAGE) TO 132S0046 (0603 PACKAGE) - (PG ALL)
184/ ADDED EMI SHIELD FOR INVERTER CHGND (PG 4) 303/ CHANGED TO TOP CONTACT SPIDEY CONNECTOR (PG 23)
185/ UPDATED MORE CONSTRAINTS 304/ ADDED BOM OPTION TO PCI CLOCK OUT FROM INTREPID TO USB CONTROLLER (PG 13)
186/ CHANGED STUFFING OPTION TO FORCE 3V/5V INTO FORCE CONTINUOUS MODE TO REDUCE INDUCTOR SINGING (PG 32) 305/ CHANGED TO NEW 30PIN TUBA CONNECTOR WITH SOLDER TAPS (PG 25)
187/ CHANGED FW DVDD LDO TO 1.95V PER BILL’S RECOMMENDATION (PG 28) 306/ UPDATED ETHERNET SERIES R VALUES (PG 14, 27)
189/ REMOVED C195 - 1.5V AGP(DOUBLED BYPASS), C24,C20 - 3VMAIN (DOUBLED BYPASS) FOR TESTPOINTS (PG 17) 307/ CONSOLIDATED 1UF, 10% CAPS TO 1UF, 20% CAPS (PG 28,31)
190/ REMOVED C91 - 1.5V AGP BULK CAP BECAUSE THERE ARE 4 ON INTREPID SIDE ALREADY! (PG 20)
C 191/
192/
CHANGED STUFFING OPTION TO FORCE 14V INTO FORCE CONTINUOUS MODE TO REDUCE INDUCTOR SINGING (PG 31)
CHANGED STUFFING OPTION TO RAISE MARVELL CORE VOLTAGE TO 1.32V (PG 27)
308/
309/
310/
CHANGED CURRENT LIMIT SETTINGS FOR 1.5V AND 2.5V SWITCHER (PG 35)
ADDED FOUR PULL-DOWN RESISTORS ON CKE FOR DDR MEMORY (PG 10)
ADDED THREE 0402 CAP PADS ON SND_SCLK, SND_CLKOUT, AND LVDS_DDC_CLK FOR EMI (PG 22, 25)
C
193/ REMOVED COMMON MODE CHOKE FOR FIREWIRE B SIGNALS (PG 28) 311/ ADDED 5 SPEAKER CLIPS SYMBOLS (PG 4)
194/ CHANGED LINE_WIDTH FOR FIREWIRE SIGNALS TO MAKE THEM 55OHM SINGLE AND 110OHM DIFFERENTIAL (PG 36) 312/ CHANGED VCORE OFFSET TO 10MV -> EVT BOARD MEASURED: IDLE 1.407V, SMOKE 1.387V, TRANSIENT 1.37V (PG 34)
195/ CHANGED STUFFING OPTION TO ENABLE 1.5V_LDO AND MAKE 1.5V_MAIN INTO 1.8V (PG 16, 19, 34) 313/ ADDED RESISTOR TO TPS2211 SHUTDOWN# PIN TO SUPPORT PSUEDO-D3COLD (PG 18)
196/ ADDED BACK IN COMMON MODE CHOKE FOR FIREWIRE B TO ENSURE TESTABILITY (PG 28)
RELEASED FOR PROTO 2 RELEASED FOR PROTO 2 RELEASED FOR DVT RELEASED FOR DVT
LAST MINUTE BOM CHANGES FOR DVT (12/20/02)
LAST MINUTE BOM CHANGES FOR PROTO2 (9/5/02) 314/ CHANGED CPU VCORE TO 1.32V@1GHZ AND 1.15V@667MHZ (PG 34)
197/ STUFFED 20K FEEDBACK RESISTOR FOR MARVELL 88E1111 CRYSTAL (PG 27) 315/ CHANGED STUFFING OPTION TO ENABLE PCI SPREADING (PG 9)
198/ NO STUFFED 4700PF FOR 14V PBUS GATE - C741 (PG 31) 316/ CHANGED STUFFING OPTION FOR A/B* SELECT ON MAX1717 TO SUPPORT L3 AT SLOW SPEED (PG 34)
199/ NO STUFFED L4 AND L5, FIREWIRE COMMON MODE CHOKES (PG 28) 317/ NO STUFFED R694 AND STUFFED R727 TO RESTOR ORIGINAL VCORE STEPPING CONTROL (PG 34)
200/ CHANGED BOOTROM APN FOR SHARP DIE-SHRINK PACAKGE (PG 10) 318/ CHANGED RP55 AND RP56 TO 22OHM RPAKS (PG 21)
201/ CHANGED VCORE STUFFING OPTION FOR 1GHZ PROCESSOR (PG 33) 319/ CHANGED R664 FROM 0OHM TO 10K BECAUSE IT SHOULD BE A WEAK PULL-DOWN (PG 24)
REV 3.0 - 09/20/02 REV A - 01/14/03
202/ COMBINED FIREWIRE FUSE INTO ONE TO LIMIT PORT POWER TO 22W@24V OR 13.5W@15V (PG 28)
203/ UPDATED L3 SYMBOLS TO REFLECT MISSING SA17 SIGNAL ON 4MBIT PARTS VS. 8MBIT PARTS (PG 8) 320/ REMOVED LTC4210 BECAUSE OF RELIABILITY ISSUES, AND UPDATED PORT CONTROL WITH OLD METHOD PLUS A NEW 1.5A FUSE (PG 29)
204/ CHANGED TO NEW SPIDEY CONNECTOR AND PINOUT (PG 23) 321/ MOVED AMP AND HP MUTE CONTROL FROM TUBA TO MLB, AND INT_PU_RESET_L IS NOW "AND"ED WITH THE SIGNALS (PG 25)
205/ REMOVED P93 SUPPORT CIRCUIT (PG 25) 322/ CHANGED ZT10 TO THE NEW PD STANDOFF, BS1 (PG 4)
206/ ADDED 0 OHM RESISTOR FOR 2.5V_MARVELL TO MEASURE CURRENT (PG 27) 323/ REMOVED ALL JUMPERS FOR PRODUCTION (PG TOO MANY)
207/ ADDED 0 OHM RESISTOR FOR POWER BUTTON - DEBUG (PG 25) 324/ CHANGED R152 TO 511 OHM, 1% TO AVOID LOW CPU CLOCK AMPLITUDE (PG 9)
208/ ADDED 2 JUMPERS FOR PMU_RESET_BUTTON_L AND PMU_NMI_BUTTON_L (PG 25) 325/ CHANGED R451 TO 10K FROM 100K (PG 23) - OTHERWISE, IT MAY BE TOO WEAK
209/ CHANGED TO PROTO2 BOM OPTION - INTREPID REV 2.0, AND MARVELL 2.0 CHANGES 326/ REMOVED R621 AND CONNECTED R608 TO GROUND WITH 10K RESISTOR TO ENSURE KBD LED IS OFF WHEN LMU IS IN RESET (PG 23)
327/ SWAPPED R265 AND R653 VALUES BECAUSE BATTERY VOLTAGE CAN GO DOWN TO 10.4V, AND WE NEED TO ENSURE VGS<-4.5V (PG 29)
RELEASED FOR PROTO 2-ENCLOSURE RELEASED FOR PROTO 2-ENCLOSURE 328/ UPDATED TO NEW S-VIDEO FILTER VALUES (PG 22)
LAST MINUTE BOM CHANGES FOR PROTO2-ENCLOSURE (9/25/02) 329/ ADDED ONE MORE SPEAKER CLIP FOR PD (PG 4)
210/ CHANGED R474 TO 49.9K, 1%, R475 TO 1.0K, 1%, AND R683 TO 10.7K, 1% (PG 30) 330/ SWITCHED FAN TACH AND GROUND ON CONNECTOR FOR PD (PG 25)
211/ CHANGED INTRPEID PART NUMBER TO REV 2.0 (PG 9-16) 331/ CHANGED TO 33OHM RPAKS FOR TMDS (PG 21)
332/ REMOVED U1 BECAUSE NO USING 1.5V MAXBUS NOR 1.5V L3 INTERFACE STRAPS (PG 7)
REV 4.0 - 10/24/02
212/ ADDED 10K PULL-UP STUFFING OPTION TO CG_ADDRSEL AND 10K PULL-DOWN STUFFING OPTION TO CG_FSEL (PG 15) RELEASED FOR DVT2 RELEASED FOR DVT2
213/ REMOVED ZEBRA 15/16 SUPPORT (PG 28) LAST MINUTE BOM CHANGES FOR DVT2 (1/18/03)
214/ REMOVED NO_TEST=TRUE PROPERTY ON MAXBUS/L3 BUS (PG 35)
B 215/
216/
ADDED FUNCTIONAL TEST POINT DEFINITION (PG 38)
REPLACED IRF7822 IN THE BATTERY CHARGER AND 14V SWITCHER SECTION WITH IRF7811W (PG 30, 31)
333/ CHANGED INPUT CAPS FOR CPU_VCORE FROM 4.7UF CERAMIC CAPS TO 22UF POSCAPS (PG 34)
334/ CHANGED R439 FROM 100K PULL-UP TO 47OHM SERIES CONNECTED TO IO_RESET_L - MAKING SURE LMU RESETS ACROSS RESTART (PG 23)
B
217/ DELETED CAPACITOR OPTION ON INT_CPUFB_IN - MAKE RISE/FALL TIME WORSE (PG 9) 335/ CHANGED SCHEMATIC NUMBER TO 051-6425 AND PCB NUMBER TO 820-1502 (PG 1)
218/ CHANGED POWER SUPPLY TO FAN TO +3V_SLEEP (PG 25)
219/ UPDATED TO NEW EMI SHIELD PART NUMBER, AND NEW 300MHZ SRAM PART NUMBER (PG 4, 8)
220/ SWITCHED TO NEW 16PIN MODEM CONNECTOR (PG 25) ANOTHER LAST MINUTE BOM CHANGES FOR DVT2 (1/24/03)
221/ FIXED AGP CLOCK CONSTRAINTS (PG 13,35)
222/ DELETED PULL-UP RESISTOR TO VCORE_VCC ON VGATE SINCE THERE’S A 10K PULL-UP RESISTOR ON INTREPID SIDE (PG 33) 336/ CHANGE R389 TO 20K AND R395 TO 47K TO ENABLE BURST MODE OPERATION ON LTC3707 (PG 33)
223/ ADDED BACK INDIVIDUAL FUSE FOR FIREWIRE PORT (PG 28) 337/ RP55 AND RP56 CHANGED TO 22OHM AND L17 CHANGED TO 370OHM COMMON MODE CHOKE (PG 21)
224/ SEPARATED FW PORTS TO ANOTHER PAGE; UPDATED PIN DEFINTIONS (PG 28, 29)
225/ ADDED 2 10K PULL-UP TO USB NC PINS (M6 AND P6) - PER NEC (PG 26)
226/ CHANGED SMBUS PULL-UP RESISTOR TO 7.15K (DON’T HAVE ANOTHER 5% ~7K RESISTOR IN BOM) - PER IBOOK (PG 30)
227/ DELETED ALL INTREPID_REV1 STUFFING OPTION (PG 9-16) RELEASED FOR PVT RELEASED FOR PVT
228/ CHANGED TO NEW MOUNTING HOLE SIZES - ALL INCREASED BY 0.2MM IN DIAMETER EXCEPT FOR THREE CPU MTG HOLES (PG 4) REV A (051-6442) - 02/28/03
229/ CHANGED BOM OPTION TO 167MHZ BUS WITH PLL SET TO 1GHZ/833MHZ (PG 7,9) 338/ BOM OMITTED SANYO CAPS AND ADDED KEMET 10UF AND PANASONIC 8.2UF AL POLYMER CAPS AT 7 LOCATIONS (PG 34)
230/ CHANGED TO 10K PULL-DOWN FOR MOD_DTI, MOD_SYNC, AND MOD_BITCLK - PER INTREPID PADS SPREADSHEET (PG 14) 339/ CHANGED R8 AND R70 TO 4.7K INSTEAD OF 10K TO IMPROVE RISE/FALL TIME (PG 15)
231/ CHANGED JUMPER PADS FOR PMU_RESET_L AND PMU_NMI_L TO 0603 RESISTOR PADS (PG 25) 340/ CHANGED SCHEMATIC NUMBER TO 051-6442 (PG 1)
232/ ADDED DAMPING RESISTOR FOR 8MHZ CRYSTAL (PG 23) 341/ UPDATED SYMBOL FOR U28 - FIREWIRE A PHY (PG 28)
233/ CHANGED INT_PLL_EN_PD TO PULL-DOWN AND CHANGED JTAG_ENET_TDI TO PULL-UP (PG 14) 342/ UPDATED SYMBOL FOR D22,D26,D29,D31,AND D33 - TO CORRECT SCHOTTKY DIODE SYMBOL (PG 29,31-33)
234/ DISCONNECTED FW_LKON FROM INT_EXTINT3_PU BECAUSE FW_LKON OUTPUT NOW WORKS FINE (PG 15) 343/ CHANGED C263 FROM 0.01UF TO 0.22UF TO FIX EXTERNAL BRIGHTNESS FLUCTUATION ON CRT (PG 21)
235/ CHANGED R21 TO +3V_SLEEP TO PREVENT LEAKAGE TO MAXBUS_SLEEP BEFORE LMU SETS OUTPUT AS OPEN-DRAIN (PG 23) 344/ CHANGED Q60 TO NEW SYMBOL WITH ONLY IRF ON AVL (PG 31)
236/ CHANGED FW_PD AND FW_PU TO 5% RESISTORS (PG 28)
237/ ADDED FIREWIRE PORT CURRENT LIMITER (PG 29)
238/ CHANGED +14V_PBUS TO +PBUS SINCE THE VOLTAGE MAY CHANGE BACK AND FORTH (PG ALL) RELEASED FOR PRODUCTION RELEASED FOR PRODUCTION
239/
240/
ADDED A29 ADAPTER DETECT (PG 30)
ADDED NEW SYSTEM CURRENT MONITOR FOR +PBUS (PG 31)
REV B (051-6442) - 03/06/03
241/ DELETED OLD BATTERY CURRENT LIMITER CIRCUIT (PG 31) 345/ UPDATED FIREWIRE PHY TO NEW "REV A" PART NUMBER (PG 28)
242/ ADDED C843 TO SPEED UP Q10 TURN ON AND CHANGED Q14 TURN ON TO AC_IN (PG 31) 346/ UPDATED BOOT ROM TO NEW "REV A" PART NUMBER (PG 10)
243/ REMOVED C650 (2MILLOHM) SENSE RESISTOR FROM CPU_VCORE SWITCHER BECAUSE IT CAUSES TOO MUCH DROOP ON VOLTAGE (PG 34) 347/ CHANGED C550 TO NEW APN 138S0536 - ONLY TAIYO YUDEN APPROVED DUE TO MAX 1.9MM HEIGHT REQUIREMENT (PG 30)
244/ REPLACED LMC6462 WITH LMC7111 BECAUSE ONLY NEED 1 OP-AMP (PG 31) 348/ CHANGED ALL 14 4.7UF, 1210, X7R CAP FROM 138S0501 TO 138S0531 (4.7UF, 1206, X5R) DUE TO MAX 1.9MM HEIGHT REQUIREMENT
245/ CHANGED LTC4210 TIMER CAPACITOR TO ONE 0805 INSTEAD OF TWO 0402 (PG 29)
246/ FINALIZED ALL POWER SUPPLY CHANGES (PG 29-32)
247/ CHANGED TO NEW CALIFORNIA MICRO DEVICES LOW-CAPACITANCE ESD DIODES FOR FIREWIRE (PG 29) BOM UPDATE FOR PRODUCTION BOM UPDATE FOR PRODUCTION
248/ ADDED 1K PULL-DOWN TO FW_DS1, FW_SE, AND FW_SM INPUTS PER TI’S RECOMMENDATION (PG 28) REV A (051-6469) - 04/09/03
A 249/
250/
CHANGED DS1 (PIN 32) TO PULL-UP FOR A-ONLY OPERATION (PG 28)
ADDED MORE FUNCTIONAL TEST POINTS PER WAYNE’S INPUT (PG 39) 349/ UPDATED SCHEMATIC NUMBER TO 051-6469 (PG 1)
350/ CHANGED C591 AND C595 TO 0.01UF TO SPEED UP 1.95V_DVDD AND 1.95V_PLLVDD RAMP TIME (PG 28) NOTICE OF PROPRIETARY PROPERTY
A
251/ CHANGED BACK TO OLD BAV99DW DIODES BECAUSE CMD1210 CAN ONLY HANDLE 8MA FORWARD CURRENT (PG 29)
252/ REMOVED COMMON MODE CHOKE PADS FOR FIREWIRE B (PG 29)
253/ ADDED PULL-UP TO PMU_SLEEP_LED_L AND CHANGED R451 TO PULL-DOWN SLEEP_LED_H TO ENSURE STATES WHEN CHIPS TRISTATE OUTPUTS (PG 23) THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
254/ ADDED SILICON IMAGE SI1162 - FIRST PASS (PG 21) BOM UPDATE FOR PRODUCTION BOM UPDATE FOR PRODUCTION PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
255/ UPDATED DVI_HPD CIRCUIT PER HYDRA IMPLEMENTATION (PG 22)
256/ REPINNED OUT TUBA CONNECTOR (PG 25) REV B (051-6469) - 04/25/03 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
257/ SWAPPED JTAG_CPU_TRST_L AND JTAG_CPU_TDI WITH SENSOR5_I2C*_PD BECAUSE 200OHM PULL-DOWN PREVENTS IN-CIRCUIT PROGRAMMING ON PA0 351/ CHANGED D31 FROM MBRS140T3 TO BS240 TO INCREASE THE CONSTANT CURRENT CAPABILITY FROM 1A TO 2A (PG 29) II NOT TO REPRODUCE OR COPY IT
258/ REMOVED XW17 - CPU_VCORE_JUMPER - FOR HUGE COPPER POUR (PG 34) 352/ CHANGED C720 TO SANYO ONLY PART BECAUSE OF PROBLEMS AT THE FACTORY/FIELD (PG 1) III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
259/ ADDED PART NUMBER TABLE FOR SPEAKER CLIP (PG 4)
260/ MIRRORED AIRPORT CONNECTOR BECAUSE CONNECTIONS ARE MIRRORED ON THE FLEX (PG 24) SIZE DRAWING NUMBER REV.
261/ FINALIZED ALL CHANGES FOR SI1162 PART - RUNNING HIGH SWING MODE (PG 21) BOM UPDATE FOR PRODUCTION BOM UPDATE FOR PRODUCTION
262/ CHANGED TO SI3446DV FOR FAN FETS (PG 25) REV C (051-6469) - 06/05/03 D 051-6469 F
APPLE COMPUTER INC.
353/ CHANGED CPU P/N TO 337S2775 FOR THE SICOH PROCESSORS (PG 5,6) SCALE SHT OF
354/ CHANGED L31 FROM 152S0036 TO 152S0125 (PG 34)
355/ CHANGED L32 FROM 152S1003 TO 152S0126 (PG 32) NONE 40 44
8 7 6 5 4 3 2 1
CR-41
8 7 6 5 4 3 2 1
*** Signal Cross-Reference *** 1625_INTVCC 32C5 38D1 CG_RESET_L 15B7 EIDE_OPTICAL_DATA<15..0> 24A5 24A6 24B7 24C7 24D7 GPU_VIPD2_ROMTYPE<1..1> 19C2 21A8 LTC3405_SW 27D4 38B3 RAM_CAS_L 10A4 12B5 12B6 36A5
--- for the entire design -- 1625_RUNSS 32C6 CHARGE_DISABLE 31A7 37B5 39B4 39C4 GPU_VIPD3_PCI_DEVID<2..2> 19C2 21A8 LTC3411_GND 35A5 38A1 RAM_CKE<3..0> 10A3 10C4 12B6 12B8 12C3 12C5 36A5
1625_SGND 32B7 38D1 CHARGE_LED_L 30C6 30D7 31D8 39D2 EIDE_OPTICAL_DMAACK_L 24A6 24A7 37A5 39A4 GPU_VIPD4_PCI_DEVID<0..0> 19C2 21A8 LTC3411_ITH 35A5 38A1 RAM_CS_L<3..0> 10C4 12B3 12B5 12B6 12B8 36A5
+1_0V_MARVELL 27D2 38B3 1625_TG 32C5 CHGND1 38A6 EIDE_OPTICAL_DMA_RQ 24A6 24B7 37A5 39A4 GPU_VIPD5_PCI_DEVID<1..1> 19C2 21A8 LTC3411_ITH_RC 35A5 38A1 RAM_DATA_A<63..0> 11B2 11B4 11B6 11B8 11C1 11C2
+1_5V_AGP 13C5 13D1 13D4 16D5 17C8 19A2 19A8 1625_VFB 32B5 CHGND2 38A6 EIDE_OPTICAL_INT 24A5 24A7 37A5 39D4 GPU_VIPD6_CRYSTAL<1..1> 19C2 21B8 LTC3411_SHDN 35A6 38A1 11C3 11C4 11C5 11C6 11C7 11C8 11D1
19C6 19D5 20D8 38C3 1625_VIN 32C6 38D1 CHGND3 38A6 EIDE_OPTICAL_IOCHRDY 24A5 24A7 37A5 39D4 GPU_VIPD7_TP 19C2 LTC3411_SYNC 35A6 38A1 11D3 12A6 12A8 12B6 12B8 12C6 12C8
+1_5V_INTREPID_PLL 9D6 13D4 13D8 15D6 38D3 1625_VSW 32C4 38D1 CHGND4 38A6 EIDE_OPTICAL_RD_L 24A6 24A7 37B5 39A4 GPU_VIPHAD0_TP 19C2 LTC3411_VCC 35A6 38B1 12D6 12D8 36A5 36B5 36C5
+1_5V_INTREPID_PLL1 15C3 38D3 1772_ACIN 31B5 CHGND5 38A6 EIDE_OPTICAL_RST_L 24A7 24B5 37A5 39D4 GPU_VIPHAD1_TP 19C2 LTC3707_START_RC 33B6 RAM_DATA_B<63..0> 11C2 11C4 11C6 11C8 11D2 11D4
+1_5V_INTREPID_PLL2 15D3 38D3 1772_ACOK_L 31B5 31C4 CHGND6 38A6 EIDE_OPTICAL_WR_L 24A5 24A7 37A5 39D4 GPU_VIPHCLK_TP 19C2 LVDS_DDC_CLK 20C2 22B5 39A7 12A3 12A5 12B3 12B5 12C3 12C5 12D3
+1_5V_INTREPID_PLL3 15D3 38D3 1772_BST 31B4 CLK10M_PMU_XIN 30B6 EIDE_RD_L 14A7 24A8 37B5 GPU_VIPHTCL_TP 19C2 LVDS_DDC_DATA 20C2 22B5 39A7 12D5 36A5 36B5 36C5
+1_5V_INTREPID_PLL4 15D3 38D3 1772_BST_ESR 31C3 CLK10M_PMU_XOUT 30B6 EIDE_RST_L 14B7 24A8 37B5 GPU_VSYNC 21D5 LVDS_L0N 20C2 22B4 37C2 39C7 RAM_DQM_A<7..0> 11B2 11B4 11B6 11B8 11C1 11C3 11C5
+1_5V_INTREPID_PLL5 13D3 38D3 1772_CCI 31B5 CLK10M_PMU_XOUT_UF 30B7 EIDE_WR_L 14A7 24A8 37B5 GPU_XOR_TESTMODE_ENABLE 20A4 LVDS_L0P 20C2 22B4 37C2 39C7 11C7 12A6 12B6 12C6 12D6 36A5 36B5
+1_5V_INTREPID_PLL6 13D6 38D3 1772_CCS 31B5 CLK18M_INT_EXT 15A6 36B1 ENET_COL 14C5 27B7 37A5 GPU_Y 21C6 22B8 LVDS_L1N 20C2 22B4 37C2 39C7 36C5
+1_5V_INTREPID_PLL7 9D5 38D3 1772_CCV 31B5 CLK18M_INT_XIN 15A5 36B1 ENET_COMA 27B7 HD_ADDR<2..0> 24B3 24C1 24C2 24C3 37C5 LVDS_L1P 20C2 22B4 37C2 39C7 RAM_DQM_B<7..0> 11C2 11C4 11C6 11C8 12A5 12B5 12C5
+1_5V_INTREPID_PLL8 15D3 38C3 1772_CCV_RC 31B5 CLK18M_INT_XOUT 15A5 36B1 ENET_CRS 14C5 27B7 37A5 HD_CS0_L 24C2 24C3 37B5 LVDS_L2N 20C2 22B4 37C2 39C7 12D5 36A5 36B5 36C5
+1_5V_LDO 16B1 19A3 35D8 38D6 1772_CELLS 31B4 CLK18M_XTAL_IN 15A5 36B1 ENET_CTAP_CHGND 27A1 38A6 HD_CS1_L 24B3 24C1 37B5 LVDS_L2P 20C2 22B4 37C2 39C7 RAM_DQS_A<7..0> 11B2 11B4 11B6 11B8 11C1 11C3 11C5
+1_5V_MAIN 38D6 1772_CLS 31A4 CLK25M_ENET_XIN 27A7 36B1 ENET_ENERGY_DET 15B5 27B7 HD_DATA<15..0> 24B3 24C1 24C2 24C3 24D1 24D2 24D3 LVDS_L3N_SPN 20C2 11C7 12A8 12B8 12C8 12D8 36A5 36B5
+1_5V_SLEEP 38D6 1772_CSIN 31B4 37A2 CLK25M_ENET_XOUT 27A7 36B1 ENET_HSDACM 27A7 37C5 LVDS_L3P_SPN 20C2 36C5
D
+1_5V_SLEEP_VIN 35D8
+1_8V_MAIN
+1_8V_SLEEP
38D6
38D6
38D6
39A2
1772_CSIP
1772_CSSN
1772_CSSP
31B4
31C5
31C5
37A2
37A2
37A2
CLK25M_XTAL_IN 27A7
CLK27M_GPU_XIN 21B4 36B1
CLK27M_GPU_XOUT 21B4 36B1
ENET_HSDACP 27A7
ENET_LINK_RXD<7..0> 14C5 27B7 27C7 37A5
ENET_LINK_TXD<7..0> 14A4 14B4 14D5 37A5
HD_DIOR_L
HD_DIOW_L
HD_DMACK_L
24A3 24C2 37B5
24A3 24C1 37B5
24A3 24C2 37B5
LVDS_U0N
LVDS_U0P
LVDS_U1N
20C2
20C2
20C2
22A4
22A4
22A4
37C2
37C2
37C2
39B7
39B7
39B7
RAM_DQS_B<7..0> 11C2 11C4 11C6 11C8 12A3 12B3 12C3
RAM_MUXSEL_H
12D3 36A5 36B5 36C5
11A3 11A5 11B1 11B3 36A5
D
+1_95V_FW_DVDD 28C4 28C7 28D5 38A3 1772_DCIN 31B5 38C6 CLK27M_XTAL_IN 21B4 36B1 ENET_LINK_TX_EN 14D5 37A5 HD_DMARQ 14C6 24C2 37B5 LVDS_U1P 20B2 22A4 37C2 39B7 RAM_MUXSEL_L 11A3 11A5 11B5 11B7 36A5
+1_95V_FW_DVDD_PORT1 28D6 38A3 1772_DHI 31B4 CLK32K_PMU_XIN 30B3 ENET_LINK_TX_ER 14D5 37A5 HD_INTRQ 14C6 24C1 37B5 LVDS_U2N 20B2 22A4 37B2 39B7 RAM_RAS_L 10A4 12B5 12B6 36A5
+1_95V_FW_DVDD_RX0 28C5 38A3 1772_DLO 31B4 CLK32K_PMU_XOUT 30B3 ENET_MDC 14C5 27B7 37A5 HD_IOCHRDY 24A3 24C1 37B5 LVDS_U2P 20B2 22A4 37B2 39B7 RAM_WE_L 10A4 12B3 12B8 36A5
+1_95V_FW_DVDD_TX0 28C5 38A3 1772_DLOV 31B4 38C6 CLK32K_PMU_XOUT_UF 30B2 ENET_MDIO 14C5 27B7 37A5 HD_RESET_L 24A3 24D2 37B5 LVDS_U3N_SPN 20B2 RF_DISABLE_L_SPN 24D6 39C1
+1_95V_FW_PLL400VDD 28D5 38A3 1772_GND 31A5 38C6 CLK33M_AIRPORT 13D8 24D5 36C1 39B1 ENET_PHY_TXD<7..0> 14A5 14B5 27C7 37A5 HIGH_VCORE 20B5 LVDS_U3P_SPN 20B2 RIGHT_USB_DM 26A3 32A7 37A2 39D1
+1_95V_FW_PLL500VDD 28D5 38A3 1772_ICHG 31B5 CLK33M_AIRPORT_UF 13C7 36C1 ENET_PHY_TX_EN 14D6 27C7 37A5 HPD_4V_REF 22C3 MAIN_RESET_L 18A7 18D5 19B8 21C3 24D6 26B8 30D4 RIGHT_USB_DP 26A3 32A7 37A2 39D1
+1_95V_FW_PLLVDD 28D5 28D7 38A3 1772_ICTL 31B5 CLK33M_CBUS 13D8 18A7 36C1 ENET_PHY_TX_ER 14D6 27C7 37A5 HPD_BASE 22C1 30D7 39C1 RJ45_C0_PD 27B2
+2_5V_CG_MAIN 15C6 38A3 1772_IINP 31B5 CLK33M_CBUS_UF 13C7 36C1 ENET_RSET 27A5 HPD_ON 22C2 MAX1715_GND 35B5 35C5 38C1 RJ45_C1_PD 27B2
+2_5V_GPU_FB 19A4 19A5 19B4 19B5 19C2 19D2 19D5 1772_LDO 31C4 38C6 CLK33M_USB2 13C8 26B7 36C1 ENET_RST_L 27B7 HPD_ON_RC 22C2 MAX1715_ON_RC 35C7 RJ45_C2_PD 27B2
38C3 1772_LX 31B4 38C6 CLK33M_USB2_UF 13C7 36C1 ENET_RX_DV 14D5 27B7 37A5 HPD_PWR_SNS_EN 20C4 22C3 MAX1715_REF 35B5 38C1 RJ45_C3_PD 27B2
+2_5V_INTREPID 10A8 11D3 11D5 11D6 11D8 16D7 17B8 1772_REF 31B5 CLK66M_AGP_15V_TP 13C4 ENET_RX_ER 14C5 27B7 37A5 HPD_PWR_SW 22C2 MAX1715_SKIP 35C4 38C1 RJ45_DN<3..0> 27B2 37D2 39A3 39B3
38D3 1772_VCTL 31B5 CLK66M_GPU_AGP 13C8 19B7 36C1 ENET_VSSC 27A7 HP_CONTROL 25C5 MAX1715_TON 35C5 38C1 RJ45_DP<3..0> 27B2 37D2 39A3 39B3
+2_5V_MAIN 38D6 1778_BG 20B7 38B1 CLK66M_GPU_AGP_UF 13C7 36C1 FAN1_GND 25B3 38B6 39B3 IAC_FB 31D4 MAX1715_VCC 35D5 38C1 ROM_CS_L 10B3 13A5 24B6 39B1
+2_5V_MARVELL 27B8 27C4 38B3 1778_BST 20B7 38B1 CLKENET_LINK_GBE_REF 14C5 27C8 36B1 FAN1_PWM 25B3 IAC_RC_COMP 31D4 MAX1717_AB_SEL 34C6 ROM_OE_L 10B3 13A5 24C5 39B1
+2_5V_MARVELL_AVDD 27C4 38B3 1778_BST_RC 20C6 38B1 CLKENET_LINK_GTX 14C5 36A1 FAN1_TACH 25B3 39B3 INTREPID_ACS_REF 9A6 MAX4172_OUT 31D4 ROM_ONBOARD_CS_L 10B3 24C6 39B1
+2_5V_SLEEP 16D7 38D6 1778_FCB 20B7 38B1 CLKENET_LINK_RX 14D5 27C8 36B1 FAN2_GND 25A4 38B6 39B3 INT_AGPPVT 13D4 MAXBUS_SLEEP 5A2 5D2 5D5 7A8 7D7 9B8 9C3 9C8 9D1 ROM_RW_L 10B3 13A5 24C6 39B1
+2_8V_IFP_PLLVDD 20A2 20A4 20A5 38C3 1778_GND 20B6 20B8 38B1 CLKENET_LINK_TX 14D5 27D8 36A1 FAN2_PWM 25A4 25B3 INT_AGP_FB_IN 13C4 36C1 9D8 16D8 17D8 23B3 34D8 38D3 ROM_WP_L 10B3
+3V_CG_PLL_MAIN 15C6 38A3 1778_ION 20B7 38B1 CLKENET_PHY_GBE_REF 27C7 36B1 FAN2_TACH 25A4 25B3 39B3 INT_AGP_FB_OUT 13C4 36C1 MDI0_PD 27B4 RUN_OR_AC 29C6
+3V_DAC1VDD 21D4 38C3 1778_ITH 20B7 38B1 CLKENET_PHY_GTX 14C6 27C7 36A1 FB_4_85V_BU 32A5 INT_AGP_VREF 13B4 13D4 38C3 MDI1_PD 27B4 SI_DK<1..0> 21C3
+3V_DAC2VDD 21D7 38C3 1778_ITH_RC 20B8 38B1 CLKENET_PHY_RX 27C7 36B1 FP_PWR_EN 20C4 22A6 22B3 INT_AUDIO_TO_SND 15B2 25C6 39C6 MDI2_PD 27B4 SI_EDGE 21C3
+3V_FW 28A3 28D7 29D5 38B3 1778_SHDN_L 20B7 CLKENET_PHY_TX 27D7 36B1 FP_PWR_EN_L 22B3 INT_CPUFB_IN 9A6 9B6 36D1 MDI3_PD 27B3 SI_EXT_SWING_SET 21C1
+3V_FW_AVDD 28C6 38A3 1778_SHDN_L_D3COLD 20D7 CLKFW_LINK_LCLK 14C3 36A1 FWB_TPB0 28A3 INT_CPUFB_IN_NORM 9A4 36D1 MDI_M<3..0> 27B5 37D2 SI_I2C_OFF 21C3
+3V_FW_AVDD_PORT0 28C6 38B3 1778_TG 20B7 38B1 CLKFW_LINK_PCLK 14C3 28C3 36A1 FWB_TPB1 28A4 INT_CPUFB_LONG 9A4 36D1 MDI_P<3..0> 27B5 37D2 SI_TMDS_CLKN 21A2 21B3 21C1
+3V_FW_AVDD_PORT1 28C6 38B3 1778_VCC 20C7 38B1 CLKFW_PHY_LCLK 14C2 28B7 36A1 FWPLL_BYP 28C8 INT_CPUFB_OUT 9A6 36D1 MEM_ADDR<12..0> 10A5 10B5 10D6 36A5 SI_TMDS_CLKP 21A2 21B3 21C1
+3V_FW_AVDD_PORT2 28D6 38B3 1778_VFB 20B7 38B1 CLKFW_PHY_PCLK 28B5 28C4 36A1 FW_BIAS0 28A5 INT_CPUFB_OUT_NORM 9A4 36D1 MEM_BA<1..0> 10A5 10C6 10D6 36A5 SI_TMDS_DN<2..0> 21A2 21B3 21C1
+3V_FW_ESD 29B3 29D2 38B3 1778_VIN 20C7 38B1 CLKLVDS_LN 20C2 22A4 37C2 39B7 FW_BIAS1 28A5 INT_CPUFB_OUT_SHORT 9A5 36D1 MEM_CAL_CLK 19B2 SI_TMDS_DP<2..0> 21A2 21B3 21C1
+3V_FW_ESD_ILIM 29D4 38B3 1778_VRNG 20B7 38B1 CLKLVDS_LP 20C2 22A4 37C2 39B7 FW_BMODE 28B7 INT_DDRCLK2_N_TP 10B6 MEM_CAL_PD 19B2 SLEEP 23C4 30B6 30D7 33A5 33A6 33B3 35B3
+3V_FW_UF 28D7 38B3 3405_MODE 27D5 CLKLVDS_UN 20B2 22A4 37C2 39B7 FW_CORE_ADJ 28C7 INT_DDRCLK2_P_TP 10B6 MEM_CAL_PU 19B2 35D2
+3V_GPU 13D1 15C5 19A4 20A8 20B2 20B4 20C4 3405_VFB 27D4 CLKLVDS_UP 20B2 22A4 37C2 39A7 FW_CORE_BYP 28C7 INT_DDRCLK5_N_TP 10B6 MEM_CAS_L 10A5 10C6 36A5 SLEEP_LED 23C1 25C7
20D2 21B8 21C7 21C8 21D1 21D3 21D6 3707_FCB 33C5 COMM_DTR_L 15C2 25D1 39B2 FW_CPS 28B7 INT_DDRCLK5_P_TP 10B6 MEM_CKE<3..0> 10B6 10C5 36A5 SLEEP_LED_I 23D1
21D7 38C3 3707_FSET 33C5 COMM_GPIO_L 15C2 25D2 39C2 FW_INPUT_PD 28A7 INT_ENET_RST_L 15B5 27B8 MEM_CS_L<3..0> 10C5 10C6 36A5 SLEEP_LED_L 23D1
+3V_GPU_AVDD0 20B4 38C3 3707_INTVCC 33D4 38D1 COMM_RESET_L 15C5 25C3 39C4 FW_LINK_CNTL<1..0> 14C3 28C3 37A5 INT_EXTINT3_PU 15B5 15B7 MEM_DATA<63..0> 10B8 10C8 10D8 11B1 11B3 11B5 11B7 SLEEP_LED_SW_L 23C2
+3V_GPU_AVDD1 20B2 38C3 3707_SGND 33B5 38D1 COMM_RING_DET_L 15B5 15C7 25C4 30C6 39C4 FW_LINK_DATA<7..0> 14C3 14D3 28A8 28B8 37A5 INT_EXTINT8_PU 15B5 15C7 11C1 11C3 11C5 11C7 36A5 36B5 36C5 SLEEP_LED_UF 23C1
+3V_GPU_DVO 21B6 38C3 3707_STBY 33C5 COMM_RTS_L 15C2 25D1 39B2 FW_LINK_LREQ 14C3 37A5 INT_EXTINT10_PU 15A7 15B5 MEM_DQM<7..0> 10C6 11B1 11B3 11B5 11B7 11C1 11C3 SLEEP_LS5 25D8 33A3 33A8
+3V_GPU_PLLVDD 21D6 38C3 A29_CLS_ADJ 31A5 COMM_RXD 15C2 25D1 39B2 FW_LKON 14C3 28B5 INT_EXTINT11_PU 15A7 15B5 11C5 11C7 36A5 36B5 36C5 SLEEP_LS5_EN_L 33A4
+3V_GPU_SS 21A4 38C3 A29_CURRENT_ADJ 31C4 COMM_SHUTDOWN 15C5 25C3 39C4 FW_OSC 28A4 36A1 INT_EXTINT12_PU 15A7 15B5 MEM_DQS<7..0> 10C6 11B1 11B3 11B5 11B7 11C1 11C3 SLEEP_L_LS5 20D6 27A8 33A4 34C8 35D7
+3V_HALL_EFFECT 23C6 38B6 39C4 A29_DETECT 30A2 31A5 31C4 COMM_TRXC 15C2 25D2 39C2 FW_OSC_EN 28A3 INT_EXTINT13_PU 15B5 15B7 11C5 11C7 36A5 36B5 36C5 SLEEP_L_LS5_EN_L 33A5
+3V_INTREPID_USB 15C3 38D3 A29_DET_L 30A3 COMM_TXD_L 15C2 25D2 39C2 FW_PC_PD 28B7 INT_EXTINT14_PU 15B5 15C7 MEM_MUXSEL_H<1..0> 10B6 11A4 11A6 36A5 SND_AGND 25C7 38B6
+3V_LCD 22B4 38B6 AC_DIV 31C8 COMP_DISABLE 22C2 FW_PC_PU 28B7 INT_EXTINT16_PU 15A7 15B5 MEM_MUXSEL_L<1..0> 10B6 11A4 11A6 36A5 SND_AMP_MUTE 25C6
+3V_LCD_SW 22A4 38B6 AC_ENABLE_GATE 31D6 COMP_ENABLE 22C1 FW_PHY_CNTL<1..0> 28B5 28C4 37A5 INT_GPIO1_PU 15C5 15C7 34C8 MEM_RAS_L 10A5 10C6 36A5 SND_AMP_MUTE_L 15C5 25D5 39C6
+3V_MAIN 38D6 AC_ENABLE_L 31C6 COMP_RC 32C6 FW_PHY_DATA<7..0> 28A8 28B8 37A5 INT_GPIO9_PU 15A7 15B5 MEM_WE_L 10A5 10C6 36A5 SND_CLKOUT 15A1 25C6 36B1 39D6
C +3V_NEC_VDD
+3V_PMU
+3V_PMU_AVCC
26D7 38A3
38D6 39A2
30B1 30B6 30D5 38C6
AC_GTR_18V
AC_IN
AC_IN_FW_CNTL
31C4
27B8 29C7 30B3 31C5 31C7
29C7
CPU_AACK_L
CPU_ARTRY_L
5A7 9B6 9C2 36D5
CPU_ADDR<31..0> 5B7 5C7 9B6 9C6 9D6
5A7 9B6 9D2 36D5
36D5
FW_PHY_LPS
FW_PHY_LREQ
FW_PHY_PD
14C3 28B7
14C2 28B7 37A5
15C5 28B7
INT_GPIO12_PU
INT_GPIO15_PU
INT_I2C_CLK0
15B5 15B7
15B5 15B7
12A3 12A8 14C2 14C3 23D2 23D4 39B8
MLB_ALS_GAIN_SW 23C4 23C8
MLB_ALS_OP_COMP 23D7
MLB_ALS_OP_IN 23D7
SND_HP_MUTE
SND_HP_MUTE_L
25C6
15C5 25C4 39C6
SND_HP_SENSE_L 15B5 25C6 39C6
C
+3V_PMU_ESR 32A2 38C6 AC_IN_L 31C2 31C6 CPU_AVDD 5D4 38D3 FW_PHY_RESET_L 28A8 INT_I2C_CLK1 14C2 14C3 15B7 25B4 39B8 MLB_ALS_OUT 23C4 23D6 SND_HW_RESET_L 15A7 15B5 25C7 39C6
+3V_PMU_RESET 30B7 34A4 AC_IN_L_RC 31C2 CPU_BG_L 5C7 9C2 9D6 36D5 FW_PINT 14C3 28B5 37A5 INT_I2C_CLK2 15A2 25C4 25C6 39C6 MLB_ALS_OUT_FB 23D7 SND_LIN_SENSE_L 15B5 25C7 39C6
+3V_SI_AVCC 21D2 38B3 ADAPTER_DET 30A4 31D8 39C2 CPU_BR_L 5C7 9D2 9D6 36D5 FW_PLL_ADJ 28C7 INT_I2C_DATA0 12A3 12A8 14C2 14C3 23D2 23D4 39B8 MLB_PHOTODIODE 23D8 SND_SCLK 15B1 25C6 36B1 39C6
+3V_SI_PLLVCC 21D2 38B3 ADAPTER_I_REG 31D3 CPU_BUS_VSEL 5C3 7B7 FW_PORT1_SEL 28B7 INT_I2C_DATA1 14B2 14C3 15B7 25B4 39B8 MODEM_USB_DM 15B1 25C3 37A2 39B6 SND_SYNC 15B1 25C6 39D6
+3V_SI_VCC 21D2 38B3 AGP_AD<31..0> 13B2 13C2 13D2 19C7 19D7 37D5 CPU_CHKSTP_OUT_L 5B3 5C2 39D8 FW_PWREN_L 29C6 INT_I2C_DATA2 15A2 25C4 25C6 39C6 MODEM_USB_DP 15B1 25C3 37A2 39B6 SND_TO_AUDIO 15B1 25C6 39D6
+3V_SLEEP 38D6 AGP_AD_STB<1..0> 13A2 13B2 19A7 19B7 37D5 CPU_CHKS_L 5B3 5D2 FW_PWR_GATE 29D6 INT_JTAG_TEI 14C2 14C5 MPIC_CPU_INT_L 5B2 5B3 15B5 SOFT_PWR_ON_L 22D1 23A8 30A8 30C6 30D7 34A4
+4_6V_BU 32A3 33B5 38C6 AGP_AD_STB_L<1..0> 13A2 13B2 19A7 37D5 CPU_CI_L 5A7 9B6 36D5 FW_R0 28A5 INT_MEM_REF_H 10B6 38C3 NEC_AMC_TP 26A5 ST7_ICP_SEL_PD 23A2 23D6
+4_85V_ESR 32A4 38C6 AGP_BUSY_L 13C4 13D2 19A7 CPU_CLKOUT_SPN 5C3 FW_R1 28A5 INT_MEM_VREF 10A7 10B6 38C3 NEC_AVDD 26D6 38A3 ST7_KBD_LED_OUT 23A4 23C4
+4_85V_RAW 30B4 32A4 38C6 AGP_CAL_PD 19A7 CPU_CLK_EN 9A6 30C4 FW_TESTM 28A7 INT_MOD_BITCLK_PD 15A2 15A7 NEC_CRUN_L 26A7 ST7_OSC1 23D5
+5V_DDC_SLEEP 22D3 22D5 38B6 39A2 AGP_CAL_PU 19A7 CPU_DATA<63..0> 6A8 6B8 6C8 6D8 9A8 9B3 9B4 9B8 9C4 FW_TPA0N 28B1 29C4 37D2 INT_MOD_CLKOUT_PU 15A2 15B7 NEC_IDSEL 26B7 ST7_OSC2 23D5
+5V_DDC_SLEEP_UF 22D6 38B6 AGP_CBE<3..0> 13B2 19B7 19C7 37D5 9C8 9D4 9D8 36D5 FW_TPA0P 28B1 29C4 37D2 INT_MOD_DTI_PD 15A2 15A7 NEC_IO_RESET_L 26B7 ST7_PB6_PD 23B2 23C4
+5V_HD_SLEEP 24D1 33A7 38C6 AGP_DEVSEL_L 13B2 13C2 19B7 37D5 CPU_DBG_L 5C3 9A4 9C2 36D5 FW_TPA1N 28B1 29A4 37C2 INT_MOD_DTO_PU 15A2 15B7 NEC_LEFT_USB_OVERCURRENT 24B2 26C1 39D1 ST7_RESET_L 23D5
+5V_INV_SW 22B1 38B6 39D1 AGP_FRAME_L 13B2 13C2 19B7 37D5 CPU_DRDY_L 5C2 9A4 9C2 36D5 FW_TPA1P 28B1 29A4 37C2 INT_MOD_SYNC_PD 15A2 15A7 NEC_LEFT_USB_PWREN 24B2 26B5 39D1 ST7_SENSOR4_SCK_PD 23B2 23D4
+5V_INV_UF_SW 22B2 38B6 AGP_GNT_L 13C2 13D2 19B7 37D5 CPU_DRDY_L_UF 5C4 36D5 FW_TPB0N 28B5 29C4 37D2 INT_PCI_FB_IN 13C7 36C1 NEC_LEGC 26A7 ST7_SENSOR4_SDA_PD 23B2 23D4
+5V_MAIN 38D6 AGP_GPU_RESET_L 19B7 CPU_DTI<2..0> 5C3 9A4 36D5 FW_TPB0P 28B5 29C4 37D2 INT_PCI_FB_OUT 13C7 36C1 NEC_MAIN_RESET_L 26A7 26B7 ST7_SENSOR5_SCK_PU 23B2 23D4
+5V_SLEEP 38D6 AGP_IRDY_L 13B2 13C2 19B7 37D5 CPU_EDTI 5B2 5C3 FW_TPB1N 28B1 29A4 37C2 INT_PEND_PROC_INT 15A5 30C4 NEC_NANDTESTEN_TP 26A5 ST7_SENSOR5_SDA_PU 23B2 23D4
+5V_SOUND_SLEEP 25C5 25D6 38B6 AGP_NV_INT_L 15B5 19B7 CPU_EMODE0_L 5A3 7B5 FW_TPB1P 28B1 29A4 37C2 INT_PROC_SLEEP_REQ_L 15A5 30B4 NEC_NANDTESTOUT_TP 26A4 ST7_SLEEP_LED_H 23C2 23C4
+5V_TPAD_SLEEP 23C7 38B6 39C4 AGP_NV_PIPE_L 19B7 CPU_EMODE1_L 5A3 5C2 FW_TPB2_PD 28A5 INT_PU_RESET_L 14D3 25C4 25D4 30A2 30C4 NEC_NC1_TP 26B5 ST7_XTAL_IN 23C5
+12_8V_INV 22B1 38B6 39A2 AGP_NV_WBF_L 19B7 CPU_GBL_L 5A7 9B6 36D5 FW_TPI0N 37C2 INT_REF_CLK_IN 15A5 15B5 36C1 NEC_NC2_TP 26B5 STOP_AGP_L 13D2 13D4 19A7
+24V_PBUS 38D6 39B2 AGP_PAR 13B2 19B7 37D5 CPU_HIT_L 5A7 9B6 9D2 36D5 FW_TPI0P 37C2 INT_REF_CLK_OUT 15A5 15B7 36C1 NEC_OCI<5..1> 26B5 26C3 SUTRO_ALS_GAIN_SW 23C4 24B2 39C2
+ADAPTER 31D8 32B7 38D6 AGP_PIPE_L 13A2 13B2 19B8 CPU_HRESET_INV 7A5 7A7 7B5 FW_TPI1N 29A3 37C2 39D2 INT_RESET_L 10B3 14D3 30C7 30D4 NEC_PCI_INTA_L 26A7 26B7 SUTRO_ALS_OUT 23C4 24B2 39C2
+ADAPTER_ILIM 32B6 38C6 AGP_RBF_L 13A2 13C2 19B7 37D5 CPU_HRESET_L 5B3 5C2 7A5 7A8 7B4 23A2 39C8 FW_TPI1P 29A3 37C2 39D2 INT_ROM_CS_L 13A6 13C7 NEC_PCI_INTB_L 26A7 26B7 SYSCLK_CPU 5C3 9A6 36D1
+ADAPTER_OR_BATT 32A5 38C6 AGP_REQ_L 13C2 13D2 19B7 37D5 CPU_L1TSTCLK 5B2 5B3 FW_TPO0N 37C2 INT_ROM_OE_L 13A6 13C7 NEC_PCI_INTC_L 26A7 26B7 SYSCLK_CPU_UF 9A6 36D1
+ADAPTER_SENSE 31D5 38C6 AGP_SBA<7..0> 13B2 19A7 37D5 CPU_L2TSTCLK 5B3 5C2 FW_TPO0P 37C2 INT_ROM_RW_L 13A6 13C7 NEC_PCI_PERR_L 26B7 26C8 SYSCLK_DDRCLK_A0 10D4 12D8 36D1
+ADAPTER_SW 31D6 38C6 AGP_SB_STB 13B2 19A7 37D5 CPU_L3_VSEL 6C3 7A7 FW_TPO0R 29C2 38A3 39A3 INT_SND_CLKOUT 15A3 NEC_PCI_SERR_L 26B7 26C8 SYSCLK_DDRCLK_A0_L 10D4 12D8 36D1
+BATT 38D6 AGP_SB_STB_L 13A2 19A7 37D5 CPU_LSSD_MODE 5B3 5C2 FW_TPO1N 29A3 37C2 39D2 INT_SND_SCLK 15A3 NEC_PME_L 26A7 26B7 SYSCLK_DDRCLK_A0_L_UF 10B6 10D5 36D1
+BATT_14V_FUSE 31D1 38C6 AGP_ST<2..0> 13A2 19B7 CPU_MCP_L 5B3 5D2 FW_TPO1P 29A3 37C2 39D2 INT_SND_SYNC 15B3 NEC_PPON3_TP 26B5 SYSCLK_DDRCLK_A0_UF 10B6 10D5 36D1
+BATT_24V_FUSE 31B1 31D2 38C6 AGP_STOP_L 13B2 13C2 19B7 37D5 CPU_PLL_CFG<3..0> 5C3 7D3 FW_VGND0 29C2 38A3 INT_SND_TO_AUDIO 15B3 NEC_PPON4_TP 26B5 SYSCLK_DDRCLK_A1 10D4 12A6 36D1
+BATT_POS 31A4 38C6 39C3 AGP_TRDY_L 13B2 13C2 19B7 37D5 CPU_PLL_CFGEXT 5C3 7D3 FW_VGND1 29A3 38A3 INT_SUSPEND_ACK_L 9B6 30B6 NEC_PPON5_TP 26B5 SYSCLK_DDRCLK_A1_L 10D4 12A6 36D1
+BATT_RSNS 31B2 38C6 AGP_WBF_L 13A4 13B2 19B8 CPU_PLL_FS00 7C3 FW_VREG_PD 28A7 INT_SUSPEND_REQ_L 9B6 30B6 30C7 NEC_RIGHT_USB_OVERCURRENT 26C1 32A7 39C1 SYSCLK_DDRCLK_A1_L_UF 10B6 10D5 36D1
+BATT_VSNS 31A4 38C6 AIRPORT_CLKRUN_L 24C6 39C1 CPU_PLL_FS01 7C3 FW_XI 28A5 36A1 INT_TST_MONIN_PD 14C2 14C5 NEC_RIGHT_USB_PWREN 26B5 32A7 39C1 SYSCLK_DDRCLK_A1_UF 10B6 10D5 36D1
+FW_FUSE 29D7 38B3 AIRPORT_IDSEL 24C5 39B1 CPU_PLL_FS10 7C4 GAIN_SETTING2 23C7 INT_TST_MONOUT_TP 14C5 NEC_RREF 26B5 SYSCLK_DDRCLK_B0 10D4 12D3 36D1
+FW_PWR_OR 28B8 28D8 29D5 38B3 AIRPORT_PCI_GNT_L 13D7 24D5 39C4 CPU_PLL_STOP_BASE 7C7 GPU_AGP_VREF 19A7 19C5 38C3 INT_TST_PLLEN_PD 14C5 14D2 NEC_SMI_L_TP 26A7 SYSCLK_DDRCLK_B0_L 10C4 12D3 36C1
+FW_PWR_PORTA 29C5 38B3 AIRPORT_PCI_INT_L 15B5 15D7 24D5 39C4 CPU_PLL_STOP_OC 7C8 30B6 GPU_B 21C5 22D8 INT_WATCHDOG_L 15A5 30C6 NEC_USB_DAM 26B4 26C3 37B2 SYSCLK_DDRCLK_B0_L_UF 10B6 10C5 36D1
+FW_SW 29D5 38B3 AIRPORT_PCI_REQ_L 13A7 13D7 24D6 39D4 CPU_PMONIN_L 5B3 5C2 GPU_BUFRST_TP 20B2 INV_ON_PWM 20C4 22A3 NEC_USB_DAP 26A4 26C4 37B2 SYSCLK_DDRCLK_B0_UF 10B6 10D5 36D1
+FW_VP0 29C2 38B3 AIRPORT_PME_L_TP 24D5 CPU_PULLDOWN 5A2 5A3 5C7 GPU_B_FILTR 22D8 IO_RESET_L 18A7 19B8 23D6 26B8 27B8 30C6 30D7 NEC_USB_DBM 26A4 26C3 37B2 SYSCLK_DDRCLK_B1 10D4 12A5 36C1
+FW_VP1 29A3 38B3 AMP_CONTROL 25D5 CPU_PULLUP 5A3 5C2 GPU_C 21C6 22B8 JTAG_ASIC_TCK 14C5 14D2 27A5 39D8 NEC_USB_DBP 26A4 26C3 37B2 SYSCLK_DDRCLK_B1_L 10D4 12A5 36C1
+HD_LOGIC_SLEEP 24C2 38C6 BATTV_HIGH 31B7 CPU_QACK_L 5B3 9B6 36D5 GPU_CLK27M_OUT 21A4 21B3 36C1 JTAG_ASIC_TDI 14C5 14D2 39D8 NEC_USB_RSDM1 26C5 37B2 SYSCLK_DDRCLK_B1_L_UF 10B6 10D5 36D1
+PBUS 38D6 39B2 BATTV_LOW 31B8 CPU_QREQ_L 5B3 9B6 9C2 36D5 GPU_CLK27M_UF 21B4 36C1 JTAG_ASIC_TDO_TP 27A5 39D8 NEC_USB_RSDM2 26C5 37B2 SYSCLK_DDRCLK_B1_UF 10B6 10D5 36D1
+VCC_CBUS_SW 18B1 18B2 18D3 38C3 BATT_14PBUS_EN 31C1 CPU_SHD0_L 5A7 5D2 GPU_COMP 21C6 22A8 JTAG_ASIC_TMS 14C5 14D2 27A5 39D8 NEC_USB_RSDP1 26C5 37B2 SYSCLK_LA_TP 9A6
+VPP_CBUS_SW 18B1 18B2 18D2 38C3 BATT_14V_GATE 31C1 CPU_SHD1_L 5A7 5D2 GPU_CRT2HSYNC_TP 21D6 JTAG_ASIC_TRST_L 14C2 14C5 27A5 39D8 NEC_USB_RSDP2 26C5 37B2 SYSTEM_CLK_EN 15A5 15B7 15C7 30C4
B 1V20_REF
1V65_REF
1_5V_2_5V_OK
31C7
31A5
20C8
32C8 38D1
35C5 38B1
BATT_24PBUS_EN
BATT_24V_GATE
BATT_CLK
31C2
31C2
31A4 39C3
CPU_SMI_L
CPU_SRESET_L
CPU_SRWX_L
5B3 5C2 30C4
5B2 5B3 39C8
5A3 5C2
GPU_CRT2VSYNC_TP 21D6
GPU_DACVREF1
GPU_DACVREF2
21C5
21C6
JTAG_CPU_TCK
JTAG_CPU_TDI
5B2 5C3 23B2 39C8
5B2 5C3 23D4 39C8
JTAG_CPU_TDO_TP 5C3 39C8
NEC_XT1
NEC_XT2
NEC_XT2_R
26D5
26D5
26D4
36B1
36B1
THERM1_A_DM
THERM1_A_DP
THERM1_DM
25A6 25A7 37A2
25A6 25A7 37A2
25A5 25B4 25B5 37A2
B
1_5V_BOOST 35C6 38C1 BATT_DATA 31A4 39C3 CPU_TA_L 5B3 9A4 9D2 36D5 GPU_DVI_DDC_CLK 20C2 22D3 JTAG_CPU_TMS 5B2 5C3 23C4 39C8 NUMLOCK_LED 23B8 THERM1_DP 25A5 25B4 25B5 37A2
1_5V_BST 35C5 38C1 BATT_DIV 31A5 CPU_TBEN 5B3 5D2 9A6 GPU_DVI_DDC_DATA 20C2 22C3 JTAG_CPU_TRST_L 5A3 5B3 23D4 39C8 NUMLOCK_LED_L 23B8 30C7 THERM1_M_DM 25B6 25B7 37A2
1_5V_DH 35C5 38C1 BATT_LOW 31A6 CPU_TBST_L 5A7 9B6 36D5 GPU_DVOD<11..0> 21A8 21B6 21B8 21C3 21C6 37D5 JTAG_ENET_TDI 14C5 14D2 27A5 OVER_18V_ADJ 31C3 THERM1_M_DP 25B6 25B7 37A2
1_5V_DL 35B5 38C1 BATT_LOW_L 31B6 CPU_TEA_L 5B3 9A4 9C2 36D5 GPU_DVO_CLKIN 21C6 21C8 JTAG_L3_SRAM2_TDI 8C3 8C6 PCI1510_VR_EN_L 18C7 THERM2_A_DM 25A6 25A7 37A2
1_5V_FB 35B5 35B7 38C1 BATT_NEG 31A4 38C6 39C3 CPU_TSIZ<2..0> 5A7 9B6 36D5 GPU_DVO_CLKN_TP 21C6 JTAG_L3_TCK 8C3 8C6 8C7 39B8 PCI_AD<31..0> 10B3 10C1 10C3 13C6 13D6 18B7 18C7 THERM2_A_DP 25A6 25A7 37A2
1_5V_ILIM 35C5 38C1 BBANG_HRESET_L 23A4 23C4 39C1 CPU_TS_L 5C7 9D2 9D6 36D5 GPU_DVO_CLKP 21B3 21C6 36B1 JTAG_L3_TDI_TP 8C6 39C8 24B5 24B6 24C5 24C6 24D4 24D5 24D6 THERM2_DM 25A5 25B4 25B5 37A2
1_5V_LX 35B5 38C1 BBANG_JTAG_TCK 23B3 23C4 CPU_TT<4..0> 5A7 9B6 36C5 GPU_DVO_DE 21C3 21C6 JTAG_L3_TDO_TP 8C3 39B8 26B7 26C7 26C8 26D7 37C5 39A5 39A6 THERM2_DP 25A5 25B4 25B5 37A2
1_8V_SLEEP_PWREN_L 35A3 BBANG_TCK_EN 23B3 CPU_VCORE_HI_OC 7B8 30D4 34C8 34D7 GPU_DVO_HSYNC 21A8 21C3 21C6 37C5 JTAG_L3_TMS 8C3 8C6 39C8 39B5 39B6 39C5 39D5 THERM2_M_DM 25A7 25B6 37A2
1_8V_SW 35A5 38A1 BCKFD_PROT_EN_L 31C6 CPU_VCORE_PWR_SEQ 34D8 GPU_DVO_VREF 21C6 21C7 KBD_CAPSLOCK_LED 23A7 39B4 PCI_CBE<3..0> 13C7 18B7 24C5 24C6 26B7 37C5 39D4 THERM2_M_DP 25B6 25B7 37A2
1_8V_VFB 35A5 38A1 BCKFD_PROT_GATE 31D6 CPU_VCORE_SEQ 34D8 GPU_DVO_VSYNC 21C3 21C6 37C5 KBD_COMMAND_L 23A5 23A7 30C6 39B4 PCI_DEVSEL_L 13B7 13C7 18A7 24C5 26B7 37C5 39A5 THERM_L_OC 25B3 30B2 30B4
2_5V_BOOST 35C4 38D1 BRIGHT_PWM 22A1 39A7 CPU_VCORE_SEQ_L 34D8 GPU_FBACAS_TP 21B6 KBD_CONTROL_L 23A5 23A7 30A8 30C6 39B4 PCI_FRAME_L 13B7 13C7 18B7 24C5 26B7 37C5 39A5 TMDS_CLKN 20A1 21B1 21B2 22C8 37B2
2_5V_BST 35C4 38D1 BRIGHT_PWM_UF 22A2 CPU_VCORE_SLEEP 5D3 5D8 34C2 34D2 38D3 39B2 GPU_FBACKE 19B4 KBD_FUNCTION_L 23A5 23A7 30B6 39B4 PCI_IRDY_L 13B7 13C7 18B7 24C6 26B7 37C5 39A5 TMDS_CLKP 20A2 21B1 21B2 22C8 37B2
2_5V_DH 35C4 38D1 BT_USB_DM 15C1 24B2 37B2 39B6 CPU_VCORE_SNUB 34B3 GPU_FBCLK0 19B5 19C4 36B1 KBD_ID 23A7 23B5 30B6 39C4 PCI_PAR 13C7 18B7 24C5 26B7 37C5 39D4 TMDS_CLK_CMF 20B1
2_5V_DL 35B4 38D1 BT_USB_DP 15C1 24B2 37B2 39B6 CPU_WT_L 5A7 9B6 36C5 GPU_FBCLK0_L 19A5 19B4 36B1 KBD_LED1_OUT 23A5 23A7 38B6 39C2 PCI_STOP_L 13A7 13C7 18B7 24C5 26B7 37C5 39A5 TMDS_CONN_CLKN 22C7 37B2 39A8
2_5V_ILIM 35C5 38C1 CAPSLOCK_LED 23A8 CSLOT_ADDR3_SPN 14B7 GPU_FBCLK1 19A5 19B4 36B1 KBD_LED2_OUT 23A5 23A7 38B6 39C2 PCI_TRDY_L 13B7 13C7 18A7 24C5 26B7 37C5 39A5 TMDS_CONN_CLKP 22C7 37B2 39D7
2_5V_LX 35B4 38D1 CAPSLOCK_LED_L 23B8 30C7 CSLOT_ADDR4_SPN 14B7 GPU_FBCLK1_L 19A5 19B4 36B1 KBD_LED_EN 23A5 PLL_STOP_L 7C7 TMDS_D0_CMF 20D1
2_5V_SLEEP_PWREN_L 35C2 CBUS_ADDR<25..0> 18A4 18B1 18B2 18B4 18C1 CSLOT_ADDR5_SPN 14B7 GPU_FB_VREF 19B4 38C3 KBD_LED_SET 23A5 PMU_ACK_L 15C2 30C4 TMDS_D1_CMF 20C1
2_8V_ADJ1 20A7 CBUS_ADDR_16_UF 18B5 CSLOT_ADDR6_SPN 14B7 GPU_G 21C5 22D8 KBD_NUMLOCK_LED 23B7 39C3 PMU_AC_DET 30A4 30B4 TMDS_D2_CMF 20C1
2_8V_BYP 20A8 CBUS_BVD1_L 18B2 18C4 CSLOT_ADDR7_SPN 14B7 GPU_GPIO8 20C4 KBD_OPTION_L 23A5 23B7 30A8 30B6 39B4 PMU_AC_IN 30B4 TMDS_DN<2..0> 20B1 20C1 20D1 21B1 21B2 22D5 22D6
2_34V_REF 30A4 CBUS_BVD2_L 18B2 18C4 CSLOT_ADDR8_SPN 14B7 GPU_GPIO9 20C4 KBD_SHIFT_L 23A5 23B7 30A8 30C6 39B4 PMU_BATT0_DET_L 30B4 37B2 39A8 39B8
3V_5V_OK 33B4 35D6 CBUS_CE1_L 18C1 18C4 CSLOT_ADDR9_SPN 14B7 GPU_G_FILTR 22D8 KBD_X<9..0> 23A5 23B5 23B7 30C6 39A4 39B4 39D3 PMU_BATT1_DET_L_PU 30B4 30D2 TMDS_DP<2..0> 20B2 20C2 20D2 21B1 21B2 22D5 22D6
3V_BG 33C4 CBUS_CE2_L 18B4 18C2 CSLOT_CE1_L_SPN 14C7 GPU_HPD 20C4 22C3 KBD_Y<7..0> 23B7 30C6 30D6 39C3 39D3 PMU_BATT_DET_L 30B3 30D2 31A4 39C3 37B2 39A8
3V_BOOST 33C4 CBUS_DATA<15..0> 18A1 18A2 18A4 18C1 18C2 CSLOT_CE2_L_SPN 14C7 GPU_HSYNC 21D5 L3_ADDR<17..0> 6D6 8C3 8C6 8D3 8D6 36C5 PMU_BYTE 30B6 30C7 TPAD_F_RXD 23A7 39C4
3V_BOOST_ESR 33D3 CBUS_DET_1_L 18C2 18C4 39B8 CSLOT_IORD_L_SPN 14C7 GPU_I2C1SCL 20C2 L3_CLK<1..0> 6C3 8D1 8D4 36C1 PMU_CAPSLOCK_LED_L 30C6 TPAD_F_TXD 23A7 39C4
3V_ITH 33C4 CBUS_DET_2_L 18A2 18C4 39B8 CSLOT_IOWAIT_L_PU 14C7 GPU_I2C1SDA 20C2 L3_CLK_REF 8B7 8D1 8D4 38D3 PMU_CHARGE_V 30C4 31B8 TPAD_RXD 23A8 30C2 30C4
3V_ITH_RC 33C3 CBUS_INPACK_L 18B2 18B4 CSLOT_IOWR_L_SPN 14C7 GPU_IFP0RSET 20A4 L3_CNTL<1..0> 6C3 8C3 8C6 36C5 PMU_CHRG_BATT_0 30C4 31A8 TPAD_TXD 23A8 30B2 30C4
3V_PMU_VTAP 32B3 CBUS_INT_L 15B5 15B7 18A7 CSLOT_OE_L_SPN 14C7 GPU_IFP0VREF 20A4 L3_DATA<63..0> 6A6 6B6 6C6 8C1 8C4 8D1 8D4 36C5 PMU_CLK 15C2 30C4 TPS2211_SHDN_L_PU 18C4
3V_RSNS 33D2 38D1 CBUS_IORD_L 18B2 18C4 CSLOT_WE_L_SPN 14C7 GPU_IFP1RSET 20A2 L3_DQPA<1..0> 8C1 8C4 8D7 PMU_CNVSS 30B6 30C7 TV_C 22B6 39D6
3V_RUNSS 33C4 CBUS_IOWR_L 18B2 18C4 CURRENT_THRESHOLD 31C4 GPU_IFP1VREF 20A2 L3_DQPB<1..0> 8C1 8C4 8D7 PMU_CPU_HRESET_L 23A4 23C4 30C4 TV_COMP 22B6 39D6
3V_SLEEP_PWREN_L 33A3 CBUS_MFUNC1_PD 18A7 CY25811_S0 21A4 GPU_MSTRAPSEL<3..0> 21B8 21C4 L3_DQPC<1..0> 8C1 8C4 8D7 PMU_EPM 30D2 30D4 TV_GND1 22B6 38B6 39A7
3V_SNSM 33C4 37A2 CBUS_MFUNC2_PD 18A7 CY25811_S1 21A4 GPU_R 21C5 22D8 L3_DQPD<1..0> 8C1 8C4 8D7 PMU_FROM_INT 15C2 30C4 TV_GND2 22A6 38B6 39A7
3V_SNSP 33C4 37A2 CBUS_MFUNC3_PD 18A7 DCDC_EN 20D6 29C7 32B7 33B5 34C8 39C1 GPU_ROMA14_TP 19B4 L3_ECHO_CLK<3..0> 6B3 8C3 8C6 36C1 PMU_I2C_CLK 30B4 30C2 TV_Y 22B6 39D6
3V_SW 33C4 38D1 CBUS_MFUNC4_PD 18A7 DCDC_EN_L 20C8 33B6 35C7 GPU_ROMA15_TP 19B4 L3_OVDD 6B1 6D3 8A2 8B5 8B7 8B8 8D1 8D4 PMU_I2C_DATA 30B4 30C2 UIDE_ADDR<2..0> 14D7 24B4 24C4 37C5
3V_TG 33D4 CBUS_MFUNC5_PD 18A7 DDC_CLK_ISO 22D4 GPU_ROMCS_TP 19B4 38D3 PMU_INT_L 15B5 15B7 30B6 UIDE_CS0_L 14C7 24C4 37C5
3V_VOSNS 33C4 CBUS_MFUNC6_PD 18A7 DDR_VREF 12D1 12D3 12D5 12D6 12D8 38D3 GPU_RSET1 21C5 L3_PULLDOWN<1..0> 8C3 8C6 8C7 PMU_INT_NMI 15B5 15B7 30D4 UIDE_CS1_L 14C7 24B4 37C5
5V_BG 33C5 CBUS_OE_L 18C1 18C4 DVI_DDC_CLK 22D4 GPU_RSET2 21C6 L3_VREF 8B7 8C3 8C6 38D3 PMU_KB_RESET_IN1 30A7 UIDE_DATA<15..0> 14D7 24B4 24C4 24D4 37C5
5V_BOOST 33C5 CBUS_PCI_GNT_L 13D7 18A7 DVI_DDC_CLK_UF 22C5 22D3 39C7 GPU_R_FILTR 22D8 L3_ZQ<1..0> 8D2 8D5 PMU_KB_RESET_IN2 30A7 UIDE_DIOR_L 14C7 24A4 37C5
5V_BOOST_ESR 33D6 CBUS_PCI_IDSEL 18B7 DVI_DDC_DATA 22C4 GPU_SSCLK_IN 21A3 21B4 36B1 LCD_DIGON_L 22A6 PMU_KB_RESET_L 30A6 30B7 39B2 UIDE_DIOW_L 14C7 24A4 37C5
5V_HD_PWREN 33A8 CBUS_PCI_PERR_L 18B7 18D7 DVI_DDC_DATA_UF 22C5 39C7 GPU_SSCLK_S0 20C4 21A5 LCD_PWREN_L 22A5 PMU_LID_CLOSED_L 23A8 23C4 30B2 30C4 UIDE_DMACK_L 14C7 24A4 37C5
5V_ITH 33C5 CBUS_PCI_REQ_L 13A7 13D7 18A7 DVI_HPD 22C4 GPU_SSCLK_S1 20C4 21A5 LED_LINK10 27B5 PMU_NMI_BUTTON_L 25C2 30C2 30C4 UIDE_DMARQ 14C7 37C5
A 5V_ITH_RC
5V_RSNS
5V_RUNSS
33C6
33D7 38D1
33C5
CBUS_PCI_RESET_L 18A7
CBUS_PCI_SERR_L 18B7 18D7
CBUS_READY 18B1 18C4
DVI_HPD_DIV
DVI_HPD_UF
22C3
22C3 22C5 39C7
DVI_TRUN_ON_ILIM 22D2
GPU_SSCLK_UF 21A3 36C1
GPU_SUS_STAT_L_PU 20C4
GPU_THERMDA_TP 21C4
LED_LINK100
LED_RX_SPN
LEFT_USB_DM
27B5
27B5
24B2 26B3 37A2 39D1
PMU_NMI_L 30C2 30C4
PMU_NUMLOCK_LED_L 30C6
PMU_OOPS 30B2 30B4
UIDE_INTRQ
UIDE_IOCHRDY
UIDE_REF
14C7 37C5
14C7 24A4 37C5
14C7 38C3
NOTICE OF PROPRIETARY PROPERTY
A
5V_SLEEP_PWREN 33A8 CBUS_REG_L 18B2 18C4 DVI_TURN_ON 22D3 GPU_THERMDC_TP 21C4 LEFT_USB_DP 24B2 26A3 37A2 39D1 PMU_PME_L 15B5 26B8 30B2 30C4 UIDE_RST_L 14C7 24A4 37C5
5V_SND_PWREN 25D8 CBUS_RESET_L 18B2 18C4 DVI_TURN_ON_BASE 22D2 GPU_TMDS_CLKN 20B2 21A1 21B2 LID_CLOSED_L 23A7 39C4 PMU_POWERUP_OK 30B4 30D2 USB2_PCI_GNT_L 13C7 26B7
5V_SNSM 33C5 37A2 CBUS_SUSPEND_PU 18A7 18D7 EEPROM_ADDR 23D4 GPU_TMDS_CLKP 20B2 21A1 21B2 LM2594_IN 28D8 38B3 PMU_POWER_UP_L 29C7 30C6 30D7 33B6 USB2_PCI_INT_L 15B5 15C7 26A8 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
5V_SNSP 33C5 37A2 CBUS_VCCD0_L 18C4 EEPROM_WP_PD 23D3 GPU_TMDS_DN<2..0> 20B2 21A1 21B2 LT1962_1V5_ADJ 16B2 PMU_REQ_L 15B7 15C2 30C4 USB2_PCI_REQ_L 13A7 13D7 26B7 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
5V_SW 33C5 38D1 CBUS_VCCD1_L 18C4 EIDE_ADDR<2..0> 14B7 24B8 37B5 GPU_TMDS_DP<2..0> 20B2 21A1 21B2 LT1962_1V5__BYP 16B2 PMU_RESET_BUTTON_L 25B2 30C4 30D2 USB_D1M 15C1 26A5 26B4 39B6 AGREES TO THE FOLLOWING
5V_TG 33C5 CBUS_VPPD0 18C4 EIDE_CS0_L 14B7 24B8 37B5 GPU_TV_GND1 22B8 38B6 LT1962_INT_ADJ 15D6 PMU_RESET_L 30B6 USB_D1P 15C1 26A4 26A5 39B6 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5V_VOSNS 33C5 CBUS_VPPD1 18C5 EIDE_CS1_L 14B7 24B8 37B5 GPU_TV_GND2 22A8 38B6 LT1962_INT_BYP 15D6 PMU_SLEEP_LED 23C4 USB_D2M 15D1 26A4 26A5 39B6
1625_BG 32C5 CBUS_VS1 18B2 18C4 EIDE_DATA<15..0> 14B7 14C7 24B8 24C8 24D8 37B5 GPU_VCORE 20C5 20D6 38C3 39B2 LT1962_L3_ADJ 6B2 39C1 PMU_SLEEP_LED_L 23C2 30C4 USB_D2P 15D1 26A4 26A5 39B6 II NOT TO REPRODUCE OR COPY IT
1625_BST 32C5 CBUS_VS2 18B2 18C4 EIDE_DMACK_L 14A7 24A8 37B5 GPU_VCORE_CNTL_L 20B6 20C4 LT1962_L3_BYP 6A2 PMU_SMB_CLK 30B4 30C2 31A3 USB_DAM 15B2 15D2 26A5
1625_BST_ESR 32C5 CBUS_WAIT_L 18B2 18B4 EIDE_DMARQ 14A7 24B8 37B5 GPU_VCORE_CNTL_L_RC 20B6 LTC1625_ITH 31D3 PMU_SMB_DATA 30B4 30C2 31A2 USB_DAP 15B2 15D2 26A5 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1625_COMP 31D2 32C6 CBUS_WE_L 18B1 18C4 EIDE_INT 14A7 24A8 37B5 GPU_VCORE_PWR_SEQ 20D8 LTC1778_SHDN 20C8 PMU_TO_INT 15C2 30C4 USB_DBM 15B2 15D2
1625_DIV 32C8 CBUS_WP_L 18A1 18B4 EIDE_IOCHRDY 14B7 24A8 37B5 GPU_VCORE_SEQ 20D8 LTC1962_1V5_VIN 16B3 38A1 POWER_UP 29C7 USB_DBP 15B2 15D2 SIZE DRAWING NUMBER REV.
1625_ENABLE 32D7 CG_ADDRSEL 15B7 EIDE_OPTICAL_ADDR<2..0> 24A5 24A6 24B7 37B5 39A4 GPU_VCORE_SEQ_L 20D8 LTC1962_1V5_VOUT 16B2 38A1 POWER_VALID 30B2 30C4 USB_DCM 15B2 15C2 26A5
1625_ENABLE_L
1625_EXTVCC
1625_FCB
32D6
32D5 38D1
32C6
CG_CLKOUT
CG_FSEL
CG_LOCK
15B6
15B7 15C5
15B7
EIDE_OPTICAL_CS0_L 24A5 24B7 37B5 39D4
EIDE_OPTICAL_CS1_L 24A6 24B7 37B5 39D4
GPU_VCORE_SW
GPU_VIPD0_TP
GPU_VIPD1_TP
20C6 38B1
19C2
19C2
LTC1962_INT_VIN 15D7 38A1
LTC1962_L3_VIN 6B3 38A1
LTC1962_L3_VOUT 6B2 38A1
PWR_BUTTON_L 23A7 25C2 39B2
RAM_ADDR<12..0> 10A4 10B4 12B3 12B5 12B6 12B8 36A5
RAM_BA<1..0> 10A4 12B3 12B5 12B6 12B8 36A5
USB_DCP
USB_DDM
USB_DDP
15B2
15B2
15B2
15C2
15C2
15C2
26A5
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 41 44
8 7 6 5 4 3 2 1
CR-42
8 7 6 5 4 3 2 1
USB_DEM 15B2 15C2 37B2
USB_DEP 15B2 15C2 37B2
USB_DFM 15B2 37B2
USB_DFP 15B2 37B2
USB_OC_AB_L 15B2 15C7
USB_OC_CD_L 15B2 15C7
USB_OC_EF_L 15B2 15C7
USB_PWREN_AB_L 15B2 15C7
USB_PWREN_CD_L 15B2 15C7
USB_PWREN_EF_L 15B2 15D7
VCORE_BOOST 34C4 38C1
VCORE_BST 34C5 38C1
VCORE_CC 34B6 38B1
VCORE_DH 34B5 38C1
VCORE_DL 34B5 38C1
VCORE_FAST<4..1> 34D2 34D3 34D5
VCORE_FB 34B5 38B1 39A2
VCORE_GND 34B5 38B1
D
VCORE_GNDA
VCORE_GNDDIV
34B6
34A5 34B5 38B1
VCORE_GNDDIV_TEST 34A4
D
VCORE_GNDSNS 34A1 34A5 38B1
VCORE_GNDSNS_TEST 34A4
VCORE_ILIM 34C6 38C1
VCORE_LX 34B5 38C1
VCORE_MUX_EN 34D5
VCORE_MUX_SEL 34D5
VCORE_REF 34B6 38C1
VCORE_SHDN_L 34C6
VCORE_SLOW<4..1> 34D6
VCORE_SNS 34A1 38B1
VCORE_TIME 34B4 38B1
VCORE_TON 34B6 38C1
VCORE_VCC 34C6 38C1
VCORE_VGATE 15B5 15B7 34B4 38B1
VCORE_VID<4..0> 34A3 34B8 34D4
VGA_B 22C6 22D7 39D7
VGA_G 22C5 22D7 39D7
VGA_HSYNC 21D4 22C6 39D7
VGA_R 22C5 22D7 39D7
VGA_VSYNC 21D4 22C5 39D7
VIPPCLK_PD 19C2
C C
B B
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 42 44
8 7 6 5 4 3 2 1
CR-43
8 7 6 5 4 3 2 1
*** Unit Cross-Reference *** C167 CAP 17B3 C336 CAP 17C8 C508 CAP 28D6 C676 CAP 22A7 C844 CAP 21D3 Q16 TRA_SI4435DY 31D2
--- for the entire design -- C168 CAP 17C3 C337 CAP 21B7 C509 CAP 12D2 C677 CAP 22A7 C845 CAP 21D3 Q17 TRA_2N7002DW 29C7 33A6
C169 CAP 17C2 C338 CAP 21D5 C510 CAP 20C8 C678 CAP 22A8 C846 CAP 21D2 Q18 TRA_2N3906 23C1
BS1 PCB_STANDOFF 4D3 C170 CAP 19D4 C339 CAP 20B4 C511 CAP 35C7 C679 CAP 6B2 C847 CAP 21D2 Q19 TRA_2N7002DW 31B7 31B8
C1 CAP 34C2 C171 CAP 6C2 C340 CAP 20B4 C512 CAP 33C5 C680 CAP_P 20C5 C848 CAP 21D2 Q20 TRA_2N7002DW 23C2 23C3
C2 CAP 34D1 C172 CAP 5D7 C341 CAP 20A5 C513 CAP 28D5 C681 CAP_P 20C5 C849 CAP 21D2 Q21 TRA_SI3443DV 33B2
C3 CAP 34D2 C173 CAP 5D6 C342 CAP 20A6 C514 CAP 28D6 C682 CAP_P 20C5 C850 CAP 21D2 Q22 TRA_2N7002DW 31B6
C4 CAP 34C1 C174 CAP 5D6 C343 CAP 20A2 C515 CAP 31B2 C683 CAP 35D8 C851 CAP 21D2 Q23 TRA_2N7002DW 31A7
C5 CAP 34C1 C175 CAP 17D2 C344 CAP 21D5 C516 CAP 26D8 C684 CAP 8A1 C852 CAP 21D1 Q24 TRA_SI3443DV 33A7
C6 CAP 34D1 C176 CAP 15C5 C345 CAP 17B5 C517 CAP 26D8 C685 CAP 8B8 C853 CAP 22C1 Q25 TRA_2N3904 7C6
C7 CAP 34C1 C177 CAP 17C1 C346 CAP 17B5 C518 CAP 32A3 C686 CAP 8A6 C854 CAP_P 34B2 Q26 TRA_2N7002 7C7
C8 CAP 34D1 C178 CAP 15D5 C347 CAP 17B7 C519 CAP 28C5 C687 CAP 8A2 C855 CAP 25A3 Q27 TRA_SI3446DV 25B3
C9 CAP 5D4 C179 CAP 6C3 C348 CAP 17A6 C520 CAP 35C3 C688 CAP 22B7 C856 CAP 25B2 Q28 TRA_2N7002DW 7C7
C10 CAP 17C4 C180 CAP 5D7 C349 CAP 17A6 C521 CAP 33C5 C689 CAP 35D7 C857 CAP 25D7 Q29 TRA_2N7002DW 22C4 22D4
C11 CAP 17D8 C181 CAP 17D8 C350 CAP 17B6 C522 CAP 32C3 C690 CAP 22B8 C858 CAP 25D7 Q30 TRA_SI3446DV 25A3
C12 CAP 17C4 C182 CAP 17C7 C351 CAP 21B4 C523 CAP 28B4 C691 CAP 11D4 C859 CAP 29B5 Q31 TRA_2N3904 25B6
C13 CAP 19C5 C183 CAP 17D7 C352 CAP 21D7 C524 CAP 31B2 C692 CAP_P 34B1 C860 CAP 29D4 Q32 TRA_TP0610 22D3
C14 CAP 34C2 C184 CAP 17D6 C353 CAP 21C6 C525 CAP 31B2 C693 CAP_P 34B1 C861 CAP 29D4 Q33 TRA_2N7002DW 22C2
D
C15
C16
C17
CAP
CAP
CAP
35A6
15A5
17C3
C185
C186
C187
CAP
CAP
CAP
17D1
17C7
17B3
C354
C355
C356
CAP
CAP
CAP
20A5
17C3
17B5
C526
C527
C528
CAP
CAP
CAP
31B2
31B1
33C6
C694
C695
C696
CAP_P
CAP_P
CAP_P
34B2
34B1
34B1
C862
C863
C864
CAP
CAP
CAP
29B3
29D3
29D2
Q34
Q35
Q36
TRA_2N3904 22D1
TRA_SI3443DV 33A7
TRA_2N3904 22C1
D
C18 CAP 17B2 C188 CAP 17D3 C357 CAP 17C5 C529 CAP 33D4 C697 CAP_P 34B2 C865 CAP 22B4 Q37 TRA_SI3446DV 35D7
C19 CAP 17B3 C189 CAP 17D3 C358 CAP 17C6 C530 CAP 32A4 C698 CAP 11D4 C866 CAP 25C6 Q38 TRA_2N3904 25A6
C21 CAP 17C1 C190 CAP 17D2 C359 CAP 21D7 C531 CAP 28D6 C699 CAP 11D2 C867 CAP 25C6 Q39 TRA_IRF7811W 20C6
C22 CAP 17B2 C191 CAP 17D1 C360 CAP 20A6 C532 CAP 31D4 C700 CAP 11D2 C1000 CAP 28C5 Q40 TRA_IRF7805 34C3
C23 CAP 17C2 C192 CAP 17D1 C361 CAP 20A6 C533 CAP 33C5 C701 CAP 11D2 C1600 CAP 16B3 Q41 TRA_IRF7805 34C4
C24 CAP 21D3 C193 CAP 17C5 C362 CAP 20B2 C534 CAP 31C5 C702 CAP 27B5 C1601 CAP 16B2 Q42 TRA_IRF7805 20C6
C25 CAP 17B2 C194 CAP 17C6 C363 CAP 20B2 C535 CAP 31C4 C703 CAP 26D8 C1602 CAP 16B1 Q43 TRA_SI4888DY 33C6
C26 CAP 17B3 C196 CAP 19C5 C364 CAP 17A6 C536 CAP 35C3 C704 CAP 35B8 D1 DIODE 27B7 Q44 TRA_IRF7822 34B3
C27 CAP 17B1 C197 CAP 20D5 C365 CAP 17B5 C537 CAP 35C6 C705 CAP 11D8 D2 DIODE_SCHOT 34C4 Q45 TRA_IRF7822 34B4
C28 CAP 19C5 C198 CAP 20D5 C366 CAP 17A7 C538 CAP 35C2 C706 CAP 11D6 D3 DIODE_SCHOT 32C5 Q46 TRA_IRF7822 34B3
C29 CAP 5D4 C199 CAP 20D4 C367 CAP 17A6 C539 CAP 33C5 C707 CAP 11D4 D4 DIODE 32C7 Q47 TRA_IRF7811W 35B6
C30 CAP 5D6 C200 CAP 5D7 C368 CAP 17A6 C540 CAP 32A2 C708 CAP_P 35B7 D5 DIODE 20C6 Q48 TRA_IRF7805 35C6
C31 CAP 5D6 C201 CAP 5D6 C369 CAP 17A5 C541 CAP 32C3 C709 CAP 22B1 D6 DIODE_DUAL_6P 29D3 Q49 TRA_SI3443DV 25D7
C32 CAP 34D1 C202 CAP 5D6 C370 CAP 17B6 C542 CAP 28A4 C710 CAP 27C5 D7 DIODE_SCHOT 33D5 Q50 TRA_IRF7805 32C4
C33 CAP 17C1 C203 CAP 5D5 C371 CAP 17B7 C543 CAP 12B2 C711 CAP 11D8 D8 DIODE_DUAL_6P 29D2 Q51 TRA_IRF7811W 32C4
C34 CAP 17B1 C204 CAP 5D8 C372 CAP 17B5 C544 CAP 35D5 C712 CAP 11D6 D9 DIODE_SCHOT 32B4 Q52 TRA_SI4888DY 33D6
C35 CAP 17C1 C205 CAP 17D6 C373 CAP 17C5 C545 CAP 33C3 C713 CAP 22B1 D10 DIODE 31C5 Q53 TRA_2N3904 25A6
C36 CAP 17B1 C206 CAP 17D2 C374 CAP 17C8 C546 CAP 28C6 C714 CAP_P 32C2 D11 DIODE 31C3 Q54 TRA_IRF7805 31B3
C37 CAP 17B2 C207 CAP 17C7 C375 CAP 20A1 C547 CAP 33C4 C715 CAP_P 35B7 D12 DIODE_SCHOT 32A4 Q55 TRA_IRF7811W 31B3
C38 CAP 17C2 C208 CAP 17C6 C376 CAP 20A1 C548 CAP 32A5 C716 CAP 11D7 D13 DIODE_DUAL_6P 29B4 Q56 TRA_2N3904 25B6
C39 CAP 17C3 C209 CAP 17C7 C377 CAP 17C4 C549 CAP 29C2 C717 CAP 11D6 D14 DIODE_SCHOT 33D4 Q57 TRA_2N7002 30A3
C40 CAP 17C3 C210 CAP 17C8 C378 CAP 17B2 C550 CAP 31C5 C718 CAP 27B4 D15 DIODE_DUAL_6P 29B4 Q58 TRA_IRF7811W 35B3
C41 CAP 17B3 C211 CAP 21D4 C379 CAP 17A6 C551 CAP 31C2 C719 CAP 27B5 D16 DIODE 33B6 Q59 TRA_IRF7805 35C3
C42 CAP 17C3 C212 CAP 20D5 C380 CAP 17A5 C552 CAP 12C2 C720 CAP_P 33C8 D17 DIODE_SCHOT 32B6 Q60 TRA_IRF7416 31D1
C43 CAP 17B3 C213 CAP 20D6 C381 CAP 17A7 C553 CAP 12C2 C721 CAP 22A1 D18 DIODE_SCHOT 32A6 Q61 TRA_SI4888DY 33D3
C44 CAP 19D6 C214 CAP 35A2 C382 CAP 17A7 C554 CAP 35D4 C722 CAP_P 32C2 D19 DIODE_SCHOT 32A6 Q62 TRA_SI4888DY 33C3
C45 CAP 5D5 C215 CAP 17D8 C383 CAP 17A6 C555 CAP 32C3 C723 CAP 33D7 D20 DIODE_SCHOT 28D7 Q63 TRA_2N3906 23B8
C46 CAP 17C3 C216 CAP 17D6 C384 CAP 17A7 C556 CAP 28B3 C724 CAP 33C8 D21 DIODE_SCHOT 22D5 Q64 TRA_2N3906 23B8
C47 CAP 17C3 C217 CAP 17D6 C385 CAP 17B6 C557 CAP 31B3 C725 CAP 27A2 D22 DIODE_SCHOT 33C7 Q65 TRA_2N7002DW 27A7 27B7
C48 CAP 17B1 C218 CAP 17D7 C386 CAP 17A7 C558 CAP 33B5 C726 CAP 27B4 D23 DIODE_SCHOT 35B6 Q66 TRA_2N7002DW 31A4 31C3
C49 CAP 17C2 C219 CAP 17D7 C387 CAP 17A5 C559 CAP 33C4 C727 CAP 27B5 D24 DIODE_SCHOT 20C5 Q67 TRA_2N7002DW 25C5
C50 CAP 20D5 C220 CAP 17D5 C388 CAP 17A5 C560 CAP 33C4 C728 CAP 20C5 D25 DIODE 34B2 Q68 TRA_2N7002DW 22C4 23C7
C51 CAP 5D5 C221 CAP 17D3 C389 CAP 17B7 C561 CAP 33C4 C729 CAP 33D7 D26 DIODE_SCHOT 32C4 Q69 TRA_2N7002DW 25D5
C52 CAP 17B3 C222 CAP 17D3 C390 CAP 20A7 C562 CAP 32A4 C730 CAP 26D8 D27 DIODE_SCHOT_3P2 28D8 Q70 TRA_TP0610 22C2
C53 CAP 17B1 C223 CAP 17D3 C391 CAP 20B2 C563 CAP 28A3 C731 CAP 34B3 D28 DIODE 31D1 Q71 TRA_2N7002DW 29C6
C54 CAP 17B3 C224 CAP 10A7 C392 CAP 17A6 C564 CAP 31A6 C732 CAP_P 32C3 D29 DIODE_SCHOT 31B2 Q2000 TRA_2N3904 20D7
C55 CAP 17C2 C225 CAP 17D3 C393 CAP 20B4 C565 CAP 31B5 C733 CAP 20C5 D30 DIODE 31D2 Q2001 TRA_2N3904 20D7
C56 CAP 17C3 C226 CAP 13B4 C394 CAP 21D6 C566 CAP 31B1 C734 CAP 25D3 D31 DIODE_SCHOT 29D5 Q3100 TRA_2N7002DW 31C3 31C4
C57 CAP 17B1 C227 CAP 17B3 C395 CAP 21D7 C567 CAP 31B1 C735 CAP 34B4 D32 DIODE_SCHOT 35B2 R1 RES 23B3
C58 CAP 17C3 C228 CAP 17B7 C396 CAP 35C1 C568 CAP 31B2 C736 CAP_P 32C2 D33 DIODE_SCHOT 33C3 R2 RES 15D8
C59 CAP 17B1 C229 CAP 17C6 C397 CAP 17B8 C569 CAP 31B5 C737 CAP 33D7 DP1 DPAK3P 34C7 34D7 R3 RES 24C4
C C60
C61
C62
CAP
CAP
CAP
17C1
17B3
17B3
C230
C231
C232
CAP
CAP
CAP
17B7
21D4
21D4
C398
C399
C400
CAP
CAP
CAP
17B8
15D5
20A8
C570
C571
C572
CAP
CAP
CAP
31B5
33A5
32C4
C738
C739
C740
CAP
CAP
CAP
29D6
18D3
29C2
DP2
DP3
DP4
DPAK3P
DPAK3P
DPAK3P
35C3 35D6 35D7
31C1 31C2 31D3
29C6 29D6
R4
R5
R6
RES
RES
RES
15C1
5D4
7B6
C
C63 CAP 17C2 C233 CAP 20D5 C401 CAP 35D2 C573 CAP 33C3 C741 CAP 32C5 DP20 DPAK3P 20D7 R7 RES 15A6
C64 CAP 17B2 C234 CAP 20D5 C402 CAP 17B8 C574 CAP 32A5 C742 CAP 18B3 DZ2 ZENER 29D3 R8 RES 15A3
C65 CAP 19C6 C235 CAP 20D6 C403 CAP 17B8 C575 CAP 28C6 C743 CAP 33D2 F1 FUSE 22D6 R9 RES 24A7
C66 CAP 19C4 C236 CAP 6D2 C404 CAP 15D6 C576 CAP 28D5 C744 CAP_P 35B1 F2 FUSE 29D7 R10 RES 24B8
C67 CAP 19D4 C237 CAP 6D3 C405 CAP 22B4 C577 CAP 28C6 C745 CAP 28D5 F3 FUSE 29D5 R11 RES 24A8
C68 CAP 20D4 C238 CAP 5D5 C406 CAP 20D1 C578 CAP 28C6 C746 CAP 29C2 F4 FUSE 31D1 R12 RES 5B1
C69 CAP 20D4 C239 CAP 5D8 C407 CAP 20D1 C579 CAP 18D6 C747 CAP_P 35B2 F5 FUSE 31D1 R13 RES 5B1
C70 CAP 20D4 C240 CAP 17D7 C408 CAP 20A8 C580 CAP 31B5 C748 CAP 18B3 G1 OSC 28A4 R14 RES 7A6
C71 CAP 20D4 C241 CAP 17D5 C409 CAP 20B1 C581 CAP 31B2 C749 CAP 28C4 J1 CON_F1ST_S2MT_SM 15A6 R15 RES 14C3
C72 CAP 19D4 C242 CAP 17C2 C410 CAP 20B1 C582 CAP 31B1 C750 CAP 33D2 J2 CON_3RTSM_125 25B2 R16 RES 24A3
C73 CAP 5D5 C243 CAP 17D3 C411 CAP 15D7 C583 CAP 31B1 C751 CAP 29C3 J3 CON_F14RT_S2MT_SM 24B1 R17 RES 24C2
C74 CAP 5D6 C244 CAP 17D3 C412 CAP_P 34C4 C584 CAP 28A4 C752 CAP 32C4 J4 CON_3RTSM_125 25A3 R18 RES 24B8
C75 CAP 5D5 C245 CAP 17D1 C413 CAP_P 34C3 C585 CAP 33B2 C753 CAP_P 35B1 J5 CON_10STSM_5087 25D1 R19 RES 5A2
C76 CAP 5D5 C246 CAP 17C7 C414 CAP_P 34C3 C586 CAP 32C3 C754 CAP 18C7 J6 CON_12 34A4 R20 RES 23B3
C77 CAP 5C3 C247 CAP 17B7 C415 CAP_P 34C3 C587 CAP 28C8 C755 CAP 18D5 J7 CON_F30RT_S2MT_SM 22B3 R21 RES 23B3
C78 CAP 17B3 C248 CAP 17C6 C416 CAP_P 34C3 C588 CAP 28C8 C756 CAP 18D5 J8 CON_4RT_WRIB 22B1 R22 RES 19C6
C79 CAP 17C2 C249 CAP 17C7 C417 CAP_P 34C4 C589 CAP 30D6 C757 CAP 31D3 J9 CON_F16ST_D_SMA 25C3 R23 RES 5A2
C80 CAP 19D4 C250 CAP 21D4 C418 CAP 22B2 C590 CAP 28C7 C758 CAP 28D6 J10 CON_M80ST_D4MT_SM 18C2 R24 RES 5C1
C81 CAP 19D4 C251 CAP 19D3 C419 CAP_P 34C4 C591 CAP 28C8 C759 CAP_P 32C2 J11 CON_M50SM_5MM 24B5 R25 RES 15A6
C82 CAP 20D4 C252 CAP 20C1 C420 CAP_P 34C4 C592 CAP 30A7 C760 CAP_P 32C2 J12 CON_F14RT_S2MT_SM 32B8 R26 RES 14C7
C83 CAP 20D5 C253 CAP 20C1 C425 CAP 27B6 C593 CAP 28C7 C761 CAP 18D6 J13 CON_M50SM_5MM 24D1 R27 RES 14C7
C84 CAP 19D3 C254 CAP 19C4 C426 CAP 27A4 C594 CAP 22A3 C762 CAP 18D6 J14 CON_F30ST_D_SM 25D6 R28 RES 19C6
C85 CAP 19D4 C255 CAP 5D7 C427 CAP 27D4 C595 CAP 28C7 C763 CAP 18D5 J15 CON_F40RT_S2MT_SM 23C6 R29 RES 19B2
C86 CAP 35A7 C256 CAP 35A2 C428 CAP 27C5 C596 CAP 33A7 C764 CAP 18D5 J16 CON_F30RT_T6MT_TH1 22D6 R30 RES 19B2
C87 CAP 13D7 C257 CAP 30A3 C429 CAP 27A7 C597 CAP 30B7 C765 CAP_P 32C2 J17 CON_F5RT_MINIDIN_TH 22B6 R31 RES 19C2
C88 CAP 15C3 C258 CAP 17C1 C430 CAP 27A8 C598 CAP 30A6 C766 CAP 33D2 J18 CON_RJ45_SHORT_4MT_TH 27C1 R32 RES 5B1
C89 CAP 15C3 C259 CAP 17D1 C431 CAP 27A4 C599 CAP 33B8 C767 CAP 32C4 J19 CON_M8RT_S_SM 31D8 R33 RES 23B3
C90 CAP 24A4 C260 CAP 17D1 C432 CAP 20B8 C600 CAP 23D3 C768 CAP 31B4 J20 CON_F200RT_DDRDIMM_SM1 12D7 R34 RES 24A4
C92 CAP 19D6 C261 CAP 17D1 C433 CAP 22B4 C601 CAP 22A3 C769 CAP 28C4 J21 CON_F80ST_D4MT_SM 24D5 R35 RES 19B4
C93 CAP 19D3 C262 CAP 17C8 C434 CAP 27A4 C602 CAP 23D6 C770 CAP 29A3 J22 CON_F9RT_S2MT_SMA 29C1 R36 RES 24A1
C94 CAP 19D2 C263 CAP 21C4 C435 CAP 27C5 C603 CAP 22C5 C771 CAP 33D2 J23 CON_F200RT_DDRDIMM_SM2 12D4 R37 RES 5C1
C95 CAP 5D5 C264 CAP 19D5 C436 CAP 34C4 C604 CAP 22C5 C772 CAP 29A3 J24 CON_F6RT_S4MT_TH1 29A2 R38 RES 5C1
C96 CAP 17D5 C265 CAP 6D2 C437 CAP 33A3 C605 CAP 23D8 C773 CAP 31B4 J25 CON_M8RT_S_SM 31A4 R39 RES 5D1
C97 CAP 17D6 C266 CAP 6C3 C438 CAP 27C4 C606 CAP 23C7 C774 CAP 31A5 L1 IND 15D3 R40 RES 35A6
C98 CAP 17B1 C267 CAP 17D5 C439 CAP 31D6 C607 CAP 34D2 C775 CAP 28D6 L2 IND 22A4 R41 RES 24A3
C99 CAP 15C2 C268 CAP 17D5 C440 CAP 34B6 C608 CAP 22D7 C776 CAP 35B2 L3 IND 28D6 R42 RES 24A7
C100 CAP 17B2 C269 CAP 17D6 C441 CAP 10D3 C609 CAP 22D8 C777 CAP 23C6 L4 IND 21D3 R43 RES 24A2
C101 CAP 17B2 C270 CAP 17A6 C442 CAP 20B8 C610 CAP 35A4 C778 CAP 23C6 L5 IND 21D3 R44 RES 5C1
C102 CAP 17B1 C271 CAP 17A7 C443 CAP 22A4 C611 CAP 34D1 C779 CAP 28D8 L6 IND 31A3 R45 RES 15C2
C103 CAP 17D4 C272 CAP 17B6 C444 CAP 32C5 C612 CAP 34D1 C780 CAP 33D2 L7 IND 31A3 R46 RES 24A3
C104 CAP 19D4 C273 CAP 17B6 C445 CAP 32C6 C613 CAP 35A4 C781 CAP 23C1 L8 IND 31A3 R47 RES 24B3
B C105
C106
C107
CAP
CAP
CAP
19C4
17C3
17B1
C274
C275
C276
CAP
CAP
CAP
17B7
17A5
17A5
C446
C447
C448
CAP
CAP
CAP
32C6
27C3
18D3
C614
C615
C616
CAP
CAP
CAP
34D1
22C7
22D7
C782
C783
C784
CAP
CAP_P
CAP_P
31B4
28D7
32C2
L9
L10
L11
IND
IND
IND
31A3
22D7
22D8
R48
R49
R50
RES
RES
RES
24A7
13A5
5D6
B
C108 CAP 5D7 C277 CAP 17B7 C449 CAP 31D7 C617 CAP 22C8 C785 CAP_P 32C2 L12 IND 22D7 R51 RES 5C3
C109 CAP 5D7 C278 CAP 17B3 C450 CAP 25D4 C618 CAP 22D7 C786 CAP_P 32C2 L13 IND 22D8 R52 RES 15D2
C110 CAP 5D6 C279 CAP 17C7 C451 CAP 10D2 C619 CAP 35A5 C787 CAP_P 32C2 L14 IND 35A4 R53 RES 24A8
C111 CAP 5D5 C280 CAP 17C5 C452 CAP 27C5 C620 CAP 34C1 C788 CAP 23D4 L15 IND 22D7 R54 RES 13A5
C112 CAP 34C1 C281 CAP 21B4 C453 CAP 20C7 C621 CAP 34D2 C789 CAP 23D5 L16 IND 22D8 R55 RES 5C1
C113 CAP 17D6 C282 CAP 19C4 C454 CAP 33C6 C622 CAP 34D1 C790 CAP_P 33C1 L17 FILTER_4P 22C8 R56 RES 5C1
C114 CAP 17D6 C283 CAP 19D4 C455 CAP 27C5 C623 CAP_P 33A7 C791 CAP 30D5 L18 IND 22D5 R57 RES 35A6
C115 CAP 17D5 C284 CAP 20D4 C456 CAP 27D3 C624 CAP 34C1 C792 CAP_P 33A7 L19 IND 21A4 R58 RES 15D1
C116 CAP 17B3 C285 CAP 20D4 C457 CAP 27C3 C625 CAP 22D2 C793 CAP 33C2 L20 IND 22B7 R59 RES 15B2
C117 CAP 17C1 C286 CAP 20D6 C458 CAP 25D4 C626 CAP 33A8 C794 CAP 30B2 L21 IND 22B7 R60 RES 15B1
C118 CAP 17B3 C287 CAP 20D5 C459 CAP 10D2 C627 CAP 34D1 C795 CAP_P 31B1 L22 IND 22A7 R61 RES 14C7
C119 CAP 17C1 C288 CAP 19D4 C460 CAP 12D1 C628 CAP 33A8 C796 CAP 30B3 L23 IND 22A7 R62 RES 24A3
C120 CAP 17B1 C289 CAP 19D4 C461 CAP 20B7 C629 CAP 21A4 C797 CAP 30D5 L24 IND 22B7 R63 RES 24A3
C121 CAP 17C2 C290 CAP 6D3 C462 CAP 22A5 C630 CAP 8A4 C798 CAP 30D6 L25 IND 20C5 R64 RES 24A8
C122 CAP 17B2 C291 CAP 9D5 C463 CAP 32C6 C631 CAP 8A4 C799 CAP 23B7 L26 IND 22B2 R65 RES 5B1
C123 CAP 17B1 C292 CAP 17A5 C464 CAP 27D3 C632 CAP 22B7 C800 CAP 23A7 L27 IND 27C4 R66 RES 5D1
C124 CAP 17D4 C293 CAP 17B7 C465 CAP 27A4 C633 CAP 22D5 C801 CAP 23A6 L28 IND 22B2 R67 RES 35A6
C125 CAP 19D5 C294 CAP 19C4 C466 CAP 27C4 C634 CAP 21A4 C802 CAP 23A7 L29 IND 22B2 R68 RES 15B6
C126 CAP 20D5 C295 CAP 6C2 C467 CAP 20C7 C635 CAP 8A5 C803 CAP 23C6 L30 IND 35B7 R69 RES 24C1
C127 CAP 20D5 C296 CAP 6C3 C468 CAP 33D7 C636 CAP 8A6 C804 CAP 12C2 L31 IND_3P 34C2 R70 RES 15A2
C128 CAP 20D5 C297 CAP 6D3 C469 CAP 32D5 C637 CAP 8A4 C805 CAP 12C2 L32 IND_3P 32C4 R71 RES 13B5
C129 CAP 15A5 C298 CAP 17D6 C470 CAP 23C4 C638 CAP 8A3 C806 CAP 12B2 L33 IND_3P 33D7 R72 RES 19B6
C130 CAP 17B2 C299 CAP 17D6 C471 CAP 34C5 C639 CAP 8A5 C807 CAP 12A2 L34 IND 29C4 R73 RES 5D1
C131 CAP 17D2 C300 CAP 17D5 C472 CAP 31D3 C640 CAP 8A3 C808 CAP 12C2 L35 IND_3P 33D2 R74 RES 5C1
C132 CAP 17C1 C301 CAP 17D4 C473 CAP 22A4 C641 CAP 8A3 C809 CAP 12C2 L36 IND 31B2 R75 RES 35A6
C133 CAP 17D3 C302 CAP 17A7 C474 CAP 27C2 C642 CAP 8A2 C810 CAP 12B2 L37 IND 29C5 R76 RES 15A8
C134 CAP 17B2 C303 CAP 17B6 C475 CAP 34C6 C643 CAP 22B8 C811 CAP 12A2 L38 IND 35B2 R77 RES 13D7
C135 CAP 17B3 C304 CAP 17A7 C476 CAP 35B5 C644 CAP 8A4 C812 CAP 12C2 L39 IND 23C1 R78 RES 15D8
C136 CAP 17D3 C305 CAP 17A5 C477 CAP 32C4 C645 CAP 8A7 C813 CAP 12C2 L40 IND 31A3 R79 RES 15B1
C137 CAP 15D5 C306 CAP 17B5 C478 CAP 32C6 C646 CAP 8A3 C814 CAP 12B2 L41 IND 28D7 R80 RES 15B1
C138 CAP 5D7 C307 CAP 17A7 C479 CAP 27C4 C647 CAP 8A4 C815 CAP 12A2 L42 IND 23A7 R81 RES 24B7
C139 CAP 5D7 C308 CAP 17B6 C480 CAP 25D3 C648 CAP 8A7 C816 CAP 12C1 L43 IND 23A7 R82 RES 19B5
C140 CAP 5D6 C309 CAP 17C5 C481 CAP 20B6 C649 CAP 8A4 C817 CAP 12C1 L44 IND 23A7 R83 RES 19B6
C141 CAP 5D7 C310 CAP 17C5 C482 CAP 20B5 C650 CAP 8A4 C818 CAP 12B1 L45 IND 23C7 R84 RES 5C1
C142 CAP 17D5 C311 CAP 17C6 C483 CAP 27C4 C651 CAP 8A8 C819 CAP 12A1 L46 IND 23A7 R85 RES 9B8
C143 CAP 17D2 C312 CAP 21D6 C484 CAP 27C4 C652 CAP 8A3 C820 CAP 12C1 L47 IND 27D3 R86 RES 9C8
C144 CAP 13D4 C313 CAP 19C4 C485 CAP 27C5 C653 CAP 8A4 C821 CAP 12C1 L48 IND 26D7 R87 RES 9D7
C145 CAP 17D2 C314 CAP 19C4 C486 CAP 27C4 C654 CAP 8A8 C822 CAP 12B1 L49 IND 15C6 R88 RES 14C5
C146 CAP 17D1 C315 CAP 21D4 C487 CAP 27C2 C655 CAP 8A4 C823 CAP 12A1 L50 IND 15C5 R89 RES 15D4
C147 CAP 17B2 C316 CAP 21D5 C488 CAP 34B4 C656 CAP 22B7 C824 CAP 26D8 L51 FILTER_4P 29B3 R90 RES 5D1
A C148
C149
C150
CAP
CAP
CAP
17C4
19C6
19D5
C317
C318
C319
CAP
CAP
CAP
19D4
19C4
21D4
C489
C490
C491
CAP
CAP
CAP
34B6
31B4
35C6
C657
C658
C659
CAP
CAP
CAP
22C5
20C5
6A3
C825
C826
C827
CAP
CAP
CAP
26D8
26D8
26D7
L52
L53
L54
FILTER_4P 29A3
IND
IND
21D1
29D4
R91
R92
R93
RES
RES
RES
5A1
9B2
9B2
NOTICE OF PROPRIETARY PROPERTY
A
C151 CAP 20D5 C320 CAP 17A6 C492 CAP 33D7 C660 CAP 8B7 C828 CAP 26D7 PD1 PHOTODIODE_2P 23D8 R94 RES 9B8
C152 CAP 20D4 C321 CAP 17A6 C493 CAP 34B4 C661 CAP 8A2 C829 CAP 26D7 Q1 TRA_FDG6324L 22B2 R95 RES 9C7
C153 CAP 5D8 C322 CAP 17A5 C494 CAP 23C4 C662 CAP 8A7 C830 CAP 26D6 Q2 TRA_2N7002 22A6 R96 RES 9D8 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
C154 CAP 17D4 C323 CAP 17A7 C495 CAP 26D8 C663 CAP 8A7 C831 CAP 26D6 Q3 TRA_2N7002DW 33A3 33A4 R97 RES 9C8 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
C155 CAP 17D7 C324 CAP 21D7 C496 CAP 26D8 C664 CAP 8A7 C832 CAP 26D6 Q4 TRA_2N7002DW 31C6 31C7 R98 RES 9A6 AGREES TO THE FOLLOWING
C156 CAP 17D6 C325 CAP 21D6 C497 CAP 34B7 C665 CAP 8A7 C833 CAP 26D5 Q5 TRA_SI3443DV 22A5 R99 RES 19B8 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
C157 CAP 17D7 C326 CAP 17D8 C498 CAP 12B2 C666 CAP 8A7 C834 CAP 26D4 Q6 TRA_2N3904 34D7 R100 RES 9B2
C158 CAP 17D7 C327 CAP 17D5 C499 CAP 35C6 C667 CAP 8A7 C835 CAP 26C3 Q7 TRA_NDS9407 29D6 R101 RES 9B7 II NOT TO REPRODUCE OR COPY IT
C159 CAP 17D7 C328 CAP 17D7 C500 CAP 33C5 C668 CAP 25B4 C836 CAP 26C2 Q8 TRA_SI4435DY 31D6 R102 RES 9C8
C160 CAP 17D6 C329 CAP 17C3 C501 CAP 33B4 C669 CAP 8A4 C837 CAP 34D4 Q9 TRA_FDG6324L 32D6 R103 RES 9C7
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
C161 CAP 17D2 C330 CAP 17B6 C502 CAP 32C4 C670 CAP 8A3 C838 CAP 31C3 Q10 TRA_SI4435DY 31D5 R104 RES 9A6
C162 CAP 17D3 C331 CAP 15D5 C503 CAP 32C3 C671 CAP 8A3 C839 CAP 15C6 Q11 TRA_2N3904 34D7 R105 RES 14C3 SIZE DRAWING NUMBER REV.
C163 CAP 17D3 C332 CAP 17A6 C504 CAP 32C7 C672 CAP 8A3 C840 CAP 15C6 Q12 TRA_2N7002DW 20B5 20C7 R106 RES 13D3
C164
C165
CAP
CAP
17D2
17D2
C333
C334
CAP
CAP
17C6
17C7
C505
C506
CAP
CAP
28A7
28C4
C673
C674
CAP
CAP
6B2
8A4
C841
C842
CAP
CAP
15C6
15C6
Q13
Q14
TRA_2N7002 35C6
TRA_2N7002DW 31C2 31C5
R107
R108
RES
RES
13D8
9B1 D 051-6469 F
C166 CAP 15D5 C335 CAP 17C6 C507 CAP 28C4 C675 CAP 8A4 C843 CAP 31D5 Q15 TRA_2N7002DW 33B5 R109 RES 9B7 APPLE COMPUTER INC.
SCALE SHT OF
NONE 43 44
8 7 6 5 4 3 2 1
CR-44
8 7 6 5 4 3 2 1
R110 RES 9C7 R279 RES 34D7 R447 RES 30C1 R615 RES 21A4 R1399 RES 13C8 ZT7 MTGHOLE 4D4
R111 RES 9D7 R280 RES 10B3 R448 RES 30C6 R616 RES 8D4 R1402 RES 14D1 ZT8 MTGHOLE 4C4
R112 RES 14A7 R281 RES 20C6 R449 RES 30C6 R617 RES 8D1 R1600 RES 16B3 ZT14 MTGHOLE 4D3
R113 RES 15D4 R282 RES 20B8 R450 RES 30D8 R618 RES 22C6 R1601 RES 16B2 ZT18 HOLE_VIA 4B4
R114 RES 15D4 R283 RES 20C8 R451 RES 23C2 R619 RES 21A4 R1602 RES 16B2 ZT19 HOLE_VIA 4B4
R115 RES 19B8 R284 RES 20B8 R452 RES 33B2 R620 RES 21A3 R1603 RES 16B1 ZT20 HOLE_VIA 4B4
R116 RES 9B2 R285 RES 32C3 R453 RES 33C2 R622 RES 25A5 R1605 RES 19A3 ZT21 HOLE_VIA 4B4
R117 RES 9B7 R286 RES 32C3 R454 RES 32A4 R623 RES 21A4 R1606 RES 35D8 ZT22 HOLE_VIA 4B4
R118 RES 9B7 R287 RES 27B8 R455 RES 31B6 R624 RES 8C8 R1607 RES 35D8 ZT23 HOLE_VIA 4B4
R119 RES 9C7 R288 RES 27C7 R456 RES 28B8 R625 RES 8C8 R1900 RES 19B4 ZT24 HOLE_VIA 4B4
R120 RES 9C6 R289 RES 27B4 R457 RES 31B7 R626 RES 25B5 R1901 RES 19B4 ZT25 HOLE_VIA 4B4
R121 RES 9D7 R290 RES 27B2 R458 RES 31B4 R627 RES 6B3 R2000 RES 20C7 ZT26 HOLE_VIA 4B4
R122 RES 9A5 R291 RES 31D7 R459 RES 23D5 R628 RES 8B7 R2001 RES 20D7 ZT27 HOLE_VIA 4A4
R123 RES 15D4 R292 RES 31D7 R460 RES 28C7 R629 RES 25B5 R2002 RES 20D8 ZT28 HOLE_VIA 4A4
R124 RES 26B3 R293 RES 31C7 R461 RES 28D5 R630 RES 25A5 R2003 RES 20D7 ZT29 HOLE_VIA 4A4
R125 RES 13A1 R294 RES 33A4 R462 RES 28C5 R631 RES 21C8 R2004 RES 20D8 ZT30 HOLE_VIA 4A4
R126 RES 13C8 R295 RES 33A4 R463 RES 28C7 R632 RES 21C8 R2200 RES 22A3 ZT31 HOLE_VIA 4A4
R127 RES 21D4 R296 RES 33C7 R464 RES 31B7 R633 RES 21C8 R2500 RES 25C1 ZT32 HOLE_VIA 4A4
D
R128
R129
R130
RES
RES
RES
19A8
9B1
9B2
R297
R298
R299
RES
RES
RES
27B4
27B4
18D4
R465
R466
R467
RES
RES
RES
31B4
31B7
31B8
R634
R635
R636
RES
RES
RES
19A2
19A3
8B7
R2501
RP1
RP2
RES
RPAK4P
RPAK4P
25B1
15A8
24C3
15B8
24D3
ZT33
ZT34
ZT35
HOLE_VIA
HOLE_VIA
HOLE_VIA
4B4
4B4
4B4
D
R131 RES 9B6 R300 RES 31D6 R468 RES 23C1 R637 RES 25B5 RP3 RPAK4P 24B3 24C3 ZT36 HOLE_VIA 4B4
R132 RES 9C7 R301 RES 31C8 R469 RES 23D1 R638 RES 25A5 RP4 RPAK4P 24B3 24C3 ZT37 HOLE_VIA 4B4
R133 RES 9D6 R302 RES 33A4 R470 RES 23D1 R639 RES 6B2 RP5 RPAK4P 24B3 24C3 ZT38 HOLE_VIA 4B4
R134 RES 9D7 R303 RES 33C7 R471 RES 28A4 R640 RES 6B1 RP6 RPAK4P 15A8 15B8 15C8 ZT39 HOLE_VIA 4B4
R135 RES 13B5 R304 RES 32C6 R472 RES 28B6 R641 RES 8C8 RP7 RPAK4P 15A8 15C8 15D1 ZT40 HOLE_VIA 4B4
R136 RES 19A8 R305 RES 27B4 R473 RES 31D8 R642 RES 25B5 RP8 RPAK4P 15B2 ZT41 HOLE_VIA 4B4
R137 RES 9B1 R306 RES 34B6 R474 RES 31B7 R643 RES 25A5 RP9 RPAK4P 24D3 ZT42 HOLE_VIA 4A4
R138 RES 9B7 R307 RES 27B2 R475 RES 31B6 R644 RES 6A2 RP10 RPAK4P 24C7 24C8 24C8 ZT43 HOLE_VIA 4A4
R139 RES 9C7 R308 RES 31C6 R476 RES 31B7 R645 RES 8B8 RP11 RPAK4P 5B1 5D1 ZT44 HOLE_VIA 4A4
R140 RES 13C5 R309 RES 31D8 R477 RES 30D1 R646 RES 8B8 RP12 RPAK4P 24B7 24B8 ZT45 HOLE_VIA 4A4
R141 RES 13C8 R310 RES 34B6 R478 RES 30D8 R647 RES 19A4 RP13 RPAK4P 14C1 ZT46 HOLE_VIA 4A4
R142 RES 20B4 R311 RES 27B7 R479 RES 30B3 R648 RES 19A4 RP14 RPAK4P 24C7 24D7 24D8 ZT47 HOLE_VIA 4A4
R143 RES 35B3 R312 RES 10C3 R480 RES 30D1 R649 RES 6B1 RP15 RPAK4P 14B4 14B4 14B5 14B5 ZT48 HOLE_VIA 4B3
R144 RES 10A7 R313 RES 22A6 R481 RES 30D8 R650 RES 28A6 RP16 RPAK4P 14A4 14B4 14B5 14B5 ZT49 HOLE_VIA 4B3
R145 RES 13B1 R314 RES 32C6 R482 RES 28C7 R651 RES 33D7 RP17 RPAK4P 14C1 14D1 ZT50 HOLE_VIA 4B3
R146 RES 13D8 R315 RES 27B4 R483 RES 28C8 R652 RES 34B2 RP18 RPAK4P 13A7 13B7 ZT51 HOLE_VIA 4B3
R147 RES 13B1 R316 RES 31C7 R484 RES 28C7 R653 RES 29D6 RP19 RPAK4P 13A7 13B7 ZT52 HOLE_VIA 4B3
R148 RES 13B1 R317 RES 34C6 R485 RES 28C7 R654 RES 29D7 RP20 RPAK4P 13C1 13D1 ZT53 HOLE_VIA 4B3
R149 RES 21C4 R318 RES 34B6 R486 RES 31A7 R655 RES 29C6 RP21 RPAK4P 13B1 13C1 ZT54 HOLE_VIA 4B3
R150 RES 20B4 R319 RES 34D7 R487 RES 31A5 R656 RES 29C7 RP22 RPAK4P 9C2 9D2 9D2 ZT55 HOLE_VIA 4B3
R151 RES 9A4 R320 RES 22A6 R488 RES 31B7 R657 RES 31C1 RP23 RPAK4P 13B1 13C1 ZT56 HOLE_VIA 4B3
R152 RES 9A6 R321 RES 32C5 R489 RES 30B7 R658 RES 24D4 RP24 RPAK4P 9C2 9D2 9D2 ZT57 HOLE_VIA 4A3
R153 RES 10A7 R322 RES 32C6 R490 RES 30C8 R659 RES 28A7 RP25 RPAK4P 9C2 9C2 9D2 15A8 ZT58 HOLE_VIA 4A3
R154 RES 10A6 R323 RES 27B4 R491 RES 30B7 R660 RES 31C1 RP26 RPAK4P 10B4 10B5 10B5 ZT59 HOLE_VIA 4A3
R155 RES 19B8 R324 RES 30A3 R492 RES 30C7 R661 RES 18B4 RP27 RPAK4P 10A4 10A5 10A5 ZT60 HOLE_VIA 4A3
R156 RES 21D4 R325 RES 25D3 R493 RES 23D3 R662 RES 18D8 RP28 RPAK4P 15A8 15B8 15C8 15D8 ZT61 HOLE_VIA 4A3
R157 RES 20C1 R326 RES 27B3 R494 RES 33A8 R663 RES 31C6 RP29 RPAK4P 10A4 10B4 10B5 ZT62 HOLE_VIA 4A3
R158 RES 20C1 R327 RES 27B4 R495 RES 23D3 R664 RES 24B6 RP30 RPAK4P 10A4 10A5 10B4 10B5 ZT63 HOLE_VIA 4B3
R159 RES 21B6 R328 RES 27B2 R496 RES 30B1 R665 RES 31C6 RP31 RPAK4P 10D4 10D4 10D5 10D5 ZT64 HOLE_VIA 4B3
R160 RES 21A6 R329 RES 34C6 R497 RES 30B1 R666 RES 26B4 RP32 RPAK4P 10D4 10D4 10D5 10D5 ZT65 HOLE_VIA 4B3
R161 RES 9A4 R330 RES 34D7 R498 RES 24D2 R667 RES 26B4 RP33 RPAK4P 10C4 10C4 10C5 10C5 ZT66 HOLE_VIA 4B3
R162 RES 9A4 R331 RES 27D7 R499 RES 24D2 R668 RES 29C3 RP34 RPAK4P 10C4 10C4 10C5 10C5 ZT67 HOLE_VIA 4B3
R163 RES 13D4 R332 RES 31A5 R500 RES 22C5 R669 RES 18D8 RP35 RPAK4P 28A8 ZT68 HOLE_VIA 4B3
R164 RES 21C4 R333 RES 20B6 R501 RES 23C7 R670 RES 18D8 RP36 RPAK4P 28B8 ZT69 HOLE_VIA 4B3
R165 RES 21C4 R334 RES 24B5 R502 RES 24A4 R671 RES 22C3 RP37 RPAK4P 26B8 ZT70 HOLE_VIA 4B3
R166 RES 21D4 R335 RES 32C6 R503 RES 24A3 R672 RES 28D5 RP38 RPAK10P2C 18A8 ZT71 HOLE_VIA 4B3
R167 RES 20C4 R336 RES 31D7 R504 RES 15C1 R673 RES 28A4 RP39 RPAK4P 26A7 ZT72 HOLE_VIA 4A3
R168 RES 9A4 R337 RES 34B4 R505 RES 7C4 R674 RES 28A3 RP40 RPAK4P 15B8 15C1 15C2 ZT73 HOLE_VIA 4A3
R169 RES 13A1 R338 RES 34D8 R506 RES 7C4 R675 RES 18A7 RP41 RPAK4P 15C8 ZT74 HOLE_VIA 4A3
R170 RES 13C4 R339 RES 20C6 R507 RES 7C4 R676 RES 18D7 RP42 RPAK4P 15B8 15C8 15D1 ZT75 HOLE_VIA 4A3
R171 RES 21B4 R340 RES 20C7 R508 RES 7D4 R677 RES 31B2 RP43 RPAK4P 24C7 24C8 24D8 ZT76 HOLE_VIA 4A3
C R172
R173
R174
RES
RES
RES
21B4
19B2
20C4
R341
R342
R343
RES
RES
RES
32D6
27A7
27A6
R509
R510
R511
RES
RES
RES
7A6
7C6
7C6
R678
R679
R680
RES
RES
RES
31C4
31A5
31A6
RP44
RP45
RP46
RPAK4P
RPAK4P
RPAK4P
24C7 24C8 24D7
8D8
8D8
ZT100
ZT101
ZT102
HOLE_VIA
HOLE_VIA
HOLE_VIA
4A3
4B2
4B2
C
R175 RES 5D8 R344 RES 27A7 R512 RES 7C6 R681 RES 31A5 RP47 RPAK4P 15B8 15C8 ZT103 HOLE_VIA 4B2
R176 RES 9A5 R345 RES 27B2 R513 RES 7D6 R682 RES 31A6 RP48 RPAK4P 23B1 ZT104 HOLE_VIA 4B2
R177 RES 9A4 R346 RES 34C5 R514 RES 7D5 R683 RES 31B5 RP49 RPAK4P 30C1 30C1 30D1 ZT105 HOLE_VIA 4B2
R178 RES 9D5 R347 RES 20C7 R515 RES 7C5 R684 RES 18B7 RP50 RPAK10P2C 23B5 ZT106 HOLE_VIA 4B2
R179 RES 21B4 R348 RES 35C5 R516 RES 7C4 R685 RES 31B3 RP51 RPAK4P 23B1 23C3 26C8 ZT107 HOLE_VIA 4B2
R180 RES 21A5 R349 RES 35D4 R517 RES 7C4 R686 RES 30D5 RP52 RPAK4P 30C8 30D8 ZT108 HOLE_VIA 4B2
R181 RES 13B1 R350 RES 35B4 R518 RES 5D1 R687 RES 30B2 RP53 RPAK10P2C 23B5 ZT109 HOLE_VIA 4B2
R182 RES 26B3 R351 RES 35D5 R519 RES 7B4 R688 RES 30B3 RP54 RPAK4P 26B3 26B4 26D2 ZT110 HOLE_VIA 4A2
R183 RES 21D7 R352 RES 35B5 R520 RES 7C5 R689 RES 30C8 RP55 RPAK4P 21B3 ZT111 HOLE_VIA 4A2
R184 RES 21B7 R353 RES 35C5 R521 RES 7C5 R690 RES 23A4 RP56 RPAK4P 21B3 ZT112 HOLE_VIA 4A2
R185 RES 19A5 R354 RES 35B7 R522 RES 7C5 R691 RES 23B7 RP57 RPAK4P 21B1 ZT114 HOLE_VIA 4A2
R186 RES 19A6 R355 RES 35B7 R523 RES 7D5 R692 RES 23C5 RP58 RPAK4P 21B1 ZT115 HOLE_VIA 4A2
R187 RES 20C4 R356 RES 32C7 R524 RES 7C6 R693 RES 23B5 RP59 RPAK4P 25C5 25C5 25D5 25D5 ZT116 HOLE_VIA 4A2
R188 RES 10A5 R357 RES 32C7 R525 RES 7C7 R694 RES 34C8 SH1 SHLD_3P_EMI 4D2
R189 RES 11A4 R358 RES 34B5 R526 RES 7C7 R695 RES 30D8 SP1 SPKR_CLIP_P84 4C3
R190 RES 21A7 R359 RES 12D2 R527 RES 7D7 R696 RES 30D1 SP2 SPKR_CLIP_P84 4C3
R191 RES 19A6 R360 RES 33D5 R528 RES 7A6 R697 RES 30B1 SP3 SPKR_CLIP_P84 4C2
R192 RES 11A6 R361 RES 24A6 R529 RES 7A6 R698 RES 30B1 SP4 SPKR_CLIP_P84 4C2
R193 RES 11A4 R362 RES 24B5 R530 RES 23D8 R699 RES 30D1 SP5 SPKR_CLIP_P84 4C2
R194 RES 15D4 R363 RES 32C7 R531 RES 23D7 R700 RES 30C1 SP6 SPKR_CLIP_P84 4C2
R195 RES 21A6 R364 RES 28B7 R532 RES 15C2 R701 RES 30B1 T1 XFR_ENET_1000BT 27B3
R196 RES 21C6 R365 RES 28A7 R533 RES 23C7 R702 RES 23A7 U1 SN74AUC1G04 7A7
R197 RES 21A7 R366 RES 28C7 R534 RES 23D7 R703 RES 27D5 U2 SN74AUC1G08 23A3
R198 RES 20C4 R367 RES 28C7 R535 RES 7C8 R704 RES 27D5 U3 SN74AUC1G08 23B3
R199 RES 10A4 R368 RES 28B7 R536 RES 7C7 R705 RES 27D4 U4 LTC3411 35A5
R200 RES 21B8 R369 RES 28D6 R537 RES 23D6 R706 RES 27D3 U5 TRA_SI3447DV 35A2
R201 RES 20A2 R370 RES 34B7 R538 RES 7C7 R707 RES 27D3 U6 SRAM_DDR_128KX36 8D2
R202 RES 11A6 R371 RES 31C4 R539 RES 25B3 R708 RES 23A4 U7 SRAM_DDR_128KX36 8D5
R203 RES 21C7 R372 RES 12D2 R540 RES 15A5 R709 RES 26A7 U8 LTC1761 20A7
R204 RES 21C7 R373 RES 35C7 R541 RES 7C7 R710 RES 26B7 U9 TRA_SI3447DV 35C1
R205 RES 21C7 R374 RES 20B5 R542 RES 25B3 R711 RES 26D7 U10 VREG_LT1962 15D6
R206 RES 20A4 R375 RES 24B6 R543 RES 14D5 R712 RES 26C5 U11 CBTV4020 11C2
R207 RES 15D7 R376 RES 29B2 R544 RES 14C1 R713 RES 26D4 U12 CBTV4020 11C4
R208 RES 21A6 R377 RES 27B7 R545 RES 35A5 R714 RES 26C4 U13 CBTV4020 11C5
R209 RES 21A7 R378 RES 20C8 R546 RES 35A4 R715 RES 26C4 U14 CBTV4020 11C7
R210 RES 21B7 R379 RES 33D5 R547 RES 14D1 R716 RES 26C4 U16 COMPARATOR_LMC7211 31C7
R211 RES 21B7 R380 RES 33C5 R548 RES 14D5 R717 RES 26C4 U17 FEPR_1MX8 10C2
R212 RES 21A8 R381 RES 24A5 R549 RES 14C1 R718 RES 26B3 U18 LTC1625 32C5
R213 RES 21B7 R382 RES 31C5 R550 RES 15A5 R719 RES 26B4 U19 LTC1778 20B7
R214 RES 21A7 R383 RES 31D3 R551 RES 35A4 R720 RES 26A4 U20 PWR_CNTRL_TPS2211 18D3
R215 RES 20A1 R384 RES 31C4 R552 RES 35A6 R721 RES 26A4 U21 MAX1717 34C5
B R216
R217
R218
RES
RES
RES
20A1
20B2
20D2
R385
R386
R387
RES
RES
RES
35D6
33C7
33C7
R553
R554
R555
RES
RES
RES
35A6
9C7
9B8
R722
R723
R724
RES
RES
RES
26A4
26A4
26A4
U22
U23
U24
COMPARATOR_LMC7211 32C7
MAX1715 35C4
AMP_MAX4172 31D5
B
R219 RES 20B4 R388 RES 28B5 R556 RES 9A8 R725 RES 26B4 U25 VREG_LP2951 32B3
R220 RES 20A7 R389 RES 33C5 R557 RES 9D8 R726 RES 26A4 U26 PCI1510GGU 18C5
R221 RES 21A6 R390 RES 32A2 R558 RES 9C8 R727 RES 34C8 U27 LTC3707 33C4
R222 RES 21B6 R391 RES 28A7 R559 RES 9B7 R728 RES 26C2 U28 TSB81BA3 28B6
R223 RES 21A6 R392 RES 28D7 R560 RES 9A8 R729 RES 26C2 U29 VREG_LP2951 32B5
R224 RES 21A6 R393 RES 28A5 R561 RES 9B2 R730 RES 34D6 U30 MAX1772 31B5
R225 RES 15D6 R394 RES 31D5 R562 RES 9B2 R731 RES 34D6 U31 VREG_LM2594 28D7
R226 RES 15D6 R395 RES 33D5 R563 RES 22C4 R732 RES 34D6 U32 7432 22A2 30A7 30A8
R227 RES 20D2 R396 RES 28C3 R564 RES 22C4 R733 RES 34D6 U33 LTC1761 28D8
R228 RES 21D7 R397 RES 28B4 R565 RES 9D7 R734 RES 34D6 U34 VREG_LT1962 28C8
R229 RES 20A4 R398 RES 35C4 R566 RES 9B8 R735 RES 34D6 U35 COMPARATOR_LMC7211 31A6
R230 RES 20A7 R399 RES 35D5 R567 RES 9A7 R736 RES 34D6 U36 FEPR_256KX8_ST72264_BGA 23D5
R231 RES 35D2 R400 RES 33C5 R568 RES 9B2 R737 RES 34D6 U37 EEPROM_16KX8_M24128B 23D3
R232 RES 21A8 R401 RES 33C4 R569 RES 25A4 R738 RES 34D6 U38 MAX6804 30B7
R233 RES 21B8 R402 RES 32A4 R570 RES 22D5 R739 RES 34D5 U39 M16C62 30D5
R234 RES 21B7 R403 RES 28C3 R571 RES 9C7 R740 RES 34D5 U40 OPAMP_MAX4236EUTT 23D7
R235 RES 21A7 R404 RES 28C3 R572 RES 9B7 R741 RES 26C8 U41 PI3B3257 34D4
R236 RES 20D1 R405 RES 28B4 R573 RES 9A7 R742 RES 31D4 U42 APOLLO483 5C5 6D5 6D7
R237 RES 20D1 R406 RES 31C5 R574 RES 9B1 R743 RES 31C4 U43 MAP31_612P 19D1 19D3 19D6 20C3 21D5
R238 RES 21B7 R407 RES 31C2 R575 RES 22D5 R744 RES 31D4 U44 INTREPID 9D4 10D7 13D3 13D7 14D4 14D8 15C4
R239 RES 21A7 R408 RES 35C5 R576 RES 22D3 R745 RES 31D4 16D4 16D7
R240 RES 20B1 R409 RES 28C7 R577 RES 22C3 R746 RES 31C3 U45 COMPARATOR_LMC7211 22C2
R241 RES 20B1 R410 RES 28B3 R578 RES 9C7 R747 RES 31C3 U46 CLK_GEN_CY25811 21A4
R242 RES 15D7 R411 RES 28A3 R579 RES 9B7 R748 RES 21C3 U47 VREG_LT1962 6B3
R243 RES 21A7 R412 RES 31B6 R580 RES 9B6 R749 RES 21C2 U48 ADM1031 25B4
R244 RES 19A4 R413 RES 31C4 R581 RES 9A7 R750 RES 21C2 U49 TRANSCEIVER_88E1111 27C6
R245 RES 19A4 R414 RES 31D5 R582 RES 9A7 R751 RES 21B2 U50 MAX1916 23A5
R246 RES 34B7 R415 RES 31C2 R583 RES 9B2 R752 RES 21D1 U51 LTC3405 27D4
R247 RES 34B7 R416 RES 33B5 R584 RES 22D4 R753 RES 23C3 U52 UPD720101_FBGA 26C6
R248 RES 34D5 R417 RES 33C3 R585 RES 22D4 R754 RES 22C2 U53 COMPARATOR_LMC7211 30A3
R249 RES 34D5 R418 RES 32B6 R586 RES 9C7 R755 RES 22C1 U54 OPAMP_LMC7111 31D3
R250 RES 34A5 R419 RES 28B3 R587 RES 9C6 R756 RES 22C1 U55 SIL1162 21C2
R251 RES 34D5 R420 RES 28B4 R588 RES 9B7 R757 RES 21B3 U56 CLK_GEN_CY28512 15B6
R252 RES 34A4 R421 RES 31B2 R589 RES 9A6 R758 RES 15C7 U1600 VREG_LT1962 16B2
R253 RES 27A7 R422 RES 31C2 R590 RES 9B2 R759 RES 15C7 XW1 SHORT 35A4
R254 RES 27A6 R423 RES 33C3 R591 RES 9B1 R760 RES 21C7 XW2 SHORT 34B1
R255 RES 34D5 R424 RES 33D2 R592 RES 25A3 R761 RES 25D8 XW4 SHORT 20B7
R256 RES 22B2 R425 RES 28B3 R593 RES 22D3 R762 RES 29D5 XW6 SHORT 32B5
R257 RES 34D5 R426 RES 33C4 R594 RES 22C3 R763 RES 18A7 XW7 SHORT 34B4
R258 RES 34D5 R427 RES 33D4 R595 RES 9B7 R764 RES 16D6 XW8 SHORT 35B6
A R259
R260
R261
RES
RES
RES
27C3
34D5
25C1
R428
R429
R430
RES
RES
RES
32A4
28A2
30A4
R596
R597
R598
RES
RES
RES
9A7
9B1
22C3
R765
R766
R767
RES
RES
RES
16D6
34D4
34D3
XW9 SHORT
XW11 SHORT
XW14 SHORT
34B4
33B4
22B8
NOTICE OF PROPRIETARY PROPERTY
A
R262 RES 23D6 R431 RES 33B6 R599 RES 15C4 R768 RES 34D3 XW15 SHORT 22A8
R263 RES 27B7 R432 RES 28A3 R600 RES 22D2 R769 RES 34D3 XW17 SHORT 25C7
R265 RES 29D6 R433 RES 28A2 R601 RES 19C8 R770 RES 10A3 XW18 SHORT 34C1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
R266 RES 30A4 R434 RES 29A3 R602 RES 5D2 R771 RES 10A3 XW20 SHORT 31B3 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
R267 RES 22B4 R435 RES 31B5 R603 RES 22D2 R772 RES 10A3 Y1 CRYSTAL 15A5 AGREES TO THE FOLLOWING
R268 RES 10C3 R436 RES 30B1 R604 RES 22D2 R773 RES 10A2 Y2 CRYSTAL_4PIN 21B4 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
R269 RES 30A4 R437 RES 33B6 R605 RES 21C4 R774 RES 18D4 Y3 CRYSTAL 27A7
R270 RES 30A3 R438 RES 27A5 R606 RES 5D2 R886 RES 15B7 Y4 CRYSTAL 23C6 II NOT TO REPRODUCE OR COPY IT
R271 RES 20B8 R439 RES 33C2 R607 RES 22C4 R887 RES 15B7 Y5 CRYSTAL 30B7
R272 RES 22B4 R440 RES 28A4 R608 RES 23A4 R888 RES 15C7 Y6 CRYSTAL_4PIN 30B3 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
R273 RES 34C5 R441 RES 31B2 R609 RES 6B4 R889 RES 15B7 Y7 CRYSTAL 26D4
R274 RES 33A3 R442 RES 30D1 R610 RES 22C1 R890 RES 15B6 ZT1 MTGHOLE 4D3 SIZE DRAWING NUMBER REV.
R275 RES 20B5 R443 RES 30B1 R611 RES 22C2 R891 RES 15B5 ZT3 MTGHOLE 4D4
R276
R277
R278
RES
RES
RES
20B5
20B8
27C7
R444
R445
R446
RES
RES
RES
30B3
30A4
30C1
R612
R613
R614
RES
RES
RES
33A8
21A5
21A4
R902
R1000
R1350
RES
RES
RES
30A4
28C5
13C8
ZT4
ZT5
ZT6
MTGHOLE
MTGHOLE
MTGHOLE
4C4
4D4
4D4 APPLE COMPUTER INC.
D 051-6469 F
SCALE SHT OF
NONE 44 44
8 7 6 5 4 3 2 1
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