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Apple Proprietary Schematics

This document appears to be a table of contents for a technical manual or design document. It lists 7 sections with brief descriptions, including BOM Configuration, DEBUG LEDs, CPU Clock/Misc/JTAG/CFG, and several audio-related sections. Each entry also includes the initials of the person who last modified that section and the date.

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Ricardo Germano Moreira

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0% found this document useful (0 votes)

69 views86 pages

Apple Proprietary Schematics

Uploaded by

Ricardo Germano Moreira

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

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8 7 6 5 4 3 2 1

CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION

J16 MLB_IG
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2013-03-22

LAST_MODIFIED=Fri Mar 22 11:24:26 2013

(.csa) Date (.csa) Date

D Page
TABLE_TABLEOFCONTENTS_HEAD
Contents Sync Page Contents
TABLE_TABLEOFCONTENTS_HEAD
Sync D
1 12/03/2012 55 03/13/2013

TABLE_TABLEOFCONTENTS_ITEM
1 Table of Contents J16_MLB
TABLE_TABLEOFCONTENTS_ITEM
49 I and V Sense(Continued) J16_TONY
2 01/29/2013 56 01/11/2013

TABLE_TABLEOFCONTENTS_ITEM
2 BOM Configuration J16_DINI
TABLE_TABLEOFCONTENTS_ITEM
50 Temperature Sensors J16_FIYIN
3 02/11/2013 60 01/07/2013

TABLE_TABLEOFCONTENTS_ITEM
3 DEBUG LEDS J16_MAX
TABLE_TABLEOFCONTENTS_ITEM
51 System Fan J16_JERRY
4 02/11/2013 61 03/07/2013

TABLE_TABLEOFCONTENTS_ITEM
4 Holes/PD parts J16_MAX
TABLE_TABLEOFCONTENTS_ITEM
52 AUDIO: CODEC/REGULATORS J16_DIRK
5 01/14/2013 62 03/07/2013

TABLE_TABLEOFCONTENTS_ITEM
5 CPU DMI/PEG/FDI/RSVD J16_DINI
TABLE_TABLEOFCONTENTS_ITEM
53 AUDIO: HEADPHONE AMP J16_DIRK
6 01/14/2013 63 03/07/2013

TABLE_TABLEOFCONTENTS_ITEM
6 CPU Clock/Misc/JTAG/CFG J16_DINI
TABLE_TABLEOFCONTENTS_ITEM
54 AUDIO: LEFT SPKR AMP J16_DIRK
7 01/14/2013 64 03/07/2013

TABLE_TABLEOFCONTENTS_ITEM
7 CPU DDR3 Interfaces J16_DINI
TABLE_TABLEOFCONTENTS_ITEM
55 AUDIO: RIGHT SPKR AMP J16_DIRK
8 01/14/2013 65 03/07/2013

TABLE_TABLEOFCONTENTS_ITEM
8 CPU Power J16_DINI
TABLE_TABLEOFCONTENTS_ITEM
56 AUDIO: Jack, Mikey, CHS Switch J16_DIRK
9 01/14/2013 66 03/07/2013

TABLE_TABLEOFCONTENTS_ITEM
9 CPU Ground J16_DINI
TABLE_TABLEOFCONTENTS_ITEM
57 Audio: Spkr/Mic Conn. J16_DIRK
10 01/14/2013 67 03/07/2013

TABLE_TABLEOFCONTENTS_ITEM
10 CPU Decoupling J16_DINI
TABLE_TABLEOFCONTENTS_ITEM
58 AUDIO: Detects/Grounding J16_DIRK
11 01/21/2013 68 03/07/2013

TABLE_TABLEOFCONTENTS_ITEM
11 PCH RTC/HDA/JTAG/SATA/CLK J16_KENNY
TABLE_TABLEOFCONTENTS_ITEM
59 AUDIO: Speaker ID J16_DIRK
12 01/21/2013 69 03/04/2013

TABLE_TABLEOFCONTENTS_ITEM
12 PCH DMI/FDI/PM/GFX/PCI J16_KENNY
TABLE_TABLEOFCONTENTS_ITEM
60 Power Connectors / VReg G3Hot J16_ROSSANA
13 01/21/2013 70 03/21/2013

TABLE_TABLEOFCONTENTS_ITEM
13 PCH PCI-E/USB J16_KENNY
TABLE_TABLEOFCONTENTS_ITEM
61 VReg CPU VCC Cntl J16_ROSSANA
14 03/07/2013 71 03/21/2013

TABLE_TABLEOFCONTENTS_ITEM
14 PCH GPIO/MISC/NCTF J16_KENNY
TABLE_TABLEOFCONTENTS_ITEM
62 VReg CPU VCC Phases J16_ROSSANA
15 01/21/2013 73 03/04/2013

TABLE_TABLEOFCONTENTS_ITEM
15 PCH Power J16_KENNY
TABLE_TABLEOFCONTENTS_ITEM
63 VReg VDDQ S3 J16_ROSSANA
16 01/21/2013 74 03/04/2013

TABLE_TABLEOFCONTENTS_ITEM
16 PCH Grounds J16_KENNY
TABLE_TABLEOFCONTENTS_ITEM
64 VREG 1V05 S0 / 1V5 S0 J16_ROSSANA
17 01/21/2013 76 03/04/2013
17 PCH DECOUPLING 65 VReg 3.3V S5/5V S4
C TABLE_TABLEOFCONTENTS_ITEM

18
18
CPU & PCH XDP
J16_KENNY

J16_KENNY
03/18/2013
TABLE_TABLEOFCONTENTS_ITEM

66
81
LCD Backlight Driver (LP8561)
J16_ROSSANA

J16_LINDA
01/22/2013 C
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

19 01/21/2013 84 02/11/2013

TABLE_TABLEOFCONTENTS_ITEM
19 Chipset Support J16_KENNY
TABLE_TABLEOFCONTENTS_ITEM
67 FET-Controlled S0 and S4 J16_MAX
20 01/21/2013 85 02/21/2013

TABLE_TABLEOFCONTENTS_ITEM
20 Project Chipset Support J16_KENNY
TABLE_TABLEOFCONTENTS_ITEM
68 PM Regulator Enables J16_AARON
21 12/11/2012 86 02/21/2013

TABLE_TABLEOFCONTENTS_ITEM
21 CPU Memory S3 Support J16_NICK
TABLE_TABLEOFCONTENTS_ITEM
69 PM Power Good J16_AARON
22 01/10/2013 100 02/11/2013

TABLE_TABLEOFCONTENTS_ITEM
22 DDR3 VREF MARGINING J16_NICK
TABLE_TABLEOFCONTENTS_ITEM
70 Power Aliases J16_MAX
23 01/10/2013 102 02/11/2013

TABLE_TABLEOFCONTENTS_ITEM
23 DDR3 SO-DIMM Connector A J16_NICK
TABLE_TABLEOFCONTENTS_ITEM
71 Signal Aliases J16_MAX
25 01/10/2013 104 02/11/2013

TABLE_TABLEOFCONTENTS_ITEM
24 DDR3 SO-DIMM CONNECTOR B J16_NICK
TABLE_TABLEOFCONTENTS_ITEM
72 Unused Signal Aliases J16_MAX
27 01/10/2013 105 02/11/2013

TABLE_TABLEOFCONTENTS_ITEM
25 DDR3 ALIASES AND BITSWAPS J16_NICK
TABLE_TABLEOFCONTENTS_ITEM
73 Functional / ICT Test J16_MAX
28 02/11/2013 110 12/03/2012

TABLE_TABLEOFCONTENTS_ITEM
26 Thunderbolt Host (1 of 2) J16_MAX
TABLE_TABLEOFCONTENTS_ITEM
74 J16 RULE DEFINITIONS J16_MLB
29 02/11/2013 111 01/10/2013

TABLE_TABLEOFCONTENTS_ITEM
27 Thunderbolt Host (2 of 2) J16_MAX
TABLE_TABLEOFCONTENTS_ITEM
75 DDR3 Constraints J16_NICK
30 02/11/2013 112 01/10/2013

TABLE_TABLEOFCONTENTS_ITEM
28 Thunderbolt Power Support J16_MAX
TABLE_TABLEOFCONTENTS_ITEM
76 CPU CONSTRAINTS J16_NICK
32 02/11/2013 113 01/10/2013

TABLE_TABLEOFCONTENTS_ITEM
29 Thunderbolt Connector A J16_MAX
TABLE_TABLEOFCONTENTS_ITEM
77 PCH PCIe/DMI Constaints J16_NICK
33 02/11/2013 114 01/10/2013

TABLE_TABLEOFCONTENTS_ITEM
30 Thunderbolt Connector B J16_MAX
TABLE_TABLEOFCONTENTS_ITEM
78 SATA/FDI/XDP Constraints J16_NICK
34 02/11/2013 115 12/03/2012

TABLE_TABLEOFCONTENTS_ITEM
31 TBT DDC Crossbar J16_MAX
TABLE_TABLEOFCONTENTS_ITEM
79 PCH and BR Constraints J16_MLB
35 01/11/2013 116 12/03/2012

TABLE_TABLEOFCONTENTS_ITEM
32 AIRPORT/BT J16_FIYIN
TABLE_TABLEOFCONTENTS_ITEM
80 USB/Ethernet/SD Constraints J16_MLB
37 01/07/2013 117 01/10/2013

TABLE_TABLEOFCONTENTS_ITEM
33 SATA/SSD Connectors J16_JERRY
TABLE_TABLEOFCONTENTS_ITEM
81 SMBus/Sensor Constraints J16_NICK
38 01/07/2013 118 01/10/2013

TABLE_TABLEOFCONTENTS_ITEM
34 HDD Connector J16_JERRY
TABLE_TABLEOFCONTENTS_ITEM
82 VReg Constraints J16_NICK
39 02/11/2013 119 12/14/2012
B TABLE_TABLEOFCONTENTS_ITEM
35
40
ETHERNET PHY (CAESAR IV) J16_MAX
02/11/2013
TABLE_TABLEOFCONTENTS_ITEM
83
120
CPU VReg Constraints J16_ROSSANA
12/20/2012
B
TABLE_TABLEOFCONTENTS_ITEM
36 Ethernet Support & Connector J16_MAX
TABLE_TABLEOFCONTENTS_ITEM
84 Platform VReg Constraints J16_ROSSANA
41 02/11/2013 121 12/03/2012

TABLE_TABLEOFCONTENTS_ITEM
37 SD READER CONNECTOR J16_MAX
TABLE_TABLEOFCONTENTS_ITEM
85 TBT/DP Constraints J16_MLB
42 02/11/2013 123 12/03/2012

TABLE_TABLEOFCONTENTS_ITEM
38 Camera Controller J16_MAX
TABLE_TABLEOFCONTENTS_ITEM
86 BLC Constraints J16_MLB
43 02/11/2013

TABLE_TABLEOFCONTENTS_ITEM
39 Camera Controller Support J16_MAX
44 02/11/2013

TABLE_TABLEOFCONTENTS_ITEM
40 Internal DP Support J16_MAX
45 02/11/2013

TABLE_TABLEOFCONTENTS_ITEM
41 Internal DP MUXing J16_MAX
46 03/18/2013

TABLE_TABLEOFCONTENTS_ITEM
42 EXTERNAL USB PORTS A & B J16_KOSECOFF
47 03/18/2013

TABLE_TABLEOFCONTENTS_ITEM
43 EXTERNAL USB PORTS C & D J16_KOSECOFF
50 03/13/2013

TABLE_TABLEOFCONTENTS_ITEM
44 SMC J16_TONY
51 03/13/2013

TABLE_TABLEOFCONTENTS_ITEM
45 SMC Support J16_TONY
52 03/13/2013

TABLE_TABLEOFCONTENTS_ITEM
46 SPI and Debug Connector J16_TONY
53 03/13/2013

TABLE_TABLEOFCONTENTS_ITEM
47 SMBus Connections J16_TONY
54 03/13/2013

TABLE_TABLEOFCONTENTS_ITEM
48 I and V Sense J16_TONY

A A
DRAWING TITLE
SCHEM,MLB IG,J16
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING
TITLE=J16 MLB_IG
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 123
ABBREV=DRAWING III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
LAST_MODIFIED=Fri Mar 22 11:24:26 2013 DRAWING
IV ALL RIGHTS RESERVED 1 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Main BOM Variants Bar Code Labels / EEEE #’s

TABLE_BOMGROUP_HEAD

BOM NUMBER BOM NAME BOM OPTIONS TABLE_5_HEAD

TABLE_BOMGROUP_ITEM
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
985-0052 PCBA,MLB_IG,DEV,J16 DEVELOPMENT,J16_DEVEL TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
825-7896 1 MLB LABEL,2D EEEE_FF3T CRITICAL EEEE:FF3T
639-4515 PCBA,MLB_IG,J16 J16,J16_COMMON,CPU:GOOD,SSD:Y,EEEE:FF3T TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
825-7896 1 MLB LABEL,2D EEEE_FGY0 CRITICAL EEEE:FGY0
639-4704 PCBA,MLB_IG,BETTER,J16 J16,J16_COMMON,CPU:BETTER,SSD:Y,EEEE:FGWY TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
825-7896 1 MLB LABEL,2D EEEE_FGWY CRITICAL EEEE:FGWY
639-4705 PCBA,MLB_IG,CTO,J16 J16,J16_COMMON,CPU:CTO,SSD:Y,EEEE:FGY0

D D

Schematic / PCB #’s

TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

BOM Groups 051-0164 1 SCH,MLB_IG,J16 SCH CRITICAL J16
TABLE_5_ITEM

TABLE_BOMGROUP_HEAD TABLE_5_ITEM

BOM GROUP BOM OPTIONS 820-3588 1 PCBF,MLB_IG,J16 PCB CRITICAL J16

TABLE_BOMGROUP_ITEM

J16_COMMON COMMON,ALTERNATE,J16_COMMON1,J16_COMMON2,J16_PROGPARTS
TABLE_BOMGROUP_ITEM

J16_COMMON1 XDP,SPEAKERID,TBTHV:P12V,CPUVCC:3PHASE
TABLE_BOMGROUP_ITEM
Alternates
J16_COMMON2 VDDQ:P1V35 ADD ’J16_PRODUCTION’ AT REVA RELEASE TABLE_ALT_HEAD

TABLE_BOMGROUP_ITEM

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

J16_PROGPARTS SMC:PROG,BOOTROM:PROG,T29ROM:PROG,CIVROM:PROG,CAMROM:PROG PART NUMBER
TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM

TABLE_5_HEAD

128S0368 128S0365 ALL 150UF AL POLY

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_ITEM

TABLE_5_ITEM

138S0681 138S0638 ALL Taiyo 10uf 805 alt

337S4515 1 CRW,QEUZ,EEU2,C0,2.7G,65W,4+3,1.15,4M,BGA U0500 CRITICAL CPU:GOOD TABLE_ALT_ITEM

TABLE_5_ITEM

197S0479 197S0478 Y4200 12 MHz Cam. Xtal

335S0862 1 IC,SERIAL FLASH,2MBIT,2.7V,REV F U3990 CRITICAL CIVROM:BLANK

TABLE_5_ITEM

341S3778 1 IC,CAMERA,FLASH,V7229,J16 U4202 CRITICAL CAMROM:PROG

TABLE_5_ITEM

335S0852 1 IC,FLASH,SPI,1MBIT,3V3 U4202 CRITICAL CAMROM:BLANK

A SYNC_MASTER=J16_DINI SYNC_DATE=01/29/2013 A
PAGE TITLE

BOM Configuration
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

GPU GOOD Led VIDEO ON Led

S5 Led ALL_SYS_PWRGD Led =PP3V3_S0_LED
D =PP3V3_S4_LED
70 3
70 3 =PP3V3_S0_LED
D
70 =PP3V3_S5_LED
70

1
R0302 R0303
1

1K
R0304
1

1K
1
R0301
1K
1K
5%
1/16W
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5% MF-LF 2 402 2 402
1/16W 2 402 GPU_PRESENT_R
MF-LF
2 402
CORE_VOLTAGES_ON_R LCD_SHOULD_ON_R
A SILK_PART=3
ITS_PLUGGED_IN CRITICAL
A SILK_PART=2 CRITICAL LE0303
A
SILK_PART=1 CRITICAL LE0302 GREEN-3.6MCD CRITICAL
LE0301 K
GREEN-3.6MCD
2.0X1.25MM-SM
K 2.0X1.25MM-SM
A SILK_PART=4
GREEN-3.6MCD
K
2.0X1.25MM-SM
CORE_VOLTAGES_ON
GPU_PRESENT_DRAIN
LE0304
GREEN-3.6MCD
6 K 2.0X1.25MM-SM
3 CRITICAL This LED is a GPIO driven from
D the southbridge that indicates
that chipset has enumerated graphics
D CRITICAL Q0302
Q0302 2
2N7002DW-X-G VIDEO_ON_L
2N7002DW-X-G 18 14 IN GPU_GOOD G S SOT-363 IN 40

69 44 21 ALL_SYS_PWRGD 5 G S SOT-363
IN
1
4

C C

B B

A SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
PAGE TITLE

DEBUG LEDS
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

CPU HEATSINK MOUNTING FEATURES WIRELESS CARD MTG HOLES

998-4560 (Plated holes, 2.3mm inner diameter, 4.3mm pad)
SH0473 SH0474 SH0475 SH0476
STDOFF-4.5OD.98H-1.1-3.40-TH CRITICAL STDOFF-4.5OD.98H-1.1-3.40-TH CRITICAL
CRITICAL STDOFF-4.5OD.98H-1.1-3.40-TH CRITICAL STDOFF-4.5OD.98H-1.1-3.40-TH
1 1 1 1
ZH0421 ZH0422 D
D 5P5R1P9-4P3B-NSP
1
5P5R1P9-4P3B-NSP
1

HEATSINK STABILITY MOUNTING FEATURES

(860-1532)

CRITICAL
CRITICAL
SH0477 SH0479
STDOFF-4.5OD.98H-1.1-3.40-TH
STDOFF-4.5OD.98H-1.1-3.40-TH
1
1

C C

Rear Cover
998-4559 (Plated holes, 4mm inner diameter, 8mm pad)
998-5089 (ZH0414) near BLC has slightly larger hole to allow for grommet
ZH0413 ZH0415 ZH0416 ZH0414
7P0R4P0-8P0B-NSP 7P0R4P0-8P0B-NSP
1 7P0R4P0-8P0B-NSP 7P0R4P6-8P0B-NSP
1 1 1

B B

SSD STANDOFF
APN: 860-1624
SSD:Y
CRITICAL
NUT0413
STDOFF-4.5OD2.2ID-6.5H-SM
1

A SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
PAGE TITLE

Holes/PD parts
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

1 1
OMIT_TABLE R0510 OMIT_TABLE R0531
24.9 10k
U0500 1% U0500 5%
1/16W 1/16W
HASWELL MF-LF HASWELL MF-LF
BGA 402 BGA 402
2 2

77 12 DMI_S2N_N<0> AB2 DMI_RX0* SYM 1 OF 12 PEG_RCOMP AH6 76 CPU_PEG_RCOMP 71 TP_DP_IG_B_MLN<0> C25 DDIB_TXN0 SYM 10 OF 12 EDP_AUXN F15 TP_DP_IG_A_AUXCHN 72
IN
77 12 IN DMI_S2N_N<1> AB3 DMI_RX1* 71 TP_DP_IG_B_MLP<0> D25 DDIB_TXP0 EDP_AUXP F14 TP_DP_IG_A_AUXCHP 72

77 12 IN DMI_S2N_N<2> AC3 DMI_RX2* PEG_RX0* E10 =PEG_D2R_N<0> IN 72 71 TP_DP_IG_B_MLN<1> A25 DDIB_TXN1 EDP_HPD E14 DP_IG_A_HPD_L
77 12 IN DMI_S2N_N<3> AC1 DMI_RX3* PEG_RX1* C10 =PEG_D2R_N<1> IN 72 71 TP_DP_IG_B_MLP<1> B25 DDIB_TXP1
PEG_RX2* B10 =PEG_D2R_N<2> TP_DP_IG_B_MLN<2> C24 DDIB_TXN2 EDP_TXN0 C14 TP_DP_IG_A_MLN<0>

EDP
72 71 72

D 77 12 IN DMI_S2N_P<0> AB1 DMI_RX0 PEG_RX3* E9 =PEG_D2R_N<3>

IN
IN 72 71 TP_DP_IG_B_MLP<2> D24 DDIB_TXP2 EDP_TXN1 A12 TP_DP_IG_A_MLN<1> 72 D
77 12 IN DMI_S2N_P<1> AB4 DMI_RX1 PEG_RX4* D9 =PEG_D2R_N<4> IN 72 71 TP_DP_IG_B_MLN<3> A24 DDIB_TXN3
EDP_TXP0 D14 TP_DP_IG_A_MLP<0> 72

DIGITAL DISPLAY INTERFACES

77 12 IN DMI_S2N_P<2> AC4 DMI_RX2 PEG_RX5* B9 =PEG_D2R_N<5> IN 72 71 TP_DP_IG_B_MLP<3> B24 DDIB_TXP3
EDP_TXP1 B12 TP_DP_IG_A_MLP<1> 72
77 12 IN DMI_S2N_P<3> AC2 DMI_RX3 PEG_RX6* L5 =PEG_D2R_N<6> IN 72

PEG_RX7* L2 =PEG_D2R_N<7> TP_DP_IG_C_MLN<0> C21 DDIC_TXN0 PPVCOMP_S0_CPU

DMI
IN 72 71 5 8

77 12 OUT DMI_N2S_N<0> AF2 DMI_TX0* PEG_RX8* M4 =PEG_D2R_N<8> IN 72 71 TP_DP_IG_C_MLP<0> D21 DDIC_TXP0

DMI_N2S_N<1> AF4 L4 =PEG_D2R_N<9> TP_DP_IG_C_MLN<1> A21 1
77 12 OUT DMI_TX1* PEG_RX9* IN 72 71 DDIC_TXN1 R0530
77 12 OUT DMI_N2S_N<2> AG4 DMI_TX2* PEG_RX10* M2 =PEG_D2R_N<10> IN 72 71 TP_DP_IG_C_MLP<1> B21 DDIC_TXP1 24.9
1%
77 12 OUT DMI_N2S_N<3> AG2 DMI_TX3* PEG_RX11* V5 =PEG_D2R_N<11> IN 72 71 TP_DP_IG_C_MLN<2> C20 DDIC_TXN2 1/16W
MF-LF
PEG_RX12* V4 =PEG_D2R_N<12> IN 72 71 TP_DP_IG_C_MLP<2> D20 DDIC_TXP2 2
402

77 12 OUT DMI_N2S_P<0> AF1 DMI_TX0 PEG_RX13* V1 =PEG_D2R_N<13> IN 72 71 TP_DP_IG_C_MLN<3> A20 DDIC_TXN3

EDP_RCOMP AG6 76 CPU_EDP_RCOMP
77 12 OUT DMI_N2S_P<1> AF3 DMI_TX1 PEG_RX14* Y3 =PEG_D2R_N<14> IN 72 71 TP_DP_IG_C_MLP<3> B20 DDIC_TXP3
EDP_DISP_UTIL E12 TP_EDP_DISP_UTIL
77 12 OUT DMI_N2S_P<2> AG3 DMI_TX2 PEG_RX15* Y2 =PEG_D2R_N<15> IN 72

77 12 OUT DMI_N2S_P<3> AG1 DMI_TX3 71 TP_DP_IG_D_MLN<2> C16 DDID_TXN2

PEG_RX0 F10 =PEG_D2R_P<0> IN 72 71 TP_DP_IG_D_MLP<2> D16 DDID_TXP2
FDI_TXN0 C12 TP_DP_IG_A_MLN<2> 72
PEG_RX1 D10 =PEG_D2R_P<1> IN 72 71 TP_DP_IG_D_MLN<3> A16 DDID_TXN3
FDI_CSYNC F11 FDI_CSYNC FDI_TXP0 D12 TP_DP_IG_A_MLP<2>

FDI
78 12 IN 72
PEG_RX2 A10 =PEG_D2R_P<2> TP_DP_IG_D_MLP<3> B16 DDID_TXP3

FDI
IN 72 71
FDI_TXN1 A14 TP_DP_IG_A_MLN<3> 72
PEG_RX3 F9 =PEG_D2R_P<3> IN 72
71 TP_DP_IG_D_MLN<0> C17 DDID_TXN0 FDI_TXP1 B14 TP_DP_IG_A_MLP<3> 72
78 12 IN FDI_INT F12 DISP_INT PEG_RX4 C9 =PEG_D2R_P<4> IN 72
71 TP_DP_IG_D_MLP<0> D17 DDID_TXP0
PEG_RX5 A9 =PEG_D2R_P<5> IN 72
71 TP_DP_IG_D_MLN<1> A17 DDID_TXN1
PEG_RX6 M5 =PEG_D2R_P<6> IN 72
71 TP_DP_IG_D_MLP<1> B17 DDID_TXP1
PEG_RX7 L1 =PEG_D2R_P<7> IN 72
Port D pins out of order
PEG_RX8 M3 =PEG_D2R_P<8> IN 72
to match Intel symbol.
PEG_RX9 L3 =PEG_D2R_P<9> IN 72

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_RX10 M1 =PEG_D2R_P<10> IN 72

PEG_RX11 Y5 =PEG_D2R_P<11> IN 72

C PEG_RX12
PEG_RX13
V3

V2
=PEG_D2R_P<12>
=PEG_D2R_P<13>
IN
IN
72

72
C
PEG_RX14 Y4 =PEG_D2R_P<14> IN 72

PEG_RX15 Y1 =PEG_D2R_P<15> IN 72

PEG_TX0* B6 =PEG_R2D_C_N<0> OUT 72

OMIT_TABLE
PEG_TX1* C5 =PEG_R2D_C_N<1> OUT 72

PEG_TX2* E6 =PEG_R2D_C_N<2> OUT 72 U0500

PEG_TX3* D4 =PEG_R2D_C_N<3> OUT 72 HASWELL
G4 =PEG_R2D_C_N<4> BGA
PEG_TX4* OUT 72 NO_TEST NO_TEST
PEG_TX5* E3 =PEG_R2D_C_N<5> 72 5 CPU_DC_A3_B3 TRUE A3 SYM 12 OF 12 BF51 CPU_DC_BF51 1
OUT TP
J5 =PEG_R2D_C_N<6> CPU_DC_A4 A4
RESERVED BF52 CPU_DC_BE52_BF52 TP-P6
TP0531
PEG_TX6* OUT 72
TP 1 TRUE 5
G3 =PEG_R2D_C_N<7>
TP0500 TP-P6 BF53 CPU_DC_BE53_BF53
PEG_TX7* OUT 72 TRUE 5

PEG_TX8* J3 =PEG_R2D_C_N<8> OUT 72

TP 1 CPU_DC_A51 A51

J2 =PEG_R2D_C_N<9>
TP0510 TP-P6 CPU_DC_A52_B52 A52 C1 CPU_DC_C1_C2
PEG_TX9* OUT 72 5 TRUE TRUE 5

PEG_TX10* T6 =PEG_R2D_C_N<10> OUT 72 5 CPU_DC_A53_B53 TRUE A53 DAISY_CHAIN_NCTF C2 TRUE CPU_DC_C1_C2 5

PEG_TX11* R6 =PEG_R2D_C_N<11> OUT 72 C3 TRUE CPU_DC_B2_C3 5

PEG_TX12* R2 =PEG_R2D_C_N<12> OUT 72 5 CPU_DC_B2_C3 TRUE B2

PEG_TX13* R4 =PEG_R2D_C_N<13> OUT 72 5 CPU_DC_A3_B3 TRUE B3 C54 TRUE CPU_DC_B54_C54 5

PEG_TX14* T4 =PEG_R2D_C_N<14> OUT 72 D1 CPU_DC_D1 1

TP
T1 =PEG_R2D_C_N<15> CPU_DC_A52_B52 B52 TP-P6
TP0501
PEG_TX15* OUT 72 5 TRUE

5 CPU_DC_A53_B53 TRUE B53 DAISY_CHAIN_NCTF D54 CPU_DC_D54 1

TP
C6 =PEG_R2D_C_P<0> CPU_DC_B54_C54 B54 TP-P6
TP0511
PEG_TX0 OUT 72 5 TRUE

PEG_TX1 B5 =PEG_R2D_C_P<1> OUT 72

TP 1 CPU Daisy-Chain Strategy:
D6 =PEG_R2D_C_P<2>
TP0520 TP-P6 CPU_DC_BC1 BC1
PEG_TX2 OUT 72
Each corner of CPU has two testpoints.
PEG_TX3 E4 =PEG_R2D_C_P<3> OUT 72
TP 1 CPU_DC_BC54 BC54

G5 =PEG_R2D_C_P<4>
TP0530 TP-P6 CPU_DC_BD1_BE1 BD1
Other corner test signals connected in
PEG_TX4 72 5 TRUE
B PEG_TX5 E2 =PEG_R2D_C_P<5>
OUT
OUT 72
daisy-chain fashion. Continuity should
exist between both TP’s on each corner.
B
PEG_TX6 J6 =PEG_R2D_C_P<6> OUT 72 5 CPU_DC_BD54_BE54 TRUE BD54

PEG_TX7 G2 =PEG_R2D_C_P<7> OUT 72 5 CPU_DC_BD1_BE1 TRUE BE1

PEG_TX8 J4 =PEG_R2D_C_P<8> OUT 72 5 CPU_DC_BE2_BF2 TRUE BE2 RSVD132 AN35

NC
PEG_TX9 J1 =PEG_R2D_C_P<9> OUT 72 5 CPU_DC_BE3_BF3 TRUE BE3 RSVD133 AN37
NC
PEG_TX10 T5 =PEG_R2D_C_P<10> OUT 72 5 CPU_DC_BE52_BF52 TRUE BE52 RSVD134 AF9
NC
PEG_TX11 R5 =PEG_R2D_C_P<11> OUT 72 5 CPU_DC_BE53_BF53 TRUE BE53 RSVD135 AE9
NC
PEG_TX12 R1 =PEG_R2D_C_P<12> CPU_DC_BD54_BE54 TRUE BE54 RSVD136 G14
OUT 72 5
NC
PEG_TX13 R3 =PEG_R2D_C_P<13> 72 5 CPU_DC_BE2_BF2 TRUE BF2 RSVD137 G17
OUT NC
PEG_TX14 T3 =PEG_R2D_C_P<14> CPU_DC_BE3_BF3 TRUE BF3 RSVD138 AD45
OUT 72 5
NC
PEG_TX15 T2 =PEG_R2D_C_P<15> OUT 72 TP 1 CPU_DC_BF4 BF4 RSVD139 AG45
NC
TP0521 TP-P6

A SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013 A
PAGE TITLE

CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT_TABLE

D U0500
HASWELL
D
BGA
61 18 10 8 5 PPVCCIO_S0_CPU SYM 2 OF 12
NC
C51 PROC_DETECT* SM_RCOMP0 BB51 75 CPU_SM_RCOMP<0>
PLACE_NEAR=U0500.BB51:12.7mm
SM_RCOMP1 BB53 75 CPU_SM_RCOMP<1>

DDR3
1
R0601 76 45 CPU_CATERR_L G50 CATERR* SM_RCOMP2 BB52 75 CPU_SM_RCOMP<2>
PLACE_NEAR=U0500.BB53:12.7mm
62 OUT
PLACE_NEAR=U0500.BB52:12.7mm
5%

THERMAL
1/16W SM_DRAMRST* BE51 =MEM_RESET_L OUT 21
MF-LF 76 45 44 14 BI CPU_PECI G51 PECI 1
R0614
1
R0613
1
R0612
402
2 R0603 100 75 100
56 (IPU) PRDY* N53 XDP_CPU_PRDY_L OUT 18 1% 1% 1%
76 62 61 45 44 BI CPU_PROCHOT_L 2 1 76 CPU_PROCHOT_R_L E50 PROCHOT* 1/16W 1/16W 1/16W
(IPU) PREQ* N52 XDP_CPU_PREQ_L IN 18 MF-LF MF-LF MF-LF
5% 402 402 402
70 =PP1V5_S3_CPU_VCCDDR 1/16W 2 2 2
MF-LF 76 45 14 OUT PM_THRMTRIP_L D53 THERMTRIP*
402 (IPD) TCK N54 XDP_CPU_TCK IN 18 78

R0620 1 (IPU) TMS M51 XDP_CPU_TMS IN 18 78

76 12 IN PM_SYNC D52 PM_SYNC
1.82K (IPU) TRST* M53 XDP_CPU_TRST_L IN 18
1%
1/16W
MF-LF 76 18 14 IN CPU_PWRGD F50 PWRGOOD
TDI N49 XDP_CPU_TDI

PWR
402 (IPU) IN 18 78
2
PLACE_NEAR=R0621.2:1mm
TDO M49 XDP_CPU_TDO OUT 18 78
21 12 IN PM_MEM_PWRGD AP48 SM_DRAMPWROK

JTAG
PLACE_NEAR=U0500.AP48:51.562mm
1
DBR* F53 XDP_DBRESET_L OUT 18 19
R0621 76 18 14 IN CPU_RESET_L L54 PLTRSTIN*
3.32K
1% (IPU) BPM0* R51 XDP_BPM_L<0> BI 18 76
1/16W 77 11 IN CPU_CLK135M_DPLLREF_N AC6 DPLL_REF_CLKN
MF-LF (IPU) BPM1* R50 XDP_BPM_L<1> BI 18 76
402 77 11 IN CPU_CLK135M_DPLLREF_P AE6 DPLL_REF_CLKP
2
(IPU) BPM2* P49 XDP_BPM_L<2> BI 18 78

BPM3* N50 XDP_BPM_L<3>

CLOCK
(IPU) BI 18 78
77 11 IN CPU_CLK135M_DPLLSS_N V6 SSC_DPLL_REF_CLKN
(IPU) BPM4* R49 XDP_BPM_L<4> BI 18 78
77 11 IN CPU_CLK135M_DPLLSS_P Y6 SSC_DPLL_REF_CLKP
(IPU) BPM5* P53 XDP_BPM_L<5> BI 18 78

C 77 11

77 11
IN DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P
AB6

AA6
BCLKN
BCLKP
(IPU)

(IPU)
BPM6*
BPM7*
U51

P51
XDP_BPM_L<6>
XDP_BPM_L<7>
BI
BI
18 78

18 78
C
IN
PLACE_NEAR=U0500.F50:157mm

R0611 1
10K
5%
1/16W
MF-LF
402
2

OMIT_TABLE

U0500
HASWELL
BGA

TP_CPU_RSVD_TP23 BE4 RSVD_TP23 SYM 11 OF 12 RSVD_TP1 F1 TP_CPU_RSVD_TP1

RESERVED
TP_CPU_RSVD_TP24 BD3 RSVD_TP24 RSVD_TP2 E1 TP_CPU_RSVD_TP2
RSVD_TP3 A5 TP_CPU_RSVD_TP3
TP_CPU_RSVD_TP25 F6 RSVD_TP25
RSVD_TP4 A6 TP_CPU_RSVD_TP4
TP_CPU_RSVD_TP26 G6 RSVD_TP26
TP_CPU_RSVD_TP27 G21 RSVD_TP27 CFG_RCOMP R54 76 CPU_CFG_RCOMP
TP_CPU_RSVD_TP28 G24 RSVD_TP28
(IPU) CFG16 Y52 CPU_CFG<16> 6 18 78
CPU_TESTLO_F21 F21 TESTLO_F21 1
R0690
CFG18 V53 CPU_CFG<18> 18
G19 VSS_G19 49.9
(IPU) CFG17 Y51 CPU_CFG<17> 18 78 1%
1 F51
R0680 VSS_F51 1/16W
CFG19 V52 CPU_CFG<19> 18 MF-LF

B 49.9
1%
1/16W
70 10 8 =PPVCC_S0_CPU F52

F22
VSS_F52
VCC_F22
2
402
B
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS MF-LF
402
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 2 TP_CPU_RSVD_TP35 L52 RSVD_TP35
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED TP_CPU_RSVD_TP36 L53 RSVD_TP36
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
TP_CPU_RSVD_TP37 L51 RSVD_TP37
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
RSVD92 B50
TP_CPU_RSVD_TP38 F24 RSVD_TP38 NC
RSVD93 AH49
TP_CPU_RSVD_TP39 F25 RSVD_TP39 NC
These can be placed close to RSVD94 AM48
CPU_TESTLO_F20 F20 TESTLO_F20 NC
J1800 and only for debug access RSVD95 AU27
NC
CPU_CFG<16> 6 18 78 R0685 1
78 18 6 CPU_CFG<0> AG49 CFG0 (IPU) RSVD9 AU26
NC
CPU_CFG<9> 6 18 78 49.9 78 18 6 CPU_CFG<1> AD49 CFG1 (IPU) RSVD10 BD4
NC
1%
CPU_CFG<3> 1/16W CPU_CFG<2> AC49 CFG2 (IPU) RSVD11 BC4
6 18 78
MF-LF
78 18 6
NC
CPU_CFG<1> 6 18 78 402 78 18 6 CPU_CFG<3> AE49 CFG3 (IPU)
2 AL6
RSVD41 NC
CPU_CFG<0> 6 18 78 78 18 6 CPU_CFG<4> Y50 CFG4 (IPU)
RSVD42 F8
NOSTUFF HSW_PRE_ES2 NOSTUFF NOSTUFF NOSTUFF 78 18 6 CPU_CFG<5> AB49 CFG5 (IPU) NC
1 1 1 1 1 CPU_CFG<6> V51
R0649 R0648 R0643 R0641 R0640 78 18 6 CFG6 (IPU) F16
RSVD16 NC
1K 1K 1K 1K 1K 78 18 6 CPU_CFG<7> W51 CFG7 (IPU)
5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 78 18 CPU_CFG<8> Y49 CFG8 (IPU)
MF-LF MF-LF MF-LF MF-LF MF-LF RSVD_TP17 G12 TP_CPU_RSVD_TP17
402 402 402 402 402 78 18 6 CPU_CFG<9> Y54 CFG9 (IPU)
2 2 2 2 2
RSVD_TP18 G10 TP_CPU_RSVD_TP18
78 18 CPU_CFG<10> Y53 CFG10 (IPU)
78 18 CPU_CFG<11> W53 CFG11 (IPU)
NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid VSS_H54 H54
78 72 18 CPU_CFG<12> U53 CFG12 (IPU)
issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569). VSS_H53 H53
78 72 18 CPU_CFG<13> V54 CFG13 (IPU)
78 72 18 CPU_CFG<14> R53 CFG14 (IPU) VSS_H51 H51

CPU_CFG<7> CPU_CFG<15> R52 H52

A CPU_CFG<6>
6 18 78

6 18 78
78 72 18 CFG15 (IPU) VSS_H52
SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013 A
CPU_CFG<5> L50 RSVD50 RSVD47 N51 TP_CPU_RSVD_TP47 PAGE TITLE
6 18 78
NC
CPU_CFG<4> 6 18 78
NC
L49 RSVD51 RSVD48 G53 TP_CPU_RSVD_TP48 CPU Clock/Misc/JTAG/CFG
CPUCFG6_PD CPUCFG5_PD CPU_CFG<2> 6 18 78
NC
E5 RSVD52 RSVD49 H50 TP_CPU_RSVD_TP49 DRAWING NUMBER SIZE
NOSTUFF R0646 1
1
R0645 EDP:YES NOSTUFF
Apple Inc. 051-0164 D
1 1K 1K 1 1
R0647 R0644 R0642 REVISION
5% 5% R
1K
5%
1/16W
MF-LF
1/16W
MF-LF
1K
5%
1K
5% BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_HEAD

12.4.0
1/16W 402
2 2
402 1/16W 1/16W
TABLE_BOMGROUP_ITEM
NOTICE OF PROPRIETARY PROPERTY: BRANCH
MF-LF MF-LF MF-LF
402
2
402
2 2
402 CPUPEG:X16 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
TABLE_BOMGROUP_ITEM

THE POSESSOR AGREES TO THE FOLLOWING: PAGE

CPUPEG:X8X8 CPUCFG5_PD
TABLE_BOMGROUP_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 123
CPUPEG:X8X4X4 CPUCFG6_PD,CPUCFG5_PD III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 6 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT_TABLE OMIT_TABLE

75 25 BI MEM_A_DQ<0> AH54 SA_DQ0 U0500 RSVD160 BD31

NC 75 25 BI MEM_B_DQ<0> AC54 SB_DQ0 U0500 RSVD171 AY36
NC
75 25 BI MEM_A_DQ<1> AH52 SA_DQ1 HASWELL 75 25 BI MEM_B_DQ<1> AC52 SB_DQ1 HASWELL
SA_CKN0 BE25 MEM_A_CLK_N<0> OUT 23 75 BGA SB_CKN0 AW27 MEM_B_CLK_N<0> OUT 24 75
MEM_A_DQ<2> AK51 SA_DQ2 BGA MEM_B_DQ<2> AE51 SB_DQ2
75 25 BI 75 25 BI
SYM 3 OF 12 SA_CKP0 BF25 MEM_A_CLK_P<0> OUT 23 75
SYM 4 OF 12 SB_CKP0 AV27 MEM_B_CLK_P<0> OUT 24 75
75 25 BI MEM_A_DQ<3> AK54 SA_DQ3 75 25 BI MEM_B_DQ<3> AE54 SB_DQ3
SA_CKE0 BE34 MEM_A_CKE<0> OUT 23 75 SB_CKE0 AU36 MEM_B_CKE<0> OUT 24 75
75 25 BI MEM_A_DQ<4> AH53 SA_DQ4 75 25 BI MEM_B_DQ<4> AC53 SB_DQ4
75 25 BI MEM_A_DQ<5> AH51 SA_DQ5 SA_CKN1 BD25 MEM_A_CLK_N<1> OUT 23 75 75 25 BI MEM_B_DQ<5> AC51 SB_DQ5 SB_CKN1 AW26 MEM_B_CLK_N<1> OUT 24 75

75 25 BI MEM_A_DQ<6> AK52 SA_DQ6 SA_CKP1 BC25 MEM_A_CLK_P<1> OUT 23 75 75 25 BI MEM_B_DQ<6> AE52 SB_DQ6 SB_CKP1 AV26 MEM_B_CLK_P<1> OUT 24 75

75 25 MEM_A_DQ<7> AK53 SA_DQ7 SA_CKE1 BF34 MEM_A_CKE<1> 23 75 75 25 MEM_B_DQ<7> AE53 SB_DQ7 SB_CKE1 AU35 MEM_B_CKE<1> 24 75

D 75 25
BI
BI MEM_A_DQ<8> AN54 SA_DQ8
SA_CKN2 BE23
NC
OUT
75 25
BI
BI MEM_B_DQ<8> AU47 SB_DQ8
SB_CKN2 BA26
NC
OUT
D
75 25 BI MEM_A_DQ<9> AN52 SA_DQ9 75 25 BI MEM_B_DQ<9> AU49 SB_DQ9
SA_CKP2 BF23 SB_CKP2 AY26
75 25 BI MEM_A_DQ<10> AR51 SA_DQ10 NC 75 25 BI MEM_B_DQ<10> AV43 SB_DQ10 NC
SA_CKE2 BC34 SB_CKE2 AV35
75 25 BI MEM_A_DQ<11> AR53 SA_DQ11 NC 75 25 BI MEM_B_DQ<11> AV45 SB_DQ11 NC
75 25 BI MEM_A_DQ<12> AN53 SA_DQ12 SA_CKN3 BD23
NC 75 25 BI MEM_B_DQ<12> AU43 SB_DQ12 SB_CKN3 BA27
NC
75 25 BI MEM_A_DQ<13> AN51 SA_DQ13 SA_CKP3 BC23
NC 75 25 BI MEM_B_DQ<13> AU45 SB_DQ13 SB_CKP3 AY27
NC
75 25 MEM_A_DQ<14> AR52 SA_DQ14 SA_CKE3 BD34 75 25 MEM_B_DQ<14> AV47 SB_DQ14 SB_CKE3 AV36
BI NC BI NC
75 25 BI MEM_A_DQ<15> AR54 SA_DQ15 75 25 BI MEM_B_DQ<15> AV49 SB_DQ15
75 25 BI MEM_A_DQ<16> AV52 SA_DQ16 SA_CS0* BE16 MEM_A_CS_L<0> OUT 23 75 75 25 BI MEM_B_DQ<16> BC49 SB_DQ16 SB_CS0* BA20 MEM_B_CS_L<0> OUT 24 75

75 25 BI MEM_A_DQ<17> AV53 SA_DQ17 SA_CS1* BC17 MEM_A_CS_L<1> OUT 23 75 75 25 BI MEM_B_DQ<17> BE49 SB_DQ17 SB_CS1* AY19 MEM_B_CS_L<1> OUT 24 75

75 25 BI MEM_A_DQ<18> AY52 SA_DQ18 SA_CS2* BE17

NC 75 25 BI MEM_B_DQ<18> BD47 SB_DQ18 SB_CS2* AU19
NC
75 25 BI MEM_A_DQ<19> AY51 SA_DQ19 SA_CS3* BD16
NC 75 25 BI MEM_B_DQ<19> BC47 SB_DQ19 SB_CS3* AW20
NC
75 25 BI MEM_A_DQ<20> AV51 SA_DQ20 75 25 BI MEM_B_DQ<20> BD49 SB_DQ20
SA_ODT0 BC16 MEM_A_ODT<0> OUT 23 75 SB_ODT0 AY20 MEM_B_ODT<0> OUT 24 75

MEMORY CHANNEL A

MEMORY CHANNEL B
75 25 BI MEM_A_DQ<21> AV54 SA_DQ21 75 25 BI MEM_B_DQ<21> BD50 SB_DQ21
SA_ODT1 BF16 MEM_A_ODT<1> OUT 23 75 SB_ODT1 BA19 MEM_B_ODT<1> OUT 24 75
75 25 BI MEM_A_DQ<22> AY54 SA_DQ22 75 25 BI MEM_B_DQ<22> BE47 SB_DQ22
SA_ODT2 BF17 SB_ODT2 AV19
75 25 BI MEM_A_DQ<23> AY53 SA_DQ23 NC 75 25 BI MEM_B_DQ<23> BF47 SB_DQ23 NC
SA_ODT3 BD17 SB_ODT3 AW19
75 25 BI MEM_A_DQ<24> AY47 SA_DQ24 NC 75 25 BI MEM_B_DQ<24> BE44 SB_DQ24 NC
75 25 BI MEM_A_DQ<25> AY49 SA_DQ25 SA_BS0 BC20 MEM_A_BA<0> OUT 23 75 75 25 BI MEM_B_DQ<25> BD44 SB_DQ25 SB_BS0 AY23 MEM_B_BA<0> OUT 24 75

75 25 BI MEM_A_DQ<26> BA47 SA_DQ26 SA_BS1 BD21 MEM_A_BA<1> OUT 23 75 75 25 BI MEM_B_DQ<26> BC42 SB_DQ26 SB_BS1 BA23 MEM_B_BA<1> OUT 24 75

75 25 BI MEM_A_DQ<27> BA45 SA_DQ27 SA_BS2 BD32 MEM_A_BA<2> OUT 23 75 75 25 BI MEM_B_DQ<27> BF42 SB_DQ27 SB_BS2 BA36 MEM_B_BA<2> OUT 24 75

75 25 BI MEM_A_DQ<28> AY45 SA_DQ28 75 25 BI MEM_B_DQ<28> BF44 SB_DQ28

75 25 BI MEM_A_DQ<29> AY43 SA_DQ29 VSS_BC21 BC21 75 25 BI MEM_B_DQ<29> BC44 SB_DQ29 VSS_AU30 AU30

75 25 BI MEM_A_DQ<30> BA49 SA_DQ30 75 25 BI MEM_B_DQ<30> BD42 SB_DQ30

SA_RAS* BF20 MEM_A_RAS_L OUT 23 75 SB_RAS* AV23 MEM_B_RAS_L OUT 24 75
75 25 BI MEM_A_DQ<31> BA43 SA_DQ31 75 25 BI MEM_B_DQ<31> BE42 SB_DQ31
SA_WE* BF21 MEM_A_WE_L OUT 23 75 SB_WE* AW23 MEM_B_WE_L OUT 24 75
75 25 BI MEM_A_DQ<32> BF14 SA_DQ32 75 25 BI MEM_B_DQ<32> BA16 SB_DQ32
SA_CAS* BE21 MEM_A_CAS_L OUT 23 75 SB_CAS* AV20 MEM_B_CAS_L OUT 24 75
75 25 BI MEM_A_DQ<33> BC14 SA_DQ33 75 25 BI MEM_B_DQ<33> AU16 SB_DQ33

C 75 25

75 25
BI
BI
MEM_A_DQ<34>
MEM_A_DQ<35>
BC11

BF11
SA_DQ34
SA_DQ35
SA_MA0
SA_MA1
BD28

BD27
MEM_A_A<0>
MEM_A_A<1>
OUT 23 75

23 75
75 25

75 25
BI
BI
MEM_B_DQ<34>
MEM_B_DQ<35>
BA15

AV15
SB_DQ34
SB_DQ35
SB_MA0
SB_MA1
BA30

AW30
MEM_B_A<0>
MEM_B_A<1>
OUT 24 75

24 75
C
MEM_A_DQ<36> BE14 OUT MEM_B_DQ<36> AY16 OUT
75 25 BI SA_DQ36 75 25 BI SB_DQ36
SA_MA2 BF28 MEM_A_A<2> OUT 23 75 SB_MA2 AY30 MEM_B_A<2> OUT 24 75
75 25 BI MEM_A_DQ<37> BD14 SA_DQ37 75 25 BI MEM_B_DQ<37> AV16 SB_DQ37
SA_MA3 BE28 MEM_A_A<3> OUT 23 75 SB_MA3 AV30 MEM_B_A<3> OUT 24 75
75 25 BI MEM_A_DQ<38> BD11 SA_DQ38 75 25 BI MEM_B_DQ<38> AY15 SB_DQ38
SA_MA4 BF32 MEM_A_A<4> OUT 23 75 SB_MA4 AW32 MEM_B_A<4> OUT 24 75
75 25 BI MEM_A_DQ<39> BE11 SA_DQ39 75 25 BI MEM_B_DQ<39> AU15 SB_DQ39
SA_MA5 BC27 MEM_A_A<5> OUT 23 75 SB_MA5 AY32 MEM_B_A<5> OUT 24 75
75 25 BI MEM_A_DQ<40> BC9 SA_DQ40 75 25 BI MEM_B_DQ<40> AU12 SB_DQ40
SA_MA6 BF27 MEM_A_A<6> OUT 23 75 SB_MA6 AT30 MEM_B_A<6> OUT 24 75
75 25 BI MEM_A_DQ<41> BE9 SA_DQ41 75 25 BI MEM_B_DQ<41> AY12 SB_DQ41
SA_MA7 BC28 MEM_A_A<7> OUT 23 75 SB_MA7 AV32 MEM_B_A<7> OUT 24 75
75 25 BI MEM_A_DQ<42> BE6 SA_DQ42 75 25 BI MEM_B_DQ<42> BA10 SB_DQ42
SA_MA8 BE27 MEM_A_A<8> OUT 23 75 SB_MA8 BA32 MEM_B_A<8> OUT 24 75
75 25 BI MEM_A_DQ<43> BC6 SA_DQ43 75 25 BI MEM_B_DQ<43> AU10 SB_DQ43
SA_MA9 BC32 MEM_A_A<9> OUT 23 75 SB_MA9 AU32 MEM_B_A<9> OUT 24 75
75 25 BI MEM_A_DQ<44> BD9 SA_DQ44 75 25 BI MEM_B_DQ<44> AV12 SB_DQ44
SA_MA10 BD20 MEM_A_A<10> OUT 23 75 SB_MA10 AU23 MEM_B_A<10> OUT 24 75
75 25 BI MEM_A_DQ<45> BF9 SA_DQ45 75 25 BI MEM_B_DQ<45> BA12 SB_DQ45
SA_MA11 BF31 MEM_A_A<11> OUT 23 75 SB_MA11 AY35 MEM_B_A<11> OUT 24 75
75 25 BI MEM_A_DQ<46> BE5 SA_DQ46 75 25 BI MEM_B_DQ<46> AY10 SB_DQ46
SA_MA12 BC31 MEM_A_A<12> OUT 23 75 SB_MA12 AW35 MEM_B_A<12> OUT 24 75
75 25 BI MEM_A_DQ<47> BD6 SA_DQ47 75 25 BI MEM_B_DQ<47> AV10 SB_DQ47
SA_MA13 BE20 MEM_A_A<13> OUT 23 75 SB_MA13 AU20 MEM_B_A<13> OUT 24 75
75 25 BI MEM_A_DQ<48> BB4 SA_DQ48 75 25 BI MEM_B_DQ<48> AU8 SB_DQ48
SA_MA14 BE32 MEM_A_A<14> OUT 23 75 SB_MA14 AW36 MEM_B_A<14> OUT 24 75
75 25 BI MEM_A_DQ<49> BC2 SA_DQ49 75 25 BI MEM_B_DQ<49> BA8 SB_DQ49
SA_MA15 BE31 MEM_A_A<15> OUT 23 75 SB_MA15 BA35 MEM_B_A<15> OUT 24 75
75 25 BI MEM_A_DQ<50> AW3 SA_DQ50 75 25 BI MEM_B_DQ<50> AV6 SB_DQ50
75 25 BI MEM_A_DQ<51> AW2 SA_DQ51 75 25 BI MEM_B_DQ<51> BA6 SB_DQ51
SA_DQSN0 AJ52 MEM_A_DQS_N<0> BI 25 75 SB_DQSN0 AD52 MEM_B_DQS_N<0> BI 25 75
75 25 BI MEM_A_DQ<52> BB3 SA_DQ52 75 25 BI MEM_B_DQ<52> AV8 SB_DQ52
SA_DQSN1 AP53 MEM_A_DQS_N<1> BI 25 75 SB_DQSN1 AU46 MEM_B_DQS_N<1> BI 25 75
75 25 BI MEM_A_DQ<53> BB2 SA_DQ53 75 25 BI MEM_B_DQ<53> AY8 SB_DQ53
SA_DQSN2 AW52 MEM_A_DQS_N<2> BI 25 75 SB_DQSN2 BD48 MEM_B_DQS_N<2> BI 25 75
75 25 BI MEM_A_DQ<54> AW4 SA_DQ54 75 25 BI MEM_B_DQ<54> AU6 SB_DQ54
SA_DQSN3 AY46 MEM_A_DQS_N<3> BI 25 75 SB_DQSN3 BD43 MEM_B_DQS_N<3> BI 25 75
75 25 BI MEM_A_DQ<55> AW1 SA_DQ55 75 25 BI MEM_B_DQ<55> AY6 SB_DQ55
SA_DQSN4 BD12 MEM_A_DQS_N<4> BI 25 75 SB_DQSN4 AW16 MEM_B_DQS_N<4> BI 25 75
75 25 BI MEM_A_DQ<56> AU3 SA_DQ56 75 25 BI MEM_B_DQ<56> AM2 SB_DQ56
SA_DQSN5 BE7 MEM_A_DQS_N<5> BI 25 75 SB_DQSN5 AW10 MEM_B_DQS_N<5> BI 25 75
75 25 BI MEM_A_DQ<57> AU1 SA_DQ57 75 25 BI MEM_B_DQ<57> AM3 SB_DQ57
SA_DQSN6 BA3 MEM_A_DQS_N<6> BI 25 75 SB_DQSN6 AW8 MEM_B_DQS_N<6> BI 25 75
75 25 BI MEM_A_DQ<58> AR1 SA_DQ58 75 25 BI MEM_B_DQ<58> AK1 SB_DQ58
SA_DQSN7 AT2 MEM_A_DQS_N<7> BI 25 75 SB_DQSN7 AL2 MEM_B_DQS_N<7> BI 25 75
75 25 BI MEM_A_DQ<59> AR4 SA_DQ59 75 25 BI MEM_B_DQ<59> AK4 SB_DQ59
RSVD161 AW39 RSVD172 BE38
75 25 MEM_A_DQ<60> AU2 SA_DQ60 NC 75 25 MEM_B_DQ<60> AM1 SB_DQ60 NC
B 75 25
BI
BI MEM_A_DQ<61> AU4 SA_DQ61
SA_DQS0 AJ53 MEM_A_DQS_P<0> BI 25 75
75 25
BI
BI MEM_B_DQ<61> AM4 SB_DQ61
SB_DQS0 AD53 MEM_B_DQS_P<0> BI 25 75
B
75 25 BI MEM_A_DQ<62> AR2 SA_DQ62 75 25 BI MEM_B_DQ<62> AK2 SB_DQ62
SA_DQS1 AP52 MEM_A_DQS_P<1> BI 25 75 SB_DQS1 AV46 MEM_B_DQS_P<1> BI 25 75
75 25 BI MEM_A_DQ<63> AR3 SA_DQ63 75 25 BI MEM_B_DQ<63> AK3 SB_DQ63
SA_DQS2 AW53 MEM_A_DQS_P<2> BI 25 75 SB_DQS2 BE48 MEM_B_DQS_P<2> BI 25 75

SA_DQS3 BA46 MEM_A_DQS_P<3> BI 25 75 SB_DQS3 BE43 MEM_B_DQS_P<3> BI 25 75

SA_DQS4 BE12 MEM_A_DQS_P<4> BI 25 75 SB_DQS4 AW15 MEM_B_DQS_P<4> BI 25 75

SA_DQS5 BD7 MEM_A_DQS_P<5> BI 25 75 SB_DQS5 AW12 MEM_B_DQS_P<5> BI 25 75

SA_DQS6 BA2 MEM_A_DQS_P<6> BI 25 75 SB_DQS6 AW6 MEM_B_DQS_P<6> BI 25 75

SA_DQS7 AT3 MEM_A_DQS_P<7> BI 25 75 SB_DQS7 AL3 MEM_B_DQS_P<7> BI 25 75

22 OUT CPU_DIMM_VREFCA AM6 SM_VREF
RSVD162 AW40 RSVD173 BD38
NC NC

RSVD163 BA40 RSVD174 BF39

NC NC
RSVD164 AY40 RSVD175 BE39
NC NC
RSVD165 BA39 RSVD176 BF37
NC NC
RSVD166 AY39 RSVD177 BE37
22 OUT CPU_DIMMA_VREFDQ AR6 SA_DIMM_VREFDQ NC NC
RSVD167 AV40 RSVD178 BD39
NC NC
22 OUT CPU_DIMMB_VREFDQ AN6 SB_DIMM_VREFDQ RSVD168 AU40
NC RSVD179 BC39
NC
RSVD169 AV39 RSVD180 BC37
NC NC
BC53 RSVD25 RSVD170 AU39 RSVD181 BD37
NC NC NC

A SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013 A
PAGE TITLE

CPU DDR3 Interfaces

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PPVCC_S0_CPU 6 8 10 70

NC
J17 RSVD64 U0500 B43

NC
J21 RSVD65 HASWELL B45
J26 RSVD66 BGA B46
NC
J31 RSVD67 SYM 5 OF 12 B48
NC
70 10 =PP1V5R1V35_S0_CPU OMIT_TABLE C27

AR29 C28

AR31 C31

AR33 C32

AT13 C34

AT19 C36

AT23 C38

D AT27

AT32
C39

C42
D
AT36 C43

AV37 C45

AW22 C46

AW25 C48

AW29 D27
AW33 D28

AY18 D31

BB21 D32

BB22 VDDQ D34

BB26 D36

BB27 D38

BB30 D39

BB31 D42

BB34 D43

BB36 D45

BD22 D46

BD26 D48

BD30 E27

BD33 E28
BE18 E31

BE22 E32

BE26 E34
BE30 E36

70 10 8 6 =PPVCC_S0_CPU BE33 E38

C NC
AN31 RSVD68
E39

E42 C
R0860 1 L6 VCC_L6 E43

PLACE_NEAR=U0500.C50:50.8mm 100 M6 VCC_M6 E45

5%
1/16W AN22 RSVD69 E46
PLACE_SIDE=BOTTOM MF-LF
NC
NOTE: Aliases not used on CPU supply outputs 402 AN18 RSVD70 E48
2 NC VCC
to avoid any extraneous connections. F27
83 61 OUT CPU_VCCSENSE_P C50 VCC_SENSE F28
61 18 10 6 5 PPVCCIO_S0_CPU NC
AH9 RSVD71
MIN_LINE_WIDTH=0.4 mm F31
Max load: 300mA MIN_NECK_WIDTH=0.2 mm D51 VCCIO_OUT
VOLTAGE=1.05V F32
5 PPVCOMP_S0_CPU NC F17 FC_F17
MIN_LINE_WIDTH=0.4 mm F34
1 1 AK6
R0800 R0802 Max load: 300mA MIN_NECK_WIDTH=0.2 mm VCOMP_OUT F36
VOLTAGE=1.05V
75 110 AN33 RSVD72
1% 1%
NC F38
1/16W 1/16W W9 RSVD73
MF-LF MF-LF
NC F39
J12 RSVD79(VSS)
402
2 R0810 2
402
NC F42
43 AR49 RSVD74
83 61 IN CPU_VIDALERT_L 1 2 NC F43

5% F45
1/16W 83 CPU_VIDALERT_R_L J53 VIDALERT*
MF-LF F46
R0811 402 83 CPU_VIDSCLK_R J52 VIDSCLK
0 F48
83 61 OUT CPU_VIDSCLK 1 2 83 CPU_VIDSOUT_R J50 VIDSOUT G27
5%
1/16W R0802.2: PLACE_NEAR=U0500.J50:2.54mm G29
MF-LF B51 VSS_B51
402 R0812 R0810.2: PLACE_NEAR=U0500.J53:38mm G31
0 18 IN CPU_PWR_DEBUG F19 PWR_DEBUG
83 61 BI CPU_VIDSOUT 1 2 R0800.2: PLACE_NEAR=R0810.1:2.54mm G32
E52 VSS_E52
5% G34
1/16W TP_CPU_RSVD_TP75 V49 RSVD75
MF-LF G36
402 TP_CPU_RSVD_TP76 U49 RSVD76 G38
TP_CPU_IVR_ERROR AM49 IVR_ERROR G39

B TP_CPU_RSVD_TP78 W49

V50
RSVD78
VSS_V50(RSVD)
G42

G43
B
AN49 VSS_AN49(RSVD) G45
AJ49 VSS_AJ49(RSVD) G46
AG50 VSS_AG50(RSVD) G48
AK49 VSS_AK49(RSVD) H11
AJ50 VSS_AJ50(RSVD) H12
AP49 VSS_AP49(RSVD) H13
AB50 VSS_AB50(RSVD) H14
AP50 VSS_AP50(RSVD) H16
AD50 VSS_AD50(RSVD) H17
AM50 VSS_AM50(RSVD) H18

H19
A36
H20
A38
H21
A39
H23
A42
H24
A43
H25
H33

H34

H36

H37

H38

H39

H40

H42

H43

H45

H46
H48

J10

J14

J19
J24

J29

J33
J36

J37
J38

J39

J40

J42

J43

J45

J46

J48

K38

K40

K43

K44
K45

K46

K48

L37

L38

L39
L40

L42

L43
L44

L46

L47

M37

M38

M39

M40
M42

M43

M44

M45

M46

N37

N38

N39

N40
N42

N43

N44

N46

N47

P45

P46

R46
R47

T45

T46

U46

U47

V45

V46

W46

W47

Y45

Y46

A27

A28
A31

A32

A34

B27

B28

B31

B32

B34
B36

B38

B39

B42
A45
H8

Y8
H26
A46 VCC
H27
A48
VCC

H29 Connections would be required

AA46

AA47
for 2014 CPU support.
AA8 FC_D5 D5 TP_CPU_FC_VCCST
AA9 FC_D3 D3 TP_CPU_FC_VCCST_PWRGD
SYM 6 OF 12
OMIT_TABLE

HASWELL
U0500

A A
POWER
BGA

SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013
PAGE TITLE

CPU Power
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
R
VCC

12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
AB45

AB46

AB8

AC46

AC47

AC8

AC9

AD46

AD8

AE46

AE47

AE8

AF8

AG46

AG8

AH46

AH47
AH8

AJ45

AJ46

AK46

AK47
AK8

AL45

AL46
AL8

AL9

AM46

AM47

AM8

AM9

AN10

AN12

AN13

AN14

AN15

AN16

AN17

AN19

AN20

AN21

AN23

AN24

AN25

AN26

AN27

AN29

AN30

AN32

AN34
AN36

AN38

AN39

AN40

AN41
AN42

AN43

AN44

AN45

AN46

AN8

AN9

AP10

AP12

AP13

AP14
AP15

AP16

AP17

AP18

AP19

AP20

AP21

AP22

AP23
AP24

AP25
AP26

AP27

AP29

AP30

AP31

AP32

AP33

AP34

AP35
AP36

AP37
AP38

AP39

AP40

AP41

AP42

AP43
AP44

AP46

AP47
AP8

AP9

AR35

AR37

AR39

AR41

AR43

AR45
AR46

H30

H31

H32
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 8 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 8 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OMIT_TABLE OMIT_TABLE
A11 U0500 AJ48 AT40 U0500 AY50

A15 HASWELL AJ51 AT42 HASWELL AY9

A19 BGA AJ54 AT43 BGA B11

A22 SYM 7 OF 12 AK48 AT45 SYM 8 OF 12 B15

A26
GROUND AK5 AT46
GROUND B19

D A30

A33
AK50

AK7
AT47

AT49
B22

B26
D
A37 AK9 AT5 B30

A40 AL1 AT50 B33

A44 AL4 AT51 B37

AA1 AL48 AT52 B40

AA2 AL5 AT53 B44

AA3 AL7 AT54 B49

AA4 AM5 AT6 B8

AA48 AM51 AT8 BA13

AA5 AM52 AT9 BA18

AA7 AM53 AU13 BA22

AB5 AM54 AU18 BA25

AB51 AM7 AU22 BA29

AB52 AN1 AU25 BA33

AB53 AN2 AU29 BA37

AB54 AN3 AU33 BA4

AB7 AN4 AU37 BA42

AB9 AN48 AU42 BA5

AC48 AN5 AU5 BA50

AC5 AN50 AU9 BA51

AC50 AN7 AV1 BA52

AC7 AP51 AV13 BA53

AD48 AP54 AV18 BA9

AD51 AP7 AV2 BB10

AD54 VSS VSS AR12 AV22 BB11

VSS VSS

C AD7

AD9
AR14

AR16
AV25

AV29
BB12

BB14 C
AE1 AR18 AV3 BB15
AE2 AR20 AV33 BB16

AE3 AR24 AV4 BB17

AE4 AR26 AV42 BB18

AE48 AR48 AV5 BB20

AE5 AR5 AV50 BB23

AE50 AR50 AV9 BB25

AE7 AR7 AW13 BB28

AF5 AR8 AW18 BB32

AF6 AR9 AW37 BB33

AF7 AT1 AW42 BB37

AG48 AT10 AW43 BB38

AG5 AT12 AW45 BB39

AG51 AT15 AW46 BB41

AG52 AT16 AW47 BB42

AG53 AT18 AW49 BB43

AG54 AT20 AW5 BB44

AG7 AT22 AW50 BB46

AG9 AT25 AW51 BB47

AH1 AT26 AW54 BB48

AH2 AT29 AW9 BB49

AH3 AT33 AY13 BB5

AH4 AT35 AY22 BB6

AH48 AT37 AY25 BB7

AH5 AT39 AY29 BB9

B AH50
AH7
AT4 AY33
AY37
B
AY42

CPU_VCCSENSE_N OUT 61 83

AR22

AB48

BA54

BB54

BD53

BF49

BF50
G20

G23
G25

G26

G30

G33

G37

G40

G44

G49
G52

G54

H44
H49

J44

J49

J51
J54

L48

M48

M50
M52

M54

N48

P48

P50

P52

P54

R48

T48

U48

U50

U52

U54

V48

W48

W50

W52

W54

Y48

G18

A49

A50

BA1

BB1

BD2

BF5

BF6

C53

E54

F54

D50
G7

K1
K2

K4
K5

P3
P4

G1
1
R0960
100

VSS_AR22(RSVD)
VSS_AB48(RSVD)
VSS_P9(RSVD)
VSS_G18(RSVD)

VSS_SENSE
PLACE_NEAR=U0500.D50:50.8mm
VSS

VSS_NCTF
5%
1/16W
MF-LF PLACE_SIDE=BOTTOM
402
2
SYM 9 OF 12
OMIT_TABLE

HASWELL
U0500
BGA

VSS

A SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013 A
BC10

BC12
BC15

BC18

BC22
BC26

BC3

BC30
BC33

BC36
BC38

BC41

BC43

BC46

BC48

BC5
BC50

BC52

BC7

BD10

BD15

BD18

BD36

BD41
BD46

BD5

BD51

BE10

BE15

BE36

BE41

BE46
BF10

BF12

BF15

BF18

BF22

BF26
BF30

BF33

BF36

BF38

BF41
BF43

BF46

BF48
BF7

C11

C15

C19

C22

C26

C30

C33
C37

C40
C44

C49

C52

D11

D15
D19

D22
D26

D30

D33

D37

D40

D44

D49

E11

E15

E16
E17

E19

E20

E21

E22

E24
E25

E26

E30
E33

E37

E40

E44

E49

E51

E53

F26

F30

F33
F37

F40
F44

F49

G11

G13

G16
PAGE TITLE

CPU Ground
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCORE Decoupling
Intel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU)
Apple Implementation: 9x 210uF 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402

PLACEMENT_NOTE (C1000-C1019):
70 8 6 =PPVCC_S0_CPU
Place on bottom side of U0500

1
C1000 1
C1001 1
C1002 1
C1003 1
C1004 1
C1005 1
C1006 1
C1007 1
C1008 1
C1009 1
C1010 1
C1011 1
C1012 1
C1013 1
C1014 1
C1015 1
C1016 1
C1017 1
C1018 1
C1019
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%

D 2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
2
10V
X6S-CERM
0402
D
PLACEMENT_NOTE (C1020-C1023): For noise floor mitigation of DP (C1070-C1075):

Place near U0500 on bottom side

1
C1020 1
C1021 1
C1022 1
C1023 1 C1070 1 C1071 1 C1072 1 C1073 1 C1074 1 C1075
10UF 10UF 10UF 10UF 1.5PF 1.5PF 1.5PF 1.5PF 1.5PF 1.5PF
20% 20% 20% 20% +/-0.1PF +/-0.1PF +/-0.1PF +/-0.1PF +/-0.1PF +/-0.1PF
4V 4V 4V 4V 25V 25V 25V 25V 25V 25V
2 X6S 2 X6S 2 X6S 2 X6S 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G
0402 0402 0402 0402 201 201 201 201 201 201

PLACEMENT_NOTE (C1024-C1045):

Place near inductors on bottom side.

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C1024 1
C1025 1
C1026 1
C1027 1
C1028 1
C1029 1
C1030 1
C1031 1
C1032 1
C1033 1
C1034 1
C1035 1
C1036 1
C1037 1
C1038 1
C1039 1
C1040 1
C1041 1
C1042 1
C1043 1
C1044 1
C1045
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402

PLACEMENT_NOTE (C1046-C1067):

Place near inductors on bottom side.

C 2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
20%
4V
X6S
0402
C

BULK CAPS ON REGULATOR PAGE

CPU VDDQ Decoupling

Intel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402
Apple Implementation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

PLACEMENT_NOTE (C1080-C1089):
70 8 =PP1V5R1V35_S0_CPU
Place on bottom side of U0500
U100.

1
C1080 1
C1081 1
C1082 1
C1083 1
C1084 1
C1085 1
C1086 1
C1087 1
C1088 1
C1089
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402

B B
PLACEMENT_NOTE (C1090-C1097):

Place near U0500 on bottom side

1
C1090 1
C1091 1
C1092 1
C1093 1
C1094 1
C1095 1
C1096 1
C1097
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V
2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM
0603 0603 0603 0603 0603 0603 0603 0603

BULK CAPS ON REGULATOR PAGE

CPU VCCIO Decoupling

A Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups)
Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page) SYNC_MASTER=J16_DINI SYNC_DATE=01/14/2013 A
PAGE TITLE

61 18 8 6 5 PPVCCIO_S0_CPU
CPU Decoupling
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
1
C1079 R
0.01UF 12.4.0
10%
16V NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 X7R-CERM
0402 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 10 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5. IV ALL RIGHTS RESERVED 10 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
SATA Port assignments:
PCH_CLK32K_RTCX1 B5 BC8 SATA_HDD_D2R_N
79 19 IN RTCX1 U1100 SATA_RXN0 IN 33 78

79 19 PCH_CLK32K_RTCX2 B4
RTCX2 LYNXPOINT SATA_RXP0 BE8 SATA_HDD_D2R_P 33 78
OUT IN
MOBILE AW8 PRIMARY HDD
SATA_TXN0 SATA_HDD_R2D_C_N OUT 33 78
FCBGA
AY8 SATA_HDD_R2D_C_P
B9 (1 OF 11) SATA_TXP0 OUT 33 78
11 PCH_SRTCRST_L SRTCRST*
BC10
A8 SATA_RXN1 NC
11 PCH_INTRUDER_L INTRUDER* BE10
SATA_RXP1 NC

RTC
PCH_INTVRMEN_L G10 AV10
11 INTVRMEN SATA_TXN1 NC
AW10
D9 SATA_TXP1 NC
45 19 11 RTC_RESET_L RTCRST*
BB9
SATA_RXN2 NC
D 79 52 OUT HDA_BIT_CLK R1110 33 1 2
5%
79
1/20W
HDA_BIT_CLK_R
MF 201
B25
HDA_BCLK
SATA_RXP2
SATA_TXN2
BD9
AY13
NC
NC
D
PLACE_NEAR=U1100.B25:3.7MM AW13
SATA_TXP2 NC
79 52 OUT HDA_SYNC R1111 33 1 2 79 HDA_SYNC_R A22
HDA_SYNC (IPD-boot)
5% 1/20W MF 201 BC12
PLACE_NEAR=U1100.A22:3.5MM SATA_RXN3 NC
PCH_SPKR AL10 BE12
11 SPKR (IPD-PLTRST#) SATA_RXP3 NC

SATA
AR13
SATA_TXN3 NC
R1112 33

AZALIA
HDA_RST_L 1 2 HDA_RST_R_L C24 AT13
79 52 OUT 79 HDA_RST* SATA_TXP3 NC
5% 1/20W MF 201
PLACE_NEAR=U1100.C24:4.5MM BD13
L22 SATA_RXN4/PERN1 SSD_D2R_N<0> IN 33 78
79 52 IN HDA_SDIN0 HDA_SDI0 (IPD) BB13
K22 SATA_RXP4/PERP1 SSD_D2R_P<0> IN 33 78
72 TP_HDA_SDIN1 HDA_SDI1 (IPD) AV15 SSD
G22 SATA_TXN4/PETN1 SSD_R2D_N<0> OUT 33 78 =PP1V5_S0_PCH_SATA 70
72 TP_HDA_SDIN2 HDA_SDI2 (IPD) AW15
F22 SATA_TXP4/PETP1 SSD_R2D_P<0> OUT 33 78
72 TP_HDA_SDIN3 HDA_SDI3 (IPD)
BC14 SSD_D2R_N<1>
SATA_RXN5/PERN2 IN 33 78

79 52 HDA_SDOUT R1113 33 1 2 79 19 HDA_SDOUT_R A24

HDA_SDO (IPD-boot) SATA_RXP5/PERP2 BE14 SSD_D2R_P<1> 33 78
R1130 1
OUT IN
5% 1/20W MF 201 AP15
7.5K
PLACE_NEAR=U1100.A24:3.7MM SATA_TXN5/PETN2 SSD_R2D_N<1> OUT 33 78 1%
B17 (IPD-DOCKEN#?) AR15 1/20W
=PPVRTC_G3_PCH 12 15 70 58 41 11 OUT DP_TBT_SEL DOCKEN*/GPIO33 SATA_TXP5/PETP2 SSD_R2D_P<1> OUT 33 78 MF
C22 201
ENET_MEDIA_SENSE 2
80 35 11 IN HDA_DOCK_RST*/GPIO13
AY5 PLACE_NEAR=U1100.AY5:2.54mm
SATA_RCOMP 78 PCH_SATA_RCOMP
1 1
R1102 R1103 78 18 IN XDP_PCH_TCK AB3
JTAG_TCK (IPD)
20K 20K AP3 PCH_SATALED_L
1 1
SATALED* 11 33
R1100 R1101 5% 5% AD1
330K 1/20W 1/20W 78 18 IN XDP_PCH_TMS JTAG_TMS (IPU)
5%
1M MF MF AT1
1/20W
5% 201 2 2 201 AE2 SATA0GP/GPIO21 DP_AUXIO_EN OUT 11 18 29 30
1/20W 78 18 IN XDP_PCH_TDI JTAG_TDI (IPU)

JTAG
MF AU2 SATARDRVR_EN
201
MF SATA1GP/GPIO19 OUT 11 18
2 2 201
PCH_SRTCRST_L 11 AD3 (IPU-PLTRST#)
78 18 OUT XDP_PCH_TDO JTAG_TDO
PCH_INTRUDER_L 11 BD4
SATA_IREF
PCH_INTVRMEN_L 11 F8
NC TP25
RTC_RESET_L 11 19 45 C26 BA2
C C1102 1 1
C1103
NC
NC
AB6
TP22
TP20
TP9
TP8 BB2
NC
NC
C
1UF 1UF
10% 10%
10V 10V
X5R 2 2 X5R OMIT_TABLE
402 402
77 33 PCIE_CLK100M_SSD_N Y43
CLKOUT_PCIE_N0 U1100 CLKOUT_PEG_A_N AB35
OUT NC
PCIE_CLK100M_SSD_P Y45
CLKOUT_PCIE_P0 LYNXPOINT CLKOUT_PEG_A_P AB36
77 33 OUT
MOBILE NC
SSD_CLKREQ_L AB1 FCBGA AF6 PCH_PEGCLKRQA_L_GPIO47
33 11 IN PCIECLKRQ0*/GPIO73 PEG_A_CLKRQ*/GPIO47 11
(2 OF 11)
PCIE_CLK100M_ENET_N AA44 Y39
77 35 OUT CLKOUT_PCIE_N1 CLKOUT_PEG_B_N NC
PCIE_CLK100M_ENET_P AA42 Y38
77 35 OUT CLKOUT_PCIE_P1 CLKOUT_PEG_B_P NC
ENET_CLKREQ_L AF1 U4 PCH_PEGCLKRQB_L_GPIO56
35 18 11 IN PCIECLKRQ1*/GPIO18 PEG_B_CLKRQ*/GPIO56 11

PCIE_CLK100M_AP_N AB43 AF39 DMI_CLK100M_CPU_N

77 32 OUT CLKOUT_PCIE_N2 CLKOUT_DMI_N OUT 6 77

PCIE_CLK100M_AP_P AB45 AF40 DMI_CLK100M_CPU_P

77 32 OUT CLKOUT_PCIE_P2 CLKOUT_DMI_P OUT 6 77

AP_CLKREQ_L AF3
32 18 11 IN PCIECLKRQ2*/GPIO20/SMI* AJ40
CLKOUT_DP_N CPU_CLK135M_DPLLSS_N OUT 6 77
AJ39 CPU_CLK135M_DPLLSS_P
AD43 CLKOUT_DP_P OUT 6 77
77 26 OUT PCIE_CLK100M_TBT_N CLKOUT_PCIE_N3
PCIE_CLK100M_TBT_P AD45
77 26 OUT CLKOUT_PCIE_P3 AF35
CLKOUT_DPNS_N CPU_CLK135M_DPLLREF_N OUT 6 77

PCH_CLKRQ3_L_GPIO25 T3 AF36 CPU_CLK135M_DPLLREF_P

NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks. 11 PCIECLKRQ3*/GPIO25 CLKOUT_DPNS_P OUT 6 77

PEG-attached (CPU) PCIe devices must use one set, Unused clock terminations for FCIM Mode
while PCH-attached PCIe devices use the other set. NC
AF43
CLKOUT_PCIE_N4 CLKIN_DMI_N AY24 PCIE_CLK100M_PCHN R1196 10K 1 2
5% 1/20W MF 201
If 2 or less devices are attached to PEG the NC
AF45
CLKOUT_PCIE_P4 CLKIN_DMI_P AW24 PCIE_CLK100M_PCHP R1195 10K 1 2

CLOCKS
5% 1/20W MF 201
CLKOUT_PEG outputs can be used for those devices. V3
28 11 IN TBT_CLKREQ_L PCIECLKRQ4*/GPIO26
CLKIN_GND_N AR24 PCH_CLKIN_GNDN R1171 10K 1 2

B NC
AE44
CLKOUT_PCIE_N5
CLKIN_GND_P AT24 PCH_CLKIN_GNDP R1170 10K 1 2
5%

5%
1/20W

1/20W
MF

MF
201

201
B
AE42
NC CLKOUT_PCIE_P5
CLKIN_DOT96_N H33 PCH_CLK96M_DOTN R1192 10K 1 2
5% 1/20W MF 201
11 PCH_CLKRQ5_L_GPIO44 AA2
PCIECLKRQ5*/GPIO44 CLKIN_DOT96_P G33 PCH_CLK96M_DOTP R1191 10K 1 2
(IPU-RSMRST#) 5% 1/20W MF 201

NC
AB40
CLKOUT_PCIE_N6 CLKIN_SATA_N BE6 PCH_CLK100M_SATAN R1194 10K 1 2
5% 1/20W MF 201
NC
AB39
CLKOUT_PCIE_P6 CLKIN_SATA_P BC6 PCH_CLK100M_SATAP R1193 10K 1 2
5% 1/20W MF 201
PEG_CLKREQ_L AE4
11 PCIECLKRQ6*/GPIO45
REFCLK14IN F45 PCH_CLK14P3M_REFCLK R1197 10K 1 2
5% 1/20W MF 201
AJ44 D17 PCH_CLK33M_PCIIN
NC CLKOUT_PCIE_N7 CLKIN_33MHZLOOPBACK IN 19 79
AJ42
CLKOUT_PCIE_P7 R1172
NC 340
AM43 SYSCLK_CLK25M_SB_R 1 2 SYSCLK_CLK25M_SB
Y3 XTAL25_IN 79
IN 19 79
11 PCH_CLKRQ7_L_GPIO46 PCIECLKRQ7*/GPIO46 AL44
(IPU-RSMRST#) XTAL25_OUT NC 1.5V -> 1.1V 1%
1/16W
1 MF-LF
=PP3V3_SUS_PCH_GPIO 12 13 14 70
R1173 402
C40 TP_PCH_GPIO64_CLKOUTFLEX0 1K
(IPD-PWROK) CLKOUTFLEX0/GPIO64 72
=PP3V3_S0_PCH_GPIO 12 14 28 70 AH43 F38 1%
CLKOUT_ITPXDP_N (IPD-PWROK) CLKOUTFLEX1/GPIO65 TP_PCH_GPIO65_CLKOUTFLEX1 1/20W
NC 72
MF
AH45 F36 TP_PCH_GPIO66_CLKOUTFLEX2
NC CLKOUT_ITPXDP_P (IPD-PWROK) CLKOUTFLEX2/GPIO66 72 201
R1177 4.7K 1 2 PCH_SPKR 11 F39
2
5% 1/20W MF 201 (IPD-PWROK) CLKOUTFLEX3/GPIO67 TP_PCH_GPIO67_CLKOUTFLEX3 72
R1176 10K 1 2 DP_TBT_SEL 11 41 58
5% 1/20W MF 201 =PP1V5_S0_PCH_CLK 19 70
R1178 4.7K 1 2 PCH_SATALED_L 11 33 AM45
5% 1/20W MF 201 ICLK_IREF
R1134 10K 1 2 DP_AUXIO_EN 11 18 29 30 79 19 OUT LPC_CLK33M_SMC_R D44
CLKOUT_33MHZ0 (IPD-PWROK)
5% 1/20W MF 201
R1133 10K 1 2 SATARDRVR_EN 11 18 79 19 OUT LPC_CLK33M_LPCPLUS_R E44
CLKOUT_33MHZ1 (IPD-PWROK) TP19 AD39
NC
5% 1/20W MF 201 B42 AD38
TP_PCI_CLK33M_OUT2 CLKOUT_33MHZ2 (IPD-PWROK) TP18
R1143 10K 1 2 SSD_CLKREQ_L
72
NC
5% 1/20W MF 201
11 33
72 TP_PCI_CLK33M_OUT3 F41
CLKOUT_33MHZ3 (IPD-PWROK) R1190 =PP1V5_S0_PCH_VCCVRM_BIAS 17
R1142 10K 1 2 ENET_CLKREQ_L 11 18 35 A40 AN44
7.5K
5% 1/20W MF 201 79 19 OUT PCH_CLK33M_PCIOUT CLKOUT_33MHZ4 (IPD-PWROK) DIFFCLK_BIASREF PCH_DIFFCLK_BIASREF 2 1
R1169 10K AP_CLKREQ_L
A R1144 10K
1

1
2

2
5%
5%
1/20W
1/20W
MF
MF
201
201
PCH_CLKRQ3_L_GPIO25
11 18 32

11
PLACE_NEAR=U1100.AN44:2.54mm 1%
1/20W
MF
SYNC_MASTER=J16_KENNY SYNC_DATE=01/21/2013 A
R1145 10K 1 2 TBT_CLKREQ_L 11 28 201 PAGE TITLE
5% 1/20W MF 201
R1147 10K 1 2
5% 1/20W MF 201
PCH_CLKRQ5_L_GPIO44 11 PCH RTC/HDA/JTAG/SATA/CLK
R1114 10K 2 1 PEG_CLKREQ_L 11 DRAWING NUMBER SIZE
5% 1/20W MF 201
R1115 10K 1 2
5% 1/20W MF 201
PCH_CLKRQ7_L_GPIO46 11
Apple Inc. 051-0164 D
REVISION
R1146 10K 1 2 PCH_PEGCLKRQA_L_GPIO47 11 R

R1148 10K 1 2
5% 1/20W MF 201
PCH_PEGCLKRQB_L_GPIO56
12.4.0
11
5% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1179 10K 1 2 ENET_MEDIA_SENSE 11 35 80 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V. I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 11 OF 123
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V. II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
If HDA = S0, must also ensure that signal cannot be high in S3.
IV ALL RIGHTS RESERVED 11 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE

DMI_N2S_N<0> AW22
DMI_RXN0 U1100 FDI_RXN0 AJ35
77 5 IN
LYNXPOINT NC
DMI_N2S_N<1> AR20 AL35
77 5 IN DMI_RXN1 MOBILE FDI_RXN1 NC
DMI_N2S_N<2> AP17
77 5 IN DMI_RXN2 FCBGA AJ36
AV20 FDI_RXP0 NC
77 5 IN DMI_N2S_N<3> DMI_RXN3 (4 OF 11) AL36
FDI_RXP1 NC
DMI_N2S_P<0> AY22
77 5 IN DMI_RXP0
DMI_N2S_P<1> AP20
77 5 IN DMI_RXP1
DMI_N2S_P<2> AR17
77 5 IN DMI_RXP2
DMI_N2S_P<3> AW20 AV43
77 5 IN DMI_RXP3 TP16 NC
AY45
TP5 NC
DMI_S2N_N<0> BD21 AV45
77 5 DMI_TXN0 TP15 NC
D 77 5
OUT
OUT DMI_S2N_N<1> BE20

BD17
DMI_TXN1 TP10 AW44
NC D
77 5 OUT DMI_S2N_N<2> DMI_TXN2
DMI_S2N_N<3> BE18
77 5 OUT DMI_TXN3

DMI

FDI
DMI_S2N_P<0> BB21 AL39 FDI_CSYNC
77 5 OUT DMI_TXP0 FDI_CSYNC OUT 5 78

DMI_S2N_P<1> BC20 AL40 FDI_INT

77 5 OUT DMI_TXP1 FDI_INT OUT 5 78

DMI_S2N_P<2> BB17
77 5 OUT DMI_TXP2
70 13 12 =PP1V5_S0_PCH_RCOMP BC18
=PP1V5_S0_PCH_RCOMP 12 13 70
77 5 OUT DMI_S2N_P<3> DMI_TXP3

BE16 AT45
DMI_IREF FDI_IREF
R1200 1 R1210 1
7.5K AW17 AU42
7.5K =PPVRTC_G3_PCH 11 15 70
1%
NC TP12 TP17 NC 1%
1/20W AV17 AU44 1/20W
MF
NC TP7 TP13 NC MF
1
201 201 R1215
2 2
PLACE_NEAR=U1100.AR44:12.7mm
PLACE_NEAR=U1100.AY17:12.7mm AY17 AR44
330K
77 PCH_DMI_RCOMP DMI_RCOMP FDI_RCOMP 78 PCH_FDI_RCOMP 5%
1/20W
MF
2 201
PCH_SUSACK_L R6
SUSACK* (IPU) C8
DSWVRMEN PCH_DSWVRMEN
PM_SYSRST_L AM1
44 19 IN SYS_RESET* L13 PM_RSMRST_PCH_L

SYSTEM POWER
DPWROK IN 12 18 69

MANAGEMENT
PM_PCH_SYS_PWROK AD7
69 45 18 IN SYS_PWROK K3
1
WAKE* PCIE_WAKE_L IN 12 32 36
1
R1286 69 39 20 18 IN PM_PCH_PWROK F10
PWROK
(IPD-DeepSx) R1209
AN7 PM_CLKRUN_L
0 CLKRUN* BI 12 44 45 46 10K
5% AB7 5%
1/20W 69 IN PM_PCH_APWROK APWROK U7 1/20W
MF SUS_STAT*/GPIO61 LPC_PWRDWN_L OUT 20 44 46 MF
0201
2
21 6 PM_MEM_PWRGD H3
DRAMPWROK 2 201
OUT Y6 PM_CLK32K_SUSCLK_R
(OD) SUSCLK/GPIO62 OUT 45 79
J2 (IPU-RSMRST#)
69 18 12 IN PM_RSMRST_PCH_L RSMRST* Y7
SLP_S5*/GPIO63 PM_SLP_S5_L OUT 12 32 44 68

C 70 14 13 11 =PP3V3_SUS_PCH_GPIO
PCH_SUSWARN_L J4
SUSWARN*/SUSPWRNACK/GPIO30
SLP_S4* C6 PM_SLP_S4_L OUT 12 44 68
C
K1
R1205 1 44 18 12 IN PM_PWRBTN_L PWRBTN* (IPU)
SLP_S3* H1 PM_SLP_S3_L 12 21 36 44 45 68 69
OUT
10K E6
5% 12 PCH_GPIO31 ACPRESENT/GPIO31 F3
1/20W (IPD-DeepSx) SLP_A* TP_PM_SLP_A_L
MF K7
201 12 IN PCH_GPIO72 BATLOW*/GPIO72 F1
2
SLP_SUS* PM_SLP_SUS_L OUT 12

PCH_RI_L N4
RI* AY3
PMSYNCH PM_SYNC OUT 6 76
AB10
NC TP21 G5
SLP_LAN* TP_PCH_SLP_LAN_L
TP_PCH_SLP_WLAN_L D2
SLP_WLAN*/GPIO29

OMIT_TABLE
T45
NC VGA_BLUE U1100
U44
VGA_GREEN LYNXPOINT
NC V45 MOBILE
NC VGA_RED FCBGA
R40 TP_DP_IG_B_DDC_CLK
(5 OF 11) DDPB_CTRLCLK 71
M43 R39 TP_DP_IG_B_DDC_DATA
NC VGA_DDC_CLK DDPB_CTRLDATA 71
VGA DAC Disabled per SB M45 (IPD-PLTRST#)
NC VGA_DDC_DATA R35
DDPC_CTRLCLK TP_DP_IG_C_DDC_CLK 71
DG v1.0 (Table 12-18).

CRT
R36 TP_DP_IG_C_DDC_DATA
N42 DDPC_CTRLDATA 71
NC VGA_HSYNC (IPD-PLTRST#)
N44 N40 TP_DP_IG_D_DDC_CLK
NC VGA_VSYNC DDPD_CTRLCLK 71
N38 TP_DP_IG_D_DDC_DATA
DDPD_CTRLDATA 71
(IPD-PLTRST#)

DISPLAY
U40
DAC_IREF
U39 H45 TP_DP_IG_B_AUXCHN
VGA_IRTN DDPB_AUXN 71
K43 TP_DP_IG_C_AUXCHN
DDPC_AUXN 71

B NC
N36
EDP_BKLTCTL
DDPD_AUXN J42 TP_DP_IG_D_AUXCHN 71
B

EDP
H43 TP_DP_IG_B_AUXCHP
K36 DDPB_AUXP 71
NC EDP_BKLTEN K45
DDPC_AUXP TP_DP_IG_C_AUXCHP 71
G36 J44 TP_DP_IG_D_AUXCHP
NC EDP_VDDEN DDPD_AUXP 71

70 28 14 12 11 =PP3V3_S0_PCH_GPIO K40
DDPB_HPD TP_DP_IG_B_HPD 71
R1260 10K 1 2 PCI_INTA_L H20
PIRQA* K38
5% 1/20W MF 201 DDPC_HPD TP_DP_IG_C_HPD 71
R1261 10K 1 2 PCI_INTB_L L20
PIRQB* H39
=PP3V3_S5_PCH_GPIO 70 5% 1/20W MF 201 DDPD_HPD TP_DP_IG_D_HPD 71
R1262 10K 1 2 PCI_INTC_L K17
PIRQC*
=PP3V3_S0_PCH_GPIO 11 12 14 28 70 5% 1/20W MF 201
R1263 10K 1 2 PCI_INTD_L M20
PIRQD*
5% 1/20W MF 201 G17
PIRQE*/GPIO2 SDCONN_OC_L IN 12 37

ENET_LOW_PWR_PCH A12 F17 AUD_IP_PERIPHERAL_DET

20 12 OUT GPIO50 PIRQF*/GPIO3 IN 12 58
R1226 10K 1 2 PCH_GPIO31 12
B13 L15
5% 1/20W MF 201 20 12 OUT AUD_IPHS_SWITCH_EN_PCH GPIO52 PIRQG*/GPIO4 TBT_PWR_REQ_L IN 12 26

PCI
R1239 3.0K 1 2 PM_PWRBTN_L 12 18 44 32 12 OUT BT_PWR_RST_L C12
GPIO54 PIRQH*/GPIO5 M15 AUD_I2C_INT_L IN 12 56
5% 1/20W MF 201
R1240 10K 1 2 PCH_GPIO72 12
C10 AD10
5% 1/20W MF 201 TP_PCH_STRP_BBS1 GPIO51 (IPU) PME* TP_PCI_PME_L
NO STUFF
R1291 10K 1 2 PM_CLKRUN_L 12 44 45 46 TP_PCH_STRP_ESI_L A10
GPIO53
5% 1/20W MF 201 AL6 Y11
45 IN PCH_STRP_TOPBLK_SWP_L GPIO55 PLTRST* PLT_RESET_L OUT 20
R1216 10K 1 2 ENET_LOW_PWR_PCH 12 20 (IPU-PWROK&PCIRST#)
5% 1/20W MF 201
R1217 100K 1 2 AUD_IPHS_SWITCH_EN_PCH 12 20
5% 1/20W MF 201
R1218 10K 1 2 BT_PWR_RST_L 12 32
5% 1/20W MF 201
R1230 10K 1 2 SDCONN_OC_L 12 37
5% 1/20W MF 201

NO STUFF Redundant to pull-up on audio page

R1214 100K 1 2 AUD_IP_PERIPHERAL_DET 12 58
5% 1/20W MF 201
R1231 10K 1 2 TBT_PWR_REQ_L 12 26
5% 1/20W MF 201

A R1233 10K
NO STUFF
1 2
Redundant to pull-up on audio page
AUD_I2C_INT_L 12 56
SYNC_MASTER=J16_KENNY SYNC_DATE=01/21/2013 A
5% 1/20W MF 201
PAGE TITLE
R1225 1K 1 2
5% 1/20W MF 201
IN 12 32 36 PCH DMI/FDI/PM/GFX/PCI
DRAWING NUMBER SIZE
R1224 100K 2 1 PM_SLP_S3_L PCIE_WAKE_L =TBT_WAKE_L
R1221 100K 2 1
5% 1/20W MF 201
PM_SLP_S4_L
12 21 36 44 45 68 69

12 44 68
MAKE_BASE=TRUE IN 26

Apple Inc. 051-0164 D

5% 1/20W MF 201 REVISION
R1222 100K 2 1 PM_SLP_S5_L 12 32 44 68 R

R1223 100K 2 1
5% 1/20W MF 201
PM_SLP_SUS_L
12.4.0
12
5% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 12 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 12 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE USB Port Assignments:
U1100 USB2N0 B37 USB_EXTA_0_N BI 42 80
LYNXPOINT D37 Ext A (LS/FS/HS)
USB2P0 USB_EXTA_0_P BI 42 80
MOBILE
FCBGA A38 USB_EXTC_1_N
USB2N1 BI 43 80
(9 OF 11) C38 Ext C (LS/FS/HS)
USB2P1 USB_EXTC_1_P BI 43 80

AW31 A36
NC PERN1_USB3RN3 USB2N2 NC
AY31 C36
NC PERP1_USB3RP3 USB2P2 NC
BE32 A34
NC PETN1_USB3TN3 USB2N3 NC
BC32 C34
NC PETP1_USB3TP3 USB2P3 NC

D NC
AT31
PERN2_USB3RN4
USB2N4
USB2P4
B33

D33
NC
NC
D
AR31
NC PERP2_USB3RP4 F31
USB2N5 NC
BD33 G31
NC PETN2_USB3TN4 USB2P5 NC
BB33
NC PETP2_USB3TP4 K31
USB2N6 NC
L31
USB2P6 NC
PCIE_AP_D2R_N AW33
77 32 IN PERN3 G29
AY33 USB2N7 NC
77 32 IN PCIE_AP_D2R_P PERP3 H29
AirPort USB2P7 NC
PCIE_AP_R2D_C_N BE34
77 32 OUT PETN3 A32
BC34 USB2N8 USB_EXTB_8_N BI 42 80
77 32 OUT PCIE_AP_R2D_C_P PETP3 C32 Ext B (LS/FS/HS)
USB2P8 USB_EXTB_8_P BI 42 80

A30 USB_EXTD_9_N
AT33 USB2N9 BI 43 80
77 35 IN PCIE_ENET_D2R_N PERN4 C30 Ext D (LS/FS/HS)
AR33 USB2P9 USB_EXTD_9_P BI 43 80
77 35 IN PCIE_ENET_D2R_P PERP4
ENET B29
BE36 USB2N10 USB_CAMERA_N BI 38 80
77 35 OUT PCIE_ENET_R2D_C_N PETN4 D29 CAMERA
BC36 USB2P10 USB_CAMERA_P BI 38 80
77 35 OUT PCIE_ENET_R2D_C_P PETP4
A28 USB_BT_N
USB2N11 BI 32 80
C28 BT
AW36 USB2P11 USB_BT_P BI 32 80
77 26 IN PCIE_TBT_D2R_N<0> PERN5
PCIE_TBT_D2R_P<0> AV36 G26
77 26 IN PERP5 USB2N12 NC
F26
BD37 USB2P12 NC
77 26 OUT PCIE_TBT_R2D_C_N<0> PETN5

PCI-E

USB
PCIE_TBT_R2D_C_P<0> BB37 F24
77 26 OUT PETP5 USB2N13 NC
G24
USB2P13 NC
(IPD)
AY38 USB3 Port Assignments:
77 26 IN PCIE_TBT_D2R_N<1> PERN6 AR26
AW38 USB3RN1 USB3_EXTA_RX_F_N IN 42 80
77 26 IN PCIE_TBT_D2R_P<1> PERP6 AP26

C 77 26 OUT PCIE_TBT_R2D_C_N<1> BC38

PETN6
USB3RP1
USB3TN1 BE24
USB3_EXTA_RX_F_P
USB3_EXTA_TX_N
IN
OUT
42 80

42 80
Ext A (SS) C
PCIE_TBT_R2D_C_P<1> BE38 BD23 USB3_EXTA_TX_P
77 26 OUT PETP6 USB3TP1 OUT 42 80
TBT
AW26 USB3_EXTB_RX_F_N
USB3RN2 IN 42 80

PCIE_TBT_D2R_N<2> AT40 AV26 USB3_EXTB_RX_F_P

77 26 IN PERN7 USB3RP2 IN 42 80
AT39 BD25 Ext B (SS)
77 26 IN PCIE_TBT_D2R_P<2> PERP7 USB3TN2 USB3_EXTB_TX_N OUT 42 80
BC24 USB3_EXTB_TX_P
BE40 USB3TP2 OUT 42 80
77 26 OUT PCIE_TBT_R2D_C_N<2> PETN7
PCIE_TBT_R2D_C_P<2> BC40 AW29 USB3_EXTC_RX_F_N
77 26 OUT PETP7 USB3RN5 IN 43 80
AV29 USB3_EXTC_RX_F_P
USB3RP5 IN 43 80
BE26 Ext C (SS)
AN38 USB3TN5 USB3_EXTC_TX_N OUT 43 80
77 26 IN PCIE_TBT_D2R_N<3> PERN8 BC26
AN39 USB3TP5 USB3_EXTC_TX_P OUT 43 80
77 26 IN PCIE_TBT_D2R_P<3> PERP8
AR29 USB3_EXTD_RX_F_N
BD42 USB3RN6 IN 43 80
77 26 OUT PCIE_TBT_R2D_C_N<3> PETN8 AP29
BD41 USB3RP6 USB3_EXTD_RX_F_P IN 43 80
77 26 OUT PCIE_TBT_R2D_C_P<3> PETP8 BD27 Ext D (SS)
USB3TN6 USB3_EXTD_TX_N OUT 43 80
BE28 USB3_EXTD_TX_P
USB3TP6 OUT 43 80

K24 PCH_USB_RBIAS
USBRBIAS* 80
K26
USBRBIAS PLACE_NEAR=U1100.K24:11.4mm
1
R1370
M33 22.6
TP24 NC
L33 1%
TP23 NC 1/20W
MF
201
70 12 =PP1V5_S0_PCH_RCOMP 2
P3 USB_EXTA_OC_L
OC0*/GPIO59 IN 13 18 42
V1 USB_EXTC_OC_L
OC1*/GPIO40 IN 13 18 43
BE30 U2 PCH_GPIO41
1
PCIE_IREF OC2*/GPIO41 OUT 13 18
R1300
B 7.5K
1%
NC
BC30
TP11
OC3*/GPIO42
OC4*/GPIO43
P1

M3
PCH_GPIO42
USB_EXTB_OC_L
OUT
IN
13 18

13 18 42
B
1/20W BB29 T1
MF TP6 OC5*/GPIO9 USB_EXTD_OC_L 13 18 43
201
NC N2
IN
2
PLACE_NEAR=U1100.BD29:12.7mm OC6*/GPIO10 PCH_GPIO10 OUT 13 18

PCH_PCIE_RCOMP BD29 M1 SDCONN_STATE_CHANGE

77 PCIE_RCOMP OC7*/GPIO14 IN 13 18 37

OMIT_TABLE

79 46 44 BI LPC_AD<0> R1340 33 1 2 79 LPC_AD_R<0> A20

LAD0 (IPU) U1100 SMBALERT*/GPIO11 N7 PCH_SMBALERT_L 13
5% 1/20W MF 201 LYNXPOINT
79 46 44 BI LPC_AD<1> R1341 33 1 2 79 LPC_AD_R<1> C20
LAD1 (IPU) R10
5% 1/20W MF 201 MOBILE SMBCLK SMBUS_PCH_CLK OUT 47 81
79 46 44 BI LPC_AD<2> R1342 33 1 2 79 LPC_AD_R<2> A18
LAD2 (IPU)
FCBGA U11
5% 1/20W MF 201 SMBDATA SMBUS_PCH_DATA BI 47 81
79 46 44 BI LPC_AD<3> R1343 33 1 2 79 LPC_AD_R<3> C18
LAD3 (IPU) (3 OF 11)
5% 1/20W MF 201

79 46 44 OUT LPC_FRAME_L R1344 33 1 2 79 LPC_FRAME_R_L B21

LFRAME* SML0ALERT*/GPIO60 N8 PCH_SML0ALERT_L 13

SMBUS
5% 1/20W MF 201

LPC
TP_LPC_DREQ0_L D21 U8 SML_PCH_0_CLK
72 LDRQ0* (IPU) SML0CLK OUT 47 81

TBT_PWR_EN_PCH G20 R7 SML_PCH_0_DATA

20 13 OUT LDRQ1*/GPIO23 SML0DATA BI 47 81
(IPU-LDRQ1#?)
LPC_SERIRQ AL11
46 44 13 BI SERIRQ H6
=PP3V3_SUS_PCH_GPIO 11 12 14 70 SML1ALERT*/PCHHOT*/GPIO74 PCH_SML1ALERT_L 13

K6 SML_PCH_1_CLK
SML1CLK/GPIO58 IN 47
=PP3V3_S3RS4_PCH_GPIO 70
N11
SML1DATA/GPIO75 SML_PCH_1_DATA BI 47
=PP3V3_S0_PCH 19 70

SPI_CLK_R AJ11
79 46 OUT SPI_CLK
R1350 10K 1 2 LPC_SERIRQ CL_CLK AF11 TP_CLINK_CLK
C-LINK
13 44 46 AJ7 (IPU/IPD)
5% 1/20W MF 201 79 46 OUT SPI_CS0_R_L SPI_CS0* (IPU)
R1351 10K 1 2 TBT_PWR_EN_PCH 13 20 AL7 (IPU/IPD) CL_DATA AF10 TP_CLINK_DATA
5% 1/20W MF 201 NC SPI_CS1* (IPU)
R1360 10K 1 2 USB_EXTA_OC_L CL_RST* AF7 TP_CLINK_RESET_L
SPI

13 18 42 AJ10
5% 1/20W MF 201 NC SPI_CS2* (IPU)
R1361 10K USB_EXTC_OC_L
A R1362 10K
1

1
2

2
5%
5%
1/20W
1/20W
MF
MF
201
201
PCH_GPIO41
13 18 43

13 18 79 46 BI SPI_MOSI_R AH1
SPI_MOSI (IPD)
TP1 BA45 SYNC_MASTER=J16_KENNY SYNC_DATE=01/21/2013 A
R1368 10K 1 2 PCH_GPIO42 13 18
NC PAGE TITLE
SPI_MISO AH3 BC45
5% 1/20W MF 201 SPI_MISO (IPU) TP2
R1320 10K 1 2
5% 1/20W MF 201
USB_EXTB_OC_L 13 18 42
79 46 BI
TP4 BE43
NC PCH PCI-E/USB
R1321 10K 1 2 USB_EXTD_OC_L AJ4
SPI_IO2 (IPU)
NC DRAWING NUMBER SIZE
5% 1/20W MF 201
13 18 43
NC TP3 BE44
R1367 10K 2 1 PCH_GPIO10 13 18
NC 051-0164 D
R1369 10K 1 2
5% 1/20W MF 201
SDCONN_STATE_CHANGE 13 18 37
NC
AJ2
SPI_IO3 (IPU) TD_IREF AY43 PCH_TD_IREF Apple Inc. REVISION
5% 1/20W MF 201 R
1
12.4.0
R1380 NOTICE OF PROPRIETARY PROPERTY: BRANCH
8.2K
1% THE INFORMATION CONTAINED HEREIN IS THE
1/20W PROPRIETARY PROPERTY OF APPLE INC.
R1353 10K 1 2 PCH_SMBALERT_L 13 MF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/20W MF 201 201
R1354 10K 1 2 PCH_SML0ALERT_L 13
2 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 13 OF 123
5% 1/20W MF 201 II NOT TO REPRODUCE OR COPY IT
R1355 10K 1 2 PCH_SML1ALERT_L 13
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
5% 1/20W MF 201
IV ALL RIGHTS RESERVED 13 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE

20 IN TBT_CIO_PLUG_EVENT_ISOL AT8
BMBUSY*/GPIO0 U1100
LYNXPOINT
14 FW_PME_L F13
TACH1/GPIO1 MOBILE
FCBGA =PP1V05_S0_PCH_V_PROC_IO 15 17 70

DPMUX_UC_IRQ A14
14 TACH2/GPIO6 (6 OF 11) NO STUFF
1
81 44 14 SMC_RUNTIME_SCI_L G15
TACH3/GPIO7 R1457
IN
1K
Y1 5%
67 18 OUT HDD_PWR_EN GPIO8 (IPU-RSMRST#) 1/16W
MF-LF
K13 402
36 14 OUT WOL_EN LAN_PHY_PWR_CTRL/GPIO12 2

AN10 PCH_A20GATE
AB11 TP14 14
14 MEM_VDD_SEL_1V5_L GPIO15
NO STUFF
D 18 14 IN PCH_GPIO16 AN2
SATA4GP/GPIO16
(IPU-Boot/SATA4GP?)
(IPD) PECI AY1 PCH_PECI R1470 43 1 2
5%
CPU_PECI
1/20W
BI 6 44 45 76 D
C14 MF 201
46 14 BI LPCPLUS_GPIO TACH0/GPIO17 AT6
RCIN* PCH_RCIN_L 14

CPU/MISC
JTAG_TBT_TMS_PCH BB4
20 14 OUT SCLOCK/GPIO22
Y10 PROCPWRGD AV3 PCH_PROCPWRGD R1440 0 1 2 CPU_PWRGD OUT 6 18 76
26 14 BI TBT_GO2SX_BIDIR GPIO24 5% 1/20W
MF 0201

81 44 14 IN SMC_WAKE_SCI_L R11
GPIO27 (IPU-DeepSx) THRMTRIP* AV1 45 PM_THRMTRIP_L_R R1456 390 1 2 PM_THRMTRIP_L IN 6 45 76
5% 1/20W
AD11 MF 201
21 OUT ISOLATE_CPU_MEM_L GPIO28 AU4
PLTRST_PROC* CPU_RESET_L OUT 6 18 76

GPIO
TBT_SW_RESET_L AN6
28 OUT GPIO34
N10
AP1 VSS
18 3 OUT GPU_GOOD GPIO35/NMI*
PCH_GPIO36 AT3
18 14 OUT SATA2GP/GPIO36
(IPD-PLTRST#)
JTAG_ISP_TCK AK1 A2
20 18 14 OUT SATA3GP/GPIO37
(IPD-PLTRST#) A41
JTAG_ISP_TDO AT7
20 14 IN SLOAD/GPIO38 A43
70 28 14 12 11 =PP3V3_S0_PCH_GPIO AM3 A44
20 14 OUT JTAG_ISP_TDI SDATAOUT0/GPIO39
B1
AN4
R1475 1
1 FW_PWR_EN_PCH SDATAOUT1/GPIO48
R1474 14
B2
10K 10K AK3 B44
5% 5% 18 14 IN PCH_GPIO49 SATA5GP/GPIO49
1/20W 1/20W (IPU-Boot/SATA5GP?) B45
MF MF U12
201
2 2
201 79 46 BI SPIROM_USE_MLB GPIO57 BA1
33.2
39 OUT PCH_CAM_EXT_BOOT_R_L 1 2 R1461 14 PCH_CAM_EXT_BOOT_L C16
TACH4/GPIO68 BC1
1% 1/20W MF 201
33.2 BD1
39 PCH_CAM_RESET_R 1 2 R1462 14 PCH_CAM_RESET D13
TACH5/GPIO69
OUT 1% 1/20W MF 201 VSS BD2
PLACE_NEAR=U1100.C16:10MM G13 BD44
PLACE_NEAR=U1100.D13:10MM PCH_GPIO70 TACH6/GPIO70
C PCH_GPIO71 H15
(IPU-Boot?)

TACH7/GPIO71
(IPU-Boot?)
BD45

BE2
C
BE3

BE41 D1

BE5 E1

C45 VSS E45

A5 A4

14
PCH_CAM_EXT_BOOT_L

14
PCH_CAM_RESET

R1422 1 1
R1423
1K 1K
5% 5%
1/20W 1/20W
MF MF
201 2 2 201

B B

=PP3V3_SUS_PCH_GPIO 11 12 13 70

=PP3V3_S0_PCH_GPIO 11 12 14 28 70

R1485 10K 1 2 FW_PME_L 14

5% 1/20W MF 201
R1411 20K 2 1 DPMUX_UC_IRQ 14
5% 1/20W MF 201
R1496 10K 1 2 SMC_RUNTIME_SCI_L 14 44 81
5% 1/20W MF 201
R1494 10K 1 2 WOL_EN 14 36
5% 1/20W MF 201
R1489 10K 1 2 MEM_VDD_SEL_1V5_L 14
5% 1/20W MF 201
R1495 10K 1 2 PCH_GPIO16 14 18
5% 1/20W MF 201
R1490 100K 1 2 LPCPLUS_GPIO 14 46
5% 1/20W MF 201
R1412 10K 2 1 JTAG_TBT_TMS_PCH 14 20
5% 1/20W MF 201
R1492 10K 1 2 TBT_GO2SX_BIDIR 14 26
5% 1/20W MF 201
R1491 10K SMC_WAKE_SCI_L
A R1498 10K
1

2
2

1
5%
5%
1/20W
1/20W
MF
MF
201
201
PCH_GPIO36
14 44 81

14 18 SYNC_MASTER=J16_KENNY SYNC_DATE=03/07/2013 A
R1413 10K 2 1 JTAG_ISP_TCK 14 18 20
PAGE TITLE
5% 1/20W MF 201
R1486 10K 1 2
5% 1/20W MF 201
JTAG_ISP_TDO 14 20 PCH GPIO/MISC/NCTF
R1499 10K 1 2 JTAG_ISP_TDI 14 20 DRAWING NUMBER SIZE
5% 1/20W MF 201
R1484 10K 1 2
5% 1/20W MF 201
FW_PWR_EN_PCH 14
Apple Inc. 051-0164 D
R1497 10K 1 2 PCH_GPIO49 14 18 REVISION
5% 1/20W MF 201 R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1450 10K 1 2 PCH_A20GATE 14 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
R1455 10K 1 2 PCH_RCIN_L 14 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/20W MF 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 14 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 14 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE

U1100
LYNXPOINT
MOBILE
FCBGA
70 17 =PP1V05_S0_PCH_VCC (7 OF 11)
Y26 P45
VCC: 1.312 A Max, 130mA Idle VCCADAC1_5 CKPLUS_WAIVE=PwrTerm2Gnd
AA24 VGA DAC Disabled per SB

CRT
VSS P43
AA26
DG v1.0 (Table 12-18).
AD20 VCCADACBG3_3 M31 CKPLUS_WAIVE=PwrTerm2Gnd
AD22

AD24
=PP1V5_S0_PCH_VCCVRM_FDI 17
BB44
VCCVRM VCCVRM: 183mA Max, 68mA Idle
D
AD26
=PP1V05_S0_PCH_VCCIO_FDI D

FDI
17 70
AD28
AN34
AE18 VCC VCCIO: 3629mA Max, 264mA Idle
VCCIO AN35
AE20

AE22 =PP3V3_S0_PCH_VCC3_3_HVCMOS 17 70

HVCMOS
AE24 R30
VCC3_3: 133mA Max, 3mA Idle
AE26 VCC3_3 R32

AG18

AG20
DCPSUS1 Y12
AG22 NC
AG24
=PP3V3_SUS_PCH_VCCSUS_USB3 70
AJ30
R1550 VCCSUS3_3: 261mA Max, 6mA Idle
PLACE_NEAR=R1550.1:2.54mm PLACE_NEAR=U1100.U14:2.54mm
5.11 VCCSUS3_3 AJ32
PPVOUT_S5_PCH_DCPSUSBYP 1 2 PPVOUT_S5_PCH_DCPSUSBYP_R U14 DCPSUSBYP
MIN_LINE_WIDTH=0.2 mm MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm 1% MIN_NECK_WIDTH=0.2 mm Powered in DeepSx

CORE

USB3
1/20W AJ26
VOLTAGE=1.05V VOLTAGE=1.05V NC
C1550 1 MF-LF
201 DCPSUS3 AJ28
1UF NC
10%
6.3V
=PP1V05_S0_PCH_VCCIO 17 70
CERM 2
VCCIO AK20 VCCIO: 3629mA Max, 264mA Idle
402
=PP1V5_S0_PCH_VCCVRM_USB3 17
AK26 VCCVRM: 183mA Max, 68mA Idle
VCCVRM AK28

=PP1V5_S0_PCH_VCCVRM_PCIE 17

PCIE/DMI
VCCVRM BE22 VCCVRM: 183mA Max, 68mA Idle

=PP1V05_S0M_PCH_VCCASW AK18
70 17 15 VCCIO
U18
VCCASW: 670mA Max, 34mA Idle
U20
=PP1V5_S0_PCH_VCCVRM_SATA 17

C VCCVRM AN11 VCCVRM: 183mA Max, 68mA Idle

SATA
U22

U24
VCCIO AK22
V18

V20
VCCASW
V22 AM18

V24 AM20

VCCMPHY
Y18 AM22

Y20 VCCIO AP22

Y22 AR22

AA18 AT22

OMIT_TABLE
U1100
LYNXPOINT
MOBILE
FCBGA
70 17 =PP3V3_SUS_PCH_VCCSUS_USB (8 OF 11) =PP3V3_SUS_PCH_VCCSUS_GPIO 17 70

VCCSUS3_3: 261mA Max, 6mA Idle R24 R20 VCCSUS3_3: 261mA Max, 6mA Idle
R26 VCCSUS3_3 R22
R28 VCCSUS3_3
U26 A16 =PP3V3_S5_PCH_VCCDSW
VCCDSW3_3 17 70

15 mA Max, 1mA Idle

GPIO/LPC
BYPASS=U1100.AA14:6.35mm
M24 AA14 PPVOUT_S0_PCH_DCPSST
VSS DCPSST
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
70 17 =PP1V05_S0_PCH_VCCUSBPLL U35 VCCUSBPLL AE14 1 C1580
??mA Max, ??mA Idle AF12 =PP3V3_S0_PCH_VCC3_3_GPIO 17 70
0.1UF
VCC3_3 10%

B 70 17 =PP3V3_S0_PCH_VCC3_3_USB
VCC3_3: 133mA Max, 3mA Idle
L24 VCC3_3 AG14
VCC3_3: 133mA Max, 3mA Idle 10V
2 X5R-CERM
0201
B

USB
=PP1V05_S0_PCH_VCCIO_USB2 U30 U36 =PP1V05_S0_PCH_VCCIO_GPIO
70 17 VCCIO 70

VCCIO: 3629mA Max, 264mA Idle V28 VCCIO: 3629mA Max, 264mA Idle
V30 VCCIO
Y30

HDA
A26 =PP3V3R1V5_S0_PCH_VCCSUSHDA
VCCSUSHDA 17 70

Y35
10mA Max, 1mA Idle
NC DCPSUS2

VCCSUS3_3 K8 =PP3V3_SUS_PCH_VCCSUS_RTC 17 70

VCCSUS3_3: 261mA Max, 6mA Idle =PPVRTC_G3_PCH 11 12 70

=PP1V5_S0_PCH_VCCVRM_CLK AF34 VCCVRM
17
A6
VCCRTC

RTC
VCCVRM: 183mA Max, 68mA Idle
AP45 6uA Max (3.0V, room temperature)
17 PP1V05_S0_PCH_VCC_CLK_F VCC P14 C1533 1
C1532 1 1
C1531
??mA Max, ??mA Idle DCPRTC P16
BYPASS=U1100.P14:6.35mm
0.1UF 0.1UF 1UF
Y32
PPVOUT_S0_PCH_DCPRTC
70 17 =PP1V05_S0_PCH_VCCCLK_SSC VCCCLK MIN_LINE_WIDTH=0.2 mm
20%
10V
20%
10V
10%
6.3V
MIN_NECK_WIDTH=0.2 mm CERM 2 CERM 2 2 CERM
VCCCLK: 306mA Max, 89mA Idle VOLTAGE=1.05V 1
=PP3V3_S0_PCH_VCCCLK3_3 M29 C1590 402 402 402
70 17
0.1UF BYPASS=U1100.A6:6.35mm
AJ12 =PP1V05_S0_PCH_V_PROC_IO 10%
VCCCLK3_3: 55mA Max, 11mA Idle

CPU
L29 14 17 70 10V BYPASS=U1100.A6:6.35mm
V_PROC_IO AJ14 2 X5R-CERM BYPASS=U1100.A6:6.35mm
4mA Max, 2mA Idle 0201
L26

M26 VCCCLK3_3
SPI
CLK/MISC

VCCSPI AD12 =PP3V3_SUS_PCH_VCC_SPI 17 70

U32

V32
22mA Max, 1mA Idle

NOTE: Pin name is VCC but really is 3.3V

=PP1V05_S0_PCH_VCCCLK_CLK135 AD34 P18 =PP3V3_S0_PCH_VCC_FUSE
A 70 17

VCCCLK: 306mA Max, 89mA Idle VCC P20 ??mA Max, ??mA Idle
17 70

SYNC_MASTER=J16_KENNY SYNC_DATE=01/21/2013 A
AA30 PAGE TITLE
AA32 L17 =PP1V05_S0M_PCH_VCCASW 15 17 70 PCH Power
VCCASW VCCASW: 670mA Max, 34mA Idle DRAWING NUMBER SIZE
70 17 =PP1V05_S0_PCH_VCCCLK_CLK100 AD35 R18 =PP1V05_S0M_PCH_VCCASW 15 17 70
Apple Inc. 051-0164 D
AG30 VCCCLK VCCASW: 670mA Max, 34mA Idle REVISION
70 17 =PP1V05_S0_PCH_VCCCLK_SSC100 R
AG32
12.4.0
VCCCLK: 306mA Max, 89mA Idle
AW40 =PP1V5_S0_PCH_VCCVRM_THRM
NOTICE OF PROPRIETARY PROPERTY: BRANCH
VCCVRM
THERMAL

17
AD36
THE INFORMATION CONTAINED HEREIN IS THE
VCCVRM: 183mA Max, 68mA Idle PROPRIETARY PROPERTY OF APPLE INC.
AE30 AK30 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
=PP3V3_S0_PCH_VCC3_3_THRM 17 70
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
AE32 VCC3_3 AK32
15 OF 123
VCC3_3: 133mA Max, 3mA Idle II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
Current data from LPT EDS (doc #486708, Rev 1.0).
IV ALL RIGHTS RESERVED 15 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
AL34 U1100 K39

AL38 LYNXPOINT L2

AL8 MOBILE L44

FCBGA
AM14 M17
(10 OF 11)
AM24 M22
VSS
AM26 N12
AM28 N35

AM30 N39
AM32 N6

AM16 P22

D
AN36

AN40
P24
P26
D
AN42 P28

AN8 P30
AP13 P32

AP24 R12

AP31 R14

AP43 R16

AR2 R2

AK16 R34

AT10 R38

AT15 R44
VSS
AT17 R8
VSS
AT20 T43

AT26 U10
AT29 U16

AT36 U28

AT38 U34
D42 U38

AV13 U42

AV22 U6

AV24 V14

AV31 V16

AV33 V26

BB25 V43

AV40 W2

AV6 W44

C AW2

F43
Y14

Y16
C
AY10 Y24

AY15 Y28
AY20 Y34

AY26 Y36

AY29 Y40

AY7 Y8

B11

B15

OMIT_TABLE
AA16 U1100 B19

AA20 LYNXPOINT B23

AA22 MOBILE B27
FCBGA
AA28 B31
(11 OF 11)
AA4 B35
VSS
AB12 B39

AB34 B7

AB38 BA40

AB8 BD11

AC2 BD15

AC44 BD19

AD14 AY36

AD16 AT43

B AD18

AD30
BD31

BD35
B
AD32 BD39
AD40 BD7

AD6 D25

AD8 AV7

AE16 F15

AE28 F20

AF38 F29

AF8 VSS VSS F33

AG16 BC16
AG2 D4

AG26 G2

AG28 G38

AG44 G44

AJ16 G8

AJ18 H10

AJ20 H13

AJ22 H17

AJ24 H22
AJ34 H24

AJ38 H26

AJ6 H31

AJ8 H36

AK14 H40
AK24 H7

A AK43

AK45
K10

K15 SYNC_MASTER=J16_KENNY SYNC_DATE=01/21/2013 A

PAGE TITLE
AL12 K20

AL2 K29 PCH Grounds

BC22 K33 DRAWING NUMBER SIZE
BB42 BC28
Apple Inc. 051-0164 D
REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 16 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 16 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH VCCCLK3_3 BYPASS PCH VCCASW BYPASS
PCH VCCDSW3_3 BYPASS (PCH 3.3V CLK PWR) (PCH 1.05V ME CORE PWR)
(PCH 3.3V DSW PWR) 70 15 =PP3V3_S0_PCH_VCCCLK3_3 70 15 =PP1V05_S0M_PCH_VCCASW
70 15 =PP3V3_S5_PCH_VCCDSW 670mA Max, 34mA Idle

1 C1700 1 C1720 1 C1721 1 C1722 1 C1723 C1750 1 1 C1751 1 C1752

0.1UF 1UF 1UF 1UF 1UF 20UF 1.0UF 1.0UF
10% 20% 20% 20% 20% 20% 20% 20%
4V
2 10V
X5R-CERM 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R X5R-CERM 2 2 6.3V
X5R
6.3V
2 X5R
0201 0201 0201 0201 0201 0402 0201-1 0201-1

BYPASS=U1100.A16:6.35mm BYPASS=U1100.L26:6.35mm PLACE_NEAR=U1100.V20:2.54mm

BYPASS=U1100.L29:6.35mm PLACE_NEAR=U1100.V20:2.54mm

D BYPASS=U1100.M29:6.35mm
BYPASS=U1100.U32:6.35mm
PLACE_NEAR=U1100.V20:2.54mm

Not documented in EDS!

D
PCH VCCSPI BYPASS PCH VCC3_3 BYPASS PCH VCC BYPASS
(PCH 3.3V SPI PWR) (PCH 3.3V HVCMOS PWR) (PCH 1.05V CORE PWR)
70 15 =PP3V3_SUS_PCH_VCC_SPI 70 15 =PP3V3_S0_PCH_VCC3_3_HVCMOS 70 15 =PP1V05_S0_PCH_VCC

1 C1702 1 C1726
1.0UF 0.1UF C1755 1 1 C1756 1 C1757 1 C1758
20% 10%
2 6.3V 2 10V 10UF 1.0UF 1.0UF 1.0UF
X5R X5R-CERM 20% 20% 20% 20%
0201-1 0201 10V 6.3V 6.3V 6.3V
X5R-CERM 2 2 X5R 2 X5R 2 X5R
BYPASS=U1100.AD12:6.35mm BYPASS=U1100.R30:6.35mm
0402-1 0201-1 0201-1 0201-1

BYPASS=U1100.AG18:12.7mm
PCH VCCSUS3_3 BYPASS PCH VCC3_3 BYPASS BYPASS=U1100.AA24:6.35mm
BYPASS=U1100.AD20:6.35mm
(PCH 3.3V SUSPEND PWR) (PCH 3.3V GPIO/LPC PWR) BYPASS=U1100.AE18:6.35mm

70 15 =PP3V3_SUS_PCH_VCCSUS_GPIO 70 15 =PP3V3_S0_PCH_VCC3_3_GPIO PCH VCCIO BYPASS

(PCH 1.05V PCIe/DMI/SATA/USB3 PWR)
1 C1704 1 C1728 70 15 =PP1V05_S0_PCH_VCCIO
0.1UF 0.01UF
10% 10%
2 10V
X5R-CERM 2 10V
X7R-CERM
0201 0201 1 1 1 1 1
C1760 C1761 C1762 C1763 C1764
BYPASS=U1100.R20:6.35mm BYPASS=U1100.AE14:6.35mm 10UF 1.0UF 1.0UF 1.0UF 1.0UF
20% 20% 20% 20% 20%
10V 6.3V 6.3V 6.3V 6.3V
X5R-CERM 2 2 X5R 2 X5R 2 X5R 2 X5R
PCH VCCSUS3_3 BYPASS PCH VCC3_3 BYPASS 0402-1 0201-1 0201-1 0201-1 0201-1
(PCH 3.3V SUSPEND USB PWR) (PCH 3.3V USB2 PWR)
BYPASS=U1100.AK18:12.7mm
70 15 =PP3V3_SUS_PCH_VCCSUS_USB 70 15 =PP3V3_S0_PCH_VCC3_3_USB BYPASS=U1100.AK18:6.35mm
BYPASS=U1100.AK22:6.35mm
BYPASS=U1100.AK20:6.35mm
1 1 BYPASS=U1100.AM18:6.35mm PCH VCCCLK BYPASS
C1706 C1730 PCH VCCUSBPLL BYPASS
(PCH 1.05V SSC100 PWR)
0.1UF 0.1UF (PCH 1.05V USB2 PLL PWR)
10% 10% =PP1V05_S0_PCH_VCCCLK_SSC100
10V 10V 70 15

C 2 X5R-CERM
0201
2 X5R-CERM
0201
70 15 =PP1V05_S0_PCH_VCCUSBPLL
C
BYPASS=U1100.R26:6.35mm BYPASS=U1100.L24:6.35mm
1 C1770 1 C1776 1 C1777
0.1UF
PCH VCCSUS3_3 BYPASS PCH VCC3_3 BYPASS 10% 1.0UF 1.0UF
6.3V 20% 20%
2 CERM-X5R 6.3V 6.3V
(PCH 3.3V SUSPEND RTC PWR) (PCH 3.3V THERMAL PWR) 0201 2 X5R 2 X5R
=PP3V3_SUS_PCH_VCCSUS_RTC =PP3V3_S0_PCH_VCC3_3_THRM BYPASS=U1100.U35:6.35mm 0201-1 0201-1
70 15 70 15

1 C1708 1 C1732 PCH VCCIO BYPASS BYPASS=U1100.AE30:6.35mm

1.0UF 0.1UF BYPASS=U1100.AG30:6.35mm
20% 10% (PCH 1.05V FDI PWR)
6.3V 10V =PP1V05_S0_PCH_VCCIO_FDI
2 X5R 2 X5R-CERM 70 15 PCH VCCCLK BYPASS
0201-1 0201
(PCH 1.05V DIFFCLK PWR)
BYPASS=U1100.AK30:6.35mm
1 C1772 70 15 =PP1V05_S0_PCH_VCCCLK_CLK100
BYPASS=U1100.K8:6.35mm 1.0UF
PCH VCC BYPASS 20%
6.3V 1
(PCH 3.3V FUSE PWR)
2 X5R C1778
0201-1 1.0UF
=PP3V3_S0_PCH_VCC_FUSE 20%
70 15 6.3V
BYPASS=U1100.AN34:6.35mm 2 X5R
0201-1
1 C1734 PCH VCCIO BYPASS
BYPASS=U1100.AD35:6.35mm
1.0UF (PCH 1.05V USB2 PWR)
20%
6.3V =PP1V05_S0_PCH_VCCIO_USB2
2 X5R 70 15 PCH VCCCLK BYPASS
0201-1
(PCH 1.05V DIFFCLK135 PWR)
BYPASS=U1100.P18:6.35mm
1 C1774 70 15 =PP1V05_S0_PCH_VCCCLK_CLK135
0.1UF
10%
6.3V 1
2 CERM-X5R
C1780
0201 1.0UF
BYPASS=U1100.U30:6.35mm 20%
2 6.3V
X5R
0201-1

B PCH VCCSUSHDA BYPASS

(PCH 3.3V/1.5V HDA PWR)
PCH VCCVRM BYPASS
(PCH 1.5V VCCVRM PWR)
PCH V_PROC_IO BYPASS
(PCH 1.05V CPU I/F PWR)
BYPASS=U1100.AD34:6.35mm
B
70 15 =PP3V3R1V5_S0_PCH_VCCSUSHDA 70 =PP1V5_S0_PCH_VCCVRM 70 15 14 =PP1V05_S0_PCH_V_PROC_IO PCH VCCCLK BYPASS
183mA Max, 68mA Idle (PCH 1.05V SSC PWR)
1 C1710 11 =PP1V5_S0_PCH_VCCVRM_BIAS 70 15 =PP1V05_S0_PCH_VCCCLK_SSC
0.1UF 15 =PP1V5_S0_PCH_VCCVRM_FDI C1785 1 1 C1786 1 C1787
10%
2
10V
15 =PP1V5_S0_PCH_VCCVRM_USB3 1.0UF 0.1UF 0.1UF 1 C1782
X5R-CERM 20% 10% 10%
0201
15 =PP1V5_S0_PCH_VCCVRM_PCIE 6.3V
2 2
6.3V
2
6.3V 1.0UF
X5R CERM-X5R CERM-X5R 20%
0201-1 0201 0201
BYPASS=U1100.A26:6.35mm 15 =PP1V5_S0_PCH_VCCVRM_SATA 2 6.3V
X5R
BYPASS=U1100.AJ12:6.35mm 0201-1
15 =PP1V5_S0_PCH_VCCVRM_CLK BYPASS=U1100.AJ12:12.7mm
BYPASS=U1100.AJ12:6.35mm
15 =PP1V5_S0_PCH_VCCVRM_THRM BYPASS=U1100.AA30:6.35mm

1 CRITICAL
C1740 OMIT_TABLE PCH CLK VCC BYPASS
10UF
20%
10V L1790 (PCH 1.05V CLK PLL PWR)
2 X5R-CERM R1790 4.7UH-170MA-0.321OHM
0402-1 70 =PP1V05_S0_PCH_VCC_CLK PP1V05_S0_PCH_VCC_CLK_F 15
1 1 2
MIN_LINE_WIDTH=0.2 MM
??mA Max, ??mA Idle 1 2 PP1V05_S0_PCH_VCC_CLK_R MIN_NECK_WIDTH=0.075 MM
BYPASS=U1100.AF34:12.7mm MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V
5% MIN_NECK_WIDTH=0.2 MM 0603
1/16W VOLTAGE=1.05V
MF-LF NO STUFF
402
C1790 1 1 C1791
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 10UF 1.0UF
20% 20%
10V 2 2 6.3V
113S0022 1 RES,FF,0 OHM,(020OHM MAX),2A,0603 L1790 X5R-CERM X5R
0402-1 0201-1

BYPASS=U1100.AP45:12.7mm
BYPASS=U1100.AP45:6.35mm

A SYNC_MASTER=J16_KENNY SYNC_DATE=01/21/2013 A
PAGE TITLE

PCH DECOUPLING
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Extra BPM Testpoints 61 10 8 6 5 PPVCCIO_S0_CPU CPU Micro2-XDP 70 18 =PP1V05_S0_XDP

CRITICAL NOTE: This is not the standard XDP pinout. XDP

78 6 IN XDP_BPM_L<2> 1
TP XDP_CONN Use with 921-0133 Adapter Flex to 78 18 6 XDP_CPU_TDO R1820 51 2 1

TP-P6
TP1802 =PP1V05_S0_XDP
PLACE_NEAR=J1800.51:5MM 5% 1/20W MF 201
70 18
J1800 support chipset debug.
78 6 IN XDP_BPM_L<3> 1
TP XDP
TP-P6
TP1803 DF40RC-60DP-0.4V
XDP_CPU_TCK R1823 51 2 1
1 M-ST-SM 78 18 6
78 6 IN XDP_BPM_L<4> 1
TP R1830 5% 1/20W MF 201
TP-P6
TP1804 150 62 61 XDP
78 6 IN XDP_BPM_L<5> 1
TP 5%
TP-P6
TP1805 1/16W 18 6 XDP_CPU_TRST_L R1824 51 2 1
MF-LF 5% 1/20W MF 201
78 6 IN XDP_BPM_L<6> 1
TP 402 2
TP-P6
TP1806 2 1

4 3
TDI and TMS are terminated in CPU.
78 6 XDP_BPM_L<7> 1 6 XDP_CPU_PREQ_L OBSFN_A0 OBSFN_C0 CPU_CFG<17> 6 78

D
IN TP
TP-P6
TP1807
6
BI
IN XDP_CPU_PRDY_L OBSFN_A1 6

8
5
7
OBSFN_C1 CPU_CFG<16>
IN
IN 6 78 D
CPU_CFG<0> OBSDATA_A0 10 9 CPU_CFG<8>
78 6 IN OBSDATA_C0 IN 6 78

CPU_CFG<1> 12 11 CPU_CFG<9>
78 6 IN OBSDATA_A1 OBSDATA_C1 IN 6 78
14 13

CPU_CFG<2> 16 15 CPU_CFG<10>
78 6 IN OBSDATA_A2 OBSDATA_C2 IN 6 78

CPU_CFG<3> 18 17 CPU_CFG<11>
78 6 IN OBSDATA_A3 OBSDATA_C3 IN 6 78
20 19

XDP_BPM_L<0> OBSFN_B0 22 21 CPU_CFG<19>

76 6 IN OBSFN_D0 IN 6

76 6 XDP_BPM_L<1> OBSFN_B1 24 23 OBSFN_D1 CPU_CFG<18> 6

IN IN
26 25

78 6 CPU_CFG<4> OBSDATA_B0 28 27 OBSDATA_D0 CPU_CFG<12>

IN IN 6 72 78

CPU_CFG<5> 30 29 CPU_CFG<13>
78 6 IN OBSDATA_B1 OBSDATA_D1 IN 6 72 78
32 31

CPU_CFG<6> 34 33 CPU_CFG<14>
78 6 IN OBSDATA_B2 OBSDATA_D2 IN 6 72 78
XDP 36 35
78 6 IN CPU_CFG<7> OBSDATA_B3 OBSDATA_D3 CPU_CFG<15> IN 6 72 78
76 14 6 IN CPU_PWRGD R1800 1K 1 2
38 37
PLACE_NEAR=U0500.AB35:16.5mm 5% 1/20W MF 201
XDP XDP_CPU_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 NC
44 18 12 OUT PM_PWRBTN_L R1802 0 1 2 XDP_CPU_PWRBTN_L HOOK1 42 41 ITPCLK#/HOOK5 NC NC per Intel DPDG.
5% 1/20W MF 0201
44 43
VCC_OBS_AB VCC_OBS_CD XDP
WF: SB DPDG says HOOK1 is BP_PWRGD_RST#
XDP 8 OUT CPU_PWR_DEBUG HOOK2 46 45 RESET#/HOOK6 XDP_CPURST_L R1805 1K 1 2 CPU_RESET_L IN 6 14 76

69 45 12 OUT PM_PCH_SYS_PWROK R1804 220 1 2 XDP_VR_READY HOOK3 48 47 DBR#/HOOK7 XDP_DBRESET_L OUT 6 18 19

5% 1/20W MF 201
5% 1/20W MF 201
50 49 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
=SMBUS_XDP_SDA 52 51 XDP_CPU_TDO
47 18 BI SDA TDO IN 6 18 78
47 18 IN =SMBUS_XDP_SCL SCL 54 53
TRSTn XDP_CPU_TRST_L OUT 6 18 CPU-PCH JTAG Chain Support
56 55 XDP_CPU_TDI
TCK1 NC TDI OUT 6 78
To link CPU and PCH JTAG pull ICT_JTAG_EN to 5V (must be in S0)
C 78 18 6 OUT XDP_CPU_TCK TCK0 58

60
57

59
TMS
XDP_PRESENT#
XDP_CPU_TMS OUT 6 18 78
TP1845 TP
TP-P6
1 C
XDP SIGNALS XDP 1
XDP XDP XDP XDP Q1840 ICT_JTAG_EN
Q1846

5
OMIT R1831 DMN5L06VK-7 DMN5L06VK-7
PCH SIGNALS (All 18 R’s) C1804 1
C1800 1 1
C1801 1
C1806

G
1K 64 63 SOT-563 SOT-563
0.1UF 0.1UF 0.1UF 0.1UF
42 13 IN USB_EXTA_OC_L R1890 SHORT 1 2 XDP_DA0_USB_EXTA_OC_L 18
5%
1/16W
20%
10V
20%
10V
20%
10V
20%
10V
NONE NONE NONE 402
R1893 MF-LF 2 2 2 2

D
CERM CERM CERM CERM
43 13 IN USB_EXTC_OC_L SHORT 1 2
NONE NONE NONE 402
XDP_DA1_USB_EXTC_OC_L 18 402 2 402 402 998-2516 402 402 78 18 6 XDP_CPU_TMS XDP_CPU_PCH_TMS XDP_PCH_TMS 11 18 78
R1894

3
PLACE_NEAR=J1800.57:5.08mm PLACE_NEAR=J1850.57:6mm

4
13 IN PCH_GPIO41 SHORT 1 2 XDP_DA2_PCH_GPIO41 18
NONE NONE NONE 402
13 IN PCH_GPIO42 R1895 SHORT 1 2 XDP_DA3_PCH_GPIO42 18 TP1840 TP 1

R1880 NONE NONE NONE 402 Q1840 TP-P6 Q1846

2
42 13 USB_EXTB_OC_L SHORT 1 2 XDP_DB0_USB_EXTB_OC_L 18
IN NONE NONE NONE 402 DMN5L06VK-7 DMN5L06VK-7
R1881

G
43 13 IN USB_EXTD_OC_L SHORT 1 2 XDP_DB1_USB_EXTD_OC_L 18 XDP_CPU_PRESENT_L SOT-563 SOT-563
NONE NONE NONE 402
13 IN PCH_GPIO10 R1896 SHORT 1 2 XDP_DB2_PCH_GPIO10 18
NONE NONE NONE 402
R1897

D
37 13 SDCONN_STATE_CHANGE SHORT 1 2 XDP_DB3_SDCONN_STATE_CHANGE_L 18 78 18 6 XDP_CPU_TCK XDP_CPU_PCH_TCK XDP_PCH_TCK 11 18 78
OUT NONE NONE NONE 402
R1872

6
PLACE_NEAR=J1800.58:5.08mm PLACE_NEAR=J1850.58:5.08mm

1
30 29 11 IN DP_AUXIO_EN SHORT 1 2 XDP_DC0_DP_AUXCH_ISOL_L 18
NONE NONE NONE 402
11 IN SATARDRVR_EN R1873 SHORT 1 2 XDP_DC1_SATARDRVR_EN 18 TP1841 TP 1

R1874 NONE NONE NONE 402 Q1842 TP-P6 Q1848

1
14 PCH_GPIO36 SHORT 1 2 XDP_DC2_PCH_GPIO36 18 DMN32D2LFB4 DMN32D2LFB4
IN NONE NONE NONE 402
R1875

G
DFN1006H4-3 DFN1006H4-3
20 14 IN JTAG_ISP_TCK SHORT 1 2 XDP_DC3_JTAG_ISP_TCK 18 SYM_VER_3 SYM_VER_3
NONE NONE NONE 402
14 OUT PCH_GPIO16 R1878 SHORT 1 2 XDP_DD0_PCH_GPIO16 18
NONE NONE NONE 402
R1879

D
PCH_GPIO49 SHORT 1 2 XDP_DD1_PCH_GPIO49 XDP_CPU_TDO XDP_CPU_TDO_PCH_TDI XDP_PCH_TDI
14 OUT
R1882 NONE NONE NONE 402
18
PCH Micro2-XDP =PP3V3_S5_XDP
78 18 6 11 18 78

3
18 70 PLACE_NEAR=J1800.51:5.08mm PLACE_NEAR=J1850.55:5.08mm

2
35 11 OUT ENET_CLKREQ_L SHORT 1 2 XDP_DD2_ENET_CLKREQ_L 18
NONE NONE NONE 402
32 11 OUT AP_CLKREQ_L R1883 SHORT 1 2 XDP_DD3_AP_CLKREQ_L 18
R1886 NONE NONE NONE 402 CRITICAL
67 14 OUT HDD_PWR_EN SHORT 1 2 XDP_FC0_HDD_PWR_EN 18

14 3 GPU_GOOD R1887 SHORT 1 2

NONE NONE NONE 402
XDP_FC1_GPU_GOOD 18
XDP_CONN R1842 1 1
R1841 1
R1840 R1845 1
OUT NONE NONE NONE 402
J1850 1M 1M 1M 1K
5% 5% 5% 5%
DF40RC-60DP-0.4V NOTE: This is not the standard XDP pinout. 1/20W 1/20W 1/20W 1/20W
M-ST-SM MF MF MF MF
Use with 921-0133 Adapter Flex to 201
2 2
201
2
201 201
2
62 61 support chipset debug.

B 2 1
NOSTUFF
B
OBSFN_A0 4 3
OBSFN_C0 XDP_FC0_HDD_PWR_EN 18
R1892
NC 0
6 5 XDP_FC1_GPU_GOOD =PP3V3_S5_XDP 1 2 PP3V3_S5_XDP_R
OBSFN_A1 NC OBSFN_C1 18 70 18
8 7 5% VOLTAGE=3.3V
1/16W MIN_LINE_WIDTH=0.2MM
18 XDP_DA0_USB_EXTA_OC_L OBSDATA_A0 10 9
OBSDATA_C0 XDP_DC0_DP_AUXCH_ISOL_L 18 MF-LF MIN_NECK_WIDTH=0.15MM
402 MAX_NECK_LENGTH=3MM
XDP_DA1_USB_EXTC_OC_L OBSDATA_A1 12 11
OBSDATA_C1 XDP_DC1_SATARDRVR_EN
18 18
PCH/XDP Signal Isolation Notes: 14 13

’Output’ non-XDP signals require pulls. 18 XDP_DA2_PCH_GPIO41 OBSDATA_A2 16 15

OBSDATA_C2 XDP_DC2_PCH_GPIO36 18
XDP XDP XDP
’Output’ PCH/XDP signals require pulls. XDP_DA3_PCH_GPIO42 OBSDATA_A3 18 17
OBSDATA_C3 XDP_DC3_JTAG_ISP_TCK 1 1 1
18 18
R1860 R1861 R1862
20 19 210 210 210
22 21 1% 1% 1%
R187x and R189x should be placed where OBSFN_B0 NC NC OBSFN_D0 1/20W 1/20W 1/20W
24 23
MF MF MF
signal path needs to split between route OBSFN_B1 NC NC OBSFN_D1 2 201 2 201 2 201
from PCH to J1850 and path to non-XDP 26 25
78 18 11 XDP_PCH_TDO
J1850.51:2.54mm U1100.W39:4mm U1100.W40:3.5mm
signal destination (to minimize stub). 18 XDP_DB0_USB_EXTB_OC_L OBSDATA_B0 28 27 OBSDATA_D0 XDP_DD0_PCH_GPIO16 18 78 18 11 XDP_PCH_TDI
XDP_DB1_USB_EXTD_OC_L 30 29 XDP_DD1_PCH_GPIO49 XDP_PCH_TMS
18 OBSDATA_B1 OBSDATA_D1 18 78 18 11
32 31
78 18 11 XDP_PCH_TCK
XDP_DB2_PCH_GPIO10 34 33 XDP_DD2_ENET_CLKREQ_L
18 OBSDATA_B2 OBSDATA_D2 18

XDP_DB3_SDCONN_STATE_CHANGE_L 36 35 XDP_DD3_AP_CLKREQ_L
18 OBSDATA_B3 OBSDATA_D3 18 XDP XDP
38 37
XDP XDP
XDP 1 J1850.51:5mm
1 U1100.W40:20MM 1
PLACE_NEAR=J1850.40:2.54mm R1867 1 U1100.W39:21MM R1869 R1866
69 12 IN PM_RSMRST_PCH_L R1884 1K 1 2 XDP_PCH_S5_PWRGD PWRGD/HOOK0 40 39
NC ITPCLK/HOOK4 R1868
5% 1/20W MF 201
42 41 XDP 100 100 100 51
XDP_PCH_PWRBTN_L HOOK1 NC ITPCLK#/HOOK5 5% 5% 5%
XDP 44 43
R1870 1K 1 2 PM_PCH_PWROK IN 12 20 39 69 1/20W
5%
1/20W 1/20W 1/20W
VCC_OBS_AB VCC_OBS_CD MF MF MF
44 18 12 OUT PM_PWRBTN_L R1885 0 1 2
46 45
5% 1/20W MF 201
2 201
MF
201 2 201 2 201
PLACE_NEAR=U5000.J3:2.54mm 5% 1/20W MF 0201 HOOK2 RESET#/HOOK6 XDP_PM_PCH_PWROK 2
NC
HOOK3 48 47 DBR#/HOOK7 XDP_DBRESET_L 6 18 19
NC OUT
50 49 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
A 47 18

47 18
BI =SMBUS_XDP_SDA
=SMBUS_XDP_SCL
SDA
SCL
52

54
51

53
TDO
TRSTn
XDP_PCH_TDO
TP_XDP_PCH_TRST_L
IN 11 18 78
SYNC_MASTER=J16_KENNY SYNC_DATE=03/18/2013 A
IN PAGE TITLE
TCK1 56 55 TDI XDP_PCH_TDI
78 18 11 XDP_PCH_TCK TCK0
NC
58 57
TMS XDP_PCH_TMS
OUT 11 18 78

11 18 78
CPU & PCH XDP
OUT OUT
60 59
DRAWING NUMBER SIZE
XDP_PRESENT#
XDP XDP Apple Inc. 051-0164 D
REVISION
C1880 1 1
C1881 R
0.1UF
64 63
0.1UF 12.4.0
20% 20% NOTICE OF PROPRIETARY PROPERTY: BRANCH
10V 10V
CERM 2 2 CERM
402 998-2516 402 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 18 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 18 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PCH Reset Button

System 25MHz Clock Generator 70 13 =PP3V3_S0_PCH

1
R1995
VDD must be powered if any VDDIO is. 4.7K
5%
ENET > S0 > TBT, so ENET is used here. XDP 1/16W
MF-LF
GreenClk 25MHz Power =PP3V3_ENET_SYSCLK
70
R1996 2
402

0
18 6 IN XDP_DBRESET_L 1 2 PM_SYSRST_L OUT 12 44

D Ethernet XTAL Power

SB XTAL Power
70

70 11
=PPVDDIO_ENET_CLK
=PP1V5_S0_PCH_CLK
5%
1/16W
MF-LF 1
OMIT
R1997
D
402
TBT XTAL Power 70 =PPVDDIO_TBT_CLK 0
5%
1/16W
MF-LF
402
2
C1924 1
C1922 1
C1920 1 1
C1902 SILK_PART=SYS RESET

VDD 2

VDDIO_A 6
VDDIO_B 3
VDDIO_C 7
0.1UF 0.1UF 0.1UF 1UF
20% 20% 20% 10%
10V 10V 10V 6.3V
CERM 2 CERM 2 CERM 2 2 CERM
402 402 402 402

U1900
C1905 SLG3NB146V
12PF R1905 TDFN
0 CRITICAL
1 2 79 SYSCLK_CLK25M_X2 1 2 79 SYSCLK_CLK25M_X2_R 10 XOUT

5%
5% NOSTUFF 1 XIN 25MHZ_A 5 SYSCLK_CLK25M_SB OUT 11 79
1/16W
50V 1
25MHZ_B 4 SYSCLK_CLK25M_ENET_R
1

MF-LF
C0G-CERM CRITICAL 402 R1906 19 79
0402 NC 1M 25MHZ_C 8 SYSCLK_CLK25M_TBT
2 4

NC Y1905 5%
OUT 26 79

1/16W
25.000MHZ-20PPM-12PF-85C
C1906
3

MF-LF

9 GND
3.2X2.5MM-SM 402
12PF 2 THRM
PAD
1 2 79 SYSCLK_CLK25M_X1

11
5% NOTE: 30 PPM crystal required
50V
C0G-CERM
0402

RTC Power Sources

C D1900
C
BAT54DW-X-G
SOT-363
PP3V3_G3_RTC 70
6 MIN_LINE_WIDTH=0.6MM
70 =PP3V3_G3H_RTC_D 1 MIN_NECK_WIDTH=0.2MM
Coin-Cell Holder R1902 VOLTAGE=3.3V
1K
PPVBATT_G3_RTC 2 1 PPVBATT_G3_RTC_R 4 3
MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm 5% MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V 1/16W VOLTAGE=3.3V
MF-LF
NC
5 NC NC 2 NC
402
1
J1900
BB10201-C1403-7H
2 SM

511S0054 TP1900 TP1901

1.97X2.02MM-NSP 1.97X2.02MM-NSP
SMT-PAD SMT-PAD
1 1
OMIT OMIT

Place TP1901-TP1903 on bottom side

TP1902 TP1903
1.4-SQ-NSP 1.4-SQ-NSP
SM-PAD SM-PAD
45 11 RTC_RESET_L 1 1
OMIT OMIT

B PCH ME Disable Strap B

PCH RTC Crystal PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
PLACE_NEAR=Y1910.4:2MM
SMC controls strap enable to allow in-field control of strap setting.
C1910
R1910 12PF
0 1 2
79 11 IN PCH_CLK32K_RTCX2 1 2 79 PCH_CLK32K_RTCX2_R
5%
1/16W 5%
R19111
50V =PP3V3_S5_PCH
MF-LF CRITICAL 70 20
4

402 C0G-CERM
10M Y1910 0402
5% 32.768K-12.5PF
1/16W SM-HF 2
MF-LF C1911
1

402
2 12PF
SPI_DESCRIPTOR_OVERRIDE_L S SOT23-3-HF
PCH_CLK32K_RTCX1 1 2 44 IN
79 11 OUT 1
G
NTR1P02L
5%
Q1920
50V
C0G-CERM
0402 D
PLACE_NEAR=Y1910.1:2MM 3

PLACE_NEAR=R1113.2:15MM

SPI_DESCRIPTOR_OVERRIDE_R 330 1
R1921
Clock series termination 5%
2 HDA_SDOUT_R
1/16W MF-LF 402
OUT 11 79

R1955
PLACE_NEAR=U1100:10MM
33
79 11 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC OUT 44 79

A 5%
1/16W
MF-LF
402 R1956 SYNC_MASTER=J16_KENNY SYNC_DATE=01/21/2013 A
33 PAGE TITLE
LPC_CLK33M_LPCPLUS_R PLACE_NEAR=U1100:10MM 1 2 LPC_CLK33M_LPCPLUS
79 11 IN
5%
OUT 46 79
Chipset Support
1/16W DRAWING NUMBER SIZE
MF-LF
R1959 402 051-0164 D
79 11 PCH_CLK33M_PCIOUT PLACE_NEAR=U1100:13MM 1
33
2 PCH_CLK33M_PCIIN 11 79
Apple Inc. REVISION
IN OUT
R
5%
1/16W
12.4.0
R1958 MF-LF NOTICE OF PROPRIETARY PROPERTY: BRANCH
33 402
79 19 SYSCLK_CLK25M_ENET_R 1 2 SYSCLK_CLK25M_ENET OUT 35 79 THE INFORMATION CONTAINED HEREIN IS THE
PLACE_NEAR=U1900.4:10MM
PROPRIETARY PROPERTY OF APPLE INC.
5% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1/16W
MF-LF
402
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
19 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 19 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Platform Reset Connections

R2081
33
12 IN PLT_RESET_L 1 2 DEBUG_RESET_L OUT 46
MAKE_BASE=TRUE
5%
1/16W
Unbuffered MF-LF
402

R2055
33

D
1

5%
2 SMC_LRESET_L
MAKE_BASE=TRUE
OUT 44 81
D
1/16W
MF-LF
402

R2094
33
1 2 PCA9557D_RESET_L 21 22
OUT
5%
1/16W
MF-LF
402
R2095
33
1 2 SSD_RESET_L 33
OUT
5%
1/16W
MF-LF
Buffered 402

70 =PP3V3_S0_RSTBUF

CRITICAL
MC74VHC1G08 EXT_GPU:YES
5 SOT23-5-HF
1 R2090
4
33
PLT_RST_BUF_L 1 2 TP_GPU_RESET_L
2
U2080 OUT 72

5%
1/16W
1 MF-LF
3 R2080 402
C2080 1 100K
0.1UF 5%
1/16W
R2091
20% MF-LF 33
10V
C CERM
402
2 2 402
1
5%
1/16W
2 TBT_PLT_RST_L
MAKE_BASE=TRUE
=TBT_RESET_L OUT 28
C
MF-LF
402

R2088
33
1 2 AP_RESET_L OUT 32

5%
1/16W
MF-LF
402

R2092
33
GPIO Glitch Prevention 1

5%
1/16W
2 ENET_SD_RESET_L OUT 37

MF-LF
402
70 20 19 =PP3V3_S5_PCH
R2093
33
C2040 1 1 2 BT_RESET_MASK_L OUT 32
0.1UF 5%
10% 1/16W
6.3V MF-LF
CERM-X5R 2
402
0201
CRITICAL
5 TC7SZ08FEAPE
12 AUD_IPHS_SWITCH_EN_PCH 2 SOT665
IN A
4 AUD_IPHS_SWITCH_EN
U2040Y OUT 56
JTAG GPIO Isolation due to glitch in and out of sleep
69 39 20 18 12 PM_PCH_PWROK 1
B
NOTE: TCK from PCH is Push-Pull CMOS
3
NOTE: TMS/TDI from PCH is Open Drain
=PP3V3_TBT_PCH_GPIO 70
NOTE: TDO from CR is Push-Pull CMOS

B CRITICAL
Q2060 1
R2063
B
DMN5L06VK-7 10K

2
5%

G
SOT-563 1/20W
MF
70 20 19 =PP3V3_S5_PCH 2 201

S
14 IN JTAG_TBT_TMS_PCH JTAG_TBT_TMS OUT 26

1
CRITICAL 8
1
C2050
0.1UF CRITICAL
VCC 20%
10V 1
U2050 2 CERM Q2060 R2061
SOT833 402
08 DMN5L06VK-7 10K

5
5%

74LVC2G08GT
ENET_LOW_PWR_PCH 1 7 ENET_LOW_PWR

G
12 35 37 1/20W
IN A1 Y1 OUT SOT-563
MF
69 39 20 18 12 PM_PCH_PWROK 2
2 201
IN B1
13 TBT_PWR_EN_PCH 5 3 TBT_PWR_EN 20 26
A2 Y2

S
IN OUT JTAG_ISP_TDI JTAG_TBT_TDI
14 IN OUT 26
LPC_PWRDWN_L 6

3
46 44 12
B2

4
IN

GND
4
CRITICAL 1
Q2062 R2062
DMN32D2LFB4 10K

1
DFN1006H4-3 5%

G
1/20W
SYM_VER_3 MF
2 201

S
70 20 19 =PP3V3_S5_PCH 14 OUT JTAG_ISP_TDO JTAG_TBT_TDO IN 26

2
CRITICAL 8
1
C2013
0.1UF
A VCC
U2000 2
10%
16V
X5R-CERM SYNC_MASTER=J16_KENNY SYNC_DATE=01/21/2013 A
TBT_PWR_EN goes high for JTAG Programming
SOT833 0201 PAGE TITLE
08
Project Chipset Support
74LVC2G08GT

26 20 TBT_PWR_EN 1 7 JTAG_TBT_TCK 26
R2060 IN A1 Y1 OUT
18 14 JTAG_ISP_TCK 2 R2074 DRAWING NUMBER SIZE
10K
IN B1 1K
2 1 TBT_CIO_PLUG_EVENT 20 26
26 20 IN TBT_CIO_PLUG_EVENT 5
A2 Y2
3 TBT_CIO_PLUG_EVENT_BUF 2 1 TBT_CIO_PLUG_EVENT_ISOL OUT 14
Apple Inc. 051-0164 D
5% 1/20W MF 201 6
R2074 for current 5% REVISION
B2 1/20W R

GND limit if PCH glitches MF

201
12.4.0
4
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
20 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 20 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. D
D WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

MEMVTT_EN = PLT_RESET_L * PM_SLP_S3_L

MEM S0 "PGOOD" FOR CPU
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
PM_MEM_PWRGD MUST ASSERT MIN 100 NS AFTER MEM_VDDQ RAMPS 80%
70 =PP5V_S4_MEMRESET THIS IS GUARANTEED BY THE 2 V/MS RAMP RATE OF THE FET
70 =PP3V3_S4_PM

R21181 R21151 CRITICAL

10K 100K
5% 5%
1/16W
MF-LF
1/16W
MF-LF
5 U2120
402 2 402 2 74LVC1G07
SC70
71 IN =PM_PGOOD_MEM_S0 2 4 PM_MEM_PWRGD OUT 6 12
22 MEMRESET_ISOL_LS5V_L
NC
=PPVDDQ_S3_MEMRESET 70
CRITICAL C2121 1 1 3

Q2115 D 3 0.01UF NC
20%
SSM6N15AFE 16V
X7R-CERM 2
SOT563
R21161 0402
1K
5%
1 C2116
1/16W 0.1UF
5 G S 4 MF-LF 10%
CRITICAL 402 2 2 16V
X7R-CERM
C Q2116
0402
C
ISOLATE_MEM_5V

1
G
VESM

CRITICAL

D
6 IN =MEM_RESET_L CPU_MEM_RESET_L MEM_RESET_L OUT 23 24 75
MAKE_BASE=TRUE

3
Q2115 D 6

2
SSM6N15AFE SSM3K15AMFVAPE
SOT563

2 G S 1
ISOLATE_CPU_MEM_L
14 IN
MEMVTT Clamp
Ensures CKE signals are held low in S3

70 =PPDDRVTT_S0_CLAMP

R21501
10 75mA max load @ 0.75V
5%
70 21 =PP3V3_S4_MEMRESET 1/10W 60mW max power
MF-LF
603 2
1 C2110 VTTCLAMP_L
0.01UF MIN_NECK_WIDTH=0.25mm
20% CRITICAL MIN_LINE_WIDTH=0.25mm
2 16V
X7R-CERM 70 21 =PP3V3_S4_MEMRESET
Q2150 D 6
B 0402

R21511 SSM6N15AFE B
SOT563
6 74LVC1G08
100K
SOT891 5%
69 68 45 44 36 12 IN PM_SLP_S3_L 2 1/16W
MF-LF
U2110 4 MEMVTT_EN OUT 21 68 402 2 2 G S 1
22 20 IN PCA9557D_RESET_L 1 08
NC VTTCLAMP_EN
5 3
NOSTUFF CRITICAL
NOSTUFF
R2112 NC Q2150 D 3
C2151 1
0 SSM6N15AFE
69 44 3 IN ALL_SYS_PWRGD 2 1 SOT563 0.001UF
20%
5% 50V
1/16W CERM 2
MF-LF 0402
402 5 G S 4

68 21 IN MEMVTT_EN

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN

S0 0 1 1 1 1 CPU_MEM_RESET_L 1
1 0 1 1 1 1 1
to 2 0 0 1 1 1 0
3 0 0 0 X 1 0
A S3 4 0 0 1 X 1 0
SYNC_MASTER=J16_NICK SYNC_DATE=12/11/2012 A
PAGE TITLE

to 5
6
0
0
1
1
1
1
0 (*)
1
1
1
1
1
CPU Memory S3 Support
DRAWING NUMBER SIZE
S0 7 1 1 1 1 CPU_MEM_RESET_L 1
Apple Inc. 051-0164 D
REVISION
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO. R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 21 OF 123
II NOT TO REPRODUCE OR COPY IT
must de-assert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 21 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes CPU-Based Margining VRef Dividers =PPDDR_S3_MEMVREF 70

CPU_MEM_VREFDQ_A_ISOL
Power aliases required by this page:
FETs for CPU isolation during S3 DDRVREF_DAC CRITICAL Always used, regardless
- =PP3V3_S3_VREFMRGN 1
R2225 EN RC’s to avoid drain glitches DDRVREF_DAC of margining option. R2221
- =PPDDR_S3_MEMVREF CRITICAL
100K Q2225 1K
Q2220 VREFMRGN_DQ_A_EN_RC

2
1 2 1%
DMN5L06VK-7

2
Signal aliases required by this page: MEMRESET_ISOL_LS5V_L

G
21 IN PLACE_NEAR=C2220.1:2mm 1/16W
DMN5L06VK-7 DDRVREF_DAC 5% DDRVREF_DAC SOT-563

G
MF-LF
- =I2C_VREFDACS_SCL SOT-563 1/16W
1
C2225 1 R2223 2
402

- =I2C_VREFDACS_SDA R2201 MF-LF

402 2
PLACE_NEAR=R2223.2:1.5MM

D
100K 0.1UF 1 2 PPVREF_S3_MEM_VREFDQ_A 23

D
CPU_DIMMA_VREFDQ 20%
- =I2C_PCA9557D_SCL

6
7 5% MIN_LINE_WIDTH=0.3 mm

1
IN 10V 5%

6
1/20W 2 PLACE_NEAR=R2221.2:1mm MIN_NECK_WIDTH=0.2 mm

1
CERM
- =I2C_PCA9557D_SDA MF 402
1/20W
1
201
2
Q2225 pin 6: MF
R2222
201
BOM options provided by this page: PLACE_NEAR=Q2220.6:5mm 1K

D - DDRVREF_DAC - Stuffs DAC margining circuit. 1

PLACE_NEAR=Q2220.6:2mm

C2220
1%
1/16W
MF-LF
D
CRITICAL 0.022UF 402
2
Q2260 CPU_MEM_VREFDQ_B_ISOL 10%
6.3V

2
2
DMN5L06VK-7 DDRVREF_DAC CRITICAL X5R-CERM

G
SOT-563 0201 R2220
24.9 1
R2245 DDRVREF_DAC R2241
MEM_VREFDQ_A_RC 1 2
100K Q2265 1K

D
CPU_DIMMB_VREFDQ VREFMRGN_DQ_B_EN_RC

2
7 1 2 1% 1%
IN DMN5L06VK-7 1/20W

G
PLACE_NEAR=C2240.1:2mm 1/16W

1
DDRVREF_DAC 5% DDRVREF_DAC SOT-563 MF MF-LF
1/16W 201
1
C2245 1 R2243 2
402

NOTE: CPU DAC output step sizes: R2202 MF-LF

402 2
PLACE_NEAR=R2243.2:1mm

D
100K 0.1UF 1 2 PPVREF_S3_MEM_VREFDQ_B 24
20%
DDR3 (1.5V) 7.70mV per step

6
5% MIN_LINE_WIDTH=0.3 mm

1
10V 5%
1/20W CERM 2 PLACE_NEAR=R2241.2:1mm MIN_NECK_WIDTH=0.2 mm
DDR3L (1.35V) 6.99mV per step CRITICAL MF 402
1/20W
1
201 Q2265 pin 6: MF
R2242
Q2220 2 201

5
DMN5L06VK-7 PLACE_NEAR=Q2260.6:5mm 1K

G
PLACE_NEAR=Q2260.6:4MM 1%
SOT-563 1/16W
1
C2240 MF-LF
402
0.022UF 2

D
7 IN CPU_DIMM_VREFCA CPU_MEM_VREFCA_A_ISOL 10%
6.3V

3
2

4
X5R-CERM
DDRVREF_DAC CRITICAL 0201 R2240
NOTE: CPU has single output for 1
R2265 DDRVREF_DAC 24.9 R2261
VREFCA. Split into two MEM_VREFDQ_B_RC 1 2
100K
VREFMRGN_CA_A_EN_RC
Q2225 1K

5
signals for independent DAC 1 2
DMN5L06VK-7
1% 1%
1/20W

G
PLACE_NEAR=C2260.1:2mm 1/16W
margining support. When CRITICAL DDRVREF_DAC 5% DDRVREF_DAC SOT-563 MF MF-LF
1/16W 201
DAC margining VREFCA ensure Q2260 1
C2265 1 R2263 2
402
R2207 MF-LF PLACE_NEAR=R2263.2:1mm

5
402 2

D
ISOLATE_CPU_MEM_L is low DMN5L06VK-7 100K 0.1UF 1 2 PPVREF_S3_MEM_VREFCA_A

G
23
SOT-563 20%

3
5% MIN_LINE_WIDTH=0.3 mm

4
10V
to remove short due to CPU. 1/20W CERM 2 5% PLACE_NEAR=R2261.2:1mm MIN_NECK_WIDTH=0.2 mm
MF 1/20W
402 MF 1
201 R2262

D
2 201
1K

3
4
PLACE_NEAR=Q2220.3:2mm 1%
1/16W
1
C2260 MF-LF

C DAC-Based Margining CPU_MEM_VREFCA_B_ISOL

2
0.022UF
10%
6.3V
402
2
C
X5R-CERM
DDRVREF_DAC CRITICAL 0201 R2260
DAC sets voltage level, PCA9557 & FETs enable outputs 1
OMIT R2285 DDRVREF_DAC 24.9 R2281
and disables margining after platform reset. MEM_VREFCA_A_RC 1 2

=PP3V3_S3_VREFMRGN R2218 100K

VREFMRGN_CA_B_EN_RC
Q2265 1K

5
70 22 1 2 1% 1%
SHORT DMN5L06VK-7 1/20W

G
PLACE_NEAR=C2280.1:2mm 1/16W
1 2 PP3V3_S3_VREFMRGN DDRVREF_DAC 5% DDRVREF_DAC SOT-563 MF MF-LF
1/16W 201
NONE
MIN_LINE_WIDTH=0.3 mm
1 MF-LF C2285 1 R2283 2
402

NONE
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
R2208 402 2
PLACE_NEAR=R2283.2:1.5MM

D
NONE DDRVREF_DAC DDRVREF_DAC 100K 0.1UF 1 2 PPVREF_S3_MEM_VREFCA_B 24
402 20%

3
5% MIN_LINE_WIDTH=0.3 mm

4
10V
C2200 1 1
C2201 1/20W CERM 2 5%
1/20W
PLACE_NEAR=R2281.2:1mm MIN_NECK_WIDTH=0.2 mm
MF
2.2UF 0.1UF 402 MF 1
20% 10%
201
2 201 R2282
6.3V 6.3V
CERM 2 2 CERM-X5R CRITICAL 1K
402-LF 0201 PLACE_NEAR=Q2260.3:2mm 1%
DDRVREF_DAC (All 4 R’s) 1/16W
8 1
C2280 MF-LF
VDD DDRVREF_DAC 0.022UF 402
2
47 IN =I2C_VREFDACS_SCL 6 SCL
U2200 VOUTA 1 VREFMRGN_DQ_A R2226 332 1 2 VREFMRGN_DQ_A_RDIV R22x6 pin 2: 10%
6.3V
MSOP 1% 1/16W MF-LF 402 2 X5R-CERM
DAC5574
PLACE_NEAR=Q2225.1:5.5mm
47 BI =I2C_VREFDACS_SDA 7 SDA VOUTB 2 VREFMRGN_DQ_B R2246 332 1 2 VREFMRGN_DQ_B_RDIV 0201 R2280
1% 1/16W MF-LF 402 PLACE_NEAR=Q2265.4:5.5mm 24.9
MEM_VREFCA_B_RC 1 2
9 A0 VOUTC 4 VREFMRGN_CA_AB R2266 332 1 2 VREFMRGN_CA_A_RDIV PLACE_NEAR=Q2225.1:5.5mm
1% 1/16W MF-LF 402 1%
Addr=0x98(WR)/0x99(RD) PLACE_NEAR=Q2265.4:5.5mm 1/20W
10 A1 VOUTD 5 VREFMRGN_MEMVREG_FBVREF R2286 332 1 2 VREFMRGN_CA_B_RDIV MF
1% 1/16W MF-LF 402 201

GND
3
NOTE: MEMVREG and FRAMEBUF share
a DAC output, cannot enable
both at the same time!
=PP3V3_S3_VREFMRGN 22 70

CRITICAL
DDRVREF_DAC
B DDRVREF_DAC
CRITICAL C2205
0.1UF
1
DDRVREF_DAC
B
DDRVREF_DAC
16

C2202 1 10%
6.3V B1 U2204 DDRVREF_DAC
2
0.1UF VCC CERM-X5R C2
10%
6.3V
0201
V+
MAX4253
UCSP
R2214
CERM-X5R 2 U2201 C1 VREFMRGN_MEMVREG_BUF 1
33.2K
2 DDRREG_FB OUT 63
0201 PCA9557
QFN C4 1%
6 C3
(OD) P0 NC V- 1/16W
MF-LF
3
A0 P1 7 VREFMRGN_DQ_A_EN B4 402

Addr=0x30(WR)/0x31(RD) 4
A1 P2 9 VREFMRGN_DQ_B_EN
5
A2 P3 10 VREFMRGN_CA_A_EN
P4 11 VREFMRGN_CA_B_EN
P5 12 VREFMRGN_MEMVREG_EN CRITICAL
47 IN =I2C_PCA9557D_SCL 1
SCL P6 13 VREFMRGN_FRAMEBUF_EN DDRVREF_DAC DDRVREF_DAC
47 =I2C_PCA9557D_SDA 2
SDA P7 14
R2213
1
BI NC
100K
THRM RESET* 15 5%
A2
B1 U2204
1/20W MAX4253
PAD GND MF V+ UCSP
201
17

2 A1 VREFMRGN_FRAMEBUF_BUF
RST* on ’platform reset’ so that system
watchdog will disable margining. A3 A4 DDRVREF_DAC
V- 1
NOTE: Margining will be disabled across all B4 R2217
1M
soft-resets and sleep/wake cycles. Pins B1 & B4: 5%
1/16W
CKPLUS_WAIVE=unconnected_pins MF-LF
21 20 IN PCA9557D_RESET_L 2
402
DDRVREF_DAC
R2215 1
MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA MEM VREG 100K
5%
1/20W

A DAC Channel: A B C C D
MF
201
2
SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013 A
PCA9557D Pin: 1 2 3 4 5 PAGE TITLE

DDR3 (1.5V) DDR3L (1.35V) DDR3 (1.5V) DDR3L (1.35V)

DDR3 VREF MARGINING
DRAWING NUMBER SIZE
Nominal value 0.750V (DAC: 0x3A = 0.747mV) 0.675V (DAC: 0x34 = 0.670mV) 1.500V (DAC: 0x74 = 1.495V) 1.343V (DAC: 0x68 = 1.341V) NOTE: DDR3 assumes TPS51916 supply with 10.0k/49.9k divider
Apple Inc. 051-0164 D
DDR3L assumes TPS51916 supply with 19.6k/57.6k divider REVISION
Margined target: 0.300V - 1.200V (+/- 450mV) 0.275V - 1.075V (+/- 400mV) 1.200V - 1.800V (+/- 300mV) 0.950V - 1.750V (+/- 400mV) R
12.4.0
DAC range: 0.000V - 1.508V (0x00 - 0x75) 0.000V - 1.354V (0x00 - 0x69) 0.000V - 3.004V (0x00 - 0xE9) 0.000V - 2.707V (0x00 - 0xD2) NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
Margined range: 0.299V - 1.206V (+/- 453mV) 0.269V - 1.083V (+/- 406mV) 1.199V - 1.801V (+/- 301mV) 0.932V - 1.760V (+/- 414mV) PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VRef current: +901uA - -911uA (- = sourced) +811uA - -816uA (- = sourced) +36uA - -36uA (- = sourced) +28uA - -29uA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 22 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
DAC step size: 7.68mV / step @ output 7.67mV / step @ output 2.575mV / step @ output 3.923mV / step @ output
IV ALL RIGHTS RESERVED 22 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PPVREF_S3_MEM_VREFDQ_A 1 2
22 VREFDQ VSS_0
VOLTAGE=0.75V 3 CRITICAL 4
VSS_1 DQ4 =MEM_A_DQ<4> BI 25

25 BI =MEM_A_DQ<0> 5
DQ0 J2300 DQ5
6 =MEM_A_DQ<5> BI 25

=MEM_A_DQ<1> 7 F-RT-SM 8
25 BI DQ1 VSS_2

2-2013310-1
9 10 =MEM_A_DQS_N<0> BI
VSS_3 DQS0* 25
1 C2330 1 C2331 11
DM0 DQS0
12 =MEM_A_DQS_P<0> BI 25
2.2UF 0.1UF 13
VSS_4 VSS_5
14
20% 20%
2 6.3V
CERM 2 10V
CERM 25 BI =MEM_A_DQ<2> 15
DQ2 DQ6
16 =MEM_A_DQ<6> BI 25
402-LF 402 =MEM_A_DQ<3> 17 18 =MEM_A_DQ<7>
25 BI DQ3 DQ7 BI 25
19 20
VSS_6 VSS_7
=MEM_A_DQ<8> 21 22 =MEM_A_DQ<12>
25 BI DQ8 DQ12 BI 25

=MEM_A_DQ<9> 23 24 =MEM_A_DQ<13>
25 BI DQ9 DQ13 BI 25

D 25 BI =MEM_A_DQS_N<1>
25
27
VSS_8
DQS1*
VSS_9
DM1
26
28 D
=MEM_A_DQS_P<1> 29 30 MEM_RESET_L
25 BI DQS1 RESET* IN 21 24 75
31 32
VSS_10 VSS_11
=MEM_A_DQ<10> 33 34 =MEM_A_DQ<14>
25 BI DQ10 DQ14 BI 25

=MEM_A_DQ<11> 35 36 =MEM_A_DQ<15>
25 BI DQ11 DQ15 BI 25
37 38
VSS_12 VSS_13
=MEM_A_DQ<16> 39 40 =MEM_A_DQ<20>
25 BI DQ16 DQ20 BI 25

=MEM_A_DQ<17> 41 42 =MEM_A_DQ<21>
25 BI DQ17 DQ21 BI 25
43 44
VSS_14 VSS_15
=MEM_A_DQS_N<2> 45 46
25 BI DQS2* DM2
=MEM_A_DQS_P<2> 47 48
25 BI DQS2 VSS_16
49 50 =MEM_A_DQ<22>
VSS_17 DQ22 BI 25

=MEM_A_DQ<18> 51 52 =MEM_A_DQ<23>
25 BI DQ18 DQ23 BI 25

=MEM_A_DQ<19> 53 54
25 BI DQ19 VSS_18
55 56 =MEM_A_DQ<28>
VSS_19 DQ28 BI 25

=MEM_A_DQ<24> 57 58 =MEM_A_DQ<29>
25 BI DQ24 DQ29 BI 25

=MEM_A_DQ<25> 59 60
25 BI DQ25 VSS_20
61 62 =MEM_A_DQS_N<3> BI
VSS_21 DQS3* 25
63 64 =MEM_A_DQS_P<3> BI
DM3 DQS3 25
65 66
VSS_22 VSS_23
=MEM_A_DQ<26> 67 68 =MEM_A_DQ<30>
25 BI DQ26 DQ30 BI 25

=MEM_A_DQ<27> 69 70 =MEM_A_DQ<31>
25 BI DQ27 DQ31 BI 25
71 72
VSS_24 VSS_25
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR) KEY
MEM_A_CKE<0> 73 74 MEM_A_CKE<1>
75 7 IN CKE0 CKE1 IN 7 75

=PPVDDQ_S3_MEM_A 75 76 =PPVDDQ_S3_MEM_A
70 23 VDD_0 VDD_1 23 70
77 78 MEM_A_A<15>
C 1 C2310 1 C2311 1 C2312 1 C2313 1 C2314 1 C2315 1 C2316 1 C2317 1 C2302
75 7 IN MEM_A_BA<2>
NC
79
NC_0
BA2
A15
A14
80 MEM_A_A<14>
IN
IN
7 75

7 75
C
81 82
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VDD_2 VDD_3 1 1 1 1 1 1 1
20% 20% 20% 20% 20% 20% 20% 20% 20% MEM_A_A<12> 83 84 MEM_A_A<11> C2300 C2301 C2318 C2319 C2320 C2321 C2322 1 C2323 1 C2324
2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V
75 7 IN A12/BC* A11 IN 7 75
10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402 75 7 MEM_A_A<9> 85
A9 A7
86 MEM_A_A<7> 7 75
20% 20% 20% 20% 20% 20% 20% 0.1UF 0.1UF
2 6.3V 2 6.3V 2 10V 2 10V 2 10V 2 10V 2 10V
IN IN 20% 20%
87 88 X5R X5R CERM CERM CERM CERM CERM 2 10V 2 10V
VDD_4 VDD_5 603 603 402 402 402 402 402 CERM CERM
MEM_A_A<8> 89 90 MEM_A_A<6> 402 402
75 7 IN A8 A6 IN 7 75

MEM_A_A<5> 91 92 MEM_A_A<4>
75 7 IN A5 A4 IN 7 75
93 94
VDD_6 VDD_7
MEM_A_A<3> 95 96 MEM_A_A<2>
75 7 IN A3 A2 IN 7 75

MEM_A_A<1> 97 98 MEM_A_A<0>
75 7 IN A1 A0 IN 7 75
99 100
VDD_8 VDD_9
MEM_A_CLK_P<0> 101 102 MEM_A_CLK_P<1>
75 7 IN CK0 CK1 IN 7 75

MEM_A_CLK_N<0> 103 104 MEM_A_CLK_N<1>

75 7 IN CK0* CK1* IN 7 75
105 106
VDD_10 VDD_11
MEM_A_A<10> 107 108 MEM_A_BA<1>
75 7 IN A10_AP BA1 IN 7 75

MEM_A_BA<0> 109 110 MEM_A_RAS_L

75 7 IN BA0 RAS* IN 7 75
111 112
VDD_12 VDD_13
MEM_A_WE_L 113 114 MEM_A_CS_L<0>
75 7 IN WE* S0* IN 7 75

MEM_A_CAS_L 115 116 MEM_A_ODT<0>

75 7 IN CAS* ODT0 IN 7 75
117 118
VDD_14 VDD_15
MEM_A_A<13> 119 120 MEM_A_ODT<1>
75 7 IN A13 ODT1 IN 7 75

MEM_A_CS_L<1> 121 122

75 7 IN S1* NC_1 NC
123 124
VDD_16 VDD_17
125 126 PPVREF_S3_MEM_VREFCA_A 22
NC TEST VREFCA
127 128 VOLTAGE=0.75V
VSS_26 VSS_27
=MEM_A_DQ<32> 129 130 =MEM_A_DQ<36>
25 DQ32 DQ36 25

B 25
BI
BI =MEM_A_DQ<33> 131
133
DQ33 DQ37
132
134
=MEM_A_DQ<37>
BI
BI 25
1 C2335
2.2UF
1 C2336
0.1UF
B
VSS_28 VSS_29 20% 20%
=MEM_A_DQS_N<4> 135 136 2 6.3V 2 10V
25 BI DQS4* DM4 CERM CERM
=MEM_A_DQS_P<4> 137 138 402-LF 402
25 BI DQS4 VSS_30
139 140 =MEM_A_DQ<38>
VSS_31 DQ38 BI 25

MEM_A_SA<1> =MEM_A_DQ<34> 141 142 =MEM_A_DQ<39>

23 25 BI DQ34 DQ39 BI 25

=MEM_A_DQ<35> 143 144

MEM_A_SA<0> 25 BI DQ35 VSS_32
23 145 146
VSS_33 DQ44 =MEM_A_DQ<44> BI 25

=PPSPD_S0_MEM_A =MEM_A_DQ<40> 147 148 =MEM_A_DQ<45>

70 23 25 BI DQ40 DQ45 BI 25

=MEM_A_DQ<41> 149 150

1 1 25 BI DQ41 VSS_34
1 C2340 R2340 R2341 151
VSS_35 DQS5*
152 =MEM_A_DQS_N<5>BI 25
2.2UF 10K 10K 153 154
20% 5% 5% DM5 DQS5 =MEM_A_DQS_P<5>BI 25
1/16W 1/16W
2 6.3V
CERM MF-LF MF-LF 155
VSS_36 VSS_37
156
402-LF 2 402 2 402 =MEM_A_DQ<42> 157 158 =MEM_A_DQ<46>
25 BI DQ42 DQ46 BI 25

=MEM_A_DQ<43> 159 160 =MEM_A_DQ<47>

25 BI DQ43 DQ47 BI 25
=PPDDRVTT_S0_MEM_A
161 162 23 70

=PPDDRVTT_S0_MEM_A VSS_38 VSS_39

70 23 163 164
25 BI =MEM_A_DQ<48> DQ48 DQ52 =MEM_A_DQ<52> BI 25

=MEM_A_DQ<49> 165 166 =MEM_A_DQ<53>

25 BI DQ49 DQ53 BI 25
167 168
VSS_40 VSS_41
25 BI =MEM_A_DQS_N<6> 169
DQS6* DM6
170 1 C2350 1 C2351 1 C2352 1 C2353
25 BI =MEM_A_DQS_P<6> 171
DQS6 VSS_42
172 1UF 1UF 1UF 1UF
10% 10% 10% 10%
173 174 =MEM_A_DQ<54> 2 10V 2 10V 2 10V 10V
2 X6S-CERM
VSS_43 DQ54 BI 25 X6S-CERM X6S-CERM X6S-CERM
=MEM_A_DQ<50> 175 176 =MEM_A_DQ<55> 0402 0402 0402 0402
25 BI DQ50 DQ55 BI 25

=MEM_A_DQ<51> 177 178

25 BI DQ51 VSS_44
179 180 =MEM_A_DQ<60>
VSS_45 DQ60 BI 25

=MEM_A_DQ<56> 181 182 =MEM_A_DQ<61>

A 25

25
BI
BI =MEM_A_DQ<57> 183
DQ56
DQ57
DQ61
VSS_46
184
BI 25

SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013 A
185 186 =MEM_A_DQS_N<7>BI PAGE TITLE
VSS_47 DQS7* 25
187
189
DM7 DQS7
188
190
=MEM_A_DQS_P<7>BI 25 DDR3 SO-DIMM Connector A
VSS_48 VSS_49 DRAWING NUMBER SIZE
25 BI =MEM_A_DQ<58> 191
DQ58 DQ62
192 =MEM_A_DQ<62> BI 25
Apple Inc. 051-0164 D
=MEM_A_DQ<59> 193 194 =MEM_A_DQ<63> REVISION
25 BI DQ59 DQ63 BI 25
R
195
VSS_50 VSS_51
196 12.4.0
MEM_A_SA<0> 197 198 MEM_EVENT_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
23 SA0 EVENT* OUT 24 44 45

=PPSPD_S0_MEM_A 199 200 =I2C_SODIMMA_SDA THE INFORMATION CONTAINED HEREIN IS THE

70 23 VDDSPD SDA BI 47
PROPRIETARY PROPERTY OF APPLE INC.
MEM_A_SA<1> 201 202 =I2C_SODIMMA_SCL THE POSESSOR AGREES TO THE FOLLOWING: PAGE
23 SA1 SCL IN 47
203
VTT_0 VTT_1
204 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
23 OF 123
205 206 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
MTG_PIN MTG_PIN
IV ALL RIGHTS RESERVED 23 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PPVREF_S3_MEM_VREFDQ_B 1 2
22 VREFDQ VSS_0
VOLTAGE=0.75V
3 CRITICAL 4
VSS_1 DQ4 =MEM_B_DQ<4> BI 25

25 BI =MEM_B_DQ<0> 5
DQ0 J2500 DQ5
6 =MEM_B_DQ<5> BI 25

=MEM_B_DQ<1> 7 F-RT-SM 8
DQ1 VSS_2
1 C2530 1 C2531 25 BI

2-2013289-1
9 10 =MEM_B_DQS_N<0> BI
2.2UF 0.1UF VSS_3 DQS0* 25
20% 20% 11 12 =MEM_B_DQS_P<0> BI
DM0 DQS0 25
2 6.3V
CERM 2 10V
CERM 13 14
402-LF 402 VSS_4 VSS_5
=MEM_B_DQ<2> 15 16 =MEM_B_DQ<6>
25 BI DQ2 DQ6 BI 25

=MEM_B_DQ<3> 17 18 =MEM_B_DQ<7>
25 BI DQ3 DQ7 BI 25
19 20
VSS_6 VSS_7
=MEM_B_DQ<8> 21 22 =MEM_B_DQ<12>
25 BI DQ8 DQ12 BI 25

=MEM_B_DQ<9> 23 24 =MEM_B_DQ<13>
25 BI DQ9 DQ13 BI 25

D 25 BI =MEM_B_DQS_N<1>
25
27
VSS_8
DQS1*
VSS_9
DM1
26
28 D
=MEM_B_DQS_P<1> 29 30 MEM_RESET_L
25 BI DQS1 RESET* IN 21 23 75
31 32
VSS_10 VSS_11
=MEM_B_DQ<10> 33 34 =MEM_B_DQ<14>
25 BI DQ10 DQ14 BI 25

=MEM_B_DQ<11> 35 36 =MEM_B_DQ<15>
25 BI DQ11 DQ15 BI 25
37 38
VSS_12 VSS_13
=MEM_B_DQ<16> 39 40 =MEM_B_DQ<20>
25 BI DQ16 DQ20 BI 25

=MEM_B_DQ<17> 41 42 =MEM_B_DQ<21>
25 BI DQ17 DQ21 BI 25
43 44
VSS_14 VSS_15
=MEM_B_DQS_N<2> 45 46
25 BI DQS2* DM2
=MEM_B_DQS_P<2> 47 48
25 BI DQS2 VSS_16
49 50 =MEM_B_DQ<22>
VSS_17 DQ22 BI 25

=MEM_B_DQ<18> 51 52 =MEM_B_DQ<23>
25 BI DQ18 DQ23 BI 25

=MEM_B_DQ<19> 53 54
25 BI DQ19 VSS_18
55 56 =MEM_B_DQ<28>
VSS_19 DQ28 BI 25

=MEM_B_DQ<24> 57 58 =MEM_B_DQ<29>
25 BI DQ24 DQ29 BI 25

=MEM_B_DQ<25> 59 60
25 BI DQ25 VSS_20
61 62 =MEM_B_DQS_N<3> BI
VSS_21 DQS3* 25
63 64 =MEM_B_DQS_P<3> BI
DM3 DQS3 25
65 66
VSS_22 VSS_23
=MEM_B_DQ<26> 67 68 =MEM_B_DQ<30>
25 BI DQ26 DQ30 BI 25

=MEM_B_DQ<27> 69 70 =MEM_B_DQ<31>
25 BI DQ27 DQ31 BI 25
71 72
VSS_24 VSS_25
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR) KEY
MEM_B_CKE<0> 73 74 MEM_B_CKE<1>
75 7 IN CKE0 CKE1 IN 7 75

=PPVDDQ_S3_MEM_B 75 76 =PPVDDQ_S3_MEM_B
70 24 VDD_0 VDD_1 24 70
77 78 MEM_B_A<15>
C 1 C2510 1 C2511 1 C2512 1 C2513 1 C2514 1 C2515 1 C2516 1 C2517 1 C2502
75 7 IN MEM_B_BA<2>
NC
79
NC_0
BA2
A15
A14
80 MEM_B_A<14>
IN
IN
7 75

7 75
C
81 82 1 C2500 1 C2501 1 C2518 1 C2519 1 C2520 1 C2521 1 C2522
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VDD_2 VDD_3 1 1
20% 20% 20% 20% 20% 20% 20% 20% 20% MEM_B_A<12> 83 84 MEM_B_A<11> 10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C2523 C2524
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
75 7 IN
85
A12/BC* A11 IN 7 75
20% 20% 20% 20% 20% 20% 20% 0.1UF 0.1UF
MEM_B_A<9> 86 MEM_B_A<7> 2 6.3V 2 6.3V 2 10V 2 10V 2 10V 2 10V 2 10V 20% 20%
402 402 402 402 402 402 402 402 402 75 7 A9 A7 7 75 X5R X5R CERM CERM CERM CERM CERM
IN
87 88
IN
603 603 402 402 402 402 402 2 10V
CERM 2 10V
CERM
VDD_4 VDD_5 402 402
MEM_B_A<8> 89 90 MEM_B_A<6>
75 7 IN A8 A6 IN 7 75

MEM_B_A<5> 91 92 MEM_B_A<4>
75 7 IN A5 A4 IN 7 75
93 94
VDD_6 VDD_7
MEM_B_A<3> 95 96 MEM_B_A<2>
75 7 IN A3 A2 IN 7 75

MEM_B_A<1> 97 98 MEM_B_A<0>
75 7 IN A1 A0 IN 7 75
99 100
VDD_8 VDD_9
MEM_B_CLK_P<0> 101 102 MEM_B_CLK_P<1>
75 7 IN CK0 CK1 IN 7 75

MEM_B_CLK_N<0> 103 104 MEM_B_CLK_N<1>

75 7 IN CK0* CK1* IN 7 75
105 106
VDD_10 VDD_11
MEM_B_A<10> 107 108 MEM_B_BA<1>
75 7 IN A10_AP BA1 IN 7 75

MEM_B_BA<0> 109 110 MEM_B_RAS_L

75 7 IN BA0 RAS* IN 7 75
111 112
VDD_12 VDD_13
MEM_B_WE_L 113 114 MEM_B_CS_L<0>
75 7 IN WE* S0* IN 7 75

MEM_B_CAS_L 115 116 MEM_B_ODT<0>

75 7 IN CAS* ODT0 IN 7 75
117 118
VDD_14 VDD_15
MEM_B_A<13> 119 120 MEM_B_ODT<1>
=PPSPD_S0_MEM_B 75 7 IN A13 ODT1 IN 7 75
70 24
MEM_B_CS_L<1> 121 122
75 7 IN S1* NC_1 NC
123 124
VDD_16 VDD_17
125 126 PPVREF_S3_MEM_VREFCA_B 22
NC TEST VREFCA
127 128 VOLTAGE=0.75V
VSS_26 VSS_27
1 =MEM_B_DQ<32> 129 130 =MEM_B_DQ<36>
R2541 DQ32 DQ36
C2535 C2536
25 25

B 10K
5%
25
BI
BI =MEM_B_DQ<33> 131
133
DQ33 DQ37
132
134
=MEM_B_DQ<37>
BI
BI 25
1
2.2UF
1
0.1UF
20%
B
1/16W VSS_28 VSS_29
MF-LF 135 136
20% 2 10V
2 402 25 BI =MEM_B_DQS_N<4> DQS4* DM4 2 6.3V
CERM
CERM
402
=MEM_B_DQS_P<4> 137 138 402-LF
25 BI DQS4 VSS_30
139 140 =MEM_B_DQ<38>
VSS_31 DQ38 BI 25

MEM_B_SA<1> =MEM_B_DQ<34> 141 142 =MEM_B_DQ<39>

24 25 BI DQ34 DQ39 BI 25

=MEM_B_DQ<35> 143 144

MEM_B_SA<0> 25 BI DQ35 VSS_32
24 145 146
VSS_33 DQ44 =MEM_B_DQ<44> BI 25

=MEM_B_DQ<40> 147 148 =MEM_B_DQ<45>

25 BI DQ40 DQ45 BI 25

=MEM_B_DQ<41> 149 150

1 25 BI DQ41 VSS_34
R2540 151
VSS_35 DQS5*
152 =MEM_B_DQS_N<5>BI 25
10K 153 154
5% DM5 DQS5 =MEM_B_DQS_P<5>BI 25
1/16W 155 156
MF-LF VSS_36 VSS_37
2 402 =MEM_B_DQ<42> 157 158 =MEM_B_DQ<46>
25 BI DQ42 DQ46 BI 25

=PPDDRVTT_S0_MEM_B =MEM_B_DQ<43> 159 160 =MEM_B_DQ<47> =PPDDRVTT_S0_MEM_B

70 24 25 BI DQ43 DQ47 BI 25 24 70
161 162
VSS_38 VSS_39
=MEM_B_DQ<48> 163 164 =MEM_B_DQ<52>
25 BI DQ48 DQ52 BI 25

25 BI =MEM_B_DQ<49> 165
DQ49 DQ53
166 =MEM_B_DQ<53> BI 25
1 C2550 1 C2551 1 C2552 1 C2553
167
VSS_40 VSS_41
168 1UF 1UF 1UF 1UF
10% 10% 10% 10%
=MEM_B_DQS_N<6> 169 170 2 10V 2 10V 2 10V 2 10V
25 BI DQS6* DM6 X6S-CERM X6S-CERM X6S-CERM X6S-CERM
=MEM_B_DQS_P<6> 171 172 0402 0402 0402 0402
25 BI DQS6 VSS_42
173 174 =MEM_B_DQ<54>
VSS_43 DQ54 BI 25

=MEM_B_DQ<50> 175 176 =MEM_B_DQ<55>

=PPSPD_S0_MEM_B 25 BI DQ50 DQ55 BI 25
70 24 177 178
25 BI =MEM_B_DQ<51> DQ51 VSS_44
179 180 =MEM_B_DQ<60>
VSS_45 DQ60
1 C2540 =MEM_B_DQ<56> 181 182 =MEM_B_DQ<61>
BI 25

A 2.2UF
20%
2 6.3V
25

25
BI
BI =MEM_B_DQ<57> 183
DQ56
DQ57
DQ61
VSS_46
184
BI 25

SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013 A
CERM 185 186 =MEM_B_DQS_N<7>BI PAGE TITLE
402-LF VSS_47 DQS7* 25
187
189
DM7 DQS7
188
190
=MEM_B_DQS_P<7>BI 25 DDR3 SO-DIMM CONNECTOR B
VSS_48 VSS_49 DRAWING NUMBER SIZE
25 BI =MEM_B_DQ<58> 191
DQ58 DQ62
192 =MEM_B_DQ<62> BI 25
Apple Inc. 051-0164 D
=MEM_B_DQ<59> 193 194 =MEM_B_DQ<63> REVISION
25 BI DQ59 DQ63 BI 25
R
195
VSS_50 VSS_51
196 12.4.0
MEM_B_SA<0> 197 198 MEM_EVENT_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
24 SA0 EVENT* OUT 23 44 45

=PPSPD_S0_MEM_B 199 200 =I2C_SODIMMB_SDA THE INFORMATION CONTAINED HEREIN IS THE

70 24 VDDSPD SDA BI 47
PROPRIETARY PROPERTY OF APPLE INC.
MEM_B_SA<1> 201 202 =I2C_SODIMMB_SCL THE POSESSOR AGREES TO THE FOLLOWING: PAGE
24 SA1 SCL IN 47
203
VTT_0 VTT_1
204 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
25 OF 123
205 206 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
MTG_PIN MTG_PIN
IV ALL RIGHTS RESERVED 24 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THERE ARE NO PIN SWAPS
75 7 MEM_A_DQS_N<0> =MEM_A_DQS_N<0> 23 75 7 MEM_B_DQS_N<0> =MEM_B_DQS_N<0> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQS_P<0> =MEM_A_DQS_P<0> 23 75 7 MEM_B_DQS_P<0> =MEM_B_DQS_P<0> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

75 7 MEM_A_DQ<7> =MEM_A_DQ<7> 23 75 7 MEM_B_DQ<7> =MEM_B_DQ<7> 24

MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<6> =MEM_A_DQ<6> 23 75 7 MEM_B_DQ<6> =MEM_B_DQ<6> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<5> =MEM_A_DQ<5> 23 75 7 MEM_B_DQ<5> =MEM_B_DQ<5> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<4> =MEM_A_DQ<4> 23 75 7 MEM_B_DQ<4> =MEM_B_DQ<4> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<3> =MEM_A_DQ<3> 23 75 7 MEM_B_DQ<3> =MEM_B_DQ<3> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
D 75 7

75 7
MEM_A_DQ<2>
MEM_A_DQ<1>
MAKE_BASE=TRUE
=MEM_A_DQ<2>
=MEM_A_DQ<1>
23

23
75 7

75 7
MEM_B_DQ<2>
MEM_B_DQ<1>
MAKE_BASE=TRUE
=MEM_B_DQ<2>
=MEM_B_DQ<1>
24

24
D
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<0> =MEM_A_DQ<0> 23 75 7 MEM_B_DQ<0> =MEM_B_DQ<0> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

75 7 MEM_A_DQS_N<1> =MEM_A_DQS_N<1> 23 75 7 MEM_B_DQS_N<1> =MEM_B_DQS_N<1> 24

MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQS_P<1> =MEM_A_DQS_P<1> 23 75 7 MEM_B_DQS_P<1> =MEM_B_DQS_P<1> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

75 7 MEM_A_DQ<15> =MEM_A_DQ<15> 23 75 7 MEM_B_DQ<15> =MEM_B_DQ<15> 24

MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<14> =MEM_A_DQ<14> 23 75 7 MEM_B_DQ<14> =MEM_B_DQ<14> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<13> =MEM_A_DQ<13> 23 75 7 MEM_B_DQ<13> =MEM_B_DQ<13> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<12> =MEM_A_DQ<12> 23 75 7 MEM_B_DQ<12> =MEM_B_DQ<12> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<11> =MEM_A_DQ<11> 23 75 7 MEM_B_DQ<11> =MEM_B_DQ<11> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<10> =MEM_A_DQ<10> 23 75 7 MEM_B_DQ<10> =MEM_B_DQ<10> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<9> =MEM_A_DQ<9> 23 75 7 MEM_B_DQ<9> =MEM_B_DQ<9> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<8> =MEM_A_DQ<8> 23 75 7 MEM_B_DQ<8> =MEM_B_DQ<8> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

75 7 MEM_A_DQS_N<2> =MEM_A_DQS_N<2> 23 75 7 MEM_B_DQS_N<2> =MEM_B_DQS_N<2> 24

MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQS_P<2> =MEM_A_DQS_P<2> 23 75 7 MEM_B_DQS_P<2> =MEM_B_DQS_P<2> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

75 7 MEM_A_DQ<23> =MEM_A_DQ<23> 23 75 7 MEM_B_DQ<23> =MEM_B_DQ<23> 24

MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<22> =MEM_A_DQ<22> 23 75 7 MEM_B_DQ<22> =MEM_B_DQ<22> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<21> =MEM_A_DQ<21> 23 75 7 MEM_B_DQ<21> =MEM_B_DQ<21> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<20> =MEM_A_DQ<20> 23 75 7 MEM_B_DQ<20> =MEM_B_DQ<20> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<19> =MEM_A_DQ<19> 23 75 7 MEM_B_DQ<19> =MEM_B_DQ<19> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<18> =MEM_A_DQ<18> 23 75 7 MEM_B_DQ<18> =MEM_B_DQ<18> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<17> =MEM_A_DQ<17> 23 75 7 MEM_B_DQ<17> =MEM_B_DQ<17> 24

C 75 7 MEM_A_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<16> 23 75 7 MEM_B_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<16> 24 C
75 7 MEM_A_DQS_N<3> =MEM_A_DQS_N<3> 23 75 7 MEM_B_DQS_N<3> =MEM_B_DQS_N<3> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQS_P<3> =MEM_A_DQS_P<3> 23 75 7 MEM_B_DQS_P<3> =MEM_B_DQS_P<3> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

75 7 MEM_A_DQ<31> =MEM_A_DQ<31> 23 75 7 MEM_B_DQ<31> =MEM_B_DQ<31> 24

MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<30> =MEM_A_DQ<30> 23 75 7 MEM_B_DQ<30> =MEM_B_DQ<30> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<29> =MEM_A_DQ<29> 23 75 7 MEM_B_DQ<29> =MEM_B_DQ<29> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<28> =MEM_A_DQ<28> 23 75 7 MEM_B_DQ<28> =MEM_B_DQ<28> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<27> =MEM_A_DQ<27> 23 75 7 MEM_B_DQ<27> =MEM_B_DQ<27> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<26> =MEM_A_DQ<26> 23 75 7 MEM_B_DQ<26> =MEM_B_DQ<26> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<25> =MEM_A_DQ<25> 23 75 7 MEM_B_DQ<25> =MEM_B_DQ<25> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<24> =MEM_A_DQ<24> 23 75 7 MEM_B_DQ<24> =MEM_B_DQ<24> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

75 7 MEM_A_DQS_N<4> =MEM_A_DQS_N<4> 23 75 7 MEM_B_DQS_N<4> =MEM_B_DQS_N<4> 24

MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQS_P<4> =MEM_A_DQS_P<4> 23 75 7 MEM_B_DQS_P<4> =MEM_B_DQS_P<4> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

75 7 MEM_A_DQ<39> =MEM_A_DQ<39> 23 75 7 MEM_B_DQ<39> =MEM_B_DQ<39> 24

MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<38> =MEM_A_DQ<38> 23 75 7 MEM_B_DQ<38> =MEM_B_DQ<38> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<37> =MEM_A_DQ<37> 23 75 7 MEM_B_DQ<37> =MEM_B_DQ<37> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<36> =MEM_A_DQ<36> 23 75 7 MEM_B_DQ<36> =MEM_B_DQ<36> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<35> =MEM_A_DQ<35> 23 75 7 MEM_B_DQ<35> =MEM_B_DQ<35> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<34> =MEM_A_DQ<34> 23 75 7 MEM_B_DQ<34> =MEM_B_DQ<34> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<33> =MEM_A_DQ<33> 23 75 7 MEM_B_DQ<33> =MEM_B_DQ<33> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<32> =MEM_A_DQ<32> 23 75 7 MEM_B_DQ<32> =MEM_B_DQ<32> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
B B
75 7 MEM_A_DQS_N<5> =MEM_A_DQS_N<5> 23 75 7 MEM_B_DQS_N<5> =MEM_B_DQS_N<5> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQS_P<5> =MEM_A_DQS_P<5> 23 75 7 MEM_B_DQS_P<5> =MEM_B_DQS_P<5> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

75 7 MEM_A_DQ<47> =MEM_A_DQ<47> 23 75 7 MEM_B_DQ<47> =MEM_B_DQ<47> 24

MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<46> =MEM_A_DQ<46> 23 75 7 MEM_B_DQ<46> =MEM_B_DQ<46> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<45> =MEM_A_DQ<45> 23 75 7 MEM_B_DQ<45> =MEM_B_DQ<45> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<44> =MEM_A_DQ<44> 23 75 7 MEM_B_DQ<44> =MEM_B_DQ<44> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<43> =MEM_A_DQ<43> 23 75 7 MEM_B_DQ<43> =MEM_B_DQ<43> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<42> =MEM_A_DQ<42> 23 75 7 MEM_B_DQ<42> =MEM_B_DQ<42> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<41> =MEM_A_DQ<41> 23 75 7 MEM_B_DQ<41> =MEM_B_DQ<41> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<40> =MEM_A_DQ<40> 23 75 7 MEM_B_DQ<40> =MEM_B_DQ<40> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

75 7 MEM_A_DQS_N<6> =MEM_A_DQS_N<6> 23 75 7 MEM_B_DQS_N<6> =MEM_B_DQS_N<6> 24

MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQS_P<6> =MEM_A_DQS_P<6> 23 75 7 MEM_B_DQS_P<6> =MEM_B_DQS_P<6> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

75 7 MEM_A_DQ<55> =MEM_A_DQ<55> 23 75 7 MEM_B_DQ<55> =MEM_B_DQ<55> 24

MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<54> =MEM_A_DQ<54> 23 75 7 MEM_B_DQ<54> =MEM_B_DQ<54> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<53> =MEM_A_DQ<53> 23 75 7 MEM_B_DQ<53> =MEM_B_DQ<53> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<52> =MEM_A_DQ<52> 23 75 7 MEM_B_DQ<52> =MEM_B_DQ<52> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<51> =MEM_A_DQ<51> 23 75 7 MEM_B_DQ<51> =MEM_B_DQ<51> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<50> =MEM_A_DQ<50> 23 75 7 MEM_B_DQ<50> =MEM_B_DQ<50> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<49> =MEM_A_DQ<49> 23 75 7 MEM_B_DQ<49> =MEM_B_DQ<49> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<48> =MEM_A_DQ<48> 23 75 7 MEM_B_DQ<48> =MEM_B_DQ<48> 24
MAKE_BASE=TRUE MAKE_BASE=TRUE

A 75 7 MEM_A_DQS_N<7>
MAKE_BASE=TRUE
=MEM_A_DQS_N<7> 23 75 7 MEM_B_DQS_N<7>
MAKE_BASE=TRUE
=MEM_B_DQS_N<7> 24 SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013 A
75 7 MEM_A_DQS_P<7> =MEM_A_DQS_P<7> 23 75 7 MEM_B_DQS_P<7> =MEM_B_DQS_P<7> 24
PAGE TITLE
MAKE_BASE=TRUE MAKE_BASE=TRUE
DDR3 ALIASES AND BITSWAPS
75 7 MEM_A_DQ<63> =MEM_A_DQ<63> 23 75 7 MEM_B_DQ<63> =MEM_B_DQ<63> 24 DRAWING NUMBER SIZE
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<62>
MAKE_BASE=TRUE
=MEM_A_DQ<62> 23 75 7 MEM_B_DQ<62>
MAKE_BASE=TRUE
=MEM_B_DQ<62> 24
Apple Inc. 051-0164 D
75 7 MEM_A_DQ<61> =MEM_A_DQ<61> 23 75 7 MEM_B_DQ<61> =MEM_B_DQ<61> 24 REVISION
MAKE_BASE=TRUE MAKE_BASE=TRUE R
75 7 MEM_A_DQ<60>
MAKE_BASE=TRUE
=MEM_A_DQ<60> 23 75 7 MEM_B_DQ<60>
MAKE_BASE=TRUE
=MEM_B_DQ<60> 24 12.4.0
75 7 MEM_A_DQ<59> =MEM_A_DQ<59> 23 75 7 MEM_B_DQ<59> =MEM_B_DQ<59> 24 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<58> =MEM_A_DQ<58> 23 75 7 MEM_B_DQ<58> =MEM_B_DQ<58> 24 THE INFORMATION CONTAINED HEREIN IS THE
MAKE_BASE=TRUE MAKE_BASE=TRUE PROPRIETARY PROPERTY OF APPLE INC.
75 7 MEM_A_DQ<57> =MEM_A_DQ<57> 23 75 7 MEM_B_DQ<57> =MEM_B_DQ<57> 24 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MAKE_BASE=TRUE MAKE_BASE=TRUE
75 7 MEM_A_DQ<56>
MAKE_BASE=TRUE
=MEM_A_DQ<56> 23 75 7 MEM_B_DQ<56>
MAKE_BASE=TRUE
=MEM_B_DQ<56> 24
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
27 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 25 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL

77 13 IN PCIE_TBT_R2D_C_P<0> C2800 1 2
AB9 OMIT_TABLE AD5
C2840 1 2 PCIE_TBT_D2R_P<0> OUT 13 77
10% 16V X5R-CERM 0201 77 PCIE_TBT_R2D_P<0> PERP_0 PETP_0 77 PCIE_TBT_D2R_C_P<0> 10% 16V X5R-CERM 0201
0.1UF 0.1UF
77 PCIE_TBT_R2D_N<0> AA10
PERN_0 U2800 PETN_0 AD7 77 PCIE_TBT_D2R_C_N<0>
77 13 IN PCIE_TBT_R2D_C_N<0> C2801 1 2
CACTUSRIDGE4C C2841 1 2
PCIE_TBT_D2R_N<0> OUT 13 77
10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
0.1UF FCBGA 0.1UF
(SYM 1 OF 2)
77 13 IN PCIE_TBT_R2D_C_P<1> C2802 1 2 C2842 1 2 PCIE_TBT_D2R_P<1> OUT 13 77

PCIE GEN2
PCIE_TBT_R2D_P<1> AA12 AD9 PCIE_TBT_D2R_C_P<1>
10% 16V X5R-CERM 0201 77 PERP_1 PETP_1 77 10% 16V X5R-CERM 0201
0.1UF AB13 AD11
0.1UF
77 PCIE_TBT_R2D_N<1> PERN_1 PETN_1 77 PCIE_TBT_D2R_C_N<1>

RECEIVE

TRANSMIT
77 13 IN PCIE_TBT_R2D_C_N<1> C2803 1 2
C2843 1 2
PCIE_TBT_D2R_N<1> OUT 13 77
10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
0.1UF 0.1UF

77 13 PCIE_TBT_R2D_C_P<2> C2804 1 2 C2844 1 2 PCIE_TBT_D2R_P<2> 13 77

D
IN
0.1UF
10% 16V X5R-CERM 0201 77

77
PCIE_TBT_R2D_P<2>
PCIE_TBT_R2D_N<2>
AB15

AA16
PERP_2
PERN_2
PETP_2
PETN_2
AD13

AD15
77

77
PCIE_TBT_D2R_C_P<2>
PCIE_TBT_D2R_C_N<2>
0.1UF
10% 16V X5R-CERM 0201
OUT
D
77 13 IN PCIE_TBT_R2D_C_N<2> C2805 1 2 C2845 1 2 PCIE_TBT_D2R_N<2> OUT 13 77
10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
0.1UF 0.1UF
70 68 30 29 28 27 26 =PP3V3_S4_TBT
77 13 IN PCIE_TBT_R2D_C_P<3> C2806 1 2
AA18 AD17
C2846 1 2 PCIE_TBT_D2R_P<3> OUT 13 77
10% 16V X5R-CERM 0201 77 PCIE_TBT_R2D_P<3> PERP_3 PETP_3 77 PCIE_TBT_D2R_C_P<3> 10% 16V X5R-CERM 0201
R2810 1 0.1UF
77 PCIE_TBT_R2D_N<3> AB19
PERN_3 PETN_3 AD19 77 PCIE_TBT_D2R_C_N<3>
0.1UF
47K 77 13 IN PCIE_TBT_R2D_C_N<3> C2807 1 2 C2847 1 2 PCIE_TBT_D2R_N<3> OUT 13 77
5% 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
1/16W 0.1UF 0.1UF
MF-LF R6 U20
402
2
28 IN TBT_PCIE_RESET_L PERST_N RSENSE TBT_RSENSE

TBT_PWR_ON_POC_RST_L J2
28 IN PWR_ON_POC_RSTN W20
RBIAS TBT_RBIAS 1
R2855
NO STUFF NOTE: The following pins require testpoints:
AD23
1K
=PP3V3_TBTLC_RTR 26 27 28 70 C2810 1 TP_TBT_MONDC0 MONDC0 U4 1% 0 - GPIO_13 8 - GPIO_15
0.1UF AC24 NC NC 1/20W
OMIT TP_TBT_MONDC1 MONDC1 MF 1 - GPIO_1 9 - GPIO_11
10%
16V 201
1 2
X7R-CERM 2 R2815 DEBUG: For monitoring current/voltage 2 - GPIO_2 10 - GPIO_14
1 0402 W18
R2892 1
1
C2890 R2893 NOSTUFF TBT_MONOBSP MONOBS_P 3 - GPIO_3 11 - GPIO_0
R2890 1
1
R2891 1UF 3.3K 3.3K
NONE
NONE TBT_MONOBSN W16
MONOBS_N 4 - GPIO_5 12 - GPIO_12
3.3K 3.3K 10%
5% 5% NONE Not used in host mode.

PCIE RESET
6.3V
5% 5% 2 1/16W 1/16W 402 2 DEBUG: For monitoring clock 5 - PCIE_RST_1_N 13 - GPIO_10

MISC
CERM N6 TP_TBT_PCIE_RESET0_L
1/16W 1/16W 402 CRITICAL MF-LF MF-LF Y7 PCIE_RST_0_N 72
MF-LF MF-LF 402 402 72 TP_TBT_THERM_DP THERMDA T1 6 - PCIE_RST_2_N 14 - PB_LSTX
402 402 OMIT_TABLE 2 2
Use AA8 GND ball for THERM_DN PCIE_RST_1_N TP_TBT_PCIE_RESET1_L
8 72
2 2 7 - PCIE_RST_3_N 15 - PB_LSRX
VCC Y5 TP_TBT_PCIE_RESET2_L
R4 PCIE_RST_2_N 72
85 TBT_SPI_MOSI EE_DI U2 TP_TBT_PCIE_RESET3_L

EEPROM
P5 PCIE_RST_3_N 72
(TBT_SPI_MOSI) 5 D U2890 Q 2 (TBT_SPI_MISO) 85 TBT_SPI_MISO EE_DO
M95256-RMC6XG TBT_SPI_CS_L AD3
85 EE_CS_N W6
(TBT_SPI_CLK) 6 C MLP
W4 PCIE_CLKREQ_OD_N =TBT_CLKREQ_L OUT 28
85 TBT_SPI_CLK EE_CLK =PP3V3_TBTLC_RTR 26 27 28 70

(TBT_SPI_CS_L) 1 S* K5 TBT_EN_LC_PWR

JTAG/TEST PORT
V1 EN_LC_PWR OUT 28
20 IN JTAG_TBT_TDI TDI 1
R2898
TBTROM_WP_L 3 W* AB3
20 IN JTAG_TBT_TMS TMS 10K
AA6 REFCLK_100_IN_P AB21 PCIE_CLK100M_TBT_P IN 11 77 5%

C TBTROM_HOLD_L 7 HOLD*
VSS THM
PAD
20

20
IN
OUT
JTAG_TBT_TCK
JTAG_TBT_TDO R2
TCK
TDO
REFCLK_100_IN_N AD21 PCIE_CLK100M_TBT_N IN 11 77
2
1/16W
MF-LF
402
R2895
C
TBT_TEST_EN N4

CLOCKS
TEST_EN AA24
806
4 9
AB5 XTAL_25_IN 79 SYSCLK_CLK25M_TBT_R 1 2 SYSCLK_CLK25M_TBT IN 19 79
TBT_TEST_PWR_GOOD TEST_PWR_GOOD AB23
XTAL_25_OUT TP_TBT_XTAL25OUT 1%
1/16W Divides 3.3V to 1.8V
MF-LF
1 1
R2825 R2829 85 26 DP_TBTSNK0_ML_P<3> E14
DPSNK0_3_P TMU_CLK_OUT AA4 TBT_TMU_CLK_OUT
402

0 0 D13 Y3
5% 5% 85 26 DP_TBTSNK0_ML_N<3> DPSNK0_3_N TMU_CLK_IN TBT_TMU_CLK_IN 70 28 27 26 =PP3V3_TBTLC_RTR
1/16W 1/16W
MF-LF MF-LF E16 NO STUFF
402 2 DP_TBTSNK0_ML_P<2> DPSNK0_2_P
2 402 85 26
TBT_SPI_CLK_RES R28011 2
DP_TBTSNK0_ML_N<2> D15
DPSNK0_2_N DPSRC_3_P A14 TP_DP_TBTSRC_ML_CP<3>
1
R2897 R2899
1 1
R2896
1
R2880
85 26 41

DISPLAYPORT
0

SINK PORT 0
5% 1/20W 100K 10K 1K 10K
B15 TP_DP_TBTSRC_ML_CN<3>
MF 0201 E18 DPSRC_3_N 41 5% 5% 5% 5%
85 26 DP_TBTSNK0_ML_P<1> DPSNK0_1_P 1/16W 1/16W 1/16W 1/16W
D17 A12 MF-LF MF-LF MF-LF MF-LF
DP_TBTSNK0_ML_N<1> DPSNK0_1_N DPSRC_2_P TP_DP_TBTSRC_ML_CP<2> 2 402 402 2
85 26 41
2 402 2
402
B13 TP_DP_TBTSRC_ML_CN<2>
E20 DPSRC_2_N 41
DP_TBTSNK0_ML_P<0> TBT_DDC_XBAR_EN_L

SOURCE PORT 0
85 26 DPSNK0_0_P 31 26

DP_TBTSNK0_ML_N<0> D19 A10 TP_DP_TBTSRC_ML_CP<1> TBT_GO2SX_BIDIR

85 26 DPSNK0_0_N DPSRC_1_P 41 26 14
B11 TP_DP_TBTSRC_ML_CN<1>
A6 DPSRC_1_N 41 R2881 FOR CYA,
85 26 DP_TBTSNK0_AUXCH_P DPSNK0_AUX_P 1
B5 A8 allows separation R2881
85 26 DP_TBTSNK0_AUXCH_N DPSNK0_AUX_N DPSRC_0_P TP_DP_TBTSRC_ML_CP<0> 41
SNK0 AC Coupling B9 TP_DP_TBTSRC_ML_CN<0>
of GPIO_2/GPIO_9 0
U6 DPSRC_0_N 41 5%
71 OUT DP_TBTSNK0_HPD DPSNK0_HPD if necessary. 1/16W
85 71 IN DP_TBTSNK0_ML_C_P<0> C2820 1 2 DP_TBTSNK0_ML_P<0> 26 85 C2 MF-LF
10% 16V DPSRC_AUX_P TP_DP_TBTSRC_AUXCH_CP 41 STUFF ONE OF R2881/2. 402
0.1UF 2
X5R-CERM 0201 E6 D3
R2830 1 85 26 DP_TBTSNK1_ML_P<3> DPSNK1_3_P DPSRC_AUX_N TP_DP_TBTSRC_AUXCH_CN 41
85 71 IN DP_TBTSNK0_ML_C_N<0> C2821 1 2 DP_TBTSNK0_ML_N<0> 26 85 D5 26 TBT_GPIO_9
10% 16V 100K 85 26 DP_TBTSNK1_ML_N<3> DPSNK1_3_N V3
0.1UF X5R-CERM 0201 5% DPSRC_HPD_OD DP_TBTSRC_HPD IN 41 26 TBT_GPIO_14
1/16W E8
MF-LF 85 26 DP_TBTSNK1_ML_P<2> DPSNK1_2_P NO STUFF
85 71 IN DP_TBTSNK0_ML_C_P<1> C2822 1 2 DP_TBTSNK0_ML_P<1> 26 85 402 D7
10% 16V
2
85 26 DP_TBTSNK1_ML_N<2> DPSNK1_2_N 1
R2832 R2883
1 1
R2882

SINK PORT 1
0.1UF Y1 TBT_GO2SX_BIDIR
X5R-CERM 0201 GPIO_2/GO2SX BI 14 26
100K 10K 10K
85 71 IN DP_TBTSNK0_ML_C_N<1> C2823 1 2 DP_TBTSNK0_ML_N<1> 26 85 85 26 DP_TBTSNK1_ML_P<1> E10
DPSNK1_1_P (FORCE_PWR) GPIO_3 W2 TBT_PWR_EN IN 20 5% 5% 5%
10% 16V D9 J4 1/16W 1/16W 1/16W
0.1UF X5R-CERM 0201 85 26 DP_TBTSNK1_ML_N<1> DPSNK1_1_N GPIO_4/WAKE_N_OD =TBT_WAKE_L 12 MF-LF MF-LF MF-LF

B 85 71 IN DP_TBTSNK0_ML_C_P<2> C2824 1 2 DP_TBTSNK0_ML_P<2> 26 85 85 26 DP_TBTSNK1_ML_P<0> E12

DPSNK1_0_P
GPIO_5/CIO_PLUG_EVENT AA2

AB1
TBT_CIO_PLUG_EVENT
OUT
OUT 20
2
402 402
2 2
402
B
10% 16V D11 GPIO_6/CIO_SDA_OD I2C_TBTRTR_SDA 26 85
0.1UF X5R-CERM 0201 85 26 DP_TBTSNK1_ML_N<0> DPSNK1_0_N AC2
GPIO_7/CIO_SCL_OD I2C_TBTRTR_SCL 26 85
85 71 IN DP_TBTSNK0_ML_C_N<2> C2825 1 2 DP_TBTSNK0_ML_N<2> 26 85
A4 P3
10% 16V 85 26 DP_TBTSNK1_AUXCH_P DPSNK1_AUX_P GPIO_8/EN_CIO_PWR_OD* (TBT_EN_CIO_PWR_L) TBT_PWR_REQ_L OUT 12
0.1UF X5R-CERM 0201 B3 M5
85 26 DP_TBTSNK1_AUXCH_N DPSNK1_AUX_N GPIO_9/OK2GO2SX_OD* TBT_GPIO_9 26 TBT_EN_CIO_PWR_L OUT 28
MAKE_BASE=TRUE 70 68 30 29 28 27 26 =PP3V3_S4_TBT
85 71 IN DP_TBTSNK0_ML_C_P<3> C2826 1 2
DP_TBTSNK0_ML_P<3> 26 85 T5 GPIO_14 T3 TBT_GPIO_14 26
10% 16V 71 OUT DP_TBTSNK1_HPD DPSNK1_HPD V5
0.1UF X5R-CERM 0201 GPIO_15 TBT_DDC_XBAR_EN_L OUT 26 31
=PP3V3_TBTLC_RTR 26 27 28 70
85 71 IN DP_TBTSNK0_ML_C_N<3> C2827 1 2 DP_TBTSNK0_ML_N<3> 26 85
R2831 1 R2885 1
1
0.1UF
10% 16V
TBT_A_R2D_C_P<0> G24
PA_CIO0_TX_P/DP_SRC_0_P PB_CIO2_TX_P/DP_SRC_0_P R24 TBT_B_R2D_C_P<0> 1 1 R2886
X5R-CERM 0201
100K
85 29 OUT OUT 30 85 R2889 R2894 10K 10K
TBT_A_R2D_C_N<0> E24 N24 TBT_B_R2D_C_N<0> 3.3K 3.3K
5% 85 29 OUT PA_CIO0_TX_N/DP_SRC_0_N PB_CIO2_TX_N/DP_SRC_0_N OUT 30 85 5% 5%
1/16W 5% 5% 1/16W 1/16W
DP_TBTSNK0_AUXCH_C_P C2828 1 2 DP_TBTSNK0_AUXCH_P

PORT0

PORT2
85 71 BI 26 85 MF-LF G22 R22 1/16W 1/16W MF-LF MF-LF
10% 16V 402
2
85 29 IN TBT_A_D2R_P<0> PA_CIO0_RX_P PB_CIO2_RX_P TBT_B_D2R_P<0> IN 30 85 MF-LF MF-LF 402
2 2
402
0.1UF X5R-CERM 0201 E22 N22 402 402
85 29 IN TBT_A_D2R_N<0> PA_CIO0_RX_N PB_CIO2_RX_N TBT_B_D2R_N<0> IN 30 85
2 2
85 71 BI DP_TBTSNK0_AUXCH_C_N C2829 1 2 DP_TBTSNK0_AUXCH_N 26 85 I2C_TBTRTR_SDA 29 26 TBT_A_DP_PWRDN
10% 16V K1 P1 85 26
0.1UF X5R-CERM 0201 29 OUT TBT_A_CONFIG1_BUF PA_CONFIG1/CIO_0_LSEO PB_CONFIG1/CIO_2_LSEO TBT_B_CONFIG1_BUF OUT 30 30 26 TBT_B_DP_PWRDN
TBT_A_CONFIG2_RC G4 H5 TBT_B_CONFIG2_RC I2C_TBTRTR_SCL TBT_A_HV_EN
29 IN PA_CONFIG2/CIO_0_LSOE PB_CONFIG2/CIO_2_LSOE IN 30 85 26 29 26

SNK1 AC Coupling 30 26 TBT_B_HV_EN

TBT_A_R2D_C_P<1> L24 W24 TBT_B_R2D_C_P<1>
85 29 OUT PA_CIO1_TX_P/DP_SRC_2_P PB_CIO3_TX_P/DP_SRC_2_P OUT 30 85
85 71 IN DP_TBTSNK1_ML_C_P<0> C2830 1 2 DP_TBTSNK1_ML_P<0> 26 85
J24 U24
10% 16V 85 29 OUT TBT_A_R2D_C_N<1> PA_CIO1_TX_N/DP_SRC_2_N PB_CIO3_TX_N/DP_SRC_2_N TBT_B_R2D_C_N<1> OUT 30 85 R2888 1 1
R2887
0.1UF X5R-CERM 0201
10K 10K

PORT1

PORT3
85 71 IN DP_TBTSNK1_ML_C_N<0> C2831 1 2 DP_TBTSNK1_ML_N<0> 26 85 85 29 IN TBT_A_D2R_P<1> L22
PA_CIO1_RX_P PB_CIO3_RX_P W22 TBT_B_D2R_P<1> IN 30 85 5% 5%
10% 16V J22 U22 1/16W 1/16W
0.1UF X5R-CERM 0201 85 29 IN TBT_A_D2R_N<1> PA_CIO1_RX_N PB_CIO3_RX_N TBT_B_D2R_N<1> IN 30 85 MF-LF MF-LF
402 402
2 2
85 71 IN DP_TBTSNK1_ML_C_P<1> C2832 1 2 DP_TBTSNK1_ML_P<1> 26 85 29 OUT TBT_A_LSTX N2
PA_LSTX/CIO_1_LSEO PB_LSTX/CIO_3_LSEO L6 TBT_B_LSTX OUT 30
10% 16V J6 G6
0.1UF X5R-CERM 0201 29 IN TBT_A_LSRX PA_LSRX/CIO_1_LSOE PB_LSRX/CIO_3_LSOE TBT_B_LSRX IN 30

85 71 IN DP_TBTSNK1_ML_C_N<1> C2833 1 2 DP_TBTSNK1_ML_N<1> 26 85

10% 16V
PORTS
0.1UF DP_TBTPA_ML_C_P<1> A16 A20 DP_TBTPB_ML_C_P<1>
X5R-CERM 0201 85 29 OUT PA_DPSRC_1_P PB_DPSRC_1_P OUT 30 85

DP_TBTPA_ML_C_N<1> B17 B21 DP_TBTPB_ML_C_N<1>

A 85 71 IN DP_TBTSNK1_ML_C_P<2> C2834
0.1UF
1 2

10% 16V
X5R-CERM 0201
DP_TBTSNK1_ML_P<2> 26 85
85 29

85 29
OUT

DP_TBTPA_ML_C_P<3> A18
PA_DPSRC_1_N

PA_DPSRC_3_P
PB_DPSRC_1_N

PB_DPSRC_3_P A22 DP_TBTPB_ML_C_P<3>

OUT 30 85

30 85
SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
OUT OUT PAGE TITLE
C2835 B19 B23
85 71 IN DP_TBTSNK1_ML_C_N<2>
0.1UF
1 2

10% 16V
X5R-CERM 0201
DP_TBTSNK1_ML_N<2> 26 85 85 29 OUT DP_TBTPA_ML_C_N<3> PA_DPSRC_3_N PB_DPSRC_3_N DP_TBTPB_ML_C_N<3> OUT 30 85
Thunderbolt Host (1 of 2)
F3 D1 DRAWING NUMBER SIZE
DP_TBTPA_AUXCH_C_P PA_AUX_P PB_AUX_P DP_TBTPB_AUXCH_C_P
85 71 IN DP_TBTSNK1_ML_C_P<3> C2836 1 2

10% 16V
DP_TBTSNK1_ML_P<3> 26 85
85 29

85 29
BI
DP_TBTPA_AUXCH_C_N F1
PA_AUX_N PB_AUX_N E2 DP_TBTPB_AUXCH_C_N
BI 30 85

30 85 Apple Inc. 051-0164 D

0.1UF BI BI
X5R-CERM 0201 REVISION
R
85 71 IN DP_TBTSNK1_ML_C_N<3> C2837 1 2 DP_TBTSNK1_ML_N<3> 26 85 29 IN DP_TBTPA_HPD H1
PA_DPSRC_HPD PB_DPSRC_HPD K3 DP_TBTPB_HPD IN 30 12.4.0
10% 16V
0.1UF X5R-CERM 0201
TBT_A_HV_EN G2 M1 TBT_B_HV_EN
NOTICE OF PROPRIETARY PROPERTY: BRANCH
29 26 OUT GPIO_0/PA_HV_EN/BYP0 GPIO_1/PB_HV_EN/BYP0 OUT 26 30
M3 L2 THE INFORMATION CONTAINED HEREIN IS THE
29 OUT TBT_A_CIO_SEL GPIO_10/PA_CIO_SEL/BYP1 GPIO_11/PB_CIO_SEL/BYP1 TBT_B_CIO_SEL OUT 30 PROPRIETARY PROPERTY OF APPLE INC.
85 71 BI DP_TBTSNK1_AUXCH_C_P C2838 1 2 DP_TBTSNK1_AUXCH_P 26 85 H3 L4 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
10% 16V 29 26 OUT TBT_A_DP_PWRDN GPIO_12/PA_DP_PWRDN/BYP2 GPIO_13/PB_DP_PWRDN/BYP2 TBT_B_DP_PWRDN OUT 26 30
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
0.1UF X5R-CERM 0201 28 OF 123
II NOT TO REPRODUCE OR COPY IT
85 71 BI DP_TBTSNK1_AUXCH_C_N C2839 1 2 DP_TBTSNK1_AUXCH_N 26 85
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
10% 16V For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.
0.1UF X5R-CERM 0201 IV ALL RIGHTS RESERVED 26 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

=PP1V05_TBTCIO_RTR 70
CRITICAL
D 70 =PP1V05_TBTLC_RTR
J10 OMIT_TABLE K11
???? mW (Single-Port)
2700 mW (Dual-Port)
D
??? mW (Single Port) VCC1P0_ON VCC1P0
J12 U2800 K15 EDP: 3000 mA
250 mW (Dual Port) VCC1P0_ON VCC1P0
EDP: 1000 mA C2900 1 1
C2910 1
C2911 1
C2912 1
C2913 J14
VCC1P0_ON CACTUSRIDGE4C VCC1P0 L10
C2940 1
C2941 1
C2942 1
C2943 1
C2944 1
C2945 1 1
C2905
10UF 1.0UF 1.0UF 1.0UF 1.0UF J16 FCBGA L14 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF
20% 20% 20% 20% 20% VCC1P0_ON (SYM 2 OF 2) VCC1P0 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V J8 M11 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM-X5R 2 2 X5R 2 X5R 2 X5R 2 X5R VCC1P0_ON VCC1P0 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 2 CERM-X5R
0402-1 0201-1 0201-1 0201-1 0201-1 K17 M15 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 0402-1
VCC1P0_ON VCC1P0
T15 N10
VCC1P0_ON VCC1P0
U14 N14
VCC1P0_ON VCC1P0
V7 P11
VCC1P0_ON VCC1P0
W8 P15
C2901 1 1 C2914 1 C2915 1 C2916 1 C2917 VCC1P0_ON VCC1P0
10UF 1.0UF 1.0UF 1.0UF 1.0UF VCC1P0 R10
20% 20% 20% 20% 20% G10
VCC1P0_PE

VCC
6.3V 6.3V 6.3V 6.3V 6.3V R14
CERM-X5R 2 2 X5R 2 X5R 2 X5R 2 X5R G12 VCC1P0
0402-1 0201-1 0201-1 0201-1 0201-1 VCC1P0_PE T11
G14 VCC1P0
VCC1P0_PE U10
G16 VCC1P0
VCC1P0_PE V11
G18 VCC1P0
VCC1P0_PE W10
=PP3V3_TBTLC_RTR 26 28 70
H19 VCC1P0
VCC1P0_PE ??? mW (Single-Port)
K19
VCC1P0_PE M7 250 mW (Dual-Port)
M19 VCC3P3
VCC1P0_PE P7 EDP: 240 mA
P19 VCC3P3
VCC1P0_PE T7
T19 VCC3P3 C2970 1
C2971 1
C2972 1
C2973 1
C2974 1 1
C2960
VCC1P0_PE 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF
V15 L18 20% 20% 20% 20% 20% 20%
VCC1P0_PE VCC3P3_CIO 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
V19 N18 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 2 CERM-X5R
VCC1P0_PE VCC3P3_CIO 0201-1 0201-1 0201-1 0201-1 0201-1 0402-1
W12 R18
VCC1P0_PE VCC3P3_CIO
W14
VCC1P0_PE H11
VCC3P3_DP
H13

C G8

H9
VCC1P0_DPAUX
VCC1P0_DPAUX
VCC3P3_DP
VCC3P3_DP H15 C
H17
VCC3P3_DP
AD1 H7
VSS VCC3P3_DPAUX
K13
VSS
K9
VSS
L12 =PP3V3_S4_TBT
VSS 26 28 29 30 68 70
L16 K7
VSS VCC3P3_POC EDP: 10 mA
L8
VSS
M13 C22
VSS VSSPE C2990 1
M17
VSS VSSPE C24 1.0UF
20%
M9 C4 6.3V
VSS VSSPE X5R 2
N12 C6 0201-1
VSS VSSPE
N16 C8
VSS VSSPE
N8 D21
VSS VSSPE
P13 D23
VSS VSSPE
P17 E4
VSS VSSPE
P9 F11
VSS VSSPE
R12 F13
VSS VSSPE
R16 F15
VSS VSSPE
R8 F17
VSS VSSPE
T13 F19
VSS VSSPE
T17 F21
VSS VSSPE
T9 F23
VSS VSSPE
U12 F5
VSS VSSPE

GND
U16 F7
VSS VSSPE

B U8

V9
VSS
VSS
VSSPE
VSSPE
F9

G20
B
H21
VSSPE
A2 H23
VSSPE VSSPE
A24 J18
VSSPE VSSPE
AA14 J20
VSSPE VSSPE
AA20 K21
VSSPE VSSPE
AA22 K23
VSSPE VSSPE
AA8 L20
VSSPE VSSPE
AB11 M21
VSSPE VSSPE
AB17 M23
VSSPE VSSPE
AB7 N20
VSSPE VSSPE
AC10 P21
VSSPE VSSPE
AC12 P23
VSSPE VSSPE
AC14 R20
VSSPE VSSPE
AC16 T21
VSSPE VSSPE
AC18 T23
VSSPE VSSPE
AC20 U18
VSSPE VSSPE
AC22 V13
VSSPE VSSPE
AC4 V17
VSSPE VSSPE
AC6 V21
VSSPE VSSPE
AC8 V23
VSSPE VSSPE
B1 Y11
VSSPE VSSPE
B7 Y13
VSSPE VSSPE
C10 Y15
VSSPE VSSPE
C12 Y17
VSSPE VSSPE
A C14

C16
VSSPE
VSSPE
VSSPE
VSSPE
Y19

Y21 SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A

PAGE TITLE
C18 Y23

C20
VSSPE
VSSPE
VSSPE
VSSPE Y9 Thunderbolt Host (2 of 2)
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
29 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
EDP current / power consumption figures from CR DG v0.57, IBL doc #472455.
IV ALL RIGHTS RESERVED 27 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
- =PPVIN_SW_TBTBST (8-13V Boost Input)
- =PP15V_TBT_REG (15V Boost Output)
- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)
- =PP3V3_TBT_FET (3.3V FET Output)
- =PP3V3_S0_TBTPWRCTL
- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)
- =PP1V05_TBT_FET (1.05V FET Output)

Signal aliases required by this page:

D - =TBT_CLKREQ_L
- =TBT_RESET_L
D
BOM options provided by this page:
TBTBST:Y - Stuffs 15V boost circuitry.

Supervisor & CLKREQ# Isolation

=PP3V3_TBTLC_RTR 26 27 28 70

C C
70 =PP3V3_S0_TBTPWRCTL

C3000 1
CRITICAL 1
R3007
1

0.1UF
Q3040 1
R3040 10%
25V
VDD 100K
5%
SSM3K15AMFVAPE 10K 2
U3000 1/16W
G 1

X5R
5% 402 MF-LF
VESM 1/16W
SLG4AP016V 2
402
MF-LF
2
402 TDFN PP1V05_TBTLC 70 82

+ SENSE
2
D

26 IN TBT_EN_LC_PWR - 0.7V
3

DLY
RESET* 4 TBT_PCIE_RESET_L OUT 26
20 IN =TBT_RESET_L 3 MR*
DLY = 60 ms +/- 20%
Platform(PCIe) Reset
TBT_EN_LC_ISOL 6 EN
=TBT_CLKREQ_L IN 26
11 OUT TBT_CLKREQ_L 8 OUT
(OD) IN 7 TBT_CLKREQ_ISOL_L
Pull-up provided by SB page. MAKE_BASE=TRUE
THRM
GND PAD
5

TBT "POC" Power-up Reset

Intel investigating whether RC is sufficient.

B 3.3V TBT "LC" Switch 70 68 30 29 27 26 =PP3V3_S4_TBT

B
U3010 SMC_DELAYED_PWRGD IN 44 45 69

=PP3V3_S0_P3V3TBTFET TPS22924 =PP3V3_TBTLC_FET CRITICAL

1
70 70
CSP
A2 A1 Max Current = 2A (85C) Pull-up: R2810
VDD =PP3V3_S0_PCH_GPIO 11 12 14 70
B2 VIN VOUT B1
R3011 2 SENSE U3030 RESET* 6 TBT_PWR_ON_POC_RST_L
36.5K2
CRITICAL U3010 TPS3808
OUT 26

1 TBT_EN_LC_RC3V3 C2 ON (IPU)
TBTPOCRST_CT 3 QFN 4 TBTPOCRST_MR_L 1
GND Part TPS22924C CT MR* R3030
C3010 1 1% THRM
1/16W GND PAD Q3025 100K
C1

1UF

5
MF-LF 1 Type Load Switch
10% 402 C3011 1 C3031 C3030 1 SSM6N37FEAPE 5%

G
6.3V 1/16W

7
CERM 2 1UF 0.0047UF 0.1UF SOT563 MF-LF
402 10% R(on) 18.5 mOhm Typ 10% 10% TPS3808G25 2
402
6.3V
CERM 2 @ 2.5V 25.8 mOhm Max 2
25V 25V
2 Vt = 2.33V +/- 2%

S
CERM X5R TBT_SW_RESET_L
402 IN 14
0402 402
Delay = 27.3ms

4
C3025 1
330PF
10%
50V
X7R-CERM 2
0402

1.05V TBT "LC" Switch 70 28 =PP1V05_S0_P1V05TBTFET 1.05V TBT "CIO" Switch

=PP3V3_TBTLC_RTR
U3015 70 28 27 26
U3020
=PP1V05_S0_P1V05TBTFET TPS22924 =PP1V05_TBTLC_FET 70 TPS22920 =PP1V05_TBTCIO_FET
70 28 CSP 70
A2 A1 Max Current = 2A (85C) R3020 1 A2
CSP
A1 Max Current = 4A (85C)
B2 VIN VOUT B1 100K
B2 B1
5% VIN VOUT
R3016 U3015
0
CRITICAL 1/16W
MF-LF C2 C1 U3020
A C3015 1
1
5%
2 TBT_EN_LC_RC1V05 C2 ON
GND Part TPS22924C
402
2

TBT_EN_CIO_PWR D2 ON
CRITICAL
Part TPS22920 SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
1/16W NOSTUFF PAGE TITLE
C1

1UF MF-LF Type Load Switch GND

10%
6.3V
402 C3016
1UF
1
Type Load Switch
Thunderbolt Power Support

D1
CERM 2
R(on) 20.3 mOhm Typ D 6 C3020 1
402 10%
6.3V Q3025 1UF R(on) 8 mOhm Typ DRAWING NUMBER SIZE
2
CERM
402
@ 1.0V 28.6 mOhm Max SSM6N37FEAPE
SOT563
10%
6.3V
2
@ 1.05V 11.5 mOhm Max
Apple Inc. 051-0164 D
CERM
402 REVISION
R
12.4.0
2 G S 1
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
26 IN TBT_EN_CIO_PWR_L PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 30 OF 123
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 28 OF 86

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V/HV Power MUX 70 68 30 29 28 27 26 =PP3V3_S4_TBT

V3P3 must be S4 to support

C3220 C3221 R3229 1
TABLE_ALT_HEAD

1 1 1
wake from Thunderbolt devices. PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: R3227
PART NUMBER 0.1UF 0.1UF 10K 100K
=PP3V3_S4_TBTAPWRSW 10% 10%
70 TABLE_ALT_ITEM

6.3V 6.3V 5% 5%
Nominal Min Max 311S0596 311S0593 ALL TI Alternate CERM-X5R 2 CERM-X5R 2 1/20W 1/20W

15
0201 0201 MF MF

3
IV3P3 1100mA 1030mA 1200mA TABLE_ALT_ITEM

2
201 201
2
CRITICAL CRITICAL 128S0398 128S0220 ALL 3.3V INPUT CAP
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) VDD
C3287 1
C3280 1 1
C3281 TBT_A_BIAS 29

100UF 22UF 0.1UF IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W) CRITICAL VOLTAGE=3.3V
20% 20% 20% U3220
6.3V 10V
6.3V
POLY-TANT
2 X5R-CERM-1 2 2 CERM CBTL05023 1
C3225

D
CASE-B2-SM 603 402
19

20 V3P3
V3P3OUT 18
NC 26 IN TBT_A_CIO_SEL 1
BIASIN
HVQFN
BIASOUT 24
2
0.1UF
10%
6.3V
CERM-X5R
D
=PPHV_SW_TBTAPWRSW 12 PPHV_SW_TBTAPWR DP_AUXIO_EN 2 0201
70 30 18 11 IN AUXIO_EN
OUT MIN_LINE_WIDTH=0.38 MM
18.9V Max 6 14 MIN_NECK_WIDTH=0.20 MM C3230 1 2
7
VHV VOLTAGE=15V 85 26 BI DP_TBTPA_AUXCH_C_N 10% 6.3V 85 DP_TBTPA_AUXCH_N AUX-
7 0.1UF CERM-X5R
0201
1
1
C3211 85 26 BI DP_TBTPA_AUXCH_C_P
C3231
85 DP_TBTPA_AUXCH_P 8 AUX+ AUXIO- 23 DP_A_AUXCH_DDC_N 29 85
C3215 1
C3210 CRITICAL 0.1UF
1 2
22 DP_A_AUXCH_DDC_P
4.7UF 0.1UF 10% 6.3V
4
AUXIO+ 29 85
10% 10%
U3210 10%
50V
0.1UF CERM-X5R
0201 31 BI DP_TBTPA_DDC_DATA DDC_DAT
25V 50V CD3210A0RGP 2 X7R 5
TBT: RX_1 Bias Sink
X5R-CERM 2 2 X7R 603-1 31 IN DP_TBTPA_DDC_CLK DDC_CLK
QFN
0603 603-1
16 RSVD RSVD 15 26 TBT_A_CONFIG1_BUF 16 CA_DETOUT CA_DET 18 TBT_A_CONFIG1_RC 29
OUT
C3232 1 2
11
68 IN =TBTAPWRSW_EN 5 EN ISET_V3P3 8 TBTAPWRSW_ISET_V3P3 85 26 IN DP_TBTPA_ML_C_P<1> 20% 6.3V 85 DP_TBTPA_ML_P<1> DP+
0.22UF X5R 0201
DP_TBTPA_ML_C_N<1> DP_TBTPA_ML_N<1> 10 DP- 19 DP_A_LSX_ML_P<1>
85 26 IN 85 DPMLO+ 29 85
26 IN TBT_A_HV_EN 11 HV_EN ISET_S0 10 TBTAPWRSW_ISET_S0 C3233 1 2
20
20% 6.3V
14
DPMLO- DP_A_LSX_ML_N<1> 29 85
0.22UF X5R 0201 26 IN TBT_A_LSTX LSTX
68 30 IN =TBT_S0_EN 17 S0 ISET_S3 9 TBTAPWRSW_ISET_S3 TBT: LSX_A_R2P/P2R (P/N)
70 68 30 29 28 27 26 =PP3V3_S4_TBT TBT_A_LSRX_UNBUF 13 LSRX
TBTHV:P15V TBTHV:P15V
GND THRM
R3210 1
PAD 1 1 TBT_A_DP_PWRDN 6 DP_PD
12V: See R3211 R3212 CRITICAL 26 IN
1

3
4

21
22.6K 22.6K 36.5K U3260 12 17
below 1% 1% 1% 26 OUT DP_TBTPA_HPD HPDOUT HPD TBT_A_HPD 29
1/16W 1/16W 1/16W 5 74AUP1T97GM
MF-LF MF-LF MF-LF SOT886
402
2 2
402
2
402 GND THMPAD
R3226 1
TBT_A_LSRX 4 1 1
TBTAPWRSW_ISET_S3_R
26 OUT R3228

25
6 1M 100K
TBTAPWRSW_ISET_S0_R 3 5% 5%
1 C3260 2 1/20W 1/20W
TBTHV:P15V TBTHV:P15V MF MF
1 1
0.1UF 201
R3213 R3214 10% 2 2 201
16V
22.6K 22.6K Two Rs in series required by CD3210 2 X5R-CERM
1% 1% for single-fault protection(S0,S3 only) 0201
1/16W 1/16W
MF-LF MF-LF
402 2 2 402

C Thunderbolt Connector A C
For 12V systems: L3200
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION FERR-120-OHM-3A C3205
1 2 PP3V3RHV_SW_TBTAPWR
0.01UF
114S0338 2 RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF R3210,R3213 TBTHV:P12V MIN_LINE_WIDTH=0.38 MM TBTACONN_1_C 1 2
0603 MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.38 MM GND_VOID=TRUE
VOLTAGE=15V MIN_NECK_WIDTH=0.20 MM 10%
114S0338 2 RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF R3211,R3214 TBTHV:P12V C3200 1
R3201 VOLTAGE=18.9V 25V (Both C’s)
(0-18.9V)
0.01UF
10%
12 X5R-CERM
0201
C3270 1 2

50V
TBTACONN_20_RC 1 2 DP Dir TBT Dir 20% 6.3V TBT_A_R2D_C_P<0> IN 26 85
Nominal Min Max X7R-CERM 2 MIN_LINE_WIDTH=0.38 MM 0.22UF X5R 0201
MIN_NECK_WIDTH=0.20 MM 5% 85 TBT_A_R2D_P<0> TBT_A_R2D_C_N<0> IN 26 85
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum) 0402
VOLTAGE=18.9V 1/20W C3271 1 2
1
C3201 MF
201
85 TBT_A_R2D_N<0>
0.22UF
20% 6.3V
X5R 0201
0.01UF
10%
GND_VOID=TRUE 50V TBT: TX_0
2 X7R-CERM CRITICAL GND_VOID=TRUE GND_VOID=TRUE
(Both C’s) 0402 1 1
TBT Dir DP Dir R3270 R3271
C3274 1 2

85 26 OUT TBT_A_D2R_N<0> 20% 4V 85 TBT_A_D2R_C_P<0> 470K 470K

0.47UF

46
45
44
43
42
41
CERM-X5R-1 201 5% 5%
85 26 OUT TBT_A_D2R_P<0> 85 TBT_A_D2R_C_N<0> 1/20W 1/20W
C3275 1 2
MF MF
20% 4V GND_VOID=TRUE GND_VOID=TRUE 2
201
2
201
0.47UF CERM-X5R-1 201 SHLD
1 1
R3294 R3295
NOTE: Polarity Swapped for layout! 1K 1K J3200 C3206
5%
1/20W
5%
1/20W
DUAL-MDP-K70 0.01UF
MF MF 2 HPD F-ANG-TH GND0 1
201 201 TBTACONN_7_C 1 2
2 2 4 CONFIG1 ML_LANE0P 3 MIN_LINE_WIDTH=0.38 MM
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE MIN_NECK_WIDTH=0.20 MM
6 CONFIG2 ML_LANE0N 5 VOLTAGE=18.9V
10%
R3278 470K 1 2 (0-18.9V) 25V
5% 1/20W 8 GND2 GND1 7 X5R-CERM
C3278 1 2
MF 201
10 9
0201
85 26 IN DP_TBTPA_ML_C_P<3> 20% 6.3V 85 DP_TBTPA_ML_P<3> ML_LANE3P ML_LANE1P DP_A_LSX_ML_P<1> 29 85
0.22UF X5R 0201

B 85 26 IN DP_TBTPA_ML_C_N<3>
C3279 1 2

20% 6.3V
85 DP_TBTPA_ML_N<3>
TBT: Terminated
12
14
ML_LANE3N
GND4
ML_LANE1N
GND3
11
13
DP_A_LSX_ML_N<1> 29 85
B
0.22UF X5R 0201 R3279 470K 1 2
16 TBT: LSX_R2P/P2R (P/N)
5% 1/20W AUX_CHP ML_LANE2P 15
MF 201
29 TBT_A_BIAS 18 AUX_CHN ML_LANE2N 17
20 DP_PWR 19
PORT A RETURN NOTE: Polarity Swapped for layout!
R3298 1
1
R3299 SHLD GND_VOID=TRUE
2.2K 2.2K CRITICAL (Both C’s)
5% 5%
C3272

65
52
51
50
49
48
47
1 2
GND_VOID=TRUE 1/20W 1/20W GND_VOID=TRUE
MF MF 20% 6.3V TBT_A_R2D_C_N<1> IN 26 85
(Both C’s) 201 201 (Both D’s) 0.22UF X5R 0201
2 2 85 TBT_A_R2D_P<1> TBT_A_R2D_C_P<1>
GND_VOID=TRUE GND_VOID=TRUE
C3276 1 2 D3298 A K C3273 1 2 IN 26 85

85 26 OUT TBT_A_D2R_N<1> 20% 4V 85 TBT_A_D2R_C_P<1> BAR90-02LRH TSLP-2-7 85 TBT_A_D2R1_AUXDDC_P 85 TBT_A_R2D_N<1> 20% 6.3V
0.47UF CERM-X5R-1 201 0.22UF X5R 0201
85 26 OUT TBT_A_D2R_P<1> 85 TBT_A_D2R_C_N<1>
D3299 85 TBT_A_D2R1_AUXDDC_N
C3277 1 2 A K
TBT: TX_1
20% 4V BAR90-02LRH TSLP-2-7 GND_VOID=TRUE GND_VOID=TRUE
0.47UF CERM-X5R-1 201
1 1
CRITICAL J16:514-0824 / J17:514-0831 R3272 R3273
NOTE: Polarity Swapped for layout! 470K 470K
L3298 5% 5%
650NH-5%-0.430MA-0.52OHM 1/20W 1/20W
MF MF
GND_VOID=TRUE 201 201
85 29 DP_A_AUXCH_DDC_P 2 1 2 2

85 29 DP_A_AUXCH_DDC_N 0603
NO_XNET_CONNECTION=TRUE

CRITICAL 470k R’s for ESD protection

C3298 1 1
C3299 L3299
30PF 30PF on AC-coupled signals.
5% 5% 650NH-5%-0.430MA-0.52OHM
50V 50V
C0G-NP0 2 2 C0G-NP0 2 1
0402 0402
GND_VOID=TRUE
0603
NO_XNET_CONNECTION=TRUE

A 29 TBT_A_HPD
SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
29 TBT_A_CONFIG1_RC DP Source must pull PAGE TITLE

26 OUT TBT_A_CONFIG2_RC
C3202
0.01UF
10%
1
down HPD input with Thunderbolt Connector A
25V greater than or equal DRAWING NUMBER SIZE
2
1 1 1
X5R-CERM
0201 to 100K (DPv1.1a).
Apple Inc. 051-0164 D
R3252 R3251 C3294 1 1
C3295 R3241 REVISION
1M 1M 100K R
5%
1/20W
5%
1/20W
330PF
10%
330PF
10%
5%
1/20W
Sink HPD range: 12.4.0
16V 16V
MF MF X7R-CERM 2 2 X7R-CERM MF High: 2.0 - 5.0V NOTICE OF PROPRIETARY PROPERTY: BRANCH
201 201 0201 0201 201
2 2 2
Low: 0 - 0.8V THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
32 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 29 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V/HV Power MUX 70 68 30 29 28 27 26 =PP3V3_S4_TBT

V3P3 must be S4 to support

C3320 C3321 R3329 1
1 1 1
wake from Thunderbolt devices. R3327
0.1UF 0.1UF 10K 100K
=PP3V3_S4_TBTBPWRSW 10% 10%
70 6.3V 6.3V 5% 5%
Nominal Min Max CERM-X5R 2 CERM-X5R 2 1/20W 1/20W

15
0201 0201 MF MF

3
IV3P3 1100mA 1030mA 1200mA 2
201 201
2
CRITICAL CRITICAL
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) VDD
C3387 1
C3380 1 1
C3381 TBT_B_BIAS 30

100UF 22UF 0.1UF IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W) CRITICAL VOLTAGE=3.3V
20% 20% 20% U3320
6.3V 10V
6.3V
POLY-TANT
2 X5R-CERM-1 2 2 CERM CBTL05023 1
C3325

D
CASE-B2-SM 603 402
19

20 V3P3
V3P3OUT 18
NC 26 IN TBT_B_CIO_SEL 1
BIASIN
HVQFN
BIASOUT 24
2
0.1UF
10%
6.3V
CERM-X5R
D
=PPHV_SW_TBTBPWRSW 12 PPHV_SW_TBTBPWR DP_AUXIO_EN 2 0201
70 29 18 11 IN AUXIO_EN
OUT MIN_LINE_WIDTH=0.38 MM
18.9V Max 6 14 MIN_NECK_WIDTH=0.20 MM C3330 1 2
7
VHV VOLTAGE=15V 85 26 BI DP_TBTPB_AUXCH_C_N 10% 6.3V 85 DP_TBTPB_AUXCH_N AUX-
7 0.1UF CERM-X5R
0201
1
C3311 85 26 BI DP_TBTPB_AUXCH_C_P
C3331
85 DP_TBTPB_AUXCH_P 8 AUX+ AUXIO- 23 DP_B_AUXCH_DDC_N 30 85
C3315 1 1
C3310 CRITICAL 0.1UF
1 2
22 DP_B_AUXCH_DDC_P
4.7UF 0.1UF 10% 6.3V
4
AUXIO+ 30 85
10% 10%
U3310 10%
50V
0.1UF CERM-X5R
0201 31 BI DP_TBTPB_DDC_DATA DDC_DAT
25V 50V CD3210A0RGP 2 X7R 5
TBT: RX_1 Bias Sink
X5R-CERM 2 2 X7R 603-1 31 IN DP_TBTPB_DDC_CLK DDC_CLK
QFN
0603 603-1
16 RSVD RSVD 15 26 TBT_B_CONFIG1_BUF 16 CA_DETOUT CA_DET 18 TBT_B_CONFIG1_RC
OUT 30

C3332 1 2
11
68 IN =TBTBPWRSW_EN 5 EN ISET_V3P3 8 TBTBPWRSW_ISET_V3P3 85 26 IN DP_TBTPB_ML_C_P<1> 20% 6.3V 85 DP_TBTPB_ML_P<1> DP+
0.22UF X5R 0201
DP_TBTPB_ML_C_N<1> DP_TBTPB_ML_N<1> 10 DP- 19 DP_B_LSX_ML_P<1>
85 26 IN 85 DPMLO+ 30 85
26 IN TBT_B_HV_EN 11 HV_EN ISET_S0 10 TBTBPWRSW_ISET_S0 C3333 1 2
20
20% 6.3V
14
DPMLO- DP_B_LSX_ML_N<1> 30 85
0.22UF X5R 0201 26 IN TBT_B_LSTX LSTX
68 29 IN =TBT_S0_EN 17 S0 ISET_S3 9 TBTBPWRSW_ISET_S3 TBT: LSX_B_R2P/P2R (P/N)
70 68 30 29 28 27 26 =PP3V3_S4_TBT TBT_B_LSRX_UNBUF 13 LSRX
TBTHV:P15V TBTHV:P15V
GND THRM
R3310 1
PAD 1 1 TBT_B_DP_PWRDN 6 DP_PD
12V: See R3311 R3312 CRITICAL 26 IN
1

3
4

21
22.6K 22.6K 36.5K U3360 12 17
below 1% 1% 1% 26 OUT DP_TBTPB_HPD HPDOUT HPD TBT_B_HPD 30
1/16W 1/16W 1/16W 5 74AUP1T97GM
MF-LF MF-LF MF-LF SOT886
402
2 2
402
2
402 GND THMPAD
R3326 1
TBT_B_LSRX 4 1 1
TBTBPWRSW_ISET_S3_R
26 OUT R3328

25
6 1M 100K
TBTBPWRSW_ISET_S0_R 3 5% 5%
1 C3360 2 1/20W 1/20W
TBTHV:P15V TBTHV:P15V MF MF
1 1
0.1UF 201
R3313 R3314 10% 2 2 201
16V
22.6K 22.6K Two Rs in series required by CD3210 2 X5R-CERM
1% 1% for single-fault protection(S0,S3 only) 0201
1/16W 1/16W
MF-LF MF-LF
402 2
2 402

C Thunderbolt Connector B C
For 12V systems: L3300
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION FERR-120-OHM-3A C3305
1 2 PP3V3RHV_SW_TBTBPWR
0.01UF
114S0338 2 RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF R3310,R3313 TBTHV:P12V MIN_LINE_WIDTH=0.38 MM TBTBCONN_1_C 1 2
0603 MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.38 MM GND_VOID=TRUE
VOLTAGE=15V MIN_NECK_WIDTH=0.20 MM
114S0338 2 R3311,R3314 TBTHV:P12V C3300 1 10% (Both C’s)
RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF
R3301 VOLTAGE=18.9V
(0-18.9V) 25V
0.01UF
10%
12 X5R-CERM
0201
C3370 1 2

50V
TBTBCONN_20_RC 1 2 DP Dir TBT Dir 20% 6.3V TBT_B_R2D_C_P<0> IN 26 85
Nominal Min Max X7R-CERM 2 MIN_LINE_WIDTH=0.38 MM 0.22UF X5R 0201
MIN_NECK_WIDTH=0.20 MM 5% 85 TBT_B_R2D_P<0> TBT_B_R2D_C_N<0> IN 26 85
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum) 0402
VOLTAGE=18.9V 1/20W C3371 1 2
1
C3301 MF
201
85 TBT_B_R2D_N<0>
0.22UF
20% 6.3V
X5R 0201
0.01UF
10%
GND_VOID=TRUE 50V TBT: TX_0
2 X7R-CERM CRITICAL GND_VOID=TRUE GND_VOID=TRUE
(Both C’s) 0402 1 1
TBT Dir DP Dir R3370 R3371
C3374 1 2

85 26 OUT TBT_B_D2R_N<0> 20% 4V 85 TBT_B_D2R_C_P<0> 470K 470K

0.47UF

58
57
56
55
54
53
CERM-X5R-1 201 5% 5%
85 26 OUT TBT_B_D2R_P<0> 85 TBT_B_D2R_C_N<0> 1/20W 1/20W
C3375 1 2
MF MF
20% 4V GND_VOID=TRUE GND_VOID=TRUE 2
201
2
201
0.47UF CERM-X5R-1 201 SHLD
1 1
R3394 R3395
NOTE: Polarity Swapped for Layout! 1K 1K J3200 C3306
5%
1/20W
5%
1/20W
DUAL-MDP-K70 0.01UF
MF MF 22 HPD F-ANG-TH GND0 21
201 201 TBTBCONN_7_C 1 2
2 2 24 CONFIG1 ML_LANE0P 23 MIN_LINE_WIDTH=0.38 MM
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE MIN_NECK_WIDTH=0.20 MM
26 CONFIG2 ML_LANE0N 25 VOLTAGE=18.9V
10%
R3378 470K 1 2 (0-18.9V) 25V
5% 1/20W 28 GND2 GND1 27 X5R-CERM
C3378 1 2
MF 201
30 29
0201
85 26 IN DP_TBTPB_ML_C_P<3> 20% 6.3V 85 DP_TBTPB_ML_P<3> ML_LANE3P ML_LANE1P DP_B_LSX_ML_P<1> 30 85
0.22UF X5R 0201

B 85 26 IN DP_TBTPB_ML_C_N<3>
C3379 1 2

20% 6.3V
85 DP_TBTPB_ML_N<3>
TBT: Terminated
32
34
ML_LANE3N
GND4
ML_LANE1N
GND3
31
33
DP_B_LSX_ML_N<1> 30 85
B
0.22UF X5R 0201 R3379 470K 1 2 TBT: LSX_R2P/P2R (P/N)
5% 1/20W 36 AUX_CHP ML_LANE2P 35
MF 201
30 TBT_B_BIAS 38 AUX_CHN ML_LANE2N 37
40 DP_PWR 39
PORT B RETURN NOTE: Polarity Swapped for Layout!
R3398 1
1
R3399 SHLD GND_VOID=TRUE
2.2K 2.2K CRITICAL (Both C’s)
5% 5%
C3372

65
64
63
62
61
60
59
1 2
GND_VOID=TRUE 1/20W 1/20W GND_VOID=TRUE
MF MF 20% 6.3V TBT_B_R2D_C_N<1> IN 26 85
(Both C’s) 201 201 (Both D’s) 0.22UF X5R 0201
2 2 85 TBT_B_R2D_P<1> TBT_B_R2D_C_P<1>
GND_VOID=TRUE GND_VOID=TRUE
C3376 1 2 D3398 A K C3373 1 2 IN 26 85

85 26 OUT TBT_B_D2R_N<1> 20% 4V 85 TBT_B_D2R_C_P<1> BAR90-02LRH TSLP-2-7 85 TBT_B_D2R1_AUXDDC_P 85 TBT_B_R2D_N<1> 20% 6.3V
0.47UF CERM-X5R-1 201 0.22UF X5R 0201
85 26 OUT TBT_B_D2R_P<1> 85 TBT_B_D2R_C_N<1> D3399 85 TBT_B_D2R1_AUXDDC_N
C3377 1 2 A K
TBT: TX_1
20% 4V BAR90-02LRH TSLP-2-7 GND_VOID=TRUE GND_VOID=TRUE
0.47UF CERM-X5R-1 201
1 1
CRITICAL J16:514-0824 / J17:514-0831 R3372 R3373
NOTE: Polarity Swapped for Layout! 470K 470K
L3398 5% 5%
650NH-5%-0.430MA-0.52OHM 1/20W 1/20W
MF MF
GND_VOID=TRUE 201 201
85 30 DP_B_AUXCH_DDC_P 2 1 2 2

85 30 DP_B_AUXCH_DDC_N 0603
NO_XNET_CONNECTION=TRUE

CRITICAL 470k R’s for ESD protection

C3398 1 1
C3399 L3399
30PF 30PF on AC-coupled signals.
5% 5% 650NH-5%-0.430MA-0.52OHM
50V 50V
C0G-NP0 2 2 C0G-NP0 2 1
0402 0402
GND_VOID=TRUE
0603
NO_XNET_CONNECTION=TRUE

A 30 TBT_B_HPD
SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
30 TBT_B_CONFIG1_RC DP Source must pull PAGE TITLE

26 OUT TBT_B_CONFIG2_RC
C3302
0.01UF
10%
1
down HPD input with Thunderbolt Connector B
25V greater than or equal DRAWING NUMBER SIZE
2
1 1 1
X5R-CERM
0201 to 100K (DPv1.1a).
Apple Inc. 051-0164 D
R3352 R3351 C3394 1 1
C3395 R3341 REVISION
1M 1M 100K R
5%
1/20W
5%
1/20W
330PF
10%
330PF
10%
5%
1/20W
Sink HPD range: 12.4.0
16V 16V
MF MF X7R-CERM 2 2 X7R-CERM MF High: 2.0 - 5.0V NOTICE OF PROPRIETARY PROPERTY: BRANCH
201 201 0201 0201 201
2 2 2
Low: 0 - 0.8V THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
33 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 30 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

Dual-Port Host DDC Crossbar

C 70 47 40 =PP3V3_S0_DP
C
1
R3402 1
R3404

VCC 13
2.2K 2.2K
1% 1%
1 C3400 1/20W
MF 1/20W
0.1UF MF
2 201 2 201
U3400 2
20%
10V
CERM 1 1
16
TS3DS10224 402 R3401 R3403
ENA QFN 2.2K 2.2K
1% 1%
1 1/20W 1/20W
29 OUT
DP_TBTPA_DDC_CLK INA+ OUTA1+ 20 MF MF
2 CRITICAL 201 201
29 BI
DP_TBTPA_DDC_DATA INA- OUTA1- 19 2 2

OUTA0+ 18 DP_TBTSNK0_DDC_CLK IN 71

OUTA0- 17 DP_TBTSNK0_DDC_DATA BI 71

14 SAI SAO 15
10 ENB

30 DP_TBTPB_DDC_CLK 3 INB+ OUTB1+ 6

OUT
30 DP_TBTPB_DDC_DATA 4 INB- OUTB1- 7
BI

OUTB0+ 8 DP_TBTSNK1_DDC_CLK IN 71

OUTB0- 9 DP_TBTSNK1_DDC_DATA BI 71

26 IN TBT_DDC_XBAR_EN_L 12 SBI SBO 11

THRM
PAD
GND
B

21
B

A SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
PAGE TITLE

TBT DDC Crossbar

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

CHANNEL
N-TYPE

18.4 MOHM @3.3V

AIRPORT
RDS(ON)

LOADING
2 A (EDP)
BLUETOOTH
CRITICAL
U3510 L3502
D TPS22924
CSP
FERR-220-OHM-2.5A
PP3V3_S4_AP_FLT
D
70 45 32 =PP3V3_S4_AP A2 A1 45 PP3V3_S4_AP_FET 1 2 32

B2 VIN VOUT B1 MIN_LINE_WIDTH=0.6 mm 0603 MIN_LINE_WIDTH=0.6 mm 514S0335

MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm CRITICAL
VOLTAGE=3.3V VOLTAGE=3.3V
CRITICAL
AP_PWR_EN C2 ON
1 C3502 1 C3503 1 C3504 J3500
45 32 IN
GND
0.1UF 0.1UF 10UF SSD-K99
10% 10% 20%
2 16V
X7R-CERM 2 16V
X7R-CERM 2 6.3V
X5R
F-RT-SM1

C1
0402 0402 603
1

PLACE_NEAR=J3500.4:7mm
45 44 BI AP_EVENT_L 2

0.1UF 3
77 13 IN PCIE_AP_R2D_C_N C3505 1 2
0201 10%
CERM-X5R
6.3V 77 PCIE_AP_R2D_N 4

C3506 1 0.1UF 77 PCIE_AP_R2D_P 5

77 13 IN PCIE_AP_R2D_C_P 2
6
0201 10%
CERM-X5R
6.3V
PLACE_NEAR=J3500.5:7mm
77 11 IN PCIE_CLK100M_AP_N 7

77 11 IN PCIE_CLK100M_AP_P 8
9

77 13 OUT PCIE_AP_D2R_P 10

77 13 OUT PCIE_AP_D2R_N 11
12

70 32 =PP3V3_G3H_BT 32 AP_WAKE_L 13

CRITICAL 32 AP_RESET_CONN_L 14

32 AP_CLKREQ_Q_L
15
CRITICAL
BT_RESET_MASK_L U3540 L3501
FERR-220-OHM-2.5A
80 32 USB_BT_MUX_N
16
20
TPS22924B 80 32 USB_BT_MUX_P
17
CSP PP3V3_G3H_BT_FLT
BT_RESET_MASK_L GATES BT_PWR_RST_L A2 A1 PP3V3_G3H_BT_FET 1 2 18

C until after S0 GPIO is guranteed stable B2 VIN VOUT B1 VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
0603 VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM 19
C
C2 ON 20
45 44 SMC_G3_WAKESRC_EN GND C3507 1 C3508 1
21
CRITICAL 0.1UF 10UF

C1
10% 20%
Q3540 16V
X7R-CERM 2
6.3V 2
X5R
DMC2400UV 0402 603
SOT563
R35421
P-CHN 10K
5%
3 D S 4 1/16W
MF-LF
402 2

BT_PWR_RST_L BT_PWR_EN
12 IN
6

D
Q3540
N-CHN

BT_PWR_RST 2 G DMC2400UV Supervisor & CLKREQ# Isolation

SOT563
S Delay = 130 ms +/- 20%
1
R3543 1 C3541
10K 0.01UF
5% 1 PP3V3_S4_AP_FLT 32 =PP3V3_S4_AP 32 45 70
1/16W 20%
MF-LF 2 16V
2 402 CRITICAL

1
CERM
B 402
1
R3530
100K
1
R3531
232K VDD 1 C3530 B
1%
1/16W
1%
1/16W U3530 0.1uF
20%
MF-LF MF-LF SLG4AP041V
2 402 2 402 2 10V
CERM
TDFN 402
P3V3AP_VMON 2 SENSE
+
VREF -
Wake from BT in G3H circuit
DLY
=PP3V3_G3H_BT 32 AP_RESET_CONN_L 4 RESET*
70 32 MR* 3 AP_RESET_L IN 20

45 44 OUT SMC_PME_S4_WAKE_L
EN 6 AP_PWR_EN IN 32 45

OUT 8 AP_CLKREQ_L OUT 11 18

CRITICAL 1 32 AP_CLKREQ_Q_L 7 IN (OD)
C3500
Q3501 0.1UF THRM
PAD GND
SSM3K15AMFVAPE 20% 1
3 D R3532

5
10V
5

VESM CERM 2 100K

402 1%
VDD
1/16W
U3501 MF-LF
2 402
USB3740
2 S G 1 80 13 BI USB_BT_N 6 DP_2 DFN

80 13 BI USB_BT_P 7 DM_2 CRITICAL

DP 10 USB_BT_MUX_N 32 80
PP3V3_S4_AP_FLT 32
USB_BT_WAKEN 2 DP_1
DM 9 USB_BT_MUX_P 32 80
1 DM_1
NC 1
Q3570 CRITICAL R3570
3 OE* 10K
A SSM3K15AMFVAPE 5%
A

G 1
1/16W
68 44 12 IN PM_SLP_S5_L 4 S VESM MF-LF SYNC_MASTER=J16_FIYIN SYNC_DATE=01/11/2013
GND 2 402 PAGE TITLE

AIRPORT/BT
8

1
R3501 D

S
SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO 36 12 PCIE_WAKE_L AP_WAKE_L 32
15K 3 DRAWING NUMBER SIZE

2
1%
1/20W Apple Inc. 051-0164 D
MF REVISION
201 2 R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
35 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 32 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
HDD SIGNAL CONNECTOR
SATA Activity LED
J3720
SILK_PART=HDD
CRITICAL 70 33 =PP3V3_S0_LED_SATA
PSA127-0747-A01-1H C3721 1 2 0.01UF
M-ST-SM DEVELOPMENT
8 10% 25V
402
X7R
SATA_HDD_R2D_C_P IN 11 78 R37991
GND_VOID=TRUE
330
1 SATA_HDD_R2D_C_N IN 11 78
5%
1/10W
2 SATA_HDD_R2D_P 1 2 MF-LF
GND_VOID=TRUE 78 603 2 SATALED_R_L
3 10% 25V X7R
GND_VOID=TRUE 78 SATA_HDD_R2D_N 402 0.01UF
4 C3722 GND_VOID=TRUE

5 78 SATA_HDD_D2R_C_N A DEVELOPMENT
GND_VOID=TRUE
6 SATA_HDD_D2R_C_P DS3799
GND_VOID=TRUE 78
C3723 1 2 0.01UF GREEN-3.6MCD
7 2.0X1.25MM-SM
10% 25V X7R K
402 SATA_HDD_D2R_N OUT 11 78 SILK_PART=SATA ACTIVE
GND_VOID=TRUE
9
SATA_HDD_D2R_P OUT 11 78 11 PCH_SATALED_L
1 2
518S0893 10% 25V X7R
402 0.01UF
C3724 GND_VOID=TRUE

C C

GS3 SSD
DC R =0.01-ohm
SSD:Y
PLACE_NEAR=J3700.1:10MM
CRITICAL
J3700 70 33
=PP3V3_S0_LED_SATA
SSD:Y
L3700 SILK_PART=SSD
FERR-26-OHM-6A
CRITICAL
R37121 1
R3713
70
=PP3V3_S0_SSD 2 1 33 PP3V3_S0_SSD_FLT
SSD-J90
100K
5% 5%
100K
0603 MIN_LINE_WIDTH=0.6mm 1/16W 1/16W
SSD:Y SSD:Y MIN_NECK_WIDTH=0.4mm F-RT-SM MF-LF MF-LF
VOLTAGE=3.3V 402 2 2 402
1 C3701 C3700 1 1 53
0.1UF 0.1UF 2 52 SMC_OOB2_R2D_L IN 45 81
20% 20%
2 10V
CERM
10V
CERM 2
3 51 SMC_OOB2_D2R_L OUT 45 81
402 402 4
5 50 SATA=H,PCIE=L
NC SATA_PCIE_SEL
6 49
NC DEVSLP
7 48
SSD_RESET_L PP3V3_AUX NC
47
NC PFW_L
20
8 SSD:Y
IN
NC
9 SSD_EN 1 2 PP3V3_S0_SSD_FLT 33
MFG_RSVD 10 46 5% 1/16W
402
MF-LF
11 45
PCIE TX3 NC
12 44
NC PCIE RX3 R3717 0
B NC
13 43
NC
1
A BP01
B
14 42
PCIE TX2 NC NC PCIE RX2 TP-BP-P19XP55SMP14X45O
C3711 SSD:Y
NC
15 41
NC
1
A BP02
1 2 0.1UF 16 40 TP-BP-P19XP55SMP14X45O
SSD_R2D_P<1> 10% 16V X5R-CERM 0201
1
A BP03
78 11 IN GND_VOID=TRUE TP-BP-P19XP55SMP14X45O
SSD_R2D_N<1> PLACE_NEAR=J3700.18:5MM
39
1
A BP04
PCIE TX1 11
78
IN
SSD:Y GND_VOID=TRUE
17
38
GND_VOID=TRUE

SSD_D2R_P<1>
TP-BP-P19XP55SMP14X45O

(POLARITY REVERSED) 10% 16V

1 2 0.1UF
X5R-CERM 0201
78
78
SSD_R2D_C_P<1>
SSD_R2D_C_N<1>
18
19 37 SSD_D2R_N<1>
OUT 11 78

11 78
PCIE RX1
OUT
C3710 GND_VOID=TRUE
PLACE_NEAR=J3700.19:5MM
GND_VOID=TRUE
GND_VOID=TRUE
20 36 GND_VOID=TRUE
GND_VOID=TRUE
Polarity Reversed
78 SSD_R2D_C_N<0> 21 35 SSD_D2R_P<0>
SSD:Y
78 SSD_R2D_C_P<0> 22 34 SSD_D2R_N<0>
OUT
OUT
11 78

11 78
PCIE RX0
C3713 1 2 0.1UF
GND_VOID=TRUE
23 33 GND_VOID=TRUE
Polarity Reversed
24
SSD_R2D_N<0> 10% 16V X5R-CERM 0201 PCIEx2 SSD requires AC coupling caps on TX side
PCIE TX0 11
78 IN GND_VOID=TRUE
PLACE_NEAR=J3700.21:5MM
25 32
78 11 IN SSD_R2D_P<0> SSD:Y
26 31 PCIE_CLK100M_SSD_N IN 11 77

1 2 0.1UF 27 30 PCIE_CLK100M_SSD_P IN 11 77

10% 16V X5R-CERM 0201 28 29

GND_VOID=TRUE
C3712 PLACE_NEAR=J3700.22:5MM

54 64
55 65
11 OUT SSD_CLKREQ_L 56 66
57 67
58 68
59

A 60
61 SYNC_MASTER=J16_JERRY SYNC_DATE=01/07/2013 A
62 PAGE TITLE

63 SATA/SSD Connectors
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
POR:514S0457 (tall) R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
37 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 33 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

HDD POWER/OOB CONNECTOR

HDD Out-of-Band Temperature Sensing

Notes:
Drive active: Valid signal protocol
Drive asleep: HDD drives HDD_OOB_TEMP low
Drive disconnected: Pulled high
70 50 49 48 34 =PP3V3_S0_SENSE
=PP1V5_S0_SENSE =PP3V3_S0_SENSE From drive:
1 SSD:N 70 70 50 49 48 34
R3815 Low: 0.0V to 0.3V
0 1 1 1 C3807 High: 1.2V to 2.0V
5%
R3802 R3800
1/16W 100K 49.9K 0.1UF
1% 10%
MF-LF 5%
2 402 1/16W 1/16W 2 16V
X7R-CERM
MF-LF MF-LF 0402
2 402 2 402 Trip is 1.0V
J3830 70 34 =PP5V_S0_SATA 1
R3814 HDD_OOB_1V00_REF
=PP3V3_S0_SENSE
C 78047-0483
M-ST-SM safety isolation
10K
5%
1/16W
1
R3801 1 C3806 1
34 48 49 50 70

C
1 R3808 MF-LF
2 402
100K 0.1UF R3805
SMC_OOB1_R2D_R_L 523 1%
10%
16V
1K
2 81 1 2 1/16W 2 X7R-CERM CRITICAL 5%
MF-LF 1/16W
3 81 HDD_OOB1_D2R_L 1% 1/16W SMC_OOB1_R2D_L IN 44 81
2 402
0402
5 U3800 MF-LF
MF-LF 402
4 3 2 402
LMV331
VCC+ SC70-5

CRITICAL
L3830 R3803
4 SMC_OOB1_D2R_L OUT 44 81

518S0864 C3830 1
1 2 81 HDD_OOB1_D2R_F_L Node is at 1.5V 1
3.3K
2 81 HDD_OOB1_D2R_R_L 1 GND
10UF
20%
6.3V 2
0402 FERR-220-OHM 5% 2
1/16W
X5R MF-LF
603 402
SSD:Y
CRITICAL
Q3801
NTR1P02L
SOT23-3-HF

70 50 49 48 34 =PP3V3_S0_SENSE 2 S D 3 P3V3_S0_OOB
MIN_LINE_WIDTH=0.3mm
MIN_NECK_WIDTH=0.15mm
VOLTAGE=3.3V
G
1SSD:Y D 6 SSD:Y
R3816 1 CRITICAL
10K
5% Q3800
1/16W
MF-LF
SSM6N15AFE
2 402
2 G S 1 SOT563

SATA_PWR_L

B D 3 SSD:Y
CRITICAL
B
Q3800
SSM6N15AFE
SOT563
5 G S 4

70 34 =PP5V_S0_SATA

A SYNC_MASTER=J16_JERRY SYNC_DATE=01/07/2013 A
PAGE TITLE

HDD Connector
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
38 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 34 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
=PP1V2_ENET_PHY 36

396mA (1000base-T, Caesar II)

70 36 35 =PP3V3_ENET_PHY
281mA (1000base-T max power, Caesar IV) VDD for Card Reader I/O
36 =PP3V3R1V8_CR_VDDIO
CRITICAL ENET_SR_LX 36
Internal 1.2V Switching Regulator pins.
L3900 =ENET_SR_VFB CRITICAL
FERR-600-OHM-300MA-0.85OHM 36
L3920
1 2 ENET_XTALVDDH FERR-600-OHM-300MA-0.85OHM
D 0402 MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V C3900 1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
PP1V2_ENET_PHY_AVDDL 1 2
D
MIN_LINE_WIDTH=0.4 mm 0402
0.1UF MIN_NECK_WIDTH=0.2 mm
10% VOLTAGE=1.2V
16V
X5R-CERM 2
0201
C3921 1 1 C3920
CRITICAL 0.1UF 4.7UF
10% 20%
L3905 16V
X5R-CERM 2 2 6.3V
X5R-CERM1 CRITICAL
FERR-600-OHM-300MA-0.85OHM 0201 402 L3925
1 2 PP3V3_ENET_PHY_BIASVDDH FERR-600-OHM-0.5A
0402
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm PP1V2_ENET_PHY_PCIEPLL 1 2
VOLTAGE=3.3V C3905 1 MIN_LINE_WIDTH=0.4 mm SM
0.1UF MIN_NECK_WIDTH=0.2 mm
10% VOLTAGE=1.2V
16V
X5R-CERM 2
0201
C3926 1 1 C3925
CRITICAL 0.1UF 4.7UF
10% 20%
L3910 16V
X5R-CERM 2 2 6.3V
X5R-CERM1 CRITICAL
FERR-600-OHM-300MA-0.85OHM 0201 402 L3930
1 2 PP3V3_ENET_PHY_AVDDH FERR-600-OHM-300MA-0.85OHM
0402
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V R39101
1 C3910 1 C3911 PP1V2_ENET_PHY_GPHYPLL
MIN_LINE_WIDTH=0.4 mm
1 2
0.1UF 0.1UF MIN_NECK_WIDTH=0.15 mm 0402
4.7K 10% 10% VOLTAGE=1.2V
5% 16V
1/16W 2 X5R-CERM 2 16V
X5R-CERM C3931 1 1 C3930
MF-LF 0201 0201
402 2 0.1UF 4.7UF
10% 20%
16V 2 6.3V
X5R-CERM 2 X5R-CERM1
0201 402

R39401 1
R3941 C3915 1 1 C3916
4.7K 4.7K 4.7UF 0.1UF
20% 10%

42
48

BIASVDDH 37

XTALVDDH 17

20
56
62

SR_VDD 14

SR_VDDP 15

SR_LX 16

SR_VFB 13
39
45
51

29
32

GPHY_PLLVDDL 36
35
61
6.3V 2 16V C3936 1 1 C3935

7
5% 5%
1/16W 1/16W X5R-CERM1 2 X5R-CERM 0.1UF 10UF
C =PP3V3_S0_ENET MF-LF
402 2
MF-LF
2 402
402 0201 10% 20% C

PCIE_PLLVDDL
70 AVDDH VDDO AVDDL VDDC 16V
X5R-CERM 2 2 6.3V
X5R LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
0201 603 the card reader on-chip I/O.
1
C3950 R3942 Connect only to U3900 pin 20.
1K
0.1UF 5% Current
1 2 1/16WLimiting OMIT_TABLE
77 13 OUT PCIE_ENET_D2R_N MF-LF
2 402 Resistor U3900
10%
16V
X5R-CERM
C3951 ENET_VMAIN_PRSNT 58 VMAIN_PRSNT (IPD-ENET) BCM57766C0KMLG TRD0_P 40 ENETCONN_MDI_P<0> BI 36 80
0201 0.1UF QFN-8X8 ENETCONN_MDI_N<0>
1 2 TRD0_N 41 BI 36 80
77 13 OUT PCIE_ENET_D2R_P
77 PCIE_ENET_D2R_C_N 27 PCIE_TXD_N TRD1_P 44 ENETCONN_MDI_P<1> BI 36 80
10% 77 PCIE_ENET_D2R_C_P 28 PCIE_TXD_P TRD1_N 43 ENETCONN_MDI_N<1> 36 80
16V BI
X5R-CERM TRD2_P 46 ENETCONN_MDI_P<2>
C3955 0201 77 PCIE_ENET_R2D_P 33 PCIE_RXD_P BI 36 80
PP3V3R1V8_ENET_LR_OUT
0.1UF TRD2_N 47 ENETCONN_MDI_N<2> BI 36 80
MIN_LINE_WIDTH=0.3 mm
36

1 2 77 PCIE_ENET_R2D_N 34 PCIE_RXD_N
MIN_NECK_WIDTH=0.15 mm
77 13 IN PCIE_ENET_R2D_C_P TRD3_P 50 ENETCONN_MDI_P<3> BI 36 80
VOLTAGE=3.3V
10% 77 11 IN PCIE_CLK100M_ENET_P 31 PCIE_REFCLK_P TRD3_N 49 ENETCONN_MDI_N<3> BI 36 80
16V
X5R-CERM
C3956 77 11 IN PCIE_CLK100M_ENET_N 30 PCIE_REFCLK_N
0201 0.1UF
GPIO_0/CR_ACT_LED* 5

(IPD)
77 13 IN PCIE_ENET_R2D_C_N 1 2 37 IN ENET_RESET_L 11 PERST* (IPD)
NC
GPIO_1/LR_OUT 8
10% 18 11 ENET_CLKREQ_L 12 CLKREQ* (OD) GPIO_2/MEDIA_SENSE 9 ENET_MEDIA_SENSE 11 80
16V OUT OUT
X5R-CERM NOTE: "IPx" == Programmable pull-up/down
36 =ENET_WAKE_L 0201 3 WAKE* (OD)
OUT ENET_SD_DETECT_L
(See note)
(IPx-ENET) SD_DETECT
SD_DETECT can only be used active low due to errata.
o1 IN 37 80

37 20 IN ENET_LOW_PWR 4 LOW_PWR (IPD) (IPU-ENET) CR_CMD 26 80 ENET_SD_CMD R3961 33 1 2 SDCONN_CMD IN 37 80

WAKE# 5% 1/20W MF 201
CR_CLK 21 80 ENET_SD_CLK R3979 33 1 2 SDCONN_CLK OUT 37 80
Must isolate from PCIe WAKE# if PHY SMB_ENET_SCL 6 SMB_CLK 5% 1/20W MF 201
is powered-down in S3/S5. Standard SMB_ENET_SDA 10 SMB_DATA (IPD-ENETM) CR_DATA0 25 80 ENET_CR_DATA<0> R3971 33 1 2 SDCONN_DATA<0> BI 37 80

N-channel FET isolation suggested. CR_DATA1 24 80 ENET_CR_DATA<1> R3972 33 1 2 5% 1/20W MF 201

SDCONN_DATA<1> BI 37 80
80 35 ENET_SCLK 66 SCLK_SPD1000LED* R3973 33 5% 1/20W MF 201
B If PHY is always powered then alias
80 35
BI
ENET_MISO 64 SI/EEDATA
CR_DATA2 23 80 ENET_CR_DATA<2>
R3974 33
1 2
5% 1/20W MF 201
SDCONN_DATA<2> BI 37 80
B

(IPU)
IN 22 ENET_CR_DATA<3> 1 2 SDCONN_DATA<3>
=ENET_WAKE_L to PCIE_WAKE_L. CR_DATA3 80
BI 37 80
ENET_MOSI 65
R3975

(IPU-ENET)
80 35 BI SO_LINKLED* 33 5% 1/20W MF 201
CR_DATA4 52 80 ENET_CR_DATA<4> 1 2 SDCONN_DATA<4> BI 37 80
80 35 BI ENET_CS_L 63 CS*/EECLK R3976 33 5% 1/20W MF 201
CR_DATA5 53 80 ENET_CR_DATA<5> 1 2 SDCONN_DATA<5> BI 37 80

NC
2 SPD100LED*/SERIAL_DO (OD) CR_DATA6 54 80 ENET_CR_DATA<6> R3977 33 1 2 5% 1/20W MF 201
SDCONN_DATA<6> BI 37 80

36 OUT ENET_TRAFFICLED_L 67 TRAFFICLED*/SERIAL_DI (OD) CR_DATA7 55 80 ENET_CR_DATA<7> R3978 33 1 2 5% 1/20W MF 201

SDCONN_DATA<7> BI 37 80
No MS (Memory Stick) Insert feature needed. 5% 1/20W MF 201
(IPU-ENET)
MS_INS* 59 Control signal to light LED or control SD bus power.
79 19 IN SYSCLK_CLK25M_ENET 18 XTALI NC
19 XTALO
(IPU-ENET)
CR_LED*/CR_BUS_PWR 60 ENET_CR_PWREN OUT 37
NC (IPU-ENET)
CR_WP* 57 SDCONN_WP IN 37

80 ENET_RDAC 38 RDAC (NO IPU OR IPD-ENET) SR_DISABLE 68 ENET_SR_DISABLE R3981 1K 1 2 402

THRM_PAD 5% 1/16W MF-LF
(See note)
PHY Non-Volatile Memory

69
1
R3965 ENET 1.2V SR IS ENABLED IF FLOATING. ENET supports both active-levels for WP.
1.24K
ROM contains MAC address, PCIe config 1% ENET_CR Signals
1/16W
info as well as code for Bonjour proxy. MF-LF
Avoids need for EFI to program at startup. 2 402 BCM requests SD CR[0:7], CMD, CLK termination. PLACEMENT_NOTE=PLACE R3961 NEAR U3900

(Required ROM size 1 Mbit)

ENET_SR_DISABLE PLACEMENT_NOTE=PLACE R3979 NEAR U3900

70 36 35 =PP3V3_ENET_PHY If ENET switching regulator is PLACEMENT_NOTE=PLACE R3971 NEAR U3900

used, this pin should have PLACEMENT_NOTE=PLACE R3972 NEAR U3900

a 1K pull-down to GND
6

PLACEMENT_NOTE=PLACE R3973 NEAR U3900

1 C3990 PLACEMENT_NOTE=PLACE R3974 NEAR U3900
VCC 0.1UF
10% PLACEMENT_NOTE=PLACE R3975 NEAR U3900
U3990 2 16V
X5R-CERM
0201 PLACEMENT_NOTE=PLACE R3976 NEAR U3900
AT45DB011D
SOIC-8S1 PLACEMENT_NOTE=PLACE R3977 NEAR U3900

80 35 IN ENET_SCLK 2 SCK OMIT_TABLE SI 1 ENET_MOSI IN 35 80 PLACEMENT_NOTE=PLACE R3978 NEAR U3900

A 80 35 ENET_CS_L 4 CS*
SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
IN PAGE TITLE
SO 8 ENET_MISO
5 WP*
NOSTUFF
OUT 35 80
ETHERNET PHY (CAESAR IV)
1 DRAWING NUMBER SIZE
3 RESET*
GND
R3990 1R3997 051-0164 D
4.7K
5%
4.7K
5%
Apple Inc. REVISION
7

NOTE: Pull-down on SO plus internal pull-ups on 1/16W 1/16W R

MF-LF MF-LF 12.4.0
other 3 SPI pins configures ENET for the 2 402 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
Atmel AT45DB011D (1Mbit) ROM. If a different THE INFORMATION CONTAINED HEREIN IS THE
ROM is used then the straps must change. PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
NOTE: ENETM requires SI pull-down instead of SO. I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
39 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 35 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

3.3V ENET FET

CAESAR IV 1.2V INT.VR CMPTS ENET Enable Generation CRITICAL
Q4020
CAESAR IV ACTIVITY LED
"ENET" = "S0" || ("S4" && "WOL_EN")
NTR4101P
CRITICAL SOT-23-HF

L4010 70 36 35 =PP3V3_ENET_PHY
70 36 35 =PP3V3_ENET_PHY 4.7UH-0.8A 70 =PP3V3_S4_FET_ENET 2 S D 3 PP3V3_ENET_FET 70

35 ENET_SR_LX 1 2 PP1V2_ENET_INTREG 36

D Power decoupling
1 C4010 1 C4011
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
PCAA031B-SM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM R40201
1 C4020
0.033UF
G
DEVELOPMENT
1
R4050
D
4.7UF 0.1UF SWITCH_NODE=TRUE C4012 1 C4013 1 VOLTAGE=1.2V 10K
5%
10%
16V
2 X5R
1 330
20% 10% DIDT=TRUE 10UF 0.1UF 5%
2 6.3V
X5R-CERM1 2 16V
X7R-CERM
20%
6.3V
10%
16V
Feedback loop 1/16W
MF-LF R4021
402 C4021 1/16W
MF-LF
402 0402 X5R 2 X7R-CERM 2 402 2 0.01UF
603 0402
100K 2 1 2 402
PM_EN_ENET_L 1 2 P3V3ENET_SS ENET_ACT
CRITICAL 3
5%
1/16W 10% A
50V DEVELOPMENT
Q4021 D
MF-LF
402 X7R-CERM
2N7002DW-X-G 0402 LED4050
SOT-363 GREEN-3.6MCD
2.0X1.25MM-SM
14 WOL_EN 5 G S CRITICAL 6 K
IN SILKSCREEN:ENET ACT
Q4021 D
4 2N7002DW-X-G
SOT-363
69 68 45 44 21 12 PM_SLP_S3_L 2 G S
IN
36 PP1V2_ENET_INTREG =PP1V2_ENET_PHY 35
1 35
ENET_TRAFFICLED_L
MAKE_BASE=TRUE
=ENET_SR_VFB 35

CAESAR IV WAKE# ISOLATION

C =PP3V3_ENET_PHY 35 36 70 C
1
Q4070 R4070
SSM3K15AMFVAPE 10K
5%
G 1

VESM 1/16W
MF-LF
2 402
D

32 12 PCIE_WAKE_L ENET_WAKE_L =ENET_WAKE_L 35

MAKE_BASE=TRUE
3

PP3V3R1V8_ENET_LR_OUT =PP3V3R1V8_CR_VDDIO
35 35
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.15 mm 1 C4030 1 C4031 1 C4032
4.7UF 0.1UF 0.1UF
514-0822 20% 10% 10%
157S0058 CRITICAL 6.3V
2 X5R-CERM12
16V 16V
CRITICAL X5R-CERM 2 X5R-CERM
402 0201 0201
T4000 J4000
80 35 ENETCONN_MDI_P<1> 1 SM 12 ENETCONN_MDI_T_P<1> BI 36 80
K70-K72
BI F-ANG-TH
ENET_MDI
ENETCONN_MDI_N<1> 2 11 ENETCONN_MDI_T_N<1> BI
80 35 BI 36 80
80 36 BI ENETCONN_MDI_T_N<3> 8 ENET_MDI_TRAN3-
80 36 BI ENETCONN_MDI_T_P<3> 7 ENET_MDI_TRAN3+
3 80 10 ENETCONN_MCT1
80 36 BI ENETCONN_MDI_T_N<1> 6 ENET_MDI_TRAN1-
TX
80 36 BI ENETCONN_MDI_T_N<2> 5 ENET_MDI_TRAN2-
LFE8904CF 80 36 BI ENETCONN_MDI_T_P<2> 4 ENET_MDI_TRAN2+
4 80 9 ENETCONN_MCT3
80 36 ENETCONN_MDI_T_P<1> 3 ENET_MDI_TRAN1+
B ENETCONN_MDI_P<3> 5 8 ENETCONN_MDI_T_P<3> BI
80 36
BI
BI ENETCONN_MDI_T_N<0> 2 ENET_MDI_TRAN0- B
80 35 BI 36 80
80 36 BI ENETCONN_MDI_T_P<0> 1 ENET_MDI_TRAN0+

ENETCONN_MDI_N<3> 6 7 ENETCONN_MDI_T_N<3> BI
80 35 BI 36 80 9
RX
10
11
CRITICAL 12 SHIELD
PINS
T4010
SM
13
80 35 ENETCONN_MDI_N<2> 1 12 ENETCONN_MDI_T_N<2> BI 36 80 14
BI

80 35 ENETCONN_MDI_P<2> 2 11 ENETCONN_MDI_T_P<2> BI 36 80
BI

3 80 10 ENETCONN_MCT2
TX
LFE8904CF
4 80 9 ENETCONN_MCT0

80 35 ENETCONN_MDI_N<0> 5 8 ENETCONN_MDI_T_N<0> BI 36 80
BI

80 35 ENETCONN_MDI_P<0> 6 7 ENETCONN_MDI_T_P<0> BI 36 80
BI
RX

ENETCONN_TCT
1 1 1 1
R4000 R4001 R4002 R4003
A 1 C4001
0.1UF
1 C4002
0.1UF
1 C4003
0.1UF
1 C4004
0.1UF
75
5% 5%
75 75
5% 5%
75 SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
20% 20% 20% 20% 1/16W 1/16W 1/16W 1/16W PAGE TITLE
10V 10V 10V 10V MF-LF MF-LF MF-LF MF-LF
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402 2 402 2 402 2 402 2 402 Ethernet Support & Connector
DRAWING NUMBER SIZE
80 ENETCONN_MCT_BS Apple Inc. 051-0164 D
MIN_LINE_WIDTH=0.4 MM REVISION
MIN_NECK_WIDTH=0.2 mm R
NOSTUFF 12.4.0
1 C4000 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1000PF THE INFORMATION CONTAINED HEREIN IS THE
10% PROPRIETARY PROPERTY OF APPLE INC.
2KV THE POSESSOR AGREES TO THE FOLLOWING: PAGE
2 CERM
1206 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
40 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 36 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SD CARD 3.3V OVERCURRENT PROTECTION CHIP

D 353S2548 D
U4100 =PP3V3_S0_SW_SD_PWR 37
TPS2553
=PP3V3_S0_SDCARD 6 IN SON
70 OUT 1 PP3V3_S0_SW_SD_PWR
CRITICAL MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 mm
ILIM 2 SDCONN_ILIM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
35 IN ENET_CR_PWREN 4 EN FAULT* 3 SDCONN_OC_L 12
THRML
GND PAD 1 1
C4100 1 C4101 1 R4118 1 C4102 1 C4103 R4100

7
22UF 0.1UF 13K 10UF 0.1UF 47K
20% 10% 1% 20% 10% 5%
6.3V 16V 1/16W 2 6.3V
X5R 2 16V
X7R-CERM
1/16W
X5R-CERM1 2 X7R-CERM 2 MF-LF
603 0402
MF-LF
0603 0402 2 402 2 402
SDCONN_ILIM_R

1
R4119
13K
1%
1/16W
MF-LF
2 402

J16:516-0249 / J17:512-0038

SD CARD CONNECTOR
=PP3V3_S0_SW_SD_PWR
37
J4100
SD-CARD-D7
F-ANG-TH

C 80 35

80 35
BI SDCONN_DATA<3>
SDCONN_CMD
1
2
CD/DAT3
CMD
C
OUT
L4102 3 VSS
47NH-1.3OHM 4 VDD
CRITICAL1 2 5
80 35 IN SDCONN_CLK 80 SDCONN_CLK_R CLK
0402 6 VSS
80 35 SDCONN_DATA<0> 7 DAT0
BI
80 35 SDCONN_DATA<1> 8 DAT1
BI
80 35 BI SDCONN_DATA<2> 9 DAT2
80 35 SDCONN_DATA<4> 10 DAT4
BI
80 35 BI SDCONN_DATA<5> 11 DAT5
80 35 SDCONN_DATA<6> 12 DAT6
BI
80 35 BI SDCONN_DATA<7> 13 DAT7
37 SDCONN_DETECT_L
14 CRD_DETECT_SWITCH
35 OUT SDCONN_WP 15 WRITE_PROTECT_SWITCH
SD switch is normally connected (i.e. gnd)
16 SHLD_PIN
17 SHLD_PIN
18 SHLD_PIN
NOSTUFF NOSTUFF 19 SHLD_PIN
1 C4171 1 C4170 20 SHLD_PIN
22PF 15PF 21
5% 5% SHLD_PIN
SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION. 2 50V
CERM 2 50V
CERM 22 SHLD_PIN
0402 402
70 =PP3V3_S4_SDCARD 23 SHLD_PIN
24 SHLD_PIN
25 SHLD_PIN

B C4110
1UF
1
26
27
SHLD_PIN
SHLD_PIN
B
10%
10V
X5R 2
402-1
10

CRITICAL
VDD

U4111
SLG4AP026V
TDFN
2
R4114
35 20 IN ENET_LOW_PWR LOW_PWR
RST RST_OUT* 4 0
SLG_ENET_RESET_R_L 1 2 ENET_RESET_L OUT 35
3 RST_IN* LOGIC
20 IN ENET_SD_RESET_L 5%
1/16W
MF-LF
DET_CH_EN* 6 402
NOSTUFF
37 SDCONN_DETECT_L 7 DET_IN
DLY (OD) 9
XOR

(IPU) SDCONN_STATE_CHANGE OUT -> TO PCH GPIO

R4110 1
FROM SD CONN -> 13 18

10K DET_CHNGD*
5% (OD) 8
XOR

ENET_SD_DETECT_L OUT 35 80 -> TO ENET CHIP

1/16W SD_DETECT_LVL 1
MF-LF DET_OUT
402 2
DET_LVL
THRM
R41151 GND PAD
10K
5

5%
1/16W
MF-LF
402 2
When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms
regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#
DLY block is 20ms nominal

A SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
PAGE TITLE

SD READER CONNECTOR
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

80 38 SMIA_DATA_N 1

80 38 SMIA_DATA_P 2
3

80 38 SMIA_CLK_N 4

D 80 38 SMIA_CLK_P 5
6
D
80 38 I2C_CAMSENSOR_SDA 7

80 38 I2C_CAMSENSOR_SCL 8
9
=PP3V3_S4_CAMERA PP1V8_S4_CAMERA
70 39 38 38 39
38 PP5V_S4_CAMERA_F 10

1 1 38 SMB_ALS_F_SDA 11
C4222 C4224
1 1.0UF 0.1UF 38 SMB_ALS_F_SCL 12
C4213 20% 10%
0.1UF 6.3V 6.3V 13
10% 2 X5R 2 CERM-X5R
PP1V8_S4_CAMERA_F 14
2 6.3V
CERM-X5R
0201-1 0201 38

0201 38 PP3V3_S4_ALS_F 15

52 GND_AUDIO_DMIC
16

52 AUD_DMIC_SDA1 1 2 AUD_DMIC_SDA1_CONN 17

L4220 PP1V2_S4_CAMERA 38 L4200 R4260 0 18

FERR-600-OHM-300MA-0.85OHM MIN_NECK_WIDTH=0.15 MM 39 FERR-1000-OHM 52 AUD_DMIC_CLK 1 2 AUD_DMIC_CLK_CONN 19
MIN_LINE_WIDTH=0.6 MM
1 2 PP3V3_S4_CAMFILT VOLTAGE=3.3V 1 C4228 70 58 55 54 52 =PP3V3_S0_AUDIO 1 2 PP3V3_DMIC_CONN R4264 0 20
0402 0.1UF 0402 MIN_NECK_WIDTH=0.15MM
1 C4216 1 C4218 1 C4220 10% MIN_LINE_WIDTH=0.4MM
1.0UF 0.1UF 0.1UF 2 6.3V
CERM-X5R VOLTAGE=3.3V 1 C4265
23 26
20% 10% 10% 0201 24
1UF
2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 10%
0201-1 0201 0201 16V
2 X5R
38 CAM_AGND 402
MIN_NECK_WIDTH=0.15 MM MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.2V R4220 VOLTAGE=1.2V L4210
39 38 PP1V2_S4_CAMERA
1
10 2 PP1V2_S4_F_R 1 2 L4202
PP1V2_S4_CAMFILT
FERR-1000-OHM
5% MF 0402
1 1 1 1
C4214
0.1UF
C4215
0.1UF
C4217
0.1UF
1/20W 201 FERR-1000-OHM R4218 1R4219 70 =PP5V_S4_CAMERA 1 2 PP5V_S4_CAMERA_F 38
R4267
1K 1K
C 10%
6.3V
2 CERM-X5R
10%
6.3V
2 CERM-X5R
10%
6.3V
2 CERM-X5R 1 C4221 1 C4223
1%
1/20W
MF
1%
1/20W
MF
0402
MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.6 MM
1 C4262
1UF 47 =SMB_ALS_SDA 1
0 2 SMB_ALS_F_SDA 38
C
0201 0201 0201 1.0UF 0.1UF VOLTAGE=5V 10% 5%
20% 10% 2 201 2 201 16V
2 X5R 1/20W 1 C4267
NC 2 6.3V
X5R 2 6.3V
CERM-X5R 402
MF
150PF
0201-1 0201 0201
L4204 5%
DVDD3 16
DVDD4 34
DVDD6 43

MAVDD33 32

USB_VDDA0 23

OVDD2 40

USB_VDDL0 19

VDDA_PLL 26
NC 45
50V

OVDD1 7
GPIO3, EXT/IN FIRMWARE BOOT SEL CAM_PLLGND 38 FERR-1000-OHM 2 CERM
402
’1’= EXT FW 1 2 NOSTUFF
39 38 PP1V8_S4_CAMERA PP1V8_S4_CAMERA_F 38
’0’= INT FW 0402 1 C4264
80 38 SMIA_DATA_P GPIO3 CAN BE CONFIGED AS MIN_NECK_WIDTH=0.15 MM 1UF
SMIA_DATA_N
MIN_LINE_WIDTH=0.6 MM 10% R4268
80 38
GENERAL GPIO AFTER POWER ON CRITICAL VOLTAGE=1.8V 0
2 16V
X5R =SMB_ALS_SCL 1 2 SMB_ALS_F_SCL
SMIA_CLK_P 47 38
80 38

SMIA_CLK_N
U4200 L4206
402
5%
1
80 38
VC0359 FERR-1000-OHM
1/20W
MF
C4268
0201 150PF
FQFN =PP3V3_S4_ALS 1 2 PP3V3_S4_ALS_F
5%
48 GPIO0 CS_PWDB 37 TP_CS_PWD_L 70 38 50V
2 CERM
NC 0402
TP_CAM_GPIO1 47 GPIO1 CS_CLK 38 TP_ISM_CLK 1 C4266 402
MIN_NECK_WIDTH=0.15 MM NOSTUFF
39 CAM_EXT_BOOT 46 GPIO3 CS_RSTB 36 TP_ISM_RST_L MIN_LINE_WIDTH=0.6 MM 1UF
VOLTAGE=3.3V 10%
12 GPIO9 CS_SCK 41 I2C_CAMSENSOR_SCL 38 80 2 16V
NC X5R Use 100 ohms and 150pF for 10MHz filter
CS_SDA 42 I2C_CAMSENSOR_SDA 38 80
402
28 MRXDATAINP
27 MRXDATAINN 337S4151 CLKIN 9 CAM_XTAL_IN 38
30 MRXCLKINP CLKOUT 10 CAM_XTAL_OUT 38
29 MRXCLKINN TEST 11 CAM_TEST

80 13 USB_CAMERA_P 20 USB_PADP USB_VRES 24 CAM_USB_VRES 70 39 38 =PP3V3_S4_CAMERA

80 13 USB_CAMERA_N 21 USB_PADM PLACE_NEAR=U4200:5mm
1 1 1 C4219
MIPI_RESISTOR 33 MIPI_RESISTOR R4213 1 C4226 R4216 0.1UF
LED_FIXED 17 NC 8.2K 0.1UF 47 R4207 2 2 R4206 1
R4208 10%

8
6 SF_CLK 1% 1% 6.3V
B 80 38 CAM_SF_CLK
CAM_SF_CS_L 3 SF_CS* RST* 1 CAM_PROC_RESET_L 39
1/20W
MF
2 201
10%
6.3V
2 CERM-X5R
1/20W
MF
2 201
10K
1%
1/20W
10K
1%
1/20W 5%
4.7K
1/20W
VCC 2 CERM-X5R
0201 B
80 38
5 SF_DIN
0201 MF MF MF U4202
80 38 CAM_SF_DIN UART1_RX 14 CAM_RX
PLACE_NEAR=U4200:5mm
201 201
2 201 1MBIT-104MHZ
USB_VSSA0

USB_VSDL0

4 SF_DOUT 1 1 PLACE_NEAR=U4200:5mm
UART1_TX 13 PLACE_NEAR=U4200:5mm
VSSA_PLL

1 CAM_SF_DOUT CAM_TX
R4204 80 38

CAM_SF_WP_L 2 SF_WP*
1
R4210 CAM_SF_CLK
R4203
1 2
33
CAM_SF_CLK_R 6 SCLK
USON
SI/SIO0 5 CAM_SF_DOUT_R 2
33 R4205
1 CAM_SF_DOUT
24K 80 38 80 38 80 80 38 80
DVSS4
DVSS6

MAVSS

OVSS1
OVSS2

DVSS3

10K 1% MF MF 1%
THRM

1% 1% MX25L1006EZUI-10G
PAD

1/20W 1/20W
=PP3V3_S4_CAMERA 38 39 70 1/20W 201 201 1/20W
MF MF CRITICAL
2 201 CAM_SF_CS_L 1 CS* R4209
PLACE_NEAR=U4200:5mm
2 201 80 38
OMIT_TABLE 33
CAM_SF_WP_L 3 WP* SO/SIO1 2 CAM_SF_DIN_R 1 2 CAM_SF_DIN
35
44

8
39

80 38 80 38 80

CAM_SF_HOLD_L 7 HOLD* 1%
2 1/20W
R4211 GND
THRM
PAD
MF
201
10K PLACE_NEAR=U4202:5mm

9
201 335S0852
MF
CAM_AGND 38 1 1/20W
XW4202
SHORT-0201
1%

1 2 38 CAM_AGND CAM_PLLGND 38

2
XW4203
SHORT-0201
UART1_TX is strap for selection
of pos/neg edge sampling of SERIAL FLASH
SPI clock during power-on.
STITCH THERMAL PAD TO INNER GROUND 1
’1’ = POSITIVE EDGE
’0’ = NEGATIVE EDGE
CRYSTAL
C4227
R4215 18PF
47 1 2
38 CAM_XTAL_OUT 1 2 CAM_XTAL_OUT_R
1%
1/20W 5%
MF 25V
A R4214
2 201 NP0-C0G-CERM
0201 SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A

3
PAGE TITLE

2 4
1M CRITICAL
1%
1/20W
MF
Y4200
3.2X2.5MM-SM
Camera Controller

1
201 1 12.000MHZ-30PPM-10PF-85C
DRAWING NUMBER SIZE

C4225 Apple Inc. 051-0164 D

18PF REVISION
R
38 CAM_XTAL_IN 1 2 12.4.0
5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
25V THE INFORMATION CONTAINED HEREIN IS THE
NP0-C0G-CERM PROPRIETARY PROPERTY OF APPLE INC.
0201 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
42 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 38 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D Camera Processor Reset Camera Processor ExtBoot Cntl D

70 39 38 =PP3V3_S4_CAMERA 70 39 38 =PP3V3_S4_CAMERA
1 C4300 1
0.1UF R4302
10% 10K
2 6.3V
CERM-X5R
1
R4300 5%
0201 1/20W
51K MF
5% 2 201
1/20W
MF CAM_EXT_BOOT 38
2 201 CRITICAL
CRITICAL CRITICAL Q4302
CRITICAL CAM_PROC_RESET_L 38
8 74LVC2G08 69 8 74LVC2G08 SSM3K15AMFVAPE D 3
69 39 20 18 12 PM_PCH_PWROK 3
A
SOT902 Q4300 20
12 PM_PCH_PWROK 7
A
SOT902 VESM
SSM3K15AMFVAPE D 3 18
U4300Y 5 VESM
39
U4300Y 1
14 PCH_CAM_RESET_R 2 08 14 PCH_CAM_EXT_BOOT_R_L 6 08
B B
1 C4301
4 4
2.2UF CAM_EXT_BOOT_L
1 G S 2
20%
1 G S 2 2 10V
X5R-CERM
CAM_PROC_RESET 402

70 39 38 =PP3V3_S4_CAMERA

C PP1V2_S4_CAMERA 1
C
39 38
R4306
10K
5%
1/20W
1 MF 3
R4304 2 201
1K
5% CAM_P1V2_RST_HOLDOFF_L 5
Q4310
1/20W MMDT3904-X-G
MF SOT-363-LF
6
2 201 4
CAM_P1V2_RST_HOLDOFF 2 Q4310
MMDT3904-X-G
SOT-363-LF
1

B B

PP1V8_S4_CAMERA Vreg PP1V2_S4_CAMERA Vreg

70 39 38 =PP3V3_S4_CAMERA 70 39 38 =PP3V3_S4_CAMERA

1 C4310 1 C4320
1UF 1UF
10% 39 38 PP1V8_S4_CAMERA 10%
2 16V
X5R 2 16V
X5R
402 402

1 1
R4310 R4320
4.7K 4.7K
1

CRITICAL CRITICAL
5% 5%
1/20W VIN 1/20W VIN
MF MF
2 201 2 201
P1V8_S4_EN 3 EN U4310 VO 6 PP1V8_S4_CAMERA 38 39 P1V2_S4_EN 3 EN U4320 VO 6 PP1V2_S4_CAMERA 38 39

ISL9021AIRUCZ-T 2 MIN_NECK_WIDTH=0.15 MM ISL9021AIRUWZ-T 2 MIN_NECK_WIDTH=0.15 MM

1 NC MIN_LINE_WIDTH=0.6 MM 1 NC MIN_LINE_WIDTH=0.6 MM
C4312 DFN NC VOLTAGE=1.8V C4322 DFN NC VOLTAGE=1.2V
1UF NC 5 NC 1UF NC 5 NC
A 10%
10V
2 X5R-CERM
0402 GND
1 C4314
4.7UF
10%
10V
2 X5R-CERM
0402 GND
1 C4324
4.7UF SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
20% 20% PAGE TITLE
6.3V 6.3V
Camera Controller Support
4

2 X5R-CERM1 2 X5R-CERM1
402 402
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

D D

Internal DP Connector
Backlight Control
518S0829 Delay applies only on a L->H transition on VIDEO_ON. This guarantees video is valid before the backlight is enabled.
On a H->L transition, output follows with standard logic propagation delay. This ensures the backlight is off immediately after loss of video
CRITICAL
J4400
C 20525-130E-01
F-RT-SM
C
L4400 31 70 47 31 =PP3V3_S0_DP
F4400 FERR-220-OHM
3AMP-32V-467
=PP12V_S0_LCD 1 2 1 2 1 1
70 PP12V_LCD_F PP12V_LCD C4450
VOLTAGE=12V
MIN_LINE_WIDTH=0.4 mm 0805 VOLTAGE=12V
MIN_LINE_WIDTH=0.4 mm 2 0.1UF
603-HF MIN_NECK_WIDTH=0.1 mm MIN_NECK_WIDTH=0.1 mm 1 C4420 1 C4401 10% 1 C4451
3 6.3V
10UF 0.001UF 2 CERM-X5R 10UF
10% 20% 4 0201 20%
16V 50V 6.3V
2 X5R-CERM 2 CERM 5 2 CERM-X5R
0805 0402 5 U4450 0402-1 5 U4450
6 74AUP2G14GM
SOT886
D4450
SOD-523
74AUP2G14GM
SOT886
7
40 VIDEO_ON 1 6 A K VIDEO_ON_L_DLY 3 4 BKLT_EN 66
8 OUT
To BLC
9 1
R4451 BAT54XV2T1
10 100K 2 2
5%
11 1/20W R4450
12 MF 30.1K2
2 201 1
81 47 SMB_DP_TCON_SDA 13
BI 1%
Display TCon Master 14 1/20W
81 47 OUT SMB_DP_TCON_SCL MF
SMB_DP_TCON_SLA_SDA 15 201
47 BI
Display TCon Slave 16
47 IN SMB_DP_TCON_SLA_SCL
85 52 DP_INT_SPDIF_AUDIO 17
OUT
41 DP_INTPNL_HPD 18 VIDEO_ON_L OUT 3
OUT To Diag LED
19

85 41 DP_INTPNL_AUX_N 20
BI
85 41 DP_INTPNL_AUX_P 21
BI
22
B 85 41 IN DP_INTPNL_ML_P<0> 23
24
B
85 41 IN DP_INTPNL_ML_N<0>
25

85 41 DP_INTPNL_ML_P<1> 26
IN
85 41 DP_INTPNL_ML_N<1> 27
IN
28

40 VIDEO_ON 29

66 BKLT_VSYNC 30
OUT

33
34
35
36
37
38
39
40
41

A SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
PAGE TITLE

Internal DP Support
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

TP to DP aliases

26 IN
TP_DP_TBTSRC_ML_CP<0> DP_TBTSRC_ML_P<0> 41 85
MAKE_BASE=TRUE

26 IN
TP_DP_TBTSRC_ML_CN<0> DP_TBTSRC_ML_N<0> 41 85
MAKE_BASE=TRUE

TP_DP_TBTSRC_ML_CP<1> DP_TBTSRC_ML_P<1>
D
26

26
IN

TP_DP_TBTSRC_ML_CN<1> DP_TBTSRC_ML_N<1>
MAKE_BASE=TRUE
41 85

41 85
D
IN
MAKE_BASE=TRUE

26 BI
TP_DP_TBTSRC_AUXCH_CP DP_TBTSRC_AUXCH_P 41 85
MAKE_BASE=TRUE

26 BI
TP_DP_TBTSRC_AUXCH_CN DP_TBTSRC_AUXCH_N 41 85
MAKE_BASE=TRUE

=PP3V3_S0_INTDPMUX 41 70

NC aliases
71 41 DP_INT_HPD
TP_DP_TBTSRC_ML_CP<2> NC_DP_TBTSRC_ML_P<2>
1 C4568 1 C4569
26 IN
NO_TEST=TRUE MAKE_BASE=TRUE
0.1UF 0.1UF
10% 10%
26 IN TP_DP_TBTSRC_ML_CN<2> NC_DP_TBTSRC_ML_N<2> 1
R4500 6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
NO_TEST=TRUE MAKE_BASE=TRUE
100K 0201 0201
5%

29
20
16
12
1/20W
TP_DP_TBTSRC_ML_CP<3> NC_DP_TBTSRC_ML_P<3>

9
3
26 IN MF
NO_TEST=TRUE MAKE_BASE=TRUE
2 201
26 IN
TP_DP_TBTSRC_ML_CN<3> NC_DP_TBTSRC_ML_N<3> 85 71 IN DP_INT_ML_P<0> 31 D0+A VDD
NO_TEST=TRUE MAKE_BASE=TRUE
DP_INT_ML_N<0> 30
85 71 IN D0-A U4500
DP_INT_ML_P<2> NC_DP_INT_ML_P<2> DP_INT_ML_P<1> 27 PI3VEDP212 C4500 1 2
71 IN 85 71 IN D1+A
NO_TEST=TRUE MAKE_BASE=TRUE TQFN 0.15UF 0201 10% DP_INTPNL_ML_P<0> OUT 40 85
85 71 DP_INT_ML_N<1> 26 D1-A CRITICAL D0+ 1 85 DP_INTPNL_ML_C_P<0> X5R 6.3V
DP_INT_ML_N<2> NC_DP_INT_ML_N<2> IN DP_INTPNL_ML_N<0>
71 IN
NO_TEST=TRUE MAKE_BASE=TRUE 85 71 BI DP_INT_AUX_P C4508 1 2
19 D0- 2 85 DP_INTPNL_ML_C_N<0> C4501 1 2 OUT 40 85
0201 10%
0.1UF CERM-X5R 85 DP_INT_AUX_C_P AUX+A 0.15UF 0201 10%
6.3V X5R 6.3V
85 DP_INT_AUX_C_N 18 AUX-A
71 IN
DP_INT_ML_P<3> NC_DP_INT_ML_P<3> 85 71 BI DP_INT_AUX_N C4509 1 2 C4502 1 2
NO_TEST=TRUE MAKE_BASE=TRUE
0201 10%
0.1UF CERM-X5R 17 0.15UF 0201 10% DP_INTPNL_ML_P<1> OUT 40 85
D1+ 4
C 71 IN
DP_INT_ML_N<3> NC_DP_INT_ML_N<3>
NO_TEST=TRUE MAKE_BASE=TRUE
6.3V
71 41 OUT DP_INT_HPD HPD_A
D1- 5
85

85
DP_INTPNL_ML_C_P<1>
DP_INTPNL_ML_C_N<1> C4503 1
0.15UF
X5R 6.3V

2
0201 10%
DP_INTPNL_ML_N<1> OUT 40 85 C
85 41 DP_TBTSRC_ML_C_P<0> 25 D0+B X5R 6.3V

85 41 DP_TBTSRC_ML_C_N<0> 24 D0-B
23 AUX+ 6 DP_INTPNL_AUX_P BI 40 85
85 41 DP_TBTSRC_ML_C_P<1> D1+B
22 AUX- 7 DP_INTPNL_AUX_N BI 40 85
85 41 DP_TBTSRC_ML_C_N<1> D1-B
85 41 BI DP_TBTSRC_AUXCH_P C4510 1 2
15 1
0201 10%
0.1UF CERM-X5R
6.3V
85 DP_TBTSRC_AUX_C_P
14
AUX+B R4502 1R4503
DP_TBTSRC_AUX_C_N AUX-B HPD 8 DP_INTPNL_HPD 100K 100K
DP_TBTSRC_AUXCH_N C4511 1
85 40
2 IN
85 41 BI 0201 10%
5% 5%
0.1UF CERM-X5R 13 1/20W 1/20W
OUT DP_TBTSRC_HPD
6.3V
26 HPD_B MF MF
PD is on the CR page 2 201 2 201

58 11 DP_TBT_SEL 10 SEL =PP3V3_S0_INTDPMUX 41 70

IN
32 AUX_SEL
11 HPD_SEL

THMPAD GND

28
21
B 70 41
=PP3V3_S0_INTDPMUX
B
1
R4504 1 R4505
2.2K 2.2K
1% 1%
1/20W 1/20W
MF MF
201 2 2 201

85 41 IN DP_TBTSRC_ML_P<0> C4512 1 2 DP_TBTSRC_ML_C_P<0> 41 85

20% 6.3V
0.22UF X5R 0201

85 41 DP_TBTSRC_ML_N<0> C4513 1 2 DP_TBTSRC_ML_C_N<0> 41 85

IN
20% 6.3V DP_INT_DDC_DATA BI 71
0.22UF X5R 0201

85 41 DP_TBTSRC_ML_P<1> C4514 1 2 DP_TBTSRC_ML_C_P<1> 41 85

DP_INT_DDC_CLK IN 71
IN
20% 6.3V
0.22UF X5R 0201

85 41 IN DP_TBTSRC_ML_N<1> C4515 1 2 DP_TBTSRC_ML_C_N<1> 41 85

20% 6.3V
0.22UF X5R 0201

1 1 1 1
R4512 R4513 R4514 R4515
2.7K 2.7K 2.7K 2.7K
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
2 201 2 201 2 201 2 201

A SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
PAGE TITLE

Internal DP MUXing
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

L4601
FERR-120-OHM-3A
PP5V_S4_EXTA_ILIM 1 2 PP5V_S4_EXTA_F
VOLTAGE=5V 0603 VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM

L4602
120-OHM-90MA 1 1
C4605 1 1 C4607
DLP0NS
SYM_VER-1
CRITICAL CRITICAL EXT PORT A
0.01UF CRITICAL TSSLP-2-1 TSSLP-2-1
20% 0.1UF 4 3
2
CRITICAL 2
ESD0P2RF-02LS ESD0P2RF-02LS
16V
X7R-CERM 2
20%
10V
2 CERM D4601 D4606 D4602 D4603 CRITICAL
0402
ESD0P2RF-02LS ESD0P2RF-02LS J4600
D
402
1 2 TSSLP-2-1 TSSLP-2-1 2 2
USB-NO1-K70
F-ANG-TH
D
CRITICAL 1 1

1
VBUS
80 USB2_EXTA_N 2
D-
80 USB2_EXTA_P 3
D+
4
GND
80 USB3_EXTA_RX_N 5
CRITICAL STDA_SSRX-
6
70 =PP3V3_G3H_SMC_USBMUX L4603 80 USB3_EXTA_RX_P STDA_SSRX+
80OHM-25%-100MA 7
0504 GND_DRAIN
80 USB3_EXTA_TX_F_N 8
STDA_SSTX-
1 L2 80 USB3_EXTA_TX_F_P 9
C4606 1 R4605 STDA_SSTX+
0.1UF 100K 80 13 OUT USB3_EXTA_RX_F_N 4 3
20% 5% CRITICAL
10V 1/16W CRITICAL 2 10
CERM 2 2
402
2
MF-LF
402 1 D4604 D4605 11
USB3_EXTA_RX_F_P 2 ESD0P2RF-02LS

9
80 13 OUT ESD0P2RF-02LS TSSLP-2-1 12
L1 TSSLP-2-1
VCC 13
CKPLUS_WAIVE=ndifpr_badterm GND_VOID=TRUE
5 M+ 1
45 44 IN SMC_DEBUGPRT_TX_L CRITICAL Y+ 1 80 USB2_EXTA_MUXED_N 1 14
SMC_DEBUGPRT_RX_L 4 M- Y- 2 15
45 44 OUT U4610 USB2_EXTA_MUXED_P
16 SHIELD
CKPLUS_WAIVE=ndifpr_badterm PI3USB102EZLE CKPLUS_WAIVE=pdifpr_badterm
80 13 USB_EXTA_0_N 7 D+ TQFN 17
BI
6 D- CRITICAL 18
80 13 BI USB_EXTA_0_P
70 43 =PP5V_S4_USB CKPLUS_WAIVE=pdifpr_badterm L4604 19
8 OE* SEL 10 SMC_DEBUGPRT_EN_L 44
80OHM-25%-100MA 20
CRITICAL IN 0504
21
C4601 1 1
C4602 GND
L2 22
0.1UF 330UF-25MOHM

3
20% 20% SIGNAL_MODEL=PI3USB102_TQFN_PI3USB102ZLE_MOJO C4608 0.1UF
C 10V
CERM 2
402
2 6.3V
TANT
CASE-D2E
80 13 IN USB3_EXTA_TX_N 1
10% CERM-X5R
2 80 USB3_EXTA_TX_C_N
6.3V 0201
4 3
C
C4609 0.1UF
1
514-0817
CRITICAL 80 13 USB3_EXTA_TX_P 1 2 80 USB3_EXTA_TX_C_P 2
IN
10% CERM-X5R 6.3V 0201 L1
U4600
TPS2561DR GND_VOID=TRUE
SON
2 IN_0 OUT1 9
3 IN_1 OUT2 8
10 FAULT1* ILIM 7
18 13 OUT USB_EXTB_OC_L USB_ILIM1
6 FAULT2*
18 13 OUT USB_EXTA_OC_L

68 43 PM_EN_USB_PWR 4 EN1 R46021

5 EN2 11.5K
THRM 1%
1/16W
GND PAD MF-LF L4611
402 2 FERR-120-OHM-3A
1

USB_ILIM1_R PP5V_S4_EXTB_ILIM 1 2 PP5V_S4_EXTB_F

VOLTAGE=5V VOLTAGE=5V 1 1 EXT PORT B
MIN_LINE_WIDTH=0.6MM 0603 MIN_LINE_WIDTH=0.6MM CRITICAL CRITICAL
1 MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
CRITICAL TSSLP-2-1 TSSLP-2-1
R4603 ESD0P2RF-02LS ESD0P2RF-02LS CRITICAL
11.5K L4612 D4612 D4613
1%
1/16W
C4615 1 1 C4617 120-OHM-90MA
DLP0NS 2 5 3 4 2 2 J4610
0.01UF 0.1UF SYM_VER-1
USB-NO2-K70

NC
IO
NC
IO
MF-LF 20% 20%
402 2 16V 10V 4 3
USB_EXTB_8_P 6 VBUS F-ANG-TH
X7R-CERM 2 2 CERM 80 13 BI
0402 402
80 13 USB_EXTB_8_N 1 GND 1
BI
1 2 VBUS
80 USB2_EXTB_N 2
D-
80 USB2_EXTB_P 3
D4611 4
D+
RCLAMP0582N GND
B SLP1210N6
CRITICAL
80

80
USB3_EXTB_RX_N
USB3_EXTB_RX_P
5
6
STDA_SSRX- B
STDA_SSRX+
7
GND_DRAIN
80 USB3_EXTB_TX_F_N 8
STDA_SSTX-
80 USB3_EXTB_TX_F_P 9
STDA_SSTX+

CRITICAL CRITICAL
CRITICAL 2 10
2
L4613 D4614 D4615 11
80OHM-25%-100MA ESD0P2RF-02LS ESD0P2RF-02LS
TSSLP-2-1 12
0504 TSSLP-2-1
13
L2 1 1 14
USB3_EXTB_RX_F_N 4 3 15
80 13 BI
16 SHIELD
17
USB3_EXTB_RX_F_P 1 2
80 13 BI 18
L1 19
GND_VOID=TRUE 20
21
22
CRITICAL
L4614
80OHM-25%-100MA 514-0825
0504

L2
C4618 0.1UF
80 13 USB3_EXTB_TX_N 1 2 80 USB3_EXTB_TX_C_N 4 3
IN
10% CERM-X5R 6.3V 0201
A C4619
1
0.1UF
2 80 USB3_EXTB_TX_C_P 1 2
SYNC_MASTER=J16_KOSECOFF SYNC_DATE=03/18/2013 A
80 13 IN USB3_EXTB_TX_P PAGE TITLE
10% CERM-X5R 6.3V 0201 L1
GND_VOID=TRUE
EXTERNAL USB PORTS A & B
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

CRITICAL 1 1 EXT PORT C

C4705 1 1 C4707 L4702
CRITICAL
TSSLP-2-1
CRITICAL
TSSLP-2-1
0.01UF 120-OHM-90MA 2 5 3 4
ESD0P2RF-02LS ESD0P2RF-02LS CRITICAL
20% 0.1UF DLP0NS

NC
IO
NC
IO
16V
X7R-CERM 2
20%
10V
2 CERM
SYM_VER-1
6 VBUS
D4702 D4703 J4700
0402 USB_EXTC_1_P 4 3 2 2
80 13

D
402 BI
1 GND USB-NO3-K70
F-ANG-TH D
80 13 USB_EXTC_1_N 1 2
BI 1
VBUS
D4701 80 USB2_EXTC_N 2
D-
RCLAMP0582N 80 USB2_EXTC_P 3
SLP1210N6 D+
CRITICAL 4
GND
80 USB3_EXTC_RX_N 5
CRITICAL STDA_SSRX-
6
L4703 80 USB3_EXTC_RX_P
STDA_SSRX+
80OHM-25%-100MA 7
0504 GND_DRAIN
80 USB3_EXTC_TX_F_N 8
STDA_SSTX-
L2 80 USB3_EXTC_TX_F_P 9
STDA_SSTX+
80 13 USB3_EXTC_RX_F_N 4 3
OUT CRITICAL
CRITICAL 2 10
2
70 42 =PP5V_S4_USB 1 D4704 D4705 11
80 13 OUT USB3_EXTC_RX_F_P 2 ESD0P2RF-02LS ESD0P2RF-02LS
TSSLP-2-1 12
L1 TSSLP-2-1
13
CRITICAL GND_VOID=TRUE 1
1 14
C4701 1 1
C4702 15
0.1UF 330UF-25MOHM CRITICAL
20% 20% 16 SHIELD
10V
CERM 2 2 6.3V
TANT
L4704 17
402 CASE-D2E 80OHM-25%-100MA
CRITICAL 0504 18
U4700 L2
19
TPS2561DR C47081 0.1UF 20
SON USB3_EXTC_TX_N 2 80 USB3_EXTC_TX_C_N 4 3
80 13 IN 21
2 IN_0 OUT1 9 10% CERM-X5R 6.3V 0201
22
3 IN_1 OUT2 8 C47091 0.1UF
USB3_EXTC_TX_P 2 80 USB3_EXTC_TX_C_P 1 2
C 18 13 OUT USB_EXTD_OC_L
10 FAULT1* ILIM 7
6 FAULT2*
USB_ILIM2
80 13 IN
10% CERM-X5R 6.3V 0201 L1
J16:514-0826
C
18 13 OUT USB_EXTC_OC_L GND_VOID=TRUE
J17:514-0841
68 42 PM_EN_USB_PWR 4 EN1 R47021
5 EN2 11.5K
THRM 1%
PAD 1/16W
GND MF-LF
402 2
1

USB_ILIM2_R

R47031
11.5K
1%
1/16W
MF-LF
402 2
L4711
FERR-120-OHM-3A 1 1
PP5V_S4_EXTD_ILIM
1 2 PP5V_S4_EXTD_F CRITICAL CRITICAL EXT PORT D
VOLTAGE=5V VOLTAGE=5V TSSLP-2-1 TSSLP-2-1
MIN_LINE_WIDTH=0.6MM 0603 MIN_LINE_WIDTH=0.6MM CRITICAL
ESD0P2RF-02LS ESD0P2RF-02LS
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
CRITICAL D4712 D4713 J4710
L4712 2 2

C4715 1 120-OHM-90MA
DLP0NS 2 5 3 4 USB-NO4-K70
1 C4717 SYM_VER-1 F-ANG-TH

NC
IO
NC
IO
0.01UF
20% 0.1UF 80 13 BI USB_EXTD_9_P 4 3 6 VBUS
16V 20% 1
X7R-CERM 2 10V VBUS
0402 2 CERM 2
1 GND 80 USB2_EXTD_N
402 D-
80 13 BI USB_EXTD_9_N 1 2 80 USB2_EXTD_P 3
D+
4
GND
D4711 80 USB3_EXTD_RX_N 5
STDA_SSRX-
RCLAMP0582N 80 USB3_EXTD_RX_P 6
B SLP1210N6
CRITICAL 7
8
STDA_SSRX+
GND_DRAIN
B
80 USB3_EXTD_TX_F_N STDA_SSTX-
80 USB3_EXTD_TX_F_P 9
STDA_SSTX+

CRITICAL CRITICAL CRITICAL

2 2 10
L4713 D4714 D4715 11
80OHM-25%-100MA ESD0P2RF-02LS ESD0P2RF-02LS
0504 TSSLP-2-1 12
TSSLP-2-1
13
L2 1 1
14
80 13 OUT USB3_EXTD_RX_F_N 4 3 15
16 SHIELD
1
17
80 13 USB3_EXTD_RX_F_P 2
OUT 18
L1
19
GND_VOID=TRUE
20
21
CRITICAL 22
L4714
80OHM-25%-100MA
0504
J16:514-0827
L2 J17:514-0842
C47181 0.1UF
2 80 USB3_EXTD_TX_C_N 4
80 13 USB3_EXTD_TX_N 3
IN
10% CERM-X5R 6.3V 0201

C4719 0.1UF
80 13 USB3_EXTD_TX_P 1 2 80 USB3_EXTD_TX_C_P 1 2
IN
10% CERM-X5R 6.3V 0201 L1
A GND_VOID=TRUE
SYNC_MASTER=J16_KOSECOFF SYNC_DATE=03/18/2013 A
PAGE TITLE

EXTERNAL USB PORTS C & D

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
47 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 43 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
L5001
70 51 45 =PP3V3_G3H_SMC 30-OHM-1.7A
those designated as inputs require pull-ups. 1 2 PP3V3_G3H_SMC_VDDA
MIN_LINE_WIDTH=0.25 MM
0402 MIN_NECK_WIDTH=0.1 MM
VOLTAGE=3.3V
1 C5001
C5002 1 1 C5003 1 C5004 1 C5005 1 C5006 0.1UF
1UF 0.1UF 0.1UF 0.1UF 0.1UF 1 10%
10% 10% 10% 10% R5002 6.3V
20%
10V
X5R-CERM 2 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 1M U5000 2 CERM-X5R
0201
0603-1 0201 0201 0201 0201 5%
1/20W
LM4FSXAH5BB
MF BGA
201
2 (2 OF 2)
46 45 SMC_RESET_L G10 RST* SWCLK/TCK C10 SMC_TCK 45 46
IN
SWDIO/TMS A10 SMC_TMS 45 46

D
1 C5007
0.1UF
10%
1 C5008
0.1UF
10%
1 C5009
0.1UF
10%
45 32 BI AP_EVENT_L (OD) B11
N13
PK4/RTCCLK SWO/TDO A11
B10
SMC_TDO 45 46 D
6.3V 6.3V 6.3V
SMC_WAKE_L WAKE* OMIT_TABLE TDI SMC_TDI 45 46
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R M12
0201 0201 0201
NC_SMC_HIB_L HIB*
NO_TEST=TRUE A2
NC NC
79 45 SMC_CLK32K M10 XOSC0
IN
NC_SMC_XOSC1 N10 XOSC1
NO_TEST=TRUE
U5000 VDDA D3
PP3V3_G3H_AVREF_SMC 45
LM4FSXAH5BB 81 45 SMC_EXTAL G12 OSC0
BGA 81 45 SMC_XTAL G13 OSC1 VREFA+ D2
79 46 13 BI LPC_AD<0> arch B13 LPC0AD0 (1 OF 2) AIN00 E2 proj analog SMC_ADC0 IN 45 PLACE_NEAR=U5000.D1:4mm
VREFA- D1 PLACE_NEAR=U5000.D2:4mm
79 46 13 BI LPC_AD<1> arch A13 LPC0AD1 AIN01 E1 proj analog SMC_ADC1 IN 45 XW5000
K12 VBAT SM C5020 1 1 C5021
79 46 13 BI LPC_AD<2> arch C12 LPC0AD2 OMIT_TABLE AIN02 F2 proj analog SMC_ADC2 IN 45
C3 2 1 1.0UF 0.01UF
79 46 13 BI LPC_AD<3> arch D11 LPC0AD3 AIN03 F1 proj analog SMC_ADC3 IN 45
20% 10%
D7 GNDA E3 PLACE_NEAR=U5000.A1:4MM 6.3V 2 2 10V
LPC_CLK33M_SMC H12 B3 SMC_ADC4 X5R X5R-CERM
79 19 IN arch LPC0CLK AIN04 proj analog IN 45 E6 0201-1 0201
79 46 13 LPC_FRAME_L arch D12 LPC0FRAME* AIN05 A3 proj analog SMC_ADC5 45
IN
SMC_LRESET_L arch C13 LPC0RESET* AIN06 B4 proj analog SMC_ADC6
IN 1 C5010 1 C5011 1 C5012 E8 A1
81 20 IN IN 45
1UF 1UF 1UF E9 C7
46 13 LPC_SERIRQ arch od H13 LPC0SERIRQ AIN07 A4 proj analog SMC_ADC7 45
10% 10% 10%
BI IN 6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
F10 VDD D9
46 45 12 OUT PM_CLKRUN_L arch od G11 LPC0CLKRUN* AIN08 B5 proj analog SMC_ADC8 IN 45
402 402 402 J7 E5
46 20 12 LPC_PWRDWN_L arch F13 LPC0PD* AIN09 A5 proj analog SMC_ADC9 45
GND_SMC_AVSS 45 48 49 81
IN IN J9 F9
81 14 SMC_RUNTIME_SCI_L arch F12 LPC0SCI* AIN10 B6 proj analog SMC_ADC10 45
OUT IN J10 H5
81 14 OUT SMC_WAKE_SCI_L arch B12 PK5 AIN11 A6 proj analog SMC_ADC11 IN 45
H9
AIN12 C1 proj analog SMC_ADC12 45
GND
IN PP1V2_G3H_SMC_VDDC J1 J5
81 47 SMBUS_SMC_0_S0_SCL arch od E10 I2C0SCL AIN13 C2 proj analog SMC_ADC13 45 MIN_LINE_WIDTH=0.25 MM
BI IN
MIN_NECK_WIDTH=0.1 MM
J6 J8
81 47 SMBUS_SMC_0_S0_SDA arch od D13 I2C0SDA AIN14 B1 proj analog SMC_ADC14 45 VOLTAGE=1.2V
BI IN 1 1 1 1 1 VDDC J11
SMBUS_SMC_1_S0_SCL M4 B2 SMC_ADC15
C5013 C5014 C5015 C5016 C5017 K13
81 47 BI arch od I2C1SCL AIN15 proj analog IN 45
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF D6 K11
81 47 SMBUS_SMC_1_S0_SDA arch od N2 I2C1SDA AIN16 G2 proj analog SMC_ADC16 45
10% 10% 10% 10% 10%
BI IN 6.3V 6.3V 6.3V 6.3V 6.3V
N8 G1 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
81 47 BI SMBUS_SMC_2_S4_SCL arch od I2C2SCL AIN17 proj analog SMC_ADC17 IN 45
0201 0201 0201 0201 0201
C 81 47

81 47
BI SMBUS_SMC_2_S4_SDA
SMBUS_SMC_3_SCL
arch
arch
od
od
M8
L8
I2C2SDA
I2C3SCL
AIN18
AIN19
H1
H2
proj
proj
analog
analog
SMC_ADC18
SMC_ADC19
IN 45

45
C
BI IN
81 47 SMBUS_SMC_3_SDA arch od K8 I2C3SDA AIN20 B7 proj analog SMC_ADC20 45
BI IN
45 BI SMBUS_SMC_4_ASF_SCL arch od N7 I2C4SCL AIN21 A7 proj analog SMC_ADC21 IN 45

45 BI SMBUS_SMC_4_ASF_SDA arch od M7 I2C4SDA AIN22 B8 proj analog SMC_ADC22 IN 45

81 45 SMBUS_SMC_5_G3H_SCL arch od N4 I2C5SCL AIN23 A8 proj analog SMC_ADC23 45

BI IN
81 45 SMBUS_SMC_5_G3H_SDA arch od N3 I2C5SDA
BI
C0- K2 arch analog CPU_PROCHOT_L 6 45 61 62 76
IN
81 51 OUT SMC_FAN_0_CTL arch H11 PM6/FAN0PWM0 C0+ K1 arch analog SMC_VCCIO_CPU_DIV2 IN 45

81 51 IN SMC_FAN_0_TACH arch L13 PM7/FAN0TACH0 C1- L2 arch analog SMC_S5_PWRGD_VIN IN 45

51 OUT SMC_FAN_1_CTL arch C11 PK6/FAN0PWM1 PC5/C1+ L1 arch SPI_DESCRIPTOR_OVERRIDE_L OUT 19

51 SMC_FAN_1_TACH arch A12 PK7/FAN0TACH1 T3CCP1/PJ5/C2- C5 arch SMC_CPU_CATERR_L 45

IN IN
45 SMC_TOPBLK_SWP_L arch G3 PN2/FAN0PWM2 T3CCP0/PJ4/C2+ D5 arch analog CPU_THRMTRIP_3V3 45
OUT IN
45 SMC_PN3 proj D10 PN3/FAN0TACH2
IN
SSI0CLK/PA2 M2 arch SMC_PM_G2_EN 45 60
OUT
45 OUT SMC_PN4 proj L11 PN4/FAN0PWM3 SSI0FSS/PA3 M3 arch PM_DSW_PWRGD OUT 45 69

45 SMC_PN5 proj N12 PN5/FAN0TACH3 SSI0RX/PA4 L4 arch SMC_DELAYED_PWRGD 28 45 69

OUT OUT
45 32 SMC_G3_WAKESRC_EN arch N11 PN6/FAN0PWM4 SSI0TX/PA5 N1 arch SMC_PROCHOT 45
OUT OUT
45 SMC_PN7 proj M11 PN7/FAN0TACH4
IN
45 IN SMC_PH2 proj J4 PH2/FAN0PWM5 U1RX/B0 F11 arch SMC_DEBUGPRT_RX_L IN 42 45

45 SMC_PH3 proj J2 PH3/FAN0TACH5 U1TX/PB1 E11 arch SMC_DEBUGPRT_TX_L 42 45

OUT OUT
T0CCP0/PB6 F4 arch pwm SMC_SYS_LED OUT 45

76 45 14 6 IN CPU_PECI arch analog C4 PECI0RX T0CCP1/PB7 F3 arch SMC_GFX_THROTTLE_L OUT 45

76 45 OUT SMC_PECI_L arch C6 PECI0TX

SSI1RX/PF0 M9 arch SPI_SMC_MISO IN 46 79

45 SMC_PP0 proj int M13 PP0/IRQ116 SSI1TX/PF1 N9 arch SPI_SMC_MOSI 46 79

IN OUT
L12
B 45

45 32
IN
IN
SMC_DP_HPD_L
SMC_PME_S4_WAKE_L
proj
proj
int
int M5
PP1/IRQ117
PP2/IRQ118
SSI1CLK/PF2
SSI1FSS/PF3
L10
K10
arch
arch
SPI_SMC_CLK
SPI_SMC_CS_L
OUT
OUT
46 79

46 79
B
45 SMC_PME_S4_DARK_L proj int J12 PP3/IRQ119 PF4 L9 arch S5_PWRGD 69
IN IN
45 SMC_PP4 proj int J13 PP4/IRQ120 PF5 K9 arch SMC_PM_PCH_SYS_PWROK IN 45
OUT
45 IN SMC_PP5 proj int L5 PP5/IRQ121
45 IN SMC_PP6 proj int D8 PP6/IRQ122 WT0CCP0/PG4 K7 arch SMC_DEBUGPRT_EN_L OUT 42

45 SMC_PP7 proj int K6 PP7/IRQ123 WT0CCP1/PG5 L7 arch SMC_GFX_OVERTEMP 45

IN IN

45 OUT ENET_ASF_GPIO arch od D4 PQ0/IRQ124 WT2CCP0/PH0 K3 arch ALL_SYS_PWRGD IN 3 21 69

45 IN SMS_INT_L arch int E4 PQ1/IRQ125 WT2CCP1/PH1 K4 arch SMC_THRMTRIP OUT 45

45 IN SMC_BC_ACOK arch int F5 PQ2/IRQ126

45 G3_POWERON_L arch int N5 PQ3/IRQ127 WT3CCP0/PH4 J3 arch od PM_PWRBTN_L 12 18
IN OUT
69 68 45 36 21 12 PM_SLP_S3_L arch int N6 PQ4/IRQ128 WT3CCP1/PH5 H4 arch PM_SYSRST_L 12 19
IN OUT
68 12 PM_SLP_S4_L arch int K5 PQ5/IRQ129 WT4CCP0/PH6 H3 arch od MEM_EVENT_L 23 24 45
IN OUT
68 32 12 PM_SLP_S5_L arch int M6 PQ6/IRQ130 WT4CCP1/PH7 G4 proj SMC_PH7 45
IN OUT
45 SMC_ONOFF_L arch int L6 PQ7/IRQ131
IN
T1CCP0/PJ0 C9 arch SMC_OOB1_D2R_L 34 81
IN
46 45 SMC_RX_L arch L3 U0RX T1CCP1/PJ1 B9 arch SMC_OOB1_R2D_L 34 81
IN OUT
46 45 SMC_TX_L arch M1 U0TX T2CCP0/PJ2 A9 proj SMC_PJ2 45
OUT IN
T2CCP1/PJ3 C8 proj SMC_PJ3 45
OUT
45 SMC_PL7 arch E13 USB0DM
BI
45 BI SMC_PL6 arch E12 USB0DP WT5CCP1/PM3 H10 arch SMC_BATLOW_L OUT 45

A SYNC_MASTER=J16_TONY SYNC_DATE=03/13/2013 A
PAGE TITLE

SMC
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
50 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 44 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ADC Channel Aliases
SMC Supervisor and AVREF Supply 44 SMC_ADC0 VSNS_P12VG3H 48 81
Project-specific Aliases SMC 32KHz Clock
MAKE_BASE=TRUE
44 SMC_PN5 ACDC_BURST_EN_L 45
44 SMC_ADC1 ISNS_P12VG3H 48 81 MAKE_BASE=TRUE R5160
70 51 45 44 =PP3V3_G3H_SMC MAKE_BASE=TRUE
44 SMC_PJ3 SMC_OOB2_R2D_L 33 81 22
R5102 44 SMC_ADC4 VSNS_PVDDQS0 49 81 MAKE_BASE=TRUE 79 12 IN PM_CLK32K_SUSCLK_R 2 1 SMC_CLK32K OUT 44 79

1
47 2
MAKE_BASE=TRUE
SMC_PJ2 SMC_OOB2_D2R_L PLACE_NEAR=U1100.W36:10MM 5%
51 45 44 =PP3V3_G3H_SMC PP3V42_G3H_SMC_SPVSR SMC_ADC5 ISNS_PVDDQS0
44
MAKE_BASE=TRUE
33 81
1/16W
70 44 49 81
MIN_LINE_WIDTH=0.4MM MAKE_BASE=TRUE MF-LF
5% MIN_NECK_WIDTH=0.1MM SMC_PP0 SMC_ACDC_ID 402
1/16W 1 C5102 VOLTAGE=3.42V 44 60
MF-LF 44 SMC_ADC6 VSNS_VDDQS3_DDR 49 81 MAKE_BASE=TRUE
402 4.7UF MAKE_BASE=TRUE
20%
6.3V 44 SMC_ADC7 ISNS_VDDQS3_DDR 49 81
44 SMC_PH2 SMC_ASSERT_RTCRST
MAKE_BASE=TRUE
45 SMC Crystal
2 X5R-CERM1 MAKE_BASE=TRUE NOTE: SMC team wants 12MHz for this Xtal
402 1 SMC_PL6 SMC_WIFI_PWR_EN
R5105 44 SMC_ADC10 VSNS_CPUVCC 48 81
44
MAKE_BASE=TRUE
45
SMC_EXTAL 44 81
100K MAKE_BASE=TRUE

D 70 =PPVIN_G3H_SMCVREF
5%
1/16W
MF-LF
44 SMC_ADC11 ISNS_CPUVCC
MAKE_BASE=TRUE
48 81
Unused Project-specific
D
2 402 NOSTUFF 1
44 SMC_ADC14 VSNS_HDDS0 48 81 44 SMC_S5_PWRGD_VIN NC_SMC_S5_PWRGD_VIN R5166

3
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
1M
C5100 1 V+ VIN 44 SMC_ADC15 ISNS_HDDS0 48 81 44 SMC_PL7 NC_SMC_PL7 5%
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 1/16W
0.47UF
10%
U5100 44 SMC_ADC17 VSNS_P1V05S0_PCH 48 81 44 SMC_PN3 NC_SMC_PN3
MF-LF
402 2
6.3V
CERM-X5R 2
VREF-3.3V-VDET-3.0V R5103 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
CRITICAL
DFN 5% 1/20W SMC_ADC19 ISNS_P3V3S4_AP SMC_PN4 NC_SMC_PN4
402 0 44 48 81 44
NC
6 MR1* (ipu)
SN0903049 RESET* 5 SMC_RESET_R_L 2 1 SMC_RESET_L OUT 44 46 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE Y5165 R5165
7 MR2* (ipu) MF 0201
44 SMC_ADC20 ISNS_SSDS0 49 81 44 SMC_PP4 NC_SMC_S4_WAKESRC_EN 12.000MHZ-50PPM-8PF-100OHM 0
NC MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 1 2 SMC_XTAL_R 2 1 SMC_XTAL 44 81

SMC_MANUAL_RST_L 4 DELAY CRITICAL REFOUT 8 PP3V3_G3H_AVREF_SMC 44 44 SMC_ADC21 VSNS_P3V3S5 49 81 44 SMC_PN7 NC_SMC_PN7 5%

MIN_LINE_WIDTH=0.4MM MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 5X3.2X1.2-SM 1/16W
THRM MIN_NECK_WIDTH=0.1MM C5165 1 1 C5166 MF-LF
GND PAD VOLTAGE=3.3V 44 SMC_PP5 NC_SMC_PP5 402
NOSTUFF MAKE_BASE=TRUE NO_TEST=TRUE 12PF 12PF
5% 5%
2

9
C5101 1 C5103 1
0.01UF
C5105 1 1 C5106
1000PF
Unused ADC Channels 44 SMC_PP6 NC_SMC_PP6
MAKE_BASE=TRUE NO_TEST=TRUE
50V
C0G-CERM 2 2 50V
C0G-CERM
10% 1UF 0.01UF 5%
0402 0402
16V 20% 10% 25V 44 SMC_PP7 NC_SMC_PP7
X7R-CERM 2 10V 16V CERM 2 SMC_PH3 NC_SMC_PH3
0402 X5R-CERM 2 2 X7R-CERM
0402
44 MAKE_BASE=TRUE NO_TEST=TRUE
0603-1 0402 MAKE_BASE=TRUE NO_TEST=TRUE
44 SMC_DP_HPD_L NC_SMC_DP_HPD_L
44 SMC_ADC2 NC_VSNS_P12VS0_GPUCORE MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
44 SMC_PME_S4_DARK_L NC_SMC_PME_S4_DARK_L
44 SMC_ADC3 NC_ISNS_P12VS0_GPUCORE MAKE_BASE=TRUE NO_TEST=TRUE
GND_SMC_AVSS MAKE_BASE=TRUE NO_TEST=TRUE
MIN_LINE_WIDTH=0.4MM
44 48 49 81
SMC_ADC8 NC_VSNS_P12VS0_FBVDDQ
44 SMC_PH7 TP_SMC_PH7 R5148
Note: IPU are pulled to VIN rail MIN_NECK_WIDTH=0.1MM 44 TP for access if ZPB re-intstated MAKE_BASE=TRUE NO_TEST=TRUE 0
VOLTAGE=0V MAKE_BASE=TRUE NO_TEST=TRUE PM_PCH_SYS_PWROK 2 1 SMC_PM_PCH_SYS_PWROK
44 SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SCL 69 18 12 IN OUT 44
44 SMC_ADC9 NC_ISNS_P12VS0_FBVDDQ MAKE_BASE=TRUE NO_TEST=TRUE 5%
MAKE_BASE=TRUE NO_TEST=TRUE 1/20W
44 SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF_SDA MF
SMC_ADC12 NC_VSNS_GPUCORE_ALT
SMC Controlled RTC Reset 44
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 0201
To absorb current from discharging RTC Reset CAP
81 44 SMBUS_SMC_5_G3H_SCL NC_SMBUS_SMC_5_G3H_SCL
R5194 44 SMC_ADC13 NC_ISNS_GPUCORE_ALT MAKE_BASE=TRUE NO_TEST=TRUE
330 MAKE_BASE=TRUE NO_TEST=TRUE
SMBUS_SMC_5_G3H_SDA NC_SMBUS_SMC_5_G3H_SDA
R5149
Power Button CRITICAL RTC_RESET_L_R 1 2 RTC_RESET_L OUT 11 19
44 SMC_ADC16 NC_SMC_ADC16
81 44
MAKE_BASE=TRUE NO_TEST=TRUE CPU_CATERR_L 2
0
1 SMC_CPU_CATERR_L
Q5199 5% MAKE_BASE=TRUE NO_TEST=TRUE
SMC_BATLOW_L NC_SMC_BATLOW_L
76 6 IN OUT 44

1/16W 44 5%
SSM3K15AMFVAPE
C 70 51 45 44 =PP3V3_G3H_SMC
SILK_PART=PwrBtn
VESM
D 3 MF-LF
402
44

44
SMC_ADC18

SMC_ADC22
NC_SMC_ADC18
MAKE_BASE=TRUE
NC_SMC_ADC22
NO_TEST=TRUE 44 SMC_GFX_THROTTLE_L
MAKE_BASE=TRUE
NC_SMC_GFX_THROTTLE_L
MAKE_BASE=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
1/20W
MF
0201
C
1 MAKE_BASE=TRUE NO_TEST=TRUE 44 SMC_GFX_OVERTEMP NC_SMC_GFX_OVERTEMP
R5120 MAKE_BASE=TRUE NO_TEST=TRUE
DEVELOPMENT 10K 44 SMC_ADC23 NC_SMC_ADC23 R5154
5% MAKE_BASE=TRUE NO_TEST=TRUE 1K
J5120 1/20W
MF
1 G S 2 44 IN SMC_TOPBLK_SWP_L 1 2 PCH_STRP_TOPBLK_SWP_L OUT 12

NTC020AA1JB260T SMC_ASSERT_RTCRST 5%
2 201 45
1/20W
SM NOSTUFF MF
1 2 SMC_ONOFF_L
MAKE_BASE=TRUE
OUT 44 R51991 1 C5199
201
10K 1.0UF
5% 20%
PWR_BTN OUT 60 1/16W
MF-LF 2 6.3V
X5R-CERM Arch Pull Up/Down
402 2 0402
3 4 Platform Thermal Control 70 =PP3V3_S0_SMC

44 24 23 MEM_EVENT_L R5170 10K 1 2 5% 1/20W

PM_THRMTRIP_L_R MF 201
CRITICAL OUT 14
46 44 12 PM_CLKRUN_L R5171 10K 1 2 5% 1/20W
MF 201
Q5123
SSM3K15AMFVAPE D 3 70 45 =PP3V3_S5_SMC 70 51 45 44 =PP3V3_G3H_SMC
VESM
44 ENET_ASF_GPIO R5175 10K 1 2 5% 1/20W
This allows SMC to shutdown system. 1 MF 201
Comparator Reference SMC control for AirPort power R5128 44 G3_POWERON_L R5176 10K 1 2 5% 1/20W
10K MF 201
5%
1/20W R5178
70 45 =PP1V05_S0_SMC 1 G S 2 MF 44 SMC_BC_ACOK 100K 1 2 5% 1/20W
=PP3V3_S4_AP R5125 201 2 MF 201
SMC_SYS_LED NOSTUFF R5179
70 32
1 44 100K 1 2 5% 1/20W
R5130 1 1K R5180 MF 201
SMC_ROMBOOT 2 1 SMS_INT_L 10K 1 2 5% 1/20W
10K R5142 46 IN CPU_THRMTRIP_3V3 OUT 44
44
MF 201
1% 100K Note: For SMC recovery mode 5% 44 32 SMC_PME_S4_WAKE_L R5181 10K 1 2 5% 1/20W
1/16W 5% 1/20W MF 201
MF-LF 1/20W MF
402 2 MF 201
PLACE_NEAR=U5000.K1:5MM 201 2 44 IN SMC_THRMTRIP 3 CRITICAL
R5127 32 PP3V3_S4_AP_FET
B PLACE_NEAR=U5000.K1:5MM
SMC_VCCIO_CPU_DIV2
PLACE_NEAR=U5000.K1:3MM
OUT 44 45 IN SMC_WIFI_PWR_EN AP_PWR_EN
MAKE_BASE=TRUE
OUT 32
R51261 76 14 6 IN PM_THRMTRIP_L 2
3.3K
1 CPU_TT_OC_L 1 Q5127 44 32 AP_EVENT_L R5185 10K 1 2 5% 1/20W
B
10K BC846BLP MF 201
R51311 1 C5131
5%
1/20W
5%
1/20W DFN1006H4-3 44 32 SMC_G3_WAKESRC_EN R5118 100K 1 2 5% 1/20W
10K 0.1UF MF MF 2 MF 201
1% 201 2 201
1/16W 10%
16V
MF-LF 2 X7R-CERM
402 2 0402 R5186
69 44 28 SMC_DELAYED_PWRGD 100K 1 2 5% 1/16W
MF-LF 402
69 44 PM_DSW_PWRGD R5184 100K 1 2 5% 1/16W
This passes CPU’s TRHMTRIP to SMC so shutdown reason can be recorded. MF-LF 402
60 44 SMC_PM_G2_EN R5187 100K 1 2 5% 1/20W
MF 201
Note:

70 =PP3V3_S4_SMC Note: PECI Support Serial/JTAG Interface Pull-ups

Open-drain stage on S4 to account Level-shifter that allows SMC to drive PECI
R51411 case when SMC is initializing in S5, Place this circuit near the Tee point to minimize reflections
70 45 =PP3V3_S5_SMC 10K 70 51 45 44 =PP3V3_G3H_SMC
5% and chip is not yet configured. 70 45 =PP1V05_S0_SMC
1/20W R5190
MF and ACDC_BURST_EN_L could be floating. 46 44 SMC_TX_L 10K 1 2 5% 1/20W
R51401 201 2 CRITICAL
SMC_RX_L R5191 100K 1
MF
2 5%
201
1/20W
10K BURSTMODE_EN_L SMC_PECI_L Q5135 46 44
MF 201
5%
OUT 60 65 76 44 IN
SSM3K15AMFVAPE D 3 44 42 SMC_DEBUGPRT_TX_L R5192 20K 1 2 5% 1/20W
1/20W AC/DC Burst Mode Enable R5193 MF 201
MF
201 2
D 6 PROCHOT Support R51351 VESM 44 42 SMC_DEBUGPRT_RX_L 20K 1 2 5%
MF
1/20W
201
CRITICAL 0
Level-shifter that allows SMC to drive PROCHOT 5% R5195
Q5140 1/16W 46 44 SMC_TCK 10K 1 2 5%
MF
1/20W
201
SSM6N15AFE MF-LF R5196
402 2 R5138 46 44 SMC_TDI 10K 1 2 5% 1/20W
SOT563 CPU_PROCHOT_L 1 G S 2 MF 201
CRITICAL
BI 6 44 61 62 76
43 46 44 SMC_TDO R5197 10K 1 2 5% 1/20W
2 G S 1 Q5125 SMC_PECI_L_R CPU_PECI_R 2 1 CPU_PECI BI 6 14 44
R5198 MF 201
76 46 44 SMC_TMS 10K 1 2 5% 1/20W
ACDC_BURST SSM3K15AMFVAPE D 3 OMIT 5% MF 201
1/16W
VESM 1 1 MF-LF
CRITICAL R5136 R5137 402
Q5140 D 3 NOSTUFF 330
=PP3V3_S5_SMC
A SSM6N15AFE
SOT563
70 45

1 C5140
NONE
NONE
NONE
402 2
5%
1/16W
MF-LF SYNC_MASTER=J16_TONY SYNC_DATE=03/13/2013 A
2 402 PAGE TITLE
0.1UF 1 G S 2
10%
6.3V
2 CERM-X5R 44 IN SMC_PROCHOT
SMC Support
5 G S 4 0201 DRAWING NUMBER SIZE

45 ACDC_BURST_EN_L Apple Inc. 051-0164 D

IN
5 REVISION
R
2
A 12.4.0
4 PM_SLP_S3_BUF_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
1
U5140Y
69 68 44 36 21 12 PM_SLP_S3_L B THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
CRITICAL 3 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
TC7SZ08FEAPE
SOT665
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
51 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 45 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SPI BootROM LPC+SPI Connector D

D MATT CONNECTOR
LPCPLUS
70 =PP3V3_S5_ROM CRITICAL
J5200
DF40C-30DP-0.4V
M-ST-SM
CRITICAL

8
1 1
R5212 R5211 C5210 1 70 =PP3V3_G3H_LPCPLUS 31 32
100K 3.3K 1UF VDD 70 =PP5V_S0_LPCPLUS
5% 5% 10%
1/16W 1/16W 6.3V
2 1 2 SPI_ALT_MISO IN 46 79
MF-LF
402
2
MF-LF
402
2
CERM
402 U5210 79 19 LPC_CLK33M_LPCPLUS 3 4 LPC_FRAME_L 13 44 79
64MBIT IN IN
SOIC 79 44 13 BI LPC_AD<0> 5 6 SPIROM_USE_MLB OUT 14 46 79
79 46 IN SPI_MLB_CLK 6 SCK SI 5 SPI_MLB_MOSI IN 46 79
7 8
SST25VF064C 79 44 13 LPC_AD<2> 9 10 PM_CLKRUN_L 12 44 45
BI OUT
79 46 IN SPI_MLB_CS_L 1 CE* 79 44 13 BI LPC_AD<1> 11 12 SPI_ALT_CLK IN 46 79
SO 2 SPI_MLB_MISO OUT 46 79
SPI_WP_L 3 WP* OMIT_TABLE 79 44 13 BI LPC_AD<3> 13 14 SPI_ALT_CS_L IN 46 79

79 46 14 IN SPIROM_USE_MLB 7 HOLD* 79 46 IN SPI_ALT_MOSI 15 16 LPC_SERIRQ BI 13 44

VSS 14 OUT LPCPLUS_GPIO 17 18 LPC_PWRDWN_L IN 12 20 44

DEBUG_RESET_L 19 20 SMC_TDI

4
20 IN OUT 44 45

45 44 OUT SMC_TDO 21 22 SMC_TCK OUT 44 45

TP_SMC_TRST_L 23 24 SMC_RESET_L OUT 44 45

TP_SMC_MD1 25 26 SMC_ROMBOOT OUT 45

45 44 IN SMC_TX_L 27 28 SMC_RX_L OUT 44 45

29 30 SMC_TMS OUT 44 45

33 34

C C
516s1039

SPI Series Termination

SPI_ALT_MISO 46 79

SPI_ALT_MOSI 46 79

SPI_ALT_CLK 46 79

SPI_ALT_CS_L 46 79

1 1 1 1
R5223 R5224 R5225 R5226 PLACE_NEAR=J5200.11:5mm
PLACE_NEAR=J5200.9:5mm
24 43 43 43 PLACE_NEAR=J5200.12:10mm
5% 5% 5% 5% PLACE_NEAR=J5200.14:5mm
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402

R5220 R5227
PLACE_NEAR=U1100.AJ7:11MM 15 43
79 13 SPI_CS0_R_L 1 2 79 SPI_CS0_L 1 2 SPI_MLB_CS_L 46 79

B IN

R5221
5%
1/16W
PLACE_NEAR=R5226.2:5mm

R5228 1/16W
5%
OUT
B
MF-LF MF-LF
PLACE_NEAR=U1100.AJ11:12.5MM 15 402 43 402
79 13 SPI_CLK_R 1 2 79 SPI_CLK 1 2 SPI_MLB_CLK 46 79
IN OUT
PLACE_NEAR=R5225.2:5mm
5% 5%
R5222 1/16W
MF-LF R5229 1/16W
MF-LF
15 402 43 402
79 13 SPI_MOSI_R 1 2 79 SPI_MOSI 1 2 SPI_MLB_MOSI OUT 46 79
IN
5% PLACE_NEAR=R5224.2:5mm 5%
PLACE_NEAR=U1100.AH1:18.5MM
1/16W 1/16W
MF-LF R5230 MF-LF
402 24 402
79 13 SPI_MISO 1 2 SPI_MLB_MISO 46 79
OUT IN
5% PLACE_NEAR=U5210.2:5MM
1/16W
MF-LF
402

SMC SPI Support

R5250
24
79 44 SPI_SMC_MISO 2 1
OUT
5% PLACE_NEAR=U5210.2:5MM
1/16W
MF-LF
402 R5251
43
79 44 SPI_SMC_MOSI 2 1
IN
PLACE_NEAR=U5000.N9:8.5MM 5%
1/16W
MF-LF
R5252 402
A 79 44 IN SPI_SMC_CLK 2
15
1 SYNC_MASTER=J16_TONY SYNC_DATE=03/13/2013 A
PLACE_NEAR=U5000.L10:15MM 5% PAGE TITLE
1/16W
MF-LF
402 R5253 SPI and Debug Connector
15 DRAWING NUMBER SIZE
SPI_SMC_CS_L 2 1
79 44 IN
PLACE_NEAR=U5000.K10:12.7MM 5% Apple Inc. 051-0164 D
1/16W REVISION
MF-LF R
402 12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
52 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 46 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Line Legend
70 47 =PP3V3_S0_SMBUS 70 =PP3V3_S0_SMBUS_SMC_0 Master
70 47 =PP3V3_S0_SMBUS
Slave
R53601 1
R5361 R53001 1
R5301 R5364 1 1
R5365
Mux
2.2K 2.2K 2.2K 2.2K
5% 5% 5% 5% 8.2K 8.2K
1/16W 1/16W 1/16W 1/16W 5% 5%
U1100 MF-LF MF-LF J2300 U5000 MF-LF MF-LF 1/16W 1/16W
402 2 2 402 402 2 2 402 U1100 MF-LF MF-LF
PCH (SMBus) Memory Channel A SMC (SMBus 0) 402
2 2 402
DIMM 0:
0xA0 Write
13 SMBUS_PCH_CLK =I2C_SODIMMA_SCL 23 0xA1 Read SMB_0_S0_CLK
81 MAKE_BASE=TRUE MAKE_BASE=TRUE 13 SML_PCH_0_CLK

D 13
81
SMBUS_PCH_DATA
MAKE_BASE=TRUE
=I2C_SODIMMA_SDA 23 SMB_0_S0_DATA
MAKE_BASE=TRUE
81

13
MAKE_BASE=TRUE
SML_PCH_0_DATA
D
81 MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA 44 81

SMBUS_SMC_0_S0_SCL 44 81
Unused PCH SM Link
J2500 U5600
Memory Channel B Temp Sensors "T1"
DIMM 2: U5600
0xA4 Write EMC1414 (Prod):
=I2C_SODIMMB_SCL 24 0xA5 Read =SMB_SNS1_SCL 50 0x98 Write
0x99 Read
=I2C_SODIMMB_SDA 24 =SMB_SNS1_SDA 50

U2200 U1100
VRef DAC PCH (SML 1)
0x98 Write 0x88 Write
0x99 Read 0x89 Read
=I2C_VREFDACS_SCL 22 SML_PCH_1_CLK 13

=I2C_VREFDACS_SDA 22 SML_PCH_1_DATA 13

U2201 U5690
Vref Control LCD Temp IRemote (Dev)
0x30 Write U5690
0x31 Read TMP006 (Prod):
=I2C_PCA9557D_SCL 22 =SMB_SNS3_SCL 50 0x8A Write
0x8B Read
70 40 31 =PP3V3_S0_DP These are needed in addition to TCON PU
=I2C_PCA9557D_SDA 22 =SMB_SNS3_SDA 50

C R5390 1 1
R5391
C
2.2K 2.2K
5% 5%
1/16W 1/16W
U8100 J4400 MF-LF MF-LF U8100
402 2
Backlight Control Display TCon 2 402 BLC Control from TCon
0x58 Write
0x59 Read 70 =PP3V3_S0_SMBUS_SMC_1
=I2C_BKLT_SCL 66 40 SMB_DP_TCON_SCL =SMB_DP_BLC_SCL 66 0x58 Write
81 MAKE_BASE=TRUE 0x59 Read
=I2C_BKLT_SDA 66 R53101 1
R5311 40
81
SMB_DP_TCON_SDA
MAKE_BASE=TRUE
=SMB_DP_BLC_SDA 66

4.7K 4.7K
5% 5%
1/16W 1/16W
U5000 MF-LF MF-LF U5650
402 2
SMC (SMBus 1) 2 402 Temp Sensors "T2"
J6500 For J16:
U5650
CHS SMB_1_S0_CLK =SMB_SNS2_SCL 50
TMP423B (Dev):
0x9A Write
0x76 Write MAKE_BASE=TRUE 0x9B Read
0x77 Read
=I2C_CHS_SCL 56 SMB_1_S0_DATA =SMB_SNS2_SDA 50
MAKE_BASE=TRUE For J17:
U5650
=I2C_CHS_SDA 56 SMBUS_SMC_1_S0_SDA 44 81 EMC1428-7:
0x92 Write
SMBUS_SMC_1_S0_SCL 0x93 Read
44 81

J4400

U6551
Display TCon
TMP421:
Mikey SMB_DP_TCON_SLA_SCL 40
0x9E Write
0x9F Read
0x72 Write
0x73 Read
=I2C_MIKEY_SCL 56 SMB_DP_TCON_SLA_SDA 40 Panel/Vendor ID:
0x1A Write
0x1B Read
=I2C_MIKEY_SDA 56

B B
J1800,J1850
XDP 70 =PP3V3_S4_SMBUS_SMC_2
0x94 Write
0x95 Read
=SMBUS_XDP_SCL 18 R53201 1
R5321
4.7K 4.7K
=SMBUS_XDP_SDA 18 5% 5%
1/16W 1/16W
U5000 MF-LF MF-LF J4200
402
SMC (SMBus 2) 2 2 402 ALS
0x52 Write
0x53 Read
SMB_2_S4_CLK 81 44 SMBUS_SMC_2_S4_SCL =SMB_ALS_SCL 38
MAKE_BASE=TRUE
SMB_2_S4_DATA 81 44 SMBUS_SMC_2_S4_SDA =SMB_ALS_SDA 38
MAKE_BASE=TRUE

70 =PP3V3_S0_SMBUS_SMC_3

R53301 1
R5331
4.7K 4.7K
5% 5%
1/16W 1/16W
U5000 MF-LF MF-LF

A SMC (SMBus 3) 402 2 2 402

SYNC_MASTER=J16_TONY SYNC_DATE=03/13/2013 A
PAGE TITLE
SMB_3_CLK
MAKE_BASE=TRUE
SMBUS_SMC_3_SCL 44 81
SMBus Connections
SMB_3_DATA SMBUS_SMC_3_SDA 44 81 DRAWING NUMBER SIZE
MAKE_BASE=TRUE
Apple Inc. 051-0164 D
REVISION
SMC multi-master experiment R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
53 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 47 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V3_S4_AP (IW0R:ADC19) Airport supply current sense
12V G3H (VD2R:ADC0/ID2R:ADC1) AC/DC lowside sense (System total) CPU Core (VC0C:ADC10/IC0C:ADC11)
CRITICAL Voltage sense and IMON amp (VC0C, IC0C)
CRITICAL R5430 PP3V3_S4_SNS
R5400 0.010 OUT 70
R5461
0.002
1% 4.53K
1%
PP12V_G3H_SNS OUT 70 NOTE:VSNS on S5 to avoid burning G3H Power 1/2W
MF
70 61 =PPCPUVCC_S0_CPU 1 2 VSNS_CPUVCC OUT 45 81
1W 1206-1 1% U5000.B6:10mm
TFT R5401 70 =PP3V3_S4_SNS_R 1 2 1/16W
1
=PP12V_G3H_SNS_R 1
0612
2 =PP12V_S5_SNS 1
18.2K
2 VSNS_P12VG3H 3 4
MF-LF
402
C5461
70 70 OUT 45 81
0.22UF
3 4 1% 20%
1/16W 2 6.3V
X5R
MF-LF
1 U5000.E2:10mm 0201
402
R5402 50 49 34 =PP3V3_S0_SENSE

D 70 =PP3V3_S5_SENSE
U5000.E2:10mm
1%
6.04K
1 C5402
0.22UF
20%
70

1 C5430
GND_SMC_AVSS 44 45 48 49
81
D
1/16W
1 C5400 MF-LF 2
6.3V 0.22UF
X5R 20% =PP5V_S0_ISENSE
AP_ISNS:Y

3
0.22UF 2 402 0201 6.3V
2 X5R
70
20%

3
6.3V V+ 0201 1
2 X5R GND_SMC_AVSS 44 45 48 49
81 AP_ISNS:Y
C5460
V+ 0.01UF
0201
U5000.E1:10mm
U5430 R5435 C7050.1:10mm 20%
U5400 R5405 SNS_P3V3S4_AP_N 5 IN-
INA210
SC70 OUT 6 81 ISNS_P3V3S4_AP_R 1
4.53K
2 ISNS_P3V3S4_AP
SIGNAL_MODEL= 2 16V
X7R-CERM
INA214 4.53K
81 OUT 45 81
VMax = 0.9V R5462 0402
U5000.A6:10mm
81 SNS_P12VG3H_N 5 IN- SC70 OUT 6 81 ISNS_P12VG3H_R 1 2 ISNS_P12VG3H OUT 45 81 1%
REG_CPUVCC_IMON 1
10K
2 REG_CPUVCC_IMON_R 1 5
4 IN+
CRITICAL 1
1/20W U5000.H2:10mm 83 61 IN 81
R5465
CRITICAL 1% 81 SNS_P3V3S4_AP_P REF 1 R5436 MF
1
1/16W AP_ISNS:Y 201
1
1%
4 5.1K
81 SNS_P12VG3H_P 4 IN+ REF 1 R5406 MF-LF
402
U5000.E1:10mm 20K C5435 1/16W
MF-LF
CRITICAL 1 2 ISNS_CPUVCC OUT 45 81
5% 0.22UF
20K 1 C5405 353S2073 GND 1/20W 402 5% U5000.A6:10mm
5% MF
20%
OMIT_TABLE 81 ISNS_CPUVCC_FB_R 3 1/16W
GND 0.22UF

2
6.3V 1
353S2208 1/20W
20%
Gain: 200 V/V 2 201 2 X5R 2 U5460 MF-LF
402
C5465
MF AP_ISNS:Y 0.22UF
OPA348
2

Gain: 100 V/V 2 6.3V Range: 0-3.3A 0201 1

2 201 X5R R5463 SC70-5 20%
0201 GND_SMC_AVSS 6.3V
Range: 0-16.5A 44 45 48 10K 2 X5R
49 81 1%
GND_SMC_AVSS 0201
44 45 48 49
81 TABLE_5_HEAD
1/16W
MF-LF
R5464
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION 2 402 2.0K GND_SMC_AVSS 44 45 48 49
1 2 81 ISNS_CPUVCC_FB 81
TABLE_5_ITEM

132S0304 1 CAP,0.22uF,201 C5435 AP_ISNS:Y 1%

1/16W
TABLE_5_ITEM

MF-LF
117S0002 1 RES,0 ohm,201 C5435 AP_ISNS:N 402

PP1V05_S0_PCH (VN1R:ADC17)
I/V-sense for PP1V05_S0_PCH
Place R5476 over PP1V05_S0 power plane shape.

C R5476
C
4.53K
70 =PP1V05_S0_SNS 1 2 VSNS_P1V05S0_PCH OUT 45 81

C1760.1:15mm 1%
1/20W U5000.G1:10mm
MF
201
1 C5476
0.22UF
20%
6.3V
2 X5R
0201

GND_SMC_AVSS 44 45 48 49 81

HDD S0 (VH05:ADC14/IH05:ADC15)
I/V-sense for HDD (Development, but need R5420)
B B
CRITICAL
R5420
0.010 PPHDD_S0_SNS 70
1% OUT
1/4W
HDD_IVSNS:Y
MF R5421
0805-2 4.02K VSNS_HDDS0
70 =PPHDD_S0_SNS_R 1 2 1 2 OUT 45 81
3 4 1%
1/16W OMIT_TABLE
MF-LF HDD_IVSNS:Y U5000.B1:10mm
1
402
R5422 1 C5422
6.04K 0.22UF
1%
1/16W 20%
6.3V
MF-LF 2 X5R
402 0201
2
HDD_IVSNS:Y
GND_SMC_AVSS 44 45 48 49

U5420 HDD_IVSNS:Y
81

INA216A4YFFX R5425
WCSP-4
A1 B2 4.53K
81 SNS_HDD_P IN+ CRITICAL OUT 81 ISNS_HDDS0_R 1 2 ISNS_HDDS0 45 81
OUT
A2 HDD_IVSNS:Y 1%
OMIT_TABLE
81 SNS_HDD_N IN- DZ5420 K 1/16W
MF-LF U5000.B2:10mm
402
CDZ3.0B 1 C5425
GND SM 0.22UF
353S3597 B1 A 20%
6.3V
Gain: 200 V/V 2 X5R
0201
Range: 0-1.65A
GND_SMC_AVSS 44 45 48 49
81

A SYNC_MASTER=J16_TONY SYNC_DATE=03/13/2013 A
PAGE TITLE

I and V Sense
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_ITEM

132S0304 2 CAP,0.22UF,201 C5422,C5425 HDD_IVSNS:Y DRAWING NUMBER SIZE

TABLE_5_ITEM

Apple Inc. 051-0164 D

117S0002 2 RES,0 OHM,201 C5422,C5425 HDD_IVSNS:N REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
54 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 48 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PPVDDQ_S0 (VC0M:ADC4/IC0M:ADC5)
lowside sense for CPU mem rail (2.5A max draw, 3.3A max sense capability)

CRITICAL
R5530
0.002 PPVDDQ_S0_SNS 70
1% OUT
1W
TFT R5531
0612 4.53K
70 =PPVDDQ_S0_SNS_R 1 2 1 2 VSNS_PVDDQS0 OUT 45 81
3 4 1%
1/20W
MF U5000.B3:12.7mm
D 49 48 34 =PP3V3_S0_SENSE
201
1 C5531
0.22UF
D
70 50
20%
1 6.3V
C5530 2 X5R
0.22UF 0201
20%

3
2 6.3V
X5R
GND_SMC_AVSS 44 45 48 49 81
V+ 0201
CRITICAL
U5530 R5535
INA211 4.53K
81 SNS_PVDDQS0_N 5 IN- SC70 OUT 6 81 ISNS_PVDDQS0_R 1 2 ISNS_PVDDQS0 OUT 45 81

1%
1/20W
81 SNS_PVDDQS0_P 4 IN+ REF 1 MF U5000.A3:10mm
201
1 C5535
353S2216 GND 0.22UF
20%

2
6.3V
Gain: 500 V/V 2 X5R
0201
Range: 0-2.5A
GND_SMC_AVSS 44 45 48 49 81

VDDQ S3 (VM0R:ADC6/IM0R:ADC7)
VDDQ lowside sense for SO-DIMM modules

C CRITICAL
R5540 C
0.0005 PPVDDQ_S3_SNS_DDR 70
1% OUT
1W
MF R5541
0612 4.53K
70 =PPVDDQ_S3_SNS_DDR_R 1 2 1 2 VSNS_VDDQS3_DDR OUT 45 81
3 4 1%
1/20W
MF U5000.B4:10mm
201
1 C5541
49 48 34 =PP3V3_S0_SENSE
70 50 0.22UF
20%
1 C5540 6.3V
2 X5R
0.22UF 0201
20%

3
6.3V GND_SMC_AVSS
2 X5R 44 45 48 49
81
V+ 0201
CRITICAL
U5540 R5545
INA211 4.53K
81 SNS_VDDQS3_DDR_N 5 IN- SC70 OUT 6 81 ISNS_VDDQS3_DDR_R 1 2 ISNS_VDDQS3_DDR OUT 45 81

1%
1/20W
SNS_VDDQS3_DDR_P 4 IN+ REF 1 1 MF U5000.A4:10mm
81 R5546 201
20K 1 C5545
5%
353S2216 GND 1/20W
0.22UF
20%
MF

2
6.3V
Gain: 500 V/V 2 201 2 X5R
0201
Range: 0-13.2A
GND_SMC_AVSS 44 45 48 49
81

SSD S0 (IH1R:ADC20/VR3R:ADC21) I-sense for SSD / V-sense for PP3V3_S5)

B SSD:Y
B
CRITICAL
R5520
0.002 PPSSD_S0_SNS 70
SSD:Y
1% OUT
1W R5526
TFT 4.53K
0612 70 =PP3V3_S5_SNS 1 2 VSNS_P3V3S5 45 81
=PPSSD_S0_SNS_R 2 1 OUT
70
1%
4 3 U5000.A7:10mm 1/20W OMIT_TABLE
MF U5000.A7:10mm
201
1 C5526
0.22UF
20%
6.3V
2 X5R
0201
SSD:Y
GND_SMC_AVSS 44 45 48 49 81

U5520 SSD:Y
INA216A4YFFX R5525
WCSP-4
A1 B2 4.53K
81 SNS_SSD_P IN+ CRITICAL OUT 81 ISNS_SSDS0_R 1 2 ISNS_SSDS0 45 81
OUT
1%
81 SNS_SSD_N A2 IN- 1/20W OMIT_TABLE
MF U5000.B7:12.7mm
201
1 C5525
GND 0.22UF
353S3597 B1 20%
6.3V
Gain: 200 V/V 2 X5R
Range: 0-8.25A 0201

GND_SMC_AVSS 44 45 48 49
81

A TABLE_5_HEAD
SYNC_MASTER=J16_TONY SYNC_DATE=03/13/2013 A
PAGE TITLE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

132S0304 2 CAP,0.22UF,201 C5525,C5526 SSD:Y

TABLE_5_ITEM

I and V Sense(Continued)
DRAWING NUMBER SIZE
051-0164 D
TABLE_5_ITEM

117S0002 2 RES,0 OHM,201 C5525,C5526 SSD:N

Apple Inc. REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
55 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 49 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Temperature Sensor T1

MLB Proximity AC/DC Diode on supply

L5614
FERR-220-OHM
SNS_T1_1_P 50 81
1 2 SNS_T1_3_P 50 81

D 3
0402
L5614.2:2MM
D
Q5610.3:2MM 70 50 49 48 34 =PP3V3_S0_SENSE
CRITICAL 1 81 60 IN SNS_ACDC_P 1
1 C5610 C5614
Q5610 2.2PF 81 60 IN SNS_ACDC_N 0.0022UF
BC846BLP +/-0.1PF L5615 10% 1 C5600 1
R5600
DFN1006H4-3 2 25V
NP0 FERR-220-OHM 2 50V
CERM 1UF
2 201 402 10%
10K
5%
SNS_T1_1_N 50 81
1 2 SNS_T1_3_N 50 81 2 10V
X5R 1/16W
402-1 MF-LF
PLACEMENT_NOTE=Place Q6010 near CPU 0402
2 402

CRITICAL 1
VDD

CPU Proximity U5600

EMC1414-1-AIZL
SNS_T1_2_P MSOP
50 81 2 DP1 7
81 50 SNS_T1_1_P THERM*/ADDR NC
MLB Prox 1 (Tm1p)
3 Q5612.3:2MM 81 50 SNS_T1_1_N 3 DN1 ALERT* 8 SNS1_ALERT_L
CRITICAL 1
1 C5612 4 DP2/DN3 9 =SMB_SNS1_SDA
Q5612 2.2PF CPU Prox 81 50 SNS_T1_2_P SMDATA BI 47
BC846BLP +/-0.1PF MAKE_BASE=TRUE
DFN1006H4-3 25V
2 NP0 81 50 SNS_T1_2_N 5 DN2/DP3 SMCLK 10 =SMB_SNS1_SCL 47
IN
2 201 MAKE_BASE=TRUE GND
SNS_T1_2_N 50 81 AC/DC 81 50 SNS_T1_3_P NOSTUFF NOSTUFF 6
PLACEMENT_NOTE=Place Q5612 between CPU socket and CPU Power supply components U5600.4:2MM U5600.5:2MM I2C Address (EMC1414-1):
81 50 SNS_T1_3_N 1 1
C5604 C5605 0x98 (Write)
47PF 47PF 0x99 (Read)
5% 5%
50V 2 50V
CERM 2 CERM
402 402

Note:

C TABLE_ALT_HEAD
Filter Caps: Stuff if needed for PSU sensor SI
Internal sensor of the EMC 1414
will be used as the ambient sensor.
C
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: Place U5600 at the coolest location
PART NUMBER
TABLE_ALT_ITEM
on the MLB.
372S0186 372S0185 ALL Alternate Temp Diode

Temperature Sensor T2 Temperature Sensor T3: LCD Remote Sensor(Dev Only)

70 50 49 48 34 =PP3V3_S0_SENSE

TEMPSNSDEV
SO-DIMM Proximity 1 C5690
0.01UF
SNS_T2_1_P 50 81 10%
16V
2 X7R-CERM TEMPSNSDEV
NO_XNET_CONNECTION=TRUE 0402 1
3 Q5660.3:2MM R5690
B CRITICAL 1 C5660 10K B

A3
1 Q5660 5%
2.2PF 1/16W
BC846BLP +/-0.1PF
25V
MF-LF
DFN1006H4-3 2 NP0 V+ 2 402
2 201 SO-DIMM 81 50 SNS_T2_1_P U5690
SNS_T2_1_N 50 81 TMP0006AIYZER
OMIT WCSP
NO_XNET_CONNECTION=TRUE 47 =SMB_SNS3_SDA C3 ADR0 C1
PLACEMENT_NOTE=Place Q5660 near SO-DIMM connectors U5650.4:2MM BI SDA CRITICAL
XW5651 B3 ADR1 B1
SM 47 IN =SMB_SNS3_SCL SCL
50 49 48 34 =PP3V3_S0_SENSE DRDY* C2 TMP006_DRDY
81 50 SNS_T2_1_N 1 2 70

BLC Proximity MLB Prox 2 (Tm2p) TEMPSNSDEV

I2C Address (TMP006):
81 50 SNS_T2_2_P 1 C5650 DGND AGND
SNS_T2_3_P 0x8A (Write)

A2
50 81
1UF
OMIT 10% 0x8B (Read)
10V
3 NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE 2 X5R
Q5664.3:2MM U5650.4:2MM 402-1
CRITICAL
1
1 C5664 XW5652 NOTE - Follow TI layout guide(SBOU108.pdf) for this part!!!
Q5664 2.2PF SM
BC846BLP +/-0.1PF
25V 81 50 SNS_T2_2_N 1 2
8
DFN1006H4-3 2 NP0
2 201 V+ This PD part is a rubber bumper to protect TMP006
SNS_T2_3_N BLC Prox SNS_T2_3_P Added to board BOM (DEV only) to clean up PD BOM
50 81 81 50
U5650 TABLE_5_HEAD

OMIT 1 DXP1
TMP423 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
PLACEMENT_NOTE=Place Q5554 near BLC controller NO_XNET_CONNECTION=TRUE SOT23-8 SCL 7 =SMB_SNS2_SCL IN 47
U5650.4:2MM 2 DXP2 6
TABLE_5_ITEM

CRITICAL SDA =SMB_SNS2_SDA BI 47 875-6433 1 BUMPER,U5690,D7 BUMPER_U5690 TEMPSNSDEV

XW5653 3 DXP3
SM
81 50 SNS_T2_3_N 1 2 SNS_T2_DXN 4 DXN I2C Address (TMP432B):
GND 0x9A (Write)
5 0x9B (Read)

A MLB Proximity SYNC_MASTER=J16_FIYIN SYNC_DATE=01/11/2013 A

PAGE TITLE

TEMPSNSDEV
SNS_T2_2_P 50 81
Temperature Sensors
3 NO_XNET_CONNECTION=TRUE DRAWING NUMBER SIZE
Q5665.3:2MM
CRITICAL 1 C5662 Apple Inc. 051-0164 D
1 Q5665 REVISION
0.0022UF R
BC846BLP 10%
50V 12.4.0
DFN1006H4-3 2 CERM
2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
SNS_T2_2_N 50 81 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PLACEMENT_NOTE=PLACE Q565 SOUTH OF SO-DIMM CONNECTORS NEAR DDR VR I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
56 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 50 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C SMC Fan 0 (System) C

Note:
The circuit for the PWM input to L6000
the fan acts as a non-inverting 220-OHM-1.4A
level-shifter to protect the SMC. 70 =PP12V_S0_FAN 1 2
It is assumed there is a pull-up to 0603
VOLTAGE=12V
1 1 MIN_LINE_WIDTH=0.5MM
5V/12V inside the fan, otherwise C6000 C6001 CRITICAL MIN_NECK_WIDTH=0.25MM
4.7UF 0.01UF
when the SMC PWM goes low and Q6010 20% 20%
16V 16V
turns on, there would be 5V/12V 2 X7R-CERM 2 X7R-CERM
1206 0402
present on the SMC pin! Then by
definition, the drain of Q6010 is
at common and the SMC sinks current
when Q6010 is on.
70 51 45 44 =PP3V3_G3H_SMC SEE RADAR:12960082 J16/J17 CONNECT GATE OF FAN PWM FET TO PP3V42_G3H
This resembles an open-drain if 518S0730
there is a pull-up, going to a Hi-Z 70 51 =PP3V3_S0_FAN
CRITICAL
FET input. 1
R6010 Q6010 J6000
Otherwise, this is simply a pass-FET. 10K SSM3K15AMFVAPE 53780-8604

1
5% M-RT-SM
See RADAR: 10565825- D7: Need scematic and PCB file of fan(All Vendors). 1/16W

G
VESM
MF-LF L6010 5
2 402 CRITICAL FERR-220-OHM MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
SMC_FAN_0_CTL

D
81 44 IN FAN_0_PWM_FET 1 2 FAN_0_PWM_FILT 1

3
2
1
0402 FAN_0_TACH_FILT 2 Tach
C6010 CRITICAL
B 5%
100PF
50V PP12V_S0_FAN_0_FILT
3
4
GND
12V DC
B
2 CERM
0402
6

70 51 45 44 =PP3V3_G3H_SMC 70 51 =PP3V3_S0_FAN
1
K R6026
47K
D6020 5%
BAS316DG 1/16W
MF-LF
SOD323-SM
A
2 402 L6021
R6020 FERR-220-OHM
SMC_FAN_0_TACH 1
47K 2 FAN_0_TACH_FET 1 2
81 44 OUT
5% 0402
1 C6020 1/16W
MF-LF
1 C6021 CRITICAL
1000PF 402 100PF
PLACE_NEAR=U5000.L13:5MM
10% 5%
2 16V
X7R-CERM 2 50V
CERM
0201 0402

Add C6020 1000pF Cap, Change R6020 to 47K -- Radar 11661918 D8 Proto1 Fan Tach instability.

A SMC Fan 1 (Unused) SYNC_MASTER=J16_JERRY SYNC_DATE=01/07/2013 A

PAGE TITLE

System Fan
DRAWING NUMBER SIZE
44 IN SMC_FAN_1_CTL NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE NO_TEST=TRUE Apple Inc. 051-0164 D
REVISION
R

44 SMC_FAN_1_TACH NC_SMC_FAN_1_TACH
12.4.0
OUT
MAKE_BASE=TRUE NO_TEST=TRUE NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
60 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 51 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO CODEC PLACE C6100 AS CLOSE TO PIN 9 AS POSSIBLE
APPLE P/N 353S2592 PP5V_AUDIO_HPAMP 52 53
IN
VD MUST BE LESS THAN OR EQUAL TO VL_HD
70 =PP1V5_S0_AUD_DIG
=PP3V3_S0_AUDIO IN 38 52 54 55 58 70

C6101 1 1 C6100
4.7UF 0.47UF
20%
4V
10%
10V
PP4V5_AUDIO_ANALOG IN 52 56 58
X5R-1 2 2 X5R
CRITICAL
402 0402
C6105 1 1 C6104C6106 C6107
C6108 1
1UF 0.47UF
1 1
10UF 10% 10% 0.47UF 10UF
20% C6102 1 1
C6103 10V 2
10V
2 X5R 10% 20%

D 59 58 56 52 GND_AUDIO_CODEC
16V 2
POLY-TANT
CASE-B2-SM
0.47UF
10%
10UF
20%
X5R
402-1 0402
10V 2
X5R
0402
2 10V
X5R-CERM
0402-1 D

25
10V 2 2 16V

9
PP4V5_AUDIO_ANALOG X5R POLY-TANT GND_AUDIO_CODEC
58 56 52 IN
C6109 1 1 C6110 VD VA_REF VA_HP VA
0402 CASE-B2-SM
GND_AUDIO_CODEC
52 56 58 59

1 2.2UF 2.2UF 52 56 58 59
1
R6100 20%
6.3V
20%
6.3V
VBIAS_DAC 29 VBIAS_DAC R6105
2.67K CERM 2 2 CERM 0
1% 402-LF 402-LF HPOUT_L 38 MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM TP_AUD_HP_L NC 5%
1/16W CS4206_FP 44 VHP_FILT+ CRITICAL 1/16W
MF-LF HPOUT_R 40 MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM TP_AUD_HP_R NC MF-LF
2 402
CS4206_FN 41 VHP_FILT- U6101 2 402
CS4206B HPREF 39 MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM CS4206_HPREF
QFN
DMICS 1 & 2 38 AUD_DMIC_SDA1
OUT 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 AUD_LO1_L_P OUT 53 54 59

NC TP_DMIC_SDA2 12 GPIO1/DMIC_SDA2
/SPDIF_OUT2
LINEOUT_L1- 34 AUD_LO1_L_N OUT 53 54 59 HP AMP/LINE OUT RESERVE SPACE FOR POSSIBLE LATCH CIRCUIT
HP AMP CNTRL 53 OUT AUD_GPIO_2 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_R_P OUT 53 55 59 TWEETERS
15 GPIO3 LINEOUT_R1- 37 AUD_LO1_R_N OUT 53 55 59
Q6170_P_S
MAC SPKR AMP CNTRL
D6100
SOD-523 13 SENSE_A LINEOUT_L2+ 31 AUD_LO2_L_P OUT 54 59
DEVEL_AUDIO DEVEL_AUDIO
54 52 IN AUD_CODEC_MICBIAS A K CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_L_N OUT 54 59 WOOFERS CRITICAL 1
CS4206_FLYC LINEOUT_R2+ 32 AUD_LO2_R_P OUT 55 59 Q6170 R6170
BAT54XV2T1 45 FLYP
AUD_LO2_R_N DMC2400UV 0
R61061 LINEOUT_R2- 33 5%

4
100K
C6111 1 1 C6112 43 FLYC OUT 55 59
SOT563 1/16W
MF-LF
WIN SPKR AMP CNTRL AUD_GPIO_3 1% 2.2UF 2.2UF 42 FLYN
54 OUT
1/16W 20% 20% 2 402
59 58 AUD_SENSE_A MF-LF 6.3V 2 2 6.3V MICBIAS 16 AUD_CODEC_MICBIAS 52 54
IN CERM CERM OUT
402 2 402-LF 402-LF

S
Q6170_P_G
3 VL_HD

P-CHN

5
CS4206_FLYN

G
MIN_LINE_WIDTH=0.20MM
VCOM 28 CS4206_VCOM MIN_NECK_WIDTH=0.15MM

D
1 VL_IF
PLACE TP FOR ALL HDA SIGNALS NEAR CODEC

3
79 11 HDA_BIT_CLK 6 BITCLK
LINEIN_L+ 21 NO_TEST=TRUE AUD_LI_P_L NC NC
IN
LINEIN_C- 22 NO_TEST=TRUE AUD_LI_COM NC
C 79 11 IN HDA_SYNC LINEIN_R+ 23 NO_TEST=TRUE AUD_LI_P_R NC 6
NC DEVEL_AUDIO
CRITICAL
C
R6101 10 SYNC
Q6170
HDA_SDIN0 22 AUD_SDI_R AUD_MIC_INL_P
79 11 OUT 1 2 79 8 SDI MICIN_L+ 18 IN 56 59
D DMC2400UV
SOT563
AUD_MIC_INL_N

N-CHN
5% 5 SDO MICIN_L- 17 IN 56 59
1/16W
MF-LF
402 11 RESET*
MICIN_R+ 19 NO_TEST=TRUE AUD_MIC_INP_R NC G 2 Q6170_N_G
79 11 IN HDA_SDOUT MICIN_R- 20 NO_TEST=TRUE AUD_MIC_INN_R NC S
79 11 IN HDA_RST_L
DEVEL_AUDIO
85 40 IN DP_INT_SPDIF_AUDIO 47 SPDIF_IN MIN_LINE_WIDTH=0.20MM
VREF+_ADC 27 MIN_NECK_WIDTH=0.15MM CS4206_VREF_ADC NC 1
R6171
79 AUD_SPDIF_CHIP 48 SPDIF_OUT 1
R6102 R6104 0
5%
22 CS4206_DMIC_SCL 0 1/16W
79 56 OUT AUD_SPDIF_OUT 1 2
1 DMIC_SCL 4 1 2 AUD_DMIC_CLK OUT 38 MF-LF
5% R6103 5% 2 402
1/16W 100K 1/16W
MF-LF 1% MF-LF Q6170_N_S
402 1/16W DGND THRM_PAD AGND 402
MF-LF
402 2

26
DMICS SHOULD HAVE OWN GND ON CONNECTOR SHARED WITH CAMERA
XW6100 CRITICAL CRITICAL
38 OUT GND_AUDIO_DMIC
MIN_LINE_WIDTH=0.20MM
C6113 1 1
C6114 1 C6115 R61071 R61081 R61091 R61101 R61111
0.47UF
1

MIN_NECK_WIDTH=0.15MM SM 1UF 10UF 100K 100K 100K 100K 100K

VOLTAGE=0V 10% 20% 10%
10V 1% 1% 1% 1% 1% Q6171_P_S
20V 2 2 16V 2 X5R 1/16W 1/16W 1/16W 1/16W 1/16W
TANT POLY-TANT MF-LF MF-LF MF-LF MF-LF MF-LF
CASE-P3-HF CASE-B2-SM 0402
402 2 402 2 402 2 402 2 402 2 DEVEL_AUDIO DEVEL_AUDIO
CRITICAL 1
Q6171 R6172
DMC2400UV 0
5%

4
SOT563 1/16W
MF-LF
59 58 56 52 GND_AUDIO_CODEC 2 402

S
Q6171_P_G

P-CHN
B

5
B

G
D
APPLE P/N 353S2456
4.5V POWER SUPPLY FOR CODEC

3
NC
NC DEVEL_AUDIO
6 CRITICAL
Q6171
MIN_LINE_WIDTH=0.40MM
DIFF FSINPUT= 2.45VRMS D
DMC2400UV
SOT563
SE FSINPUT= 1.22VRMS

N-CHN
MIN_NECK_WIDTH=0.20MM
L6111 VOLTAGE=4.5V
DAC1 FSOUTPUT= 1.34VRMS
FERR-220-OHM G 2 Q6171_N_G
1 2 PP5V_AUDIO_HPAMP 52 53
DAC2/3 FSOUTPUTDIFF= 2.67VRMS S
OUT
0402
DAC2/3 FSOUTPUTSE= 1.34VRMS DEVEL_AUDIO
1
1 R6173
MIN_LINE_WIDTH=0.40MM 0
MIN_NECK_WIDTH=0.20MM 5%
VOLTAGE=4.5V 1/16W
MF-LF
L6110 2 402
FERR-220-OHM VR6101
TPS71745 Q6171_N_S
70 59 =PP5V_S0_AUDIO 1 2 4V5_REG_IN 6 IN SON 1 PP4V5_AUDIO_ANALOG 52 56 58
IN OUT OUT
0402 MIN_LINE_WIDTH=0.40MM
CRITICAL MIN_NECK_WIDTH=0.15MM
VOLTAGE=4.5V
R6120 4V5_REG_EN 4 EN NR/FB 3 4V5_NR
=PP3V3_S0_AUDIO
0
70 58 55 54 52 38 IN
1 2
GND NC 5 MIN_LINE_WIDTH=0.4MM
5%
1/16W
C6122 1
2
MIN_NECK_WIDTH=0.2MM
MF-LF 1UF C6123 1 1 C6124
402 10%
A 10V
X5R 2
402-1
XW6110 0.1UF
10%
16V
1UF
10%
2 10V
SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013 A
X7R-CERM 2
1

X5R PAGE TITLE

SM 0402 402-1

GND_AUDIO_CODEC 52 56 58 59
AUDIO: CODEC/REGULATORS
MIN_LINE_WIDTH=0.5MM DRAWING NUMBER SIZE
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
Apple Inc. 051-0164 D
XW6111 REVISION
GND_AUDIO_HPAMP 53 R
MIN_LINE_WIDTH=0.5MM 12.4.0
1

SM MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
PLACE XW6110 BENEATH U6101, BETWEEN PINS 2 & 5 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
61 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 52 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NO_XNET_CONNECTION=TRUE
C6262
100PF
1 2

5%
50V
CERM
0402
NO_XNET_CONNECTION=TRUE
R6262
19.6K2
1
R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL
1%
1/20W
MF MAX97220_OUTR OUT 53 56 53 52 IN PP5V_AUDIO_HPAMP
201

D CRITICAL
C6261 R6261
D
33UF
AUD_LO1_R_N 1 2 59 AUD_LO1_R_C_N 1
26.1K2
MAX97220_INR_N C6250 1 1 C6251 C6252 1 1 C6253
59 55 52 IN OUT 53 59
0.1UF 10UF 1UF 1UF
1% 10% 20% 10% 10%
1/20W 16V 10V 10V 10V
20% X7R-CERM 2 2 X5R-CERM X5R 2 2 X5R
6.3V MF
201 0402 0402-1 402-1 402-1
TANT
CASE-A
53 52 GND_AUDIO_HPAMP GND_AUDIO_HPAMP 52 53
CRITICAL
C6263 R6263

13
33UF

9
26.1K2
59 55 52 IN AUD_LO1_R_P 1 2 59 AUD_LO1_R_C_P 1 MAX97220_INR_P OUT 53 59

PVDD
SVDD
SVDD2
1%
20% 1/20W R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL
6.3V MF
TANT 201
CASE-A
NO_XNET_CONNECTION=TRUE 59 53 IN MAX97220_INR_N 14 INL- OUTL 12 MAX97220_OUTR OUT 53 56
NO_XNET_CONNECTION=TRUE 15 INL+ CRITICAL MIN_LINE_WIDTH=0.4MM
R62641 59 53 MAX97220_INR_P MIN_NECK_WIDTH=0.2MM
19.6K
1 C6264 IN
U6250 BIAS 11 MAX97220_BIAS
MIN_LINE_WIDTH=0.4MM
1% 100PF MAX97220AETE MIN_NECK_WIDTH=0.2MM
1/20W 5%
50V 59 53 IN MAX97220_INL_P 7 INR+ TQFN OUTR 10 MAX97220_OUTL OUT 53 56
MF 2 CERM MIN_LINE_WIDTH=0.4MM MIN_LINE_WIDTH=0.4MM
201 2 0402 59 53 IN MAX97220_INL_N 8 INR- MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
2 MAX97220_C1P
C1P
AUD_HP_PORT_REF MAX97220_SHDN_L 16 SHDN* C1N 4

17 THM_PAD
56 53
1 C6255 1 C6256

PGND

SGND

PVSS
2.2UF 1UF
20% 10%
NO_XNET_CONNECTION=TRUE 2 25V 2 10V
R6274 1 NO_XNET_CONNECTION=TRUE X5R-CERM X5R R62531 1
R6254
1 C6274 0402-1 402-1 2.0K 2.0K

5
19.6K 100PF 5% 5% CRITICAL CRITICAL
1% 1/16W 1/16W
1/20W
MF
5%
50V
2 CERM
MAX97220_C1N
MIN_LINE_WIDTH=0.4MM
C6257 1 1 C6258 MF-LF
402 2
MF-LF Q6250 Q6251
201 2 MIN_NECK_WIDTH=0.2MM 0.1UF 0.1UF 2 402 DMN2015UFDE DMN2015UFDE
0402 10% 10%
16V 2 16V 1 UDFN 1UDFN
C CRITICAL
C6273
X7R-CERM 2
0402
X7R-CERM
0402
D D
C
33UF R6273 NC MAX97220_OUTL_ZOBEL MAX97220_OUTR_ZOBEL NC
AUD_LO1_L_C_P 126.1K2
MAX97220_PVSS
59 54 52 IN AUD_LO1_L_P 1 2 59 MAX97220_INL_P OUT 53 59
MIN_LINE_WIDTH=0.5MM
1% MIN_NECK_WIDTH=0.2MM G 3 3 G
20%
6.3V
1/20W
MF 1 C6254 R62511 1
R6252
TANT 201
2.2UF 33 33 S S
CASE-A 20% 5% 5%
25V 1/16W 1/16W
2 X5R-CERM MF-LF MF-LF
CRITICAL 0402-1 402 2 2 402 7 4 4 7
C6271 R6271
33UF
59 54 52 IN AUD_LO1_L_N 1 2 59 AUD_LO1_L_C_N 126.1K2 MAX97220_INL_N OUT 53 59

1%
20% 1/20W 53 52 GND_AUDIO_HPAMP
6.3V MF
TANT 201
CASE-A NO_XNET_CONNECTION=TRUE
MAX97220_OUTL OUT 53 56
R6272
19.6K2
1
1%
1/20W
MF PP5V_AUDIO_HPAMP
201 53 52 IN

C6272 R62571
100PF 100K
1 2 5%
1/20W
5% MF
50V 201 2
CERM MUTE_SWITCH
0402
NO_XNET_CONNECTION=TRUE
NC

B Q6252
SSM6N15AFE
D 6
Q6252
SSM6N15AFE
D 3
NOSTUFF
R6256 2 B
SOT563 SOT563
0
5%
1/16W
MF-LF
R6255 2 G S 1 5 G S 4 402 1

1
0 2 MUTE_CONTROL
53 MAX97220_SHDN_L
5%
1/16W
MF-LF
402 R62581 R62591
100K 100K
5% 5%
1/20W 1/20W
MF MF
201 2 201 2

53 52 GND_AUDIO_HPAMP

L6250
FERR-220-OHM
52 IN AUD_GPIO_2 1 2 MAX97220_SHDN_L 53
0402

R62501
100K
5%
1/20W
MF
A 201 2
SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013 A
PAGE TITLE

AUDIO: HEADPHONE AMP

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
62 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 53 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LEFT CH SPEAKER AMP
APPLE P/N 353S3163 SPEAKER AMP GAIN = +9 DB
SPEAKER AMP RIN = 40K NOMINAL
70 55 IN =PP12V_S0_AUDIO_SPKRAMP FC_HPF, TWEETERS = ~847 HZ (4700 PF)
CRITICAL
FC_HPF, WOOFERS = ~4 HZ (1.0 UF)
C6300 1 1 C6301 C6302 1 1 C6303 C6304 1 1 C6305 C6306 1
10UF 10UF 0.1UF 1UF 0.1UF 1UF 470UF
10% 10% 10% 10% 10% 10% 20%
25V 2 2 25V 25V 2 25V
2 X5R 25V 2 25V
2 X5R 16V 2
X5R X5R X5R X5R POLY
805 805 402 603-1 402 603-1 SM

D D

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

L6303 C6308 OUTPUT POLARITY FLIP TO
FERR-1000-OHM 4700PF
AUD_LO1_L_N 1 2 AUD_LAMP_RINC_P 1 2 AUD_LAMP_RIN_P TP_AUD_LAMP_THERM NC MAKE LAYOUT MORE LOGICAL

34
35
36
37
59 53 52 59 59
IN
0402
5%
50V
NPO-C0G-CERM PVDD
C6313
0805 20 INR+ 0.22UF NO_XNET_CONNECTION=TRUE
THERM 17 1 2
AUD_LAMP_BOOTRP CRITICAL
L6302 C6309 19 INR- CRITICAL MIN_LINE_WIDTH=0.20MM
FERR-1000-OHM 4700PF WOOFERS & TWEETERS ON UNDER MAC OS U6300 BOOTR+ 30
MIN_NECK_WIDTH=0.15MM 20%
AUD_LAMP_OUTPR
MIN_LINE_WIDTH=0.6MM
54 L6305
110-OHM-3A
AUD_SPKR_LTWT_OUT_P OUT 57 59
25V MIN_NECK_WIDTH=0.25MM NO_XNET_CONNECTION=TRUE
59 53 52 IN AUD_LO1_L_P 1 2 59 AUD_LAMP_RINC_N 1 2 59 AUD_LAMP_RIN_N 55 54 IN AUD_SPKRAMP_MAC_SHDN_L 22 SDNR* SSM3302 X5R
603 AUD_LAMP_OUTNR 4
DLY5ATN111SQ2
SYM_VER-2 3 CRITICAL
0402
5%
LFCSP
OUTR+
28 54
1 C6323
50V 29 1000PF
NPO-C0G-CERM 5%
0805 54 AUD_LAMP_MONO 16 MONO 54 AUD_LAMP_OUTPR 1 2 2 25V
CERM
L6300 C6310 26
C6314 0402
FERR-1000-OHM 1UF ONLY WOOFERS ON UNDER WINDOWS OUTR- 27 0.22UF AUD_LAMP_OUTNR 54 AUD_SPKR_LTWT_OUT_N 57 59
OUT
MIN_LINE_WIDTH=0.6MM
59 52 IN AUD_LO2_L_N 1 2 59 AUD_LAMP_LINC_P 1 2 59 AUD_LAMP_LIN_P 55 54 IN AUD_SPKRAMP_WIN_SHDN_L 9 SDNL* AUD_LAMP_BOOTRN 1 2 MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.20MM
0402
10% BOOTR- 25 MIN_NECK_WIDTH=0.15MM 20%
25V 11 INL+ 25V
X5R X5R
0402 12 INL- EDGE 10 AUD_LAMP_EDGE 54
603

L6301 C6311 C6315

FERR-1000-OHM 1UF BOOTL+ 1 0.22UF NO_XNET_CONNECTION=TRUE
59 52 IN AUD_LO2_L_P 1 2 59 AUD_LAMP_LINC_N 1 2 59 AUD_LAMP_LIN_N 54 AUD_LAMP_GAIN 21 GAIN AUD_LAMP_BOOTLP 1 2 CRITICAL
C 0402
10%
25V OUTL+
2
3
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM 20%
25V
AUD_LAMP_OUTPL
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
L6307
110-OHM-3A
AUD_SPKR_LWFR_OUT_N
NO_XNET_CONNECTION=TRUE
OUT 57 59 C
X5R X5R DLY5ATN111SQ2 CRITICAL
0402 AUD_LAMP_AVDD 8 VREG/AVDD 603 4 SYM_VER-2 3

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

54
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM 4
1 C6324
VOLTAGE=5V 1000PF
OUTL- 5 5%
1 2 2 25V
CERM
0402
70 58 55 52 38 =PP3V3_S0_AUDIO 23 REGEN BOOTL- 6 C6316
0.22UF AUD_LAMP_OUTNL AUD_SPKR_LWFR_OUT_P OUT 57 59
1 2 MIN_LINE_WIDTH=0.6MM
AUD_LAMP_BOOTLN MIN_NECK_WIDTH=0.25MM
18 MIN_LINE_WIDTH=0.20MM
NC MIN_NECK_WIDTH=0.15MM
NC 13 20%
NC 25V
C6317 1 14 X5R
603 OUTPUT POLARITY FLIP TO
2.2UF AGND PGND
TEST 15
20%
10V THRM_PAD MAKE LAYOUT MORE LOGICAL CRITICAL CRITICAL
X5R-CERM 2
402
C6320 C6322 1

7
24

31
32
33
38
39
40
NO_XNET_CONNECTION=TRUE 1 NO_XNET_CONNECTION=TRUE
1000PF 1000PF
5% 5%
25V 25V
CERM 2 CERM 2
PINS 14 & 15 ARE TEST PINS AND 0402 0402

SHOULD BE TIED TO GND

CRITICAL CRITICAL
1
NO_XNET_CONNECTION=TRUE C6319 1 C6321 NO_XNET_CONNECTION=TRUE
1000PF 1000PF
5% 5%
2 25V
CERM 2 25V
CERM
0402 0402

B B
L6308
FERR-1000-OHM
52 IN AUD_CODEC_MICBIAS1 2 AUD_SPKRAMP_MAC_SHDN_L OUT 54 55
0402 GAIN R6306 R6307
+9 DB NOSTUFF 0 OHM
NOSTUFF
EDGE RATE +12 DB NOSTUFF 47 KOHM
R63011 1 C6312 CONTROL R6304 R6305 AUD_RAMP_MONO NET: +15 DB NOSTUFF NOSTUFF
100K
5% 100PF ON 0 OHM NOSTUFF HIGH = MONO OPERATION +18 DB 47 KOHM NOSTUFF
1/16W
MF-LF
5%
50V
2 CERM
OFF NOSTUFF 0 OHM LOW = STEREO OPERATION +24 DB 0 OHM NOSTUFF
402 2 0402
54 AUD_LAMP_AVDD

NOSTUFF
1 1
R6304 R6306
0 0
5% 5%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402

R6308 AUD_LAMP_EDGE 54 AUD_LAMP_MONO 54 AUD_LAMP_GAIN 54

1
0 2
52 IN AUD_GPIO_3 AUD_SPKRAMP_WIN_SHDN_L OUT 54 55
NOSTUFF
5%
1 1 1
1/16W
MF-LF R6305 R6303 R6307
402 0 0 47K
A R6309 1
1
NOSTUFF
C6318
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013 A
100K 2 402 2 402 2 402 PAGE TITLE
100PF
5%
1/16W
MF-LF
5%
50V
2 CERM
AUDIO: LEFT SPKR AMP
402 2 0402 DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
63 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 54 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RIGHT CH SPEAKER AMP
APPLE P/N 353S3163 SPEAKER AMP GAIN = +9 DB
SPEAKER AMP RIN = 40K NOMINAL
70 54 IN =PP12V_S0_AUDIO_SPKRAMP FC_HPF, TWEETERS = ~847 HZ (4700 PF)
CRITICAL
FC_HPF, WOOFERS = ~4 HZ (1.0 UF)
C6400 1 1 C6401 C6402 1 1 C6403 C6404 1 1 C6405 C6406 1
10UF 10UF 0.1UF 1UF 0.1UF 1UF 470UF
10% 10% 10% 10% 10% 10% 20%
25V 2 25V
2 X5R 25V 2 25V
2 X5R 25V 2 25V
2 X5R 16V 2
X5R X5R X5R POLY
805 805 402 603-1 402 603-1 SM

D D

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

L6400 C6408 OUTPUT POLARITY FLIP TO
FERR-1000-OHM 1UF
AUD_LO2_R_N 1 2 AUD_RAMP_RINC_P 1 2 AUD_RAMP_RIN_P TP_AUD_RAMP_THERM NC MAKE LAYOUT MORE LOGICAL

34
35
36
37
59 52 59 59
IN
0402
10%
25V
X5R PVDD
C6413
0402 20 INR+ 0.22UF NO_XNET_CONNECTION=TRUE
THERM 17 1 2
AUD_RAMP_BOOTRP CRITICAL
L6401 C6409 19 INR- CRITICAL MIN_LINE_WIDTH=0.20MM
FERR-1000-OHM 1UF ONLY WOOFERS ON UNDER WINDOWS U6400 BOOTR+ 30
MIN_NECK_WIDTH=0.15MM 20%
AUD_RAMP_OUTPR
MIN_LINE_WIDTH=0.6MM
55 L6405
110-OHM-3A
AUD_SPKR_RWFR_OUT_P OUT 57 59
25V MIN_NECK_WIDTH=0.25MM NO_XNET_CONNECTION=TRUE
59 52 IN AUD_LO2_R_P 1 2 59 AUD_RAMP_RINC_N 1 2 59 AUD_RAMP_RIN_N 54 IN AUD_SPKRAMP_WIN_SHDN_L 22 SDNR* SSM3302 X5R
603 AUD_RAMP_OUTNR 4
DLY5ATN111SQ2
SYM_VER-2 3 CRITICAL
0402
10%
LFCSP
OUTR+
28 55
1 C6423
25V 29 1000PF
X5R 5%
0402 55 AUD_RAMP_MONO 16 MONO 55 AUD_RAMP_OUTPR 1 2 2 25V
CERM
L6402 C6410 26
C6414 0402
FERR-1000-OHM 4700PF WOOFERS & TWEETERS ON UNDER MAC OS OUTR- 27 0.22UF AUD_RAMP_OUTNR 55 AUD_SPKR_RWFR_OUT_N 57 59
OUT
MIN_LINE_WIDTH=0.6MM
59 53 52 IN AUD_LO1_R_P 1 2 59 AUD_RAMP_LINC_P 1 2 59 AUD_RAMP_LIN_P 54 IN AUD_SPKRAMP_MAC_SHDN_L 9 SDNL* AUD_RAMP_BOOTRN 1 2 MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.20MM
0402
5% BOOTR- 25 MIN_NECK_WIDTH=0.15MM 20%
50V 11 INL+ 25V
NPO-C0G-CERM X5R
0805 12 INL- EDGE 10 AUD_RAMP_EDGE 55
603

L6403 C6411 C6415

FERR-1000-OHM 4700PF BOOTL+ 1 0.22UF NO_XNET_CONNECTION=TRUE
59 53 52 IN AUD_LO1_R_N 1 2 59 AUD_RAMP_LINC_N 1 2 59 AUD_RAMP_LIN_N 55 AUD_RAMP_GAIN 21 GAIN AUD_RAMP_BOOTLP 1 2 CRITICAL
C 0402
5%
50V OUTL+
2
3
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM 20%
25V
AUD_RAMP_OUTPL
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
L6407
110-OHM-3A
AUD_SPKR_RTWT_OUT_P
NO_XNET_CONNECTION=TRUE
OUT 57 59 C
NPO-C0G-CERM X5R DLY5ATN111SQ2 CRITICAL
0805 AUD_RAMP_AVDD 8 VREG/AVDD 603 4 SYM_VER-2 3
55
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM 4
1 C6424
VOLTAGE=5V 1000PF
OUTL- 5 5%
1 2 2 25V
CERM
0402
70 58 54 52 38 =PP3V3_S0_AUDIO 23 REGEN BOOTL- 6 C6416
0.22UF AUD_RAMP_OUTNL AUD_SPKR_RTWT_OUT_N OUT 57 59
1 2 MIN_LINE_WIDTH=0.6MM
AUD_RAMP_BOOTLN MIN_NECK_WIDTH=0.25MM
18 MIN_LINE_WIDTH=0.20MM
NC MIN_NECK_WIDTH=0.15MM
NC 13 20%
NC 25V
C6417 1 14 X5R
603
2.2UF AGND PGND
TEST 15
20%
10V THRM_PAD CRITICAL CRITICAL
X5R-CERM 2
402
C6420 C6422 1

7
24

31
32
33
38
39
40
NO_XNET_CONNECTION=TRUE 1 NO_XNET_CONNECTION=TRUE
1000PF 1000PF
5% 5%
25V 25V
CERM 2 CERM 2
PINS 14 & 15 ARE TEST PINS AND 0402 0402

SHOULD BE TIED TO GND

CRITICAL CRITICAL
1
NO_XNET_CONNECTION=TRUE C6419 1 C6421 NO_XNET_CONNECTION=TRUE
1000PF 1000PF
5% 5%
2 25V
CERM 2 25V
CERM
0402 0402

B B

GAIN R6406 R6407

+9 DB NOSTUFF 0 OHM
EDGE RATE +12 DB NOSTUFF 47 KOHM
CONTROL R6404 R6405 AUD_RAMP_MONO NET: +15 DB NOSTUFF NOSTUFF
ON 0 OHM NOSTUFF HIGH = MONO OPERATION +18 DB 47 KOHM NOSTUFF
OFF NOSTUFF 0 OHM LOW = STEREO OPERATION +24 DB 0 OHM NOSTUFF
55 AUD_RAMP_AVDD

NOSTUFF
1 1
R6404 R6406
0 0
5% 5%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402

AUD_RAMP_EDGE 55 AUD_RAMP_MONO 55 AUD_RAMP_GAIN 55

NOSTUFF
1 1 1
R6405 R6403 R6407
0 0 47K
A 5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013 A
2 402 2 402 2 402 PAGE TITLE

AUDIO: RIGHT SPKR AMP

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

70 =PP3V3_S0_AUDIO_DIG

CRITICAL
PORT B LEFT(HEADSET MIC)
HP=80HZ, LP=10.63KHZ
MIKEY RECEIVER
WRITE: 0X72 READ: 0X73
CKT
APN 353S2640
I2C ADDRESSES
MIKEY
MIKEY
READ
WRITE
0111
0111
0011
0010
0X73
0X72
R65621 C6555 1 1 C6560 CHS READ 0111 0111 0X77
10K 4.7UF 0.1UF
5% 20% 10% MIKEY 1A CHS WRITE 0111 0110 0X76
1/20W 10V 2 16V
X5R-CERM 2 X7R-CERM
MF 0402 0402 APN:353S2640
201 2
MIKEY ADDRESS: WRITE=72H, READ=73H
AUDIO JACK: HP CONNECTOR WITH MIKEY
PLACE XWS 6500 & 6501 AT J6500 PINS

14
15
CRITICAL

D AVDD
U6551
D
I2C PULLUPS ON SOUTHBRIDGE PAGE CD3285A0
MQFN-RSV
47 =I2C_MIKEY_SCL 3 SCL MICBIAS 10 HS_MIC_BIAS 56
IN
MIN_LINE_WIDTH=0.25MM
11 HS_SW_DET MIN_NECK_WIDTH=0.20MM
47 =I2C_MIKEY_SDA 2 SDA DETECT
BI

12 AUD_I2C_INT_L 4 INT* BYPASS 9 HS_RX_BP

OUT
1 NO_XNET_CONNECTION=TRUE
20 IN AUD_IPHS_SWITCH_EN ENABLE
R65541
HS_HDET 13 HDET 1K
NOSTUFF 5%
1/16W
16
R6561 CS MF-LF
402 2
47K 1 C6556
58 IN AUD_PORTD_DET_L 1 2
R65551 DGND AGND 0.01UF
10%
5% 100K
2 25V

5
6

7
8
12
1/16W 5%
MF-LF X7R
1/20W 402
402 MF
201 2

59 58 56 52 GND_AUDIO_CODEC

C6552 R6550
0.1UF 2.2K 2
1 2 1
59 52 OUT AUD_MIC_INL_P 59 AUD_HS_MIC_RC_P AUD_HS_MIC_P IN 56 59

5%
10% CRITICAL 1/16W CRITICAL
16V 1
C X7R-CERM
0402
R6556
100K
5%
1 C6550
0.0082UF
MF-LF
402 1 C6558
27PF
C
1/20W 10% 5%
25V 50V
C6553 MF
201 2
2 X7R-CERM
0402 R6551
2 CERM
0402-1
0.1UF 0
1 2 AUD_HS_MIC_RC_N 1 2
59 52 OUT AUD_MIC_INL_N 59 AUD_HS_MIC_N IN 56 59

5%
10% 1/16W
16V MF-LF
X7R-CERM 402
0402
R/C6750 FILTER TO ADDRESS OUT-OF-BAND
NOISE ISSUE SEEN ON EARLY HEADSETS
(SEE RADAR # 6210118)
NOSTUFF
NO_XNET_CONNECTION=TRUE
R65531
1K
5%
1/16W
MF-LF
402 2

L6500
FERR-1000-OHM 59 58 56 52 GND_AUDIO_CODEC

58 AUD_TYPEDET_R 1 2
OUT
0402

L6501
FERR-1000-OHM
59 56 AUD_HS_MIC_N 1 2
OUT
0402
APN 516S0687
L6502
FERR-1000-OHM CRITICAL
B 59 56 OUT AUD_HS_MIC_P 1 2 NO_XNET_CONNECTION=TRUE B
0402
J6500 CRITICAL
CRITICAL 54722-0224 L6507
L6503 F-ST-SM FERR-120-OHM-2.0A
FERR-120-OHM-2.0A 1 2 1 2
AUD_J1_TYPEDET_R AUD_J1_HP_OUTL MAX97220_OUTL IN 53
HS_MIC_BIAS 1 2 3 4 MIN_LINE_WIDTH=0.25MM
56 59 AUD_J1_MIC_N AUD_J1_HP_PORT_REF MIN_NECK_WIDTH=0.20MM 0402
0402 MIN_LINE_WIDTH=0.25MM CRITICAL
MIN_NECK_WIDTH=0.20MM 59 AUD_J1_MIC_P 5 6 AUD_J1_HP_OUTR
7 8
L6508
FERR-120-OHM-2.0A
9 10
1 2 AUD_HP_PORT_REF 53
11 12 OUT
CRITICAL 0402
L6511 AUD_J1_MIC_BIAS 13 14
CRITICAL
FERR-120-OHM-2.0A 15 16
=PP3V3_S4_AUDIO_DIG 1 2 AUD_J1_PP3V3_S0 17 18 =I2C_CHS_SCL
L6509
70 IN 47 FERR-120-OHM-2.0A
0402 MIN_LINE_WIDTH=0.25MM 47 =I2C_CHS_SDA 19 20 AUD_SPDIF_OUT 52 79
IN IN 1 2 MAX97220_OUTR
MIN_NECK_WIDTH=0.20MM 21 22 IN 53
AUD_J1_TIPDET2_R AUD_J1_TIPDET1_R MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM 0402

L6510
FERR-1000-OHM
L6505 1 2 AUD_TIPDET1_R OUT 58
FERR-1000-OHM 0402
1 2
58 OUT AUD_TIPDET2_R
0402

R6506
GND_AUDIO_CODEC 1
0 2 AUD_J1_GND_ANALOG
A 59 58 56 52 IN
5%
1/16W
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=0V NOSTUFF NOSTUFF NOSTUFF SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013 A
PAGE TITLE
MF-LF
402
NOSTUFF NOSTUFF NOSTUFF DZ6503 DZ6504 DZ6505
DZ6500

2
DZ6501 DZ6502 ESDALC5-1BM2
SOD882
ESDALC5-1BM2
SOD882
ESDALC5-1BM2
SOD882
AUDIO: Jack, Mikey, CHS Switch
2

ESDALC5-1BM2 ESDALC5-1BM2 ESDALC5-1BM2

DRAWING NUMBER SIZE

SOD882 SOD882
SOD882
Apple Inc. 051-0164 D
POLARITY REVISION

1
INTENTIONALLY R
12.4.0
OPPOSIDE
1

1
2

NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
65 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 56 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SPEAKER CABLE CONNECTORS
APPLE P/N 518S0862

CRITICAL CRITICAL
J6603 J6602
504050-0691 504050-0691
M-RT-SM M-RT-SM
7 7
WOOFER (BL) WOOFER (BR)
59 54 AUD_SPKR_LWFR_OUT_P 1 59 55 AUD_SPKR_RWFR_OUT_P 1
IN IN
59 54 AUD_SPKR_LWFR_OUT_N 2 59 55 AUD_SPKR_RWFR_OUT_N 2

D 59
IN
OUT AUD_SPKR_VENDOR_ID_L
3 59
IN
OUT AUD_SPKR_VENDOR_ID_R
3 D
4 4
59 54 IN AUD_SPKR_LTWT_OUT_P 5 59 55 IN AUD_SPKR_RTWT_OUT_P 5
59 54 AUD_SPKR_LTWT_OUT_N 6 59 55 AUD_SPKR_RTWT_OUT_N 6
IN IN

TWEETER (FL) 8
TWEETER (FR) 8

C C

B B

A SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013 A
PAGE TITLE

Audio: Spkr/Mic Conn.

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

IPHS HS Detect Debounce CKT

70 55 54 52 38 =PP3V3_S0_AUDIO

R67441
100K
5%
1/20W
MF
201 2 R6745
0
D
AUD_IP_PERPH_DET_DB 1
5%
2 AUD_IP_PERIPHERAL_DET
OUT 12
D
1/16W
D 3 MF-LF
Q6741 402
SSM6N15AFE
SOT563
L6743 NC
FERR-1000-OHM
AUD_J1_DET_RC 1 2 AUD_IP_PERPH_DET_R 5 G S 4
58
0402
Q6741 D 6
SSM6N15AFE
AUDIO CONNECTOR DETECT STATES SOT563

NOSTUFF
1 C6741 NOTHING SPDIF HEADPHONE
0.1UF 2 G S 1
10%
16V
AUD_J1_TYPEDET_R 1 1 0
2 X7R-CERM
0402
AUD_J1_TIPDET_R 0 1 1
AUD_OUTJACK_INSERT_L 1 0 0
AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV

PORT D DETECT (HEADPHONES) PORT B DETECT(SPDIF DELEGATE)

59 58 52 OUT AUD_SENSE_A
C 1
C
58 56 52 IN PP4V5_AUDIO_ANALOG R6795 1
R6796
5.11K
1%
1/16W
1%
20.0K
1/16W
Target Display Mode Detect
MF-LF MF-LF
1 2 402 2 402
R6742
47K 59 58 52 IN AUD_SENSE_A
5% 1 AUD_PORTD_DET_L OUT 56 AUD_PORTB_DET_L NC
1/20W
MF 1
201 2
S R6743
47K
AUD_TIPDET1_R
SOT-563-HF
NTZD3152P
5%
1/20W
Q6796 D 3 Q6796 D 6
56 IN 2 MF SSM6N15AFE SSM6N15AFE 1
R6731
G Q6740 201 2 SOT563 SOT563
R67411 1%
39.2K
47K D 1/16W
5% 4 MF-LF
1/20W 6 5 G S 4 2 G S 1 2 402
MF
201 2
S AUD_J1_DET_RC 58
AUD_OUTJACK_INSERT_L AUD_PORTA_DET_L NC
SOT-563-HF
56 IN AUD_TIPDET2_R 5 NTZD3152P
G Q6740 APN:376S1032 TBT/DP Audio Enable
Q6797 D 3 Q6800 D 3
D SSM6N15AFE Q6797 D 6 SSM6N15AFE
3 SOT563 SOT563
SSM6N15AFE
SOT563 L6732
FERR-1000-OHM
R6792 5 G S 4 DP_TBT_SEL 1 2 AUD_LI_TIPDET 5 G S 4
41 11 IN
47K 2 G S 1 0402
AUD_TIPDET_INV 1 2

5%
1/16W R67301
R67911 MF-LF AUD_OUTJACK_INSERT 10K
B 100K
5%
402 1
C6791
0.1UF
5%
1/20W
MF
B
1/20W 20% 10V 201 2
MF 2 CERM 402
201 2
59 58 56 52 GND_AUDIO_CODEC
59 58 56 52 GND_AUDIO_CODEC

PLACE C6700 CLOSE TO Q6700 PIN 4

58 56 52 IN PP4V5_AUDIO_ANALOG

C6700 1
0.1UF
10%
16V
R67011 1
R6703
X7R-CERM 2 270K 100K
0402 5% 5%
1/20W
MF
Q6700 1/20W
201 2 DMC2400UV MF
4

59 58 56 52 GND_AUDIO_CODEC SOT563 2 201

AUD_TYPEDET_OD_INV
S

56 IN AUD_TYPEDET_R
P-CHN
5

6
D

D
Q6700
3

N-CHN

A AUD_TYPEDET_OD 2 G DMC2400UV
SOT563
SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013 A
PAGE TITLE
S
AUDIO: Detects/Grounding
R67021 DRAWING NUMBER SIZE
100K 1 051-0164 D
5%
1/20W Apple Inc. REVISION
MF R
201 2 12.4.0
59 58 56 52 GND_AUDIO_CODEC NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
67 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 58 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_SPACING_RULE_HEAD TABLE_PHYSICAL_RULE_HEAD

CODEC OUTPUT SIGNAL PATHS SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM

FUNCTION VOLUME/MUTE CONVERTER PIN COMPLEX MAC SHDN WIN SHDN DET ASSIGNMENT AUDIO * 0.1 MM ? AUDIODIFF * Y 0.1 MM 0.1 MM 10 MM 0.1 MM 0.1 MM

HP/LINE OUT 0X03 (3) 0X03 (3) 0X0A (10,D) GPIO_2 GPIO_2 0X0A (DET D) TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM

SPKROUT * 0.2 MM ? SPKROUTDIFF * Y 0.6 MM 0.25 MM 10 MM 0.2 MM 0.2 MM

PRIMARY SPKRS (WFR) 0X04 (4) 0X04 (4) 0X0B (11) MICBIAS GPIO_3 N/A
SECONDARY SPKRS (TWT) 0X03 (3) 0X03 (3) 0X0A (10,V24) MICBIAS N/A N/A
SPDIF OUT N/A 0X08 (8) 0x10 (16) N/A N/A 0X0D (DET B) TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_TYPE
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_PHYSICAL_ASSIGNMENT_ITEM

AUDIODIFF * AUDIODIFF
CODEC INPUT SIGNAL PATHS TABLE_PHYSICAL_ASSIGNMENT_ITEM

SPKROUTDIFF * SPKROUTDIFF
FUNCTION CONVERTER PIN COMPLEX ENABLE/CONTROL DET ASSIGNMENT AUD_LO1_L_P 52 53 54

D SPDIF IN
INTERNAL MIC ARRAY
0X07
0X06
(7)
(6)
0x0F
0X0E
(15)
(14,LEFT & RIGHT)
N/A
N/A
0X09 (DET A)
N/A
I215

I216
AUDIO_DIFFPAIR

AUDIO_DIFFPAIR
AUDIODIFF

AUDIODIFF
AUDIO

AUDIO AUD_LO1_L_N 52 53 54 D
0X05 (5) 0X12 (18,LEFT) I217 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_L_C_P 53

EXTERNAL MIC 0X06 (6) 0X0D (13,V22,B,LEFT) Lynx POINT GPIO 16 Lynx POINT GPIO 5 (RCVR INT) I218 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_L_C_N 53
Lynx POINT GPIO 3 (PERIPH DET)
I211 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_R_P 52 53 55

AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_R_N 52 53 55

I212
OTHER DETECT AUD_LO1_R_C_P
I210 AUDIO_DIFFPAIR AUDIODIFF AUDIO 53

FUNCTION CONVERTER PIN COMPLEX ENABLE/CONTROL DET ASSIGNMENT I209 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_R_C_N 53

MULTIPLE SPKR VENDORS N/A N/A N/A 0X0C (DET C) I208 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_L_P 52 54

I206 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_L_N 52 54

I207 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_R_P 52 55

AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_R_N 52 55

I204

I205 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LINC_P 55

AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LINC_N 55

I203
I220 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_RINC_P 55

I219 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_RINC_N 55

AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LIN_P 55

I222

I221 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LIN_N 55

I224 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_RIN_P 55

I223 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_RIN_N 55

70 59 52 =PP5V_S0_AUDIO
I226 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_LINC_P 54

I225 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_LINC_N 54

SPEAKERID SPEAKERID
I227 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RINC_P 54
R68101 1
R6811 I229 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RINC_N 54
100K 100K AUD_LAMP_LIN_P
1% 1% I228 AUDIO_DIFFPAIR AUDIODIFF AUDIO 54
1/16W 1/16W
MF-LF MF-LF I230 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_LIN_N 54
402 2 2 402
I264 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RIN_P 54

C 57 IN AUD_SPKR_VENDOR_ID_L AUD_SPKR_VENDOR_ID_R IN 57 I263 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RIN_N 54

C
R68121 1
R6813
100K 100K
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402 PORT C DETECT(SPEAKER MISMATCH)
SPEAKERID SPEAKERID
58 52 OUT AUD_SENSE_A I236 AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INL_P 53

AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INL_N 53

I238
SPEAKERID
I237 AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INR_P 53
R6816 SPEAKERID I239 AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INR_N 53
100K 2 1
1
R6894 I240 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_RWFR_OUT_P 55 57

1% 10K I241 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_RWFR_OUT_N 55 57

1/16W 1%
MF-LF 1/16W I242 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_RTWT_OUT_P 55 57
402 MF-LF
402 2 I243 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_RTWT_OUT_N 55 57

I244 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LWFR_OUT_P 54 57

70 59 52 =PP5V_S0_AUDIO I246 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LWFR_OUT_N 54 57

SPEAKERID I245 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LTWT_OUT_P 54 57

NC AUD_PORTC_DET_L
1 C6810 I247 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LTWT_OUT_N 54 57
0.1UF
10%
16V
2 X7R-CERM
0402 AUD_MIC_INL_P
I326 AUDIO_DIFFPAIR AUDIODIFF AUDIO 52 56

Q6800 D 6
I327 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_MIC_INL_N 52 56
SSM6N15AFE I328 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_HS_MIC_RC_P 56
SPEAKERID SOT563
CRITICAL I329 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_HS_MIC_RC_N 56
SPEAKERID
U6800 SPEAKERID
L6802 I254 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_HS_MIC_P 56

MAX9119_POS 3 5 MAX9119EXK-T R6820 FERR-1000-OHM 2 G S 1 AUD_HS_MIC_N 56

B SC70-5
1 MAX9119_OUT 1
33 2 SPKR_MATCH_DRV_R 1 2 SPKR_MATCH_DRV
I255

I324
AUDIO_DIFFPAIR

AUDIO_DIFFPAIR
AUDIODIFF

AUDIODIFF
AUDIO

AUDIO AUD_J1_MIC_P 56 B
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_J1_MIC_N 56
5% 0402 I325
MAX9119_NEG 4 1/16W
2 MF-LF
402

70 59 52 =PP5V_S0_AUDIO
SPEAKERID
R68141
226K 58 56 52 GND_AUDIO_CODEC
1%
1/16W
MF-LF
402 2 SPEAKERID
R6817
37.4K2
1
1%
SPEAKERID 1/16W
SPEAKERID MF-LF
R68151 1 C6811
402
75K 2.2UF
1% 10%
1/16W 16V
MF-LF 2 X7R-CERM
402 2 805

A SYNC_MASTER=J16_DIRK SYNC_DATE=03/07/2013 A
PAGE TITLE

AUDIO: Speaker ID
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

3.425V "G3Hot" Regulator

D Switching freq: 409 kHz = 13.5

L6901
D
TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
MLB to AC-DC Connector 138S0676 138S0691 C6905
TABLE_ALT_ITEM

70 =PP12V_G3H_REG_3V42_G3H
CRITICAL
1 C6906 1 C6907 1 C6902 84 P3V42G3H_BOOST
J6900 1UF 1UF 10UF 1
43650-0603
F-RT-TH
10%
25V
10%
25V
10%
25V R6901
2 X6S-CERM 2 X6S-CERM 2 X6S 150K 1 C6903

3
1 0402 0402 0805 1% 0.22UF
1/16W VIN BOOST 10%
2 MF-LF 16V CRITICAL
PP12V_G3H_ACDC
3
70
2 402 U6900 2 CERM
402 L6901
LT3470AED 33UH PP3V42_G3H_REG 70
4 DFN Vout = 3.425
84 P3V42G3H_SHDN_L 8 SHDN* SW 4 84 P3V42G3H_SW 1 2 250mA max output
5 EMC EMC CRITICAL (Switcher limit)
6 BIAS 2 CDPH4D19FHF-SM
J6900.4:3mm J6900.5:3mm J6900.4:4mm NOSTUFF 7 NC
1 C6911 1 C6912 1 C6913 1 NC
10UF 1000PF 1000PF
R6902 1 C6901 FB 1
10% 5% 5%
49.9K 1000PF THRM
1%
2 16V
X5R-CERM 2 25V
CERM 2 25V
CERM 1/16W
MF-LF
5%
25V
2 CERM
GND PAD 1 C6904 1
R6903 1 C6905
22PF 22UF

9
0805 0402 0402
2 402 0402 5% 348K 20%
50V <Ra> 1% 6.3V
2 CERM 1/16W 2 X5R-CERM1
0402 MF-LF 0603
2 402
84 P3V42G3H_FB

1
R6904
200K
C <Rb> 1%
1/16W
MF-LF
C
MLB to AC-DC Supplemental Signal Connector 2 402

SILK_PART=PwrSig
CRITICAL Vout = 1.25V * (1 + Ra / Rb)
J6901
53780-8606
M-RT-SM
7
R6911 70 64 61 =PP3V3_S0_VRD
100
45 OUT PWR_BTN 1 2 PWR_BTN_R 1
5% 2
1/16W 2 1
C6914 1 MF-LF
402
D6911 81 50 OUT SNS_ACDC_N 3 R6913
1UF 6.8V-100PF 81 50 SNS_ACDC_P 4 10K
OUT 5%
10% 402
6.3V
CERM 2
402 1 60 45
BURSTMODE_EN_R_L
SMC_ACDC_ID
5
6
1/16W
MF-LF
2 402
12V S5 FET CRITICAL
Q6970
OUT IRFH3702TRPBF
PQFN
8 60 45 SMC_ACDC_ID

R6912

S
=PP12V_G3H_FET_P12V_S5 PP12V_S5_FET

1
C6916 1 70 OUT 70
1K
65 45 IN BURSTMODE_EN_L 1 2 1UF
10%
5% 6.3V

G
C6915 1 1/16W 2 CERM 2
0.1UF MF-LF
402
D6912 402
10% 6.8V-100PF

4
16V
X7R-CERM 2 402
0402 1
1
C6970
0.1UF
10%
16V
2 X7R-CERM
FET_EN_P12V_S5_R
0402
B B

1
1
VCC R6972
49.9K
U6970
SLG5AP022-200030V
1%
1/16W
MF-LF
Input: 2.4V to 5.5V 2 TDFN 2 402
45 44 IN SMC_PM_G2_EN ON D 5
3 CRITICAL 7
NC NC G FET_EN_P12V_S5

SMC_PM_G2_EN IS PULLED DOWN ON SMC PAGE S 6

PG 8 PM_PGOOD_FET_P12V_S5 68
OUT
THRM
GND PAD

9
A SYNC_MASTER=J16_ROSSANA SYNC_DATE=03/04/2013 A
PAGE TITLE

Power Connectors / VReg G3Hot

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

CPU VCC S0 Regulator 70 62 =PP5V_S0_REG_CPUVCC_S0

Pull-ups 1
OC trip point: 114 A 1
R7000 83 61 REG_PWM_CPUVCC_1_R R7026 1
0
2 REG_PWM_CPUVCC_1 62 83 (pu 2)
PPVCCIO_S0_CPU OUT
18 10 8 6 5 2.2
5% MF-LF
5 E10 5%
1/16W 1/16W 402
Switching freq: 403 kHz = C7017 1 NOSTUFF
MF-LF
REG_PWM_CPUVCC_2_R R7027 1
0
2 REG_PWM_CPUVCC_2 (pu 2)
R7003 2 402 83 61 OUT 62 83
0.1UF 1 1 1 REG_VCC_U7000 5% MF-LF
10% R7017 R7018 R7019 83 61
1/16W 402
16V 54.9 90.9 110 0
X7R-CERM 2 1 R7028
0402 1% 1% 1% C7000 83 61 REG_PWM_CPUVCC_3_R 1 2 REG_PWM_CPUVCC_3 OUT 62 83 (pu 2)
Compensation and feedback 1/16W 1/16W 1/16W 10UF 5% MF-LF
MF-LF MF-LF MF-LF 20%
83 71 62 61 AGND_CPU 2 402 2 402 2 402
1/16W 402

D 83 61 REG_CPUVCC_COMP
83 61 8 CPU_VIDSCLK
PLACE_NEAR=U7000.15:12.7mm PLACE_NEAR=U7000.13:12.7mm
2 16V
X6S-CERM
0603 61 REG_PWM_CPUVCC_4_R R7029 1
0
2 REG_PWM_CPUVCC_4 OUT 72 (pu 2) D
REG_CPUVCC_DVC 61 83 5% MF-LF
CPU_VIDALERT_L 1/16W 402

25
83 61 8
1 C7031 1 C7030 CPUVCC:4PHASE
1 CPU_VIDSOUT
68PF 0.0012UF R7037 83 61 8
5% 10% 1.82K VCC
2 50V
COG-CERM 2 50V
CERM 1%
0402 0402 1/16W
MF-LF
U7000
CPUVCC_COMP_RC 2 402 ISL6372
83
(pgood) 61 REG_CPUVCC_PGOOD 11 VR_RDY QFN FS_FDVID 24 REG_CPUVCC_FDVID 61 83 (straps)
1
CPUVCC_DVC_RC 83 CRITICAL
R7030 83 61 REG_CPUVCC_MEMVRSEL 26 MEMVRSEL EN_PWR_OVP 3 PM_EN_REG_CPUVCC_S0 68
7.15K 1 C7037 Pull-ups 2
1% (straps) REG_CPUVCC_TMX 18 TMX_DRP_DE_TC 1M
1/16W 0.0012UF 83 61
VIN- 1 83 REG_CPUVCC_VIN R70141 2
MF-LF 10% 83 61 REG_VCC_U7000 (straps) 83 61 REG_CPUVCC_IMX 20 IMADR_BTRM
2 402 50V
2 CERM To feedback 15 VIN+ 2 1% MF-LF PP12V_S0_CPUVCC_FLT 62 83
0402 (pu 1) 83 61 8 IN CPU_VIDSCLK SVCLK 1/16W 402
REG_CPUVCC_FB 61 83
14 29
NOSTUFF NOSTUFF NOSTUFF CPUVCC:3PHASE (pu 1) 83 61 8 OUT CPU_VIDALERT_L SVALERT* PWM1 REG_PWM_CPUVCC_1_R 61 83

NOSTUFF 1 1 1 1 (pu 1) CPU_VIDSOUT 13 SVDATA PWM2 27 REG_PWM_CPUVCC_2_R

1 1 C7033 R7021 R7022 R7023 R7024 83 61 8 BI 61 83
R7031 1 C7038 0 0 0 0 PWM3 30 REG_PWM_CPUVCC_3_R 61 83
1K 390PF 5% 5% 5% 5% (vsen in) 83 61 REG_CPUVCC_VSEN 5 VSEN
1% 10% 0.0012UF 1/16W 1/16W 1/16W 1/16W PWM4 28 REG_PWM_CPUVCC_4_R 61
50V 10%
1/16W 2 X7R-CERM 50V MF-LF MF-LF MF-LF MF-LF 4
MF-LF 2 CERM 2 402 2 402 2 402 2 402 83 61 REG_CPUVCC_RGND RGND
2 402
0402
0402 10 ISEN1- 37 REG_ISENVCC_1_NR IN 62 83
83 61 REG_PWM_CPUVCC_1_R 83 61 REG_CPUVCC_DVC DVC_MEM
83 CPUVCC_FB_R_1 CPUVCC_FB_RC 83 CPUVCC_FB_RC_2 83
8 ISEN1+ 38 REG_ISENVCC_1_P IN 62 83
83 61 REG_PWM_CPUVCC_2_R (fb in) 83 61 REG_CPUVCC_FB FB
OMIT_TABLE
1 1 NOSTUFF REG_PWM_CPUVCC_3_R REG_CPUVCC_PSICOMP 7 ISEN2- 33 REG_ISENVCC_2_NR
R7032 R7033 1 83 61 (psi comp) 83 61 PSICOMP IN 62 83

750 249 R7038 61 REG_PWM_CPUVCC_4_R ISEN2+ 34 REG_ISENVCC_2_P IN 62 83

1% 1% 3.83K (hf comp) 83 61 REG_CPUVCC_HFCOMP 6 HFCOMP
1/16W 1/16W 1%
MF-LF MF-LF 1/16W 9 COMP ISEN3- 39 REG_ISENVCC_3_NR IN 62 83
(comp out) REG_CPUVCC_COMP
2 402 2 402 MF-LF 83 61
ISEN3+ 40 REG_ISENVCC_3_P
2 402 IN 62 83

AGND_CPU 61 62 71 83 (straps) 83 61 REG_CPUVCC_NPSI 22 AUTO_NPSI

83 CPUVCC_FB_R_2 ISEN4- 35 REG_ISENVCC_4_NR IN 71

(imon out) REG_CPUVCC_IMON 12 IMON ISEN4+ 36 REG_ISENVCC_4_P

C7034 To PSI comp
83 61 48 IN 72
R7034
C 2.2NF
1 2 83 CPUVCC_PSICOMP_RC 1
787
2 REG_CPUVCC_PSICOMP 61 83
83 61 REG_VCC_U7000 83 61 REG_CPUVCC_MEMVRSEL
(vr hot out) 61 REG_CPUVCC_VRHOT_L 16 VR_HOT* RSET 23 REG_CPUVCC_RSET 83 C
1% 83 61 REG_CPUVCC_TM 21 TM_EN_OTP OPEN1 17
10% 1/16W NC
10V
X5R-CERM
MF-LF NOSTUFF OPEN2 19 NC
402
0201 1
R7039 OPEN3 32 NC
To VSense To HF comp 0 R70091 OMIT_TABLE
R7035 R7036 5% 0 GND THRM_PAD
1
R7016
10 2.67K 1/16W 5%
1 2 83 61 REG_CPUVCC_VSEN 1 2 REG_CPUVCC_HFCOMP 61 83 MF-LF 1/16W Tie to GND for VR12.5 12.7K

41
1% NOSTUFF 1% 2 402 MF-LF
402 2 OMIT 1%
1/16W
1/16W 1/16W MF-LF
MF-LF 1 C7035 MF-LF U7000.41:6MM
402 402 2 402
0.01UF 83 61 REG_CPUVCC_DVC XW7000
20% 83 71 62 61 AGND_CPU SM
16V
2 X7R-CERM 1 2 AGND_CPU 61 62 71 83
0402
AGND_CPU 61 62 71 83 TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_ITEM

114S0324 1 RES,12.7K,402 R7016 CPUVCC:3PHASE

TABLE_5_ITEM

Voltage sense input IMON output Temp measurement 114S0316 1 RES,10.2K,402 R7016 CPUVCC:4PHASE

OMIT
R7150.1:25MM 83 61 REG_VCC_U7000 83 61 REG_VCC_U7000

=PPCPUVCC_S0_CPU
XW7042 R7042
70 48 SM
1K Straps
1 2 83 SNS_VCC_XW_P 1 2
R70521 R70901
5% 2.49M 1K
1/16W 1% 5% 83 61 REG_VCC_U7000
MF-LF 1/16W 1/16W
402 NO_XNET_CONNECTION=TRUE MF MF-LF
Sense from CPU R7040 R7041 To voltage sense 0402 2 To sense amps 402 2
0 10 OMIT_TABLE NOSTUFF
83 8 CPU_VCCSENSE_P 1 2 83 CPU_VCCSENSE_R_P 1 2 REG_CPUVCC_VSEN 61 83 REG_CPUVCC_IMON 48 61 83 REG_CPUVCC_TM 61 83
IN OUT 1 1 1 1
R7001 R7003 R7005 R7007
B 5%
1/16W
MF-LF
5%
1/16W
MF-LF 1
NOSTUFF
C7048
OMIT_TABLE
R70501 1 C7050
33NF
1 1 C7090
0.1UF
340K
1% 1%
124K
1%
150K
5%
0 B
402 402
0.0012UF 402 10% 10% 1/20W 1/20W 1/20W 1/20W
10% 1% 25V RT7090 16V MF MF MF MF
NO_XNET_CONNECTION=TRUE 50V 1/16W 2 CERM 2 X7R-CERM 2 201 2 201 2 201 2 0201
R7045 R7046 2 CERM MF-LF 402 0402
402 2 6.8K
0 10 0402 REG_CPUVCC_IMX
83 61
83 9 CPU_VCCSENSE_N 1 2 83 CPU_VCCSENSE_R_N 1 2 REG_CPUVCC_RGND 61 83
0603
IN CPUVCC_IMON_R REG_CPUVCC_FDVID
83 83 61
5% 5% 2
OMIT 1/16W 1/16W 1 C7041 1 C7046 83 61 REG_CPUVCC_TMX
XW7042.2:3MM MF-LF
402
MF-LF
402 0.0012UF 0.0012UF R70511 AGND_CPU 61 62 71 83
83 61 REG_CPUVCC_NPSI
XW7047 R7047
10% 10% 30.9K
SM 2 50V
CERM 2 50V
CERM 1%
1K 0402 0402 1/16W OMIT_TABLE NOSTUFF
1 2 83 SNS_VCC_XW_N 1 2 MF-LF 1 1 1 1
5% AGND_CPU 61 62 71 83
402 2 R7002 R7004 R7006 R7008 1 C7001
1/16W
MF-LF
AGND_CPU 61 62 71 83 95.3K 0 147K 249K 0.047UF
1% 5% 1% 1% 10%
402 1/20W 1/20W 1/20W 1/20W 16V
MF MF MF MF 2 X5R
2 201 2 0201 2 201 2 201 0201

AGND_CPU 61 62 71 83

J16: 3PHASE
J17: 4PHASE
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

Power goods VRHot to ProcHot TABLE_5_ITEM

118S0311 1 RES,340K,201 R7001 CPUVCC:3PHASE

R7093 TABLE_5_ITEM

0 118S0116 1 RES,158K,201 R7001 CPUVCC:4PHASE

61 REG_CPUVCC_VRHOT_L 1 2 CPU_PROCHOT_L 6 44 45 62 76
=PP3V3_S0_VRD OUT
70 64 60 TABLE_5_ITEM

5%
1/16W 118S0575 1 RES,95.3K,201 R7002 CPUVCC:3PHASE
1 MF-LF 1 C7091
R7098 402
TABLE_5_ITEM

10K 47PF 118S0380 1 RES,44.2K,201 R7002 CPUVCC:4PHASE

5% 5% Per Intel Shark Bay PDG
50V TABLE_5_ITEM

1/16W 2 CERM
114S0206 1 RES,750 OHM,402 R7032 CPUVCC:3PHASE
A MF-LF
2 402
402
114S0211 1 RES,845 OHM,402 R7032 CPUVCC:4PHASE
TABLE_5_ITEM

SYNC_MASTER=J16_ROSSANA SYNC_DATE=03/21/2013 A
61 REG_CPUVCC_PGOOD PM_PGOOD_REG_CPUVCC_S0 69
PAGE TITLE
OUT
VReg CPU VCC Cntl
TABLE_5_ITEM

MAKE_BASE=TRUE 114S0179 1 RES,402 OHM,402 R7050 CPUVCC:3PHASE

TABLE_5_ITEM

114S0184 1 RES,453 OHM,402 R7050 CPUVCC:4PHASE DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
70 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 61 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
Filtered 12V Rail L7100
70 62 61 =PP5V_S0_REG_CPUVCC_S0 83 62 61 PP12V_S0_CPUVCC_FLT 0.36UH-30A-0.6MOHM
70 =PP12V_S0_REG_CPUVCC_S0 1 2 PP12V_S0_CPUVCC_FLT 61 62 83
SDP110808MR36MF-TH
U7110.3:3MM Acoustics E-noise Components
1 C7125
CPU Phase 1 1.0UF
10% EMC EMC EMC EMC
2 16V CRITICAL CRITICAL
X7R U7110.11:3MM U7110.11:3MM CRITICAL CRITICAL CRITICAL CRITICAL U7110.11:3MM U7110.11:3MM

3
0603
R7116 VDRV
1 C7118 1 C7119 1
C7110 1
C7111 1 C7112 1 C7113 1 C7114 1 C7115
0 1000PF 1000PF 180UF 180UF 10UF 10UF 1UF 1UF
83 REG_BOOT_CPUVCC_1_RC 1 2 83 REG_BOOT_CPUVCC_1 4 BOOT U7110 NC 8 5% 5% 20% 20% 20% 20% 10% 10%

D 5%
1/10W 39 DISB* FDMF6808N
PQFN
9
10
2 25V
CERM
0402
2 25V
CERM
0402
2 16V
POLY
TH1
2 16V
POLY
TH1
2 16V
X6S-CERM
0603
2 16V
X6S-CERM
0603
25V
2 X6S-CERM
0402
2 25V
X6S-CERM
0402 D
MF-LF
603
11
C7116 NC 6 GH CRITICAL VIN
0.22UF 12
1 2 13 CRITICAL
36 GL R7110
NC 14 CRITICAL
10% 0.0005
25V
X7R 83 REG_PHASE_CPUVCC_1 7 PHASE
42 L7110 1%
1W
0603 230NH-10%-45A-0.00031OHM MF
0612
15 83 REG_PHASE_CPUVCC1 1 2 83 PPCPUVCC_S0_SENSE_1 1 2 PPCPUVCC_S0_REG
83 61 IN REG_PWM_CPUVCC_1 40 PWM NC OUT 62 70
29 CTX01-SM 3 4
NOSTUFF REG_ISENVCC_1_P OUT 61 83
30
NOSTUFF 1 ZCD_EN* 1 C7117 NO_XNET_CONNECTION=TRUE
31 U7000.38:3MM
R7115 VSWH
0.0022UF
10% 1
0 32 C7121
CPU_PROCHOT_L 1 2 REG_THWN_1 38 THWN* 50V
76 61 45 44 6 OUT 83
33 2 CERM 220PF
402 NO_XNET_CONNECTION=TRUE 10%
5% C7121.2:2MM
1/20W 34 50V
2 VCIN 2 X7R-CERM
MF REG_SNUBBER_CPUVCC_1 83
R7121 0402
0201 35
43 1.02K
CGND PGND 83 REG_ISENVCC_1_N 1 2 REG_ISENVCC_1_NR OUT 61 83
1 NOSTUFF NO_XNET_CONNECTION=TRUE 1%
R7117 C7121.1:2MM 1/16W

5
37
41

16
17
18
19
20
21
22
23
24
25
26
27
28
1 1
MF-LF
5% C7120 402
1/8W 0.1UF
MF-LF 10%
70 62 61 =PP5V_S0_REG_CPUVCC_S0 2 805 16V
2 X7R-CERM
0402
AGND_CPU 61 62 71 83
U7130.3:3MM
CPU Phase 2 1 C7145
1.0UF EMC EMC EMC EMC
10% CRITICAL CRITICAL
2 16V
C U7130.11:3MM U7130.11:3MM CRITICAL CRITICAL CRITICAL CRITICAL U7130.11:3MM U7130.11:3MM
C

3
X7R
0603
R7136 VDRV
1 C7138 1 C7139 1
C7130 1
C7131 1 C7132 1 C7133 1 C7134 1 C7135
0 1000PF 1000PF 180UF 180UF 10UF 10UF 1UF 1UF
83 REG_BOOT_CPUVCC_2_RC 1 2 83 REG_BOOT_CPUVCC_2 4 BOOT U7130 NC 8 5%
2 25V
5%
2 25V
20%
2 16V
20%
2 16V
20%
2 16V
20%
16V
2 X6S-CERM
10%
2 25V
10%
2 25V
5%
1/10W 39 DISB* FDMF6808N 9 CERM
0402
CERM
0402
POLY
TH1
POLY
TH1
X6S-CERM
0603 0603
X6S-CERM
0402
X6S-CERM
0402
MF-LF PQFN 10
603
11
C7136 6 GH CRITICAL
0.22UF NC VIN 12
1 2 13 CRITICAL
36 GL R7130
NC 14 CRITICAL
10% 0.0005
25V
X7R 83 REG_PHASE_CPUVCC_2 7 PHASE
42 L7130 1%
1W
0603 230NH-10%-45A-0.00031OHM MF
0612
15 83 REG_PHASE_CPUVCC2 1 2 83 PPCPUVCC_S0_SENSE_2 1 2 PPCPUVCC_S0_REG
83 61 IN REG_PWM_CPUVCC_2 40 PWM NC OUT 62 70
29 CTX01-SM 3 4
NOSTUFF REG_ISENVCC_2_P OUT 61 83
30
NOSTUFF 1 ZCD_EN* 1 C7137 NO_XNET_CONNECTION=TRUE
31 U7000.34:3MM
R7135 0.0022UF
0 VSWH 32 10% 1 C7141
1 2 83 REG_THWN_2 38 THWN* 2 50V
CERM 220PF
33 NO_XNET_CONNECTION=TRUE
5% 402 10%
C7141.2:2MM
1/20W 34 2 50V
X7R-CERM
MF 2 VCIN REG_SNUBBER_CPUVCC_2
0201 35 83
R7141 0402
43
1.02K
83 REG_ISENVCC_2_N 1 2 REG_ISENVCC_2_NR
CGND PGND OUT 61 83
1 NOSTUFF NO_XNET_CONNECTION=TRUE 1%
R7137 C7141.1:2MM 1/16W
5
37
41

16
17
18
19
20
21
22
23
24
25
26
27
28

1 1
MF-LF
5% C7140 402
1/8W 0.1UF
MF-LF 10%
70 62 61 =PP5V_S0_REG_CPUVCC_S0 2 805 16V
2 X7R-CERM
0402

AGND_CPU 61 62 71 83

B 1
U7150.3:3MM
C7165
B
CPU Phase 3 1.0UF EMC EMC EMC EMC
10% CRITICAL CRITICAL
16V
U7150.11:3MM U7150.11:3MM CRITICAL CRITICAL CRITICAL CRITICAL U7150.11:3MM U7150.11:3MM
3

2 X7R
0603 1 1 1 1 1 1 1 1
R7156 VDRV C7158 C7159 C7150 C7151 C7152 C7153 C7154 C7155
0 1000PF 1000PF 180UF 180UF 10UF 10UF 1UF 1UF
83 REG_BOOT_CPUVCC_3_RC 1 2 83 REG_BOOT_CPUVCC_3 4 BOOT U7150 NC 8 5%
25V
2 CERM
5%
25V
2 CERM
20%
2 16V
20%
2 16V
20%
16V
2 X6S-CERM
20%
16V
2 X6S-CERM
10%
25V
2 X6S-CERM
10%
25V
2 X6S-CERM
5%
1/10W 39 DISB* FDMF6808N 9
0402 0402
POLY
TH1
POLY
TH1 0603 0603 0402 0402
MF-LF PQFN 10
603
C7156 11
0.22UF 6 GH CRITICAL
NC VIN 12
1 2 CRITICAL
13
36 GL R7150
10% NC 14 CRITICAL
25V 0.0005
X7R 42 L7150 1%
0603 83 REG_PHASE_CPUVCC_3 7 PHASE 1W
230NH-10%-45A-0.00031OHM MF
0612
15 83 REG_PHASE_CPUVCC3 1 2 83 PPCPUVCC_S0_SENSE_3 2 1 PPCPUVCC_S0_REG
83 61 IN REG_PWM_CPUVCC_3 40 PWM NC OUT 62 70
29 CTX01-SM 4 3
NOSTUFF REG_ISENVCC_3_P OUT 61 83
30
NOSTUFF 1 ZCD_EN* 1 C7157 NO_XNET_CONNECTION=TRUE
31 U7000.40:3MM
R7155 0.0022UF
0 VSWH 32 10% 1 C7161
1 2 83 REG_THWN_3 38 THWN* 2 50V
CERM 220PF
33 NO_XNET_CONNECTION=TRUE
5% 402 10%
C7161.2:2MM
1/20W 34 2 50V
X7R-CERM
MF 2 VCIN REG_SNUBBER_CPUVCC_3
0201 35 83
R7161 0402
70 62 61 =PP5V_S0_REG_CPUVCC_S0 1.02K
43 83 REG_ISENVCC_3_N 1 2 REG_ISENVCC_3_NR
CGND PGND NOSTUFF OUT 61 83
1 NO_XNET_CONNECTION=TRUE 1%
R7157 C7161.1:2MM 1/16W
5
37
41

16
17
18
19
20
21
22
23
24
25
26
27
28

1 1 MF-LF
R7180 5% 1 C7160 402
1K
A 1%
1/16W
MF-LF
1/8W
MF-LF
2 805
0.1UF
10%
16V
2 X7R-CERM
SYNC_MASTER=J16_ROSSANA SYNC_DATE=03/21/2013 A
402 2 PAGE TITLE
0402
CPU Output Decoupling VReg CPU VCC Phases
REG_ZCDEN 70 62 PPCPUVCC_S0_REG AGND_CPU 61 62 71 83
DRAWING NUMBER SIZE
NOSTUFF
1 Apple Inc. 051-0164 D
R7181 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL REVISION
1K R
1%
1/16W
1
C7180 1
C7181 1
C7182 1
C7183 1
C7184 1
C7185 12.4.0
MF-LF 270UF-0.006OHM 270UF-0.006OHM 270UF-0.006OHM 270UF-0.006OHM 270UF-0.006OHM 270UF-0.006OHM NOTICE OF PROPRIETARY PROPERTY: BRANCH
402 2 20% 20% 20% 20% 20% 20%
2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V THE INFORMATION CONTAINED HEREIN IS THE
TANT TANT TANT TANT TANT TANT PROPRIETARY PROPERTY OF APPLE INC.
CASE-D2 CASE-D2 CASE-D2 CASE-D2 CASE-D2 CASE-D2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
71 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 62 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

VDDQ (1.5V / 1.35V) S3 Regulator

OC trip point: 30.4 A VDDQ = R7336 + 0.65625
8 E5 * Rds(Q7310) L7310 * f(switch)
3 A VTT (FIXED)
10 mA VTTREF (FIXED)
D Switching freq: 500 kHz 70 =PP12V_S5_REG_VDDQ_S3 D
CRITICAL CRITICAL
C7310 1 C7311 1 EMC EMC
180UF 180UF 1 1 1 1 1
Q7310.1:3MM
1
Q7310.1:3MM
20%
16V 2
20%
16V 2
C7342 C7343 C7344 C7345 C7346 C7347
POLY POLY 1UF 1UF 10UF 10UF 1UF 1UF
TH1 TH1 10% 10% 20% 20% 10% 10%
25V 25V 16V 16V 25V 25V
2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM
70 =PP5V_S4_REG_VDDQ_S3 0402 0402 0603 0603 0402 0402
70 =PPVDDQ_S3_LDO_DDRVTT
R73001
2.2 C7301 1
5% 10UF
1/8W 20%
MF-LF 6.3V 2
805 2 X5R
603 82 REG_BOOT_VDDQS3_RC 82 REG_UGATE_VDDQS3_R
EMC EMC
R73161 1 C7316 R73111 L7310.2:8MM L7310.2:8MM
C7300 1 0 0.1UF 0 CRITICAL 1 C7340 1 C7341
5% 10% 5%
2.2UF 25V 1000PF 1000PF

2
1/10W 2 X6S 1/10W
10%
16V 2 MF-LF 0402 MF-LF Q7310 5% 5%
X5R VLDOIN 603 2 603 2 CSD58872Q5D 2 25V
CERM 2 25V
CERM
603 SON5X6 VIN 1 0402 0402
3 TG
82 REG_V5IN_U7300 12 V5IN CRITICAL VBST 15 82 REG_BOOT_VDDQS3 CRITICAL
DRVH 14 82 REG_UGATE_VDDQS3 VSW 6 L7310
68 PM_EN_LDO_DDRVTT_S0 17 S3
U7300 SW 13 82 REG_PHASE_VDDQS3 4 TGR 7 1.0UH-27A-1.05MOHM
IN
PM_EN_REG_VDDQ_S3 16 S5
TPS51916 8 82 REG_PHASE_VDDQS3_L 1 2 PPVDDQ_S3_REG
68 IN OUT 70
QFN
DRVL 11 82 REG_LGATE_VDDQS3 SDP1182-SM CRITICAL CRITICAL
82 REG_VDDQS3_VREF 6 VREF 5 BG NOSTUFF
20 REG_VDDQS3_PGOOD 1 1 1 C7322
PGOOD 63
1 C7317 C7320 C7321
<Ra> VDDQSNS 9 82 REG_VDDQS3_VDDQSNS 330UF-0.009OHM 330UF-0.009OHM 10UF
82 63 REG_VDDQS3_REFIN 8 REFIN PGND 1000PF 20% 20% 20%
5% 2 6.3V
C OMIT_TABLE VTT 3 PPDDRVTT_S0_LDO OUT 70 25V 2 2V
POLY
2 2V
POLY X5R
C

9
1 1 2 CERM 603
C7330 R7330 82 REG_VDDQS3_MODE 19 MODE VTTSNS 1 82 LDO_DDRVTTS0_SNS 0402
CASE-D2-HF CASE-D2-HF
0.1UF REG_VDDQS3_TRIP 1 2
10%
10K 82 18 TRIP CRITICAL
16V 1% SM REG_SNUBBER_VDDQS3 82
VTTREF 5 REG_VDDQS3_VTTREF 1 C7325
X7R-CERM 2 1/16W 82
0402 MF-LF
402 2
XW7325 22UF Critical: NOSTUFF
C7325.1:6MM 20%
VTT THRM
PGND GND GND PAD 2 6.3V
X5R-CERM-1 Need copper around Q7310 1
R7317
OMIT 603
to sink heat 0.499
10

21
<Rb> C7327 1 1%
CRITICAL 1/10W
R73311 1 C7331 1
R7335 R73361 0.22UF
10% C7326 1 MF
OMIT
49.9K 0.01UF 1K 44.2K 16V 2 603
1% 10% 1% 1% CERM 2 22UF L7310.2:10MM
1/16W 50V
2 X7R-CERM 1/16W 1/16W 402 20%
6.3V XW7310
MF-LF 0402 MF-LF MF-LF X5R-CERM-1 2
402 2 2 402 402 2 603 SM
1 2
82 AGND_VDDQS3

OMIT
Vout = 1.8 * (Rb / (Ra + Rb))
2 U7300.21:4MM

J16: 1.35V XW7300

SM
J17: 1.5V =PP3V3_S4_PWRCTL
1 70 67

Margining support 1
R7340
20K
5%
22 IN DDRREG_FB REG_VDDQS3_REFIN 63 82 1/16W
MAKE_BASE=TRUE MF-LF
TABLE_5_HEAD 2 402
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
63 REG_VDDQS3_PGOOD PM_PGOOD_REG_VDDQ_S3 OUT 68
TABLE_5_ITEM

MAKE_BASE=TRUE
114S0335 1 RES,16.5K,402 R7330 VDDQ:P1V35

B
TABLE_5_ITEM

B 114S0315 1 RES,10K,402 R7330 VDDQ:P1V5

A SYNC_MASTER=J16_ROSSANA SYNC_DATE=03/04/2013 A
PAGE TITLE

VReg VDDQ S3
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

PCH/TBT (1.05V) S0 REGULATOR

Switching freq: 500 kHz OC trip point: 12.4 A = R7450 * 8.5 E-6
DCR(L7410)

FSEL STRAP SW FREQ

GND 300 kHz
70 =PP12V_S0_REG_P1V05_S0

D VCC 1 MHz D
100k to GND 600 kHz 70 =PP5V_S0_REG_P1V05_S0 CRITICAL CRITICAL CRITICAL
1 1 C7411 1 C7412
FLOAT 500 kHz C7410
180UF 20%
10UF 10UF
20%
20%
1 1 16V 16V
R7400 R7401 2 16V 2 X6S-CERM 2 X6S-CERM
POLY
10 2.2 TH1 0603 0603
5% 5%
1/8W 1/8W
70 64 IN PP1V05_S0_REG MF-LF MF-LF
805 2 2 805
82 REG_BOOT_P1V05S0_RC
82 REG_VCC_U7400 REG_PVCC_U7400 82
R74161 1 C7416
NO_XNET_CONNECTION=TRUE 2 2 NO_XNET_CONNECTION=TRUE C7400 1 1 C7401 0 0.1UF EMC EMC
5% 10%
1UF 2.2UF 2 16V
XW7411 XW7410 10% 10% 1/10W
MF-LF
X7R-CERM Q7410.1:3MM Q7410.1:3MM
SM SM 16V 16V 0402 1 1
X5R 2 2 X5R 603 2 C7480 C7481
1 1
402 603 1UF 1UF
10% 10%
REG_P1V05S0_RTN_R REG_P1V05S0_FB_R 2 25V
X6S-CERM
25V
2 X6S-CERM
0402 0402

14
82 REG_UGATE_P1V05S0_R
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE
<Ra> <Ra> VCC PVCC
R74111
R74301 1
R7435 U7400 0
CRITICAL
3.01K 3.01K 5%
1% 1% ISL95870 1/10W Q7410
1/16W
MF-LF
1/16W
MF-LF UTQFN
MF-LF
603 2
CSD58872Q5D DCR(L7410) = 7.5 +/- 10% MOHM
402 2 PM_EN_REG_P1V05_S0 3 EN BOOT 12 REG_BOOT_P1V05S0 SON5X6 VIN 1
2 402 68 82
IN 3 TG
6 CRITICAL CRITICAL
82 REG_P1V05S0_FB FB UGATE 11 82 REG_UGATE_P1V05S0
VSW 6 L7410
<Rb> 4 1.2UH-14A-0.0075OHM
1
82 REG_P1V05S0_SREF SREF PHASE 10 82 REG_PHASE_P1V05S0 4 TGR 7
R7436 8 82 REG_PHASE_P1V05S0_L 1 2 PP1V05_S0_REG OUT 64 70
8 LGATE 15
C 1%
2.74K
1/16W
C7440
0.047UF
1 82 64 REG_P1V05S0_VO

REG_P1V05S0_OCSET 7
VO

OCSET
82 REG_LGATE_P1V05S0
5 BG
PIC0605H-SM

C7418 1 1 CRITICAL CRITICAL CRITICAL

C
MF-LF 10% 82 64 R7418
2 402 16V 1000PF 200 1 1 1 1 C7423
X7R-CERM 2 64 REG_P1V05S0_PGOOD 9 PGOOD PGND
NOSTUFF 5% 5%
C7420 C7421 C7422
0402 C7417 1 25V 330UF-0.009OHM 330UF-0.009OHM 330UF-0.009OHM 10UF
CERM 2 1/10W 20%

9
2 MF-LF 20% 20% 20%
REG_P1V05S0_RTN RTN 0.001UF 0402
2 2V 2 2V 2 2V
6.3V
2 603 2 X5R
82
10% POLY POLY POLY
50V CASE-D2-HF CASE-D2-HF CASE-D2-HF 603
REG_P1V05S0_FSEL 5 X7R-CERM 2
82 FSEL 0402
<Rb> GND PGND
1 NOSTUFF 1 82 REG_SNUBBER_P1V05S0

16
R7431 C7430 1 1 C7435 R7460 Note:
2.74K 10PF 10PF 0 NOSTUFF
1% 5% 5% 5% Regulator requires
1/16W
MF-LF
50V 50V 1/16W R74171 a minimum load to
402 2 C0G-CERM 2 2 C0G-CERM MF-LF
402 2 2.2
0402 0402
5% prevent noise in the
1/10W
MF-LF audio frequencies
82 AGND_P1V05S0 603 2

U7400.1:1MM 2
Vout = 0.5 * (1 + Ra / Rb) XW7400
SM L7410.1:3MM
1 R74501
11K R7450.2:3MM
1% 70 64 61 60 =PP3V3_S0_VRD
1/16W C7450
MF-LF 1
402 2 0.015UF R7480
1 2 20K
L7410.2:6MM 5%
10% 1 1/16W
50V R7451 MF-LF
X7R 11K 2 402
To regulator: 603-1 1%
1/16W 64 REG_P1V05S0_PGOOD PM_PGOOD_REG_P1V05_S0 OUT 68 69
MF-LF MAKE_BASE=TRUE
B 82 64 REG_P1V05S0_OCSET
2 402 B
82 64 REG_P1V05S0_VO

1.5V S0 REGULATOR

70 =PP3V3_S0_REG_P1V5_S0

PP1V5_S0_REG OUT 70
CRITICAL CRITICAL
1 C7495 1 C7490 1
R7490 CRITICAL <Ra> CRITICAL CRITICAL
10UF 10UF 20.0K 1 C7493 1 C7494
20%
2 16V
20%
2 16V
1%
1/16W
U7450 1 C7492
1
R7491 10UF 10UF
X6S-CERM X6S-CERM 20% 20%
0603 0603 MF-LF ISL80101A 150PF 2.61K 16V 16V
2 402 DFN 5% 1%
1/16W
2 X6S-CERM 2 X6S-CERM
9 1 2 50V MF-LF 0603 0603
C0G-CERM
10 VIN VOUT 2 0402 2 402
70 64 61 60 =PP3V3_S0_VRD
68 PM_EN_FET_REG_P1V5_S0 7 ENABLE ADJ 3 84 REG_P1V5S0_ADJ
IN 1
84 REG_P1V5S0_SS 6 SS R7493
PG 4 REG_P1V5S0_PGOOD 64 <Rb> 10K
A 1 C7491
84 REG_P1V5S0_ISET 8 ISET
GND
THRM
PAD
1
R7492
1.3K
5%
1/16W
MF-LF SYNC_MASTER=J16_ROSSANA SYNC_DATE=03/04/2013 A
4700PF 1% 2 402 PAGE TITLE
10%
VREG 1V05 S0 / 1V5 S0
5

50V 1/16W
2 X7R-CERM MF-LF 64 REG_P1V5S0_PGOOD PM_PGOOD_FET_REG_P1V5_S0 OUT
0402 2 402 MAKE_BASE=TRUE
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

REVISION
R
Vout = 0.5 * (1 + Ra / Rb) 12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
74 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 64 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

3.3V S5 Regulator 5V S4 Regulator

R7618 * 10 E-6
OC trip point: 12.5 A = R7658 * 10 E-6
DCR(L7610) OC trip point: 14.1 A =
DCR(L7650)
1
Switching freq: 356 kHz = 1
170 E-12 * R7633 Switching freq: 356 kHz =
170 E-12 * R7673
D 70 =PP12V_S5_REG_P3V3P5V_S5
D
CRITICAL CRITICAL CRITICAL
C7610 1 1
C7650 1
C7651
180UF 180UF 180UF
20% 20% 20%
16V 2 2 16V 2 16V
POLY POLY POLY
TH1 TH1 TH1

1
R7603
1
5%
1/8W
MF-LF
2 805

EMC EMC EMC EMC

Q7610.2:3MM Q7610.2:3MM 84 REG_VIN_U7600 Q7650.5:3MM Q7650.5:3MM
C7642 1 C7643 1 1 C7682 1 C7683
1UF 1UF 1UF 1UF
10% 10% 10% 10%
25V 25V 2 25V 25V
X6S-CERM 2 X6S-CERM 2 PP5V_S5_LDO X6S-CERM 2 X6S-CERM
0402 0402 OUT 70 0402 0402
5
1
1 C7601 R7602
2.2 D CRITICAL
4.7UF
EMC EMC 20%
6.3V
5%
1/8W
4 G
Q7650 EMC EMC
L7610.1:8MM L7610.1:8MM 2 CERM MF-LF FDMC0225 L7650.2:4MM L7650.2:4MM
C7640 1 C7641 1 603 2 805 MLP3.3X3.3 1 C7680 1 C7681
C 1000PF
5%
25V
1000PF
5%
25V 2
84 REG_VCC2_U7600
1 C7602 1 C7603 S 5%
1000PF
2 25V
5%
1000PF
2 25V
C
CERM 2 CERM 2 CRITICAL 84 REG_VCC1_U7600 84 REG_BOOT_P5VS4_RC CERM CERM
0402 0402
DCR(L7610) = 11.2 MOHM (TYP) / 12.5 MOHM (MAX) 1UF 1UF DCR(L7650) = 6.2 MOHM (TYP) / 6.9 MOHM (MAX) 0402 0402

CRITICAL
Q7610 C7600 1
10%
2 16V
10%
2 16V
1 2 3
CRITICAL
FDMS3602S X5R X5R 1
R7656 1 C7656
L7610 POWER56 1UF 402 402 L7650
1 10% 0 0.1UF
2.2UH-10A-12.5MOHM 16V 10% 2.2UH+/-20%-0.0069OHM-16A
X5R 2 5% 25V
1 2 (reg_phase_p3v3s5) 7 402 1/10W 2 X6S (reg_phase_p5vs4) 1 2
70 OUT PP3V3_S5_REG PHASE MF-LF 0402
PP5V_S4_REG OUT 70
PAB0705AR-SM 2 603 PIC1005H-SM

4
CRITICAL CRITICAL NOSTUFF NOSTUFF CRITICAL CRITICAL

VCC1

VCC2
1
C7622 C7621 1 C7620 1 C7618 C7617 1 1 C7616 6
1 C7657 C7658
1
C7660 1
C7661 1 C7662
10UF 150UF 150UF 0.01UF R7618 0.001UF 0.1UF 18 LDO5 VIN 17 0.001UF R7658 27.0NF 330UF 330UF 10UF
20% 20% 20% 15.8K 10% 10% 10% 9.76K 20% 20% 20%
6.3V 2 1 2 50V 2 25V 2 50V 1 2 2 6.3V
X5R
6.3V 2
POLY
6.3V 2
POLY
1 2
CERM 2 X6S U7600 FCCM 3 REG_U7600_FCCM 65
CRITICAL 5 X7R-CERM
1 2 2 6.3V
POLY-TANT
2 6.3V
POLY-TANT X5R
603 B1A-SM-1 B1A-SM-1
10%
1%
1/16W
402 0402
5 4 3 ISL62383CRTZ Q7655 0402 1%
1/16W 10%
CASE-D3L-SM CASE-D3L-SM 603
16V
X7R-CERM
MF-LF 65 REG_P3V3S5_PGOOD 7 PGOOD1 QFN PGOOD2 1 REG_P5VS4_PGOOD 65 FDMC0223S D MF-LF 10V
X5R
402 REG_BOOT_P3V3S5_RC 84 MLP3.3X3.3 REG_SNUBBER_P5VS4 84 402
0402 402
84 REG_SNUBBER_P3V3S5 84 REG_UGATE_P3V3S5 14 UGATE1 UGATE2 22 84 REG_UGATE_P5VS4 4 G
NOSTUFF
NOSTUFF 1 REG_BOOT_P3V3S5 15 BOOT1 CRITICAL BOOT2 21 REG_BOOT_P5VS4 1
OMIT R7616 84 84
R7657 OMIT
1 0 0.499
L7610.1:6MM 2 1
R7619 R7617 5% 84 REG_PHASE_P3V3S5 13 PHASE1 PHASE2 23 84 REG_PHASE_P5VS4
S
1% R76591 2 L7650.2:3MM
0.499 1/10W 1/10W
XW7610 15.8K 1% MF-LF
16 LGATE1 MF 9.76K XW7650
SM 1% 1/10W 2 603
84 REG_LGATE_P3V3S5 LGATE2 20 84 REG_LGATE_P5VS4 1 2 3 2 603 1% SM
1/16W MF 1/16W
MF-LF 603 2 MF-LF
1 2 402
84 REG_P3V3S5_ISEN 10 ISEN1 ISEN2 26 84 REG_P5VS4_ISEN 402 2 1

84 REG_P3V3S5_OCSET 11 OCSET1 OCSET2 25 84 REG_P5VS4_OCSET

(reg_p3v3s4_isen) (reg_p5vs4_isen)
84 REG_P3V3S5_VOUT 9 VOUT1 VOUT2 27 84 REG_P5VS4_VOUT
(reg_p3v3s4_ocset) (reg_p5vs4_ocset)
84 REG_P3V3S5_FB 8 FB1 FB2 28 84 REG_P5VS4_FB
(reg_p3v3s4_vout) (reg_p5vs4_vout)

B <Ra>
84 REG_P3V3S5_FSET 6 FSET1 FSET2 2 84 REG_P5VS4_FSET
<Ra> B
R76301 R76321 12 EN1 EN2 24 1
R7672 1
R7670
45.3K 976 THRM
976 75K
1% 1% PAD PGND NOSTUFF 1% 1%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF 1 C7633 1
R7633 1 C7673 1
R7673 1 C7675 MF-LF MF-LF

19
402 2 402 2 0.01UF 0.01UF 0.001UF 2 402 2 402
10% 16.5K 10% 16.5K 10%
16V 1% 16V 1% 50V
REG_P3V3S5_VOUT_R 84 2 X7R-CERM 1/16W 2 X7R-CERM 1/16W 2 X7R-CERM 84 REG_P5VS4_VOUT_R
<Rb> 0402 MF-LF 0402 MF-LF 0402 <Rb>
2 402 2 402
R76311 C7632 1 1 C7672 1
R7671
10.0K 1000PF 1000PF 10K
0.5% 5% 5% 1%
1/16W 25V 2 25V
MF CERM 2 CERM 1/16W
MF-LF
0402 0402
402 2 2 402

Vout = 0.6 * (1 + Ra / Rb) Vout = 0.6 * (1 + Ra / Rb)

68 IN PM_EN_REG_P3V3_S5
NOSTUFF
R7600 68 IN PM_EN_REG_P5V_S4
1K
NOSTUFF 2 1 REG_U7600_FCCM 65

5%
Q7600 1/16W
SSM6L36FE MF-LF
402
SOT563 D 3 REG_U7600_FCCM_R 70 65 =PP3V3_S5_VRD
P-CH
=PP5V_S5_PWRCTL 65 67 70
1
NOSTUFF R7680
This circuit toggles the Vreg 20K
between PWM and ultrasonic DCM R76011 5%
10K 1/16W
modes based on load requirements 65 BURSTMODE_EN 5 G 5% MF-LF
1/16W 2 402
A 70 67 65 =PP5V_S5_PWRCTL 4 S
MF-LF
402 2 65 REG_P5VS4_PGOOD PM_PGOOD_REG_P5V_S4
MAKE_BASE=TRUE OUT 68 SYNC_MASTER=J16_ROSSANA SYNC_DATE=03/04/2013 A
D 6 PAGE TITLE
65 BURSTMODE_EN
BURSTMODE_EN_L Vreg Mode 70 65 =PP3V3_S5_VRD
VReg 3.3V S5/5V S4
DRAWING NUMBER SIZE
0 PWM 1
R7640 Apple Inc. 051-0164 D
1 DCM 2 G 20K REVISION
60 45 IN BURSTMODE_EN_L 5% R
1/16W
MF-LF
12.4.0
1 S 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
N-CH THE INFORMATION CONTAINED HEREIN IS THE
65 REG_P3V3S5_PGOOD PM_PGOOD_REG_P3V3_S5 OUT 69 PROPRIETARY PROPERTY OF APPLE INC.
MAKE_BASE=TRUE THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
76 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 65 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_HEAD

TABLE_5_ITEM

OMIT_TABLE CRITICAL PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
152S1668 1 IND,PWR,33UH,20%,10A,35MOHM L8100 CRITICAL PART NUMBER

OMIT/table L8100 due to late sourcing change, did not want footprint change
CRITICAL D8100
POWERDI5-TO277A
TABLE_ALT_ITEM

Add 152s1668 (Cyntec) directly for next program L8100 1

371S0648 371S0694 D8100 BLC Switch Diode ACOUSTICS E-NOISE COMPONENTS
BKLT_BOOST
33UH-20%-10A-0.0351OHM 66 86
86 66 PP12V_S0_BKLT_PWR
1 2 86 BKLT_PHASE 3
IHLP6767GZ-IHLP4040DZ11-SM
CRITICAL K NOSTUFF NOSTUFF 2 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C8100 1 C8101 1 C8102 1 C8103 1 C8104 1 C8105 1 C8106 1 C8107 1 C8108 1 C8109 1 C8110 1 C8111 1 C8112 1 C8113 1 C8114 1 C8115 1 C8116 1 C8117 1 C8118 1 C8119 1 C8197 1 C8190
D8101
SOD-323 10UF 10UF 10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF PDS5100H 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
SBR130S3 25V
2 X6S
25V
2 X6S
25V
2 X6S
25V
2 X6S
25V
2 X6S
25V
2 X6S
25V
2 X6S
25V
2 X6S
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
100V
2 X7R
A 0805 0805 0805 0805 0402 0402 0402 0402 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
PGND_BKLT 66 86

D NOSTUFF PGND_BKLT 66 86
D
1
R8109
4.7
86 66 PP12V_S0_BKLT_PWR 86 66 PP12V_S0_BKLT_PWR_R 5% 86 66 BKLT_BOOST
1/4W
MF-LF CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C8151 1 C8152 1 C8153 1 C8154 2 1206
1UF 1UF 1UF 1UF
1 C8140 1 C8141 1 C8142 1 C8143 1 C8144 1 C8145
10% 10% 10% 10% 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF
25V 25V 25V 25V 10% 10% 10% 10% 10% 10%
2 X7R 2 X7R 2 X7R 2 X7R 86 BKLT_SNUBBER 100V
2 X7R 100V
2 X7R 100V
2 X7R 100V
2 X7R 100V
2 X7R 100V
2 X7R
805 805 805 805 0603 0603 0603 0603 0603 0603
PGND_BKLT 66 86 PGND_BKLT 66 86
1 2 6 7 PGND_BKLT 66 86
XW8102
CRITICAL D CRITICAL SM
R8104 Q8100 86 BKLT_FB_XW 2 1
86
66 BKLT_BOOST
86 66 PP12V_S0_BKLT_PWR 1 0.05 2 PP12V_S0_BKLT_PWR_R 66 86
BKLT_GATE_R 5 G IRF6645PBF
1
NOSTUFF
1% 0402 1/16W MF
86 DIRECTFET-SJ C8127
0 PP5V_S0_BKLT_R S 100PF
47 IN =SMB_DP_BLC_SCL R8140 1 2 NOSTUFF
86 66
5% 1
402 5% 1/16W MF-LF 100V 1 C8121
0 86 66 PP3V3_S0_BKLT_VDDIO_R 3 4 2 C0G-CERM R8124 1 C8123 1 C8125
47 IN =SMB_DP_BLC_SDA R8141 1 2 NOSTUFF R8107 0603-1 0 5%
100PF
100PF 100PF BKLT_BOOST
402 5% 1/16W MF-LF 0 86 66
1 2 86 BKLT_SW_R 5%
1/10W
100V
2 C0G-CERM 5% 5%
MF-LF 0603 2 100V
C0G-CERM 2 100V
C0G-CERM CRITICAL CRITICAL CRITICAL CRITICAL
1 5%
R8100 1 0 R8106 1/10W 2 603 0603 0603 1 C8191 1 C8192 1 C8193 1 C8194
47 IN =I2C_BKLT_SCL 2 BKLT_SCL 66 86 MF-LF 1CRITICAL 2.2UF 2.2UF 2.2UF 2.2UF
402 5% 1/16W MF-LF 0 R8108

23
603 1 C8120 1 C8122 10% 10% 10% 10%
0

8
R8101 1 5% 0.05 1 C8124 100V 100V 100V 100V
47 IN =I2C_BKLT_SDA 2 BKLT_SDA 66 86 1/8W NOSTUFF 100PF 100PF 2 X7R 2 X7R 2 X7R 2 X7R
402 5% 1/16W MF-LF MF-LF 1 C8126
1%
1W
86 BKLT_FB_R 5% 5% 100PF 1206 1206 1206 1206
VDDIO VLDO VIN 805 2 100V 100V 5% PGND_BKLT66
1000PF MF 2 C0G-CERM 2 C0G-CERM 100V 86
OMIT_TABLE 5% 2 2512 0603 0603 2 C0G-CERM
XW8103 U8100 50V
2 C0G-CERM 1
R8110 0603
SM LLP 603 XW8101 86 66 BKLT_ISEN1
1M

LP8561B0SQ
86 66 LGND_BKLT 2 1 SM NOSTUFF NOSTUFF
7 SD 6 86 1% CRITICAL CRITICAL CRITICAL CRITICAL
66 BKLT_SHUTDOWN GD 86 BKLT_GATE 86 66 BKLT_SW_N 2 1 66 PGND_BKLT 1/16W 1 C8195 1 C8196 1 C8198 1 C8199
MF-LF 86 66 BKLT_ISEN2
XW8104 24 86 BKLT_SW_P 2 402 2.2UF 2.2UF 2.2UF 2.2UF
SM 3 ISET ISENSE 10% 10% 10% 10%
BKLT_ISET
C 86 66 PGND_BKLT 2 1
86

FB 21 86 BKLT_FB
1

5%
C8160
33PF
86 66 BKLT_ISEN3
100V
2 X7R
1206
100V
2 X7R
1206
100V
2 X7R
1206
100V
2 X7R
1206
PGND_BKLT66
C
XW8105 86 BKLT_FLT 20 FILTER 12 100V 86
SM OUT1 BKLT_ISEN1 66 86
1
2 C0G-CERM 86 66 BKLT_ISEN4
R8111 0603 TABLE_ALT_HEAD

86 66 DGND_BKLT 2 1 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
66 BKLT_VSYNC_R 19 VSYNC OUT2 13 BKLT_ISEN2 66 86 330K PART NUMBER
1% 86 66 BKLT_ISEN5
1/8W TABLE_ALT_ITEM

86 66 BKLT_SCL 10 SCLK OUT3 14 BKLT_ISEN3 66 86 MF 138S0810 138S0745 2.2UF_CAP BLC OUTPUT CAPS
2 0402 86 66 BKLT_ISEN6 TABLE_ALT_ITEM

BKLT_SDA 11 SDA OUT4 16 BKLT_ISEN4

86 66 66 86
86 66 PGND_BKLT 138S0839 138S0745 2.2UF_CAP BLC OUTPUT CAPS
TABLE_ALT_ITEM

LVDS_BKLT_PWM_RC 2 PWM OUT5 17 BKLT_ISEN5 66 86 371S0748 371S0731 D8101 INPUT DIODE

66 40 BKLT_EN 4 EN OUT6 18 BKLT_ISEN6 66 86

IN
1 ISENSE_GND

NOSTUFF 1 1
C8128 1 R8123 R8105 CRITICAL
10K 12.4K
5 GND_GD

33PF
9 GND_S

15 GND_L

5%
1% 1%
50V 1/16W 1/16W
CERM 2 MF-LF MF-LF THRM
402 2 402 2 402 PAD
86 66 DGND_BKLT
25

86 66 BKLT_SW_N
86 66 LGND_BKLT
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
86 66 PGND_BKLT
DGND_BKLT
Q8105 Q8106 Q8107 Q8108 Q8109 Q8110
1
86 66 SI3440DVT1GE3 BKLT_ISEN1_R SI3440DVT1GE3 BKLT_ISEN2_R SI3440DVT1GE3 BKLT_ISEN3_R SI3440DVT1GE3 BKLT_ISEN4_R SI3440DVT1GE3 BKLT_ISEN5_R SI3440DVT1GE3 BKLT_ISEN6_R 66 86
R8103 TSOP 1 TSOP 1 TSOP 1 TSOP 1 TSOP 1 TSOP 1
270K 2 2 2 2 2 2
5%
1/16W 5 5 5 5 5 5
MF-LF
2 402 86 66 PP12V_S0_BKLT_PWR 3 6 3 6 3 6 3 6 3 6 3 6

B 86
BKLT_FLT_RC
R8150 1 86 66 BKLT_ISEN1 4 86 66 BKLT_ISEN2 4 86 66 BKLT_ISEN3 4 86 66 BKLT_ISEN4 4 86 66 BKLT_ISEN5 4 86 66 BKLT_ISEN6 4 B
1 1 C8130 100K
C8129 1%
4700PF 330PF 1/10W
5% 10% MF-LF
50V 50V 603 2 TABLE_ALT_HEAD

2 CERM 2 X7R-CERM PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
603 0402 PART NUMBER
86 66 PGND_BKLT TABLE_ALT_ITEM

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

CRITICAL
R8152 DGND_BKLT 66 86 FB8100 376S1071 376S1073 ALL Short Protection FET PART NUMBER
0 600-OHM-25%-0.5A-0.40OHM
TABLE_ALT_ITEM TABLE_ALT_ITEM

40 BKLT_VSYNC 1 2 BKLT_VSYNC_R 66 155S0831 155S0797 ALL FB8100 to FB8107 376S1121 376S1116 Q8102 BLC Inrush FET
402 5% 1/16W MF-LF
86 66 BKLT_ISEN6_R 1 2 TABLE_ALT_ITEM

740S0145 740S0146 F8100 BLC Fuse

0603
NOSTUFF FB8101 CRITICAL
1
R8153 600-OHM-25%-0.5A-0.40OHM
CRITICAL
Q8102 CRITICAL
10K CRITICAL AON6407_001
BKLT_ISEN5_R 1 2 CRITICAL FB8108 DFN5X6
1% 86 66
J8100 F8100 SYM-VER-2
R8130
1/16W
MF-LF FB8102 CRITICAL
0603
504050-1091 6AMP-32V R8112 FERR-600-OHM-3A
1 2 402 600-OHM-25%-0.5A-0.40OHM
F-RT-SM
=PP12V_S0_BKLT 1 2 86 PP12V_BKLT_SNS 10.0052 PP12V_BKLT_FUSED 1 86 2 PP12V_S0_BKLT_FILT 3 S PP12V_S0_BKLT_PWR 66 86
70 =PP5V_S0_BKLT 1 2 11 70

1% 1206 2 D 5
5% GND 86 66 BKLT_ISEN4_R 1 2
0603-1 1/4W
1/16W PP5V_S0_BKLT_R MF 1
MF-LF 86 66 0603 1 NOSTUFF
CRITICAL 1206
402 FB8103 LED_RETURN_6 2 1 1
R8121
600-OHM-25%-0.5A-0.40OHM 86 C8171 G NOSTUFF
C8131 1 C8132 1 C8133 1 0.1UF 71.5K
1 2
86 LED_RETURN_5 3
10% 1% 4 1 C8137
1UF 0.01UF 0.1UF 86 LED_RETURN_4 4 25V 1/16W
10% 10% 10% 0603 2 X6S MF-LF 100PF
25V 2 16V 16V NOSTUFF 5%
X7R X7R-CERM 2 X7R-CERM 2 FB8104 86 BKLT_BOOST_1 5 0402 2 402
0603 0402 0402 86 66 BKLT_BOOST600-OHM-25%-0.5A-0.40OHM R8120 2 50V
CERM
86 BKLT_BOOST_2 6 0402
DGND_BKLT 66 86 CRITICAL
1 2 86 LED_RETURN_3 7 NOSTUFF BKLT_EN_L 1 147K 2 BKLT_EN_DIV
0603 86 LED_RETURN_2 8 Q8101 1%
CRITICAL FB8105 SSM3K15AMFVAPE D 3 1/16W
MF-LF
86 LED_RETURN_1 9 1
600-OHM-25%-0.5A-0.40OHM VESM 402
R8122
R8131
A
70 =PP3V3_S0_BKLT_VDDIO 1
1 2
86 66 BKLT_ISEN3_R 1
0603
2
86 66 PGND_BKLT
10
0
5%
1/16W
SYNC_MASTER=J16_LINDA SYNC_DATE=01/22/2013 A
CRITICAL FB8106 12 MF-LF PAGE TITLE
5% PP3V3_S0_BKLT_VDDIO_R
1/16W
MF-LF
402
86 66
600-OHM-25%-0.5A-0.40OHM 1 G S 2 2 402 LCD Backlight Driver (LP8561)
86 66 BKLT_ISEN2_R 1 2
BKLT_EN BKLT_SHUTDOWN DRAWING NUMBER SIZE
C8134 1 C8135 1 C8136 1
CRITICAL FB8107
0603
66 40 IN 66

Apple Inc. 051-0164 D

1UF 0.01UF 0.1UF REVISION
10% 10% 10% 600-OHM-25%-0.5A-0.40OHM R
25V
X7R 2
16V
X7R-CERM 2
16V
X7R-CERM 2 12.4.0
0603 0402 0402 86 66 BKLT_ISEN1_R 1 2
NOTICE OF PROPRIETARY PROPERTY: BRANCH
DGND_BKLT 66 86 0603
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
81 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 66 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

3.3V S4 FET 3.3V S0 FET 3V3 S0 SSD 5V S0 FET

70 69 68 67 =PP3V3_S5_PWRCTL 70 =PP5V_S4_PWRCTL
70 65 =PP5V_S5_PWRCTL
SSD:Y
D 1 C8400
1 C8410
0.1UF
1 C8420
0.1UF
D
0.1UF 10% 10%
10% 16V 16V
2 X7R-CERM 2 X7R-CERM
2 16V
X7R-CERM 0402 0402
0402

1
VDD VDD
U8410 U8420

4
CRITICAL
5_VDD SLG5AP304V SLG5AP304V
TDFN TDFN
P3V3_S0_SSD_FET_RAMP 7 CAP D 3 =PP3V3_S5_FET_P3V3_S0 P5V_S0_FET_RAMP 7 CAP D 3 =PP5V_S4_FET_P5V_S0
U8400 CRITICAL 67 70
CRITICAL 70

SLG5AP439 68 67 IN PM_EN_FET_P3V3_S0 2 ON SSD:Y S 5 PP3V3_S0_SSD_FET OUT 70 67 IN PM_EN_FET_P5V_S0 2 ON S 5 PP5V_S0_FET OUT 67 70

TDFN 68
PM_EN_FET_P3V3_S4 3 ON_MOS1 ON_MOS2 5 PM_EN_FET_P3V3_S0 SSD:Y
68 IN IN 67 68 GND GND
12 CAP_MOS2 10
C8411 1 C8421 1

8
FET_RAMP_P3V3_S4 CAP_MOS1 FET_RAMP_P3V3_S0 0.0047UF 0.0047UF
10% 10%
70 OUT PP3V3_S4_FET 13 MOS1_S MOS2_S 8 PP3V3_S0_FET OUT 67 70
25V
CERM 2 4nF corresponds to
25V
CERM 2 4nF corresponds to
70 =PP3V3_S5_FET_P3V3_S4 1 MOS1_D MOS2_D 6 =PP3V3_S5_FET_P3V3_S0 67 70
0402
2.2V / ms ramp rate
0402 2.2V / ms ramp rate
IN IN
THRM 1 C8402
C8401 1 GND PAD
0.0047UF 0.0022UF
10%

15
10% 50V
25V 2 CERM
CERM 2 402
0402

C 5V HDD FET C
5V / 3V3 S0 PGOODs 70 67 =PP5V_S0_FET_P5V_HDD
1 C8460
0.1UF
10%
70 69 68 67 =PP3V3_S5_PWRCTL 2 16V
X7R-CERM
0402
1 C8440

1
0.1UF
10%
16V VDD
2 X7R-CERM
CRITICAL 8 0402 U8460
VCC SLG5AP304V
U8440
SOT833 P5V_S0_HDD_FET_RAMP 7 CAP
TDFN
D 3 =PP5V_S0_FET_P5V_HDD 67 70
CRITICAL
08

74LVC2G08GT
PM_EN_FET_P5V_S0 1 7 PM_PGOOD_FET_P5V_S0 OUT HDD_PWR_EN 2 ON S 5
68 67 IN
2
A1 Y1 68 18 14 IN
70 67 PP5V_S0_FET
5
B1 3
GND
68 67 PM_EN_FET_P3V3_S0 PM_PGOOD_FET_P3V3_S0 OUT 68
C8461 1
IN A2 Y2

8
70 67 PP3V3_S0_FET 6 0.0047UF
B2 10%
25V
GND CERM 2
0402
4
PP5V_S0_HDD_FET OUT 70

B B

VDDQ S0 FET 12V S0 FET CRITICAL

70 68 =PP12V_S5_PWRCTL Q8450
CRITICAL
1
649135PBF
Q8430 C8430 DIRECTFET_S3C
649135PBF 0.1UF
10%
DIRECTFET_S3C 2 16V
X7R-CERM
7
0402 8 6
7 70 =PP12V_G3H_FET_P12V_S0
2 5

D
PP12V_S0_FET

S
8 6 3 OUT 70
1
2 5

G
D

=PPVDDQ_S3_FET_VDDQ_S0 PPVDDQ_S0_FET
S

70 3 OUT 70
1

4
G

P12V_S0_FET_GATE_R
70 =PP3V3_S0_PWRCTL 1 C8450
4

0.1UF 1 C8451
1

10%
16V 0.022UF

1
1 VCC 2 X7R-CERM X7R
R8430 0402 VCC
2 10%
5%
22K U8430 U8450 1
R8453
50V
0402
1/16W SLG5AP004 =PP3V3_S4_PWRCTL
A MF-LF
2 402 5D DFN
ON 2 PM_EN_FET_P1V35_S0 IN 68
68 PM_EN_FET_P12V_S0
Input: 2.4V to 5.5V 2
ON
SLG5AP036
TDFN
D 5 5%
1/16W
0
R84521
63 70

SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
IN PAGE TITLE
7G MF-LF 47K
S6
P1V5_S0_FET_GATE

PM_PGOOD_FET_P1V35_S0 8 PG
CRITICAL
1
R8451 NC
3 NC CRITICAL G 7 P12V_S0_FET_GATE 2 402 5%
1/16W FET-Controlled S0 and S4
71 68 OUT NC 3 NC 6
MF-LF
402 2 DRAWING NUMBER SIZE
100K S
THRM
5%
1/16W Apple Inc. 051-0164 D
PAD GND MF-LF PG 8 PM_PGOOD_FET_P12V_S0 OUT 68 REVISION
9

2 402 THRM
R
12.4.0
GND PAD
NOTICE OF PROPRIETARY PROPERTY:
4

BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
84 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 67 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
S5 Enable S0 Enables
70 67 =PP12V_S5_PWRCTL
70 69 68 67 =PP3V3_S5_PWRCTL
1
R8590
68K
5% 14 74LVC08
1/16W 10 TSSOP-HF
MF-LF 69 45 44 36 21 12 IN PM_SLP_S3_L
2 402 8 PM_EN_FET_P12V_S0
U8500 OUT 67

D
60 PM_PGOOD_FET_P12V_S5 PM_EN_REG_P3V3_S5 OUT
MAKE_BASE=TRUE
65 63 IN PM_PGOOD_REG_VDDQ_S3 9 08

7
D
1
R8591
33K
5%
1/16W
MF-LF 70 69 68 67 =PP3V3_S5_PWRCTL
2 402

R85021
33K
5%
1/16W

S4 Enables MF-LF

PU_U8500
402 2

13
14 74LVC08
TSSOP-HF R8530
70 69 68 67 =PP3V3_S5_PWRCTL 11
100
U8500 PM_EN_S0_R 1 2 PM_EN_FET_P5V_S0 OUT 67
12 MAKE_BASE=TRUE
67 IN PM_PGOOD_FET_P12V_S0 08 5%
1/16W =TBT_S0_EN OUT 29 30
1 C8500 MF-LF
7 402
0.1UF NOSTUFF
Note: 10%
16V C8501 1
2 X7R-CERM
Halt power sequencing at S5 0402 0.47UF
10%
if there is no processor. 6.3V
CERM-X5R 2
Remove Q8500 to circumvent 402
PLACE_SIDE=BOTTOM
or short gate to source.
14 74LVC08
44 32 12 IN PM_SLP_S5_L 1 TSSOP-HF R8531
3
0
PM_EN_S4 PM_PGOOD_FET_P5V_S0 1 2 PM_EN_FET_P3V3_S0
U8500 67 IN OUT 67

70 69 68 67 =PP3V3_S5_PWRCTL 2 08 5%
1/16W
1 1 MF-LF
J17 7 R8510 R8511 402
R85001 R85011 5%
33
5%
33

C 100K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
1/16W
MF-LF
2 402
1/16W
MF-LF
2 402
NOSTUFF
R8534 C
0
402 2 402 2 1 2 PM_EN_REG_CPUVCC_S0 61 68
PM_EN_REG_P5V_S4 65 OUT
CPU_SKTOCC OUT
5% NOSTUFF
1/16W 1
J17
PM_EN_FET_P3V3_S4 OUT 67 MF-LF C8522
402 0.47UF
D 3 PLACE_SIDE=BOTTOM 10%
NOSTUFF NOSTUFF 6.3V
Q8500 1 C8510 1 C8511 21 IN MEMVTT_EN PM_EN_LDO_DDRVTT_S0 OUT 63
2 CERM-X5R
402
SSM3K15AMFVAPE 0.47UF 0.47UF MAKE_BASE=TRUE
10% 10%
VESM

1 G S 2
6.3V
2 CERM-X5R
402
6.3V
2 CERM-X5R
402
S0 GPU SEQUENCING(J17 ONLY)
J17
71 IN CPU_SKTOCC_L
R8537
0
68 67 IN PM_PGOOD_FET_P3V3_S0 1 2 PM_EN_REG_GPUCORE_S0 OUT 72
tau (RC delay, ms): 0.0 0.0
5%
1/16W
MF-LF
402
R8538
0
PM_PGOOD_REG_GPUCORE_S0 PM_EN_REG_GPU_VDDQ_S0
S4 USB Enable 72 IN 1
5%
1/16W
MF-LF
2 OUT 72

402

R8520 J17
0
68 65 PM_PGOOD_REG_P5V_S4 1 2 PM_EN_USB_PWR 42 43
IN
5%
1/16W
OUT
S0 PCH Sequencing
MF-LF NOSTUFF OMIT_TABLE
402 R8533
1 C8520 1.5K TABLE_5_HEAD

0.47UF 68 67 IN PM_PGOOD_FET_P3V3_S0 1 2 PM_EN_FET_REG_P1V5_S0 OUT 64 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
10%

B 6.3V
2 CERM-X5R
402
5%
1/16W
MF-LF
402
1
J16
C8524
116S0070 1 RES,1.5K,0402,5% R8533 J16
TABLE_5_ITEM

TABLE_5_ITEM
B
1UF 116S0004 1 RES,0OHM,0402,5% R8533 J17
10%
10V
2 X6S-CERM
0402
Rail definitions
J16
R8513 Platform: All processor non-Core and non-Graphics (5 V, 3.3 V, 1.5 V, 1.05V for PCH/TBT/GPU)
S4 TBT S4 Port Enable 1
0
5%
2 PM_EN_FET_P1V35_S0 OUT 67 Uncore: VDDQ

1/16W
MF-LF
70 30 29 28 27 26 IN =PP3V3_S4_TBT =TBTAPWRSW_EN OUT 29
402 Notes on sequencing requirements
=TBTBPWRSW_EN 30
Intel:
OUT
1. No hard specification on platform rails
J16 R8514
0 2. SMC guarantees timing on PCH DPWROK and PWROK
67
PM_PGOOD_FET_P1V35_S0 1 2
71
IN 3. VCC3_3 may power up before VCC, VCC must ramp to 0.6V within 25ms of VCC3V3 ramping to 2.6V
5%
PM_PGOOD_REG_GPU_P1V35_S0
1/16W 4. VCC1_5 may power up before VCC, VCC must ramp to 0.6V within 25ms of VCC1V5 ramping to 1.35V
MF-LF
402 5. VCC may power down before VCC3_3, VCC3_3 must ramp down to 2.6V within 35ms
J17 R8515 6. VCC may power down before VCC1_5, VCC1_5 must ramp down to 1.35V within 35ms
0 CKPLUS_WAIVE=UNCONNECTED_PINS NVIDIA:
PM_PGOOD_REG_GPU_VDDQ_S0 1 2

S3 VDDQ Enable 72 IN
5%
1/16W
MF-LF
402
10
14 74LVC08
TSSOP-HF
1. 3V3_S0 must ramp first
4. VDDQ MUST RAMP AFTER GPU_CORE
5. PEX_VDD with IFPC/D/E/F_IOVDD (1.05V) must ramp after VDDQ
9
U8600 8 PM_EN_REG_P1V05_S0_R OUT 68
6. All rails must reach their target voltages in more than 40 uS
64 IN PM_PGOOD_FET_REG_P1V5_S0 08
70 69 68 67 =PP3V3_S5_PWRCTL
7
CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC08
A 44 12 IN PM_SLP_S4_L 4
14
TSSOP-HF R8536
0
SYNC_MASTER=J16_AARON SYNC_DATE=02/21/2013 A
6 PM_EN_REG_VDDQ_S3 PM_EN_REG_P1V05_S0_R 1 2 PM_EN_REG_P1V05_S0 PAGE TITLE
U8500 OUT 63 68 IN 64
68 65 IN PM_PGOOD_REG_P5V_S4 5 08 5%
1/16W
OUT
PM Regulator Enables
7 MF-LF NOSTUFF DRAWING NUMBER SIZE
402
1 C8523 Apple Inc. 051-0164 D
0.47UF REVISION
10% R
2 6.3V
CERM-X5R
12.4.0
402 NOTICE OF PROPRIETARY PROPERTY: BRANCH

R8535 THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
0 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PM_PGOOD_REG_P1V05_S0 1 2 PM_EN_REG_CPUVCC_S0
69 64 IN
5%
OUT 61 68
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
85 OF 123
1/16W SHEET
MF-LF III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
402 IV ALL RIGHTS RESERVED 68 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ALL_SYS_PWRGD,PCH_PWROK & SYS_PWROK Generation

PCH Power Goods Resume Reset
Intel Doc# 29517 Maho Bay PDG, Section 22.13
Intel Doc# 29562 Panther Point EDS, Section 8.7 and 8.8

Note:
To PCH The iMac J16/J17 designs does not support Deep Sx modes so both DPWROK and
PM_PCH_APWROK OUT 12 RSMRST# signals are shorted together
D 70 69 68 67 =PP3V3_S5_PWRCTL
BYPASS=U8601:5MM Second Requirements:
D
1
C8605 Power on:
0.1UF Asserted at least 10 ms after all suspend well power is valid
20%
10V
2 CERM
To PCH Power off or loss of AC:
402 PM_PCH_PWROK OUT 12 18 20 39 Transition to 0.8V or less before VccSUS3_3 drops to 2.90 V
=PP3V3_S5_PWRCTL 67 68 69 70 MAKE_BASE=TRUE
Second to allow PCH to switch suspend well to battery without excessive loading
74LVC1G08GW
SOT353 NO STUFF
1
PM_PGOOD_REG_P1V05_S0 1
5 R8624 1 C8621
68 64 IN B 10K 0.1UF
4 5% 10%
2
U8601Y 1/16W
MF-LF 2 16V
X7R-CERM
PM_SLP_S3_L

PM_PGOOD_SLP_S3_P1V05_S0
68 45 44 36 21 12 IN A 0402
2 402
PLACE_SIDE=BOTTOM 3 BYPASS=U8600:5MM Method:
1
C8620 The SMC guarantees proper assertion and de-assertion of RSMRST# for
0.1UF NO STUFF normal operation via PM_DSW_PWRGD.
20% 1 1
2
10V
CERM
R8621 R8622 RSMRST# is asserted when power good from regulator is de-asserted in the
402 0 0
5% 5% event AC is lost. Power good de-assertion should happen quickly enough
1/16W 1/16W
MF-LF MF-LF to meet Intel spec.
402 2 2 402 CKPLUS_WAIVE=UNCONNECTED_PINS
14 74LVC08
4 TSSOP-HF 74LVC08
14
6 PM_PGOOD_ALL 13 TSSOP-HF R8625 To PCH
U8600 1K
PM_PGOOD_REG_CPUVCC_S0 5 08 11 PM_PCH_SYS_PWROK_R 1 2 PM_PCH_SYS_PWROK To SMC
61 IN U8600 OUT 12 18 45

PLACE_SIDE=BOTTOM 12 08 PLACE_NEAR=U1100.W31:7MM 5% 69 65 PM_PGOOD_REG_P3V3_S5 S5_PWRGD 44

7 Third IN OUT
1/20W MAKE_BASE=TRUE
MF
BYPASS=U8600:5MM 7 201
CKPLUS_WAIVE=UNCONNECTED_PINS
1
C8622
2.2UF
C 2
10%
6.3V
X5R
Delay=10ms From SMC
CKPLUS_WAIVE=UNCONNECTED_PINS
C
402
14 74LVC08
45 44 IN PM_DSW_PWRGD 1 TSSOP-HF R8635 To PCH
3
0
PM_RSMRST_PCH_L_R 1 2 PM_RSMRST_PCH_L
2
U8600 OUT 12 18

69 65 IN PM_PGOOD_REG_P3V3_S5 08 5%
1/16W
MF-LF
7 402
CKPLUS_WAIVE=UNCONNECTED_PINS

44 21 3 OUT ALL_SYS_PWRGD
MAKE_BASE=TRUE
To SMC, for 99ms delay
ALL_SYS_PWRGD must remain low for
5ms minimum after all rails are valid

45 44 28 IN
SMC_DELAYED_PWRGD

B B

A SYNC_MASTER=J16_AARON SYNC_DATE=02/21/2013 A
PAGE TITLE

PM Power Good
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

Always on: Keeps the PCH RTC alive Enabled when system is in run
82 PPVDDQ_S0_CPU PPVDDQ_S0_SNS 49
MAKE_BASE=TRUE
84 PP3V3_G3 PP3V3_G3_RTC 19 84 PP12V_S0 PP12V_S0_FET 67 =PP1V5_S3_CPU_VCCDDR 6
MAKE_BASE=TRUE MAKE_BASE=TRUE
=PP12V_S0_REG_CPUVCC_S0 =PP1V5R1V35_S0_CPU 8 10
=PPVRTC_G3_PCH 11 12 15
62

=PP12V_S0_REG_P1V05_S0 64

=PP12V_S0_AUDIO_SPKRAMP 54 55
G3H Rails
84 PP12V_ACDC PP12V_G3H_ACDC 60 =PP12V_S0_BKLT 66 84 PP1V5_S0 PP1V5_S0_REG 64
MAKE_BASE=TRUE MAKE_BASE=TRUE
=PP12V_G3H_SNS_R =PP12V_S0_FAN 51
=PP1V5_S0_SENSE 34
48

D =PP12V_S0_LCD 40
=PP1V5_S0_PCH_VCCVRM
=PP1V5_S0_PCH_RCOMP
17

12 13
D
84 PP12V_G3H PP12V_G3H_SNS 48 =PP1V5_S0_PCH_SATA 11
MAKE_BASE=TRUE
=PP12V_G3H_REG_3V42_G3H 60 =PP1V5_S0_PCH_CLK 11 19

=PP12V_G3H_FET_P12V_S5 =PP1V5_S0_AUD_DIG 52
60

=PP12V_G3H_FET_P12V_S0 67
84 PP5V_S0 PP5V_S0_FET 67
MAKE_BASE=TRUE 82 PPDDRVTT_S0 PPDDRVTT_S0_LDO 63
=PP5V_S0_REG_CPUVCC_S0 61 62 MAKE_BASE=TRUE
=PPDDRVTT_S0_CLAMP 21
84 PP3V42_G3H PP3V42_G3H_REG 60 =PP5V_S0_REG_P1V05_S0 64
MAKE_BASE=TRUE =PPDDRVTT_S0_MEM_A 23
=PP3V3_G3H_BT 32 =PP5V_S0_AUDIO 52 59 =PPDDRVTT_S0_MEM_B 24

=PP3V3_G3H_SMC 44 45 51 =PP5V_S0_ISENSE 48
82 PP1V05_S0 PP1V05_S0_REG 64
=PP3V3_G3H_RTC_D =PP5V_S0_LPCPLUS MAKE_BASE=TRUE
19 46 =PP1V05_S0_P1V05TBTFET 28

=PPVIN_G3H_SMCVREF 45
=PP5V_S0_BKLT 66 =PP1V05_S0_PCH_VCC 15 17
=PP5V_S0_FET_P5V_HDD 67 =PP1V05_S0_PCH_VCCCLK_CLK100 15 17
=PP3V3_G3H_SMC_USBMUX 42
=PP1V05_S0M_PCH_VCCASW 15 17
=PP3V3_G3H_LPCPLUS 46
=PP1V05_S0_PCH_VCC_CLK 17

=PP1V05_S0_PCH_VCCIO_FDI 15 17
Ground/Common 84 PPHDD_S0 PP5V_S0_HDD_FET 67 =PP1V05_S0_PCH_VCCCLK_SSC 15 17
MAKE_BASE=TRUE
GND =PPHDD_S0_SNS_R 48
=PP1V05_S0_PCH_VCCUSBPLL 15 17
MAKE_BASE=TRUE =PP1V05_S0_PCH_VCCIO 15 17

=PP1V05_S0_PCH_VCCCLK_SSC100 15 17
PP5V_S0_HDD PPHDD_S0_SNS =PP1V05_S0_PCH_VCCCLK_CLK135 15 17
84 48
MAKE_BASE=TRUE =PP1V05_S0_PCH_VCCIO_USB2 15 17
=PP5V_S0_SATA 34
=PP1V05_S0_PCH_VCCIO_GPIO 15

=PP1V05_S0_PCH_V_PROC_IO 14 15 17

=PP1V05_S0_SNS
C S5 Rails
Enabled when system has AC and is in S5
=PP1V05_S0_SMC
48

45 C
=PP1V05_S0_XDP 18

84 PP12V_S5 PP12V_S5_FET 60
MAKE_BASE=TRUE
=PP12V_S5_REG_P3V3P5V_S5 65

=PP12V_S5_REG_VDDQ_S3 63

=PP12V_S5_PWRCTL 67 68
S4 Rails
Enabled when system has AC and is in run or sleep
=PPHV_SW_TBTAPWRSW 29 83 PPCPUVCC_S0_CPU PPCPUVCC_S0_REG 62
MAKE_BASE=TRUE
PP5V_S4 PP5V_S4_REG =PPCPUVCC_S0_CPU
=PPHV_SW_TBTBPWRSW 30
84
MAKE_BASE=TRUE
65 48 61
=PPVCC_S0_CPU
=PP12V_S5_SNS 48
=PP5V_S4_REG_VDDQ_S3 63
6 8 10

=PP5V_S4_FET_P5V_S0 67 84 PP3V3_S0 PP3V3_S0_FET 67

MAKE_BASE=TRUE
84 PP5V_S5 PP5V_S5_LDO 65
=PP5V_S4_MEMRESET 21 =PP3V3_S0_P3V3TBTFET 28
Thunderbolt Rails (S0)
MAKE_BASE=TRUE Enabled when Thunderbolt cable is plugged in
=PP5V_S5_PWRCTL 65 67
=PP5V_S4_PWRCTL 67 =PP3V3_S0_PWRCTL 67

=PP5V_S4_USB =PP3V3_S0_VRD 84 PP3V3_TBTLC =PP3V3_TBTLC_FET 28

42 43 60 61 64
MAKE_BASE=TRUE
=PP3V3_TBT_PCH_GPIO 20
PP3V3_S5 PP3V3_S5_REG =PP5V_S4_CAMERA 38 =PP3V3_S0_AUDIO 38 52 54 55 58
84
MAKE_BASE=TRUE
65 =PP3V3_TBTLC_RTR 26 27 28

=PP3V3_S5_FET_P3V3_S4 67
=PP3V3_S0_AUDIO_DIG 56 =PPVDDIO_TBT_CLK 19

=PP3V3_S5_FET_P3V3_S0 67
84 PP3V3_S4 PP3V3_S4_FET 67 =PP3V3_S0_DP 31 40 47
MAKE_BASE=TRUE
=PP3V3_S5_PWRCTL 67 68 69
=PP3V3_S4_FET_ENET 36 =PP3V3_S0_ENET 35
82 28 PP1V05_TBTLC =PP1V05_TBTLC_FET 28
=PP3V3_S4_PWRCTL =PP3V3_S0_FAN MAKE_BASE=TRUE
=PP3V3_S5_VRD 65
63 67 51 =PP1V05_TBTLC_RTR 27

=PP3V3_S5_LED =PP3V3_S4_ALS 38 =PP3V3_S0_INTDPMUX 41

=PP3V3_SUS_PCH_VCCSUS_GPIO 15 17
=PP3V3_S4_LED 3 =PP3V3_S0_LED 3 PP1V05_TBTCIO =PP1V05_TBTCIO_FET
82 28
MAKE_BASE=TRUE
=PP3V3_S5_PCH_VCCDSW 15 17
=PP3V3_S4_MEMRESET 21 =PP3V3_S0_LED_SATA 33 =PP1V05_TBTCIO_RTR 27

B =PP3V3_SUS_PCH_VCC_SPI 15 17
=PP3V3_S3RS4_PCH_GPIO 13 =PP3V3_S0_PCH 13 19 B
=PP3V3R1V5_S0_PCH_VCCSUSHDA 15 17
=PP3V3_S4_PM 21 =PP3V3_S0_PCH_VCC3_3_GPIO 15 17

=PP3V3_SUS_PCH_VCCSUS_USB 15 17
=PP3V3_S4_SDCARD 37 =PP3V3_S0_PCH_VCC3_3_THRM 15 17

=PP3V3_SUS_PCH_VCCSUS_RTC 15 17
=PP3V3_S4_SMC 45 =PP3V3_S0_PCH_VCCCLK3_3 15 17

=PP3V3_SUS_PCH_VCCSUS_USB3 15
=PP3V3_S4_SMBUS_SMC_2 47 =PP3V3_S0_PCH_VCC3_3_HVCMOS 15 17

=PP3V3_S5_PCH 19 20
=PP3V3_S4_TBT 26 27 28 29 30 68 =PP3V3_S0_PCH_VCC_FUSE 15 17

=PP3V3_S5_ROM 46
=PP3V3_S4_CAMERA 38 39 =PP3V3_S0_PCH_VCC3_3_USB 15 17

=PP3V3_S5_SENSE 48
=PP3V3_S4_AUDIO_DIG 56 =PP3V3_S0_RSTBUF 20

=PP3V3_S5_SMC 45
=PP3V3_S4_SNS_R 48 =PP3V3_S0_SDCARD 37

=PP3V3_S5_XDP 18
=PP3V3_S3_VREFMRGN 22 =PP3V3_S0_SENSE 34 48 49 50

=PP3V3_S4_TBTAPWRSW 29 =PP3V3_S0_SMBUS 47

=PP3V3_S4_TBTBPWRSW 30 84 PP3V3_S4_AP PP3V3_S4_SNS 48 =PP3V3_S0_SMBUS_SMC_0 47

MAKE_BASE=TRUE
=PP3V3_S5_SNS 49
=PP3V3_S4_AP 32 45 =PP3V3_S0_SMBUS_SMC_1 47

=PP3V3_SUS_PCH_GPIO 11 12 13 14 S3 Rails =PP3V3_S0_SMBUS_SMC_3 47

=PP3V3_S5_PCH_GPIO Enabled when system is in run or sleep

12 =PP3V3_S0_SMC 45

84 PP3V3_ENET PP3V3_ENET_FET 36 =PP3V3_S0_TBTPWRCTL 28

MAKE_BASE=TRUE
=PP3V3_ENET_PHY 35 36 =PP3V3_S0_BKLT_VDDIO 66

=PP3V3_ENET_SYSCLK 19 =PPSPD_S0_MEM_A 23

=PPVDDIO_ENET_CLK 19 =PPSPD_S0_MEM_B 24

=PP3V3_S0_PCH_GPIO 11 12 14 28

PPVDDQ_S3 PPVDDQ_S3_REG =PP3V3_S0_REG_P1V5_S0 64

82 63

A MAKE_BASE=TRUE
=PPVDDQ_S3_FET_VDDQ_S0 67 SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
PAGE TITLE
=PPVDDQ_S3_SNS_DDR_R 49
Power Aliases
DRAWING NUMBER SIZE
82 PPVDDQ_S3_DDR PPVDDQ_S3_SNS_DDR 49
051-0164 D
MAKE_BASE=TRUE
=PPVDDQ_S3_LDO_DDRVTT 63
Apple Inc. REVISION
R
=PPDDR_S3_MEMVREF 22
12.4.0
=PPVDDQ_S3_MEM_A PP3V3_S0_SSD PP3V3_S0_SSD_FET
NOTICE OF PROPRIETARY PROPERTY: BRANCH
23 84 67
MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE
=PPVDDQ_S3_MEM_B 24 =PPSSD_S0_SNS_R 49
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
=PPVDDQ_S3_MEMRESET 21 84 PPSSD_S0
MAKE_BASE=TRUE
PPSSD_S0_SNS 49
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
100 OF 123
=PP3V3_S0_SSD 33 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 70 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

Display Aliases

61 REG_ISENVCC_4_NR AGND_CPU 61 62 83
MAKE_BASE=TRUE 26 DP_TBTSNK0_HPD TP_DP_IG_B_HPD 12
MAKE_BASE=TRUE

85 26 DP_TBTSNK0_ML_C_P<3..0> TP_DP_IG_B_MLP<3..0> 5
MAKE_BASE=TRUE
85 26 DP_TBTSNK0_ML_C_N<3..0> TP_DP_IG_B_MLN<3..0> 5
MAKE_BASE=TRUE

85 26 DP_TBTSNK0_AUXCH_C_P TP_DP_IG_B_AUXCHP 12
MAKE_BASE=TRUE
UNUSED CPU SOCKET 85 26 DP_TBTSNK0_AUXCH_C_N TP_DP_IG_B_AUXCHN 12
MAKE_BASE=TRUE

C 68 CPU_SKTOCC_L CPU_SKTOCC_L_ALIAS
MAKE_BASE=TRUE
31

31
DP_TBTSNK0_DDC_DATA
MAKE_BASE=TRUE
DP_TBTSNK0_DDC_CLK
TP_DP_IG_B_DDC_DATA

TP_DP_IG_B_DDC_CLK
12

12
C
MAKE_BASE=TRUE

26 DP_TBTSNK1_HPD TP_DP_IG_C_HPD 12
MAKE_BASE=TRUE

85 26 DP_TBTSNK1_ML_C_P<3..0> TP_DP_IG_C_MLP<3..0> 5
MAKE_BASE=TRUE
MEMORY PGOOD 85 26 DP_TBTSNK1_ML_C_N<3..0> TP_DP_IG_C_MLN<3..0> 5
MAKE_BASE=TRUE
85 26 DP_TBTSNK1_AUXCH_C_P TP_DP_IG_C_AUXCHP 12
21 =PM_PGOOD_MEM_S0 PM_PGOOD_FET_P1V35_S0 67 68 MAKE_BASE=TRUE
MAKE_BASE=TRUE 85 26 DP_TBTSNK1_AUXCH_C_N TP_DP_IG_C_AUXCHN 12
MAKE_BASE=TRUE

31 DP_TBTSNK1_DDC_DATA TP_DP_IG_C_DDC_DATA 12
MAKE_BASE=TRUE

31 DP_TBTSNK1_DDC_CLK TP_DP_IG_C_DDC_CLK 12
MAKE_BASE=TRUE

41 DP_INT_HPD TP_DP_IG_D_HPD 12
MAKE_BASE=TRUE

85 41 DP_INT_ML_P<3..0> TP_DP_IG_D_MLP<3..0> 5
MAKE_BASE=TRUE

85 41 DP_INT_ML_N<3..0> TP_DP_IG_D_MLN<3..0> 5
MAKE_BASE=TRUE

41 DP_INT_DDC_DATA TP_DP_IG_D_DDC_DATA 12
MAKE_BASE=TRUE

41 DP_INT_DDC_CLK TP_DP_IG_D_DDC_CLK 12
MAKE_BASE=TRUE

85 41 DP_INT_AUX_P TP_DP_IG_D_AUXCHP 12
MAKE_BASE=TRUE

85 41 DP_INT_AUX_N TP_DP_IG_D_AUXCHN 12
MAKE_BASE=TRUE

B B

A SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
PAGE TITLE

Signal Aliases
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

CPU Reserved UNUSED GRAPHICS ALIASES

78 18 6 CPU_CFG<15..12> TP_CPU_CFG<15..12> 20 TP_GPU_RESET_L NC_TP_GPU_RESET_L
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE

CPU Memory
UNUSED THUNDERBOLT ALIASES
75 MEM_A_CLK_N<2..3> NC_MEM_A_CLKN<2..3> 26 TP_TBT_PCIE_RESET0_L NC_TBT_PCIE_RESET0_L
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
MEM_A_CLK_P<2..3> NC_MEM_A_CLKP<2..3> 26 TP_TBT_PCIE_RESET1_L NC_TBT_PCIE_RESET1_L
75
MAKE_BASE=TRUE NO_TEST=TRUE

D 75 MEM_A_CS_L<2..3>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_MEM_A_CS_L<2..3>
MAKE_BASE=TRUE NO_TEST=TRUE
26 TP_TBT_PCIE_RESET2_L NC_TBT_PCIE_RESET2_L
MAKE_BASE=TRUE NO_TEST=TRUE
D
26 TP_TBT_PCIE_RESET3_L NC_TBT_PCIE_RESET3_L
75 MEM_A_CKE<2..3> NC_MEM_A_CKE<2..3> MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 26 TP_TBT_THERM_DP NC_TBT_THERM_DP
MAKE_BASE=TRUE NO_TEST=TRUE
75 MEM_B_CLK_N<2..3> NC_MEM_B_CLKN<2..3>
MAKE_BASE=TRUE NO_TEST=TRUE
75 MEM_B_CLK_P<2..3> NC_MEM_B_CLKP<2..3>
MAKE_BASE=TRUE NO_TEST=TRUE UNUSED VREG ALIASES
75 MEM_B_CS_L<2..3> NC_MEM_B_CS_L<2..3> 61 REG_PWM_CPUVCC_4 NC_REG_PWM_CPUVCC_4
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
75 MEM_B_CKE<2..3> NC_MEM_B_CKE<2..3> REG_ISENVCC_4_P NC_REG_ISENVCC_4P
61
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
75 MEM_A_ODT<2..3> NC_MEM_A_ODT<2..3>
MAKE_BASE=TRUE NO_TEST=TRUE
75 MEM_B_ODT<2..3> NC_MEM_B_ODT<2..3>
MAKE_BASE=TRUE NO_TEST=TRUE
UNUSED GPU ALIASES
68 PM_EN_REG_GPUCORE_S0 NC_PM_EN_REG_GPUCORE_S0
MAKE_BASE=TRUE NO_TEST=TRUE
PCH GPIO 68 PM_PGOOD_REG_GPUCORE_S0 NC_PM_PGOOD_REG_GPUCORE_S0
MAKE_BASE=TRUE NO_TEST=TRUE
11 TP_PCH_GPIO64_CLKOUTFLEX0 NC_PCH_GPIO64_CLKOUTFLEX0 PM_EN_REG_GPU_VDDQ_S0 NC_PM_EN_REG_GPU_VDDQ_S0
68
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
11 TP_PCH_GPIO65_CLKOUTFLEX1 NC_PCH_GPIO65_CLKOUTFLEX1 PM_PGOOD_REG_GPU_VDDQ_S0 NC_PM_PGOOD_REG_GPU_VDDQ_S0
68
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
11 TP_PCH_GPIO66_CLKOUTFLEX2 NC_PCH_GPIO66_CLKOUTFLEX2
MAKE_BASE=TRUE NO_TEST=TRUE
11 TP_PCH_GPIO67_CLKOUTFLEX3 NC_PCH_GPIO67_CLKOUTFLEX3
MAKE_BASE=TRUE NO_TEST=TRUE UNUSED PEG ALIASES
5 =PEG_D2R_P<0..15> NC_PEG_D2R_P<0..15>
MAKE_BASE=TRUE NO_TEST=TRUE

UNUSED IG DISPLAY 5 =PEG_D2R_N<0..15> NC_PEG_D2R_N<0..15>

MAKE_BASE=TRUE NO_TEST=TRUE
5 =PEG_R2D_C_P<0..15> NC_PEG_R2D_C_P<0..15>
MAKE_BASE=TRUE NO_TEST=TRUE

C 5 TP_DP_IG_A_MLP<3..0>
MAKE_BASE=TRUE
NC_DP_IG_A_MLP<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE
5 =PEG_R2D_C_N<0..15> NC_PEG_R2D_C_N<0..15>
MAKE_BASE=TRUE NO_TEST=TRUE
C
5 TP_DP_IG_A_MLN<3..0> NC_DP_IG_A_MLN<3..0>
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
5 TP_DP_IG_A_AUXCHP NC_DP_IG_A_AUXCHP
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
5 TP_DP_IG_A_AUXCHN NC_DP_IG_A_AUXCHN
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE

PCH PCI
13 TP_LPC_DREQ0_L NC_LPC_DREQ0_L
MAKE_BASE=TRUE NO_TEST=TRUE

PCH Miscellaneous
11 TP_HDA_SDIN1 NC_HDA_SDIN1
MAKE_BASE=TRUE NO_TEST=TRUE
11 TP_HDA_SDIN2 NC_HDA_SDIN2
MAKE_BASE=TRUE NO_TEST=TRUE
11 TP_HDA_SDIN3 NC_HDA_SDIN3
MAKE_BASE=TRUE NO_TEST=TRUE
11 TP_PCI_CLK33M_OUT2 NC_PCI_CLK33M_OUT2
MAKE_BASE=TRUE NO_TEST=TRUE
11 TP_PCI_CLK33M_OUT3 NC_PCI_CLK33M_OUT3
MAKE_BASE=TRUE NO_TEST=TRUE

B B

A SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
PAGE TITLE

Unused Signal Aliases

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

D D

C C

B B

A SYNC_MASTER=J16_MAX SYNC_DATE=02/11/2013 A
PAGE TITLE

Functional / ICT Test

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

J16 BOARD SPECIFIC PHYSICAL AND SPACING CONSTRAINTS

TABLE_BOARD_INFO

BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO

(MIL or MM) VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM NO_TYPE,BGA MM 16.2

General Physical Rule Definitions General Spacing Definitions Board Stack-up

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP Default Finished board thickness: 1.58 mm
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD

D DEFAULT * Y 0.1 MM =50_OHM_SE 12.7 MM 0 MM 0 MM

TABLE_PHYSICAL_RULE_ITEM
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
Top Signal
Prepreg
0.5 oz (Cu plated)
0.071 mm
D
STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT DEFAULT * 0.1 MM ?
TABLE_SPACING_RULE_ITEM
2 Plane 1 oz
STANDARD * =DEFAULT ? Prepreg 0.076 mm
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

3 Signal 0.5 oz
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
Prepreg 0.435 mm
TABLE_PHYSICAL_RULE_ITEM

Fixed and Dielectric

34_OHM_SE * Y 0.215 MM 0.085 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD
4 Plane 1 oz
TABLE_PHYSICAL_RULE_ITEM

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT Core 0.127 mm

34_OHM_SE TOP,BOTTOM Y 0.215 MM 0.085 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM

5 Plane 1 oz
1:1_SPACING * 0.1 MM ?
TABLE_SPACING_RULE_ITEM
Prepreg 0.435 mm
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

1X_DIELECTRIC * 0.076 MM ? 6 Signal 0.5 oz

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM

Prepreg 0.076 mm
TABLE_PHYSICAL_RULE_ITEM

1X_DIELECTRIC TOP,BOTTOM 0.071 MM ?

39_OHM_SE * Y 0.170 MM 0.085 MM =STANDARD =STANDARD =STANDARD 2 Plane 1 oz
TABLE_PHYSICAL_RULE_ITEM

Prepreg 0.071 mm
39_OHM_SE TOP,BOTTOM Y 0.170 MM 0.085 MM =STANDARD =STANDARD =STANDARD
BGA Btm Signal 0.5 oz (Cu plated)
TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_HEAD
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM

ON LAYER? BGA_P1MM * =STANDARD ?

TABLE_PHYSICAL_RULE_ITEM

42_OHM_SE * Y 0.145 MM 0.085 MM =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

42_OHM_SE TOP,BOTTOM Y 0.145 MM 0.085 MM =STANDARD =STANDARD =STANDARD Power and Common
TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP GND * =STANDARD ?
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM

45_OHM_SE * Y 0.138 MM 0.085 MM =STANDARD =STANDARD =STANDARD GND_P2MM * =2:1_SPACING 1000

90_OHM_DIFF TOP,BOTTOM Y 0.111 MM 0.085 MM =STANDARD 0.200 MM 0.1 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF * Y 0.089 MM 0.085 MM =STANDARD 0.220 MM 0.1 MM

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF TOP,BOTTOM Y 0.089 MM 0.085 MM =STANDARD 0.220 MM 0.1 MM

A SYNC_MASTER=J16_MLB SYNC_DATE=12/03/2012 A
PAGE TITLE

J16 RULE DEFINITIONS

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

DDR3 DDR3
DDR3-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD
Electrical Contraint Set Physical Spacing
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? Channel A
TABLE_PHYSICAL_RULE_ITEM

DDR_34S * =34_OHM_SE =34_OHM_SE =34_OHM_SE =34_OHM_SE =STANDARD =STANDARD I178 DDR_A_CLK0 DDR_CLK_PHY DDR_CLK MEM_A_CLK_P<1..0> 7 23
TABLE_PHYSICAL_RULE_ITEM

I179 DDR_A_CLK0 DDR_CLK_PHY DDR_CLK MEM_A_CLK_N<1..0> 7 23

DDR_39S * =39_OHM_SE =39_OHM_SE =39_OHM_SE =39_OHM_SE =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM
I255 DDR_A_CLK1 DDR_CLK_PHY DDR_CLK MEM_A_CLK_P<3..2> 72

DDR_42S * =42_OHM_SE =42_OHM_SE =42_OHM_SE =42_OHM_SE =STANDARD =STANDARD I256 DDR_A_CLK1 DDR_CLK_PHY DDR_CLK MEM_A_CLK_N<3..2> 72
TABLE_PHYSICAL_RULE_ITEM

Minimum diff spacing is 4 mil

DDR_42S_D * =42_OHM_SE =42_OHM_SE =42_OHM_SE =42_OHM_SE 0.1016 MM 0.1016 MM DDR_A_CTRL0 DDR_CTRL_PHY DDR_CTRL MEM_A_CKE<1..0> 7 23

D DDR_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM
Table 4-5, Intel Doc# 486712 I180

I181 DDR_A_CTRL0 DDR_CTRL_PHY DDR_CTRL MEM_A_CS_L<1..0> 7 23 D

TABLE_PHYSICAL_RULE_ITEM
I182 DDR_A_CTRL0 DDR_CTRL_PHY DDR_CTRL MEM_A_ODT<1..0> 7 23

DDR_68D * =68_OHM_DIFF =68_OHM_DIFF =68_OHM_DIFF =68_OHM_DIFF =68_OHM_DIFF =68_OHM_DIFF I247 DDR_A_CTRL1 DDR_CTRL_PHY DDR_CTRL MEM_A_CKE<3..2> 72
TABLE_PHYSICAL_RULE_ITEM

I248 DDR_A_CTRL1 DDR_CTRL_PHY DDR_CTRL MEM_A_CS_L<3..2> 72

DDR_COMP * Y 0.305 MM 0.105 MM =STANDARD =STANDARD =STANDARD MEM_A_ODT<3..2>
I249 DDR_A_CTRL1 DDR_CTRL_PHY DDR_CTRL 72

I183 DDR_A_CMD DDR_CMD_PHY DDR_CMD MEM_A_A<15..0> 7 23

TABLE_PHYSICAL_RULE_HEAD
I184 DDR_A_CMD DDR_CMD_PHY DDR_CMD MEM_A_BA<2..0> 7 23

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DDR_A_CMD DDR_CMD_PHY DDR_CMD MEM_A_RAS_L 7 23
ON LAYER? I185
TABLE_PHYSICAL_RULE_ITEM

I186 DDR_A_CMD DDR_CMD_PHY DDR_CMD MEM_A_CAS_L 7 23

POWER_DDR_P4MM * Y 0.400 MM 0.100 MM 3.0 MM =STANDARD =STANDARD
I187 DDR_A_CMD DDR_CMD_PHY DDR_CMD MEM_A_WE_L 7 23

I188 DDR_A_DQ_BYTE0 DDR_DQ_PHY DDR_A_DQ_BYTE0 MEM_A_DQ<7..0> 7 25

Physical Net Type to Rule Map DDR3 Power-specific Spacing Definitions MEM_A_DQ<15..8>
TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_RULE_HEAD
I189 DDR_A_DQ_BYTE1 DDR_DQ_PHY DDR_A_DQ_BYTE1 7 25

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I191 DDR_A_DQ_BYTE2 DDR_DQ_PHY DDR_A_DQ_BYTE2 MEM_A_DQ<23..16> 7 25
TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM

I190 DDR_A_DQ_BYTE3 DDR_DQ_PHY DDR_A_DQ_BYTE3 MEM_A_DQ<31..24> 7 25

POWER_DDR * POWER_DDR_P4MM POWER_DDR * =2:1_SPACING ? MEM_A_DQ<39..32>
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I192 DDR_A_DQ_BYTE4 DDR_DQ_PHY DDR_A_DQ_BYTE4 7 25

DDR_CLK_PHY * DDR_68D I193 DDR_A_DQ_BYTE5 DDR_DQ_PHY DDR_A_DQ_BYTE5 MEM_A_DQ<47..40> 7 25

TABLE_PHYSICAL_ASSIGNMENT_ITEM

I194 DDR_A_DQ_BYTE6 DDR_DQ_PHY DDR_A_DQ_BYTE6 MEM_A_DQ<55..48> 7 25

DDR_CTRL_PHY * DDR_39S
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I195 DDR_A_DQ_BYTE7 DDR_DQ_PHY DDR_A_DQ_BYTE7 MEM_A_DQ<63..56> 7 25

DDR_CMD_PHY * DDR_34S
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I196 DDR_A_DQS0 DDR_DQS_PHY DDR_A_DQS0 MEM_A_DQS_P<0> 7 25

DDR_DQ_PHY * DDR_42S I197 DDR_A_DQS0 DDR_DQS_PHY DDR_A_DQS0 MEM_A_DQS_N<0> 7 25

TABLE_PHYSICAL_ASSIGNMENT_ITEM

I198 DDR_A_DQS1 DDR_DQS_PHY DDR_A_DQS1 MEM_A_DQS_P<1> 7 25

DDR_DQS_PHY * DDR_42S_D
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I199 DDR_A_DQS1 DDR_DQS_PHY DDR_A_DQS1 MEM_A_DQS_N<1> 7 25

DDR_COMP_PHY * DDR_COMP I200 DDR_A_DQS2 DDR_DQS_PHY DDR_A_DQS2 MEM_A_DQS_P<2> 7 25

DDR3-specific Spacing Definitions I201 DDR_A_DQS2 DDR_DQS_PHY DDR_A_DQS2 MEM_A_DQS_N<2> 7 25

Main Segment Min Spacing Rules (mils) (Shark Bay PDG, Intel Doc# 486712) MEM_A_DQS_P<3>
TABLE_SPACING_RULE_HEAD

I203 DDR_A_DQS3 DDR_DQS_PHY DDR_A_DQS3 7 25

C SPACING_RULE_SET

DDR_CLK_ISO
LAYER

*
LINE-TO-LINE SPACING

=5:1_SPACING
WEIGHT

?
TABLE_SPACING_RULE_ITEM
Table
4-2
Trace Design
4 (diff)
Iso
15
Design
19.69
Comments
CLK trace spacing controlled by =68_OHM_DIFF
I202 DDR_A_DQS3
DDR_A_DQS4
DDR_DQS_PHY
DDR_DQS_PHY
DDR_A_DQS3
DDR_A_DQS4
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
7 25

7 25
C
I204
TABLE_SPACING_RULE_ITEM

I205 DDR_A_DQS4 DDR_DQS_PHY DDR_A_DQS4 MEM_A_DQS_N<4> 7 25

DDR_CTRL_ISO * =3.5:1_SPACING ? 4-3 8 9.84 12 13.78
TABLE_SPACING_RULE_ITEM
I206 DDR_A_DQS5 DDR_DQS_PHY DDR_A_DQS5 MEM_A_DQS_P<5> 7 25

DDR_CTRL2CTRL * =2.5:1_SPACING ? I207 DDR_A_DQS5 DDR_DQS_PHY DDR_A_DQS5 MEM_A_DQS_N<5> 7 25

TABLE_SPACING_RULE_ITEM

I208 DDR_A_DQS6 DDR_DQS_PHY DDR_A_DQS6 MEM_A_DQS_P<6> 7 25

DDR_CMD_ISO * =3.5:1_SPACING ? 4-4 6 7.87 12 13.78
MEM_A_DQS_N<6>
I209 DDR_A_DQS6 DDR_DQS_PHY DDR_A_DQS6 7 25
TABLE_SPACING_RULE_ITEM

DDR_CMD2CMD * =2:1_SPACING ? I210 DDR_A_DQS7 DDR_DQS_PHY DDR_A_DQS7 MEM_A_DQS_P<7> 7 25

TABLE_SPACING_RULE_ITEM

I211 DDR_A_DQS7 DDR_DQS_PHY DDR_A_DQS7 MEM_A_DQS_N<7> 7 25

DDR_DATA_ISO * =3:1_SPACING ? 4-5 8.5 7.87 12 11.81 DQ or DQS to other signals not in the same bytelane (but not ch)
TABLE_SPACING_RULE_ITEM

DDR_DQ2DQ * =2:1_SPACING 900 DQ to DQ in the same bytelane of the same channel Channel B
TABLE_SPACING_RULE_ITEM

I212 DDR_B_CLK0 DDR_CLK_PHY DDR_CLK MEM_B_CLK_P<1..0> 7 24

DDR_DQ2DQS * =3:1_SPACING ? 10 11.81 DQ to DQS in the same bytelane of the same channel
MEM_B_CLK_N<1..0>
TABLE_SPACING_RULE_ITEM
I213 DDR_B_CLK0 DDR_CLK_PHY DDR_CLK 7 24

DDR_BL2BL * =3:1_SPACING ? 12 11.81 DQ or DQS in different bytelanes of the same channel I254 DDR_B_CLK1 DDR_CLK_PHY DDR_CLK MEM_B_CLK_P<3..2> 72
TABLE_SPACING_RULE_ITEM

I253 DDR_B_CLK1 DDR_CLK_PHY DDR_CLK MEM_B_CLK_N<3..2> 72

DDR_CH2CH * =6.5:1_SPACING ? 25 25.59 DQ or DQS in different channels
TABLE_SPACING_RULE_ITEM

I214 DDR_B_CTRL0 DDR_CTRL_PHY DDR_CTRL MEM_B_CKE<1..0> 7 24

DDR_COMP_ISO * 0.381 MM ? - 25.59 DDR3 to any other signal not DDR3
MEM_B_CS_L<1..0>
I215 DDR_B_CTRL0 DDR_CTRL_PHY DDR_CTRL 7 24

I216 DDR_B_CTRL0 DDR_CTRL_PHY DDR_CTRL MEM_B_ODT<1..0> 7 24

I250 DDR_B_CTRL1 DDR_CTRL_PHY DDR_CTRL MEM_B_CKE<3..2> 72

Constraints MEM_B_CS_L<3..2>
I251 DDR_B_CTRL1 DDR_CTRL_PHY DDR_CTRL 72
Clocks: CK[3:0], CK#[3:0] Data: DQS[7:0], DQS#[7:0], DQ[63:0] MEM_B_ODT<3..2>
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
I252 DDR_B_CTRL1 DDR_CTRL_PHY DDR_CTRL 72

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
I217 DDR_B_CMD DDR_CMD_PHY DDR_CMD MEM_B_A<15..0> 7 24

DDR_CLK * * DDR_CLK_ISO DDR_A_DQ_BYTE* * * DDR_DATA_ISO I218 DDR_B_CMD DDR_CMD_PHY DDR_CMD MEM_B_BA<2..0> 7 24

TABLE_SPACING_ASSIGNMENT_ITEM

I219 DDR_B_CMD DDR_CMD_PHY DDR_CMD MEM_B_RAS_L 7 24

DDR_A_DQS* * * DDR_DATA_ISO
I220 DDR_B_CMD DDR_CMD_PHY DDR_CMD MEM_B_CAS_L 7 24
Control: CS#[3:0], CKE[3:0], ODT[3:0] TABLE_SPACING_ASSIGNMENT_ITEM

B NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD
DDR_B_DQ_BYTE* * * DDR_DATA_ISO
TABLE_SPACING_ASSIGNMENT_ITEM
I221 DDR_B_CMD DDR_CMD_PHY DDR_CMD MEM_B_WE_L 7 24
B
TABLE_SPACING_ASSIGNMENT_ITEM
DDR_B_DQS* * * DDR_DATA_ISO I222 DDR_B_DQ_BYTE0 DDR_DQ_PHY DDR_B_DQ_BYTE0 MEM_B_DQ<7..0> 7 25

DDR_CTRL * * DDR_CTRL_ISO TABLE_SPACING_ASSIGNMENT_ITEM

I223 DDR_B_DQ_BYTE1 DDR_DQ_PHY DDR_B_DQ_BYTE1 MEM_B_DQ<15..8> 7 25

DDR_*_DQ_BYTE* =SAME * DDR_DQ2DQ See Note (3)
TABLE_SPACING_ASSIGNMENT_ITEM

I225 DDR_B_DQ_BYTE2 DDR_DQ_PHY DDR_B_DQ_BYTE2 MEM_B_DQ<23..16> 7 25

DDR_CTRL DDR_CTRL * DDR_CTRL2CTRL TABLE_SPACING_ASSIGNMENT_ITEM

DDR_A_DQ_BYTE* DDR_A_DQS* * DDR_DQ2DQS See Note (1) I224 DDR_B_DQ_BYTE3 DDR_DQ_PHY DDR_B_DQ_BYTE3 MEM_B_DQ<31..24> 7 25
TABLE_SPACING_ASSIGNMENT_ITEM

I226 DDR_B_DQ_BYTE4 DDR_DQ_PHY DDR_B_DQ_BYTE4 MEM_B_DQ<39..32> 7 25

DDR_A_DQ_BYTE* DDR_A_DQ_BYTE* * DDR_BL2BL See Note (3)
Command: MA[15:0], RAS#, CAS#, WE# BS[2:0] TABLE_SPACING_ASSIGNMENT_ITEM
I227 DDR_B_DQ_BYTE5 DDR_DQ_PHY DDR_B_DQ_BYTE5 MEM_B_DQ<47..40> 7 25
TABLE_SPACING_ASSIGNMENT_HEAD

DDR_B_DQ_BYTE* DDR_B_DQS* * DDR_DQ2DQS See Note (1) I228 DDR_B_DQ_BYTE6 DDR_DQ_PHY DDR_B_DQ_BYTE6 MEM_B_DQ<55..48> 7 25
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM

I229 DDR_B_DQ_BYTE7 DDR_DQ_PHY DDR_B_DQ_BYTE7 MEM_B_DQ<63..56> 7 25

TABLE_SPACING_ASSIGNMENT_ITEM

DDR_B_DQ_BYTE* DDR_B_DQ_BYTE* * DDR_BL2BL

DDR_CMD * * DDR_CMD_ISO TABLE_SPACING_ASSIGNMENT_ITEM

I230 DDR_B_DQS0 DDR_DQS_PHY DDR_B_DQS0 MEM_B_DQS_P<0> 7 25

TABLE_SPACING_ASSIGNMENT_ITEM

DDR_A_* DDR_B_* * DDR_CH2CH See Note (2)

DDR_CMD DDR_CMD * DDR_CMD2CMD I231 DDR_B_DQS0 DDR_DQS_PHY DDR_B_DQS0 MEM_B_DQS_N<0> 7 25

I232 DDR_B_DQS1 DDR_DQS_PHY DDR_B_DQS1 MEM_B_DQS_P<1> 7 25

Note (1):
I233 DDR_B_DQS1 DDR_DQS_PHY DDR_B_DQS1 MEM_B_DQS_N<1> 7 25
Deliberately set DQ to DQS spacing to 3:1 to avoid adding
I234 DDR_B_DQS2 DDR_DQS_PHY DDR_B_DQS2 MEM_B_DQS_P<2> 7 25
TABLE_SPACING_ASSIGNMENT_HEAD

complexity to contraints, even though it can be less. Only

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I235 DDR_B_DQS2 DDR_DQS_PHY DDR_B_DQS2 MEM_B_DQS_N<2> 7 25
one rule per channel is needed by trading off a little space.
TABLE_SPACING_ASSIGNMENT_ITEM

I237 DDR_B_DQS3 DDR_DQS_PHY DDR_B_DQS3 MEM_B_DQS_P<3> 7 25

DDR_COMP * * DDR_COMP_ISO
Note (2): I236 DDR_B_DQS3 DDR_DQS_PHY DDR_B_DQS3 MEM_B_DQS_N<3> 7 25

Intel suggests 25 mil (0.65 mm) spacing for via to channel, I238 DDR_B_DQS4 DDR_DQS_PHY DDR_B_DQS4 MEM_B_DQS_P<4> 7 25

and via to pad to two different channels. DDR3 draws about I239 DDR_B_DQS4 DDR_DQS_PHY DDR_B_DQS4 MEM_B_DQS_N<4> 7 25

20 mA per trace with edge rates in the 100s of ps. The main I240 DDR_B_DQS5 DDR_DQS_PHY DDR_B_DQS5 MEM_B_DQS_P<5> 7 25

coupling mechanism is capacitive. A 0.65 mm spacing is used I241 DDR_B_DQS5 DDR_DQS_PHY DDR_B_DQS5 MEM_B_DQS_N<5> 7 25

for power nets, which draw far more current (inductive I242 DDR_B_DQS6 DDR_DQS_PHY DDR_B_DQS6 MEM_B_DQS_P<6> 7 25

coupling however). These rules are far too conservative. I243 DDR_B_DQS6 DDR_DQS_PHY DDR_B_DQS6 MEM_B_DQS_N<6> 7 25

To meet these rules, the spacing must be applied to the net. I244 DDR_B_DQS7 DDR_DQS_PHY DDR_B_DQS7 MEM_B_DQS_P<7> 7 25

I245 DDR_B_DQS7 DDR_DQS_PHY DDR_B_DQS7 MEM_B_DQS_N<7> 7 25

A Note (3):
In order for the constraints DDR_*_DQ_BYTE* to =SAME to win
Reset
SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013 A
out over DDR_{A,B}_DQ_BYTE* to DDR_{A,B}_DQ_BYTE* so that PAGE TITLE

the small intra-bytelane spacing is used, the spacing rule

I246 DDR_50S MEM_RESET_L 21 23 24
DDR3 Constraints
DDR_DQ2DQ must have a weight greater than DDR_BL2BL. DRAWING NUMBER SIZE
SM COMP
DDR_COMP_PHY DDR_COMP CPU_SM_RCOMP<0..2> 6 Apple Inc. 051-0164 D
I257
REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
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IV ALL RIGHTS RESERVED 75 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PCI Express/DMI CPU ASYNCHRONOUS PCIe (CPU)

PCIe-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD
Electrical Contraint Set Physical Spacing Electrical Contraint Set Physical Spacing
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CPU PCIe Compensation
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

I573 CPU_ASYNC_PHY CPU_ASYNC CPU_PROCHOT_L 6 44 45 61 62 I570 COMP_PCIE_PHY COMP_PCIE CPU_PEG_RCOMP 5

PCIE_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
I574 CPU_ASYNC_PHY CPU_ASYNC CPU_PROCHOT_R_L 6

PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF I575 PECI CPU_ASYNC_PHY CPU_ASYNC_MS CPU_PECI 6 14 44 45
CPU eDP Compensation
TABLE_PHYSICAL_RULE_ITEM

I576 CPU_ASYNC_PHY CPU_ASYNC_MS SMC_PECI_L 44 45

PCIE_COMP * Y 0.305 MM 0.105 MM =STANDARD =STANDARD =STANDARD
I578 CPU_ASYNC_PHY CPU_ASYNC CPU_CATERR_L 6 45 I571 COMP_PCIE_PHY COMP_PCIE CPU_EDP_RCOMP 5
TABLE_PHYSICAL_RULE_ITEM

CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD CPU_ASYNC_PHY CPU_ASYNC CPU_PWRGD 6 14 18

D
I577

I579 CPU_ASYNC_PHY CPU_ASYNC PM_SYNC 6 12 I572 COMP_PCIE_PHY COMP_PCIE CPU_CFG_RCOMP 6 D

I581 CPU_ASYNC_PHY CPU_ASYNC PM_THRMTRIP_L 6 14 45

I580 CPU_ASYNC_PHY CPU_ASYNC CPU_RESET_L 6 14 18

I582 XDP_BPM_L CPU_ASYNC_PHY CPU_ASYNC XDP_BPM_L<1..0> 6 18

Physical Net Type to Rule Map

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

CPU_MS_ISO * =3:1_SPACING ?

C C
Spacing Constraints
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

CLK_PCIE * * CLK_PCIE_ISO
TABLE_SPACING_ASSIGNMENT_ITEM

COMP_PCIE * * COMP_PCIE_ISO
TABLE_SPACING_ASSIGNMENT_ITEM

CPU_ASYNC * * CPU_ASYNC_ISO
TABLE_SPACING_ASSIGNMENT_ITEM

CPU_ASYNC_MS * * CPU_MS_ISO

PEG Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)
Section Imp Design Iso Design Comments
4.2.1 80 80 16 15.75 PCIe Gen3. Allow looser spacing for same direction on stripline per Anil

B B

A SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013 A
PAGE TITLE

CPU CONSTRAINTS
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

PCIE_PHY * PCIE_85D Electrical Contraint Set Physical Spacing Electrical Contraint Set Physical Spacing
TABLE_PHYSICAL_ASSIGNMENT_ITEM

COMP_DMI_PHY * DMI_COMP x4 Thunderbolt DMI

I132 PCIE_GEN2_R2D PCIE_PHY PCIE_TBT_R2D PCIE_TBT_R2D_P<3..0> 26 I166 DMI_N2S PCIE_PHY DMI_N2S DMI_N2S_P<3..0> 5 12

I133 PCIE_GEN2_R2D PCIE_PHY PCIE_TBT_R2D PCIE_TBT_R2D_N<3..0> 26 I165 DMI_N2S PCIE_PHY DMI_N2S DMI_N2S_N<3..0> 5 12

I134 PCIE_PHY PCIE_TBT_R2D PCIE_TBT_R2D_C_P<3..0> 13 26 I167 DMI_S2N PCIE_PHY DMI_S2N DMI_S2N_P<3..0> 5 12

I135 PCIE_PHY PCIE_TBT_R2D PCIE_TBT_R2D_C_N<3..0> 13 26 I168 DMI_S2N PCIE_PHY DMI_S2N DMI_S2N_N<3..0> 5 12

PCIe-specific Spacing Definitions I136 PCIE_GEN2_D2R PCIE_PHY PCIE_TBT_D2R PCIE_TBT_D2R_P<3..0> 13 26

PCIE_REF_CLK CLK_PCIE_PHY CLK_PCIE DMI_CLK100M_CPU_P 6 11

D SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_HEAD
I137
I138
PCIE_GEN2_D2R PCIE_PHY
PCIE_PHY
PCIE_TBT_D2R
PCIE_TBT_D2R
PCIE_TBT_D2R_N<3..0>
PCIE_TBT_D2R_C_P<3..0>
13 26

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_TBT_D2R * * PCIE_ISO
TABLE_SPACING_ASSIGNMENT_ITEM x1 AirPort
PCIE_TBT_R2D * * PCIE_ISO PCIE_GEN2_R2D_CONN_AP PCIE_PHY PCIE PCIE_AP_R2D_P 32
I142

I143 PCIE_GEN2_R2D_CONN_AP PCIE_PHY PCIE PCIE_AP_R2D_N 32

I144 PCIE_PHY PCIE PCIE_AP_R2D_C_P 13 32

I146 PCIE_PHY PCIE PCIE_AP_R2D_C_N 13 32

I145 PCIE_GEN2_D2R_CONN_AP PCIE_PHY PCIE PCIE_AP_D2R_P 13 32

I147 PCIE_GEN2_D2R_CONN_AP PCIE_PHY PCIE PCIE_AP_D2R_N 13 32

C PCIE_REF_CLK CLK_PCIE_PHY CLK_PCIE PCIE_CLK100M_AP_P 11 32

C
I148

I149 PCIE_REF_CLK CLK_PCIE_PHY CLK_PCIE PCIE_CLK100M_AP_N 11 32

x1 Caesar IV
I151 PCIE_GEN2_R2D PCIE_PHY PCIE PCIE_ENET_R2D_P 35

I150 PCIE_GEN2_R2D PCIE_PHY PCIE PCIE_ENET_R2D_N 35

PCH x1 PCIE Constraints PCIE_ENET_R2D_C_P
TABLE_SPACING_ASSIGNMENT_HEAD
I152 PCIE_PHY PCIE 13 35

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I154 PCIE_PHY PCIE PCIE_ENET_R2D_C_N 13 35

TABLE_SPACING_ASSIGNMENT_ITEM

I153 PCIE_GEN2_D2R PCIE_PHY PCIE PCIE_ENET_D2R_P 13 35

PCIE * * PCIE_ISO
I155 PCIE_GEN2_D2R PCIE_PHY PCIE PCIE_ENET_D2R_N 13 35

I156 PCIE_PHY PCIE PCIE_ENET_D2R_C_P 35

I157 PCIE_PHY PCIE PCIE_ENET_D2R_C_N 35

I158 PCIE_REF_CLK CLK_PCIE_PHY CLK_PCIE PCIE_CLK100M_ENET_P 11 35

DMI-specific Spacing Definitions I159 PCIE_REF_CLK CLK_PCIE_PHY CLK_PCIE PCIE_CLK100M_ENET_N 11 35
TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT x2 SSD

TABLE_SPACING_RULE_ITEM

I172 PCIE_REF_CLK_CONN CLK_PCIE_PHY CLK_PCIE PCIE_CLK100M_SSD_P 11 33

DMI_SAME_DIR TOP,BOTTOM =5X_DIELECTRIC ? PCIE_CLK100M_SSD_N
TABLE_SPACING_RULE_ITEM
I173 PCIE_REF_CLK_CONN CLK_PCIE_PHY CLK_PCIE 11 33

DMI_SAME_DIR * =4X_DIELECTRIC ?
TABLE_SPACING_RULE_ITEM

PCH PCIE Compensation

DMI_ALT_DIR * =5X_DIELECTRIC ? PCH_PCIE_RCOMP
TABLE_SPACING_RULE_ITEM
I178 COMP_DMI_PHY COMP_PCIE 13

DMI_ISO * =4X_DIELECTRIC ?

DMI x4 PCIE Spacing Constraints

B NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD

B
TABLE_SPACING_ASSIGNMENT_ITEM

DMI_N2S DMI_N2S * DMI_SAME_DIR

TABLE_SPACING_ASSIGNMENT_ITEM

DMI_S2N DMI_S2N * DMI_SAME_DIR

TABLE_SPACING_ASSIGNMENT_ITEM

DMI_N2S DMI_S2N * DMI_ALT_DIR

TABLE_SPACING_ASSIGNMENT_ITEM CPU DP REF CLK
DMI_N2S * * DMI_ISO
TABLE_SPACING_ASSIGNMENT_ITEM

DMI_S2N * * DMI_ISO Electrical Contraint Set Physical Spacing

CPU DP REF CLK

I175 CPU_CLK135_PLL PCIE_PHY CLK_PCIE CPU_CLK135M_DPLLREF_N 6 11

I174 CPU_CLK135_PLL PCIE_PHY CLK_PCIE CPU_CLK135M_DPLLREF_P 6 11

I176 CPU_CLK135_PLL PCIE_PHY CLK_PCIE CPU_CLK135M_DPLLSS_N 6 11

I177 CPU_CLK135_PLL PCIE_PHY CLK_PCIE CPU_CLK135M_DPLLSS_P 6 11

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

DMI_COMP * Y 0.2032 MM 0.2032 MM 3 MM =STANDARD =STANDARD

A SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013 A
PAGE TITLE

PCH PCIe/DMI Constaints

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

SATA SATA XDP

SATA-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD
Electrical Contraint Set Physical Spacing Electrical Contraint Set Physical Spacing
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? PCH SATA Port 0 (HDD) CPU XDP
TABLE_PHYSICAL_RULE_ITEM

SATA_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD I90 SATA_R2D SATA_PHY_90 SATA SATA_HDD_R2D_P 33 I37 XDP_BPM_L XDP_PHY XDP XDP_BPM_L<7..2> 6 18
TABLE_PHYSICAL_RULE_ITEM

I92 SATA_R2D SATA_PHY_90 SATA SATA_HDD_R2D_N 33 I38 XDP_CPU_CFG XDP_PHY XDP CPU_CFG<17..4> 6 18 72
SATA_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
I88 SATA_PHY_90 SATA SATA_HDD_R2D_C_P 11 33 I117 XDP_CPU_CFG_3 XDP_PHY XDP CPU_CFG<3> 6 18

SATA_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF I89 SATA_PHY_90 SATA SATA_HDD_R2D_C_N 11 33 I118 XDP_CPU_CFG XDP_PHY XDP CPU_CFG<2..0> 6 18

I94 SATA_D2R SATA_PHY_90 SATA SATA_HDD_D2R_P 11 33 I45 XDP_PHY CLK_JTAG XDP_CPU_TCK 6 18

D I95
I91
SATA_D2R SATA_PHY_90
SATA_PHY_90
SATA
SATA
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
11 33

33
I46
I47
XDP_PHY
XDP_PHY
XDP
XDP
XDP_CPU_TMS
XDP_CPU_TDI
6 18

6 18
D
Physical Net Type to Rule Map SATA_HDD_D2R_C_N XDP_CPU_TDO
TABLE_PHYSICAL_ASSIGNMENT_HEAD
I93 SATA_PHY_90 SATA 33 I48 XDP_PHY XDP 6 18

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PCH XDP
SATA_PHY * SATA_85D
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I49 XDP_PHY CLK_JTAG XDP_PCH_TCK 11 18

COMP_SATA_PHY * SATA_50S PCH SATA Port 1 (SSD) I50 XDP_PHY XDP XDP_PCH_TMS 11 18
SATA Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718) SSD_R2D_P<0..1> XDP_PCH_TDI
TABLE_PHYSICAL_ASSIGNMENT_ITEM

I96 SATA_SSD_R2D SATA_PHY SATA 11 33 I51 XDP_PHY XDP 11 18

SATA_PHY_90 * SATA_90D
Section Imp Design Iso Design Comments I98 SATA_SSD_R2D SATA_PHY SATA SSD_R2D_N<0..1> 11 33 I52 XDP_PHY XDP XDP_PCH_TDO 11 18

15.2.1 90 95 20 23.62 SATA Gen2, SATA Gen3 I115 SATA_SSD_R2D SATA_PHY SATA SSD_R2D_C_P<0..1> 33

I116 SATA_SSD_R2D SATA_PHY SATA SSD_R2D_C_N<0..1> 33

SATA-specific Spacing Definitions
TABLE_SPACING_RULE_HEAD
SATA Compensation Rules (mils) I103 SATA_SSD_D2R SATA_PHY SATA SSD_D2R_P<0..1> 11 33

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I102 SATA_SSD_D2R SATA_PHY SATA SSD_D2R_N<0..1> 11 33
TABLE_SPACING_RULE_ITEM
Table Imp Design Iso Design Comments
SATA_ISO * =6:1_SPACING ? 15-3 50 50 15 15.75 SATA Gen2, SATA Gen3
TABLE_SPACING_RULE_ITEM
PCH SATA Compensation
COMP_SATA_ISO * =4:1_SPACING ? I104 COMP_SATA_PHY COMP_SATA PCH_SATA_RCOMP 11

Constraints
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

SATA * * SATA_ISO
TABLE_SPACING_ASSIGNMENT_ITEM

COMP_SATA * * COMP_SATA_ISO

FDI
C FDI-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD
C
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

FDI_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

COMP_FDI * Y 0.25 MM 0.25 MM 3 MM =STANDARD =STANDARD

FDI
Physical Net Type to Rule Map
TABLE_PHYSICAL_ASSIGNMENT_HEAD
Electrical Contraint Set Physical Spacing
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET FDI
TABLE_PHYSICAL_ASSIGNMENT_ITEM

FDI_SE_PHY FDI FDI_CSYNC 5 12

FDI_SE_PHY * FDI_50S I112
TABLE_PHYSICAL_ASSIGNMENT_ITEM

COMP_FDI_PHY * COMP_FDI I113 FDI_SE_PHY FDI FDI_INT 5 12

FDI-specific Spacing Definitions FDI Compensation

TABLE_SPACING_RULE_HEAD
FDI Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718) I114 COMP_FDI_PHY COMP_FDI PCH_FDI_RCOMP 12
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
Table Imp Design Iso Design Comments
FDI_ISO * =3:1_SPACING ? 6-1/6-2 85 85 12 11.81 FDI main length
TABLE_SPACING_RULE_ITEM

COMP_FDI_ISO * =4:1_SPACING ?
FDI Compensation Rules (mils)
Table Trace Design Iso Design Comments
Constraints
TABLE_SPACING_ASSIGNMENT_HEAD
6-4 10 11.81 - 15.75 Using PCIe guidelines
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

FDI * * FDI_ISO
TABLE_SPACING_ASSIGNMENT_ITEM

COMP_FDI * * COMP_FDI_ISO

B B
XDP
XDP-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

XDP_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

Physical Net Type to Rule Map

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_ITEM

XDP_PHY * XDP_55S

XDP-specific Spacing Definitions

TABLE_SPACING_RULE_HEAD
Desktop Debug Design Guide (Intel Doc# 430883)
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
Section Imp Design Iso Design Comments
XDP_ISO * =2:1_SPACING ? 1.5 45-65 55 - 15.75 Isolation is for JTAG clocks.
TABLE_SPACING_RULE_ITEM

All signals default are 50 Ohm SE.

CLK_JTAG_ISO * =4:1_SPACING ?

Constraints
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

XDP * * XDP_ISO
A CLK_JTAG * * CLK_JTAG_ISO
TABLE_SPACING_ASSIGNMENT_ITEM

SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013 A
PAGE TITLE

SATA/FDI/XDP Constraints
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

PCH PCI HDA

PCH-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD
Electrical Contraint Set Physical Spacing Electrical Contraint Set Physical Spacing
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? PCI Clock HDA
TABLE_PHYSICAL_RULE_ITEM

PCH_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD I333 CLK_PCI_55S CLK_PCI PCH_CLK33M_PCIIN 11 19 I353 HDA_55S HDA HDA_BIT_CLK 11 52
TABLE_PHYSICAL_RULE_ITEM

I334 CLK_PCI_55S CLK_PCI PCH_CLK33M_PCIOUT 11 19 I361 HDA_55S HDA HDA_BIT_CLK_R 11

CLK_PCH_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
I363 HDA_55S HDA HDA_RST_L 11 52

I362 HDA_55S HDA HDA_RST_R_L 11

PCH-specific Spacing Definitions I364 HDA_55S HDA HDA_SDOUT 11 52

D SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM
LPC I367
I366
HDA_55S
HDA_55S
HDA
HDA
HDA_SDOUT_R
HDA_SYNC
11 19

11 52
D
CLK_PCH * =4:1_SPACING ? I368 HDA_55S HDA HDA_SYNC_R 11
Electrical Contraint Set Physical Spacing
TABLE_SPACING_RULE_ITEM

I365 HDA_55S HDA HDA_SDIN0 11 52

COMP_PCH * =2:1_SPACING ?
LPC I369 HDA_55S HDA AUD_SDI_R 52

I336 LPC_55S LPC LPC_AD<3..0> 13 44 46

I335 LPC_55S LPC LPC_AD_R<3..0> 13 SPDIF

LPC_FRAME_L AUD_SPDIF_CHIP
PCI I338

I337
LPC_55S
LPC_55S
LPC
LPC LPC_FRAME_R_L
13 44 46

13
I370

I371
HDA
HDA AUD_SPDIF_OUT
52

52 56

PCI-specific Physical Rules

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

LPC Clocks
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
I339 CLK_LPC_55S CLK_LPC LPC_CLK33M_LPCPLUS 19 46
TABLE_PHYSICAL_RULE_ITEM

CLK_PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD I340 CLK_LPC_55S CLK_LPC LPC_CLK33M_LPCPLUS_R 11 19

I341 CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC 19 44

I342 CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC_R 11 19

PCI-specific Spacing Definitions SPI Bootrom

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

Electrical Contraint Set Physical Spacing
CLK_PCI * =2:1_SPACING ?
TABLE_SPACING_RULE_ITEM

PCH Clocks
SPI ROM
Electrical Contraint Set Physical Spacing I391 SPI_50S SPI SPI_CLK_R 13 46

I392 SPI_50S SPI SPI_CLK 46

PCH Reference Clock
I393 SPI_50S SPI SPI_ALT_CLK 46
I385 CLK_PCH_55S CLK_PCH SYSCLK_CLK25M_SB 11 19
I408 SPI_50S SPI SPI_SMC_CLK 44 46
SYSCLK_CLK25M_SB_R
LPC I406 CLK_PCH_55S CLK_PCH 11
I407 SPI_50S SPI SPI_MLB_CLK 46

LPC-specific Physical Rules I394 SPI_50S SPI SPI_CS0_R_L 13 46

C PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP
TABLE_PHYSICAL_RULE_HEAD

DIFFPAIR NECK GAP

I395 SPI_50S
SPI_50S
SPI
SPI
SPI_CS0_L
SPI_ALT_CS_L
46

46
C
TABLE_PHYSICAL_RULE_ITEM
I396
LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCH RTC 32K I409 SPI_50S SPI SPI_SMC_CS_L 44 46
TABLE_PHYSICAL_RULE_ITEM

I347 CLK_XTAL XTAL PCH_CLK32K_RTCX1 11 19 I397 SPI_50S SPI SPI_MLB_CS_L 46

CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCH_CLK32K_RTCX2
I348 CLK_XTAL XTAL 11 19
I399 SPI_50S SPI SPI_MOSI_R 13 46
I352 CLK_XTAL XTAL PCH_CLK32K_RTCX2_R 19
I400 SPI_50S SPI SPI_MOSI 46
LPC-specific Spacing Definitions SPI_ALT_MOSI
I401 SPI_50S SPI 46
TABLE_SPACING_RULE_HEAD

SMC 32K
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I410 SPI_50S SPI SPI_SMC_MOSI 44 46
I349 CLK_PCH_55S CLK_PCH PM_CLK32K_SUSCLK_R 12 45
TABLE_SPACING_RULE_ITEM

I411 SPI_50S SPI SPI_MLB_MOSI 46

LPC * =1.5:1_SPACING ? I350 CLK_PCH_55S CLK_PCH SMC_CLK32K 44 45
TABLE_SPACING_RULE_ITEM

I404 SPI_50S SPI SPI_MISO 13 46

CLK_LPC * =2:1_SPACING ?
I403 SPI_50S SPI SPI_ALT_MISO 46

I412 SPI_50S SPI SPI_SMC_MISO 44 46

SPI_50S SPI SPI_MLB_MISO 46

25 MHz Reference Clocks I413

HDA I405 SPI_50S SPI SPIROM_USE_MLB 14 46

Electrical Contraint Set Physical Spacing

HDA-specific Physical Rules
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

25M Reference Crystal

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
I379 CLK_XTAL XTAL SYSCLK_CLK25M_X1 19
TABLE_PHYSICAL_RULE_ITEM

HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD I380 CLK_XTAL XTAL SYSCLK_CLK25M_X2 19

I381 CLK_XTAL XTAL SYSCLK_CLK25M_X2_R 19

HDA-specific Spacing Definitions

TABLE_SPACING_RULE_HEAD
25M Reference Clocks
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I384 CLK_PCH_55S CLK_PCH SYSCLK_CLK25M_ENET 19 35
TABLE_SPACING_RULE_ITEM

I386 CLK_PCH_55S CLK_PCH SYSCLK_CLK25M_ENET_R 19

HDA * =2x_DIELECTRIC ?
CLK_PCH_55S CLK_PCH SYSCLK_CLK25M_TBT 19 26

B I388

I387 CLK_PCH_55S CLK_PCH SYSCLK_CLK25M_TBT_R 26 B

Crystal
Crystal-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

CLK_XTAL * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

Crystal-specific Spacing Definitions

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_ITEM

XTAL * =4X_DIELECTRIC ?

SPI
SPI-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

SPI_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

A SYNC_MASTER=J16_MLB SYNC_DATE=12/03/2012 A
SPI-specific Spacing Definitions PAGE TITLE

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_HEAD

PCH and BR Constraints

TABLE_SPACING_RULE_ITEM
DRAWING NUMBER SIZE
SPI * =2:1_SPACING ?
Apple Inc. 051-0164 D
REVISION
R
12.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
115 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 79 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

USB USB 3.0 and USB 2.0 Trixies Muxing RMH Love
USB-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD
Electrical Contraint Set Physical Spacing Electrical Contraint Set Physical Spacing
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? External Port A (J4600)
TABLE_PHYSICAL_RULE_ITEM

USB_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF I320 USB3_RX_CONN USB3_PHY USB3 USB3_EXTA_RX_P 42
TABLE_PHYSICAL_RULE_ITEM

I321 USB3_RX_CONN USB3_PHY USB3 USB3_EXTA_RX_N 42

USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
I391 USB3_PHY USB3 USB3_EXTA_RX_F_P 13 42
I409 USB2_MUXED_BT USB2_PHY USB2 USB_BT_P 13 32
I392 USB3_PHY USB3 USB3_EXTA_RX_F_N 13 42
I410 USB2_MUXED_BT USB2_PHY USB2 USB_BT_N 13 32
Physical Net Type to Rule Map USB3_EXTA_TX_P USB_BT_MUX_P
USB3_TX_CONN USB3_PHY USB3 13 42 USB2_MUXED_BT USB2_PHY USB2 32

D NET_PHYSICAL_TYPE AREA_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD

PHYSICAL_RULE_SET
I413

I414 USB3_TX_CONN USB3_PHY USB3 USB3_EXTA_TX_N 13 42

I505

I506 USB2_MUXED_BT USB2_PHY USB2 USB_BT_MUX_N 32 D

TABLE_PHYSICAL_ASSIGNMENT_ITEM

I415 USB3_PHY USB3 USB3_EXTA_TX_F_P 42

USB2_PHY * USB_90D
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I416 USB3_PHY USB3 USB3_EXTA_TX_F_N 42

USB3_PHY * USB_85D I493 USB3_PHY USB3 USB3_EXTA_TX_C_P 42

I494 USB3_PHY USB3 USB3_EXTA_TX_C_N 42

USB-specific Spacing Definitions I417 USB2_MUXED_MOJO_CONN USB2_PHY USB2 USB_EXTA_0_P 13 42

USB Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718) USB_EXTA_0_N
TABLE_SPACING_RULE_HEAD

I418 USB2_MUXED_MOJO_CONN USB2_PHY USB2 13 42

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
Section Imp Design Iso Design Comments I419 USB2_PHY USB2 USB2_EXTA_MUXED_P 42

USB2_ISO * =3:1_SPACING ? 12.2.1 90 90 12 11.81 USB 2.0 I420 USB2_PHY USB2 USB2_EXTA_MUXED_N 42
TABLE_SPACING_RULE_ITEM

I393 USB2_PHY USB2 USB2_EXTA_P 42

USB2_ISO TOP,BOTTOM =3:1_SPACING ? 13.3.1 85 85 20 21.65 USB 3.0
I394 USB2_PHY USB2 USB2_EXTA_N 42
TABLE_SPACING_RULE_ITEM

USB3_ISO * =5.5:1_SPACING ?
TABLE_SPACING_RULE_ITEM

External Port B (J4610)

USB3_ISO TOP,BOTTOM =5.5:1_SPACING ? USB3_EXTB_RX_P
I421 USB3_RX_CONN USB3_PHY USB3 42

I422 USB3_RX_CONN USB3_PHY USB3 USB3_EXTB_RX_N 42

Et tu Brute?
Constraints I423 USB3_PHY USB3 USB3_EXTB_RX_F_P 13 42
TABLE_SPACING_ASSIGNMENT_HEAD

USB3_PHY USB3 USB3_EXTB_RX_F_N 13 42

Electrical Contraint Set Physical Spacing
I424
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

USB3_TX_CONN USB3_PHY USB3 USB3_EXTB_TX_P 13 42

Ethernet
I425
USB2 * * USB2_ISO ENET_MDI ENET_DIFF_PHY ENET_DIFF ENETCONN_MDI_P<3..0>
TABLE_SPACING_ASSIGNMENT_ITEM
I427 USB3_TX_CONN USB3_PHY USB3 USB3_EXTB_TX_N 13 42 I474 35 36

USB3 * * USB3_ISO USB3_PHY USB3 USB3_EXTB_TX_F_P 42 I475 ENET_MDI ENET_DIFF_PHY ENET_DIFF ENETCONN_MDI_N<3..0> 35 36
I426
USB3_PHY USB3 USB3_EXTB_TX_F_N 42 I476 ENET_DIFF_PHY ENET_TRANS ENETCONN_MDI_T_P<3..0> 36
I428
USB3_PHY USB3 USB3_EXTB_TX_C_P 42 I477 ENET_DIFF_PHY ENET_TRANS ENETCONN_MDI_T_N<3..0> 36
I495

I496 USB3_PHY USB3 USB3_EXTB_TX_C_N 42 ENETCONN_MCT0

I519 ENET_TRANS 36
Caesar IV (Ethernet/SD) I429 USB2_CONN USB2_PHY USB2 USB_EXTB_8_P 13 42 I520 ENET_TRANS ENETCONN_MCT1 36

CIV-specific Physical Rules USB2_CONN USB2_PHY USB2 USB_EXTB_8_N 13 42 I521 ENET_TRANS ENETCONN_MCT2 36
I430

C PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_HEAD

I434 USB2_PHY
USB2_PHY
USB2
USB2
USB2_EXTB_P
USB2_EXTB_N
42

42
I522
I523
ENET_TRANS
ENET_TRANS
ENETCONN_MCT3
ENETCONN_MCT_BS
36

36
C
TABLE_PHYSICAL_RULE_ITEM
I433
ENET_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD ENET_COMP_PHY COMP_ENET ENET_RDAC 35
I478
TABLE_PHYSICAL_RULE_ITEM

ENET_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF SD

TABLE_PHYSICAL_RULE_ITEM

I479 SD_DATA SD_PHY SD ENET_CR_DATA<7..0> 35

SD_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
I480 SD_PHY SD SDCONN_DATA<7..0> 35 37

External Port C (J4700)

Physical Net Type to Rule Map USB3_EXTC_RX_P
I437 USB3_RX_CONN USB3_PHY USB3 43
SD_CMD SD_PHY SD ENET_SD_CMD 35
TABLE_PHYSICAL_ASSIGNMENT_HEAD
I481
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET I439 USB3_RX_CONN USB3_PHY USB3 USB3_EXTC_RX_N 43
SD_PHY SD SDCONN_CMD 35 37
I482
TABLE_PHYSICAL_ASSIGNMENT_ITEM

I438 USB3_PHY USB3 USB3_EXTC_RX_F_P 13 43

SD_PHY SD SDCONN_CMD_R
ENET_COMP_PHY * ENET_50S I516
I440 USB3_PHY USB3 USB3_EXTC_RX_F_N 13 43
TABLE_PHYSICAL_ASSIGNMENT_ITEM

ENET_DIFF_PHY * ENET_100D I483 SD_CLK SD_PHY SD ENET_SD_CLK 35

I441 USB3_TX_CONN USB3_PHY USB3 USB3_EXTC_TX_P 13 43

SD_PHY SD SDCONN_CLK 35 37
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I484
SD_PHY * SD_50S I442 USB3_TX_CONN USB3_PHY USB3 USB3_EXTC_TX_N 13 43 SDCONN_CLK_R
I486 SD_PHY SD 37
TABLE_PHYSICAL_ASSIGNMENT_ITEM

I444 USB3_PHY USB3 USB3_EXTC_TX_F_P 43

CIV_SPI * SPI_55S SD_PHY SD ENET_MEDIA_SENSE
I443 USB3_PHY USB3 USB3_EXTC_TX_F_N 43 I485 11 35

USB3_EXTC_TX_C_P I488 SD_PHY SD ENET_SD_DETECT_L 35 37

I498 USB3_PHY USB3 43

CIV-specific Spacing Definitions Constraints I497 USB3_PHY USB3 USB3_EXTC_TX_C_N 43

Ethernet Ethernet USB_EXTC_1_P

TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
I446 USB2_CONN USB2_PHY USB2 13 43 CIV SPI
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I445 USB2_CONN USB2_PHY USB2 USB_EXTC_1_N 13 43 I490 CIV_SPI SPI ENET_SCLK 35
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

I450 USB2_PHY USB2 USB2_EXTC_P 43 I489 CIV_SPI SPI ENET_MISO 35

ENET_DIFF_ISO * =6:1_SPACING ? ENET_DIFF * * ENET_DIFF_ISO
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
I452 USB2_PHY USB2 USB2_EXTC_N 43 I492 CIV_SPI SPI ENET_MOSI 35

ENET_DIFF2DIFF * =3:1_SPACING ? ENET_DIFF ENET_DIFF * ENET_DIFF2DIFF I491 CIV_SPI SPI ENET_CS_L 35

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

External Port D (J4710)

ENET_TRANS_ISO * 1.27 MM ? ENET_TRANS * * ENET_TRANS_ISO 2 kV isolation
USB3_RX_CONN USB3_PHY USB3 USB3_EXTD_RX_P 43
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
I453
Camera Processor-Camera Sensor I/F
B COMP_ENET_ISO * =4:1_SPACING ? COMP_ENET * * COMP_ENET_ISO
TABLE_SPACING_ASSIGNMENT_ITEM
I455

I454
USB3_RX_CONN USB3_PHY
USB3_PHY
USB3
USB3
USB3_EXTD_RX_N
USB3_EXTD_RX_F_P
43

13 43
B
ENET_TRANS ENET_TRANS * ENET_DIFF2DIFF Electrical Contraint Set Physical Spacing
I456 USB3_PHY USB3 USB3_EXTD_RX_F_N 13 43
I501 SMIA_DP SMIA_DIFF_PHY SMIA_DIFF SMIA_DATA_P 38

SD SD I457 USB3_TX_CONN USB3_PHY USB3 USB3_EXTD_TX_P 13 43 I502 SMIA_DP SMIA_DIFF_PHY SMIA_DIFF SMIA_DATA_N 38

TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
I458 USB3_TX_CONN USB3_PHY USB3 USB3_EXTD_TX_N 13 43
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET USB3_PHY USB3 USB3_EXTD_TX_F_P 43
I460
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

USB3_PHY USB3 USB3_EXTD_TX_F_N 43 SMIA_CLK_P

SD_ISO * =3:1_SPACING ? SD * * SD_ISO I459
I504 SMIA_DP SMIA_DIFF_PHY SMIA_DIFF 38

I499 USB3_PHY USB3 USB3_EXTD_TX_C_P 43

SMIA_DP SMIA_DIFF_PHY SMIA_DIFF SMIA_CLK_N 38
I503
I500 USB3_PHY USB3 USB3_EXTD_TX_C_N 43

Camera Processor-to-Camera Sensor I/F (SMIA/MIPI) I462 USB2_CONN USB2_PHY USB2 USB_EXTD_9_P
USB_EXTD_9_N
13 43

I461 USB2_CONN USB2_PHY USB2 13 43

Camera Processor’s SMIA Interface Physical Rules
TABLE_PHYSICAL_RULE_HEAD
I466 USB2_PHY USB2 USB2_EXTD_P 43
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPI_50S SPI CAM_SF_CLK
ON LAYER? I468 USB2_PHY USB2 USB2_EXTD_N 43 I507 38
TABLE_PHYSICAL_RULE_ITEM

I508 SPI_50S SPI CAM_SF_CLK_R 38

SMIA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
I509 SPI_50S SPI CAM_SF_DIN 38

TABLE_PHYSICAL_ASSIGNMENT_HEAD
I510 SPI_50S SPI CAM_SF_DIN_R 38

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET I511 SPI_50S SPI CAM_SF_CS_L 38

TABLE_PHYSICAL_ASSIGNMENT_ITEM

I513 SPI_50S SPI CAM_SF_WP_L 38

SMIA_DIFF_PHY * SMIA_100D Camera (J3510)
I512 SPI_50S SPI CAM_SF_DOUT 38

I324 USB2_CONN_INT USB2_PHY USB2 USB_CAMERA_P 13 38

SPI_50S SPI CAM_SF_DOUT_R 38
I514
I326 USB2_CONN_INT USB2_PHY USB2 USB_CAMERA_N 13 38
Camera Processor’s SMIA Interface Spacing Definitions I517 SMB_PHY SMB I2C_CAMSENSOR_SDA 38
TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

I518 SMB_PHY SMB I2C_CAMSENSOR_SCL 38

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

SMIA_DIFF_ISO * =6:1_SPACING ? SMIA_DIFF * * SMIA_DIFF_ISO PCH USB Compensation

A SMIA_DIFF2DIFF * =3:1_SPACING ?
TABLE_SPACING_RULE_ITEM

SMIA_DIFF SMIA_DIFF * SMIA_DIFF2DIFF

TABLE_SPACING_ASSIGNMENT_ITEM

I384 PCH_55S COMP_PCH PCH_USB_RBIAS 13

SYNC_MASTER=J16_MLB SYNC_DATE=12/03/2012 A
PAGE TITLE

USB/Ethernet/SD Constraints
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

SMBus Current/Voltage Sense SMC

SMBus-specific Physical Rules Electrical Contraint Set Physical Spacing
TABLE_PHYSICAL_RULE_HEAD
Electrical Contraint Set Physical Spacing
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP Common
ON LAYER? SMC
TABLE_PHYSICAL_RULE_ITEM

I3 SENSE GND_SMC_AVSS 44 45 48 49
SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD I1 CLK_XTAL XTAL SMC_XTAL 44 45

I2 CLK_XTAL XTAL SMC_EXTAL 44 45

12V S5 (System Total)
I91 SMC_GEN SMC_CTRL SMC_LRESET_L 20 44
Physical Net Type to Rule Map I4 SNS_CURRENT SNS_DIFF_PHY SENSE SNS_P12VG3H_P 48
SMC_RUNTIME_SCI_L
I90 SMC_GEN SMC_CTRL 14 44
TABLE_PHYSICAL_ASSIGNMENT_HEAD

I5 SNS_CURRENT SNS_DIFF_PHY SENSE SNS_P12VG3H_N 48

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET I92 SMC_GEN SMC_CTRL SMC_WAKE_SCI_L 14 44
SENSE ISNS_P12VG3H_R 48

D SMB_PHY * SMB_55S
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I6

I7 SENSE ISNS_P12VG3H 45 48
I93
I94
SMC_GEN
SMC_GEN
SMC_CTRL
SMC_CTRL
SMC_FAN_0_CTL
SMC_FAN_0_TACH
44 51

44 51
D
I8 SENSE VSNS_P12VG3H 45 48

SMBus-specific Spacing Definitions Constraints

TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

SMB_ISO * =2x_DIELECTRIC ? SMB * * SMB_ISO

SMBus
Electrical Contraint Set Physical Spacing

SMC
Sensor HDD
I10 SMB_PHY SMB SMBUS_SMC_0_S0_SCL 44 47
I80 SNS_CURRENT SNS_DIFF_PHY SENSE SNS_HDD_P 48
Sensor-specific Physical Rules SNS_HDD_N I9 SMB_PHY SMB SMBUS_SMC_0_S0_SDA 44 47
TABLE_PHYSICAL_RULE_HEAD
I82 SNS_CURRENT SNS_DIFF_PHY SENSE 48

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SENSE ISNS_HDDS0_R 48 SMB_PHY SMB SMBUS_SMC_1_S0_SCL 44 47
ON LAYER? I81 I11
TABLE_PHYSICAL_RULE_ITEM

I83 SENSE ISNS_HDDS0 45 48 I12 SMB_PHY SMB SMBUS_SMC_1_S0_SDA 44 47

1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.085 MM VSNS_HDDS0
I84 SENSE 45 48
I13 SMB_PHY SMB SMBUS_SMC_2_S4_SCL 44 47

I14 SMB_PHY SMB SMBUS_SMC_2_S4_SDA 44 47

Physical Net Type to Rule Map
TABLE_PHYSICAL_ASSIGNMENT_HEAD

I15 SMB_PHY SMB SMBUS_SMC_3_SCL 44 47

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I16 SMB_PHY SMB SMBUS_SMC_3_SDA 44 47

SNS_DIFF_PHY * 1:1_DIFFPAIR
I19 SMB_PHY SMB SMBUS_SMC_5_G3H_SCL 44 45

I20 SMB_PHY SMB SMBUS_SMC_5_G3H_SDA 44 45

Sensor-specific Spacing Definitions Constraints

TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
SSD
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I85 SNS_CURRENT SNS_DIFF_PHY SENSE SNS_SSD_P 49
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

I87 SNS_CURRENT SNS_DIFF_PHY SENSE SNS_SSD_N 49

SENSE_ISO * =1.5:1_SPACING ? SENSE * * SENSE_ISO
C SENSE POWER * PWR_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
I86
I88
SENSE
SENSE
ISNS_SSDS0_R
ISNS_SSDS0
49

45 49
PCH
I21 TBT_I2C_55S TBT_I2C SMBUS_PCH_CLK 13 47
C
TABLE_SPACING_ASSIGNMENT_ITEM

I89 SENSE VSNS_P3V3S5 45 49 I52 TBT_I2C_55S TBT_I2C SMBUS_PCH_DATA 13 47

SENSE GND * GND_P2MM
VDDQ S3 (DDR) I53 SMB_PHY SMB SML_PCH_0_CLK 13 47

I33 SNS_CURRENT SNS_DIFF_PHY SENSE SNS_VDDQS3_DDR_P 49 I54 SMB_PHY SMB SML_PCH_0_DATA 13 47

SMC Generic Control Line Spacing Definitions Constraints I32 SNS_CURRENT SNS_DIFF_PHY SENSE SNS_VDDQS3_DDR_N 49
TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

I35 SENSE ISNS_VDDQS3_DDR_R 49 Display TCon

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
I34 SENSE ISNS_VDDQS3_DDR 45 49 I55 SMB_PHY SMB SMB_DP_TCON_SCL 40 47

SMC_ISO * =1:1_SPACING ? SMC_CTRL * * SMC_ISO I36 SENSE VSNS_VDDQS3_DDR 45 49 I56 SMB_PHY SMB SMB_DP_TCON_SDA 40 47

Temperature Sense
Electrical Contraint Set Physical Spacing
SMC Generic Control Line Physical Rules
TABLE_PHYSICAL_RULE_HEAD
EMC1414-1 (Production)
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CPU Core SNS_TEMP SNS_DIFF_PHY SENSE SNS_T1_1_P 50
ON LAYER? I57
TABLE_PHYSICAL_RULE_ITEM

I42 SNS_CURRENT SNS_DIFF_PHY SENSE REG_CPUVCC_IMON_R 48 I58 SNS_TEMP SNS_DIFF_PHY SENSE SNS_T1_1_N 50
SMC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
I43 SNS_CURRENT SNS_DIFF_PHY SENSE ISNS_CPUVCC_FB_R 48
I59 SNS_TEMP SNS_DIFF_PHY SENSE SNS_T1_3_P 50
I44 SENSE ISNS_CPUVCC_FB 48
I60 SNS_TEMP SNS_DIFF_PHY SENSE SNS_T1_3_N 50
Physical Net Type to Rule Map I45 SENSE ISNS_CPUVCC 45 48
TABLE_PHYSICAL_ASSIGNMENT_HEAD

I46 SENSE VSNS_CPUVCC 45 48 I65 SNS_TEMP SNS_DIFF_PHY SENSE SNS_ACDC_P 50 60

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I66 SNS_TEMP SNS_DIFF_PHY SENSE SNS_ACDC_N 50 60

SMC_GEN * SMC_50S
I123 SNS_DIFF_PHY SENSE SNS_T1_2_P 50

SNS_DIFF_PHY SENSE SNS_T1_2_N 50

B I124
B
TMP423 (Development)
I67 SNS_TEMP SNS_DIFF_PHY SENSE SNS_T2_1_P 50

I68 SNS_TEMP SNS_DIFF_PHY SENSE SNS_T2_1_N 50

I69 SNS_TEMP SNS_DIFF_PHY SENSE SNS_T2_2_P 50

I70 SNS_TEMP SNS_DIFF_PHY SENSE SNS_T2_2_N 50

PP1V05_S0_PCH
I110 SENSE VSNS_P1V05S0_PCH 45 48
I71 SNS_TEMP SNS_DIFF_PHY SENSE SNS_T2_3_P 50

I72 SNS_TEMP SNS_DIFF_PHY SENSE SNS_T2_3_N 50

PP1V5_S0
I111 SNS_CURRENT SNS_DIFF_PHY SENSE SNS_PVDDQS0_P 49 HDD Out-of-Band
I113 SNS_CURRENT SNS_DIFF_PHY SENSE SNS_PVDDQS0_N 49 I73 SENSE HDD_OOB1_D2R_L 34

I112 SENSE ISNS_PVDDQS0_R 49 I74 SENSE HDD_OOB1_D2R_F_L 34

I114 SENSE ISNS_PVDDQS0 45 49 I75 SENSE HDD_OOB1_D2R_R_L 34

I115 SENSE VSNS_PVDDQS0 45 49 I117 SENSE SMC_OOB1_D2R_L 34 44

I76 SENSE SMC_OOB1_R2D_L 34 44

Airport I116 SENSE SMC_OOB1_R2D_R_L 34

I102 SNS_CURRENT SNS_DIFF_PHY SENSE SNS_P3V3S4_AP_P 48 SSD Out-of-Band

I103 SNS_CURRENT SNS_DIFF_PHY SENSE SNS_P3V3S4_AP_N 48 I77 SENSE SMC_OOB2_R2D_L 33 45

I104 SENSE ISNS_P3V3S4_AP_R 48 I78 SENSE SMC_OOB2_D2R_L 33 45

I105 SENSE ISNS_P3V3S4_AP 45 48

A SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013 A
PAGE TITLE

SMBus/Sensor Constraints
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

DC-DC PCH/GPU/TBT 1.05V S0

Power-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD
Electrical Contraint Set Physical Spacing Voltage DIDT NO_TEST
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? Input Bus
TABLE_PHYSICAL_RULE_ITEM

GND_P3MM * Y 0.300 MM 0.150 MM 12.7 MM =STANDARD =STANDARD I1 POWER POWER 5V REG_VCC_U7400 64

TABLE_PHYSICAL_RULE_ITEM

I2 POWER POWER 5V REG_PVCC_U7400 64

GND_P5MM * Y 0.500 MM 0.150 MM 12.7 MM =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM

POWER_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD Local Ground

TABLE_PHYSICAL_RULE_ITEM

I3 GND GND 0V AGND_P1V05S0 64

POWER_P3MM * Y 0.300 MM 0.150 MM 12.7 MM =STANDARD =STANDARD
D POWER_P6MM * Y 0.600 MM 0.150 MM 12.7 MM =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM

1.05V S0
D
I5 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_PHASE_P1V05S0 64

I4 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_PHASE_P1V05S0_L 64

Physical Net Type to Rule Map REG_BOOT_P1V05S0
TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD
I7 VR_DIDT_PHY VR_SWITCH 12V TRUE 64

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET I6 VR_DIDT_PHY VR_SWITCH 12V TRUE TRUE REG_BOOT_P1V05S0_RC 64
TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM

I8 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_UGATE_P1V05S0 64

GND * GND_P5MM VR_DIDT_PHY * POWER_P6MM
I9 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_UGATE_P1V05S0_R 64
TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM

GND BGA GND_P3MM VR_DIDT_PHY BGA STANDARD I10 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_LGATE_P1V05S0 64
TABLE_PHYSICAL_ASSIGNMENT_ITEM

I12 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_SNUBBER_P1V05S0 64

POWER * POWER_P6MM
TABLE_PHYSICAL_ASSIGNMENT_ITEM

I11 VR_CTL_PHY VR_CTL REG_P1V05S0_OCSET 64

POWER BGA POWER_P3MM
I14 VR_CTL_PHY VR_CTL REG_P1V05S0_VO 64
TABLE_PHYSICAL_ASSIGNMENT_ITEM

VR_CTL_PHY * POWER_P3MM
TABLE_PHYSICAL_ASSIGNMENT_ITEM

VR_CTL_PHY BGA STANDARD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

VR_VID_PHY * POWER_50S

I19 SENSE REG_P1V05S0_FB 64

I18 SENSE REG_P1V05S0_RTN 64

Power-specific Spacing Definitions Constraints
Power and Common Power and Common I21 VR_CTL_PHY VR_CTL REG_P1V05S0_SREF 64
TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

I20 VR_CTL_PHY VR_CTL REG_P1V05S0_FSEL 64

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

POWER_ISO * =STANDARD ? POWER * * POWER_ISO Output Bus

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

I22 POWER POWER 1.05V PP1V05_S0 70

GND_ISO * =STANDARD ? GND * * GND_ISO

FET Switched

C DC-DC Baddies
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD
DC-DC Baddies
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE
TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET
I23

I66
POWER
POWER
POWER
POWER
1.05V
1.05V
PP1V05_TBTLC
PP1V05_TBTCIO
28 70

70
C
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

SWNODE_ISO * =8:1_SPACING 1000 VR_SWITCH * * SWNODE_ISO

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

SWNODE_SW2SW * =1:1_SPACING ? VR_SWITCH * BGA BGA_P1MM

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

SWNODE_SW2PWR * =2:1_SPACING ? VR_SWITCH VR_SWITCH * SWNODE_SW2SW

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

SWNODE_SW2GND * =2:1_SPACING ? VR_SWITCH POWER * SWNODE_SW2PWR

TABLE_SPACING_ASSIGNMENT_ITEM

VR_SWITCH GND * SWNODE_SW2GND

DC-DC Control DC-DC Control

TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

VR_CTL_ISO * =3:1_SPACING ? VR_CTL * * VR_CTL_ISO

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

VR_VID_ISO * =4X_DIELECTRIC ? VR_VID * * VR_VID_ISO

VDDQ S3 (1.35V)/VTT S0
Physical Spacing Voltage DIDT NO_TEST

Input Bus
I43 POWER POWER 5V REG_V5IN_U7300 63

B Local Ground
B
I44 GND GND 0V AGND_VDDQS3 63

VDDQ S3
I45 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_PHASE_VDDQS3 63

I47 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_PHASE_VDDQS3_L 63

I46 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_BOOT_VDDQS3 63

I48 VR_DIDT_PHY VR_SWITCH 12V TRUE TRUE REG_BOOT_VDDQS3_RC 63

I49 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_UGATE_VDDQS3 63

I50 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_UGATE_VDDQS3_R 63

I52 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_LGATE_VDDQS3 63

I51 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_SNUBBER_VDDQS3 63

I53 VR_CTL_PHY VR_CTL REG_VDDQS3_VDDQSNS 63

I55 VR_CTL_PHY VR_CTL REG_VDDQS3_VREF 63

I56 VR_CTL_PHY VR_CTL REG_VDDQS3_REFIN 63

I57 VR_CTL_PHY VR_CTL REG_VDDQS3_MODE 63

I58 VR_CTL_PHY VR_CTL REG_VDDQS3_TRIP 63

I59 VR_CTL_PHY VR_CTL LDO_DDRVTTS0_SNS 63

I61 VR_CTL_PHY VR_CTL REG_VDDQS3_VTTREF 63

Output Bus
POWER POWER 1.35V PPVDDQ_S3 70

A I60

I62 POWER_DDR POWER_DDR 0.675V PPDDRVTT_S0 70

SYNC_MASTER=J16_NICK SYNC_DATE=01/10/2013 A
PAGE TITLE
FET Switched
POWER POWER 1.35V PPVDDQ_S0 70
VReg Constraints
I63 DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

Sensed REVISION
PPVDDQ_S3_DDR R
I64 POWER POWER 1.35V 70
12.4.0
I67 POWER POWER 1.35V PPVDDQ_S0_CPU 70
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
118 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 82 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCC Phases CPU VCC Controller
Electrical Contraint Set Physical Spacing Voltage DIDT NO_TEST Electrical Contraint Set Physical Spacing Voltage DIDT NO_TEST

Input Bus ISL6372

I836 POWER POWER 12V PP12V_S0_CPUVCC_FLT 61 62

I1136 POWER POWER 5V REG_VCC_U7000 61

I1020 VR_CTL_PHY VR_CTL REG_CPUVCC_DVC 61

I1022 VR_CTL_PHY VR_CTL CPUVCC_DVC_RC 61

Local Ground
I1021 VR_CTL_PHY VR_CTL CPUVCC_FB_RC_2 61
I1264 GND GND 0V AGND_CPU 61 62 71
I1027 VR_CTL_PHY VR_CTL REG_CPUVCC_COMP 61

VR_CTL_PHY VR_CTL CPUVCC_COMP_RC 61

D Phase 1
I1026

I1028 VR_CTL_PHY VR_CTL REG_CPUVCC_FB 61 D

I1029 VR_CTL_PHY VR_CTL CPUVCC_FB_RC 61

I1030 VR_CTL_PHY VR_CTL CPUVCC_FB_R_1 61

I883 VR_CTL_PHY VR_CTL REG_THWN_1 62 I1031 VR_CTL_PHY VR_CTL CPUVCC_FB_R_2 61

I884 VR_CTL_PHY VR_CTL REG_PWM_CPUVCC_1 61 62 I1033 VR_CTL_PHY VR_CTL CPUVCC_PSICOMP_RC 61

I885 VR_CTL_PHY VR_CTL REG_PWM_CPUVCC_1_R 61 I1041 VR_CTL_PHY VR_CTL REG_CPUVCC_PSICOMP 61

I1042 VR_CTL_PHY VR_CTL REG_CPUVCC_HFCOMP 61

I887 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_PHASE_CPUVCC_1 62

I1265 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_PHASE_CPUVCC1 62 I1039 VSNS_CPU_CORE SNS_DIFF_PHY SENSE CPU_VCCSENSE_P 8 61

I888 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_BOOT_CPUVCC_1 62 I1040 VSNS_CPU_CORE SNS_DIFF_PHY SENSE CPU_VCCSENSE_N 9 61

I890 VR_DIDT_PHY VR_SWITCH 12V TRUE TRUE REG_BOOT_CPUVCC_1_RC 62 I1034 SNS_DIFF_PHY SENSE CPU_VCCSENSE_R_P 61

I1036 SNS_DIFF_PHY SENSE CPU_VCCSENSE_R_N 61

I892 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_SNUBBER_CPUVCC_1 62 I1038 SNS_DIFF_PHY SENSE 1.8V SNS_VCC_XW_P 61

I1037 SNS_DIFF_PHY SENSE 0V SNS_VCC_XW_N 61

I893 POWER POWER 1.8V PPCPUVCC_S0_SENSE_1 62
I1032 SENSE REG_CPUVCC_VSEN 61

I894 ISNS_CPU_CORE SNS_DIFF_PHY SENSE REG_ISENVCC_1_P 61 62 I1035 SENSE REG_CPUVCC_RGND 61

I895 ISNS_CPU_CORE SNS_DIFF_PHY SENSE REG_ISENVCC_1_N 62 I1043 SENSE REG_CPUVCC_VIN 61

I896 SENSE REG_ISENVCC_1_NR 61 62

I1045 VR_CTL_PHY VR_CTL REG_CPUVCC_IMON 48 61

I1046 VR_CTL_PHY VR_CTL CPUVCC_IMON_R 61

Phase 2
I1050 VR_CTL_PHY VR_CTL REG_CPUVCC_TM 61

I1054 VR_CTL_PHY VR_CTL REG_CPUVCC_IMX 61

I1056 VR_CTL_PHY VR_CTL REG_CPUVCC_NPSI 61

I1138 VR_CTL_PHY VR_CTL REG_THWN_2 62
I1055 VR_CTL_PHY VR_CTL REG_CPUVCC_FDVID 61
I1140 VR_CTL_PHY VR_CTL REG_PWM_CPUVCC_2 61 62
I1051 VR_CTL_PHY VR_CTL REG_CPUVCC_TMX 61
I1141 VR_CTL_PHY VR_CTL REG_PWM_CPUVCC_2_R 61
I1052 VR_CTL_PHY VR_CTL REG_CPUVCC_MEMVRSEL 61

I1142 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_PHASE_CPUVCC_2 62

C I1266 VR_DIDT_PHY
VR_DIDT_PHY
VR_SWITCH
VR_SWITCH
12V
12V
TRUE
TRUE
REG_PHASE_CPUVCC2
REG_BOOT_CPUVCC_2
62

62
I1060

CPU_VIDSCLK
VR_CTL_PHY

VR_VID_PHY
VR_CTL

VR_VID
REG_CPUVCC_RSET

CPU_VIDSCLK
61

8 61
C
I1143 I1063

I1145 VR_DIDT_PHY VR_SWITCH 12V TRUE TRUE REG_BOOT_CPUVCC_2_RC 62 I1062 VR_VID_PHY VR_VID CPU_VIDSCLK_R 8

I1061 CPU_VIDALERT_L VR_VID_PHY VR_VID CPU_VIDALERT_L 8 61

I1146 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_SNUBBER_CPUVCC_2 62 I1066 VR_VID_PHY VR_VID CPU_VIDALERT_R_L 8

I1065 CPU_VIDSOUT VR_VID_PHY VR_VID CPU_VIDSOUT 8 61

I1149 POWER POWER 1.8V PPCPUVCC_S0_SENSE_2 62
I1064 VR_VID_PHY VR_VID CPU_VIDSOUT_R 8

I1148 ISNS_CPU_CORE SNS_DIFF_PHY SENSE REG_ISENVCC_2_P 61 62

I1151 ISNS_CPU_CORE SNS_DIFF_PHY SENSE REG_ISENVCC_2_N 62 Output Bus

I1150 SENSE REG_ISENVCC_2_NR 61 62 I1068 POWER POWER 1.8V PPCPUVCC_S0_CPU 70

Phase 3

I1152 VR_CTL_PHY VR_CTL REG_THWN_3 62

I1156 VR_CTL_PHY VR_CTL REG_PWM_CPUVCC_3 61 62

I1155 VR_CTL_PHY VR_CTL REG_PWM_CPUVCC_3_R 61

I1158 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_PHASE_CPUVCC_3 62

I1267 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_PHASE_CPUVCC3 62

I1157 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_BOOT_CPUVCC_3 62

I1159 VR_DIDT_PHY VR_SWITCH 12V TRUE TRUE REG_BOOT_CPUVCC_3_RC 62

I1162 VR_CTL_PHY VR_SWITCH 12V TRUE REG_SNUBBER_CPUVCC_3 62

I1163 POWER POWER 1.8V PPCPUVCC_S0_SENSE_3 62

B I1164 ISNS_CPU_CORE SNS_DIFF_PHY SENSE REG_ISENVCC_3_P 61 62 B

I1165 ISNS_CPU_CORE SNS_DIFF_PHY SENSE REG_ISENVCC_3_N 62

I1166 SENSE REG_ISENVCC_3_NR 61 62

A SYNC_MASTER=J16_ROSSANA SYNC_DATE=12/14/2012 A
PAGE TITLE

CPU VReg Constraints

DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

12V HDD S0
Physical Spacing Voltage DIDT NO_TEST Physical Spacing Voltage DIDT NO_TEST
Input Bus
FET Switched
I1449 POWER POWER 12V PP12V_ACDC 70
I1392 POWER POWER 5V PPHDD_S0 70

FET Switched
Sensed
PP12V_S5
D
I1448

I1453
POWER
POWER
POWER
POWER
12V
12V PP12V_S0
70

70
I1460 POWER POWER 5V PP5V_S0_HDD 70 D
Sensed
I1451 POWER POWER 12V PP12V_G3H 70

1V5 S0
Physical Spacing Voltage DIDT NO_TEST
3.42V G3H OUTPUT BUS
I1477 POWER POWER 1.5V PP1V5_S0 70
Physical Spacing Voltage DIDT NO_TEST
I1481 VR_CTL_PHY VR_CTL REG_P1V5S0_SS 64
3.42V G3H
I1482 VR_CTL_PHY VR_CTL REG_P1V5S0_ISET 64
I1443 POWER VR_SWITCH 12V TRUE P3V42G3H_BOOST 60
I1483 VR_CTL_PHY VR_CTL REG_P1V5S0_ADJ 64
I1447 POWER VR_SWITCH 12V TRUE P3V42G3H_SW 60

I1444 VR_CTL_PHY VR_CTL P3V42G3H_FB 60

I1445 VR_CTL_PHY VR_CTL P3V42G3H_SHDN_L 60

Output Bus
I1446 POWER POWER 3.425V PP3V42_G3H 70 Ground/Common
Physical Spacing Voltage DIDT NO_TEST

Common
3.3V G3 I1390 GND GND 0V GND

Physical Spacing Voltage DIDT NO_TEST

C I1476 POWER POWER 3.3V PP3V3_G3 70
C

3.3V S5/5V S4
Physical Spacing Voltage DIDT NO_TEST

Input Bus
I843 POWER POWER 12V REG_VIN_U7600 65

I1254 POWER POWER 5V REG_VCC1_U7600 65

I1255 POWER POWER 5V REG_VCC2_U7600 65

3.3V S5
I849 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_PHASE_P3V3S5 65

I847 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_BOOT_P3V3S5 65

I851 VR_DIDT_PHY VR_SWITCH 12V TRUE TRUE REG_BOOT_P3V3S5_RC 65

I848 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_UGATE_P3V3S5 65

I850 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_LGATE_P3V3S5 65

I852 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_SNUBBER_P3V3S5 65

I1071 VR_CTL_PHY VR_CTL REG_P3V3S5_ISEN 65

I1072 VR_CTL_PHY VR_CTL REG_P3V3S5_OCSET 65

I1136 VR_CTL_PHY VR_CTL REG_P3V3S5_FSET 65

B I1082 VR_CTL_PHY
VR_CTL_PHY
VR_CTL
VR_CTL
REG_P3V3S5_VOUT
REG_P3V3S5_VOUT_R
65

65
B
I1078

I1077 VR_CTL_PHY VR_CTL REG_P3V3S5_FB 65

5V S3
I1137 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_PHASE_P5VS4 65

I1138 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_BOOT_P5VS4 65

I1139 VR_DIDT_PHY VR_SWITCH 12V TRUE TRUE REG_BOOT_P5VS4_RC 65

I1140 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_UGATE_P5VS4 65

I1141 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_LGATE_P5VS4 65

I1143 VR_DIDT_PHY VR_SWITCH 12V TRUE REG_SNUBBER_P5VS4 65

I1142 VR_CTL_PHY VR_CTL REG_P5VS4_ISEN 65

I1144 VR_CTL_PHY VR_CTL REG_P5VS4_OCSET 65

I1145 VR_CTL_PHY VR_CTL REG_P5VS4_FSET 65

I1146 VR_CTL_PHY VR_CTL REG_P5VS4_VOUT 65

I1148 VR_CTL_PHY VR_CTL REG_P5VS4_VOUT_R 65

I1147 VR_CTL_PHY VR_CTL REG_P5VS4_FB 65

Output Bus
I1151 POWER POWER 5V PP5V_S5 70

I1153 POWER POWER 5V PP5V_S4 70

I1149 POWER POWER 3.3V PP3V3_S5 70

FET Switched
POWER POWER 5V PP5V_S0 70

A I1236

I1218 POWER POWER 3.3V PP3V3_S4 70

SYNC_MASTER=J16_ROSSANA SYNC_DATE=12/20/2012 A
I1233 POWER POWER 3.3V PP3V3_S0 70 PAGE TITLE
I1452 POWER
POWER
POWER
POWER
3.3V
3.3V
PP3V3_S0_SSD
PP3V3_ENET
70

70
Platform VReg Constraints
I1219 DRAWING NUMBER SIZE
I1382 POWER POWER 3.3V PP3V3_TBTLC 70
051-0164 D
Apple Inc. REVISION
Sensed R

POWER POWER 3.3V PPSSD_S0 70

12.4.0
I1454
PP3V3_S4_AP
NOTICE OF PROPRIETARY PROPERTY: BRANCH
I1475 POWER POWER 3.3V 70
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
120 OF 123
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 84 OF 86
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Thunderbolt TBT IC Net Properties TBT/DP Net Properties

Thunderbolt-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD
Electrical Contraint Set Physical Spacing Electrical Contraint Set Physical Spacing
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DP_85D DISPLAYPORT DP_TBTSNK0_ML_C_P<3..0> 26 71
ON LAYER? I511
Port A
TABLE_PHYSICAL_RULE_ITEM

I513 DP_85D DISPLAYPORT DP_TBTSNK0_ML_C_N<3..0> 26 71

TBT_I2C_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD I541 TBT_A_R2D1 TBTDP_90D TBTDP TBT_A_R2D_C_P<1> 26 29
I512 DP_TBTSNK0_ML DP_85D DISPLAYPORT DP_TBTSNK0_ML_P<3..0> 26
TABLE_PHYSICAL_RULE_ITEM

I542 TBT_A_R2D1 TBTDP_90D TBTDP TBT_A_R2D_C_N<1> 26 29

TBT_SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD I514 DP_TBTSNK0_ML DP_85D DISPLAYPORT DP_TBTSNK0_ML_N<3..0> 26
I689 TBT_A_R2D0 TBTDP_90D TBTDP TBT_A_R2D_C_P<0> 26 29
TABLE_PHYSICAL_RULE_ITEM

I516 DP_85D DISPLAYPORT DP_TBTSNK0_AUXCH_C_P 26 71

TBTDP_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF I688 TBT_A_R2D0 TBTDP_90D TBTDP TBT_A_R2D_C_N<0> 26 29
I515 DP_85D DISPLAYPORT DP_TBTSNK0_AUXCH_C_N 26 71
I544 TBTDP_90D TBTDP TBT_A_R2D_P<1..0> 29
DP_TBTSNK0_AUX DP_85D DISPLAYPORT DP_TBTSNK0_AUXCH_P 26

D
I517

I518 DP_TBTSNK0_AUX DP_85D DISPLAYPORT DP_TBTSNK0_AUXCH_N 26

I543
I595 DP_TBTPA_ML1
TBTDP_90D
DP_85D
TBTDP
DISPLAYPORT
TBT_A_R2D_N<1..0>
DP_TBTPA_ML_C_P<1>
29

26 29
D
Thunderbolt-specific Spacing Definitions I519 DP_85D DISPLAYPORT DP_TBTSNK1_ML_C_P<3..0> 26 71 I596 DP_TBTPA_ML1 DP_85D DISPLAYPORT DP_TBTPA_ML_C_N<1> 26 29
TABLE_SPACING_RULE_HEAD

I521 DP_85D DISPLAYPORT DP_TBTSNK1_ML_C_N<3..0> 26 71 I680 DP_TBTPA_ML3 DP_85D DISPLAYPORT DP_TBTPA_ML_C_P<3> 26 29

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
I520 DP_TBTSNK1_ML DP_85D DISPLAYPORT DP_TBTSNK1_ML_P<3..0> 26 I681 DP_TBTPA_ML3 DP_85D DISPLAYPORT DP_TBTPA_ML_C_N<3> 26 29

TBT_I2C * =2x_DIELECTRIC ? I523 DP_TBTSNK1_ML DP_85D DISPLAYPORT DP_TBTSNK1_ML_N<3..0> 26 I545 DP_85D DISPLAYPORT DP_TBTPA_ML_P<1> 29
TABLE_SPACING_RULE_ITEM

I522 DP_85D DISPLAYPORT DP_TBTSNK1_AUXCH_C_P 26 71 I547 DP_85D DISPLAYPORT DP_TBTPA_ML_N<1> 29

TBT_SPI * =2x_DIELECTRIC ?
TABLE_SPACING_RULE_ITEM
I524 DP_85D DISPLAYPORT DP_TBTSNK1_AUXCH_C_N 26 71 I678 DP_85D DISPLAYPORT DP_TBTPA_ML_P<3> 29

TBTDP * =5x_DIELECTRIC ? I526 DP_TBTSNK1_AUX DP_85D DISPLAYPORT DP_TBTSNK1_AUXCH_P 26 I679 DP_85D DISPLAYPORT DP_TBTPA_ML_N<3> 29
TABLE_SPACING_RULE_ITEM

I525 DP_TBTSNK1_AUX DP_85D DISPLAYPORT DP_TBTSNK1_AUXCH_N 26

TBTDP TOP,BOTTOM =7x_DIELECTRIC ? I546 DP_A_LSX DP_85D DISPLAYPORT DP_A_LSX_ML_P<1> 29

I548 DP_A_LSX DP_85D DISPLAYPORT DP_A_LSX_ML_N<1> 29

SOURCE: Bill Cornelius’s T29 Routing Notes I603 DP_INTPNL_TBT_ML_MUX DP_85D DISPLAYPORT DP_TBTSRC_ML_P<3..0> 41 I549 TBTDP_90D TBTDP TBT_A_D2R_C_P<1..0> 29

I604 DP_INTPNL_TBT_ML_MUX DP_85D DISPLAYPORT DP_TBTSRC_ML_N<3..0> 41 I550 TBTDP_90D TBTDP TBT_A_D2R_C_N<1..0> 29

I686 DP_INTPNL_TBT_ML_MUX DP_85D DISPLAYPORT DP_TBTSRC_ML_C_P<3..0> 41 I564 TBT_A_D2R1 TBTDP_90D TBTDP TBT_A_D2R_P<1> 26 29

I687 DP_INTPNL_TBT_ML_MUX DP_85D DISPLAYPORT DP_TBTSRC_ML_C_N<3..0> 41 I563 TBT_A_D2R1 TBTDP_90D TBTDP TBT_A_D2R_N<1> 26 29
*
DisplayPort I529 DP_INTPNL_TBT_AUX_MUX DP_85D DISPLAYPORT DP_TBTSRC_AUXCH_P 41 I675 TBT_A_D2R0 TBTDP_90D TBTDP TBT_A_D2R_P<0> 26 29

I530 DP_INTPNL_TBT_AUX_MUX DP_85D DISPLAYPORT DP_TBTSRC_AUXCH_N 41 I674 TBT_A_D2R0 TBTDP_90D TBTDP TBT_A_D2R_N<0> 26 29
DP-specific Physical Rules DP_TBTSRC_AUX_C_P DP_TBTPA_AUXCH_C_P
TABLE_PHYSICAL_RULE_HEAD
I601 DP_85D DISPLAYPORT 41 I599 TBT_A_AUXCH DP_85D DISPLAYPORT 26 29

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DP_85D DISPLAYPORT DP_TBTSRC_AUX_C_N 41 TBT_A_AUXCH DP_85D DISPLAYPORT DP_TBTPA_AUXCH_C_N 26 29
ON LAYER? I602 I600
TABLE_PHYSICAL_RULE_ITEM

I565 DP_85D DISPLAYPORT DP_TBTPA_AUXCH_P 29

DP_85D * =85_OHM_DIFF =85_OHM_DIFF 0.08MM =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
I566 DP_85D DISPLAYPORT DP_TBTPA_AUXCH_N 29

I648 DP_A_AUXCH_DDC DP_85D DISPLAYPORT DP_A_AUXCH_DDC_P 29

I531 TBT_I2C_55S TBT_I2C I2C_TBTRTR_SCL 26
DP-specific Spacing Definitions I2C_TBTRTR_SDA I649 DP_A_AUXCH_DDC DP_85D DISPLAYPORT DP_A_AUXCH_DDC_N 29
I532 TBT_I2C_55S TBT_I2C 26
TABLE_SPACING_RULE_HEAD

I650 TBTDP_90D TBTDP TBT_A_D2R1_AUXDDC_P 29

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
I651 TBTDP_90D TBTDP TBT_A_D2R1_AUXDDC_N 29
TABLE_SPACING_RULE_ITEM

I533 TBT_SPI_CLK TBT_SPI_55S TBT_SPI TBT_SPI_CLK 26

DISPLAYPORT * =3:1_SPACING ? TBT_SPI_MOSI
I534 TBT_SPI_MOSI TBT_SPI_55S TBT_SPI 26

C Pairs should be within 100 mils of clock length.

I538 TBT_SPI_MISO
TBT_SPI_CS_L
TBT_SPI_55S
TBT_SPI_55S
TBT_SPI
TBT_SPI
TBT_SPI_MISO
TBT_SPI_CS_L
26

26
Port B
I652 TBT_B_R2D1 TBTDP_90D TBTDP TBT_B_R2D_C_P<1> 26 30
C
I535
I653 TBT_B_R2D1 TBTDP_90D TBTDP TBT_B_R2D_C_N<1> 26 30
Max length of DisplayPort traces: 12 inches
I690 TBT_B_R2D0 TBTDP_90D TBTDP TBT_B_R2D_C_P<0> 26 30

DisplayPort intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps. I691 TBT_B_R2D0 TBTDP_90D TBTDP TBT_B_R2D_C_N<0> 26 30

DisplayPort AUX channel intra-pair matching should be 5 ps. No relationship to other signals. I655 TBTDP_90D TBTDP TBT_B_R2D_P<1..0> 30

I654 TBTDP_90D TBTDP TBT_B_R2D_N<1..0> 30

I657 DP_TBTPB_ML1 DP_85D DISPLAYPORT DP_TBTPB_ML_C_P<1> 26 30

I658 DP_TBTPB_ML1 DP_85D DISPLAYPORT DP_TBTPB_ML_C_N<1> 26 30

*: Only used on hosts supporting T29 video-in I685 DP_TBTPB_ML3 DP_85D DISPLAYPORT DP_TBTPB_ML_C_P<3> 26 30

I684 DP_TBTPB_ML3 DP_85D DISPLAYPORT DP_TBTPB_ML_C_N<3> 26 30

I683 DP_85D DISPLAYPORT DP_TBTPB_ML_P<1> 30

DisplayPort I682 DP_85D DISPLAYPORT DP_TBTPB_ML_N<1> 30

I656 DP_85D DISPLAYPORT DP_TBTPB_ML_P<3> 30

Electrical Contraint Set Physical Spacing I660 DP_85D DISPLAYPORT DP_TBTPB_ML_N<3> 30

I659 DP_B_LSX DP_85D DISPLAYPORT DP_B_LSX_ML_P<1> 30

Graphics Source
I662 DP_B_LSX DP_85D DISPLAYPORT DP_B_LSX_ML_N<1> 30
I642 DP_INTPNL_EG_ML_MUX DP_85D DISPLAYPORT DP_INT_ML_P<1..0> 41 71

I643 DP_INTPNL_EG_ML_MUX DP_85D DISPLAYPORT DP_INT_ML_N<1..0> 41 71 I661 TBTDP_90D TBTDP TBT_B_D2R_C_P<1..0> 30

I644 DP_INTPNL_EG_AUX_MUX DP_85D DISPLAYPORT DP_INT_AUX_P 41 71 I663 TBTDP_90D TBTDP TBT_B_D2R_C_N<1..0> 30

I645 DP_INTPNL_EG_AUX_MUX DP_85D DISPLAYPORT DP_INT_AUX_N 41 71 I665 TBT_B_D2R1 TBTDP_90D TBTDP TBT_B_D2R_P<1> 26 30

I646 DP_85D DISPLAYPORT DP_INT_AUX_C_P 41 I664 TBT_B_D2R1 TBTDP_90D TBTDP TBT_B_D2R_N<1> 26 30

I647 DP_85D DISPLAYPORT DP_INT_AUX_C_N 41 I676 TBT_B_D2R0 TBTDP_90D TBTDP TBT_B_D2R_P<0> 26 30

I677 TBT_B_D2R0 TBTDP_90D TBTDP TBT_B_D2R_N<0> 26 30

Internal Panel I666 TBT_B_AUXCH DP_85D DISPLAYPORT DP_TBTPB_AUXCH_C_P 26 30

I605 DP_85D DISPLAYPORT DP_INTPNL_ML_C_P<3..0> 41 I667 TBT_B_AUXCH DP_85D DISPLAYPORT DP_TBTPB_AUXCH_C_N 26 30

I606 DP_85D DISPLAYPORT DP_INTPNL_ML_C_N<3..0> 41 I669 DP_85D DISPLAYPORT DP_TBTPB_AUXCH_P 30

B I607

I608
DP_INTPNL_ML_CONN
DP_INTPNL_ML_CONN
DP_85D
DP_85D
DISPLAYPORT
DISPLAYPORT
DP_INTPNL_ML_P<3..0>
DP_INTPNL_ML_N<3..0>
40 41

40 41
I670

I668 DP_B_AUXCH_DDC
DP_85D
DP_85D
DISPLAYPORT
DISPLAYPORT
DP_TBTPB_AUXCH_N
DP_B_AUXCH_DDC_P
30

30
B
I609 DP_INTPNL_AUX_CONN DP_85D DISPLAYPORT DP_INTPNL_AUX_P 40 41 I672 DP_B_AUXCH_DDC DP_85D DISPLAYPORT DP_B_AUXCH_DDC_N 30

I610 DP_INTPNL_AUX_CONN DP_85D DISPLAYPORT DP_INTPNL_AUX_N 40 41 I671 TBTDP_90D TBTDP TBT_B_D2R1_AUXDDC_P 30

I673 TBTDP_90D TBTDP TBT_B_D2R1_AUXDDC_N 30

Internal DP SPDIF
I611 HDA DP_INT_SPDIF_AUDIO 40 52

A SYNC_MASTER=J16_MLB SYNC_DATE=12/03/2012 A
PAGE TITLE

TBT/DP Constraints
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

Backlight Controller Is it chel’oh or sel’oh?

BLC-specific Physical Rules
TABLE_PHYSICAL_RULE_HEAD
Physical Spacing Voltage DIDT NO_TEST
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? Input Bus
TABLE_PHYSICAL_RULE_ITEM

POWER POWER 12V PP12V_BKLT_SNS 66

BLC_P6MM * Y 0.600 MM 0.100 MM 3.0 MM =STANDARD =STANDARD I802
TABLE_PHYSICAL_RULE_ITEM
I749 POWER POWER 12V PP12V_BKLT_FUSED 66
BLC_P3MM * Y 0.300 MM 0.100 MM 3.0 MM =STANDARD =STANDARD I750 POWER POWER 12V PP12V_S0_BKLT_FILT 66

I772 POWER POWER 12V PP12V_S0_BKLT_PWR 66

Physical Net Type to Rule Map I794 POWER POWER 12V PP12V_S0_BKLT_PWR_R 66

PP5V_S0_BKLT_R
D NET_PHYSICAL_TYPE AREA_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD

PHYSICAL_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I795

I796
POWER
POWER
POWER
POWER
5V
3.3V PP3V3_S0_BKLT_VDDIO_R
66

66
D
POWER_BLC * BLC_P6MM Local Ground
TABLE_PHYSICAL_ASSIGNMENT_ITEM

POWER_BLC_RET * BLC_P3MM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I751 BLC_CTL_PHY BLC_PHASE 0V PGND_BKLT 66

BLC_CTL_PHY * BLC_P3MM I799 BLC_CTL_PHY BLC_PHASE 0V DGND_BKLT 66

I800 BLC_CTL_PHY BLC_PHASE 0V LGND_BKLT 66

Backlight
BLC-specific Spacing Definitions Constraints I752 POWER_BLC BLC_PHASE 80V TRUE BKLT_PHASE 66
BLC High Voltage Output BLC High Voltage Output I753 BLC_CTL_PHY BLC_PHASE 80V TRUE BKLT_GATE 66
TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I754 BLC_CTL_PHY BLC_PHASE 80V TRUE BKLT_GATE_R 66

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
I755 BLC_CTL_PHY BLC_PHASE 80V TRUE BKLT_SNUBBER 66
BLC_HV_ISO * 0.45mm 1000 BLC_HV BLC_CTL * BLC_CTL_ISO BLC_CTL_PHY BLC_PHASE 12V TRUE BKLT_SW_R 66
I757
TABLE_SPACING_ASSIGNMENT_ITEM

BLC_HV BLC_HV * BLC_CTL_ISO

TABLE_SPACING_ASSIGNMENT_ITEM

I759 BLC_CTL_PHY BLC_CTL BKLT_ISET 66

BLC_HV * * BLC_HV_ISO
I763 BLC_CTL_PHY BLC_CTL BKLT_FLT 66

I765 BLC_CTL_PHY BLC_CTL BKLT_FLT_RC 66

I797 SNS_DIFF_PHY SENSE BKLT_SW_P 66

SNS_DIFF_PHY SENSE BKLT_SW_N

BLC Baddies BLC Baddies I798 66

TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
I762 SENSE BKLT_FB 66
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
I801 BLC_HV 67V BKLT_FB_XW 66
PHASE_ISO * =8:1_SPACING 2000 BLC_PHASE * * PHASE_ISO BLC_HV 67V BKLT_FB_R 66
I764
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

PHASE_SW2SW * =1:1_SPACING ? BLC_PHASE BLC_PHASE * PHASE_SW2SW POWER_BLC_RET BLC_CTL BKLT_ISEN1 66

I776
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

PHASE_SW2PWR * =2:1_SPACING ? BLC_PHASE POWER * POWER_BLC_RET BLC_CTL BKLT_ISEN2 66

PHASE_SW2PWR I775
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
I778 POWER_BLC_RET BLC_CTL BKLT_ISEN3 66

C PHASE_SW2GND * =2:1_SPACING ? BLC_PHASE GND * PHASE_SW2GND

I777

I780
POWER_BLC_RET
POWER_BLC_RET
BLC_CTL
BLC_CTL
BKLT_ISEN4
BKLT_ISEN5
66

66
C
BLC Control BLC Control I779 POWER_BLC_RET BLC_CTL BKLT_ISEN6 66

TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I789 POWER_BLC_RET BLC_HV BKLT_ISEN1_R 66

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
I788 POWER_BLC_RET BLC_HV BKLT_ISEN2_R 66
BLC_CTL_ISO * =3:1_SPACING ? BLC_CTL * * BLC_CTL_ISO
I790 POWER_BLC_RET BLC_HV BKLT_ISEN3_R 66

I791 POWER_BLC_RET BLC_HV BKLT_ISEN4_R 66

I792 POWER_BLC_RET BLC_HV BKLT_ISEN5_R 66

I793 POWER_BLC_RET BLC_HV BKLT_ISEN6_R 66

I783 POWER_BLC_RET BLC_HV LED_RETURN_1 66

I782 POWER_BLC_RET BLC_HV LED_RETURN_2 66

I784 POWER_BLC_RET BLC_HV LED_RETURN_3 66

I785 POWER_BLC_RET BLC_HV LED_RETURN_4 66

I786 POWER_BLC_RET BLC_HV LED_RETURN_5 66

I787 POWER_BLC_RET BLC_HV LED_RETURN_6 66

Output Bus
I770 POWER_BLC BLC_HV 67V BKLT_BOOST 66

I773 POWER_BLC BLC_HV 67V BKLT_BOOST_1 66

I774 POWER_BLC BLC_HV 67V BKLT_BOOST_2 66

Cello Miscellaneous
B Electrical Contraint Set Physical Spacing
B
SPI
I564 SMB_PHY SMB BKLT_SCL 66

I563 SMB_PHY SMB BKLT_SDA 66

A SYNC_MASTER=J16_MLB SYNC_DATE=12/03/2012 A
PAGE TITLE

BLC Constraints
DRAWING NUMBER SIZE

Apple Inc. 051-0164 D

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