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M9 MLB DVT Resolved - Bak

This document contains the table of contents for a schematic design document. The table of contents lists 86 sections related to the design of a computer system, including sections on the CPU, memory, graphics processing unit, chipsets, interfaces, and power supplies. Dates are provided for some sections, and a revision history section is listed near the end, indicating this is a revised design document.

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0% found this document useful (0 votes)

320 views86 pages

M9 MLB DVT Resolved - Bak

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You are on page 1/ 86

8

REV

(.csa)

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Contents
Table of Contents
System Block Diagram
Power Block Diagram
BOM Configuration
Functional / ICT Test
Signal Aliases
CPU 1 OF 2-FSB
CPU 2 OF 2-PWR/GND
CPU Decoupling & VID
CPU MISC1-TEMP SENSOR
CPU ITP700FLEX DEBUG
NB CPU Interface
NB PEG / Video Interfaces
NB Misc Interfaces
NB DDR2 Interfaces
NB Power 1
NB Power 2
NB Grounds
NB (GM) Decoupling
NB Config Straps
SB: 1 OF 4
SB: 2 of 4
SB: 3 OF 4
SB: 4 OF 4
SB Decoupling
SB Misc
M1 SMBus Connections
DDR2 SO-DIMM Connector A
DDR2 SO-DIMM Connector B
Memory Active Termination
Memory Vtt Supply
DDR2 VRef
CLOCKS
Clock Termination
Mobile Clocking
PATA Connector
FireWire Link (TSB83AA22)
FireWire PHY (TSB83AA22)
ETHERNET CONTROLLER
Ethernet Connector
Yukon Power Control
FW PHY Power Supply
FireWire Port Power

Date

Sync
N/A

(.csa)

Page
TABLE_TABLEOFCONTENTS_HEAD

N/A
(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)
(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)
(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)
(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)
(11/11/2005)

TABLE_TABLEOFCONTENTS_ITEM

(M1_MLB)
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/08/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/08/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
01/04/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
(11/07/2006)

TABLE_TABLEOFCONTENTS_ITEM

(M1_MLB)
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
12/19/2005

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)
(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
02/10/2006

TABLE_TABLEOFCONTENTS_ITEM

M1_MLB
(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)
(11/03/2005)

TABLE_TABLEOFCONTENTS_ITEM

(M1_MLB)

TABLE_TABLEOFCONTENTS_ITEM

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ZONE

ECN

ENG
APPD

DESCRIPTION OF CHANGE
DATE

DVT

M9 MLB
3/3/2006

1
CK
APPD

Sully

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DATE

(6.0.0)

D
Date

Contents

Sync

FireWire Ports
Internal USB Connections
External USB Connector
Left I/O Board Connector
Current & Thermal Sensors
PCI-E Connections
SMC
SMC Support
LPC+ Debug Connector
Thermal Sensors
Current & Voltage Sensing
SPI BOOTROM
ALS Support
Fan Connectors
Sudden Motion Sensor (SMS)
TPM
IMVP6 CPU VCore Regulator
5V / 1.5V Power Supply
2.5V & 1.2V Regulators
1.8V Supply
3.3V / 1.05V Power Supplies
3.3V G3Hot Supply & Power Control
Power Aliases
DC-In & Battery Connectors
PBus Supply & Batt. Charger
ATI M56 PCI-E
GPU (M56) Core Supplies
ATI M56 Core Power
ATI M56 Frame Buffer I/F
GPU Straps
GDDR3 Frame Buffer A
GDDR3 Frame Buffer B
ATI M56 GPIO/DVO/Misc
ATI M56 Video Interfaces
Internal Display Connectors
External Display Connector
M9 Specific Connectors
LVDS Interface Pull-downs
Revision History
Napa Platform Constraints
More System Constraints
M1 Spacing & Physical Constraints
M1 Net Properties

(MASTER)

(MASTER)
02/10/2006

M1_MLB
02/10/2006

M1_MLB
(MASTER)

(MASTER)
(MASTER)

(MASTER)
02/10/2006

M1_MLB
02/10/2006

M1_MLB
01/05/2006

M1_MLB
02/10/2006

M1_MLB

02/10/2006

M1_MLB
02/08/2006

M1_MLB
02/10/2006

M1_MLB
12/19/2005

M1_MLB
(MASTER)

(MASTER)
12/19/2005

M1_LIO
02/10/2006

M1_MLB
02/10/2006

M1_MLB

02/10/2006

M1_MLB
01/09/2006

M1_MLB
11/18/2005

M1_MLB
(MASTER)

(MASTER)
12/19/2005

M1_MLB
(MASTER)

(MASTER)
02/10/2006

M1_MLB
02/10/2006

M1_MLB

TABLE_TABLEOFCONTENTS_ITEM

ALIASES RESOLVED
A

DIMENSIONS ARE IN MILLIMETERS

Apple Computer Inc.

METRIC

X.XX
DRAFTER

Schematic / PCB #s
PART NUMBER

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD

MFG APPD

QA APPD

DESIGNER

RELEASE

SCALE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

ANGLES

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

051-7023

SCHEM,SULLY,M9

SCH

CRITICAL

820-2023

PCBF,SULLY,FINAL,M9

PCB

CRITICAL

NOTICE OF PROPRIETARY PROPERTY

DESIGN CK

X.XXX

BOM OPTION

TITLE

DO NOT SCALE DRAWING

SCHEM,SULLY,M9
NONE

DRAWING

SIZE

TITLE=SULLY
ABBREV=DRAWING
LAST_MODIFIED=Fri Mar

3 17:59:45 2006

THIRD ANGLE PROJECTION

MATERIAL/FINISH
NOTED AS
APPLICABLE

DRAWING NUMBER

REV.

051-7023
SHT

06
OF

GDDR3
Frame Buffer
128MB/256MB
P.74-75

INVERTER
CONNECTOR

Core Duo
(Yonah)

CPU
THERMAL
SENSOR
P.10

ITP700FLEX
CPU Debug
Connector
P.11

479 BGA
P.7-9

P.78

D
J2800

LCD Panel

PWM

P.78,81

Dual-Channel LVDS
S-Video/Composite

DVI-I/DL Connector
w/TV-Out Support

FSB

ATI M56P
GPU

Lower Connector

PCIe x16

CH.A

945GM
NB

Dual-Channel TMDS

P.79

DDR2 SO-DIMM A

P.69-73,76-77

P.28
J2900

DDR2 SO-DIMM B

CH.B

DDR2 VTT

Upper Connector

& REGULATOR

1466UFCBGA
RJ45 (Ethernet)
Connector

ENET

Yukon Gig-E
Controller

P.40
1394a/b (FireWire)

P.44

P.41

BUFFER

P.32

TSB83AA22 FireWire

Controller
Port Power

PCIe x1
PCI

P.37-38
PHY Power

ICH7-M

P.42

USB

PCIe x1
PCIe x1

P.46
HDD/BT/IR
Connectors
P.80

P.30-31

DDR2 VREF

P.12-20

DMI x4

P.43
Right USB 2.0
Connector

Yukon Power

P.39

Connectors

P.29

SATA

Left I/O &

Audio Board
Connector

USB x2
USB

USB x2

Azalia (HD-Audio)
P.47

Camera
Connector
P.45

USB

Geyser KB /
TP Connector
P.45

USB

ODD
Connector
P.36

P.21-26

B
SMBus

PATA

Batt Chgr/
PBUS Supply
P.68

66MHZ
16BITS

LPC 33MHZ
BootROM
SB SMBus

Temperature
Sensors

SMC SMBus

SMC

SMBus x5

LPC
Debug
Connector

P.59

P.52

P.60-67,70

System Block Diagram

RT ALS

P.56

SYNC_MASTER=(MASTER)

SMS

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

P.58

Battery SMBus
Connector

Fan
Connectors

P.82

P.57

PWM/Tach

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

P.50-51

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

Analog
Sensors

SIZE

P.54

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

SCALE

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

P.27

P.48,53

TPM
H8S/2116

P.27

P.33-34

Power
Supplies

SPI

P.55

CK410 Clock
Controller

609 BGA

06
OF

U8000
ENABLE

J5500
LIO Flex
Connector

3.425
G3Hot
(LT3470)

PPDCIN_G3H
18.5V - 9V

Q7610
PP5V_S3
5.0V

PP3V42_G3H
3.425V
SMC_PM_G2_ENABLE
PM_SLP_S3_L

5V
1.5V

D
PM_SLP_S4_LS5V
Q7615

U7600

ENABLES
J8200
LIO Power
Connector

5V/1.5V
S5/S0

PPBUS_G3H_B
12.6V - 9V

(LTC3728)
PPBUS_G3H_A
12.6V - 9V

PM_SLP_S3_LS5V
Q7945
PP3V3_S3
3.3V

U7900
ENABLE

3.3V

ENABLES

PM_SLP_S4_LS5V

PP3V3_S5
3.3V

S5
(ISL6269)
PPVCORE_S0_CPU
?V

U7700
ENABLE

PGOOD

Q7720
RSMRST_PWRGD
PM_SLP_S3_L

2.5V
S3
(LTC3411)

U7950

VR_PWRGOOD_DELAY

PP2V5_S0
2.5V

PGOOD
1.05V
U7750

(ISL6269)

PM_SLP_S4_L

ENABLE
1.2V

ENABLE
IMVP_PWRGD_IN/ALL_SYS_PWRGD
PM_SLP_S3_L

PP1V8_S3
1.8V

PP1V2_S3
1.2V

PP1V2_S0
1.2V

(LTC3412)

U8500

PGOOD

ENABLE

PM_SLP_S3_LS5V_L

NC
GPU VCore
S0

PGOOD
NC

Q7770

PGOOD

U7800

PM_SLP_S3_LS5V_L

PP1V05_S0
1.05V

Connector

1.8V
S3
(ISL6269)

PP2V5_S3
2.5V

ENABLE

J5500
Inverter

PP1V5_S0
1.5V

NC
SMC_PM_G2_ENABLE

U7530
CPU VCore
S0
(ISL6262)
"IMVP6"
PGOOD

PP5V_S0
5.0V

PGOOD

IMVP_VR_ON
IMVP_PWRGD_IN

PP5V_S5
5.0V

PPVCORE_S0_GPU
1.2V - 1.0V

Q7947
PP3V3_S0
3.3V

(ISL6269)
PGOOD
PM_SLP_S3_L
NC

U3100

Q7845
0.9V (Vtt)
S0
(BD3533FVM)

Power Block Diagram

PM_SLP_S3_LS5V

ENABLE
PP0V9_S0
0.9V

SYNC_MASTER=(MASTER)

Q4565
PP1V8_S0
1.8V

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

PPBUS_S5_FWPORT

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

12.6V - 9V

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE COMPUTER INC.

PM_SLP_S3_LS5V_L

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

SHT
NONE

REV.

051-7023

SCALE

FWPWR_EN

DRAWING NUMBER

06
86

TABLE_BOMGROUP_HEAD

BOM NUMBER

BOM NAME

BOM OPTIONS

630-7404

PCBA,SULLY,2.0GHz,M9

VRAM_256SAM,M9_COMMON,CPU_2_0GHZ,EEE_UNZ

630-7406

PCBA,SULLY,2.16GHz,M9

VRAM_256SAM,M9_COMMON,CPU_2_16GHZ,EEE_UP1

TABLE_BOMGROUP_ITEM

PART NUMBER

DESCRIPTION

REFERENCE DES

CRITICAL

338S0270

QTY
1

IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

U4101

CRITICAL

BOM OPTION

338S0274

IC,SMC,HS8/2116

U5800

CRITICAL

SMC_BLANK

341S1876

IC,SMC,PRGRM,M9

U5800

CRITICAL

SMC_DEVEL

341S1876

IC,SMC,PRGRM,M9

U5800

CRITICAL

SMC_FINAL

341S1797

IC,EEPROM,SERIAL IIC,8KBIT,SO8

U4102

CRITICAL

335S0384

IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8

U6301

CRITICAL

BOOTROM_BLANK

341S1828

IC,EFI,BOOTROM DEVELOPMENT,M9

U6301

CRITICAL

BOOTROM_DEVEL

341S1829

IC,EFI,BOOTROM FINAL,M9

U6301

CRITICAL

BOOTROM_FINAL

353S1235

IC,CPU VOLTAGE REGULATOR,IMVP,TWO PHASE

U7530

CRITICAL

359S0101

IC,CY28445-5,CLOCK GEN,68PIN QFN

U3301

CRITICAL

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

IC, TPM, 28-PIN TSSOP

U6700

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

VRAM_128SAM

VRAM_128_SAMSUNG

TABLE_BOMGROUP_ITEM

VRAM_256SAM

GPU_MEM_256M,VRAM_256_SAMSUNG

VRAM_128HY

GPU_MEM_HYNIX,VRAM_128_HYNIX

VRAM_256HY

GPU_MEM_HYNIX,GPU_MEM_256M,VRAM_256_HYNIX

BOM GROUP

BOM OPTIONS

M9_COMMON

ALTERNATE,COMMON,M9_COMMON1,M9_COMMON2,M9_COMMON3,M9_COMMON4,M9_DEBUG

M9_COMMON1

ENET_LOM_DISABLE,ENETPWR_S3AC,GPUTHM_A_GPU,GPU_BB_CTL,HSTHMSNS_HAS,INVERTER_BUF,ONEWIRE_PU

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

PART NUMBER

BOM OPTION

TABLE_BOMGROUP_ITEM

341S1789

TABLE_BOMGROUP_ITEM

M9_COMMON2

KBDLED_HAS,MEMVREF_S3,MEMVTT_EN_PU,RTUSB_ESD,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU

M9_COMMON3

LVDS_PD,M56_REV_B24_LP,FW_B_BILINGUAL,FW_A_DS_ONLY,FW_PORT_FAULT_PU,FW_PLTRST_UNGATED

M9_COMMON4

LIO_TEMP,BOOTROM_DEVEL,SMC_DEVEL

M9_DEBUG

ITP,ITPCONN,LPCPLUS

TABLE_BOMGROUP_ITEM

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

337S3282

IC,CPU,479 BGA

U0700

CRITICAL

CPU_1_83GHZ

337S3267

IC,CPU,479 BGA

U0700

CRITICAL

CPU_2_0GHZ

337S3268

IC,CPU,479 BGA

U0700

CRITICAL

CPU_2_16GHZ

338S0269

IC,945GM,SOUTHBRIDGE

U1200

CRITICAL

343S0385

IC,SB,652BGA

U2100

CRITICAL

TABLE_BOMGROUP_ITEM

Bar Code Labels / EEE #s

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:UNZ]

CRITICAL

BOM OPTION
EEE_UNZ

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:UP0]

CRITICAL

EEE_UP0

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:UP1]

CRITICAL

EEE_UP1

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:UP2]

CRITICAL

EEE_UP2

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:UYU]

CRITICAL

EEE_UYU

DESCRIPTION

REFERENCE DES

CRITICAL

M9 Specific Aliases

Module Parts
PART NUMBER

QTY

64 63 61 60 54 47 43 41 5 4
78 70 68 66

BOM OPTION

338S0266

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

U8400

CRITICAL

M56_REV_B24_LL

338S0302

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

U8400

CRITICAL

M56_REV_B24_HL

68 67 66 65 4

50 37 4

PPBUS_G3H

PPDCIN_G3H

4 65 66 67 68

PPDCIN_G3H

4 65 66 67 68

SMC_RSTGATE_L

4 37 50

MAKE_BASE=TRUE

4 5 41 43 47 54 60 61 63 64 66
68 70 78

338S0309

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

U8400

CRITICAL

M56_REV_B24_LP

338S0315

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

U8400

CRITICAL

M56_REV_B26_LP

44 43 4

PPFW_PORTA_VP_UF

4 43 44

338S0316

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

U8400

CRITICAL

M56_REV_B26_P

44 43 4

PPFW_PORTB_VP_UF

4 43 44

333S0354

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

CRITICAL

VRAM_128_SAMSUNG

PP3V3_S0

333S0350

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

CRITICAL

VRAM_256_SAMSUNG

333S0358

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

CRITICAL

VRAM_128_HYNIX

333S0351

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

CRITICAL

VRAM_256_HYNIX

PART NUMBER

IS
ALTERNATE FOR
PART NUMBER

MAKE_BASE=TRUE
MAKE_BASE=TRUE

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

PP3V3_S0
PP3V3_S0

TABLE_ALT_HEAD

BOM OPTION

REF DES

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79
48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79
48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

50 48 27 10 4

SMBUS_SMC_B_S0_SCL

50 48 27 10 4

SMBUS_SMC_B_S0_SDA

4 10 27 48 50

PCI_AD<19>

=FW_PCI_IDSEL

4 10 27 48 50

COMMENTS:
37 22

MAKE_BASE=TRUE

TABLE_ALT_ITEM

338S0309

338S0266

M56_REV_B24_LL U8400

LP is alt to LL

338S0266

338S0309

M56_REV_B24_LP U8400

LL is alt to LP

56 54 52 47 42 36 31 25 5 4
80 79 78 70 67 66 65 61 60 57

TABLE_ALT_ITEM

PP5V_S0

PPBUS_S5_FW_FET

4 5 25 31 36 42 47 52 54 56 57
60 61 65 66 67 70 78 79 80

TABLE_ALT_ITEM

338S0315

338S0309

376S0448

376S0445

M56_REV_B24_LP U8400
ALL

B26_LP is alt to B24_LP

Vishay 2nd source

128S0083

128S0073

C2516

1.86 max alt to 1.9 max

128S0093

128S0092

ALL

Kemet is alt to Sanyo

128S0060

128S0094

ALL

Sanyo is alt to Panasonic

128S0095

128S0094

ALL

330uF,2V,6MOHM,D2

66 43 42 38 4

TABLE_ALT_ITEM

4 38 42 43 66

PPBUS_S5_FW_FET

4 38 42 43 66

PP3V3_FWPHY

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE

4 5 38 42 43 44

PP3V3_FWPHY

4 5 38 42 43 44

TABLE_ALT_ITEM

44 43 42 38 5 4

TABLE_ALT_ITEM

PP3V3_FWPHY

44 43 42 38 5 4

TABLE_ALT_ITEM

128S0081

128S0061

ALL

4 38 42 43 66

PPBUS_S5_FW_FET

TABLE_ALT_ITEM

PP3V3_FWPHY

4 5 38 42 43 44

PP3V3_FWPHY

4 5 38 42 43 44

C2 package is alt to C3

42 38 5 4

PP1V95_FWPHY

42 38 5 4

A
37 32 31 29 28 19 16 14 5 4
66 63 54

47 22 5 4

PP3V3_FWPHY

4 5 38 42 43 44

PP1V95_FWPHY

VOLTAGE=1.95V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE

4 5 38 42

PP1V95_FWPHY

4 5 38 42

PP1V8_S3

LT2USB_OC_L

MAKE_BASE=TRUE

BOM Configuration
SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

4 5 14 16 19 28 29 31 32 37 54
63 66

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
4 5 22 47

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

37 22 4

PCI_GNT3_L

4 22 37

37 26 22 4

PCI_REQ3_L

4 22 26 37

MAKE_BASE=TRUE
MAKE_BASE=TRUE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Functional Test Points

Power Supply NO_TESTs
NO_TEST

Power Nets

EXPOSED_VIA
IMVP6_RBIAS

TRUE

I179

P5VS5_RUNSS
P1V5S0_RUNSS

TRUE
TRUE

I178
61 65

I182
61 65

I183

TRUE
TRUE

P2V5S3_MODE
P2V5S3_SHDNRT

I184

I185

TRUE
TRUE

P1V2S3_RT
P1V2S3_RUNSS

41 62

TRUE
TRUE

P1V8S3_COMP
P1V8S3_FSET

I186
62

I187
I188

P3V3S5_COMP
P3V3S5_FSET

TRUE
TRUE

I189

I190
I191

I192
64

I193

TRUE
TRUE

P1V05S0_COMP
P1V05S0_FSET

TRUE

P3V42G3H_FB
GPUVCORE_COMP
GPUVCORE_FSET

TRUE
TRUE

GPUBBP_ADJ

TRUE

I194

I195
I197

TRUE
TRUE
TRUE

I198

I199
I201
7 12 86

I202
7 12 86

I203
7 12 86

I204
7 12 86

I205
7 12 86

I206
7 12 86

I207
7 12 86

I208
7 12 86

I209
7 12 86

I210
7 12 86

I211
7 12 86

I212
7 12 86

I213
7 12 86

I215
7 12 86

I214
7 12 86

EXPOSED_VIA property indicates that the net

should have a via with 10-mil soldermask
opening for use as engineering probe point.

I217
I219
I218
I221
I220
I222

Misc EXPOSED_VIA Nets

I223
I224

EXPOSED_VIA

I225

DMI_N2S_P<1..0>
DMI_N2S_N<1..0>
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66
62 65 66 69 76

FUNC_TEST

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE

PP5V_S0

TRUE
TRUE

FAN_LT_PWM
FAN_LT_TACH

TRUE
TRUE

FAN_RT_PWM
FAN_RT_TACH

66 67 70 78 79 80
4 5 25 31 36 42 47
I134
52 54 56 57 60 61 65

I135

5 8 9 13 16 17 19 24 25
47 65 66
63 65 66

57
57

LPC+ Debug Connector

39 62 66
5
70 78 79
48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
27 32 37 41 45 51 56 58 59 62
63 64 66 80
11 22 23 24 25 26 55 62
64 65 66 78
78 79 80
4 5 25 31 36 42 47 52 54
56 57 60 61 65 66 67 70
5 45 51 61 66 80
5 25 46 51 61 63 64 65 66
67 70
4 5 41 43 47 54 60 61 63
64 66 68 70 78

IMVP_VR_ON
IMVP_DPRSLPVR
PM_SLP_S3_L
PM_SLP_S3BATT
PM_SLP_S4_L
PM_SLP_S5_L
P1V5P1V05S0_PGOOD
CPU_DPRSTP_L
IMVP6_VID<6..0>
FSB_CLK_CPU_N
FSB_CLK_CPU_P
PLT_RST_L
PLT_RST_L
PEG_RESET_L
SMC_LRESET_L
TPM_LRESET_L
CPU_STPCLK_L
FSB_CLK_NB_P
FSB_CLK_NB_N
CLK_NB_OE_L
NB_CLK100M_GCLKIN_P
NB_CLK100M_GCLKIN_N
GND
GND
GND
GND
CPU_THERMTRIP_R
TP_SB_SUS_CLK

50 60
60 86
23 32 39 43 50 54 64 65
41
5 23 41 46 47 50 63 65
23 50 51
60 64 65
7 21 60
9 60
7 34
7 34
5 14 22 26
5 14 22 26
26 69

26 59
7 21 86

PP3V42_G3H
PP5V_S0

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

LPC_AD<0>
LPC_AD<1>
LPC_FRAME_L
PM_CLKRUN_L
BOOT_LPC_SPI_L
SMC_TMS
DEBUG_RST_L
SMC_TRST_L
SMC_TDO
SMC_MD1
SMC_TX_L
FWH_INIT_L
PCI_CLK_PORT80_LPC
LPC_AD<2>
LPC_AD<3>
INT_SERIRQ
PM_SUS_STAT_L
SMC_TDI
SMC_TCK
SMC_RST_L
SMC_NMI
SMC_RX_L
SV_SET_UP

21 50 52 59
21 50 52 59
21 50 52 59
23 50 52 59

I165
22 50 52

I166
50 51 52
26 52
50 52
50 51 52
50 52
50 51 52
21 50 51 52

I138
34 52
21 50 52 59
21 50 52 59
23 50 52 59
23 50 51 52 59
50 51 52
50 51 52
50 51 52
50 52
50 51 52
23 52

Resistor Calibration

12 34

FUNC_TEST

12 34
14 33

I142

14 34

I141

14 34

I140
I139
I143
I164
21

PP5V_S0
PP1V8_S3
PP1V05_S0
PPVCORE_S0_CPU
PPVCORE_S0_GPU
ISENSE_CAL_EN
GND

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

66 67 70 78 79 80
4 5 25 31 36 42 47
52 54 56 57 60 61 65
64 66
5 7 8 9 11 12 13 16
17 19 21 24 25 34 54
8 9 54 60 66
54 66 70 71 76
50 54

Request for at least 2 GND TPs per resistor

6 23

MAC-1 TPs

FUNC_TEST
I168

FUNC_TEST

I167

I228
I229
I230
I231
I232
I233
I235
I234
I236
I237
I238
I239
I240
I241
I242
I243
I244
I245
I246
I247
I248
I250
I249
I251
I253

I252
I254
I256
I255
I257
I258
I259
I260
I261
I263
I262
I264

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

SMC_BS_ALRT_L
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA

50 51 67

27 50 67
27 50 67

TRUE
TRUE
TRUE
TRUE
TRUE

CPU_PWRGD
7 21 86
I169
TP_CPU_CPUSLP_L
21
I171
PM_DPRSLPVR
14 23 60 86
I170
CPU_DPSLP_L
7 21 86
PM_LAN_ENABLE
23 50
PCI_RST_L
22 37
PM_RSMRST_L
23 50
FUNC_TEST
PM_SB_PWROK
23 26
TRUE
I173
SB_RTC_RST_L
21 26
TRUE
I174
PM_STPCPU_L
23 33
TRUE
I172
PM_STPPCI_L
23 33
TRUE
I175
VR_PWRGD_CK410
23 26
VR_PWRGOOD_DELAY
14 26 60
FSB_CPURST_L
7 11 12 86
FSB_SLPCPU_L
7 12
FUNC_TEST
FSB_DPWR_L
7 12 86
NB_SB_SYNC_L
14 22
TRUE
I177
PP2V5_S0_GPU_TPVDD
TRUE
77
I176
PP2V5_S0_GPU_TXVDDR
77
PP2V5_S0_GPU_AVDD
77
PP2V5_S0_GPU_A2VDD
77
PP2V5_S0_GPU_LPVDD
77
PP2V5_S0_GPU_LVDDR
59 60 64 65 66 70 78 79
28 29 33
PP3V3_S0
4 5 10 14 (=PP3V3_S0_CK410)
17 19 20 21 22 23 24 25 26 27
34 36 37 43 48 51 53 56 57
PP3V3_S0_CK410_VDD48
33
PP3V3_S0_CK410_VDD_PCI 33
PP3V3_S0_CK410_VDD_REF 33
PP3V3_S0_CK410_VDD_CPU_SRC 33
PP3V3_S0_CK410_VDDA
33
PP3V3_FWPHY
4 38 42 43 44
PP3V3_FWPHY_AVDD
38
PP3V3_FWPHY_PLLVDD
38
PP1V95_FWPHY
4 38 42
PP1V95_FWPHY_PLLVDD
38
PP1V2_S3
5 39 62 66 (=PP1V2_S3_ENET)
PP3V3_S3AC
39 41 66
(=PP3V3_S3_ENET)
PP2V5_S3
5 39 62 66 (=PP2V5_S3_ENET)
PP2V5_S3_ENET_AVDD
39 40

PP5V_S3
USB2_CAMERA_N
USB2_CAMERA_P
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCL

5 45 51 61 66 80
6 22 45
6 22 45

I226

27 45 50 53
27 50 53

PP1V5_S0
PPBUS_G3H
PP3V42_G3H
PP5V_S0_AUDIO
GND_AUDIO

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

ALS_GAIN
LTALS_OUT
ACZ_SDATAIN<0>
ACZ_SDATAOUT
ACZ_BITCLK
ACZ_RST_L
EXCARD_OC_L
LTUSB_OC_L
LT2USB_OC_L
PM_SLP_S3_LS5V
PM_SLP_S4_L
SYS_ONEWIRE
MINI_CLKREQ_L
SMC_EXCARD_CP
EXCARD_CLKREQ_L
SMC_EXCARD_PWR_EN
LIO_PLT_RESET_L
ACZ_SYNC
USB2_LT_N
USB2_LT_P
USB2_EXCARD_N
USB2_EXCARD_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
USB2_LT2_N
USB2_LT2_P
PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_C_P
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
SMBUS_SB_SCL
SMBUS_SB_SDA
PCIE_WAKE_L
SMC_BC_ACOK

25 47 65 66
5 8 9 13 16 17
19 24
68 70 78
4 5 41 43 47 54
60 61 63 64 66
5 26 27 35 45 50 51 52
54 65 66 67 68
47
47

6 47 50
47 56
21 47 86
21 47 86
21 47 86
21 47 86
6 22 47 51
6 22 47
4 22 47
47 61 65
5 23 41 46 47 50 63 65
47 50 51
33 34 47
47 50 51

33 34 47
47 50
26 47
21 47 86
6 22 47
6 22 47
6 22 47
6 22 47
47 49
47 49
22 47 49
22 47 49
34 47
34 47
6 22 47
6 22 47
47 49
47 49
22 47 49
22 47 49
34 47
34 47
23 27 28 29 33
45 47
23 27 28 29 33
45 47
23 39 47
47 50 51 67 68

Left I/O Power Connector

FUNC_TEST

Thermal Sensors
HSTHMSNS_DX_P
HSTHMSNS_DX_N
RSFSTHMSNS_D_P
RSFSTHMSNS_D_N

TRUE
TRUE
TRUE
TRUE
TRUE

53
53

PP18V5_DCIN
PP5V_S5
PP5V_S0_AUDIO_PWR
GND_AUDIO_PWR
GND

67
5 25 46 51 61 63 64 65
66 67 70
67
67

Request for at least 10 GND test points

SMC TPs
PM_SYSRST_L
SMC_ONOFF_L

23 26 50
45 50 51 54

Functional / ICT Test

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

REV.

051-7023

SHT
NONE

67 68

FUNC_TEST

TRUE
TRUE

68
5 26 27 35 45 50 51 52 54 65 66
67
66 67 70 78 79 80
4 5 25 31 36 42 47
52 54 56 57 60 61 65

Camera Connector

I227

TRUE
TRUE
TRUE

67 68

Left I/O Data Connector

FUNC_TEST

26 50

14 22

21 34

BATT_POS
BATT_NEG

4 5 14 16 19 28 29 31 32 37 54
63 66
17 19 62 65 66 76 77

14 22

21 34

TRUE
TRUE

5 39 62 66

FUNC_TEST

I216

TRUE
TRUE
TRUE
TRUE

30 31 65 66

Characterization TPs

EXPOSED_VIA

TRUE

PP0V9_S0
PP1V05_S0
PP1V2_S0
PP1V2_S3
PP1V5_S0
PP1V8_S0
PP1V8_S3
PP2V5_S0
PP2V5_S3
PP3V3_S0
PP3V3_S3
PP3V3_S5
PP5V_S0
PP5V_S3
PP5V_S5
PPBUS_G3H
GND

FSB_A_L<31..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>
FSB_BNR_L
FSB_BREQ0_L
FSB_D_L<63..0>
FSB_DBSY_L
FSB_DINV_L<3..0>
FSB_DRDY_L
FSB_DSTBN_L<3..0>
FSB_DSTBP_L<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<4..0>

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

Request for at least 10 GND TPs

I200

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

Battery Connector

FUNC_TEST

CPU FSB NO_TESTs

NO_TEST

Fan Connectors

FUNC_TEST
60

06
86

USB Port "A" (Debug Port) = Right USB 2.0 Port

7 6

NC_CPU_A32_L

6 7

NC_MEM_A_A<15..14>

NC_CPU_A33_L

6 7

NC_MEM_B_A<15..14>

NC_CPU_A34_L

6 7

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A33_L
MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A34_L

7 6

NC_CPU_A35_L

6 7

NC_CPU_A36_L

6 7

NC_CPU_A37_L

6 7

MAKE_BASE=TRUE
NO_TEST=TRUE

7 6

TP_NB_CFG<8>

7 6

NB_CFG<8>

TP_NB_CFG<11..10>

NB_CFG<11..10>

MAKE_BASE=TRUE

NC_CPU_A38_L

NC_CPU_A39_L

MAKE_BASE=TRUE
NO_TEST=TRUE

6 7

TP_NB_CFG<15..14>

NB_CFG<17>

NC_CPU_APM0_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_APM1_L

6 7

NC_CPU_APM1_L

6 7

NC_CPU_EXTBREF

6 7

7 6

MAKE_BASE=TRUE

NC_ENET_CTRL12

MAKE_BASE=TRUE
NO_TEST=TRUE

NB_CFG<13..12>

46 22 6

NC_CPU_HFPLL

NC_CPU_SPARE0

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_SPARE1

RTUSB_OC_L

6 22 46

RTUSB_OC_L

6 22 46

MAKE_BASE=TRUE

USB Port "B" = Trackpad (Geyser)

6 56

USB_TRACKPAD_P

45 22 6

USB_TRACKPAD_N

45 22 6

6 39

USB_TRACKPAD_P

6 22 45

USB_TRACKPAD_N

6 22 45

MAKE_BASE=TRUE

USB_TRACKPAD_N
MAKE_BASE=TRUE

UNUSED_USB_B_OC_L

6 22

MAKE_BASE=TRUE

USB2_LT_P

47 22 6 5

NC_ENET_CTRL25

MAKE_BASE=TRUE
NO_TEST=TRUE

6 39

USB2_LT_N

47 22 6 5

LTUSB_OC_L

USB2_LT_P
USB2_LT_N

USB2_LT_P

5 6 22 47

USB2_LT_N

5 6 22 47

LTUSB_OC_L

5 6 22 47

MAKE_BASE=TRUE
MAKE_BASE=TRUE

USB Port "D" = Camera

USB2_CAMERA_P

45 22 6 5

USB2_CAMERA_N

USB2_CAMERA_P

5 6 22 45

USB2_CAMERA_N

5 6 22 45

MAKE_BASE=TRUE
14

USB2_CAMERA_N
MAKE_BASE=TRUE

22 6

UNUSED_USB_D_OC_L

6 22

MAKE_BASE=TRUE
23 6 5

MAKE_BASE=TRUE
NO_TEST=TRUE

6 22 46

USB2_RT_N

MAKE_BASE=TRUE

NC_CPU_EXTBREF
MAKE_BASE=TRUE
NO_TEST=TRUE

USB2_RT_P

MAKE_BASE=TRUE

NC_ENET_CTRL25

NOTE: NB_CFG<13..12> require test access

TP_NB_CFG<13..12>

USB2_RT_N

USB Port "C" = Left USB 2.0 Port

NC_ENET_CTRL12

TP_SB_SUS_CLK

USB Port "E" = ExpressCard

5 6 23

MAKE_BASE=TRUE
6 7

USB2_EXCARD_P

47 22 6 5

USB2_EXCARD_N

47 22 6 5

USB2_EXCARD_P

5 6 22 47

USB2_EXCARD_N

5 6 22 47

EXCARD_OC_L

5 6 22 47 51

MAKE_BASE=TRUE
6 7

Ethernet Powr Management Support

USB2_EXCARD_N
MAKE_BASE=TRUE

51 47 22 6 5

6 7

MAKE_BASE=TRUE
NO_TEST=TRUE
7 6

RTALS_GAIN

RTUSB_OC_L

22 6

NB_CFG<15..14>

MAKE_BASE=TRUE

RTALS_GAIN

46 22 6

USB2_RT_P
MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_NB_CFG<17>

USB2_RT_N

46 22 6

39 6
6 7

5%
1/16W
MF-LF
402

39 6

MAKE_BASE=TRUE
NO_TEST=TRUE
7 6

NB_CFG<6>

ALS_GAIN

MAKE_BASE=TRUE

NC_CPU_A37_L
MAKE_BASE=TRUE
NO_TEST=TRUE

7 6

NB_CFG<4..3>

MAKE_BASE=TRUE

NC_CPU_A36_L

50 47 5

MAKE_BASE=TRUE
NO_TEST=TRUE

TP_NB_CFG<6>

MAKE_BASE=TRUE
NO_TEST=TRUE
7 6

MEM_B_A<15..14>

MAKE_BASE=TRUE

MAKE_BASE=TRUE
NO_TEST=TRUE

R0600

MAKE_BASE=TRUE
NO_TEST=TRUE

TP_NB_CFG<4..3>

MAKE_BASE=TRUE
NO_TEST=TRUE

MEM_A_A<15..14>

USB2_RT_P

46 22 6

EXCARD_OC_L
MAKE_BASE=TRUE

NC_CPU_SPARE2

6 7

NC_CPU_SPARE4

6 7

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_SPARE4

ENET_LOM_DISABLE

MAKE_BASE=TRUE
NO_TEST=TRUE

USB Port "F" = IR Receiver

R0690
22

SB_GPIO30

ENET_LOM_DIS_L

5%
1/16W
MF-LF
402

USB_IR_P

80 22 6

USB_IR_N

80 22 6

USB_IR_P

6 22 80

USB_IR_N

6 22 80

MAKE_BASE=TRUE

USB_IR_N
MAKE_BASE=TRUE

USB Port "G" = Bluetooth (M13P)

NOTE: BOM options "USB_G_OC_PU" and

"ENET_LOM_DISABLE" are mutually-exclusive.

USB_BT_P

80 22 6

USB_BT_N

80 22 6

USB_BT_P

6 22 80

USB_BT_N

6 22 80

MAKE_BASE=TRUE

USB_BT_N
MAKE_BASE=TRUE

USB Port "H" = 2nd Left USB 2.0 Port

USB2_LT2_P

47 22 6 5

USB2_LT2_N

47 22 6 5

USB2_LT2_P

5 6 22 47

USB2_LT2_N

5 6 22 47

MAKE_BASE=TRUE

USB2_LT2_N
MAKE_BASE=TRUE

Chassis connection to be made at the fan cutout near the right ALS
GND_CHASSIS_FANFRAME
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

SH0601
EMI-SPRING 1
0G-502620R

R0601
0

5%
1/16W
MF-LF
402

Chassis connection to be made at the mounting hole northwest of the DVI connector

ZT0600

HOLE-VIA-P5RP25
1

79 6

GND_CHASSIS_DVI_TOP

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MAKE_BASE=TRUE

GND_CHASSIS_DVI_TOP
GND_CHASSIS_DVI_TOP
GND

6 79
6 79

Chassis connection to be made on FW shell

ZT0603

HOLE-VIA-P5RP25
1

79 44 40 6

GND_CHASSIS_DVI_BOT

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MAKE_BASE=TRUE

GND_CHASSIS_DVI_BOT
GND_CHASSIS_DVI_BOT
GND_CHASSIS_DVI_BOT
GND_CHASSIS_DVI_BOT
GND_CHASSIS_DVI_BOT

6 40 44 79
6 40 44 79
6 40 44 79
6 40 44 79
6 40 44 79

Chassis connection to be made at the mounting hole southwest of the USB connector

ZT0601

HOLE-VIA-P5RP25
1

46 44 6

GND_CHASSIS_USB

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MAKE_BASE=TRUE

GND_CHASSIS_USB
GND_CHASSIS_USB
GND_CHASSIS_USB

6 44 46
6 44 46
6 44 46

Signal Aliases

Chassis connection to be made at the mounting hole east of the LVDS connector

ZT0602

HOLE-VIA-P5RP25
1

78 6

SYNC_MASTER=(M1_MLB)

GND_CHASSIS_LVDS

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MAKE_BASE=TRUE

GND_CHASSIS_LVDS
GND_CHASSIS_LVDS
GND_CHASSIS_LVDS
GND_CHASSIS_LVDS

SYNC_DATE=(11/11/2005)

NOTICE OF PROPRIETARY PROPERTY

6 78
6 78

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

6 78
6 78

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1

78 6

GND_CHASSIS_INVERTER

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MAKE_BASE=TRUE

SH0600 2
OG-503040
SHLD-SM-LF

SIZE

GND_CHASSIS_INVERTER

6 78

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

OMIT

86 12 5

86 12 5
86 12 5

86 12 5

86 21
21
86 21

IN
OUT
IN

86 21 5

86 21

IN
6
6
6
6
6
6
6
6
6
6

FSB_REQ_L<0>K3 REQ0*
FSB_REQ_L<1>H2 REQ1*
FSB_REQ_L<2>K2 REQ2*
FSB_REQ_L<3>J3 REQ3*
FSB_REQ_L<4>L5 REQ4*
FSB_A_L<17> Y2 A17*
FSB_A_L<18> U5 A18*
FSB_A_L<19> R3 A19*
FSB_A_L<20> W6 A20*
FSB_A_L<21> U4 A21*
FSB_A_L<22> Y5 A22*
FSB_A_L<23> U2 A23*
FSB_A_L<24> R4 A24*
FSB_A_L<25> T5 A25*
FSB_A_L<26> T3 A26*
FSB_A_L<27> W3 A27*
FSB_A_L<28> W5 A28*
FSB_A_L<29> Y4 A29*
FSB_A_L<30> W2 A30*
FSB_A_L<31> Y1 A31*
FSB_ADSTB_L<1>
V4 ADSTB1*
CPU_A20M_L A6 A20M*
CPU_FERR_L A5 FERR*
CPU_IGNNE_L C4 IGNNE*
CPU_STPCLK_LD5 STPCLK*
CPU_INTR
C6 LINT0
CPU_NMI
B4 LINT1
CPU_SMI_L
A3 SMI*
NC_CPU_A32_L
AA1 RSVD1
NC_CPU_A33_L
AA4 RSVD2
NC_CPU_A34_L
AB2 RSVD3
NC_CPU_A35_L
AA3 RSVD4
NC_CPU_A36_LM4 RSVD5
NC_CPU_A37_LN5 RSVD6
NC_CPU_A38_LT2 RSVD7
NC_CPU_A39_LV3 RSVD8
NC_CPU_APM0_L
B2 RSVD9
NC_CPU_APM1_L
C3 RSVD10
NC_CPU_HFPLL
B25 RSVD11

DBSY*
BR0*

G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

XDP_BPM_L<0> BI
XDP_BPM_L<1> BI
XDP_BPM_L<2> BI
XDP_BPM_L<3> BI
XDP_BPM_L<4> BI
XDP_BPM_L<5>
XDP_TCK
IN
XDP_TDI
IN
XDP_TDO
OUT
XDP_TMS
IN
XDP_TRST_L
IN
XDP_DBRESET_L
OUT

H5
F21
E1
F1

INIT*

D20
B3

LOCK*

RESET*
RS0*

B1
F3
F4
G3
G2

IERR*

RS1*
RS2*
TRDY*
HIT*
HITM*
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*

PROCHOT*
THERMDA
THERMDC
THERMTRIP*

D21
A24
A25

5 12 86

12 86

5 12 86

IN
BI

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

R0702
54.9

1%
1/16W
MF-LF
2402

PLACE TESTPOINT ON
FSB_IERR_L WITH A GND
0.1" AWAY

21 86

5 12 86

5 11 12 86

12 86

5 12
86

11 86
11 86
11 86

PP1V05_S0

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

R0703
54.9

OMIT

1%
1/16W
MF-LF
2402

U0700

YONAH D32*
FSB_D_L<0> E22 D0*
CPU
FSB_D_L<1> F24 D1*
D33*
BGA
FSB_D_L<2> E26 D2*
D34*
(2 OF 4)
BI
FSB_D_L<3> H22 D3*
D35*
BI
1R0704
FSB_D_L<4>
F23
D36*
D4*
BI
68
FSB_D_L<5>
G25
D37*
D5*
5%
BI
1/16W
FSB_D_L<6>
E25 D6*
D38*
MF-LF
BI
2402
FSB_D_L<7> E23 D7*
D39*
BI
FSB_D_L<8>
K24
D40*
D8*
BI
CPU_PROCHOT_L TO SMC
CPU_PROCHOT_L
FSB_D_L<9>
G24 D9*
D41*
OUT
BI
AND
CPU
VR
TO
INFORM
CPU_THERMD_P OUT
FSB_D_L<10> J24 D10*
D42*
BI
CPU IS HOT
CPU_THERMD_N OUT
FSB_D_L<11>
J23
D43*
D11*
BI
FSB_D_L<12>
H26
D44*
D12*
BI
PM_THRMTRIP_L
OUT
FSB_D_L<13> F26 D13*
D45*
BI
FSB_D_L<14> K22 D14*
D46*
BI
PM_THRMTRIP#
FSB_D_L<15>
H25
D47*
D15*
BI
SHOULD CONNECT TO
FSB_DSTBN_L<0>
FSB_CLK_CPU_PIN
H23 DSTBN0*
DSTBN2*
BI
ICH7-M
AND
GMCH
FSB_DSTBP_L<0>
FSB_CLK_CPU_NIN
G22 DSTBP0*
DSTBP2*
BI
WITHOUT T-ING (NO
FSB_DINV_L<0>
J26 DINV0*
DINV2*
BI
STUB)
FSB_D_L<16> N22 D16*
D48*
BI
FSB_D_L<17> K25 D17*
D49*
BI
FSB_D_L<18>
P26 D18*
D50*
BI
NC_CPU_EXTBREF
FSB_D_L<19>
R23
D51*
D19*
BI
FSB_D_L<20> L25 D20*
D52*
BI
NC_CPU_SPARE0
FSB_D_L<21> L22 D21*
D53*
BI
NC_CPU_SPARE1 SPARE[7-0],HFPLL:
FSB_D_L<22>
L23
D54*
D22*
BI
NC_CPU_SPARE2 ROUTE TO TP VIA AND
FSB_D_L<23> M23 D23*
D55*
BI
TP_CPU_SPARE3 PLACE GND VIA W/IN 1000 MILS
FSB_D_L<24> P25 D24*
D56*
BI
NC_CPU_SPARE4
FSB_D_L<25>
P22 D25*
D57*
BI
TP_CPU_SPARE5
FSB_D_L<26>
P23
D26*
D58*
BI
TP_CPU_SPARE6
FSB_D_L<27> T24 D27*
D59*
BI
TP_CPU_SPARE7
FSB_D_L<28> R24 D28*
D60*
BI
PP1V05_S0
FSB_D_L<29>
L26
D29*
D61*
BI
FSB_D_L<30> T25 D30*
D62*
BI
FSB_D_L<31> N24 D31*
D63*
BI
1R0705
FSB_DSTBN_L<1>
M24 DSTBN1*
DSTBN3*
BI
1K
FSB_DSTBP_L<1>
N25
1%
DSTBP1*
DSTBP3*
BI
1/16W
FSB_DINV_L<1>
M26 DINV1*
MF-LF
DINV3*
BI
2402
CPU_GTLREF
AD26 GTLREF
COMP0
11 86
11 86

11 86

86 12 5

7 11

86 12 5

7 11

86 12 5

7 11

86 12 5

11 26

86 12 5
12 5
86
86 12 5

86 12 5

86 12 5
86 12 5

14 21 51

DATA GRP2

BPRI*
DEFER*
DRDY*

PP1V05_S0

FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
FSB_BREQ0_L
FSB_IERR_L
CPU_INIT_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
FSB_HIT_L
FSB_HITM_L

H1
E2
G5

86 12 5
86 12 5
86 12 5

BCLK0
BCLK1

A22
A21

5 34

86 12 5

5 34

86 12 5
86 12 5

RSVD12

T22

86 12 5

86 12 5
86 12 5

RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

D2
F6
D3
C1
AF1
D22
C23
C24

86 12 5

86 12 5
86 12 5

86 12 5
86 12 5
86 12 5

DATA GRP3

86 12 5

ADS*
BNR*

DATA GRP1

86 12 5

CONTROL

86 12 5

ADDR GROUP0

86 12 5

XDP/ITP SIGNALS

THERM

86 12 5

HCLK

86 12 5

ADDR GROUP1

FSB_A_L<3> J4 A3*
YONAH
FSB_A_L<4> L4 A4*
CPU
FSB_A_L<5> M3 A5*
BGA
FSB_A_L<6> K5 A6*
(1 OF 4)
FSB_A_L<7> M1 A7*
FSB_A_L<8> N2 A8*
FSB_A_L<9> J1 A9*
FSB_A_L<10> N3 A10*
FSB_A_L<11> P5 A11*
FSB_A_L<12> P2 A12*
FSB_A_L<13> L1 A13*
FSB_A_L<14> P4 A14*
FSB_A_L<15> P1 A15*
FSB_A_L<16> R1 A16*
FSB_ADSTB_L<0>
L2 ADSTB0*

RESERVED

86 12 5

DATA GRP0

U0700

86 12 5

21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

86 12 5
86 12 5
86 12 5
86 12 5

PP1V05_S0

B
11 7

XDP_TMS

R0720
54.9
1

86 12 5

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

86 12 5

LAYOUT NOTE: 0.5"

R0706
CPU_TEST1
2.0K

1%
402

11 7

XDP_TDI

1%
1/16W
MF-LF
2402

R0721
54.9
1

1%
402

11 7

XDP_TCK

OUT

CPU_TEST2
CPU_BSEL<0>
CPU_BSEL<1>
CPU_BSEL<2>
NOSTUFF

D25
B22
B23
C21

TEST2

MISC

COMP1
COMP2
COMP3
DPRSTP*

BSEL0
BSEL1

DPSLP*
DPWR*

BSEL2

PWRGOOD
SLP*
PSI*

R0730
0

R0722
54.9
1

A2 NC
MAX LENGTH
C26 TEST1

AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
R26
U26
U1
V1
E5
B5
D24
D6
D7
AE6

86
86
86
86

FSB_D_L<32> BI
FSB_D_L<33> BI
FSB_D_L<34> BI
FSB_D_L<35> BI
FSB_D_L<36> BI
FSB_D_L<37> BI
FSB_D_L<38> BI
FSB_D_L<39> BI
FSB_D_L<40> BI
FSB_D_L<41> BI
FSB_D_L<42> BI
FSB_D_L<43> BI
FSB_D_L<44> BI
FSB_D_L<45> BI
FSB_D_L<46> BI
FSB_D_L<47> BI
FSB_DSTBN_L<2>
BI
FSB_DSTBP_L<2>
BI
FSB_DINV_L<2>BI
FSB_D_L<48> BI
FSB_D_L<49> BI
FSB_D_L<50> BI
FSB_D_L<51> BI
FSB_D_L<52> BI
FSB_D_L<53> BI
FSB_D_L<54> BI
FSB_D_L<55> BI
FSB_D_L<56> BI
FSB_D_L<57> BI
FSB_D_L<58> BI
FSB_D_L<59> BI
FSB_D_L<60> BI
FSB_D_L<61> BI
FSB_D_L<62> BI
FSB_D_L<63> BI
FSB_DSTBN_L<3>
BI
FSB_DSTBP_L<3>
BI
FSB_DINV_L<3>BI
CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>
CPU_DPRSTP_L IN
CPU_DPSLP_L IN
FSB_DPWR_L
IN
CPU_PWRGD
IN
FSB_SLPCPU_L IN
CPU_PSI_L
IN

5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86

5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86

5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86

LAYOUT NOTE:
COMP0,2 CONNECT WITH
TRACE LENGTH SHORTER
COMP1,3 CONNECT WITH
TRACE LENGTH SHORTER

5 12 86
5 12 86
5 12 86
5 12 86

ZO=27.4OHM, MAKE
THAN 0.5".
ZO=55OHM, MAKE
THAN 0.5".

5 12 86

R0716
27.4

5 12 86
5 12 86

12 86
5

402

R0717
54.9
1

5 12
86
5 12 86

2
1% 402

R0718
27.4

5 12 86

R0719
54.9
1

5 21 60

1%
402

5 21 86
5 12 86
5 21 86
5 12
60

402

NOSTUFF

1R0707
R0712
51
1K

1%
402

5%
1/16W
MF-LF
2402

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

CPU 1 OF 2-FSB
WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50
SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM
TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

OMIT

PPVCORE_S0_CPU
OMIT

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

U0700

VCC_1
VCC_2

VCC_68
VCC_69

YONAH VCC_70
CPU VCC_71
VCC_4
VCC_3
VCC_5

BGA

(3 OF 4)

VCC_72

VCC_6

VCC_73

VCC_7
VCC_8

VCC_74
VCC_75

VCC_9

VCC_76

VCC_10
VCC_11

VCC_77
VCC_78

VCC_12
VCC_13

VCC_79
VCC_80

VCC_14

VCC_81

VCC_15
VCC_16

VCC_82
VCC_83

VCC_17

VCC_84

VCC_18
VCC_19

VCC_85
VCC_86

VCC_20

VCC_87

VCC_21
VCC_22

VCC_88
VCC_89

VCC_23
VCC_24

VCC_90
VCC_91

VCC_25

VCC_92

VCC_26
VCC_27

VCC_93
VCC_94

VCC_28

VCC_95

VCC_29
VCC_30

VCC_96
VCC_97

VCC_31

VCC_98

VCC_32
VCC_33

VCC_99
VCC_100

VCC_34
VCC_35

VCCP_1

VCC_36

VCCP_2

VCC_37
VCC_38

VCCP_3
VCCP_4

VCC_39

VCCP_5

VCC_40
VCC_41

VCCP_6
VCCP_7

VCC_42

VCCP_8

VCC_43
VCC_44

VCCP_9
VCCP_10

VCC_45
VCC_46

VCCP_11
VCCP_12

VCC_47

VCCP_13

VCC_48
VCC_49

VCCP_14
VCCP_15

VCC_50

VCCP_16

VCC_51
VCC_52
VCC_53

VCCA

VCC_54
VCC_55

VID0

VCC_56
VCC_57

VID1
VID2

VCC_58

VID3

VCC_59
VCC_60

VID4
VID5

VCC_61

VID6

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
AD6
AF5
AE5
AF4
AE3
AF2
AE2

A4
A8
A11
A14
A16
A19
A23
A26
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

5 8 9 54 60 66

(CPU CORE POWER)

PP1V05_S0

25 34 54 64 66
5 7 9 11 12 13 16 17 19 21 24

(CPU IO POWER 1.05V)

VCCA=1.5 ONLY

PP1V5_S0

(CPU INTERNAL PLL POWER 1.5V)

CPU_VID<0>
OUT
CPU_VID<1>
OUT
CPU_VID<2>
OUT
CPU_VID<3>
OUT
CPU_VID<4>
OUT
CPU_VID<5>
OUT
CPU_VID<6>
OUT

9 86
9 86
9 86
9 86
9 86

SUPPLYPPVCORE_S0_CPU

VID FOR CPU POWER

IF NO USE, NEED PULL-UP OR
PULL-DOWN
1

5 8 9 54 60 66

R0802
100

9 86

1%
1/16W
MF-LF

9 86

2402

VCC_62
VCC_63
VCC_64
VCC_65
VCC_66

VCCSENSE

AF7

VCC_67

VSSSENSE

AE7

CPU_VCCSENSE_P

OUT

60 86

CPU_VCCSENSE_N

OUT

60 86

R0803

1
LAYOUT NOTE: CONNECT R0803100
1%
TO TP_VSSSENSE WITH NO
1/16W
MF-LF
STUB.
2402

LAYOUT NOTE:
PROVIDE A TEST POINT (WITH NO STUB)
TO CONNECT A DIFFERENCTIAL PROBE
LAYOUT NOTE:
BETWEEN VCCSENSE AND VSSSENSE AT THE
CPU_VCCSENSE_P/CPU_VCCSENSE_N USE
LOCATION WHERE THE TWO 54.9 OHM
ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.
RESISTORS TERMINATE THE 55 OHM
TRANSMISSION LINE

LAYOUT NOTE:
VCCSENSE AND VSSSENSE LINES
SHOULD BE OF EQUAL LENGTH

U0700

VSS_1

VSS_82

VSS_2

YONAH VSS_83
CPU VSS_84
VSS_85

VSS_3
VSS_4
VSS_5
VSS_6

BGA

(4 OF 4)

VSS_86
VSS_87

VSS_7

VSS_88

VSS_8
VSS_9

VSS_89
VSS_90

VSS_10

VSS_91

VSS_11
VSS_12

VSS_92
VSS_93

VSS_13

VSS_94

VSS_14
VSS_15

VSS_95
VSS_96

VSS_16
VSS_17

VSS_97
VSS_98

VSS_18

VSS_99

VSS_19
VSS_20

VSS_100
VSS_101

VSS_21

VSS_102

VSS_22
VSS_23

VSS_103
VSS_104

VSS_24

VSS_105

VSS_25
VSS_26

VSS_106
VSS_107

VSS_27
VSS_28

VSS_108
VSS_109

VSS_29

VSS_110

VSS_30
VSS_31

VSS_111
VSS_112

VSS_32

VSS_113

VSS_33
VSS_34

VSS_114
VSS_115

VSS_35

VSS_116

VSS_36
VSS_37

VSS_117
VSS_118

VSS_38
VSS_39

VSS_119
VSS_120

VSS_40

VSS_121

VSS_41
VSS_42

VSS_122
VSS_123

VSS_43

VSS_124

VSS_44
VSS_45

VSS_125
VSS_126

VSS_46

VSS_127

VSS_47
VSS_48

VSS_128
VSS_129

VSS_49
VSS_50

VSS_130
VSS_131

VSS_51

VSS_132

VSS_52
VSS_53

VSS_133
VSS_134

VSS_54

VSS_135

VSS_55
VSS_56

VSS_136
VSS_137

VSS_57

VSS_138

VSS_58
VSS_59

VSS_139
VSS_140

VSS_60
VSS_61

VSS_141
VSS_142

VSS_62

VSS_143

VSS_63
VSS_64

VSS_144
VSS_145

VSS_65

VSS_146

VSS_66
VSS_67

VSS_147
VSS_148

VSS_68

VSS_149

VSS_69
VSS_70

VSS_150
VSS_151

VSS_71
VSS_72

VSS_152
VSS_153

VSS_73

VSS_154

VSS_74
VSS_75

VSS_155
VSS_156

VSS_76

VSS_157

VSS_77
VSS_78

VSS_158
VSS_159

VSS_79

VSS_160

VSS_80
VSS_81

VSS_161
VSS_162

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24

CPU 2 OF 2-PWR/GND
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

D
CPU VCORE HF AND BULK DECOUPLING
66 60 54 8 5

PPVCORE_S0_CPU

4x 470uF. 20x 22uF 0805

C0900

22UF

C0901

22UF

20%
2 6.3V
CERM
805

C0902
22UF

20%
2 6.3V
CERM
805

C0903
22UF

20%
2 6.3V
CERM
805

C0904
22UF

20%
2 6.3V
CERM
805

C0905
22UF

20%
2 6.3V
CERM
805

C0906
22UF

20%
2 6.3V
CERM
805

C0907
22UF

20%
2 6.3V
CERM
805

C0908
22UF

20%
2 6.3V
CERM
805

CPU VCORE VID Connections

C0909
22UF

Resistors to allow for override of CPU VID

Will probably be removed before production

20%
2 6.3V
CERM
805

R0990
86 8

C0910

22UF

C0911

22UF

20%
2 6.3V
CERM
805

C0912
22UF

20%
2 6.3V
CERM
805

C0913
22UF

20%
2 6.3V
CERM
805

C0914
22UF

20%
2 6.3V
CERM
805

C0915
22UF

20%
2 6.3V
CERM
805

C0916
22UF

20%
2 6.3V
CERM
805

C0917
22UF

20%
2 6.3V
CERM
805

C0918
22UF

20%
2 6.3V
CERM
805

CRITICAL
1

470uF-8MOHM

20%
3 2 2.5V
POLY
D2TS

CRITICAL

C0950

CRITICAL

C0952

470uF-8MOHM

22UF

86 8

20%
2 6.3V
CERM
805

20%
3 2 2.5V
POLY
D2TS

C0954

86 8

R0992

5%
1/16W
MF-LF
402

20%
3 2 2.5V
POLY
D2TS

86 8

CPU_VID<4>

R0993

R0994

5%
1/16W
MF-LF
402

R0995

R0996

5%
1/16W
MF-LF
402

CPU_VID<5>

CPU_VID<6>

5%
1/16W
MF-LF
402

CPU_VID<3>

470uF-8MOHM

R0991

CPU_VID<1>

CPU_VID<2>

5%
1/16W
MF-LF
402

CRITICAL

C0953

470uF-8MOHM

C0919

86 8

CPU_VID<0>

IMVP6_VID<0>

5 60

IMVP6_VID<1>

5 60

IMVP6_VID<2>

5 60

IMVP6_VID<3>

5 60

IMVP6_VID<4>

5 60

IMVP6_VID<5>

5 60

IMVP6_VID<6>

5 60

5%
1/16W
MF-LF
402

VCCA (CPU AVdd) Decoupling

65 47 25 24 19 17 16 13 8 5
66

PP1V5_S0

1x 10uF, 1x 0.01uF
C0980 1
10uF

20%
6.3V 2
X5R
603

C0981
0.01UF

20%
2 16V
CERM
402

VCCP (CPU I/O) Decoupling

24 21 19 17 16 13 12 11 8 7 5
66 64 54 34 25

PP1V05_S0

1x 470uF, 6x 0.1uF 0402

C0935 1

470uF-9MOHM

20%
2.5V 2 3
POLY
D2TS

C0936
0.1UF

20%
2 10V
CERM
402

C0937
0.1UF

20%
2 10V
CERM
402

C0938
0.1UF

20%
2 10V
CERM
402

C0939
0.1UF

20%
2 10V
CERM
402

C0940
0.1UF

20%
2 10V
CERM
402

C0941
0.1UF

20%
2 10V
CERM
402

CRITICAL

NOTE: This cap is shared

between CPU and NB

CPU Decoupling & VID

SYNC_MASTER=M1_MLB

SYNC_DATE=02/08/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

CPU ZONE THERMAL SENSOR

79 78 70 66 65
64 60 59 57 56 53 51 48 43
37 36 34 33 29 28 27 26 25
24 23 22 21 20 19 17 14 5 4

PP3V3_S0

C
LAYOUT NOTE:
ADD GND GUARD TRACE
FOR CPU_THERMD_P AND
CPU_THERMD_N

LAYOUT NOTE:
ROUTE CPU_THERMD_P AND
CPU_THERMD_N ON SAME
LAYER.
10 MIL TRACE
10 MIL SPACING

R1005

C1002

10K

0.1UF

5%
1/16W
MF-LF
2 402

10%
2 16V
X5R
402

PLACEHOLDER ADT7461A

R1006
10K

5%
1/16W
MF-LF
2 402

CRITICAL 1
VDD

R1001
7

OUT

CPU_THERMD_P

499

1%
1/16W
MF-LF
402

(TO CPU INTERNAL THERMAL DIODE)

THRM_CPU_DX_P 2
THRM_CPU_DX_N 3

D+
D-

ALERT*/ 6
THM2*
THM* 4

ADT7461
MSOP

C1001

THRM_ALERT_L
THRM_ALERT

SCLK 8
SDATA 7

SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA

0.001uF

R1002
7

U1001

CPU_THERMD_N

499

10%
50V
2 CERM
402

4 27 48 50

GND
5

1%
1/16W
MF-LF
402

PLACE U1001 NEAR THE U1200

CPU MISC1-TEMP SENSOR

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

CPU ITP700FLEX DEBUG SUPPORT

C
ITPCONN
21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

CRITICAL

PP1V05_S0

J1101

ITP

52435-2872
F-RT-SM

1
R1101
R1103
54.9 54.9

1%
1/16W
MF-LF
2402

OUT

XDP_TDI
XDP_TMS

XDP_TRST_L

ITP
7

R1102
22.6

XDP_TDO

86 34

22.62
1
FSB_CPURST_L

11 7

65 64 62 55 26 25 24 23 22 5
78 66

CPU_XDP_CLK_N
CPU_XDP_CLK_P

XDP_TCK

OUT
86

1%
1/16W
MF-LF
402

OUT

IN
(FROM CK410M HOST 133/167MHZ)

R1100

86 12 7 5

(TCK)
XDP_TCK
ITP_TDO

1%
1/16W
MF-LF
402

ITP

11 7

86 7

PP3V3_S5

R1104
240

5%
1/16W
MF-LF
2402

(AND WITH RESET BUTTON) OUT

XDP_DBRESET_L
21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

(FBO)

ITPRESET_L

XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
PP1V05_S0
1 C1100
0.1UF
10%
2 16V
X5R
402

1
2
3
NC 4
5
NC 6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NC 24
25
26
27
28

(DBA#)INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

(DEBUG PORT ACTIVE)
(DBR#)
TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC
(DEBUG PORT RESET)

518S0320

R1106

680
ITP TCK SIGNAL LAYOUT NOTE:
5%
MF-LF
ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTORS TCK PIN TO 1/16W
CPUS
402
2
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO
ITP700FLEX
CONNECTORS FBO PIN.

CPU ITP700FLEX DEBUG

SYNC_MASTER=M1_MLB
SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

86 7 5

86 7 5
86 7 5

21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

PP1V05_S0

R1220

R1225

54.9

221

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

R1221
24.9

1%
1/16W
MF-LF
402 2

R1226

100

1%
1/16W
MF-LF
2 402

C1226
0.1uF

10%
16V
2 X5R
402

BI
BI

86 7 5

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8

NB_FSB_XRCOMP
NB_FSB_XSCOMP
NB_FSB_XSWING

21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

E1 HXRCOMP
E2 HXSCOMP
E4 HXSWING

NB_FSB_YRCOMP
NB_FSB_YSCOMP
NB_FSB_YSWING

PP1V05_S0

R1230

R1235

54.9

221

1%
1/16W
MF-LF
402 2

34 5

FSB_CLK_NB_P
FSB_CLK_NB_N

HD0*
HD1*
HD2*
HD3*
HD4*
HD5*
HD6*
HD7*
HD8*
HD9*
HD10*
HD11*
HD12*
HD13*
HD14*
HD15*
HD16*
HD17*
HD18*
HD19*
HD20*
HD21*
HD22*
HD23*
HD24*
HD25*
HD26*
HD27*
HD28*
HD29*
HD30*
HD31*
HD32*
HD33*
HD34*
HD35*
HD36*
HD37*
HD38*
HD39*
HD40*
HD41*
HD42*
HD43*
HD44*
HD45*
HD46*
HD47*
HD48*
HD49*
HD50*
HD51*
HD52*
HD53*
HD54*
HD55*
HD56*
HD57*
HD58*
HD59*
HD60*
HD61*
HD62*
HD63*

Y1 HYRCOMP
U1 HYSCOMP
W1 HYSWING
AG2 HCLKIN
AG1 HCLKIN*

OMIT

U1200
945GM
NB
BGA
(1 OF 10)

HA3*
HA4*
HA5*
HA6*
HA7*
HA8*
HA9*
HA10*
HA11*
HA12*
HA13*
HA14*
HA15*
HA16*
HA17*
HA18*
HA19*
HA20*
HA21*
HA22*
HA23*
HA24*
HA25*
HA26*
HA27*
HA28*
HA29*
HA30*
HA31*

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>

5 7 86

PP1V05_S0

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

R1210

HOST

E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13

FSB_ADS_L
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
NB_FSB_VREF
FSB_BNR_L
FSB_BPRI_L
FSB_BREQ0_L
FSB_CPURST_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DPWR_L
FSB_DRDY_L

J7
W8
U3
AB10

FSB_DINV_L<0>
FSB_DINV_L<1>
FSB_DINV_L<2>
FSB_DINV_L<3>

HDSTBN0*
HDSTBN1*
HDSTBN2*
HDSTBN3*

K4
T7
Y5
AC4

FSB_DSTBN_L<0>
FSB_DSTBN_L<1>
FSB_DSTBN_L<2>
FSB_DSTBN_L<3>

HDSTBP0*
HDSTBP1*
HDSTBP2*
HDTSBP3*

K3
T6
AA5
AC5

FSB_DSTBP_L<0>
FSB_DSTBP_L<1>
FSB_DSTBP_L<2>
FSB_DSTBP_L<3>

HHIT*
HHITM*
HLOCK*

D3
D4
B3

FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L

HREQ0*
HREQ1*
HREQ2*
HREQ3*
HREQ4*

D8
G8
B8
F8
A8

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

HRS0*
HRS1*
HRS2*

B4
E6
D6

FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>

HSLPCPU*
HTRDY*

E3
E7

FSB_SLPCPU_L
FSB_TRDY_L

HADS*
HADSTB0*
HADSTB1*
HAVREF
HBNR*
HBPRI*
HBREQ0*
HCPURST*
HDBSY*
HDEFER*
HDPWR*
HDRDY*
HDVREF
HDINV0*
HDINV1*
HDINV2*
HDINV3*

100

5 7 86

BI
OUT
BI
OUT
BI
OUT

5 7 86
7 86
5 7 86
5 7 11 86
5 7 86

C1211

1
1

R1211
200

0.1uF

10%
16V
X5R 2
402

1%
1/16W
MF-LF
2 402

7 86

5 7 86

1%
1/16W
MF-LF
2 402

5 7 86

OUT

7 86

OUT

7 86

OUT

7 86

OUT

5 7

OUT

7 86

1%
1/16W
MF-LF
2 402

NB CPU Interface
SYNC_MASTER=M1_MLB

A
1

R1231
24.9

1%
1/16W
MF-LF
402 2

R1236
100

1%
1/16W
MF-LF
2 402

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

C1236

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

0.1uF

10%
2 16V
X5R
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

PP1V5_S0

5 8 9 13 16 17 19 24 25 47 65
66

R1310
24.9

OMIT

1%
1/16W
MF-LF
2 402

U1200
OUT

OUT

19
19

OUT
OUT

OUT

TV-Out Signal Usage:

65 47 25 24 19 17 16 13 9 8 5
66

Composite: DACA only

S-Video:
DACB & DACC only
Component: DACA, DACB & DACC
Unused DAC outputs must remain powered, but can omit
filtering components. Unused DAC outputs should
connect to GND through 75-ohm resistors.

OUT

65 47 25 24 19 17 16 13 9 8 5
66

OUT

65 47 25 24 19 17 16 13 9 8 5
66

OUT

65 47 25 24 19 17 16 13 9 8 5
66

OUT

65 47 25 24 19 17 16 13 9 8 5
66
65 47 25 24 19 17 16 13 9 8 5
66
65 47 25 24 19 17 16 13 9 8 5
66

OUT
OUT
OUT

TP_LVDS_BKLTCTL
TP_LVDS_BKLTEN
TP_LVDS_CLKCTLA
TP_LVDS_CLKCTLB
TP_LVDS_DDC_CLK
TP_LVDS_DDC_DATA
NC_LVDS_IBG
TP_LVDS_VBG
TP_LVDS_VDDEN
NC_LVDS_VREFH
TP_LVDS_VREFL

D32 L_BKLTCTL
J30 L_BKLTEN
H30 L_CLKCTLA
H29 L_CLKCTLB
G26 L_DDC_CLK

NC_LVDS_A_CLKN
NC_LVDS_A_CLKP
NC_LVDS_B_CLKN
NC_LVDS_B_CLKP

A33 LA_CLK*
A32 LA_CLK
E27 LB_CLK*

NC_LVDS_A_DATAN<0>
NC_LVDS_A_DATAN<1>
NC_LVDS_A_DATAN<2>

C37 LA_DATA0*
B35 LA_DATA1*
A37 LA_DATA2*

EXP_A_COMPI

BGA

EXP_A_COMPO

(3 OF 10)

EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7

C32 L_VREFL

E26 LB_CLK

B37 LA_DATA0
B34 LA_DATA1
A36 LA_DATA2

NC_LVDS_B_DATAN<0>
NC_LVDS_B_DATAN<1>
NC_LVDS_B_DATAN<2>

G30 LB_DATA0*
D30 LB_DATA1*
F29 LB_DATA2*

EXP_A_RXN8
EXP_A_RXN9
EXP_A_RXN10
EXP_A_RXN11
EXP_A_RXN12
EXP_A_RXN13
EXP_A_RXN14
EXP_A_RXN15
EXP_A_RXP0
EXP_A_RXP1
EXP_A_RXP2
EXP_A_RXP3

F30 LB_DATA0
D29 LB_DATA1
F28 LB_DATA2

PP1V5_S0
PP1V5_S0
PP1V5_S0

A16 TV_DACA_OUT
C18 TV_DACB_OUT
A19 TV_DACC_OUT

PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0

J20 TV_IREF
B16 TV_IRTNA
B18 TV_IRTNB
B19 TV_IRTNC

TV-Out Disable

CRT Disable
Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie
HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core
rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

OUT

21 19 17 16 13 12 11 9 8
66 64 54 34 25
21 19 17 16 13 12 11 9 8
66 64 54 34 25

7 5
24
7 5
24

OUT

21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

OUT

21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

OUT

BI
OUT

21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

OUT
OUT

PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
TP_CRT_DDC_CLK
TP_CRT_DDC_DATA
GND
PP1V05_S0
GND

E23 CRT_BLUE
D23 CRT_BLUE*
C22 CRT_GREEN
B22 CRT_GREEN*
A21 CRT_RED
B21 CRT_RED*

EXP_A_RXP4
EXP_A_RXP5
EXP_A_RXP6
EXP_A_RXP7
EXP_A_RXP8
EXP_A_RXP9
EXP_A_RXP10
EXP_A_RXP11
EXP_A_RXP12
EXP_A_RXP13
EXP_A_RXP14
EXP_A_RXP15
EXP_A_TXN0
EXP_A_TXN1
EXP_A_TXN2
EXP_A_TXN3
EXP_A_TXN4
EXP_A_TXN5
EXP_A_TXN6
EXP_A_TXN7
EXP_A_TXN8
EXP_A_TXN9

VGA

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and
VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24
21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2

G25 L_DDC_DATA
B38 L_IBG
C35 L_VBG
F32 L_VDDEN
C33 L_VREFH

NC_LVDS_A_DATAP<0>
NC_LVDS_A_DATAP<1>
NC_LVDS_A_DATAP<2>

NC_LVDS_B_DATAP<0>
NC_LVDS_B_DATAP<1>
NC_LVDS_B_DATAP<2>

945GM
NB

PCI-EXPRESS GRAPHICS

LVDS

Can leave all signals NC if LVDS is not implemented

Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used
VCCD_LVDS must remain powered with proper decoupling.
Otherwise, tie VCCD_LVDS to GND also.

LVDS Disable

EXP_A_TXN10

C26 CRT_DDC_CLK
C25 CRT_DDC_DATA
G23 HSYNC

EXP_A_TXN11
EXP_A_TXN12

J22 CRT_IREF
H23 CRT_VSYNC

EXP_A_TXN14
EXP_A_TXN15

EXP_A_TXN13

EXP_A_TXP0
EXP_A_TXP1
EXP_A_TXP2

EXP_A_TXP3
EXP_A_TXP4
EXP_A_TXP5
EXP_A_TXP6
EXP_A_TXP7
EXP_A_TXP8
EXP_A_TXP9
EXP_A_TXP10
EXP_A_TXP11
EXP_A_TXP12
EXP_A_TXP13
EXP_A_TXP14
EXP_A_TXP15

D40
D38

PEG_COMP

F34

PEG_D2R_N<0>
PEG_D2R_N<1>
PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<6>
PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>

G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

SDVO Alternate Function

PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>
PEG_D2R_P<9>
PEG_D2R_P<10>
PEG_D2R_P<11>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<14>
PEG_D2R_P<15>
PEG_R2D_C_N<0>
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
PEG_R2D_C_P<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>

SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#

OUT

SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL

SDVOB_RED#
SDVOB_GREEN#
SDVOB_BLUE#
SDVOB_CLKN
SDVOC_RED#
SDVOC_GREEN#
SDVOC_BLUE#
SDVOC_CLKN

SDVOB_RED
SDVOB_GREEN
SDVOB_BLUE
SDVOB_CLKP
SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP

NB PEG / Video Interfaces

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

R14401

R1441
OMIT

TP_NB_XOR_FSB2_H7
TP_NB_TESTIN_L
NB_TV_DCONSEL0
NB_TV_DCONSEL1

19
19
19

PP3V3_S0

R14201
10K

5%
1/16W
MF-LF
402 2
51 50 29 28

86 60 23 5

NB_BSEL<0>
NB_BSEL<1>
NB_BSEL<2>
NB_CFG<3>
NB_CFG<4>
NB_CFG<5>
NB_CFG<6>
NB_CFG<7>
NB_CFG<8>
NB_CFG<9>
NB_CFG<10>
NB_CFG<11>
NB_CFG<12>
NB_CFG<13>
TP_NB_CFG<14>
TP_NB_CFG<15>
NB_CFG<16>
NB_CFG<17>
NB_CFG<18>
NB_CFG<19>
NB_CFG<20>

OUT

PM_BMBUSY_L

PLT_RST_L

100

51 21 7

OUT

60 26 5

5%
1/16W
MF-LF
402

19
19

BI
BI

22 5

OUT

33 5

OUT

A41 RSVD11
A35 RSVD12
A34 RSVD13

K16 CFG0
K18 CFG1
J18 CFG2
F18 CFG3

G28 PM_BM_BUSY*
F25 PM_EXTTS0*
H26 PM_EXTTS1*

D19 CFG7
D16 CFG8
G16 CFG9
E16 CFG10
D15 CFG11
G15 CFG12
K15 CFG13
C15 CFG14
H16 CFG15
G18 CFG16
H15 CFG17
J25 CFG18
K27 CFG19
J26 CFG20

PM_THRMTRIP_L
VR_PWRGOOD_DELAY
NB_RST_IN_L_R

IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD

G6 PW_THRMTRIP*
AH33 PWROK
AH34 RSTIN*

TP_SDVO_CTRLCLK
TP_SDVO_CTRLDATA
NB_SB_SYNC_L
CLK_NB_OE_L

SM_CK1
SM_CK2
SM_CK3

AG11 RSVD5
AF11 RSVD6
H7 RSVD7

E15 CFG4
F15 CFG5
E18 CFG6

H28 SDVO_CTRLCLK
H27 SDVO_CTRLDATA
K28 ICH_SYNC*
H32 CLK_REQ*

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

BGA

D28 RSVD14
D27 RSVD15

PM_EXTTS_L
PM_DPRSLPVR

R1430
26 22 5

NC_NB_XOR_LVDS_A35
NC_NB_XOR_LVDS_A34
NC_NB_XOR_LVDS_D28
NC_NB_XOR_LVDS_D27

SM_CK0

(2 OF 10)

J19 RSVD8
K30 RSVD9
J29 RSVD10

NC
19

945GM
NB

T32 RSVD1
R32 RSVD2
F3 RSVD3
F7 RSVD4

RSVD

NC
NC
NC
NC
NC
NC

(D_PLLMON1#)
(D_PLLMON1)
(H_EDRDY#)
(H_PCREQ#)
(H_PLLMON1#)
(H_PLLMON1)
(H_PROCHOT#)
(TESTIN#)
(TV_DCONSEL0)
(TV_DCONSEL1)
(VSS_MCHDETECT)
(LA_DATAN3)
(LA_DATAP3)
(LB_DATAN3)
(LB_DATAP3)

U1200

SM_CK2*

AY7
AY40
AU20

SM_CKE2

BA29
AY29

SM_CS0*
SM_CS1*
SM_CS2*
SM_CS3*

AW21

AF10

AY20
AU21

SMVREF0

AK1

SMVREF1

AK41

G_CLKIN*

AF33
AG33

D_REFSSCLKIN*
D_REFSSCLKIN

DMI_RXN1
DMI_RXN2

AT9

A27
A26
C40
D41
AE35
AF39
AG35

DMI_RXN3

AH39

DMI_RXP0

AC35
AE39

DMI_RXP1
DMI_RXP2

AF35

DMI_RXP3

AG39

DMI_TXN0

AE37

DMI_TXN1
DMI_TXN2

AF41

DMI_TXN3

AG37
AH41

DMI_TXP0
DMI_TXP1

AC37

DMI_TXP2

AF37
AG41

DMI_TXP3

OUT

28 30

OUT

28 30

OUT

29 30

OUT

29 30

OUT

28 30

OUT

28 30

OUT

29 30

OUT

29 30

PP1V8_S3
MEM_ODT<0>
MEM_ODT<1>
MEM_ODT<2>
MEM_ODT<3>

OUT

28 30

OUT

28 30

OUT

29 30

OUT

29 30

4 5 16 19 28 29 31 32 37 54 63
66

R1410
80.6

1%
1/16W
MF-LF
2 402

MEM_RCOMP_L
MEM_RCOMP

AV9

D_REFCLKIN

OUT

NC
NC

BA13
BA12

SMRCOMP*
SMRCOMP

DMI_RXN0

BA41 NC3
BA40 NC4
BA39 NC5

AW12
AY21

SMOCDCOMP1

G_CLKIN
D_REFCLKIN*

MEM_CS_L<0>
MEM_CS_L<1>
MEM_CS_L<2>
MEM_CS_L<3>

AW13

AL20

SM_ODT3

MEM_CKE<0>
MEM_CKE<1>
MEM_CKE<2>
MEM_CKE<3>

AT20

SMOCDCOMP0

SM_ODT1
SM_ODT2

MEM_CLK_N<0>
MEM_CLK_N<1>
MEM_CLK_N<2>
MEM_CLK_N<3>

AT1

SM_CKE0
SM_CKE1

SM_ODT0

D1 NC0
C41 NC1
C1 NC2

AW7
AW40
AW35

SM_CKE3

MEM_CLK_P<0>
MEM_CLK_P<1>
MEM_CLK_P<2>
MEM_CLK_P<3>

AY35
AR1

SM_CK0*
SM_CK1*
SM_CK3*

DDR MUXING

5%
1/16W
MF-LF
2 402

CFG

10K

5%
1/16W
MF-LF
402 2

CLK

10K

65 64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66

PP3V3_S0

MISC
DMI

65 64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66

AE41

MEMORY_VREF
MEMORY_VREF
NB_CLK100M_GCLKIN_N
NB_CLK100M_GCLKIN_P
GND
GND
GND
GND
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

5 34

C1415

5 34

0.1uF

20%
10V
CERM 2
402

IN
IN
IN

C1416
0.1uF

20%
10V
2 CERM
402

14 28 29 32

R1411
80.6

1%
1/16W
MF-LF
2 402

IN
IN

OUT

5 22

OUT

5 22

OUT

5 22

OUT

5 22

OUT

BA3 NC6
BA2 NC7
BA1 NC8
B41 NC9
B2 NC10
AY41 NC11
AY1 NC12
AW41 NC13

AW1 NC14
A40 NC15
A4 NC16
A39 NC17
A3 NC18

NB Misc Interfaces
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

OMIT

28
28

BI
BI

28
28

BI
BI

AJ35 SA_DQ0
AJ34 SA_DQ1
AM31 SA_DQ2
AM33 SA_DQ3
AJ36 SA_DQ4
AK35 SA_DQ5
AJ32 SA_DQ6

BGA

AP24 SA_DQ29
AP20 SA_DQ30
AT21 SA_DQ31
AR12 SA_DQ32
AR14 SA_DQ33
AP13 SA_DQ34
AP12 SA_DQ35
AT13 SA_DQ36
AT12 SA_DQ37
AL14 SA_DQ38
AL12 SA_DQ39

AT5 SA_DQ46
AL5 SA_DQ47
AY2 SA_DQ48
AW2 SA_DQ49
AP1 SA_DQ50

AV14

SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

MEM_A_BS<0>
MEM_A_BS<1>
MEM_A_BS<2>

BA20

AM35
AL26
AN22
AM14
AL9
AR3
AH4
AK33

SA_DQS1

AT33
AN28

SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0*
SA_DQS1*
SA_DQS2*
SA_DQS3*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*

AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5
AY16

SA_MA1

AU14
AW16

SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_RAS*
SA_RCVENIN*

AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

OUT

28 30

OUT

28 30

OUT

28
28

OUT

28 30

OUT

28 30

OUT

28 30

OUT

28 30

OUT

28 30

OUT

28 30

OUT

28 30

OUT

28 30

OUT

28 30

OUT

28 30

28 30
28 30

OUT

MEM_A_RAS_L

AW14

28 30

OUT

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>

BA16
BA17

OUT

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

AM22

SA_MA0
SA_MA2
SA_MA3

MEM_A_CAS_L
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>

AY13
AJ33

SA_DQS0
SA_DQS2
SA_DQS3

AK9 SA_DQ40
AN7 SA_DQ41
AK8 SA_DQ42
AK7 SA_DQ43
AP9 SA_DQ44
AN9 SA_DQ45

SA_BS1
SA_BS2

SA_DM0
SA_DM1

AM36 SA_DQ13
AM34 SA_DQ14
AN33 SA_DQ15
AK26 SA_DQ16
AL27 SA_DQ17

AP23 SA_DQ24
AL22 SA_DQ25
AP21 SA_DQ26
AN20 SA_DQ27
AL23 SA_DQ28

AU12

SA_CAS*

AR31 SA_DQ10
AP31 SA_DQ11
AN38 SA_DQ12

AL28 SA_DQ21
AM24 SA_DQ22
AP26 SA_DQ23

SA_BS0

(4 OF 10)

AH31 SA_DQ7
AN35 SA_DQ8
AP33 SA_DQ9

AM26 SA_DQ18
AN24 SA_DQ19
AK28 SA_DQ20

U1200

945GM
NB

28 30

28 30
29

AN2 SA_DQ51
AV2 SA_DQ52
AT3 SA_DQ53

AN1 SA_DQ54
AL2 SA_DQ55
AG7 SA_DQ56

AF9 SA_DQ57
AG4 SA_DQ58
AF6 SA_DQ59
AG9 SA_DQ60
AH6 SA_DQ61

AF4 SA_DQ62
AF8 SA_DQ63

SA_RCVENOUT*
SA_WE*

AK23
AK24
AY14

NC
NC
MEM_A_WE_L

OUT

28 30

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

945GM
NB

AK39 SB_DQ0
AJ37 SB_DQ1

BGA

AP39 SB_DQ2
AR41 SB_DQ3
AJ38 SB_DQ4
AK38 SB_DQ5
AN41 SB_DQ6

SB_BS0

AT24

SB_BS1
SB_BS2

AV23

SB_CAS*

AR24
AK36

MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_BS<2>

AY28

(5 OF 10)
SB_DM0
SB_DM1
SB_DM2

AP41 SB_DQ7
AT40 SB_DQ8
AV41 SB_DQ9

SB_DM3
SB_DM4
SB_DM5

AU38 SB_DQ10
AV38 SB_DQ11
AP38 SB_DQ12

SB_DM6
SB_DM7

AR40 SB_DQ13
AW38 SB_DQ14
AY38 SB_DQ15
BA38 SB_DQ16
AV36 SB_DQ17
AR36 SB_DQ18
AP36 SB_DQ19
BA36 SB_DQ20
AU36 SB_DQ21
AP35 SB_DQ22
AP34 SB_DQ23
AY33 SB_DQ24
BA33 SB_DQ25
AT31 SB_DQ26
AU29 SB_DQ27
AU31 SB_DQ28
AW31 SB_DQ29
AV29 SB_DQ30
AW29 SB_DQ31
AM19 SB_DQ32
AL19 SB_DQ33
AP14 SB_DQ34
AN14 SB_DQ35
AN17 SB_DQ36
AM16 SB_DQ37
AP15 SB_DQ38
AL15 SB_DQ39

SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0*
SB_DQS1*
SB_DQS2*
SB_DQS3*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*

AN4

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

OUT

AY27
AR23

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>

SB_RAS*
SB_RCVENIN*

AU23

MEM_B_RAS_L

OUT

29 30

SB_RCVENOUT*

AK18
AR27

MEM_B_WE_L

OUT

29 30

SB_MA0

AY23

SB_MA1

AW24
AY24

SB_MA2
SB_MA3
SB_MA4
SB_MA5

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

AK10 SB_DQ46
AJ8 SB_DQ47
BA10 SB_DQ48
AW10 SB_DQ49
BA4 SB_DQ50

AH8
BA5

AT39
AU35

SB_MA7
SB_MA8

AN10 SB_DQ43
AK13 SB_DQ44
AH11 SB_DQ45

AL17

AM39

SB_MA6

AJ11 SB_DQ40
AH10 SB_DQ41
AJ9 SB_DQ42

AT36
BA31

SB_DQS1

SB_DQS4

MEM_B_CAS_L
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>

AR38

SB_DQS0
SB_DQS2
SB_DQS3

DDR SYSTEM MEMORY B

MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

DDR SYSTEM MEMORY A

OMIT

U1200
28

SB_WE*

AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27

AK16

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

OUT

29 30

NC
NC

AW4 SB_DQ51
AY10 SB_DQ52
AY9 SB_DQ53
AW5 SB_DQ54
AY5 SB_DQ55
AV4 SB_DQ56
AR5 SB_DQ57
AK4 SB_DQ58
AK3 SB_DQ59
AT4 SB_DQ60
AK5 SB_DQ61
AJ5 SB_DQ62
AJ3 SB_DQ63

NB DDR2 Interfaces
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

NCTF balls are Not Critical To Function

PP1V05_S0

AD27
AC27

VCC_NCTF0
VCC_NCTF1

AB27

VCC_NCTF2
VCC_NCTF3

AA27
Y27
W27
V27
U27

T27
R27
AD26

R26

0.47uF

20%
6.3V
CERM-X5R 2
402

C1615
0.47uF

66 63 54 37
19 14 5 4
32 31 29 28

Layout Note:
Place near pin BA23

0.47uF

20%
6.3V
2 CERM-X5R
402

VCC_106 N17
VCC_107 M17
VCC_108 N16

VCC_109 M16
VCC_110 L16

V23
U23
T23

NB_VCCSM_LF2
NB_VCCSM_LF1

C1620 1
10uF

20%
6.3V
X5R 2
603

C1621
10uF

C1610
0.47uF

20%
6.3V
2 CERM-X5R
402

20%
6.3V
2 X5R
603

C1612 1
0.47uF

20%
6.3V
CERM-X5R 2
402

0.47uF

U21
T21
R21

Layout Note:
Place in cavity

VCC_NCTF41
VCC_NCTF42

AD18
AC18

VCC_NCTF52
VCC_NCTF53

VCCAUX_NCTF40 W16
VCCAUX_NCTF41 V16
VCCAUX_NCTF42 U16
VCCAUX_NCTF43 T16
VCCAUX_NCTF44 R16

VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF63
VCC_NCTF64

VCCAUX_NCTF48 AD15
VCCAUX_NCTF49 AC15
VCCAUX_NCTF50 AB15

VCC_NCTF65

VCC_NCTF68
VCC_NCTF69

VCCAUX_NCTF45 AG15
VCCAUX_NCTF46 AF15
VCCAUX_NCTF47 AE15

VCC_NCTF62

Y18

T18

VCCAUX_NCTF37 AB16
VCCAUX_NCTF38 AA16
VCCAUX_NCTF39 Y16

VCC_NCTF54

VCC_NCTF66
VCC_NCTF67

U18

VCCAUX_NCTF34 AE16
VCCAUX_NCTF35 AD16
VCCAUX_NCTF36 AC16

VCC_NCTF51

AB18
AA18
W18
V18

VCCAUX_NCTF31 R17
VCCAUX_NCTF32 AG16
VCCAUX_NCTF33 AF16

VCC_NCTF49
VCC_NCTF50

VCC_NCTF57
VCC_NCTF58

T19

VCCAUX_NCTF29 V17
VCCAUX_NCTF30 T17

VCC_NCTF48

U20

V19
U19

VCCAUX_NCTF26 AB17
VCCAUX_NCTF27 AA17
VCCAUX_NCTF28 W17

VCC_NCTF43

VCC_NCTF55
VCC_NCTF56

AD19

VCCAUX_NCTF23 AF17
VCCAUX_NCTF24 AE17
VCCAUX_NCTF25 AD17

VCC_NCTF40

AD20
V20
T20
R20

VCCAUX_NCTF20 AF18
VCCAUX_NCTF21 R18
VCCAUX_NCTF22 AG17

VCC_NCTF38
VCC_NCTF39

VCC_NCTF46
VCC_NCTF47

VCCAUX_NCTF18 R19
VCCAUX_NCTF19 AG18

VCC_NCTF37

V22

AD21
V21

Layout Note:
Place near pin BA15

VCCAUX_NCTF15 AF20
VCCAUX_NCTF16 AG19
VCCAUX_NCTF17 AF19

VCC_NCTF32

VCC_NCTF44
VCC_NCTF45

R22

20%
6.3V
2 CERM-X5R
402

VCCAUX_NCTF12 AG21
VCCAUX_NCTF13 AF21
VCCAUX_NCTF14 AG20

VCC_NCTF30
VCC_NCTF31

R23
AD22
U22
T22

C1611

VCCAUX_NCTF9 AF23
VCCAUX_NCTF10 AG22
VCCAUX_NCTF11 AF22

VCC_NCTF29

VCC_NCTF35
VCC_NCTF36

R24
AD23

VCCAUX_NCTF7 AF24
VCCAUX_NCTF8 AG23

VCC_NCTF27
VCC_NCTF28

W24

T24

VCCAUX_NCTF4 AG25
VCCAUX_NCTF5 AF25
VCCAUX_NCTF6 AG24

VCC_NCTF26

VCC_NCTF33
VCC_NCTF34

25 47 65
5 8 9 13
17 19 24
66

VCCAUX_NCTF2 AG26
VCCAUX_NCTF3 AF26

VCC_NCTF21

AA24
Y24
V24
U24

AV1 VCC_SM106
AJ1 VCC_SM107

VCC_103 M18
VCC_104 L18
VCC_105 P17
AL6 VCC_SM103
AK6 VCC_SM104
AJ6 VCC_SM105

VCC_98 Y19
VCC_99 N19
VCC_100 M19
VCC_101 L19
VCC_102 N18

AY6 VCC_SM96
AW6 VCC_SM97
AV6 VCC_SM98
AT6 VCC_SM99

AR8 VCC_SM93
AP8 VCC_SM94
BA6 VCC_SM95

AW8 VCC_SM90
AV8 VCC_SM91
AT8 VCC_SM92

AK11 VCC_SM87
BA8 VCC_SM88
AY8 VCC_SM89

AJ12 VCC_SM84
AH12 VCC_SM85
AG12 VCC_SM86

AJ13 VCC_SM81
AH13 VCC_SM82
AK12 VCC_SM83

AR15 VCC_SM78
AJ15 VCC_SM79
AJ14 VCC_SM80

AW15 VCC_SM74
AV15 VCC_SM75
AU15 VCC_SM76
AT15 VCC_SM77

AH16 VCC_SM71
BA15 VCC_SM72
AY15 VCC_SM73

AJ17 VCC_SM68
AH17 VCC_SM69
AJ16 VCC_SM70

AK19 VCC_SM65
AJ19 VCC_SM66
AJ18 VCC_SM67

AT19 VCC_SM62
AR19 VCC_SM63
AP19 VCC_SM64

AW19 VCC_SM59
AV19 VCC_SM60
AU19 VCC_SM61

AR6 VCC_SM100
AP6 VCC_SM101
AN6 VCC_SM102

VCC_95 L20
VCC_96 AB19
VCC_97 AA19

VCC_92 P20
VCC_93 N20
VCC_94 M20

VCC_90 Y20
VCC_91 W20

VCC_87 L21
VCC_88 AC20
VCC_89 AB20

VCC_84 W21
VCC_85 N21
VCC_86 M21

VCC_81 L22
VCC_82 AC21
VCC_83 AA21

VCC_79 N22
VCC_80 M22

VCC_76 Y22
VCC_77 W22
VCC_78 P22

VCC_73 L23
VCC_74 AC22
VCC_75 AB22

VCC_70 P23
VCC_71 N23
VCC_72 M23

VCC_68 AA23
VCC_69 Y23

VCC_65 N24
VCC_66 M24
VCC_67 AB23

VCC_62 M25
VCC_63 L25
VCC_64 P24

VCC_59 N26
VCC_60 L26
VCC_61 N25

VCC_57 L27
VCC_58 P26

PP1V8_S3

20%
2 6.3V
CERM-X5R
402

C1613

AK20 VCC_SM56
BA19 VCC_SM57
AY19 VCC_SM58

AP22 VCC_SM52
AK22 VCC_SM53
AJ22 VCC_SM54
AK21 VCC_SM55

AU22 VCC_SM49
AT22 VCC_SM50
AR22 VCC_SM51

AY22 VCC_SM46
AW22 VCC_SM47
AV22 VCC_SM48

BA23 VCC_SM43
AJ23 VCC_SM44
BA22 VCC_SM45

AH25 VCC_SM40
AJ24 VCC_SM41
AH24 VCC_SM42

AJ26 VCC_SM37
AH26 VCC_SM38
AJ25 VCC_SM39

AU26 VCC_SM34
AT26 VCC_SM35
AR26 VCC_SM36

BA26 VCC_SM30
AY26 VCC_SM31
AW26 VCC_SM32
AV26 VCC_SM33

AH28 VCC_SM27
AJ27 VCC_SM28
AH27 VCC_SM29

AJ29 VCC_SM24
AH29 VCC_SM25
AJ28 VCC_SM26

AM29 VCC_SM21
AL29 VCC_SM22
AK29 VCC_SM23

AP30 VCC_SM18
AN30 VCC_SM19
AM30 VCC_SM20

AU30 VCC_SM15
AT30 VCC_SM16
AR30 VCC_SM17

AY30 VCC_SM12
AW30 VCC_SM13
AV30 VCC_SM14

AU34 VCC_SM8
AT34 VCC_SM9
AR34 VCC_SM10
BA30 VCC_SM11

NB_VCCSM_LF4
NB_VCCSM_LF5

C1614 1

VCC_54 P27
VCC_55 N27
VCC_56 M27

VCC_51 N28
VCC_52 M28
VCC_53 L28

VCC_48 T28
VCC_49 R28
VCC_50 P28

VCC_46 V28
VCC_47 U28

VCC_43 AB28
VCC_44 AA28
VCC_45 Y28

VCC_40 P29
VCC_41 M29
VCC_42 L29

VCC_37 V29
VCC_38 U29
VCC_39 R29

VCC_35 Y29
VCC_36 W29

VCC_32 M30
VCC_33 L30
VCC_34 AA29

VCC_29 R30
VCC_30 P30
VCC_31 N30

VCC_26 V30
VCC_27 U30
VCC_28 T30

VCC_24 Y30
VCC_25 W30

VCC_21 N31
VCC_22 M31
VCC_23 AA30

VCC_18 T31
VCC_19 R31
VCC_20 P31

VCC_15 AA31
VCC_16 W31
VCC_17 V31

VCC_12 M32
VCC_13 L32
VCC_14 J32

VCC_10 P32
VCC_11 N32

VCC_7 Y32
VCC_8 W32
VCC_9 V32

VCC_4 L33
VCC_5 J33
VCC_6 AA32

BGA

(6 OF 10)

AY34 VCC_SM5
AW34 VCC_SM6
AV34 VCC_SM7

AM41 VCC_SM2
AU40 VCC_SM3
BA34 VCC_SM4

945GM
NB

VCC_0 AA33
VCC_1 W33
VCC_2 P33
VCC_3 N33

U1200
AU41 VCC_SM0
AT41 VCC_SM1

OMIT

AC24
AB24

VSS_NCTF8 AE19
VSS_NCTF9 AE18
VSS_NCTF10 AC17

PP1V5_S0

VCC_NCTF19
VCC_NCTF20

VCC_NCTF24
VCC_NCTF25

T25
R25

VSS_NCTF5 AE22
VSS_NCTF6 AE21
VSS_NCTF7 AE20

VCCAUX_NCTF0 AG27
VCCAUX_NCTF1 AF27

VCC_NCTF18

Y25

AD24

VSS_NCTF3 AE24
VSS_NCTF4 AE23

VSS_NCTF11 Y17
VSS_NCTF12 U17

VCC_NCTF16
VCC_NCTF17

VCC_NCTF22
VCC_NCTF23

U25

VSS_NCTF0 AE27
VSS_NCTF1 AE26
VSS_NCTF2 AE25

VCC_NCTF15

AB25
AA25
W25
V25

1.8V Max Current

Speed
1 Channel
2 Channel
400MTs
1300mA
2400mA
533MTs
1500mA
2800mA
667MTs
1700mA
3200mA

VCC

64 66
5 7 8
17 19

VCC_NCTF10

VCC_NCTF13
VCC_NCTF14

AD25
AC25

BGA
(7 OF 10)

VCC_NCTF8
VCC_NCTF9

AA26

U26
T26

945GM
NB

VCC_NCTF7

VCC_NCTF11
VCC_NCTF12

V26

PP1V05_S0
1.05V or 1.5V

VCC_NCTF5
VCC_NCTF6

AC26
AB26
Y26
W26

1.05V, Internal Graphics: 3500mA Max

1.05V, External Graphics: 1500mA Max
9 11 12 13 16
21 24 25 34 54 1.5V,
Internal Graphics: 5500mA Max

VCC_NCTF4

U1200

NCTF

21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

These connections can break without

impacting part performance.
OMIT

VCCAUX_NCTF51 AA15
VCCAUX_NCTF52 Y15
VCCAUX_NCTF53 W15
VCCAUX_NCTF54 V15
VCCAUX_NCTF55 U15

VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

VCCAUX_NCTF56 T15
VCCAUX_NCTF57 R15

NB Power 1
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

70mA Max VCCA_CRTDAC/VCCSYNC

OMIT

GND

H22 VCCSYNC

GND
60mA Max

C30 VCC_TXLVDS0
B30 VCC_TXLVDS1
A30 VCC_TXLVDS2

PP1V5_S0_NB_VCC3G

U1200
945GM
NB
BGA
(8 OF 10)

AJ41 VCC3G0
AB41 VCC3G1
Y41 VCC3G2
V41 VCC3G3
R41 VCC3G4

1500mA Max VCC3G/3GPLL

N41 VCC3G5
19
77 76 66 65 62 19 5

21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

PP1V5_S0_NB_VCCA_3GPLL
PP2V5_S0
GND

L41 VCC3G6
AC33 VCCA_3GPLL
G41 VCCA_3GBG 2mA
H41 VSSA_3GBG
F21 VCCA_CRTDAC0
E21 VCCA_CRTDAC1
G21 VSSA_CRTDAC

PP1V05_S0
GND

See VCCSYNC

TP_NB_VCCA_DPLLA
TP_NB_VCCA_DPLLB
PP1V5_S0_NB_VCCA_HPLL
GND
NC_GND_NB_VSSA_LVDS

A38 VCCA_LVDS
B39 VSSA_LVDS

10mA Max

PP1V5_S0_NB_VCCA_MPLL

AF2 VCCA_MPLL

45mA Max

PP1V5_S0
GND

H20 VCCA_TVBG
G20 VSSA_TVBG

PP1V5_S0

E20 VCCA_TVDACC0
F20 VCCA_TVDACC1
C20 VCCA_TVDACB0

65 47 25 24 19 17 16 13 9 8 5
66

Max

B26 VCCA_DPLLA
C39 VCCA_DPLLB

65 47 25 24 19 17 16 13 9 8 5
66

AF1 VCCA_HPLL

PP1V5_S0

50mA Max
50mA Max
45mA Max

PP1V5_S0

AH1 VCCD_HMPLL0
AH2 VCCD_HMPLL1

GND
20mA Max

A28 VCCD_LVDS0
B28 VCCD_LVDS1

120mA Max

150mA Max

66 65 64 60 59 57 56 53 51 48
24 23 22 21 20 19 14 10 5 4
43 37 36 34 33 29 28 27 26 25
79 78 70

65 47 25 24 19 17 16 13 9 8 5
66
65 47 25 24 19 17 16 13 9 8 5
66

PP1V5_S0

D21 VCCD_TVDAC

PP3V3_S0
40mA Max

A23 VCC_HV0
B23 VCC_HV1
B25 VCC_HV2

PP1V5_S0

H19 VCCD_QTVDAC

PP1V5_S0
1900mA Max

AK31 VCCAUX0
AF31 VCCAUX1
AE31 VCCAUX2
AC31 VCCAUX3
AL30 VCCAUX4
AK30 VCCAUX5
AJ30 VCCAUX6
AH30 VCCAUX7
AG30 VCCAUX8
AF30 VCCAUX9
AE30 VCCAUX10
AD30 VCCAUX11
AC30 VCCAUX12

VTT6 P14
VTT7 N14
VTT8 M14

VTT9 L14
VTT10 AD13
VTT11 AC13
VTT12 AB13
VTT13 AA13
VTT14 Y13
VTT15 W13
VTT16 V13
VTT17 U13
VTT18 T13
VTT19 R13
VTT20 N13
VTT21 M13
VTT22 L13
VTT23 AB12
VTT24 AA12
VTT25 Y12

VTT28 U12
VTT29 T12
VTT30 R12
VTT31 P12
VTT32 N12
VTT33 M12

VTT34 L12
VTT35 R11
VTT36 P11

VTT39 R10
VTT40 P10
VTT41 N10

24mA Max

VTT42 M10
VTT43 P9
VTT44 N9
VTT45 M9
VTT46 R8
VTT47 P8
VTT48 N8
VTT49 M8
VTT50 P7
VTT51 N7
VTT52 M7
VTT53 R6
VTT54 P6
VTT55 M6

NB_VTTLF_CAP3

VTT56 A6
VTT57 R5
VTT58 P5

C1713

AD29 VCCAUX16
AC29 VCCAUX17
AG28 VCCAUX18

VTT64 R3
VTT65 P3
VTT66 N3

AF28 VCCAUX19
AE28 VCCAUX20
AH22 VCCAUX21

VTT67 M3
VTT68 R2
VTT69 P2

AJ21 VCCAUX22
AH21 VCCAUX23
AJ20 VCCAUX24

VTT70 M2
VTT71 D2

0.47uF

VTT59 N5
VTT60 M5
VTT61 P4
VTT62 N4
VTT63 M4

P16 VCCAUX28
AH15 VCCAUX29
P15 VCCAUX30
AH14 VCCAUX31

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

VTT3 V14
VTT4 T14
VTT5 R14

AG29 VCCAUX13
AF29 VCCAUX14
AE29 VCCAUX15

AH20 VCCAUX25
AH19 VCCAUX26
P19 VCCAUX27

PP1V05_S0
800mA Max

VTT37 N11
VTT38 M11

C28 VCCD_LVDS2
65 47 25 24 19 17 16 13 9 8 5
66

VTT0 AC14
VTT1 AB14
VTT2 W14

VTT26 W12
VTT27 V12

D20 VCCA_TVDACB1
E19 VCCA_TVDACA0
F19 VCCA_TVDACA1

PP1V5_S0

POWER

20%
6.3V
CERM-X5R 2
402

VTT72 AB1
VTT73 R1
VTT74 P1

NB_VTTLF_CAP2
NB_VTTLF_CAP1

C1711

0.47uF

VTT75 N1
VTT76 M1

20%
6.3V
CERM-X5R 2
402

C1712
0.22uF

20%
2 6.3V
X5R
402

AG14 VCCAUX32
AF14 VCCAUX33
AE14 VCCAUX34
Y14 VCCAUX35
AF13 VCCAUX36
AE13 VCCAUX37
AF12 VCCAUX38

NB Power 2
SYNC_MASTER=M1_MLB

AE12 VCCAUX39
AD12 VCCAUX40

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

OMIT
AC41
AA41
W41
T41

VSS_0
VSS_1
VSS_2
VSS_3

P41
M41

VSS_4
VSS_5

J41

VSS_6
VSS_7

F41
AV40

U1200
945GM
NB
BGA
(9 OF 10)

VSS_106 AE33
VSS_107 AB33
VSS_108 Y33

AJ40 VSS_12
AH40 VSS_13
AG40 VSS_14

VSS_109 V33
VSS_110 T33
VSS_111 R33

AF40 VSS_15
AE40 VSS_16
B40 VSS_17

VSS_112 M33
VSS_113 H33
VSS_114 G33

AY39 VSS_18
AW39 VSS_19
AV39 VSS_20

VSS_115 F33
VSS_116 D33

AC39 VSS_24
AB39 VSS_25
AA39 VSS_26
Y39 VSS_27
W39 VSS_28
V39 VSS_29
T39 VSS_30

H39 VSS_37
G39 VSS_38
F39 VSS_39

VSS_134 E30
VSS_135 AT29
VSS_136 AN29

D39 VSS_40
AT38 VSS_41
AM38 VSS_42

VSS_137 AB29
VSS_138 T29

AB21 VSS_202
Y21 VSS_203
P21 VSS_204
K21 VSS_205
J21 VSS_206
H21 VSS_207
C21 VSS_208

M37 VSS_59
L37 VSS_60
J37 VSS_61

VSS_156 AP27
VSS_157 AM27
VSS_158 AK27

H37 VSS_62
G37 VSS_63
F37 VSS_64

VSS_159 J27
VSS_160 G27

VSS_175 A25
VSS_176 BA24
VSS_177 AU24

AA35 VSS_81
Y35 VSS_82
W35 VSS_83

VSS_178 AL24
VSS_179 AW23

P35 VSS_87
N35 VSS_88
M35 VSS_89

VSS_286 AR9
VSS_287 AH9
VSS_288 AB9
VSS_289 Y9
VSS_290 R9
VSS_291 G9
VSS_292 E9
VSS_293 A9
VSS_294 AG8
VSS_295 AD8
VSS_296 AA8
VSS_297 U8
VSS_298 K8
VSS_299 C8
VSS_300 BA7
VSS_301 AV7

VSS_311 AG6
VSS_312 AD6
VSS_313 AB6
VSS_314 Y6
VSS_315 U6
VSS_316 N6
VSS_317 K6
VSS_318 H6
VSS_319 B6
VSS_320 AV5
VSS_321 AF5
VSS_322 AD5
VSS_323 AY4
VSS_324 AR4
VSS_325 AP4
VSS_326 AL4

AL16 VSS_234
J16 VSS_235
F16 VSS_236

VSS_327 AJ4
VSS_328 Y4
VSS_329 U4

C16 VSS_237
AN15 VSS_238
AM15 VSS_239

VSS_330 R4
VSS_331 J4
VSS_332 F4

AK15 VSS_240
N15 VSS_241
M15 VSS_242

VSS_333 C4
VSS_334 AY3
VSS_335 AW3
VSS_336 AV3
VSS_337 AL3

VSS_338 AH3
VSS_339 AG3
VSS_340 AF3
VSS_341 AD3
VSS_342 AC3
VSS_343 AA3
VSS_344 G3
VSS_345 AT2

H14 VSS_253
E14 VSS_254
AV13 VSS_255

VSS_346 AR2
VSS_347 AP2
VSS_348 AK2

AR13 VSS_256
AN13 VSS_257
AM13 VSS_258

VSS_349 AJ2
VSS_350 AD2
VSS_351 AB2

AL13 VSS_259
AG13 VSS_260
P13 VSS_261

VSS_352 Y2
VSS_353 U2
VSS_354 T2

F13 VSS_262
D13 VSS_263
B13 VSS_264

VSS_355 N2
VSS_356 J2

AY12 VSS_265
AC12 VSS_266
K12 VSS_267

VSS_283 U10
VSS_284 BA9
VSS_285 AW9

AK17 VSS_231
AV16 VSS_232
AN16 VSS_233

AA14 VSS_250
U14 VSS_251
K14 VSS_252

V35 VSS_84
T35 VSS_85
R35 VSS_86

VSS

VSS_308 R7
VSS_309 G7
VSS_310 D7

BA14 VSS_246
AT14 VSS_247
AK14 VSS_248
AD14 VSS_249

VSS_170 P25
VSS_171 K25

VSS_280 AG10
VSS_281 AC10
VSS_282 W10

A20 VSS_215
AN19 VSS_216
AC19 VSS_217

L15 VSS_243
B15 VSS_244
A15 VSS_245

VSS_167 F26
VSS_168 D26
VSS_169 AK25

AR35 VSS_78
AH35 VSS_79
AB35 VSS_80

VSS_278 AL10
VSS_279 AJ10

VSS_305 AH7
VSS_306 AF7
VSS_307 AC7

AR17 VSS_228
AP17 VSS_229
AM17 VSS_230

VSS_164 AN26
VSS_165 M26
VSS_166 K26

VSS_172 H25
VSS_173 E25
VSS_174 D25

(10 OF 10)

VSS_275 B11
VSS_276 AV10
VSS_277 AP10

AA20 VSS_212
K20 VSS_213
B20 VSS_214

H18 VSS_224
D18 VSS_225
A18 VSS_226
AY17 VSS_227

VSS_161 F27
VSS_162 C27
VSS_163 B27

B36 VSS_75
BA35 VSS_76
AV35 VSS_77

BGA

VSS_273 J11
VSS_274 D11

VSS_302 AP7
VSS_303 AL7
VSS_304 AJ7

C19 VSS_221
AH18 VSS_222
P18 VSS_223

VSS_148 AU28
VSS_149 AP28

VSS_153 W28
VSS_154 J28
VSS_155 E28

945GM
NB

AW20 VSS_209
AR20 VSS_210
AM20 VSS_211

W19 VSS_218
K19 VSS_219
G19 VSS_220

VSS_145 A29
VSS_146 BA28
VSS_147 AW28

R37 VSS_56
P37 VSS_57
N37 VSS_58

AE36 VSS_72
AC36 VSS_73
C36 VSS_74

AR21 VSS_199
AN21 VSS_200
AL21 VSS_201

VSS_142 E29
VSS_143 C29
VSS_144 B29

VSS_150 AM28
VSS_151 AD28
VSS_152 AC28

AN36 VSS_68
AH36 VSS_69
AG36 VSS_70
AF36 VSS_71

A22 VSS_196
BA21 VSS_197
AV21 VSS_198

VSS_139 N29
VSS_140 K29
VSS_141 G29

W37 VSS_53
V37 VSS_54
T37 VSS_55

D37 VSS_65
AY36 VSS_66
AW36 VSS_67

F22 VSS_193
E22 VSS_194
D22 VSS_195

VSS_126 AY31
VSS_127 AV31

VSS_131 AB31
VSS_132 Y31
VSS_133 AB30

AB37 VSS_50
AA37 VSS_51
Y37 VSS_52

AA22 VSS_190
K22 VSS_191
G22 VSS_192

VSS_123 AB32
VSS_124 G32
VSS_125 B32

M39 VSS_34
L39 VSS_35
J39 VSS_36

U1200

J23 VSS_187
F23 VSS_188
C23 VSS_189

VSS_120 AF32
VSS_121 AE32
VSS_122 AC32

VSS_128 AN31
VSS_129 AJ31
VSS_130 AG31

AE38 VSS_46
C38 VSS_47
AK37 VSS_48
AH37 VSS_49

AC23 VSS_184
W23 VSS_185
K23 VSS_186

VSS_117 B33
VSS_118 AH32
VSS_119 AG32

R39 VSS_31
P39 VSS_32
N39 VSS_33

AH38 VSS_43
AG38 VSS_44
AF38 VSS_45

VSS_101 AC34
VSS_102 C34
VSS_103 AW33

VSS_9
AN40 VSS_10
AK40 VSS_11

AR39 VSS_21
AN39 VSS_22
AJ39 VSS_23

AT23 VSS_180
AN23 VSS_181
AM23 VSS_182
AH23 VSS_183

VSS_99 AF34
VSS_100 AE34

VSS_8

VSS

OMIT
VSS_97 AK34
VSS_98 AG34

VSS_104 AV33
VSS_105 AR33

AP40

VSS_357 H2
VSS_358 F2
VSS_359 C2

NB Grounds

VSS_360 AL1

H12 VSS_268
E12 VSS_269
AD11 VSS_270
AA11 VSS_271

L35 VSS_90
J35 VSS_91
H35 VSS_92
G35 VSS_93

SYNC_MASTER=M1_MLB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

Y11 VSS_272

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

F35 VSS_94
D35 VSS_95
AN34 VSS_96

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

06
86

7
21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

Power Interface

(MCH LVDS DATA/CLK TX 2.5V PWR)

PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0

19 13

TP_LVDS_BKLTCTL

9 11 12 13 16 17 19 21 24
54 64 66
9 11 12 13 16 17 19 21 24
54 64 66

19 13

TP_LVDS_BKLTEN

9 11 12 13 16 17 19 21 24
54 64 66

19 13

TP_LVDS_CLKCTLA

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66
5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

19 13

TP_LVDS_CLKCTLB

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

19 13

TP_LVDS_DDC_CLK

19 13

TP_LVDS_DDC_DATA

1500mA Max

19 13

NC_LVDS_IBG

?mA
100mA
24mA
150mA
1900mA

19 13

TP_LVDS_VDDEN

19 13

NC_LVDS_VREFH

19 13

TP_LVDS_VREFL

These are the power signals that leave the NB "block"

2310mA Max?
21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

21 19 17 16 13 12 11 9 8
66 64 54 34 25
21 19 17 16 13 12 11 9 8
66 64 54 34 25

7 5
24
7 5
24

65 47 25 24 19 17 16 13 9 8 5
66

65 47 25 24 19 17 16 13 9 8 5
66
65 47 25 24 19 17 16 13 9 8 5
66

65 47 25 24 19 17 16 13 9 8 5
66

PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0

PP1V8_S3

3674mA Max

PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0

3200mA Max
132mA Max

IN
IN

77 76 66 65 62 19 17 5

40mA Max?

65
37
23 22 21 20 19 17 14 10 5 4
36 34 33 29 28 27 26 25 24
64 60 59 57 56 53 51 48 43
79 78 70 66

IN
IN
IN

1500mA
10mA
800mA
?mA

Max
Max?
Max
Max

?mA Max

3200mA Max

GND
GND
PP2V5_S0

19 13

TP_CRT_DDC_CLK

5 7 8
25 34
5 7 8
25 34
5 7 8
25 34

TP_CRT_DDC_CLK

13 19

MAKE_BASE=TRUE
19 13

TP_CRT_DDC_DATA

13 19

MAKE_BASE=TRUE

65 47 25 24 19 17 16 13 9 8 5
66

PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0

?mA Max
40mA Max

MAKE_BASE=TRUE

(MCH LVDS DIGITAL 1.5V PWR)

TP_LVDS_CLKCTLB

13 19

TP_LVDS_DDC_CLK

13 19

(MCH LVDS ANALOG 2.5V PWR)

TP_LVDS_DDC_DATA

13 19

GND

NC_LVDS_IBG

13 19

TP_LVDS_VDDEN

13 19

NC_LVDS_VREFH

13 19

NO_TEST=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

19 17

NO_TEST=TRUE

TP_LVDS_VREFL

MAKE_BASE=TRUE

19 13

NC_LVDS_A_CLKN

NC_LVDS_A_DATAP<2..0>

5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66

NC_LVDS_A_DATAN<2..0>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

(MCH CRTDAC ANALOG 2.5V PWR)

PP1V05_S0

C1900

470uF-9MOHM

20%
3 2 2.5V
POLY
D2TS

C1902

10uF

C1903
10uF

20%
2 6.3V
X5R
603

C1904
1uF

C1905

0.22uF

C1906
0.22uF

20%
2 6.3V
X5R
402

10%
2 6.3V
CERM
402

20%
2 6.3V
X5R
402

5 7 8 9 11 12 13 16 17
19 21 24 25 34 54 64 66

LVDS_A_DATA_P<2..0>

(MCH H/V SYNC 2.5V PWR)

LVDS_A_DATA_N<2..0>

GND

NC_LVDS_B_CLKP

13 19

NC_LVDS_B_CLKN

13 19

NO_TEST=TRUE

NC_LVDS_B_DATAP<2..0>

NC_LVDS_B_DATAN<2..0>

LVDS_B_DATA_P<2..0>

47 25 24 19 17 16 13 9 8 5
66 65

(MCH TVDAC DEDICATED PWR 1.5V)

PP1V5_S0

NO_TEST=TRUE

19 14

NC_NB_XOR_LVDS_A34

19 14

NC_NB_XOR_LVDS_A35

19 14

NC_NB_XOR_LVDS_D27

19 14

NC_NB_XOR_LVDS_D28

5 8 9 13 16 17 19 24 25
47 65 66

LVDS_B_DATA_N<2..0>

NO_TEST=TRUE

(MCH TVDAC DIGITAL QUIET 1.5V PWR)

NC_NB_XOR_LVDS_A34

14 19

NC_NB_XOR_LVDS_A35

14 19

NC_NB_XOR_LVDS_D27

14 19

(MCH TV OUT CHANNEL A 3.3V PWR)

NC_NB_XOR_LVDS_D28

14 19

PP1V5_S0

TP_SDVO_CTRLCLK

14 19

(MCH TV OUT CHANNEL B 3.3V PWR)

TP_SDVO_CTRLDATA

14 19

PP1V5_S0

NO_TEST=TRUE

PP1V5_S0

5 8 9 13 16 17 19 24 25
47 65 66

NO_TEST=TRUE
NO_TEST=TRUE

5 8 9 13 16 17 19 24 25
47 65 66

NO_TEST=TRUE

19 14

TP_SDVO_CTRLCLK

19 14

TP_SDVO_CTRLDATA

MAKE_BASE=TRUE
MAKE_BASE=TRUE

CRITICAL
1

17 19

GND

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GND_NB_VSSA_LVDS

NO_TEST=TRUE

NC_LVDS_B_CLKN

MAKE_BASE=TRUE

13 19

NC_GND_NB_VSSA_LVDS
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_CLKP

MAKE_BASE=TRUE

13 19

NC_LVDS_A_CLKN

NO_TEST=TRUE

19 13

MAKE_BASE=TRUE

13 19
21 19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24

NC_LVDS_A_CLKP

NO_TEST=TRUE

19 13

MAKE_BASE=TRUE

GND

MAKE_BASE=TRUE

13 19

MAKE_BASE=TRUE

19 13

GMCH CORE PWR 1.05V BYPASS

13 19

MAKE_BASE=TRUE

PP1V05_S0
1500mA Max

TP_LVDS_BKLTEN
TP_LVDS_CLKCTLA

MAKE_BASE=TRUE

25 24 21 19
11 9 8 7 5
17 16 13 12
66 64 54 34

13 19

MAKE_BASE=TRUE

5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66

5 8 9 13 16 17 19 24 25 47 65
66

TP_LVDS_BKLTCTL

MAKE_BASE=TRUE

NC_LVDS_A_CLKP

PP1V5_S0

70mA Max
60mA Max
2mA Max

PP3V3_S0
PP3V3_S0

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

GND
GND

Max
Max
Max
Max
Max

PP1V05_S0

Rail Totals:
IN

5 8 9 13 16 17 19 24 25
47 65 66

C1907

(MCH TV OUT CHANNEL C 3.3V PWR)

0.22uF

PP1V5_S0

20%
2 6.3V
X5R
402

5 8 9 13 16 17 19 24 25
47 65 66

(MCH TV DAC BAND GAP 3.3V PWR)

PP1V5_S0

5 8 9 13 16 17 19 24 25
47 65 66

GND

(MCH DISPLAY A PLL 1.5V PWR)

66 64 54 34
13 12 11 9 8 7 5
25 24 21 19 17 16

MCH VTT BYPASS

79 78 70 66 65
53 51 48 43 37 36 34 33 29
(MCH FSB 1.05V PWR)
23 22 21 20 19 17 14 10 5
27 26 25
(SHARE C0940 470UF) 60 59 57

PP1V05_S0
800mA Max
1

C1965
4.7uF

20%
2 6.3V
CERM
603

C1966

2.2uF

64
28
4
24
56

MCH VCCA_3GBG BYPASS

(MCH PCIE/DMI BAND GAP 2.5V PWR)

PP3V3_S0
40mA Max

C1967

77 76 66 65 62 19 17 5

C1914 1

0.22uF

10uF

20%
2 6.3V
X5R
402

20%
2 6.3V
CERM1
603

19 17

MCH VCC_HV BYPASS

(MCH HV BUFFER 3.3V PWR)

20%
6.3V 2
X5R
603

PP2V5_S0
2mA Max

65 47 25 24 19 17 16 13 9 8 5
66

C1915
0.1uF

TP_NB_VCCA_DPLLA

GMCH VCCAUX FILTER

(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)
TP_NB_VCCA_DPLLB

TP_NB_VCCA_DPLLB

17 19

MAKE_BASE=TRUE

C1918 1

20%
10V
CERM 2
402

0.1uF

17 19

(MCH DISPLAY B PLL 1.5V PWR)

19 17

PP1V5_S0
1900mA Max

C1916 1

20%
2 10V
CERM
402

TP_NB_VCCA_DPLLA
MAKE_BASE=TRUE

0.1uF

GND
GND

Layout Note:
Place in cavity

Layout Note:
Place on the edge

GND
GND

B
GMCH VCC3G FILTER
(PCI-E/DMI ANALOG 1.5V PWR)

L1970
GMCH VCCA_HPLL FILTER
(HOST PLL 1.5V PWR)
PP1V5_S0_NB_VCCA_HPLL

L1934

24 19 17 16 13 9 8 5
66 65 47 25

PP1V5_S0
100mA Max

FERR-120-OHM-0.2A
1

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.5V

2
0603
1

22UF

Layout Note:
Place L and C
close to MCH

C1935

20%
2 10V
CERM
402

1500mA Max

GMCH VCCA_MPLL FILTER

(MCH MEMORY PLL 1.5V PWR)
PP1V5_S0_NB_VCCA_MPLL 17

L1936

FERR-120-OHM-0.2A
0603

13 9 8 5
66 65 47 25 24 19 17 16

45mA Max

C1936 1

22UF

PP1V5_S0

C1937
0.1uF

20%
2 10V
CERM
402

20%
6.3V 2
CERM
805

20%
2 6.3V
X5R
603

20%
2 2.5V
POLY
SMB2

C1972
10uF

20%
2 6.3V
X5R
603

Layout Note:
10uF caps should
be close to MCH
on opposite side.

1500mA Max

GMCH VCCA_3GPLL FILTER

(3GIO PLL 1.5V PWR)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=1.5V

R1975
1

PP1V5_S0_NB_VCCA_3GPLL

0.51 2
1%
1/16W
MF-LF
402

Layout Note:
3GPLL 10uF cap should
be placed in cavity

C1971
10uF

220UF

1.0UH-220MA-0.12-OHM
1
2
PP1V5_S0_NB_3GPLL_F
0805

C1970

L1975

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.5V

PP1V5_S0_NB_VCC3G
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.5V

2
1210

0.1uF

20%
6.3V 2
CERM
805

91nH

PP1V5_S0

45mA Max

C1934 1

66 65 47 25
13 9 8 5
24 19 17 16

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.5V

C1975 1
10uF

20%
6.3V 2
X5R
603

C1976
0.1uF

20%
2 10V
CERM
402

NB (GM) Decoupling

GND

SYNC_MASTER=M1_MLB

Layout Note: Route to caps, then GND

SYNC_DATE=02/08/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Internal pull-ups

NB_CFG<13:12>
NB_CFG<3>

RESERVED

NB_CFG<4>

RESERVED

NB_CFG<5>
Internal pull-up

00
01
10
11

=
=
=
=

Partial Clock Gating Disable

XOR Mode Enabled
All-Z Mode Enabled
Normal Operation

NB_CFG<14>

RESERVED

NB_CFG<15>

RESERVED

NBCFG_DMI_X2
1

R2075

NB_CFG<5>

High = DMIx4

DMI x2 Select

Low

= DMIx2

2.2K
5%
1/16W
MF-LF
2 402

PROBABLY NOT NEEDED

NB_CFG<16>
Internal pull-up

NBCFG_DYN_ODT_DISABLE

NB_CFG<6>

RESERVED

NB_CFG<7>
Internal pull-up

R2085

NB_CFG<16>

High = Enabled

FSB Dynamic
ODT

Low

= Disabled

2.2K

5%
1/16W
MF-LF
2 402

NO STUFF
1

R2077

NB_CFG<7>

High = Mobile CPU

CPU Strap

Low

= RESERVED

2.2K

5%
1/16W
MF-LF
2 402

NB_CFG<17>

RESERVED

PP3V3_S0
NBCFG_VCC_1V5

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

NB_CFG<18>
NB_CFG<8>

RESERVED

VCC Select

R2058

Low
14

B
14

NB_CFG<9>
Internal pull-up

= 1.05V

NB_CFG<9>

Low

= Reversed

B
37 43 48 51 53 56 57 59 60 64
PP3V3_S0
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36
NBCFG_DMI_REVERSE 65 66 70 78 79

NBCFG_PEG_REVERSE

R2079

High = Normal

5%
1/16W
MF-LF
2 402

NB_CFG<18>
Internal pull-down

PCIE Graphics
Lane Reversal

2.2K

High = 1.5V

2.2K

5%
1/16W
MF-LF
2 402

R2059

NB_CFG<19>

High = Reversed

DMI Lane
Reversal

Low
14

= Normal

2.2K

5%
1/16W
MF-LF
2 402

NB_CFG<19>
Internal pull-down
78 79

945 External Design Spec says reserved

34 36 37 43 48 51 53 56 57 59
PP3V3_S0
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33
NBCFG_SDVO_AND_PCIE 60 64 65 66 70

NB_CFG<10>

RESERVED

NB_CFG<20>

High = Both active

PCIe Backward
Interop. Mode

Low
14

= Only SDVO
or PCIe x1

R2060
2.2K

5%
1/16W
MF-LF
2 402

NB_CFG<20>
Internal pull-down

PROBABLY NOT NEEDED

NB Config Straps
SYNC_MASTER=M1_MLB

NB_CFG<11>

RESERVED

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

PP3V3_G3C_SB_RTC_D

R2105 NOTE:
332K
402MF-LF

PP3V3_S0

1/16W 1%

R2194
10K

5%
1/16W
MF-LF
2402

OMIT

U2100
26

OUT
IN

SB_RTC_RST_L

AA3

Y5
SB_SM_INTRUDER_L
W4
SB_INTVRMEN

ICH7-M
SB
BGA

RTCX1
RTCX2

LAD0
LAD1
LAD2
LAD3

(1 OF 6)

RTCRST*
INTRUDER*
INTVRMEN

LPC

AB1
AB2

RTC

SB_RTC_X1
SB_RTC_X2

LDRQ0*
LDRQ1*/GPIO23

W1 EE_CS
NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN TP_SB_XOR_W1
LAN_RST#=L

86 47 5

OUT

86 47 5

OUT

86 47 5

OUT

86 47 5

OUT

ACZ_BITCLK
ACZ_SYNC

R2195 1
R2198 1
R2197 1

ACZ_RST_L
ACZ_SDATAIN<0>

ACZ_SDATAOUTR2196 1

39
39
39

2
2

86
86

U1
SB_ACZ_BITCLK
SB_ACZ_SYNC R6

LAN_RSTSYNC

OUT

34 5

OUT

AF18
TP_SB_SATALED_L
AF3
TP_SATA_A_D2RN
AE3
TP_SATA_A_D2RP
AG2
TP_SATA_A_R2DN
AH2
TP_SATA_A_R2DP
SATA_C_D2R_NAF7
SATA_C_D2R_PAE7
AG6
SATA_C_R2D_C_N
AH6
SATA_C_R2D_C_P

CPUSPL*

LAN

(WEAK INT PD)

TP1/DPRSTP*
TP2/DPSLP*

LAN_RXD0
LAN_RXD1 (WEAK INT PU)
LAN_RXD2

ACZ_BIT_CLK
ACZ_SYNC

FERR*
GPIO49/CPUPWRGD

CPU

LAN_TXD0
LAN_TXD1
LAN_TXD2

IGNNE*
INIT3_3V*
INIT*
INTR
RCIN*
NMI
SMI*
STPCLK*
THRMTRIP*

SATALED*

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

SATA_0RXN
SATA_0RXP
SATA_0TXN
SATA_0TXP
SATA_2RXN
SATA_2RXP
SATA_2TXN
SATA_2TXP

36 21

SATA_RBIAS AH10
SATA_RBIAS AG10

AF15
OUT IDE_PDIOR_L
AH15
36
OUT IDE_PDIOW_L
AF16
36
OUT IDE_PDDACK_L
AH16
IDE_IRQ14
36
IN
AG16
36
IN IDE_PDIORDY
IDE_PDDREQ AE15
NOTE: DDREQ HAS INTERNAL 11.5K INPD

AA6
AB5
AC4
Y6

LPC_AD<0>
BI 5 50 52 59
LPC_AD<1>
BI
NOTE: LAD<0-3> HAVE INTERNAL 20K PU
LPC_AD<2>
BI 5 50 52 59
LPC_AD<3>
BI 5 50 52 59

AC3
AA5

TP_SB_DRQ0_L
NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU
TP_SB_GPIO23
BI
NOSTUFF
LPC_FRAME_L

AB3
AE22
AH28
AG27
AF24
AH25

OUT

1
2
SB_A20GATE
NOTE: PULLED UP PER INTEL
CPU_A20M_L
5%
OUT 7 86

TP_CPU_CPUSLP_L

1/16W
MF-LF
402

CPU_DPRSTP_L
OUT
CPU_DPSLP_L
OUT

5 7 86

AG24

CPU_PWRGD
OUT

5 7 86

AG22
AG21
AF22
AF25

CPU_IGNNE_L
OUT
FWH_INIT_L
OUT
CPU_INIT_L
OUT
CPU_INTR
OUT

PP3V3_S0

R2101
2.2K

5 50 52 59

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

5 7 60

PP1V05_S0

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

R2199
10K

R2110=56 IN CV.
R2110 NOTE:
CHANGED TO 54.9 FOR

54.9
MF-LF402

5%
1/16W
MF-LF
2402

AH24
AF23
AH22

BOM CONSOLIDATION

1/16W 1%

AG26

AG23

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

CPU_FERR_L
IN

7 86
5 50 51 52

PP1V05_S0

NOSTUFF

7 86
7 86

NOTE: KEYBOARD CONTROLLER RESET CPU

CPU_RCIN_L

CPU_NMI
OUT NOTE: RISING-EDGE TRIGGERED AT CPU
CPU_SMI_L
OUT 7 86
CPU_STPCLK_L
OUT

R2100
0
1
2
MF-LF402
1/16W 5%

SMC_RCIN_L
IN

NOTE: R2108=56 IN CV.

CHANGED TO 54.9 2FOR
BOM CONSOLIDATION

R2108 LAYOUT
54.9
MF-LF402

R2107 1

5 7 86

AF26

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

NOTE: R2108 TO BE
< 2 IN OF R2107 W/O STUB

1/16W 1%

24.92
1
CPU_THERMTRIP_R

PM_THRMTRIP_L
IN

7 14 51

MF-LF402
1/16W 1%

AF1 SATA_CLKN
SB_CLK100M_SATA_N
AE1 SATA_CLKP
SB_CLK100M_SATA_P

LAN_CLK

SB_ACZ_RST_LR5 ACZ_RST*
T2 ACZ_SDIN0
20K PD
T3 ACZ_SDIN1
TP_SB_ACZ_SDIN1
20K PD
T1 ACZ_SDIN2
TP_SB_ACZ_SDIN2
20K PD
T4 ACZ_SDOUT
2 3986 SB_ACZ_SDATAOUT
2

A20GATE
A20M*

(INT PU)

IDE

EE_SHCLK
EE_DOUT
(INT PU)
EE_DIN

AC-97/
AZALIA

NOTE:
U3
TP_SB_XOR_U3
POR IS SMC WILL PUT LAN INTF
U5
TP_SB_XOR_U5
INTO RESET STATE TO SAVE PWR.
V4
INTEL CONFIRMS OK TO LEAVE PINS ASTP_SB_XOR_V4
NC
T5
TP_SB_XOR_T5
U7
TP_SB_XOR_U7
V6
TP_SB_XOR_V6
V7
5%
TP_SB_XOR_V7

LFRAME*

SATA

Y1
TP_SB_XOR_Y1
Y2
TP_SB_XOR_Y2
W3
TP_SB_XOR_W3
V3
TP_SB_XOR_V3

1/16W
MF-LF
402

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

ENABLE INTERNAL 1.05V SUSPEND REG

26 5

26 25 24

SATARBIASN
SATARBIASP

(HSTROBE)
(STOP)

DIOR*
DIOW*
DDACK*
IDEIRQ
IORDY (DSTROBE)
DDREQ

DA0
DA1
DA2
DCS1*
DCS3*

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

IDE_PDD<0>BI
IDE_PDD<1>BI
IDE_PDD<2>BI
IDE_PDD<3>BI
IDE_PDD<4>BI
IDE_PDD<5>BI
IDE_PDD<6>BI
IDE_PDD<7>BI
IDE_PDD<8>BI
IDE_PDD<9>BI
IDE_PDD<10>
BI
IDE_PDD<11>
BI
IDE_PDD<12>
BI
IDE_PDD<13>
BI
IDE_PDD<14>
BI
IDE_PDD<15>
BI

AH17
AE17
AF17

IDE_PDA<0>
OUT
IDE_PDA<1>
OUT
IDE_PDA<2>
OUT

AE16
AD16

IDE_PDCS1_L
OUT
IDE_PDCS3_L
OUT

LAYOUT NOTE: R2107 TO BE

< 2 IN OF SB

36
36
36
36
36
36

NOTE: DD<7> HAS INTERNAL 11.5K PD

36
36
36
36
36
36
36
36

36
36
36

36
36

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES RS

AC 07

SB: 1 OF 4

INTEL HIGH DEFINITION AUDIO

SYNC_MASTER=M1_MLB

ACZ_BIT_CLK INTERNAL 20K PD ENABLED WHEN

INTERNAL 20K PD ONLY ENABLED IN S3COLD

- LSO BIT IN AC97 GLOBAL CONTROL REG = 1; OR
NONE
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

ACZ_RST#

ACZ_SDIN[0-2]
INTERNAL 20K PD
ACZ_SDOUT

ACZ_SYNC

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

INTERNAL 20K PD

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

INTERNAL 20K PD ENABLED DURING RESET AND

INTERNAL
WHEN 20K PD ENABLED WHEN
- LSO BIT IN AC97 GLOBAL CONTROL REG -= LSO
1; OR
BIT IN AC97 GLOBAL CONTROL REG = 1; OR
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE- DISABLED
BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

INTERNAL 20K PD

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

06
86

PP3V3_S5

64 62 55 26 25 24 23 22 11 5
78 66 65

22
51 47 22 6

5%
1/16W
MF-LF
2402

6 RTUSB_OC_L
6 UNUSED_USB_B_OC_L
5 LTUSB_OC_L
6 UNUSED_USB_D_OC_L
5 EXCARD_OC_L

OUT

49 47 5
49 47 5

47 22 5

OUT

49 47 5

SB_GPIO29
6 SB_GPIO30
4 LT2USB_OC_L

OUT

PP3V3_S5

64 62 55 26 25 24 23 22 11 5
78 66 65

R2205

NOSTUFF

10K

MF-LF
1/16W
402 5%

55 50

R2206

R2207

10K

MF-LF
1/16W
402 5%

10K

MF-LF
1/16W
402 5%

22
22

OUT

PCIE_A_D2R_N F26
PCIE_A_D2R_P F25
E28
PCIE_A_R2D_C_N
E27
PCIE_A_R2D_C_P
H26
PCIE_MINI_D2R_N
H25
PCIE_MINI_D2R_P
G28
PCIE_B_R2D_C_N
G27
PCIE_B_R2D_C_P

K26 PERN3
PCIE_EXCARD_D2R_N
K25 PERP3
PCIE_EXCARD_D2R_P
J28 PETN3
PCIE_C_R2D_C_N
J27 PETP3
PCIE_C_R2D_C_P

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

M26
TP_PCIE_D_D2RN
M25
TP_PCIE_D_D2RP
L28
TP_PCIE_D_R2DN
L27
TP_PCIE_D_R2DP
P26
TP_PCIE_E_D2RN
P25
TP_PCIE_E_D2RP
N28
TP_PCIE_E_R2DN
N27
TP_PCIE_E_R2DP
T25
TP_PCIE_F_D2RN
T24
TP_PCIE_F_D2RP
R28
TP_PCIE_F_R2DN
R27
TP_PCIE_F_R2DP

SPI_SI
SPI_SO

P5
P2

22 6
47 22 6 5
22 6
51 47 22 6 5

(3 OF 6)

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

R2
P6
P1

BGA

PERN2
PERP2
PETN2
PETP2

SPI_SCLK
SPI_CE_L
SPI_ARB

46 22 6

ICH7-M
SB

PERN1
PERP1
PETN1
PETP1

D3
RTUSB_OC_L
C4
UNUSED_USB_B_OC_L
D5
LTUSB_OC_L
D4
UNUSED_USB_D_OC_L
E5
EXCARD_OC_L
C3
22 SB_GPIO29
A2
22 6 SB_GPIO30
B3
22 5 4 LT2USB_OC_L

PERN4
PERP4
PETN4
PETP4

DMI

47 22 6

5%
1/16W
MF-LF
2402

PERN5
PERP5
PETN5
PETP5

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP

PERN6
PERP6
PETN6
PETP6
SPI_CLK (INT PD)
SPI_CS*
SPI_ARB (INT PD)

USB

PCI-EXP

SPI

46 22

U2100

1
1
R2223
R2222
R2226
10K
10K
10K

R2225
R2200
R2250
R2255
R2251
10K
10K
10K
10K
10K
1

OMIT

USB_G_OC_PU

USB_C_OC_PUUSB_D_OC_PUUSB_E_OC_PU
1

SPI_MOSI
SPI_MISO
OC0*
OC1*
OC2*
OC3*
OC4*
OC5*/GPIO29
OC6*/GPIO30
OC7*/GPIO31

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBRBIAS*
USBRBIAS

V26
V25
U28
U27

DMI_N2S_N<0>
IN
DMI_N2S_P<0>
IN
DMI_S2N_N<0>
OUT
DMI_S2N_P<0>
OUT

Y26
Y25
W28
W27

DMI_N2S_N<1>
IN
DMI_N2S_P<1>
IN
DMI_S2N_N<1>
OUT
DMI_S2N_P<1>
OUT

AB26
AB25
AA28
AA27

DMI_N2S_N<2>
IN
DMI_N2S_P<2>
IN
DMI_S2N_N<2>
OUT
DMI_S2N_P<2>
OUT

AD25
AD24
AC28
AC27

DMI_N2S_N<3>
IN
DMI_N2S_P<3>
IN
DMI_S2N_N<3>
OUT
DMI_S2N_P<3>
OUT

AE28
AE27
C25
D25
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
D2
D1

5 14
5 14
14
14

5 14

5 14
14
14

14
14
14
14

SB_CLK100M_DMI_N
IN
SB_CLK100M_DMI_P
IN

OMIT

37 4

37 26

PCI_AD<0>E18
PCI_AD<1>C18
PCI_AD<2>A16
PCI_AD<3>F18
PCI_AD<4>E16
PCI_AD<5>A18
PCI_AD<6>E17
PCI_AD<7>A17
PCI_AD<8>A15
PCI_AD<9>C14
E14
PCI_AD<10>
D14
PCI_AD<11>
B12
PCI_AD<12>
C13
PCI_AD<13>
G15
PCI_AD<14>
G13
PCI_AD<15>
E12
PCI_AD<16>
C11
PCI_AD<17>
D11
PCI_AD<18>
A11
PCI_AD<19>
A10
PCI_AD<20>
F11
PCI_AD<21>
F10
PCI_AD<22>
PCI_AD<23>E9
PCI_AD<24>D9
PCI_AD<25>B9
PCI_AD<26>A8
PCI_AD<27>A6
PCI_AD<28>C7
PCI_AD<29>B6
PCI_AD<30>E6
PCI_AD<31>D6
F16
PCI_FRAME_L
A3
INT_PIRQA_L
B4
INT_PIRQB_L
C5
INT_PIRQC_L
B5
INT_PIRQD_L

AE5
TP_SB_XOR_AE5
AD5
TP_SB_XOR_AD5
AG4
TP_SB_XOR_AG4
AH4
TP_SB_XOR_AH4
AD9
TP_SB_XOR_AD9

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

U2100
ICH7-M
SB
BGA
(2 OF 6)

PP3V3_S0

REQ0*
GNT0*
REQ1*
GNT1*
REQ2*
GNT2*
REQ3*
GNT3*
REQ4*/GPIO22
GNT4*/GPIO48
GPIO1/REQ5*
GPIO17/GNT5*

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

PCI_REQ0_L
IN
TP_PCI_GNT0_L
OUT
PCI_REQ1_L
IN
TP_PCI_GNT1_L
OUT
PCI_REQ2_L
IN
TP_PCI_GNT2_L
OUT
PCI_REQ3_L IN
PCI_GNT3_L OUT

PCI

IRDY*
PAR
PCICLK
DEVSEL*
PERR*
PLOCK*
SERR*
STOP*
TRDY*

(INT

PLTRST*
PCIRST*
20K PU)
PME*

DMI_IRCOMP_R1

2
1/16WMF-LF 1% 402

USB2_RT_N
BI
EXTERNAL 0
USB2_RT_P
BI 6 46
USB_TRACKPAD_N
BI
AIRPORT (MINI-PCIE)
USB_TRACKPAD_P
6 45
BI
USB2_LT_N
BI
EXTERNAL 1
USB2_LT_P
BI 5 6 47
USB2_CAMERA_N
5 6 45
BI
CAMERA
NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD
USB2_CAMERA_P
5 6 45
BI
USB2_EXCARD_N
BI
EXTERNAL 2
USB2_EXCARD_P
5 6 47
BI
USB_IR_NBI
6 80
USB_IR_PBI CF/SD
6 80
USB_BT_NBI
6 80
USB_BT_PBI BT6 80
USB2_LT2_N
5 6 47
BI
IR
USB2_LT2_P
5 6 47
BI

R2204

USB_RBIAS_PN122.62

51 53 56 57 59 60 64 65 66 70
4 5 10 14 17 19 20 21 23 24 25
26 27 28 29 33 34 36 37 43 48
78 79

1
R2298
R2299
10K
10K

1
26

5%
1/16W
MF-LF
2402

4 26 37
4 37

SB_CRT_TVOUT_MUX
BI NOTE: FWH_WP_L NOT USED
PCI_PME_FW_L
IN

BOOT_LPC_SPI_L
OUT
1

PCI_C_BE_L<0>
BI
PCI_C_BE_L<1>
BI
PCI_C_BE_L<2>
BI
PCI_C_BE_L<3>
BI

A7
E10
A9
A12
C9
E11
B10
F15
F14

PCI_IRDY_L
BI
PCI_PARBI
PCI_CLK_SB IN
PCI_DEVSEL_L
BI
PCI_PERR_L
BI
PCI_LOCK_L
BI
PCI_SERR_L
BI
PCI_STOP_L
BI
PCI_TRDY_L
BI
PLT_RST_L
OUT
PCI_RST_L
OUT
TP_PCI_PME_L

37
37
37
37

5 50 52

R2211

1K
5%

NO STUFF - DEFAULT
STUFF - A16 SWAP OVERRIDE

1/16W
MF-LF
2402

(STRAPPED TO TOP-BLOCK SWAP MODE

IE SB INVERTS A16 FOR ALL CYCLES
TARGETING FWH BIOS SPACE)

26 37
37
34

SB BOOT BIOS SELECT

26 37
26 37

GNT5#
STRAP R2211

GNT4#
R2210

26 37

LPC (DEFAULT)11

UNSTUFFUNSTUFF

26 37

PCI

UNSTUFF STUFF

5 14 26

SPI

26 37

STUFF UNSTUFF

5 37

NOTE:
GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

SB: 2 OF 4

FRAME*
PIRQA*
PIRQB*
PIRQC*
PIRQD*
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4

INT I/F GPIO2/PIRQE* G8

GPIO3/PIRQF*
GPIO4/PIRQG*
GPIO5/PIRQH*

MISC
NOTE:
TO

RSVD5
RSVD6
CHANGE SYMBOL
RSVD7
RSVD[1-9]
RSVD8
MCH_SYNC*

F7
F8
G7

VOLTAGE=0V

TP_PCI_GNT4_L
OUT

B15
C12
D12
C15

C26
B18
B19

NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L

SB_GPIO2BI 26
SB_GPIO3BI 26
SB_GPIO4BI 26
ODD_PWR_EN_L
36
BI

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

AE9 TP_SB_XOR_AE9
AG8 TP_SB_XOR_AG8
AH8 TP_SB_XOR_AH8
F21
TP_SB_RSVD9
(AKA TP3, INTERNAL 20K PU)
AH20
NB_SB_SYNC_L
IN 5 14

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

APPLE COMPUTER INC.

LAYOUT NOTE:
PLACE R2203 < 1/2 IN FROM SB

LAYOUT NOTE:
PLACE R2204 < 1/2 IN FROM SB

BOM NOTE FOR PD ON PCI_GNT3_L:

C/BE0*
C/BE1*
C/BE2*
C/BE3*

PP1V5_S0_SB_VCC1_5_B 24

R2203
24.9

1%
1/16W
MF-LF
402

NOTE:
GNT[0-3]# HAVE INT 20K PU
ENABLED ONLY WHEN PCIRST#=0
AND PWROK=H

06
86

NOTE FOR R2323 (DEF=NOSTUFF)

STRAPPING @ PWROK RISING:
SB WILL DISABLE TCO TIMER
SYSTEM REBOOT FEATURE

PP3V3_S0

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

PP3V3_S5

5 11 22 23 24 25 26 55 62 64 65
66 78

8 7 6 5
1

1 NOSTUFF
1 NOSTUFF
1 NO_REBOOT_MODE

RP2300
10K

R2318 R2395 R2396 R2397 R2327 R2326 R2323

10K

1/16W
2402
MF-LF
5%

PP3V3_S5

8.2K

1/16W
2402
MF-LF
5%

10K

1/16W
2402
MF-LF
5%

8.2K

1/16W
2402
MF-LF
5%

10K

1/16W
2402
MF-LF
5%

10K

1/16W
2MF-LF
402
5%

1/16W
2402
MF-LF
5%

U2100

45 33 29 28 27 5
47
45 33 29 28 27 5
47

R2398 R2320 R2317 R2316

1/16W
2402
MF-LF
5%

10K

1/16W
2402
MF-LF
5%

10K

1/16W
2402
MF-LF
5%

BI
BI

SMBUS_SB_SCL
SMBUS_SB_SDA

10K

1/16W
2402
MF-LF
5%

NOT USED

(4
C22 SMBCLK
B22 SMBDATA
A26 LINKALERT*
SMB_LINK_ALERT_L
B25 SMLINK0
SMLINK<0>
A25 SMLINK1
SMLINK<1>

PM_RI_L
SB_SPKR
59 52 51 50 5
50 26 5

OUT
IN
IN

A28

A19
PM_SUS_STAT_L A27
A22
PM_SYSRST_L
PM_BMBUSY_L AB18
B23
SMB_ALERT_L

RI*
SPKR (INT WEAK PD)
SUS_STAT*
SYS_RST*

OUT

33 5

OUT

AC20
AF21

PM_STPPCI_L
PM_STPCPU_L

A21

SB_GPIO26

B21
BIOS_REC
E23
23 FWH_MFG_MODE
AG18

59 52 50 5

PM_CLKRUN_L

AC19
TP_AZ_DOCK_EN_L
RESERVED FOR MOBILE
U2
TP_AZ_DOCK_RST_L
AZALIA DOCKING INTF

C
47 39 5
59 52 50 5
50

IN
BI
IN

F20
AH21
AF20

PCIE_WAKE_L
INT_SERIRQ
PM_THRM_L
26 5

AD22
VR_PWRGD_CK410
BI

SMC_RUNTIME_SCI_L
SMC_EXTSMI_L

AC21
TP_SB_GPIO6
AC18
E21

GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP
GPIO37/SATA3GP

GPIO18/STPPCI*
GPIO20/STPCPU*
GPIO26

CLK14
CLK48
SUSCLK
SLP_S3*
SLP_S4*
SLP_S5*

GPIO0/BM_BUSY*

PWROK
GPIO16/DPRSLPVR
TP0/BATLOW*

(INT 20K PU)

PWRBTN*

GPIO27
GPIO28

LAN_RST*

GPIO32/CLKRUN*

RSMRST*

GPIO33/AZ_DOCK_EN*
GPIO34/AZ_DOCK_RST*
WAKE*
SERIRQ
THRM*
VRMPWRGD

GPIO6
GPIO7
GPIO8

GPIO

5 11 22 23 24 25 26 55 62
64 65 66 78

R2319
R2343
10K
8.2K

SATA GPIO

OF 6)

GPIO11/SMBALERT*
NOTE: RESERVED FOR FUTURE

33 5

ICH7-M
SB
BGA

1 2 3 4

64 62 55 26 25 24 23 22 11 5
78 66 65

PP3V3_S5

OMIT

5%
1/16W
SM-LF

CLKS

SMB

SYS GPIO
PWR MNGT

GPIO9
GPIO10
DEF=GPI
GPIO12
GPIO13
DEF=GPI
GPIO14
GPIO15
GPIO24
GPIO25
ODGPIO35
GPIO38
DEF=GPI
GPIO39

AF19SB_GPIO21
1001
AH18SB_GPIO19
1001
AH19
AE19SB_GPIO37
1001
AC1
B2
C20

TP_SB_SUS_CLK
OUT
PM_SLP_S3_L
OUT
PM_SLP_S4_L
OUT
PM_SLP_S5_L
OUT

AA4

PM_SB_PWROK
IN

AC22
C21 NOTE:

C19

5%
21/16W
MF-LF
402

1/16W
2402
MF-LF
5%

SATA_C_DET_L
IN

SB_CLK14P3M_TIMER
34
IN
SB_CLK48M_USBCTLR
34
IN

B24
D23
F22

C23

R2302
R2303
2 R2305
2
2

5 6

5 32 39 43 50 54 64 65
5 41 46 47 50 63 65
5 50 51

5 26

PM_DPRSLPVR
OUT 5 14 60 86
DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN
PM_PWRBTN_L
IN

PM_BATLOW_L
IN

PM_RSMRST_L
IN

5 50

PM_LAN_ENABLE
IN NOTE:

SMC WILL DRIVE 0-1-0 TO KEEP LAN INTF

IN RESET STATE TO SAVE PWR

R2399
100K
1
2

E20
SMS_INT_L
IN 50 51
A20
SMC_SB_NMI
IN 50
F19
PATA_PWR_EN_L
OUT 23
E19
R4
IDE_RESET_L
OUT 36
E22
SV_SET_UP 5 23 52
R3
CRB_SV_DET 23
D20 TP_SB_GPIO25_DO_NOT_USE
AD21
SB_CLK100M_SATA_OE_L
33
OUT
AD20 TP_SB_GPIO38
BI
AE20
SATA_C_PWR_EN_L
23
OUT

5% 1/16W
402MF-LF

SMC_WAKE_SCI_L
IN

NOTE FOR GPIO25:

- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS
- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)

PP3V3_S5

5 11 22 23 24 25 26 55 62 64 65
66 78

PP3V3_S5

64 62 55 26 25 24 23 22 11 5
78 66 65

R2390
10K

NOTE:
SV_SET_UP IS LINDACARD DETECT
HI = PRESENT
LO = NOT PRESENT

1 NOSTUFF1

R2306
R2308
10K
10K

1/16W
2402
MF-LF
5%

SV_SET_UP 5 23
CRB_SV_DET 23

5%
1/16W
MF-LF
2402

PATA_PWR_EN_L

PP3V3_S0

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

R2388
10K

1
1

2402
MF-LF
5%

5%
1/16W
MF-LF
2402

NOSTUFF
LAYOUT NOTE:
R2307
R2309
10K
0
PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE
1/16W
1/16W

SATA_C_PWR_EN_L

PP3V3_S5

64 62 55 26 25 24 23 22 11 5
78 66 65

SB: 3 OF 4

R2313
R2310
10K
10K

1/16W
2402
MF-LF
5%

1/16W
402
2MF-LF
5%

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

FWH_MFG_MODE 23
BIOS_REC 23

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

1 NOSTUFF 1 NOSTUFF

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

R2314
R2311
0
10K

1/16W
2402
MF-LF
5%

SIZE

1/16W
2402
MF-LF
5%

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

OMIT

OMIT
A4
A23
N24
P24
R18
U14
V27
AA24
AB27
AD11
B1
D10
F4
G18
J1
L24
M17
N14
N17
N18
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P27
P28
R1
R11
R12
R13
R14
R15
R16
R17
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB28
AC2
AC5
AC9
AC11
AD1
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7

U2100
ICH7-M
SB
BGA
(6 OF 6)

VSS

AD3
AD4
AD7
AD8
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N15
N16
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

25 22

PP5V_S0_SB_V5REFG10
AD17

U2100

F6 V5REF_SUS
25 PP5V_S5_SB_V5REF_SUS
AA22
PP1V5_S0_SB_VCC1_5_B
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22 VCCA3GP
H23 VCC1_5_B
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23

ICH7-M
SB

PP3V3_S0

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65
25

V5REF

B27

AG28
PP1V5_S0_SB_VCCDMIPLL
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

BGA

(5 OF 6)

CORE
VCC1_05

VCC PAUX
VCCLAN_3_3

VCC3_3/VCCHDA
VCCSUS3_3/VCCSUSHDA

V_CPU_IO

IDE
VCC3_3

PCI
VCC3_3

VCCRTC

VCCSUS3_3
VCC3_3
VCCDMIPLL

PP1V5_S0

AD2

PP3V3_S0

AH11

65 47 25 24 19 17 16 13 9 8 5
66

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

PP1V5_S0

65 47 25 24 19 17 16 13 9 8 5
66

64 62 55 26 25 24 23 22 11
78 66

5 PP3V3_S5
65

PP1V5_S0

65 47 25 24 19 17 16 13 9 8 5
66

AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
E3
C1

ARX
VCC1_5_A

USB
VCCSUS3_3

VCCSATAPLL
VCC3_3
VCC1_5_A

VCC1_5_A

ATX
VCC1_5_A

VCC1_5_A

PP1V05_S0

NOTE FOR VCCLAN_3_3:

S3 IF INTERNAL LAN IS USED
S0 OR S3 IF NOT
PP3V3_S0

U6
R7

PP3V3_S0
PP3V3_S5

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

70 78 79
57 59 60
37 43 48
27 28 29
21 22 23
4 5 10 14
17 19 20
24 25 26
33 34 36
51 53 56
64 65 66

AE23 PP1V05_S0
AE26
AH26
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
W5

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

V5
V1
W2
W7

PP1V5_S0

65 47 25 24 19 17 16 13 9 8 5
66

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

NOTE:
VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V
DEPENDING ON VIO OF AZALIA INTERFACE
CODEC ICS CONSIDERED SO FAR ARE 3.3V

5 7 8 9 11 12 13 16 17 19
21 24 25 34 54 64 66

PP3V3_S0

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

PP3V3_S0

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

PP3V3_G3C_SB_RTC_D
PP3V3_S5

21 25 26

5 11 22 23 24 25 26 55 62 64 65
66 78

A24
C24
D19
D22
G19
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

PP3V3_S5

5 11 22 23 24 25 26 55 62 64 65
66 78

AB17
AC17
T7
F17
G17

PP1V5_S0

5 8 9 13 16 17 19 24 25 47 65
66

AB8
AC8
K7

VCCSAUS1_5

VCCSUS3_3

C28

CHANGE SYMBOL TO 1.05

G20

VCCUSBPLL

AA2
VOLTAGE GENERATED INTERNALLY
Y7 VCCLAN1_5
USB CORE
SO NO CONNECT HERE
CHANGE SYMBOL TO 1.05
VCC1_5_A

A1
H6
H7
J6
J7

VOLTAGE GENERATED INTERNALLY

SO NO CONNECT HERE

SB: 4 OF 4
SYNC_MASTER=M1_MLB
PP1V5_S0

5 8 9 13 16 17 19 24 25 47 65
66

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

REV.

051-7023

SHT
NONE

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

06
86

78 70 66 65 64 60 59 57
53 51 48 43 37 36 34 33
22 21 20 19 17 14 10 5 4
79 78 29 28 27 26 25 24 23
56
65 61
79
54 52
31 5 4
47 42 36
60 57 56
70 67 66
80

PP3V3_S0
65 47 25 24 19 17 16 13 9

PP5V_S0

R2502
100
1/16W

5
NC

MF-LF
1 402
5%

1
1

D2502

ICH V5REF BYPASS

(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)
PP5V_S0_SB_V5REF 24
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

C2503
0.1UF

10%
2 16V
X5R
402

65 47 25 24 19 17 16 13 9 8

PLACEMENT NOTE:
PLACE C2503 < 2.54MM OF PIN AD17 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY

C2511
0.1UF

10%
2 16V
X5R
402

BAT54DW
SOT-363

ICH VCC1_5_A/ARX BYPASS

(ICH LOGIC&IO[ARX] 1.5V PWR)
8 5 PP1V5_S0
66
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN AG5

10%
2 16V
X5R
402

2
NC

2
1

1/16W
MF-LF
402
5%

D2502

BAT54DW

C2504
0.1UF

10%
2 16V
X5R
402

C2513
0.1UF

10%
2 16V
X5R
402

VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

402

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN AH11

C2519
PP3V3_S5

64 62 55 26 25 24 23 22 11 5
78 66 65

ICH VCC3_3/VCCHDA BYPASS

(ICH INTEL HDA CORE 3.3V PWR)
PP3V3_S0

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

C2521

2 X5R
402

ICH VCC1_5_A/ATX BYPASS

(ICH LOGIC&IO[ATX] 1.5V PWR)
PP1V5_S0

C2514
1UF

10%
2 6.3V
CERM
402

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN AG9

ICH VCC1_5A BYPASS

(ICH LOGIC&IO 1.5V PWR)
65 47 25 24 19 17 16 13 9 8 5
66

21 19 17 16 13 12 11
66 64 54

PP1V5_S0

ICH V_CPU_IO BYPASS

(ICH CPU I/O 1.05V PWR)
PP1V05_S0
9 8 7 5
34 25 24

ICH VCCA3GP(VCC1_5_B BYPASS

(ICH IO,LOGIC 1.5V PWR)

PLACEMENT NOTE:
PLACE NEAR PINS AE23, AE26 & AH26 OF SB

100-OHM-EMI
SM-3

PP1V5_S0_SB_VCC1_5_B
1 C2505
1 C2506
1 C2507
C2500
220UF 0.1UF 0.1UF 0.1UF

20%
2.5V
2 POLY
SMB2

10%
2 16V
X5R
402

ICH VCCSUS3_3 BYPASS

(ICH SUSPEND 3.3V PWR)
1

PP3V3_S5

55 26 25 24 23 22 11 5
78 66 65 64 62

10%
2 16V
X5R
402

PLACEMENT NOTE:
PLACE C2500 & C2505-07 < 2.54MM OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
NEAR PINS D28, T28, AD28

NOTE:
PLACE C2520 NEAR PIN E3 OF SB

C2509
0.1UF

10%
2 16V
X5R
402

PP1V5_S0

65 47 25 24 19 17 16 13 9 8 5
66

1
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY 0.1UF
OR
10%
3.56MM ON PRIMARY NEAR PINS A1 ...
J7
2 16V
X5R

NOTE:
PLACE C2520 NEAR PIN C1 OF SB

402

16V
2 X5R
402

C2515
0.1UF PLACEMENT

10%
2 16V
X5R
402

PLACEMENT NOTE:
PLACE C2509 NEAR PIN B27 OF SB

C2512

C2525

PP1V5_S0
1

ICH IDE/VCC3_3 BYPASS

(ICH IDE I/O 3.3V PWR)
PP3V3_S0

PLACEMENT NOTE:
1
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PINS AA7 ... 0.1UF
AG19
10%

65 47 25 24 19 17 16 13 9 8 5
66

79 78 70
51 48 43 37 36 34 33
21 20 19 17 14 10 5 4
29 28 27 26 25 24 23 22
66 65 64 60 59 57 56 53

20%
2 6.3V
CERM
603

ICH VCCUSBPLL BYPASS

(ICH USB PLL 1.5V PWR)
ICH VCC3_3 BYPASS
(ICH IO BUFFER 3.3V PWR)
PP3V3_S0

10%
2 16V
X5R
402

ICH USB CORE/VCC1_5_A BYPASS

(ICH USB CORE 1.5V PWR)

65 64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66

1 C2522
1 C2524
C2523
0.1UF 0.1UF 4.7UF

10%
2 16V
X5R
402

C2520
0.1UF PLACEMENT

10%
16V
2 X5R
402

C2510

22 24

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

PP1V5_S0

PLACEMENT NOTE:
0.1UF
PLACE CAPS NEAR PINS 10%
2 16V
X5R
AB8 AND AC8 OF SB
402

C25331 C2532

PLACEMENT NOTE:
0.1UF 0.1UF
10%
PLACE CAPS NEAR PINS 10%
2 16V
2 16V
X5R
X5R
K3 ... N7 OF SB
402
402

PLACEMENT NOTE:
1
PLACE < 2.54MM OF SB ON SECONDARY
OR
0.1UF
10%
3.56MM ON PRIMARY NEAR PIN U6
16V

L2500

ICH USB/VCCSUS3_3 BYPASS

(ICH SUSPEND USB 3.3V PWR)

29 33 34

65 47 25 24 19 17 16 13 9 8 5
66

66
25 24 19 17
9 8 5
16 13
65 47

402

PLACEMENT NOTE:
PLACE C2504 < 2.54MM OF PIN F6 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY

2 2.5V
POLY
CASE-C2

PLACEMENT NOTE:
0.1UF
10%
PLACE CAP UNDER SB NEAR PINS V1,
2 16V
X5R
V5, W2, OR W7
402

C2531 C2534

1
1
PLACEMENT NOTE:
0.1UF
0.1UF
PLACE CAPS NEAR PINS
10%
10%
16V
A24 ... G19 AND P7 OF 2SB
2 16V
X5R
X5R

FOR 270UF

70 78 79

79 78 70 66 65

(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)

PP5V_S5_SB_V5REF_SUS 24

330UF
20%

10%
2 6.3V
CERM
402

64 60 59 57
23 22 21 20
37 36 34 33 29

SOT-363
3 ICH V5REF_SUS BYPASS

PP3V3_S5

ICH VCC_PAUX/VCCLAN3_3 BYPASS

(ICH LAN I/F BUFFER 3.3V PWR)
48 51 53 56 57 59 60 64 65 66
PP3V3_S0
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28
36 37 43

ICH VCC3_3 BYPASS

(ICH IO BUFFER 3.3V PWR)
56 53 51 48 43
19 17 14 10 5 4 PP3V3_S0
28 27 26 25 24

64 62 55 26 25 24 23 22 11 5
78 66 65
19 21 24

1 C2502
1
C2518
C2516 PLACEHOLDER
0.1UF 1UF

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN AD2

PP3V3_S5

R2501

ICH VCCSUS3_3 BYPASS

(ICH SUSPEND 3.3V PWR)

62 55 26 25 24 23 22 11 5
78 66 65 64

PP5V_S5

ICH VCCSATAPLL BYPASS

(ICH SATA PLL 1.5V PWR)
5 PP1V5_S0
66

C2517
0.1UF

64 66

0
66 65
51 46 5
64 63 61
70 67

ICH CORE/VCC1_05 BYPASS

PLACEMENT NOTE:
(ICH CORE 1.05V PWR)
PLACE CAPS AT EDGE OF SB
PP1V05_S0 525 7348 95411 12 13 16 17

10%
2 16V
X5R
402

ICH PCI/VCC3_3 BYPASS

(ICH PCI I/O 3.3V PWR)
65 64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66

PP3V3_S0

C2526 C2527 C2528

1
1
1
PLACEMENT NOTE:
0.1UF
0.1UF
0.1UF
DISTRIBUTE IN PCI SECTION OF SB
10%
10%
10%
16V
16V
16V
NEAR PINS A5 ... G16
2 X5R
2 X5R
2 X5R
402

402

0
PP1V5_S0

65 47 25 24 19 17 16 13 9 8 5
66

R2500
1
1
2
1/10W 5%
MF-LF603

L2507

ICH VCCDMIPLL BYPASS

(ICH DMI PLL 1.5V PWR)
PP1V5_S0_SB_VCCDMIPLL

0.28-OHM
1
PP1V5_S0_SB_VCCDMIPLL_F
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

SB: 4 OF 4
24

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

1206
1

1 C2508
C2501
0.01UF 10UF

10%
2 16V
CERM
402

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON
SECONDARY SIDE OR 3.56MM ON PRIMARY

26 24 21

ICH VCCRTC BYPASS

(ICH RTC 3.3V PWR)
PP3V3_G3C_SB_RTC_D
1

20%
2 6.3V
X5R
603

C25301 C2529
0.1UF

PLACEMENT NOTE:
0.1UF
10%
PLACE CAPS NEAR PIN W5 OF SB
16V
2 X5R
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

10%
2 16V
X5R
402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

0
APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

06
86

RTC Battery Connector

26 25 24 21

CRITICAL

D2600

J2600
F-RT-SM

66 65 54 52 51 50 45 35 27 5
68 67

SYM_1

NC
VOLTAGE=3.3V

SOT-363

PP3V42_G3H

1
6

65 64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66

21 24 25 26

5%
1/16W
MF-LF
402

518S0226

PPVBATT_G3C_RTC_R

C2610
1UF

10%
2 6.3V
CERM
402

R2607

PPVBATT_G3C_RTC

PP3V3_G3C_SB_RTC_D

BAT54DW

88460-0201
3

PP3V3_G3C_SB_RTC_D

MAKE_BASE=TRUE
VOLTAGE=3.3V

37 22

VOLTAGE=3.3V
NC 2

5 NC

R2600

NOTE: R2607 and D2600 form the doublefault protection for RTC battery.

20K

SB_RTC_RST_L

5%
1/16W
MF-LF
402

OUT

5 21

C2605
1UF

10%
2 6.3V
CERM
402

R2606
1M

5%
1/16W
MF-LF
2 402

37 22 4

SB_SM_INTRUDER_L

OUT

37 22

PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_SERR_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_LOCK_L
PCI_REQ0_L
PCI_REQ1_L
PCI_REQ2_L
PCI_REQ3_L
INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
SB_GPIO2
SB_GPIO3
SB_GPIO4

PP3V3_S0

R2623
R2624
R2625
R2626
R2627
R2628
R2630
R2629
R2632
R2631
R2633
R2634
R2637
R2636
R2638
R2639
R2640
R2642
R2641

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K

1
1
1
1

2
2
2
2

8.2K
8.2K
8.2K
8.2K

1
1
1
1
1
1
1

2
2
2
2
2
2
2

8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K

Platform Reset Connections

SB RTC Crystal Circuit

5%
1/16W
MF-LF
402

R26091
10M

CRITICAL

Y2600

5%
1/16W
MF-LF
402 2
21

SM-2

NC
NC

32.768K

R2696

5%
50V
CERM
402

11 7

XDP_DBRESET_L

OMIT

5%
50V
CERM
402

MAKE_BASE=TRUE

OUT

PLT_RST_L

MAKE_BASE=TRUE

100K

5%
1/16W
MF-LF
402 2

Silk: "SYS RST"

65 64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66

Buffered
MC74VHC1G08
SC70

U2680 4

PLT_RST_BUF_L

R2681
1

C2680
0.1UF

20%
10V
2 CERM
402

R2683

R2684

5%
1/16W
MF-LF
402

R2680
100K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
402

PP3V3_S0

C2611

MC74VHC1G00

PP3V3_S0

R2611

20%
10V
CERM 2
402

TPM_LRESET_L

5 59

ENET_RST_L

R2682
1

1.8K

5%
1/16W
MF-LF
2 402

MC74VHC1G08

U2603 2

VR_PWRGD_CK410_L

23 5

26 33 60

OUT

PM_SB_PWROK

5
1

SC70
4

U2601 2

R26121

5 14 60

ALL_SYS_PWRGD

50 65

R2622

5%
1/16W
MF-LF
402 2

VR_PWRGD_CK410_L

VR_PWRGOOD_DELAY

10K

OUT

5 50

MAKE_BASE=TRUE

60 33 26

SMC_LRESET_L

Initial resistor values are based on CRB,

but may change after characterization.

0.1UF

SC70-5
4

VR_PWRGD_CK410

5%
1/16W
MF-LF
402

C2607 1

20%
10V
CERM 2
402

OUT

100

DEBUG_RST_L
5 52
Linda Card represents 3 loads

0.1UF

23 5

5 69

PP3V3_S0

65 64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66

PEG_RESET_L

5 14 22 26

5%
1/16W
MF-LF
402

65 64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66

PLT_RST_L
100-ohm on NB page

R2687

LIO_PLT_RESET_L 5 47
LIO represents X loads (2?)

5%
1/16W
MF-LF
402

5 23 50

R26981

This part is never stuffed,

it provides a set of pads
on the board to short or
to solder a reset button.

12pF

26 22 14 5

PM_SYSRST_L

5%
1/16W
MF-LF
402

C2609
1

SB_RTC_X2

5%
1/16W
MF-LF
402 2

ITP

R2685

10K

12pF

SB_RTC_X1_R
3

2 4

SB_RTC_X1

Unbuffered
R26971

C2608

R2610
21

PP3V3_S5

64 62 55 25 24 23 22 11 5
78 66 65

10K

5%
1/16W
MF-LF
2 402

1G00 used as small & cheap inverter

SB Misc
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

ICH7-M SMBus Connections

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

R27001
4.7K

U2100
(MASTER)

28 27 23 5
47 45 33 29
28 27 23 5
47 45 33 29

SMC "0" SMBus Connections

PP3V3_S0

ICH7-M

5%
1/16W
MF-LF
402 2

SMBUS_SB_SCL

R2701
4.7K

5%
1/16W
MF-LF
2 402

Clock Chip

SMC

CY28445-5: U3301
(Write: 0xD2 Read: 0xD3)

U5800
(MASTER)

SMBUS_SB_SCL

MAKE_BASE=TRUE

SMBUS_SB_SDA

MAKE_BASE=TRUE

NO STUFF
1

53 50 27 5

50 45 27 5
53

100pF

SMBUS_SB_SCL
SMBUS_SB_SDA

4.7K

5%
1/16W
MF-LF
402 2

R2751
4.7K

5%
1/16W
MF-LF
2 402

Right-Side Temp

SMC

ADT7461: U6150
(Write: 0x98 Read: 0x99)

U5800
(MASTER)

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

5 27
50 53

48 27 10 4
50

5 27
45 50 53

48 27 10 4
50

5%
2 50V
CERM
402

50
5
27
53
45
5
27
50
53

SMBUS_SMC_0_S0_SDA

5 23 27 28
29 33 45 47

5%
1/16W
MF-LF
2 402

J2900
(Write: 0xA4 Read: 0xA5)
5 23 27 28
29 33 45 47

45 27

Ambient Thermal
TMP105: J4930
(Write: 0x90 Read: 0x91)

SMBUS_SMC_0_S0_SCL_R

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

5 23 27 28
29 33 45 47

SMBUS_SMC_B_S0_SCL

Trackpad

SMBUS_SMC_B_S0_SCL

U2 - Keyboard Controller

SMBUS_SB_SCL

45 47
5 23 27
28 29 33

(Write: 0x72 Read: 0x73)

SMBUS_SB_SDA

45 47
5 23 27
28 29 33

62 59 58 56 51 45 41 37 32 5
80 66 64 63

MAKE_BASE=TRUE

C2761

R27701

Left I/O SMBus Connections:

Left I/O Board

J5500
(See Table)

M35 - TMP105

4.7K

5%
1/16W
MF-LF
402 2

50 45 27

SMBUS_SMC_A_S3_SCL

50 45
27

50 45 27

SMBUS_SMC_A_S3_SDA

50 45
27

27
45

J5400
(See Table)

SMBUS_SMC_B_S0_SDA

ExpressCard Slot

SMBUS_SB_SCL

45 47
5 23 27
28 29 33

(Address determined by ARP)

SMBUS_SB_SDA

45 47
5 23 27
28 29 33

4 10 27 48
50
4 10 27 48
50

LIO - TMP105

SMC "Battery A" SMBus Connections

66 65 54 52 51 50 45 35 26 5
68 67

PP3V42_G3H

R27801
4.7K

U5800
(MASTER)

5%
1/16W
MF-LF
402 2

SMBUS_SMC_BSA_SCL

R2781
4.7K

Battery
J8250
(Write: 0x16 Read: 0x17)

5%
1/16W
MF-LF
2 402

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

5 27 50
67
5 27 50
67

R2771
4.7K

SMC "Battery B" SMBus Connections

5%
1/16W
MF-LF
2 402

SMBUS_SMC_A_S3_SCL

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

MAKE_BASE=TRUE

(Write: 0x92 Read: 0x93)

Left I/O Board

SMBUS_SMC_B_S0_SCL

67 50 27 5

U5800
(MASTER)

4 10 27
48 50
4 10 27
48 50

5 27 45
50 53

PP3V3_S3

SMC

SMBUS_SMC_B_S0_SDA

Left I/O SMBus Connections:

NOTE: SMC RMT bus remains powered and may be active in S3 state

(Write: 0x70 Read: 0x71)

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

5%
50V
2 CERM
402

SMC "A" SMBus Connections

J4900
(See Table)

U1 - Trackpad Controller

CPU Temp
ADT7461: U1001
(Write: 0x98 Read: 0x99)

5%
1/16W
MF-LF
2 402

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

SMC
Trackpad I2C Connections:

4.7K

(Write: 0x90 Read: 0x91)

R2752
47

R2761

5%
1/16W
MF-LF
402 2

100pF

SMBUS_SMC_0_S0_SCL

5 23 27 28
29 33 45 47

4.7K

SMBUS_SB_SDA

R27601

MAX6695: U6100
(Write: 0x30 Read: 0x31)

SO-DIMM "B"
SMBUS_SB_SCL

PP3V3_S0

GPU Temp

C2751
100pF

J2800
(Write: 0xA0 Read: 0xA1)

5%
2 50V
CERM
402

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

R27501

SMC "B" SMBus Connections

PP3V3_S0

SMBUS_SMC_0_S0_SCL

5 23 27 28
29 33 45 47
5 23 27 28
29 33 45 47

SO-DIMM "A"

C2701

PP3V3_S0

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

R27901

SMC
Top-Case

Top-Case SMBus Connections:

J4900
(See Table)

Left Temp - TMP105

Right Temp - TMP105
(Write: 0x92 Read: 0x93)

SMBUS_SMC_A_S3_SDA

5%
1/16W
MF-LF
402 2

50 27

SMBUS_SMC_BSB_SCL

50
27

50 27

SMBUS_SMC_BSB_SDA

50
27

(Write: 0x90 Read: 0x91)

SMBUS_SMC_A_S3_SCL

100K

U5800
(MASTER)

27 45
50

R2791
100K

5%
1/16W
MF-LF
2 402

SMBUS_SMC_BSB_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSB_SDA

MAKE_BASE=TRUE

27 45
50

Left ALS - TSL2561

(Write: 0x52 Read: 0x53)

M1 SMBus Connections
SYNC_MASTER=M1_MLB

SYNC_DATE=01/04/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Page Notes

32 29 14

Power aliases required by this page:

- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)

2.2uF

20%
6.3V
CERM1 2
603

C2800

0.1uF

20%
2 10V
CERM
402

15
15

BOM options provided by this page:

(NONE)

1A
3A
5A
7A
9A
11A
13A
15A
17A
19A
21A
23A
25A
27A
29A
31A
33A
35A
37A
39A

MEMORY_VREF

C2801

Signal aliases required by this page:

- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA

203
201

PP1V8_S3

15
15

NOTE: This page does not supply VREF.

The reference voltage must be provided
by another page.

15
15

MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DQ<6>
MEM_A_DQ<7>

MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DQ<20>
MEM_A_DQ<16>

MEM_A_DQ<28>
MEM_A_DQ<25>

MEM_A_DM<3>

"Lower" (surface-mount) slot

15
15

30 14

MEM_A_DQ<27>
MEM_A_DQ<30>
MEM_CKE<0>
NC

30 15

30 15
30 15
30 15

30 15
30 14

30 14

15
15

MEM_A_BS<2>
MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
MEM_A_A<10>
MEM_A_BS<0>
MEM_A_WE_L
MEM_A_CAS_L
MEM_CS_L<1>
MEM_ODT<1>
MEM_A_DQ<35>
MEM_A_DQ<39>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQ<37>
MEM_A_DQ<33>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DM<7>
MEM_A_DQ<58>
MEM_A_DQ<61>
MEM_A_DQ<43>
MEM_A_DQ<45>
NC

15
15

MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DQ<41>
MEM_A_DQ<46>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DM<6>

MEM_A_DQ<53>
15 MEM_A_DQ<48>
79
65 64 60 59 57 56 53 51 48
23 22 21 20 19 17 14 10 5 4 PP3V3_S0
43 37 36 34 33 29 27 26 25 24
78 70 66
47 45 33 29 27 23 5 SMBUS_SB_SDA
47 45 33 29 27 23 5 SMBUS_SB_SCL
15

41A
43A
45A
47A
49A
51A
53A
55A
57A
59A
61A
63A
65A
67A
69A
71A
73A
75A
77A
79A
81A
83A
85A
87A
89A
91A
93A
95A
97A
99A
101A
103A
105A
107A
109A
111A
113A
115A
117A
119A
121A
123A
125A
127A
129A
131A
133A
135A
137A
139A
141A
143A
145A
147A
149A
151A
153A
155A
157A
159A
161A
163A
165A
167A
169A
171A
173A
175A
177A
179A
181A
183A
185A
187A
189A
191A
193A
195A
197A
199A

VREF
VSS1

CRITICAL VSS0

DQ0
DQ1
VSS4

J2800
F-RT-SM

DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8
DQ9
VSS10

DQ4
DQ5
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1
VSS11

DQS1*
DQS1

CK0
CK0*

VSS12

VSS13

DQ10
DQ11

DQ14
DQ15

VSS14

VSS15
KEY

VSS16
DQ16

VSS17
DQ20

DQ17

DQ21

VSS18
DQS2*

VSS19
NC0

DQS2

DM2

VSS21
DQ18

VSS22
DQ22

DQ19
VSS23

DQ23
VSS24

DQ24

DQ28

DQ25
VSS25

DQ29
VSS26

DM3

DQS3*

NC1
VSS27

DQS3
VSS28
DQ30

DQ26
DQ27
VSS29
CKE0
VDD0

DQ31
VSS30
NC/CKE1
VDD1

NC2

NC/A15

BA2
VDD2

NC/A14
VDD3

A12

A11

A9
A8

A7
A6

VDD4

VDD5

A5
A3

A4
A2

A1
VDD6

A0
VDD7

A10/AP

BA1

BA0
WE*

RAS*
S0*

VDD8

VDD9

CAS*
NC/S1*

ODT0
NC/A13

VDD10

VDD11

NC/ODT1
VSS31

NC3
VSS32

DQ32
DQ33

DQ36
DQ37

VSS33

VSS34

DQS4*
DQS4

DM4
VSS35

VSS36

DQ38
DQ39
VSS37

DQ34
DQ35
VSS38

DQ44
DQ45
VSS39

DQ40
DQ41
VSS40
DM5

DQS5*
DQS5

VSS41

VSS42

DQ42
DQ43

DQ46
DQ47

VSS43

VSS44

DQ48
DQ49

DQ52
DQ53

VSS45

VSS46

NC_TEST
VSS47

CK1
CK1*

DQS6*
DQS6

VSS48
DM6

VSS49

VSS50

DQ50
DQ51

DQ54
DQ55

VSS51

VSS52

DQ56
DQ57

DQ60
DQ61

VSS53

VSS54

DM7
VSS55

DQS7*
DQS7

DQ58
DQ59

VSS56
DQ62

VSS57

DQ63
VSS58
SA0

SDA
SCL
VDDSPD

516S0382

PP1V8_S3

SA1

202
204

2A
4A
6A
8A
10A
12A
14A
16A
18A
20A
22A
24A
26A
28A
30A
32A
34A
36A
38A
40A
42A
44A
46A
48A
50A
52A
54A
56A
58A
60A
62A
64A
66A
68A
70A
72A
74A
76A
78A
80A
82A
84A
86A
88A
90A
92A
94A
96A
98A
100A
102A
104A
106A
108A
110A
112A
114A
116A
118A
120A
122A
124A
126A
128A
130A
132A
134A
136A
138A
140A
142A
144A
146A
148A
150A
152A
154A
156A
158A
160A
162A
164A
166A
168A
170A
172A
174A
176A
178A
180A
182A
184A
186A
188A
190A
192A
194A
196A
198A
200A

37 32 31 29 28 19 16 14 5 4
66 63 54

DDR2-SODIMM-DUAL

MEM_A_DQ<8>
MEM_A_DQ<12>

MEM_A_DM<1>

MEM_A_DQ<15>
MEM_A_DQ<9>

15
15

MEM_A_DQ<2>
MEM_A_DQ<3>

MEM_A_DM<0>

MEM_CLK_P<0>
MEM_CLK_N<0>
MEM_A_DQ<1>
MEM_A_DQ<0>

MEM_A_DQ<23>
MEM_A_DQ<22>
PM_EXTTS_L
MEM_A_DM<2>
MEM_A_DQ<21>
MEM_A_DQ<17>
MEM_A_DQ<29>
MEM_A_DQ<24>
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MEM_A_DQ<26>
MEM_A_DQ<31>
MEM_CKE<1>
NC_MEM_A_A<15>
NC_MEM_A_A<14>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<0>

4 5 14 16 19 28 29 31 32 37 54
63 66

14
14

15
15

14 29 50 51
15

15
15

14 30

6
6

DDR2 Bypass Caps

15 30
15 30

(For return current)

15 30
37 32 31 29 28 19 16 14 5 4
66 63 54

PP1V8_S3

15 30
15 30

15 30

C2808
10UF

MEM_A_BS<1>
MEM_A_RAS_L
MEM_CS_L<0>

14 30

MEM_ODT<0>
MEM_A_A<13>

15 30

15 30
15 30

14 30

C2810

20%
2 10V
CERM
402

MEM_A_DM<4>
MEM_A_DQ<32>
MEM_A_DQ<36>
MEM_A_DQ<57>
MEM_A_DQ<63>

MEM_A_DQ<56>
MEM_A_DQ<62>
MEM_A_DQ<40>
MEM_A_DQ<42>

C2811
0.1uF

C2812
0.1uF

20%
2 10V
CERM
402

C2814
0.1uF

20%
2 10V
CERM
402

0.1uF

C2815
0.1uF

20%
2 10V
CERM
402

C2816
0.1uF

20%
2 10V
CERM
402

C2817
0.1uF

20%
2 10V
CERM
402

C2818

20%
2 10V
CERM
402

15
15

C2819
0.1uF

20%
2 10V
CERM
402

C2820
0.1uF

20%
2 10V
CERM
402

C2821
0.1uF

20%
2 10V
CERM
402

15
15

MEM_A_DM<5>

DDR2 SO-DIMM Connector A

15
15

SYNC_MASTER=M1_MLB

MEM_A_DQS_N<6>
MEM_A_DQS_P<6>

C2813

20%
2 10V
CERM
402

MEM_A_DQ<54>
MEM_A_DQ<55>

MEM_CLK_P<1>
MEM_CLK_N<1>

MEM_A_DQ<47>
MEM_A_DQ<44>

20%
2 10V
CERM
402

0.1uF

MEM_A_DQS_N<7>
MEM_A_DQS_P<7>

C2809

20%
2 6.3V
X5R
603

0.1uF

MEM_A_DQ<38>
MEM_A_DQ<34>

10UF

20%
2 6.3V
X5R
603

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

MEM_A_DQ<52>
MEM_A_DQ<49>

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

15
15

SIZE

APPLE COMPUTER INC.

ADDR=0xA0(WR)/0xA1(RD)

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Page Notes

32 28 14

MEMORY_VREF

C2901

2.2uF

20%
6.3V
CERM1 2
603

Signal aliases required by this page:

- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA

C2900

0.1uF

20%
2 10V
CERM
402

MEM_B_DQ<15>
MEM_B_DQ<14>

5B
7B
9B

15
15

MEM_B_DQS_N<1>
MEM_B_DQS_P<1>

11B
13B
15B

BOM options provided by this page:

(NONE)

15
15

MEM_B_DQ<10>
MEM_B_DQ<13>

17B
19B
21B

NOTE: This page does not supply VREF.

The reference voltage must be provided
by another page.

15
15

MEM_B_DQ<7>
MEM_B_DQ<2>

23B

MEM_B_DQS_N<0>
MEM_B_DQS_P<0>

29B

25B
27B

15
15

31B
33B

15
15

MEM_B_DQ<1>
MEM_B_DQ<4>

35B
37B
39B
41B

15
15

MEM_B_DQ<21>
MEM_B_DQ<19>

43B
45B
47B

15
15

MEM_B_DQS_N<2>
MEM_B_DQS_P<2>

49B
51B
53B

15
15

MEM_B_DQ<20>
MEM_B_DQ<23>

55B
57B
59B

15
15

MEM_B_DQ<29>
MEM_B_DQ<24>

61B
63B
65B

MEM_B_DM<3>

67B

69B
71B

"Upper" (thru-hole) slot

MEM_B_DQ<27>
MEM_B_DQ<25>

73B
75B
77B

30 14

MEM_CKE<2>

79B
81B

NC
30 15

MEM_B_BS<2>

83B
85B
87B

30 15
30 15
30 15

MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>

89B
91B
93B
95B

30 15
30 15
30 15

MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>

97B
99B
101B
103B

30 15
30 15
30 15

MEM_B_A<10>
MEM_B_BS<0>
MEM_B_WE_L

105B
107B
109B
111B

30 15
30 14

MEM_B_CAS_L
MEM_CS_L<3>

113B
115B
117B

30 14

MEM_ODT<3>

119B
121B

15
15

MEM_B_DQ<36>
MEM_B_DQ<33>

123B
125B
127B

15
15

MEM_B_DQS_N<4>
MEM_B_DQS_P<4>

129B
131B
133B

15
15

MEM_B_DQ<34>
MEM_B_DQ<35>

135B
137B
139B

15
15

MEM_B_DQ<40>
MEM_B_DQ<41>

141B
143B
145B

MEM_B_DM<5>

147B
149B

15
15

MEM_B_DQ<42>
MEM_B_DQ<43>

151B
153B
155B

15
15

MEM_B_DQ<62>
MEM_B_DQ<59>

157B
159B
161B

163B
165B

15
15

MEM_B_DQS_N<7>
MEM_B_DQS_P<7>

167B
169B
171B

15
15

MEM_B_DQ<60>
MEM_B_DQ<61>

173B
175B
177B

15
15

MEM_B_DQ<54>
MEM_B_DQ<51>

179B
181B
183B

MEM_B_DM<6>

185B
187B

MEM_B_DQ<52>
15 MEM_B_DQ<49>
64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4 PP3V3_S0
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65
SMBUS_SB_SDA
47 45 33 28 27 23 5 SMBUS_SB_SCL

189B

191B
193B
195B
197B
199B

VREF
VSS1

CRITICAL VSS0

DQ0

J2900

DQ1
VSS4

F-RT-TH1

DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8
DQ9

DQ4
DQ5
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1

VSS10

VSS11

DQS1*
DQS1

CK0
CK0*

VSS12

VSS13

DQ10
DQ11

DQ14
DQ15

VSS14

VSS15
KEY

VSS16
DQ16
DQ17
VSS18
DQS2*
DQS2

VSS17
DQ20
DQ21
VSS19
NC0
DM2

VSS21
DQ18

VSS22
DQ22

DQ19
VSS23

DQ23
VSS24

DQ24

DQ28

DQ25
VSS25

DQ29
VSS26

DM3

DQS3*

NC1
VSS27

DQS3
VSS28

DQ26
DQ27
VSS29
CKE0
VDD0

DQ30
DQ31
VSS30
NC/CKE1
VDD1

NC2

NC/A15

BA2
VDD2

NC/A14
VDD3

A12

A11

A9
A8
VDD4

A7
A6
VDD5

A5
A3
A1
VDD6
A10/AP
BA0
WE*
VDD8
CAS*
NC/S1*

A4
A2
A0
VDD7
BA1
RAS*
S0*
VDD9
ODT0
NC/A13

VDD10

VDD11

NC/ODT1
VSS31

NC3
VSS32

DQ32
DQ33
VSS33

DQ36
DQ37
VSS34

DQS4*
DQS4

DM4
VSS35

VSS36

DQ38

DQ34
DQ35
VSS38
DQ40
DQ41

DQ39
VSS37
DQ44
DQ45
VSS39

VSS40
DM5

DQS5*
DQS5

VSS41

VSS42

DQ42
DQ43
VSS43
DQ48
DQ49
VSS45
NC_TEST
VSS47

DQ46
DQ47
VSS44
DQ52
DQ53
VSS46
CK1
CK1*

DQS6*
DQS6

VSS48
DM6

VSS49

VSS50

DQ50
DQ51
VSS51
DQ56
DQ57

DQ54
DQ55
VSS52
DQ60
DQ61

VSS53

VSS54

DM7
VSS55

DQS7*
DQS7

DQ58
DQ59
VSS57
SDA
SCL
VDDSPD

516-0140

PP1V8_S3

201NC

Power aliases required by this page:

- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)

PP1V8_S3

VSS56
DQ62
DQ63
VSS58
SA0
SA1

37 32 31 29 28 19 16 14 5 4
66 63 54

DDR2-SODIMM-DUAL

4 5 14 16 19 28 29 31 32 37 54
63 66

MEM_B_DQ<9>
MEM_B_DQ<11>

4B
6B

15
15

MEM_B_DM<1>

10B

12B

MEM_B_DQ<12>
MEM_B_DQ<8>

14B
16B

15
15

18B

MEM_B_DQ<3>
MEM_B_DQ<6>

20B
22B

24B
26B

MEM_B_DM<0>

MEM_CLK_P<3>
MEM_CLK_N<3>

28B
30B
32B

34B

MEM_B_DQ<0>
MEM_B_DQ<5>

36B
38B

15
15

40B
42B

MEM_B_DQ<22>
MEM_B_DQ<18>

44B
46B

15
15

48B

PM_EXTTS_L
MEM_B_DM<2>

50B
52B

14 28 50 51
15

54B

MEM_B_DQ<17>
MEM_B_DQ<16>

56B
58B

15
15

60B

MEM_B_DQ<26>
MEM_B_DQ<28>

62B
64B

15
15

66B

MEM_B_DQS_N<3>
MEM_B_DQS_P<3>

68B
70B

15
15

72B

MEM_B_DQ<31>
MEM_B_DQ<30>

74B
76B

15
15

78B

MEM_CKE<3>

80B

14 30

82B

NC_MEM_B_A<15>
NC_MEM_B_A<14>

84B
86B

6
6

DDR2 Bypass Caps

88B

MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>

90B
92B
94B

15 30
15 30

(For return current)

15 30

96B

MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>

98B
100B
102B

37 32 31 29 28 19 16 14 5 4
66 63 54

PP1V8_S3

15 30
15 30

15 30

C2908
10UF

104B

MEM_B_BS<1>
MEM_B_RAS_L
MEM_CS_L<2>

106B
108B
110B

15 30
15 30

C2909
10UF

20%
2 6.3V
X5R
603

14 30

112B

MEM_ODT<2>
MEM_B_A<13>

114B
116B

14 30

15 30

120B

C2910
0.1uF

118B

20%
2 10V
CERM
402

122B

MEM_B_DQ<32>
MEM_B_DQ<37>

124B
126B

MEM_B_DM<4>
MEM_B_DQ<38>
MEM_B_DQ<39>

136B

0.1uF

20%
2 10V
CERM
402

C2912
0.1uF

20%
2 10V
CERM
402

C2913
0.1uF

20%
2 10V
CERM
402

C2914
0.1uF

20%
2 10V
CERM
402

132B
134B

C2911

128B
130B

C2915
0.1uF

20%
2 10V
CERM
402

C2916
0.1uF

20%
2 10V
CERM
402

C2917
0.1uF

20%
2 10V
CERM
402

138B

MEM_B_DQ<44>
MEM_B_DQ<45>

140B
142B

C2918
0.1uF

144B

MEM_B_DQS_N<5>
MEM_B_DQS_P<5>

146B
148B

20%
2 10V
CERM
402

15
15

C2919
0.1uF

20%
2 10V
CERM
402

C2920
0.1uF

20%
2 10V
CERM
402

C2921
0.1uF

20%
2 10V
CERM
402

150B

MEM_B_DQ<46>
MEM_B_DQ<47>

152B
154B

15
15

156B

MEM_B_DQ<58>
MEM_B_DQ<63>

158B
160B

15
15

162B
164B
166B

MEM_CLK_P<2>
MEM_CLK_N<2>

MEM_B_DM<7>

168B
170B
172B

MEM_B_DQ<56>
MEM_B_DQ<57>

174B
176B

DDR2 SO-DIMM Connector B

15
15

178B

SYNC_MASTER=M1_MLB
MEM_B_DQ<55>
MEM_B_DQ<50>

180B
182B

15
15

184B

MEM_B_DQS_N<6>
MEM_B_DQS_P<6>

186B
188B

PP3V3_S0

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

190B

MEM_B_DQ<53>
15
MEM_B_DQ<48>
15
Resistor prevents pwr-gnd short

192B
194B
196B
198B

II NOT TO REPRODUCE OR COPY IT

R2900

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

10K
5%
1/16W
MF-LF
2 402

SIZE

APPLE COMPUTER INC.

SODIMM_A_SA1

200B

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

ADDR=0xA4(WR)/0xA5(RD)

202 NC

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

06
86

One cap for each side of every RPAK, one cap for every two discrete resistors
Ensure CS_L and ODT resistors are close to SO-DIMM connector
66 65 31 5

29 28 14

MEM_CS_L<3..0>
0

1
2
3

29 28 14

MEM_CKE<3..0>
0
1
2
3

29 28 14

MEM_ODT<3..0>
0
1
2
3

28 15

MEM_A_A<13..0>
0
1
2
3
4
5
6

7
8
9
10
11
12
13

PP0V9_S0

RP3001
RP3004
RP3007
RP3010

56
56
56
56

2
4
1
1

7
5 5%
8 5%
8 5%
5%

1/16W
1/16W
1/16W
1/16W

SM-LF
SM-LF
SM-LF
SM-LF

RP3009
RP3009
RP3012
RP3012

56
56
56
56

3
2
2
1

6
7 5%
7 5%
8 5%
5%

1/16W
1/16W
1/16W
1/16W

SM-LF
SM-LF
SM-LF
SM-LF

RP3013
RP3004
RP3007
RP3010

56
56
56
56

1
3
2
2

8
6 5%
7 5%
7 5%
5%

1/16W
1/16W
1/16W
1/16W

SM-LF
SM-LF
SM-LF
SM-LF

RP3002
RP3005
RP3002
RP3001
RP3002
RP3002
RP3006
RP3003
RP3006
RP3003
RP3005
RP3006
RP3003
RP3013

56
56
56
56
56
56
56
56
56
56
56
56
56
56

4
4
3
1
1
2
3
3
2
4
1
4
1
3

5
5
6
8
8
7
6
6
7
5
8
5
8
6

1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W

SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF

0.1uF

C3005

20%
10V
2 CERM
402

C3010

20%
2 10V
CERM
402

C3030
0.1uF

20%
2 10V
CERM
402

C3032
0.1uF

20%
2 10V
CERM
402

C3034
0.1uF

MEM_A_BS<2..0>
0
1
2

28 15

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

29 15

MEM_B_A<13..0>
0

1
2
3
4
5
6
7
8
9
10
11
12
13

RP3001
RP3005
RP3009

56
56
56

3
3
4

RP3005
RP3004
RP3001

56
56
56

2
2
4

RP3013
RP3012
RP3006
RP3009
RP3003
RP3011
RP3008
RP3008
RP3011
RP3012
RP3008
RP3008
RP3011
RP3007

56
56
56
56
56
56
56
56
56
56
56
56
56
56

2
4
1
1
2
4
3
4
3
3
1
2
2
3

6
6 5%
5 5%
5%

1/16W SM-LF
1/16W SM-LF
1/16W SM-LF

7
7 5%
5 5%
5%

1/16W SM-LF
1/16W SM-LF
1/16W SM-LF

7
5
8
8
7
5
6
5
6
6
8
7
7
6

0.1uF

1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W

C3038
0.1uF

20%
10V
2 CERM
402

5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%

C3036

20%
10V
2 CERM
402

SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF
SM-LF

C3050

C3052

MEM_B_BS<2..0>
0
1
2

29 15

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

RP3007
RP3013
RP3011

56
56
56

4
4
1

RP3004
RP3010
RP3010

56
56
56

1
4
3

5
5 5%
8 5%
5%

1/16W SM-LF
1/16W SM-LF
1/16W SM-LF

8
5 5%
6 5%
5%

1/16W SM-LF
1/16W SM-LF
1/16W SM-LF

20%
2 10V
CERM
402

C3054
0.1uF

C3056
0.1uF

20%
2 10V
CERM
402

C3007
0.1uF

20%
10V
2 CERM
402

C3011
0.1uF

20%
2 10V
CERM
402

C3031
0.1uF

20%
2 10V
CERM
402

C3033

0.1uF

20%
10V
2 CERM
402

C3035
0.1uF

20%
10V
2 CERM
402

C3037
0.1uF

20%
10V
2 CERM
402

C3039
0.1uF

20%
10V
2 CERM
402

C3051

0.1uF

20%
10V
2 CERM
402

0.1uF

20%
2 10V
CERM
402

29 15

0.1uF

20%
10V
2 CERM
402

C3002

20%
10V
2 CERM
402

0.1uF

20%
10V
2 CERM
402

28 15

0.1uF

5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%

C3000

20%
10V
2 CERM
402

C3053
0.1uF

20%
2 10V
CERM
402

C3055
0.1uF

20%
10V
2 CERM
402

C3057
0.1uF

20%
2 10V
CERM
402

Memory Active Termination

C3058
0.1uF

20%
10V
2 CERM
402

C3059

SYNC_MASTER=(M1_MLB)

SYNC_DATE=(11/07/2006)

0.1uF

20%
10V
2 CERM
402

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Page Notes
Power aliases required by this page:
- =PP5V_S0_MEMVTT
- =PP1V8_S0_MEMVTT
- =PP0V9_S0_MEMVTT_LDO
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

DDR2 Vtt Regulator

57 56 54 52 47 42 36 25 5 4
80 79 78 70 67 66 65 61 60
54 37 32 29 28 19 16 14 5 4
66 63

PP5V_S0

R3104

PP1V8_S3

220

5%
1/16W
MF-LF
402

If power inputs are not S0,

MEMVTT_EN can be used to
disable MEMVTT in sleep.

PP1V8_S0_MEMVTT_VDDQ

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

R3100
1K

5%
1/16W
MF-LF
2 402

C3104 1
2.2uF

20%
6.3V
CERM1 2
603

5
VDDQ

C3101

BD3533FVM
MSOP-8

2 EN

10uF

20%
6.3V 2
X5R
603

6
VCC

10%
2 6.3V
CERM
402

U3100
7 VTT_IN

MEMVTT_EN

C3100
1uF

MEMVTT_EN_PU
1

Okay to turn off 5V and

leave 1.8V powered in S3.

MEMVTT_VREF

VTTS 3
VTT 8

C3103
0.1uF

VREF 4

CRITICAL
1

10uF

20%
2 6.3V
X5R
603

GND

10%
2 16V
X5R
402

C3102

PP0V9_S0

5 30 65 66

C3105
150UF
20%
6.3V
POLY
SMC-LF

Memory Vtt Supply

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

62 59 58 56 51 45 41 37 27 5
80 66 64 63

PP3V3_S3
MEMVREF_S3

C3200 1

R32021

0.1UF

100K

20%
10V
CERM 2
402

54 37 31 29 28 19 16 14 5 4
66 63

5%
1/16W
MF-LF
402 2

PP1V8_S3
CRITICAL

R32051

U3200

10K

1%
1/16W
MF-LF
402 2

V+

MEMVREF_UNBUF

R32061

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V

10K

1%
1/16W
MF-LF
402 2

MAX4236EUTT
SOT23-6-LF
1
MEMVREF_OUT
5

V-

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

MEMVREF_S0

C3205 1

R3203

220pF

5%
25V
CERM 2
402

MEMVREF_SHDN_L

PM_SLP_S3_L

5 23 39 43 50 54 64 65

5%
1/16W
MF-LF
402

NO STUFF

R3290
31

MEMVTT_VREF

MIN_LINE_WIDTH=0.2 mm
5%
MIN_NECK_WIDTH=0.15 mm
1/16W
VOLTAGE=0.9V

32 29
28 14

MEMORY_VREF
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

MF-LF
402

MEMORY_VREF
MEMORY_VREF
MEMORY_VREF

14 28 29 32
14 28 29 32
14 28 29 32

R3291
32

MEMVREF_OUT

5%
1/16W
MF-LF
402

DDR2 VRef
SYNC_MASTER=M1_MLB

SYNC_DATE=12/19/2005

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

R3302
2.2

PP3V3_S0_CK410_VDD48
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

L3302

FERR-120-OHM-1.5A
1
2
PP3V3_S0
0402

5%
1/16W
MF-LF
402

1 C3309
C3308
0.1UF 10UF

10%
2 16V
X5R
402

20%
2 6.3V
X5R
603

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

C3310
1UF

10%
2 6.3V
CERM
402

D
L3301
FERR-120-OHM-1.5A
2

PP3V3_S0_CK410_VDD_CPU_SRC

1 C3315
1 C3301
1 C3302
1 C3303
1 C3304
C3316
10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

10%
2 16V
X5R
402

10%
402

PP3V3_S0_CK410_VDDA
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

C3312
C3311
10UF 0.1UF

10%

2 16V
X5R

402

Y3301

VDD48

14.31818
1
2
5X3.2-SM

1 C3390
C3389
18pF
18pF

5%
50V
2 CERM
402

U3301

5%
50V
2 CERM
402

QFN

38
39

CK410_XTAL_IN
CK410_XTAL_OUT
PP3V3_S0
34

R3301
10K

5%
1/16W
MF-LF
2402
34

OUT

CK410_PCIF0_CLK

51
50

CK410_FSB_TEST_MODE
8

CY284455
OMIT

PCI_STP*
CPU_STP*

CRITICAL

VDDA

CPUC1
CPUT1

41
42

CPUC2_ITP/SRCC_10

36
37

XOUT

CPUT2_ITP/SRCT_10
SRCC_0/LCD100MC
SRCT_0/LCD100MT

65
(INT PD)

(PORT80 LPC 33MHZ)

OUT CK410_PCIF1_CLK
(ICH7M PCI 33MHZ)

(PULL UP PIN 68 TO ENABLE ITP HOST CLK)

SMBUS_SB_SCL
(ICH SM BUS)IN SMBUS_SB_SDA
BI

CK410_IREF

68
1

(INT PU)
CLKREQ_1*
SRCC_2
SRCT_2

16
15

SRCC_3

19
18
59

R3300
475

1%
1/16W
MF-LF
2402

SRCT_1

PCIF0/ITP_SEL
PCIF1

47
48

SCLK
SDATA

IREF

(INT

VSS48

SRCC_4 22
SRCT_4 21
(INT PU)
CLKREQ_4* 20

5
1

PCI5/FCTSEL1

11
10
14
13
9

SRCC_1

CK410_PCI5_FCTSEL1

VSS_CPU

62
66

VSS_PCI0

VSS_REF

VSS_SRC

THRML_PAD

SRCT_3
PU)
CLKREQ_3*

SRCC_5
SRCT_5

(INT PU)
CLKREQ_5*

VSS_PCI1

24
23
60

SRCC_6 27
SRCT_6 26
CLKREQ_6* 25
(INT PU)
SRCC_7
SRCT_7

30
29

SRCC_8

32
33
34

SRCT_8

(INT PU)
CLKREQ_8*
DOT96C/27MHZ_SPREAD
DOT96T/27MHZ_NON-SPREAD

PM_STPPCI_L IN (FROM ICH7 GPIO18 STPPCI* )

PM_STPCPU_L IN (FROM ICH7 GPIO20 STPCPU* )
CK410_CPU0_N OUT
CK410_CPU0_P OUT (CPU HOST 133/167MHZ)
CK410_CPU1_N OUT
CK410_CPU1_P OUT (GMCH HOST 133/167MHZ)
CK410_CPU2_ITP_SRC10_N
OUT
CK410_CPU2_ITP_SRC10_P
(ITP HOST 133/167MHZ)
OUT
TP_CK410_LVDSN OUT
TP_CK410_LVDSP OUT (GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)
CK410_SRC1_N OUT (GPU PCI-E 100 MHZ )
CK410_SRC1_P OUT
CK410_SRC_CLKREQ1_L
IN
NEED TO DECIDE THE CLKREQ CONNECTION,TO
CK410_SRC2_N OUT
CK410_SRC2_P OUT (ICH7M DMI 100 MHZ )

56 (INT PU)
55 (INT PU)
44
45

CPUC0

XIN

FSB

(EACH POWER PIN PLACED ONE 0.1UF)

(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)

CPUT0

VSSA

57 PCI1
(FW PCI 33MHZ)
OUT CK410_PCI1_CLK
58 PCI2
(TPM LPC 33MHZ)
OUT CK410_PCI2_CLK
63 PCI3
(SMC LPC 33MHZ)
OUT CK410_PCI3_CLK
TP_CK410_PCI4_CLK
64 PCI4
(NO USED)
OUT

47 45 29 28 27 23 5

5%
1/16W
MF-LF
402

C3307
0.1UF

10%

2 16V
X5R

CRITICAL

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

20%
2 6.3V
X5R
603

402

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
1

20%
2 6.3V
X5R
603

10%

2 16V
X5R

1 1
PP3V3_S0_CK410_VDD_REF
VOLTAGE=3.3V

VDD_SRC2
VDD_SRC3

5%
1/16W
MF-LF
402

1 C3306
1 C3317
C3305
0.1UF 0.1UF 10UF

R3303

NEED TO CHECK CAP VALUE

2 16V
X5R

10%
2 16V
X5R
402

12
17
28
35

10%
2 16V
X5R
402

VDD_SRC1

R3304
2.2

10%
2 16V
X5R
402

VDD_SRC0

20%
2 6.3V
X5R
603

10%
2 6.3V
CERM
402

PP3V3_S0_CK410_VDD_PCI

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

VDD_REF

C3314
1UF

61
67

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

0402

VDD_PCI0
VDD_PCI1

PP3V3_S0

VDD_CPU

79 78 70
48 43 37 36 34 33
20 19 17 14 10 5 4
29 28 27 26 25 24 23 22 21
66 65 64 60 59 57 56 53 51

7
6

(INT PD)
VTT_PWRGD*/PD 2
FSA/48M 4
REF0/FSC 54
(INT PD)
REF1/FCTSEL0 53

5
23
5
23

34
34

GPIO?

CK410_SRC3_N
CK410_SRC3_P
EXCARD_CLKREQ_L
CK410_SRC4_N
CK410_SRC4_P

OUT
OUT
IN

(FOR PCI-E CARD)

5 34 47

OUT

(ICH SATA 100 MHZ)

SB_CLK100M_SATA_OE_L
(FROM ICH7 GPIO35)
(SIGNAL NAME WILL BE CHANGED
PROTO
POST
TO REMOVE 100M FROM SIGNAL NAME)
IN

CK410_SRC5_N
CK410_SRC5_P
CLK_NB_OE_L

OUT

5
14

(GMCH G_CLKIN 100 MHZ )

(FROM GMCH CLK_REQ*)

CK410_SRC6_N OUT
CK410_SRC6_P OUT (WIRELESS PCI-E 100 MHZ )
MINI_CLKREQ_L
IN
TP_CK410_SRC7NOUT (NOT USED )
TP_CK410_SRC7POUT
CK410_SRC8_N OUT (GIGA LAN PCI-E 100 MHZ )
CK410_SRC8_P OUT
CK410_SRC_CLKREQ8_L
IN
CK410_27M_SPREAD
OUT
CK410_27M_NONSPREAD OUT(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)
VR_PWRGD_CK410_L IN
(FROM CPU VCORE PWR GOOD)
CK410_USB48_FSA OUT
(ICH7M USB 48MHZ)
CK410_CLK14P3M_TIMER
OUT
(ICH7M,SIO,LPC REF. 14.318MHZ)
CK410_REF1_FCTSEL0
BI
34
34

5 34 47

34
34

26 60

CLOCKS

SYNC_MASTER=M1_MLB
SYNC_DATE=02/10/2006

FCTSEL1FCTSEL0PIN 6 PIN 7 PIN 10

PIN 11
0
0
DOT96T DOT96C 100MT_SST100MC_SST* FOR INT. GRAPHIC SYSTEM
0
1
DOT96T DOT96C SRCT0
SRCC0
27M NON 27M
1
0
SPREAD SPREAD SRCT0
SRCC0
* FOR EXT. GRAPHIC SYSTEM
1
1
OFF LOWTBD
SRCT0
SRCC0

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

R3463
33

CK410_PCIF0_CLK

PCI_CLK_PORT80_LPC

5%
1/16W
MF-LF
402

CK410_PCIF1_CLK

CK410_PCI1_CLK

CK410_PCI3_CLK

34 33

TP_CK410_PCI4_CLK

PCI_CLK_SB

5%
1/16W
MF-LF
402

PCI_CLK_FW

(TO ICH7M PCI 33MHZ)

OUT

(TO FIREWIRE PCI 33MHZ)

OUT

PCI_CLK_TPM

5%
1/16W
MF-LF
402

(TO TPM PCI 33MHZ)

OUT

5%
1/16W
MF-LF
402

OUT

TP_CK410_PCI4_CLK

(TO SMC PCI 33MHZ)

33
33 34

SB_CLK48M_USBCTLR

5%
1/16W
MF-LF
402
1

(TO ICH7M USB 48MHZ)

OUT

PP1V05_S0
NOSTUFF

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

5%
1/16W
MF-LF
2 402

NB_BSEL<0>

5%
1/16W
MF-LF
402

R3401
2.2K 2

OUT

CK410_CPU1_P

CK410_CPU1_N

CK410_CPU2_ITP_SRC10_P

CPU_BSEL<0>

5%
1/16W
MF-LF
402

R3469
1K

(FROM CPU FS_A) IN

CK410_SRC6_P

CK410_SRC5_P

CK410_SRC2_P

R3470

5%
1/16W
MF-LF
2 402

CK410_SRC4_P

5%
1/16W
MF-LF
402

NB_BSEL<1>

OUT

(TO MCH FS_B)

R3451
1

NOSTUFF

CK410_SRC3_P

CK410_SRC3_N

(FROM CPU FS_B)

34 33

IN
34 33

5%
1/16W
MF-LF
2 402

R3473

CK410_27M_NONSPREAD
CK410_27M_NONSPREAD

R3474
IN

CK410_CLK14P3M_TIMER

5%
1/16W
MF-LF
402

NB_BSEL<2>

5%
1/16W
MF-LF
402

CPU_BSEL_R<2>
1

NOSTUFF

R3454
1K

CK410_27M_SPREAD
CK410_27M_SPREAD
MAKE_BASE=TRUE

CK410_SRC1_P
CK410_SRC1_N

121

5%
1/16W
MF-LF
402

NB_CLK100M_GCLKIN_N

SB_CLK100M_DMI_P

66 65 64 60 59 57 56 53 51 48
23 22 21 20 19 17 14 10 5 4
43 37 36 33 29 28 27 26 25 24
79 78 70

(TO MCH FS_C)

OUT

R3453
1

CPU_BSEL<2>

34 33

TP_CK410_SRC7P

34 33

TP_CK410_SRC7N

34 33

TP_CK410_LVDSP

TP_CK410_LVDSN

(FROM CPU FS_C)

5%
1/16W
MF-LF
402

SB_CLK14P3M_TIMER

10K

5%
1/16W
MF-LF
2 402

A
33

CK410_PCI5_FCTSEL1
CK410_REF1_FCTSEL0
1

R3466
10K

5%
1/16W
MF-LF
2 402

ITP

1%
1/16W
MF-LF
402

86 34 11

11 34 86

CPU_XDP_CLK_P

11 34 86

86 34 11

49.9 2

CPU_XDP_CLK_N

5 34 47

47 34 5

PCIE_CLK100M_MINI_P

1%
1/16W
MF-LF
402

PCIE_CLK100M_MINI_N

OUT

5 14 34

34 14 5

NB_CLK100M_GCLKIN_P

34 14 5

NB_CLK100M_GCLKIN_N

5 14 34

22 34

SB_CLK100M_DMI_N

1%
1/16W
MF-LF
402

R3406
1

SB_CLK100M_DMI_P

1%
1/16W
MF-LF
402

34 22

SB_CLK100M_DMI_N

OUT

34 39

39 34

ENET_CLK100M_PCIE_P

39 34

ENET_CLK100M_PCIE_N

R3407
1

OUT

34 39

R3438
1

OUT

5 21 34

34 21 5

SB_CLK100M_SATA_P
SB_CLK100M_SATA_N

49.9 2
1%
1/16W
MF-LF
402

(ICH7M SATA 100MHZ)

SB_CLK100M_SATA_N

OUT

5 21 34

34 21 5

PCIE_CLK100M_EXCARD_P

OUT

5 34 47

47 34 5

PCIE_CLK100M_EXCARD_P

47 34 5

PCIE_CLK100M_EXCARD_N

49.9 2
1%
1/16W
MF-LF
402

OUT

5 34 47

49.9 2
1%
1/16W
MF-LF
402

(ExpressCard Slot)
PCIE_CLK100M_EXCARD_N

R3496
1

OUT

34 73 76

76 73 34

GPU_CLK27M

1%
1/16W
MF-LF
402

(GPU 27MHz Spread / Non-Spread)

GPU_CLK27MSS_IN

OUT

34 73 76

76 73 34

71.5 2

GPU_CLK27MSS_IN

NO STUFF

R3402
1

OUT

34 69

69 34

PEG_CLK100M_GPU_P

49.9 2
1

PEG_CLK100M_GPU_N

1%
1/16W
MF-LF
402

(GPU PCI-E Graphics 100MHz)

PEG_CLK100M_GPU_N

OUT

34 69

69 34

34 33

TP_CK410_SRC7P
MAKE_BASE=TRUE

TP_CK410_SRC7N
MAKE_BASE=TRUE

TP_CK410_LVDSP

71.5 2
1%
1/16W
MF-LF
402

R3490
PEG_CLK100M_GPU_P

49.9 2
1%
1/16W
MF-LF
402

R3405
GPU_CLK27M

R3482

R3495
1

49.9 2
1%
1/16W
MF-LF
402

R3481
SB_CLK100M_SATA_P

49.9 2
1%
1/16W
MF-LF
402

(Yukon PCI-E 100MHZ)

ENET_CLK100M_PCIE_N

49.9 2
1%
1/16W
MF-LF
402

R3439
ENET_CLK100M_PCIE_P

49.9 2
1%
1/16W
MF-LF
402

49.9 2

34 22

22 34

49.9 2

R3437

49.9 2
1

OUT

R3440

49.9 2
1

47 34 5

49.9 2

ITP

1%
1/16W
MF-LF
402

5 34 47

OUT

R3491
1

49.9 2
1%
1/16W
MF-LF
402

33 34

MAKE_BASE=TRUE

TP_CK410_LVDSN

33 34

MAKE_BASE=TRUE
47 34 33 5

EXCARD_CLKREQ_L

47 34 33 5

MINI_CLKREQ_L

EXCARD_CLKREQ_L

5 33 34 47

MAKE_BASE=TRUE

MINI_CLKREQ_L

5 33 34 47

MAKE_BASE=TRUE

R3485
OUT

(ICH7M 14.318MHZ)

NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY

FS_C FS_B FS_A CPU
0
0
0
266M
# 0
0
1
133M
# 0
1
0
166M
0
1
1
200M
1
0
0
100M
1
0
1
333M
1
1
0
400M
RESERVED
1
1
1
# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED

R3467

FSB_CLK_NB_N

1%
1/16W
MF-LF
402

R3403

34 12 5

CK410_SRC_CLKREQ1_L
GPU CLK OE*

5%
1/16W
MF-LF
402

CK410_SRC_CLKREQ8_L
Yukon CLK OE*

R3486
1K

5%
1/16W
MF-LF
402

PP3V3_S0
1

5 12 34

5%
1/16W
MF-LF
402

FSB_CLK_NB_P

(ICH7M DMI 100MHZ)

R3476
33

1%
1/16W
MF-LF
402

34 12 5

OUT

5%
1/16W
MF-LF
2 402

5 12 34

49.9 2

49.9 2
1

(GMCH G_CLKIN 100MHZ)

R3494
33

R3431

5%
1/16W
MF-LF
402

R3493

R3400

R3408

R3419
33

OUT

NB_CLK100M_GCLKIN_P

5%
1/16W
MF-LF
402

OUT

PCIE_CLK100M_MINI_N

R3499

1%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

(WIRELESS PCI-E MINI 100MHZ)

R3478
1

OUT

PCIE_CLK100M_MINI_P

5%
1/16W
MF-LF
402

OUT

CPU_XDP_CLK_N

R3426
1

FSB_CLK_CPU_N

49.9 2

R3436

5%
1/16W
MF-LF
402

5 7 34

(ITP HOST 133/167MHZ)

R3428

5%
1/16W
MF-LF
402

OUT

FSB_CLK_NB_N

R3423
1

34 7 5

R3441

5%
1/16W
MF-LF
402

OUT

CPU_XDP_CLK_P

5%
1/16W
MF-LF
402

FSB_CLK_CPU_P

(GMCH HOST 133/167MHZ)

R3435

5%
1/16W
MF-LF
402

ITP

5%
1/16W
MF-LF
402

FSB_CLK_CPU_N

R3416
1

34 7 5

5%
1/16W
MF-LF
402

R3475

MAKE_BASE=TRUE

5%
1/16W
MF-LF
2 402

R3498
IN

34 33

CPU_BSEL<1>

5%
1/16W
MF-LF
402

R3452

PP1V05_S0

R3418

CPU_BSEL_R<1>

5%
1/16W
MF-LF
402

5 7 34

(CPU HOST 133/167MHZ)

FSB_CLK_NB_P

ITP

OUT

R3404

R3412

5%
1/16W
MF-LF
402

CK410_SRC4_N

R3472

5%
1/16W
MF-LF
402

19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24 21

R3477

NEED TO CHECK THE BSEL PULLS

OUT

5%
1/16W
MF-LF
402

R3465

5%
1/16W
MF-LF
402

CK410_SRC2_N

CK410_SRC8_N

CK410_SRC5_N

CK410_SRC8_P

PP1V05_S0

R3471

5%
1/16W
MF-LF
402

CK410_SRC6_N

CK410_FSB_TEST_MODE

CK410_CPU2_ITP_SRC10_N

R3450

5%
1/16W
MF-LF
2 402

(TO MCH FS_A)

CPU_BSEL_R<0>

5%
1/16W
MF-LF
402

19 17 16 13 12 11 9 8 7 5
66 64 54 34 25 24 21

R3414

R3427

R3468

5%
1/16W
MF-LF
402

CK410_CPU0_N

R3442
FSB_CLK_CPU_P

R3422
33

R3480

R3434

R3417
CK410_USB48_FSA

R3415
PCI_CLK_SMC

MAKE_BASE=TRUE

CK410_CPU0_P

R3411

R3430

R3433
33

5%
1/16W
MF-LF
402

CK410_PCI2_CLK

R3432

R3429
33

R3413

(PORT80 LPC 33MHZ)

5 52

OUT

Clock Termination
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

TPM Crystal Circuit

C3720

R3721

15pF

5%
1/16W
MF-LF
402

R37201
10M

CRITICAL

Y3720

5%
1/16W
MF-LF
402 2
59

TPM_XTALO_R

2 4

TPM_XTALO
NO STUFF

32.768K
SM-2

NC
NC

5%
50V
CERM
402

C3721
15pF
1

TPM_XTALI

5%
50V
CERM
402

SMC G3Hot Oscillator

L3750

66 65 54 52 51 50 45 27 26 5
68 67

FERR-EMI-100-OHM

PP3V42_G3H

PP3V42_G3H_SMC_CLK_F

2
SM

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.425V
1

C3750

C3751

4.7uF

0.1uF

20%
2 6.3V
CERM
603

20%
10V
CERM 2
402

12 CRITICAL
VDD

U3750
32.768KHZ-9-3.6V
NC
NC
NC
NC

SG-3040LC-SM
OUT

VIO

2
3

NC0

NC4

NC1
NC2

NC5
NC6

NC3

NC7

7
8
9
10
11

R3750
SMC_CLK32K_SUSCLK_R

5%
1/16W
MF-LF
402

NC
NC
NC
NC

50
35

SMC_CLK32K_SUSCLK

35 50

MAKE_BASE=TRUE

GND
6

Mobile Clocking
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

IDE (ODD) Connector

65 64 60 59 57 56 53 51 48
23 22 21 20 19 17 14 10 5 4
43 37 34 33 29 28 27 26 25 24
79 78 70 66

57 56 54 52 47 42 31 25 5 4
80 79 78 70 67 66 65 61 60

PP3V3_S0
CRITICAL

Q3820

PP5V_S0
B3

FDZ293P
BGA
D

A3
A2

PP5V_S0_IDE_ODD

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=5V

NO STUFF

R38011

4.7K

R38201

5%
1/16W
MF-LF
402 2

10K

5%
1/16W
MF-LF
402 2

ODD_PWR_EN_L_RC

10K

5%
1/16W
MF-LF
402 2
22

ODD_PWR_EN_L

(UATA_HSTROBE)
(UATA_DSTROBE)

(UATA_CS0*)

OUT

33K

CRITICAL

5%
1/16W
MF-LF
402 2

20%
6.3V
X5R
402

R38211

R3810

4.7K

0.22uF
1

R38021

C3821

5%
1/16W
MF-LF
2 402

J3800
M-ST-SM1-LF
1
50
2
49
3
48
47
4
46
5
6
45
7
44
43
8
42
9
10
41
11
40
12
39
13
38
14
37
15
36
16
35
17
34
18
33
19
32
20
31
21
30
22
29
23
28
24
27
25
26

IDE_RESET_L
IDE_PDD<7>
IDE_PDD<6>
IDE_PDD<5>
IDE_PDD<4>
IDE_PDD<3>
IDE_PDD<2>
IDE_PDD<1>
IDE_PDD<0>
IDE_PDDREQ
IDE_PDIOR_L
IDE_PDIORDY
IDE_PDA<2>
IDE_PDCS1_L

R38111
15K

5%
1/16W
MF-LF
402 2

IDE_PDD<8>
IDE_PDD<9>
IDE_PDD<10>
IDE_PDD<11>
IDE_PDD<12>
IDE_PDD<13>
IDE_PDD<14>
IDE_PDD<15>
IDE_PDIOW_L
IDE_PDDACK_L
IDE_IRQ14
IDE_PDA<1>
IDE_PDA<0>
IDE_PDCS3_L

OUT

(UATA_STOP)

(UATA_CS1*)

Indicates disk presence

SMC_ODD_DETECT OUT 50
1

R3803
6.2K

5%
1/16W
MF-LF
2 402

516S0335

Counters 10K pull-up to 5V in

ODD to keep SB GPIO <= 3.3V

SATA_C_DET_L
1

R3850
100

5%
1/16W
MF-LF
2 402

36 21

TP_SATA_A_R2DP

36 21

TP_SATA_A_R2DN

36 21

TP_SATA_A_D2RP

36 21

TP_SATA_A_D2RN

21 36

MAKE_BASE=TRUE

21 36

MAKE_BASE=TRUE

21 36

MAKE_BASE=TRUE

PATA Connector

21 36

MAKE_BASE=TRUE

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

36 21
36 21

SATA_RBIAS
SATA_RBIAS

36 21

SATA_RBIAS

MAKE_BASE=TRUE

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

R3860

Placement note
Place within 12.7mm
from ball of SB

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

24.9

1%
1/16W
MF-LF
2 402

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

59 58 56 51 45 41 37 32 27 5
80 66 64 63 62

PP3V3_S3

59 58 56 51 45 41 37 32 27 5
80 66 64 63 62

C3900

1uF

C3901

1uF

10%
2 10V
X5R
402

C3902
1uF

10%
2 10V
X5R
402

C3903
1uF

10%
2 10V
X5R
402

1uF

C3908

1uF

C3909
1uF

10%
2 10V
X5R
402

10%

2 10V
X5R
402

VCC
BI

22 4

From PCI clock generator via 33 Ohms

=FW_PCI_IDSEL

R3900
4

L12
N11
M11
N10
M10
K12
M9
N9
L8
M8
N6
M6
M7
K9
K8
M5
K3
N1
L4
M2
M1
L1
J4
H3
H4
J3
H2
G3
H1
F1
F2
G4

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>

5%
1/16W
MF-LF
402 2

VCCP

PCI_AD0

PCI_DEVSEL_L

PCI_AD1
PCI_AD2

PCI_FRAME_L
PCI_GNT_L

PCI_AD3
PCI_AD4

CRITICAL

PCI_AD5

TSB83AA22

PCI_INTA_L
PCI_IRDY_L

U3900

PCI_AD6
PCI_AD7

PCI_PERR_L
PCI_PME_L
PCI_REQ_L

BGA

(2 OF 2)

PCI_REQ64_L

PCI_AD8
PCI_AD9
PCI_AD10

PCI_RST_L
PCI_SERR_L

PCI_AD11

PCI_STOP_L

PCI_AD12
PCI_AD13

PCI_TRDY_L
PCI_ACK64_L

PCI_AD14
PCI_AD15

PHY_CTL0-CTL0

PCI_AD16

PHY_CTL1-CTL1

PCI_AD17
PCI_AD18

PHY_D0-D0

PCI_AD19

PHY_D1-D1

PCI_AD20
PCI_AD21

PHY_D2

PCI_AD22

PHY_D3

PCI_AD23
PCI_AD24

PHY_D4
PHY_D5

PCI_AD25
PCI_AD26

PHY_D6
PHY_D7

PCI_AD27

PHY_LCLK

PCI_AD28
PCI_AD29

PHY_LINKON
PHY_LPS

PCI_AD30

PHY_LREQ

PCI_AD31

PHY_PCLK
PHY_PINT

N2
L3
E3
B3
K4
L6
F4
F3
J13
D1
L7
L5
J5
N12

FW_DATA<2>
FW_DATA<3>
FW_DATA<4>
FW_DATA<5>
FW_DATA<6>
FW_DATA<7>
CLKFW_LINK_LCLK
FW_LKON
FW_LPS
FW_LREQ
CLKFW_LINK_PCLK
FW_PINT

C2
G11
G12

FW_LLC_PP1V8LDO_EN_L

FW_SCL
FW_SDA

PCI_CLK

SCL

PCI_IDSEL
PCI_PAR

SDA

C3
C4

G_RST_L

MFUNC

OUT

PCI_RST_FW_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L

22 26

C7
C8
D6
D7
E6
E7
E8
E9
E10
F6
F7
F8
F9
F10
G6
G7
G8
G9
G10
H6
H7
H8
H9
H10
J8
J9
J10
K10

22 26
22 26
4 22

BI
BI
OUT

22 26
22 26
22 26
22

OUT

R3903
100

PCI_RST_L

5%
1/16W
MF-LF
402

5 22

THIS IS FROM ICH-7M

C
R3920

1
38

BI
OUT

CLKFW_PHY_LCLK

5%
1/16W
MF-LF
402

59 58 56 51 45 41 37 32 27 5
80 66 64 63 62

OUT

R3910
10K

5%
1/16W
MF-LF
2 402

PP1V8_S3

C3910
0.1uF

10%
2 16V
X5R
402

FW_MFUNC

Might use
MFUNC as a
GPIO

R3980

5%
1/16W
MF-LF
2 402

R3990
220

5%
1/16W
MF-LF
2 402

PP3V3_S3
1

59 58 56 51 45 41 37 32 27 5
80 66 64 63 62

Resistor can probably be removed from design after evaluation

GND

PCI_ACK64_L

C13
B9
B10
C11
B12
A11
B7
B4
A2
D4
B6
A3

D3
L2
N3

REG18_1

PCI_DEVSEL_L
PCI_FRAME_L
PCI_GNT3_L
INT_PIRQD_L
PCI_IRDY_L
PCI_PERR_L
PCI_PME_FW_L
PCI_REQ3_L
PCI_REQ64_L

TP_FW_DATA<0>
TP_FW_DATA<1>

PCI_CLK_FW
FW_PCI_IDSEL
PCI_PAR

REG_EN_L
REG18_0

5%
1/16W
MF-LF
2 402

E13
E12

PCI_C_BE0_L
PCI_C_BE1_L
PCI_C_BE2_L
PCI_C_BE3_L

4.7K

TP_FW_CTL<0>
TP_FW_CTL<1>

PCI_C_BE_L<0>
PCI_C_BE_L<1>
PCI_C_BE_L<2>
PCI_C_BE_L<3>

5%
1/16W
MF-LF
402

R3902

F13
F12

N8
M3
K5
K2

4.7K

E11
F11

D5
D8
D9
E5
F5
H11
J6
J7
J11

R39011

PP3V3_S3

C3904

R3991
220

5%
1/16W
MF-LF
2 402

C3911
0.1uF

10%
2 16V
X5R
402

54 63 66
4 5 14 16 19
28 29 31 32

NO STUFF
1

R3911
1K

5%
1/16W
MF-LF
2 402

FW_G_RST_L
IN
G_RST* is clamped to VCCP
It must not be taken high
when theres no power on VCCP
(OK if VCCP and VCC are
aliased to the same rail)
G_RST* assertion min 2ms

PP3V3_S3
FW_PLTRST_GATED

Ungated Platform Reset

R3977
10K

5%
1/16W
MF-LF
2 402

FW_PLTRST_UNGATED

R3978
26

PLT_RST_BUF_L

100

FW_G_RST_L

5%
1/16W
MF-LF
402

FW_PLTRST_GATED

Q3970

2N7002DW-X-F

NO STUFF
1
6

Gated Platform Reset

50 4

OUT

SMC_RSTGATE_L

SOT-363

C3977
0.001uF

10%
50V
2 CERM
402

1
79 78
57 56 53 51
28 27 26 25
17 14 10 5
23 22 21 20
43 36 34 33
66 65 64 60

70
48
24
4
19
29
59

PP3V3_S0

FW_PLTRST_GATED

FW_PLT_RST_L

R3971
100K

5%
1/16W
MF-LF
2 402

PLT_RST_FW

FW_PLTRST_GATED

FireWire Link (TSB83AA22)

Q3971

2N7002DW-X-F

SYNC_MASTER=(MASTER)

SOT-363

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

FW_PLTRST_GATED

4
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

Q3971

2N7002DW-X-F

SOT-363

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

PP3V3_FWPHY_AVDD
44 43 42 38 5 4

R4035

PP1V95_FWPHY

1 C4002

C4001
1uF

1uF

10%

0.01uF

C4011
1uF

1 C4012

1uF

1 C4013
10%
2 10V
X5R
402

C4030

1uF

C4031

1uF

10%
402

PP1V95_FWPHY_PLLVDD

VOLTAGE=1.95V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

5%
1/16W
MF-LF
402

1 C4035

1uF

10%
10V
X5R 2
402

2 10V
X5R

402

1uF
10%

10%
10V 2
X5R
402

2 10V
X5R
402

1 C4014

1uF

10%
2 10V
X5R
402

1 C4004

2 10V
X5R

402

1uF

10%
2 10V
X5R
402

20%
2 16V
CERM
402

1 C4003
10%

2 10V
X5R

402

C4010

4.7

10V
2 X5R

42 38 5 4

5%
1/16W
MF-LF
402

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

R4000

PP3V3_FWPHY

1uF
10%

2 10V
X5R
402

R4020
2

PP3V3_FWPHY_PLLVDD

10K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
4022

FW_A_BILINGUAL

FW_B_BILINGUAL

R40431

R40451

R4040
1K

5%
1/16W
MF-LF
4022

5%
1/16W
MF-LF
2 402

A6 DS0
B8 DS1
G13 LCLK

FW_LPS

N13 LPS

FW_LREQ

K13 LREQ

FW_PC0

R4056
2

10K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402 2

R4091
1K

R4061
1K
5%

5%
1/16W
MF-LF
2 402

Resistor can probably be removed

from design after evaluation

1/16W
MF-LF
2 402

BGA

R4060
PCLK H13

CLKFW_PHY_PCLK

PINT M13

FW_PINT

OUT

FW_LKON

U3900
TSB83AA22

1
44

DUAL PORT DEVICES ARE POWER CLASS 4 (100)

SINGLE PORT DEVICES ARE POWER CLASS 0 (000)
IMPLEMENT 1K PULLUP OR PULLDOWN ON PORT PAGE

N4 PC0
M4 PC1
N5 PC2

CNA M12

CLKFW_LINK_PCLK

OUT

5%
1/16W
MF-LF
402

FW_BMODE

R4055

1MA (MAX) BUS HOLDERS

L9 BMODE

37 38

TPA0P E1
TPA0N E2

FW_PORT2_TPA_P
FW_PORT2_TPA_N

TPA1P J2
TPA1N J1

FW_PORT1_TPA_P
FW_PORT1_TPA_N

TPB0P C1

FW_PORT2_TPB_P
FW_PORT2_TPB_N

TPB0N B1

PPBUS_S5_FW_FET 1 390K 2
5%
1/16W
MF-LF
402

LKON_DS2 L13

K11 PD

66 43 42 4

R40901

(1 OF 2)

5%
1/16W
MF-LF
4022

FW_A_DS
FW_B_DS
CLKFW_PHY_LCLK

CRITICAL

PLLVDD_CORE A8

10K

402

R40441

PLLVDD_3P3 A7

R40421

K6
C5
C6

10%

2 10V
X5R

FW_B_DS_ONLY

DVDD_CORE

1uF
FW_A_DS_ONLY

D12
H12
DVDD_3P3 J12
K7

D10
D11

1 C4021

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

5%
1/16W
MF-LF
402

AVDD_3P3 G5

FW_CPS

A5 CPS

44 43 42 38 5 4

FW_PORT1_TPB_P
FW_PORT1_TPB_N

TPB1P G2
37

FW_DATA<2>
FW_DATA<3>
FW_DATA<4>
FW_DATA<5>
FW_DATA<6>
FW_DATA<7>

D13
C9
C10
C12
B13
B11

FW_PHY_RESET_L

L10 RESET

D2
D3

TPB1N G1

D4
D5

TPBIAS0 D2
TPBIAS1 K1
TESTM L11
TESTW N7

R0 A12
R1 A13

C4050

R4062

XI A9

FW_TESTM
FW_TESTW

20%
2 6.3V
X5R
402

OUT

44
42 38 5 4

R4085
PP3V3_FWPHY

PP1V8_FWPHY_OSC

VOLTAGE=1.83V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.20 mm

R4086
PP1V95_FWPHY

4.7

5%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

FW_R0
FW_R1

5%
1/16W
MF-LF
402

26.34K1

CRITICAL

R4080

CLK98P304_FW_XI

NO STUFF

R40811

A10

0.22uF

PLLGND

B5 SM
1

FW_A_TPBIAS
FW_B_TPBIAS

A4 SE

CAPACITOR IN CONJUCTION WITH

INTERNAL PULLUP PROVIDES
RESET PULSE WHEN PHY FIRST
RECEIVES POWER

NO STUFF

R4082

20%
2 6.3V
X5R
402

G4080

CLK98P304M_FW_XI_R

98P3040MHZ

5%
1/16W
MF-LF
402

NO STUFF

C4080
0.22uF

VCC

100K

5%
1/16W
MF-LF
2 402

SM
3

1
OUT

TRI-ST/NC

FW_OSC_EN

100

1%
1/16W
MF-LF
402 2

FW_LKON

GND
2

37 38

NO STUFF

R40631
1K

1%
1/16W
MF-LF
402 2

FireWire PHY (TSB83AA22)

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6.

SCHEME MATCHES DOC MVL100258-01 MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.22MM
VOLTAGE=2.5V
40 5 PP2V5_S3_ENET_AVDD

L4100

FERR-120-OHM-1.5A
1

PP2V5_S3

5 62 66

0402
1

C4100

C4101

1UF

C4102

0.1UF

0.1UF
10%

10%

10%
2 6.3V
CERM
402

2 16V
X5R

402

C4103
0.1UF

C4104

C4105

0.1UF

10%

2 16V
X5R

402

2 16V
X5R

402

0.001UF
10%

C4106

0.001UF

0.1UF

10%

2 50V
CERM

402

C4107

2 16V
X5R

402

PLACE C4107 NEAR U4101 AVDD

PP3V3_S3AC

PP1V2_S3

41 39 5
66

5 39 62 66

PP3V3_S3AC

5 39 41 66

VAUX_AVLBL

VMAIN_AVLBL
SWITCH_VCC

U4101

SWITCH_VAUX

88E8053

4.87K2
1

NC 59
NC 60
NC 62
NC 63

64
VDD25

PCI EXPRESS
ANALOG

PCIE_A_D2R_P
PCIE_A_D2R_N

C4111

OUT

X5R
C4112 10%

0.1UF

402

16V

402
1
2
PCIE_A_R2D_P
PCIE_A_R2D_C_P
IN
PCIE_A_R2D_N 1 2
PCIE_A_R2D_C_N
IN
PLACE
C4113
AND
C4112
WITHIN
ENET_CLK100M_PCIE_P
IN
C4113 12 MIL OF U2100 E27 AND E28
ENET_CLK100M_PCIE_N
0.1UF
IN
402
X5R
PCIE_WAKE_L
OUT
16V
10%
ENET_RST_L
IN

REFCLKP 55
REFCLKN 56

22
22

47
5
23

WAKE* 6
PERST* 5

NC_ENET_CTRL25
4 CTRL25
NC_ENET_CTRL12
3 CTRL12
ENET_RSET 16 RSET
NO PULL-UP NEEDED

OUT

1%
1/16W
MF-LF
402

OUT

R4102

HSDACP
HSDACN

10%
16V
X5R

RX_P 54
RX_N 53

QFN

NC 24
NC 25

AVDDL0

AVDDL4 32
AVDDL3 28
AVDDL2 22
AVDDL1 19

CRITICAL

X5R

402
1
PCIE_A_D2R_C_P
PCIE_A_D2R_C_N

TX_P 49
TX_N 50

OMIT

NC 11
NC 9

AVDD
57
AVDDL6 52
AVDDL5 51

VDDO_TTL1
VDDO_TTL0

61
VDDO_TTL4 45
VDDO_TTL3 40
VDDO_TTL2
8

7
2
VDD0

VDD2
VDD1

VDD5 39
VDD4 33
VDD3 13

58
VDD7 48
VDD6 44

PM_SLP_S3_L
OPTIONAL EXTERNAL LDO

0.1UF

ENET_LOM_DIS_L
10 LOM_DISABLE*

64 54 50 43 32 23 5
65

C4110 10%
16V

5%
1/16W
MF-LF
402

4.7K 2

R4101

PLACE C4110 AND C4111 WITHIN

12 MIL OF U4101 PIN 49 AND 50

ENET_MDI_P<0>
BI
ENET_MDI_N<0>
BI
ENET_MDI_P<1>
BI
ENET_MDI_N<1>
BI
ENET_MDI_P<2>
BI
ENET_MDI_N<2>
BI
ENET_MDI_P<3>
BI
ENET_MDI_N<3>
BI

MDIP0 17
MDIN0 18
MDIP1 20
MDIN1 21

LED_ACT*
LED_LINK10/100*

MEDIA

LED

LED_LINK1000*
LINK*

MDIP2 26
MDIN2 27
MDIP3 30
MDIN3 31

29
46

TSTPT

TEST

TESTMODE

TWSI

VPD_CLK 38
VPD_DATA 41

TEST

PU_VDDO_TTL0 42
PU_VDDO_TTL1 43
SPI_DI 35
SPI_DO 34

SPI

SPI_CLK 37
SPI_CS 36
XTALI 15
XTALO 14

MAIN CLK

ENET_VPD_CLK
ENET_VPD_DATA
ENET_PU_VDD_TTL0
ENET_PU_VDD_TTL1

40
40

39
39

ASF IS UNAVAILABLE ON 8053

NC
NC
INTERNAL PULL-UP
NC
NC

R4106
49.9

CRITICAL

ENET_XTALI
3
1
ENET_XTALO

1. KEEP ENET_XTALI AND ENET_XTALO

TRACE LENGTH <12MIL

1%
1/16W
MF-LF
2 402

R4105

1%
1/16W
MF-LF
2 402

R4104

49.9

R4103

49.9

1%
1/16W
MF-LF
2 402

R4120
49.9

1%
1/16W
MF-LF
2 402

R4119

R4118

49.9

1%
1/16W
MF-LF
2 402

R4117
49.9

1%
1/16W
MF-LF
2 402

THRML_PAD
4

2. DO NOT ROUTE UNDER CRYSTAL

Y4101

ENET_MDI0

ENET_MDI1

ENET_MDI2

ENET_MDI3

SM-3.2X2.5MM

25.0000M
1

C4150
27pF

5%
2 50V
CERM
402

C4151

27pF

C4116

0.001UF

5%
2 50V
CERM
402

C4115

0.001UF

10%
2 50V
CERM
402

C4117

0.001UF

10%
2 50V
CERM
402

C4118

0.001UF

10%
2 50V
CERM
402

B
PLACE RESISTORS CLOSE TO U4101

PP3V3_S3AC

5 39 41 66
66 41 39 5

0.1UF
10%
402

OMIT

CRITICAL
8
3
2
1

PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101

SCHEME MATCHES DOC MVL100258-01
66 62 39 5

PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101

SCHEME MATCHES DOC MVL100258-01

PP1V2_S3

66 41 39 5

VCC
E2
NC1 U4102 SDA
NC0
M24C08SCL
WC* SO8

PP3V3_S3AC

5
6

5%
1/16W
MF-LF
402

C4140

2 16V
X5R

4.7K 2

ENET_PU_VDD_TTL0
ENET_PU_VDD_TTL1

5%
1/16W
MF-LF
2 402

R4123

PLACE C4140 NEAR U4102 VCC

4.7K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
2 402

R4131

4.7K2

4.7K

PP3V3_S3AC

R4130

R4122

ENET_VPD_DATA
ENET_VPD_CLK

VSS
4

C4126
0.1UF
10%

2 16V
X5R

402

C4127
0.1UF
10%

16V
2 X5R
402

C4128
0.1UF
10%

16V
2 X5R
402

C4129
0.1UF
10%

16V
2 X5R
402

C4130
0.1UF
10%

16V
2 X5R
402

C4131
0.001UF
10%

2 50V
CERM

402

C4132
0.001UF
10%

2 50V
CERM

C4133
0.001UF
10%

2 50V
CERM

402

C4134

0.001UF

C4135
0.1UF

10%

50V
2 CERM

2 16V
X5R

402

C4136
0.1UF
10%

2 16V
X5R

402

C4137

0.1UF
10%

16V
2 X5R
402

C4138
0.001UF
10%

2 50V
CERM

402

C4139

ETHERNET CONTROLLER

0.001UF
10%
50V
402

2 CERM

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

8
ELECTRICAL_CONSTRAINT_SET

PROVIDED
BY
ETHERNET
PHY

NET_TYPE
SPACING
PHYSICAL
ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENETCONN

ENET_100D
ENET_100D
ENET_100D
ENET_100D
ENET_100D
ENET_100D
ENET_100D
ENET_100D

ENETCONN_P<0>
ENETCONN_N<0>
ENETCONN_P<1>
ENETCONN_N<1>
ENETCONN_P<2>
ENETCONN_N<2>
ENETCONN_P<3>
ENETCONN_N<3>

40
40
40
40
40
40
40
40

Page Notes
Power aliases required by this page:
- =PP2V5_ENET
- =GND_CHASSIS_ENET
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

39 5

PP2V5_S3_ENET_AVDD

Place one cap at each pin of transformer

C4200
1uF

C4201

1uF

10%
2 6.3V
CERM
402

C4202
1uF

10%
2 6.3V
CERM
402

C4203
1uF

10%
2 6.3V
CERM
402

1000BT-824-00275
CRITICAL
39

ENET_MDI_P<0>

T4200
XFR-SM

ENETCONN_P<0>

ENET_CTAP0

ENET_MDI_N<0>
ENET_MDI_P<1>

2
4
5
7

NC1
NC2

LINE
SIDE

CHIP
SIDE

CRITICAL
NC4
NC3

15
13
12
10

J4200

ENETCONN_N<0>

JM36113-P2054-7F
F-RT-TH-RJ45

11
40

ENETCONN_P<1>
ENET_CTAP1

1
2

ENET_MDI_N<1>

ENETCONN_N<1>

3
4

SYM_VER2

ENET_MDI_P<2>

ENET_MDI_N<2>

ENET_MDI_P<3>

ENET_MDI_N<3>

1000BT-824-00275
CRITICAL

T4201
XFR-SM

2
4
5
7

15
13
12
10

NC1
NC2

LINE
SIDE

CHIP
SIDE

Transformers should be
mirrored on opposite
sides of the board

NC4
NC3

ENETCONN_P<2>
ENET_CTAP2

ENETCONN_N<2>

ENETCONN_P<3>

514-0277
Short shielded RJ-45
NO STUFF

ENET_CTAP3
40

R4210

ENETCONN_N<3>

5%
1/16W
MF-LF
402

SYM_VER2

R42001 R42011
75

5%
1/16W
MF-LF
402 2

R4202
75

5%
1/16W
MF-LF
2 402

Place close to connector

R4203
75

5%
1/16W
MF-LF
2 402

C4204
100pF

ENET_CTAP_COMMON
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

10%
3KV
CERM
1808

GND_CHASSIS_DVI_BOTOUT

6 44 79

Ethernet Connector
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Yukon Power Control

Allows powering Yukon down during battery sleep to save power

Q4300
FDG6332C_NL
SC70-6
P-CHN

PP3V3_S3

62 59 58 56 51 45 37 32 27 5
80 66 64 63

PP3V3_S3AC
D

5 39 66

G
5

PPVIN_S3_P2V5S3_SVIN
1

R4305

100K

5%
1/16W
MF-LF
2 402

PM_SLP_S3BATT_L

P2V5S3_EN_L

62 41

P2V5S3_EN_L

MAKE_BASE=TRUE
3

Q4304

2N7002DW-X-F

66 64 63 61 60 54 47 43 5 4
78 70 68

2N7002DW-X-F

SOT-363

41 62

Q4304

R4304

SOT-363

S
1

PPBUS_G3H
P1V2S3_RUNSS 5 62
1.2V enable has pull-up to 3.3V

R4302
470K

5%
1/16W
MF-LF
2 402

2N7002

PM_SLP_S3BATT

Q4302

D
1

SOT23-LF

S
2

6
D

PM_SLP_S4_L
ENETPWR_S3AC

N-CHN

65 63 50 47 46 23 5

2 G

FWPWR_EN_L

FDG6332C_NL
SC70-6

R4300
43

Q4300

FWPWR_EN_L_OR_GND
ENETPWR_S3

5%
1/16W
MF-LF
402

R4301
0

5%
1/16W
MF-LF
2 402

When ENETPWR_S3AC BOMOPTION is active:

State

FWPWR_EN_L

S0 AC

3.3V

(3.3V ON)

3.3V

(2.5V ON)

3.3V (1.2V ON)

S0 Batt

3.3V

(3.3V ON)

3.3V

(2.5V ON)

3.3V (1.2V ON)

S3 AC

3.3V

(3.3V ON)

3.3V

(2.5V ON)

3.3V (1.2V ON)

PBUS

3.3V

PBUS (3.3V OFF)

3.3V (2.5V OFF)

(1.2V OFF)

PBUS (3.3V OFF)

Hi-Z (2.5V OFF)

(1.2V OFF)

S5 Batt

PBUS

PBUS (3.3V OFF)

Hi-Z (2.5V OFF)

(1.2V OFF)

G3H Batt

PBUS

PBUS (3.3V OFF)

Hi-Z (2.5V OFF)

(1.2V OFF)

S3 Batt
S5 AC

PM_SLP_S4_L

PM_SLP_S3BATT

PM_SLP_S3BATT_L

P2V5S3_EN_L

P1V2S3_RUNSS

When ENETPWR_S3 BOMOPTION is active:

State

PM_SLP_S4_L

PM_SLP_S3BATT

PM_SLP_S3BATT_L

P2V5S3_EN_L

P1V2S3_RUNSS

3.3V

(3.3V ON)

3.3V

(2.5V ON)

3.3V (1.2V ON)

3.3V

(3.3V ON)

3.3V

(2.5V ON)

3.3V (1.2V ON)

S5
G3H

0V
0V

PBUS (3.3V OFF)

0V
0V

Hi-Z (2.5V OFF)

0V
0V

Yukon Power Control

SYNC_MASTER=M1_MLB

(1.2V OFF)

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

(1.2V OFF)

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

165MA MAX LOAD

D4400
SC-59
66 43 38 4

PPBUS_S5_FW_FET

U4400

57 56 54 52 47 36 31 25 5 4
80 79 78 70 67 66 65 61 60

PP5V_S0

PP5VR33V_FWPHY3V3

VOLTAGE=33V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

SMD20E40C-X-F

L4400

FB
VOUT
GND ON/OFF

PP3V3_FWPHY

220uH-0.26A

4
8

44 43 42 38 5 4

CDH73-SM

FWPHY3V3_SW

10uF

N20P20%
50V
CERM 2
2320

LT1962-ADJ
MSOP-LF

OUT 1

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

PP3V3_FWPHY

4 5 38 42 43 44

C4420 1
2.2uF

C4400 1

SM-LF

VIN

U4420

CRITICAL

LM2594

PP1V95_FWPHY

CRITICAL

D4401
SOD-123

10%
6.3V 2
X5R
603

C4401
100uF

SHDN

0.01uF

20%
16V
CERM 2
402

ADJ 2

FWPHY_CORE_ADJ

BYP 3
GND 4

FWPHY_CORE_BYP

4 5 38

R4420
16.2K

1%
1/16W
MF-LF
2 402

<Ra>
1

C4422
10uF

20%
2 6.3V
X5R
603

R4421
27.4K

1%
1/16W
MF-LF
2 402

20%
2 6.3V
POLY
B2

MBR0540XXG

C4421

<Rb>

Vout = 1.22V * (1 + Ra/Rb) + (Iadj * Ra)

Iadj = 30nA @ 25 deg C

FW PHY Power Supply

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Page Notes
Power aliases required by this page:
- =PPBUS_S0_FWPWRSW (system supply for bus power)
- =PP3V3_S0_FWPORTPWRSW
Signal aliases required by this page:
- =FWPWR_PWRON (see related text note below)

Port Power Switch

BOM options provided by this page:

(NONE)

D
66 64 63 61 60 54 47 41 5 4
78 70 68

FireWire Port Current Sense

CRITICAL

Q4565

CRITICAL

F4565

PPBUS_G3H

CRITICAL

NDS9407

1.1A-24V
1

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

MINISMDC

R4565

C4565

470K

8
7
6
5

3
2
1

PPBUS_S5_FWPWRSW_F

PPBUS_S5_FW_FET_D_R

PPBUS_S5_FW_FET_D
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

0.5%
1W
MF
0612

20%
16V
CERM 2
402

D
PPBUS_S5_FW_FET

4 38 42 43 66

B340XF

VIN+ VIN-

FWPWR_EN_L_DIV
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
1

65 64 60 59 57 56 53 51 48
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66

R4566

U4595

PP3V3_S0

INA194
5

330K

5%
1/16W
MF-LF
2 402

Enables port power when machine

is running or on AC.

0.02 2

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

0.01uF

5%
1/16W
MF-LF
2 402

D4565
SMB

R4570

SOI-LF

SOT23-5

V+

1uF

FWPWR_IOUT
1A = 1V

OUT

GND
2 CRITICAL

10%
6.3V 2
CERM
402

FWPWR_EN_L

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
3

OUT

50V/V

C4595 1

Q4560

2N7002DW-X-F

67 51 50

SMC_ADAPTER_EN

SOT-363

Q4560

4
65 64 54 50 39 32 23 5

2N7002DW-X-F

PM_SLP_S3_L

SOT-363

Current Limit/Active Late-VG Protection

NO STUFF

R4521
0

Late-VG Event Detection

5%
1/8W
MF-LF
805

Q4520
SI2318DS

CRITICAL
66 43 42 38 4

SOT23-3

PPBUS_S5_FW_FETR4520
0.0202 PPFW_PORTA_ISENSE
1

44 42 38 5 4

CRITICAL

INA

9
10

INB

FW_PORT_FAULT_PU

5%
1/16W
MF-LF
2 402

10K

PP2V4_FWLATEVG_RC

1%
1/16W
MF-LF
402 2

4
V+

FWLATEGV_3V_REF

R4506
80.6K

1%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
2 402

LATEVG_EVENT_L

V-

SOD-123
2
1

MBR0540XXG

100K

5%
1/16W
MF-LF
2 402

200K 2
1%
1/16W
MF-LF
402

GATE2A
GATE1A

ONA

ONB

SENSEB
OUTB

FAULTA_L

GATE2B
GATE1B

FAULTB_L

16
13
14
15

8
5
6
7

FW_PORTA_PWRCTRL

FW_PORTB_PWRCTRL

GND

C4509
0.33uF

100pF

OUTA

FW_PORTPWR_EN
1

10%
2 10V
CERM-X5R
603

R4500

ONQ1

FW_PORT_FAULT_L

D4500

C4501

5%
2 50V
CERM
402

2.0M

LMC7211
SM-LF
1

R4529

R4509

U4500

5
1

1
1

20%
2 10V
CERM
402

10K

R45051

C4500
0.1UF

R4501

SENSEA

1
1

SOIC

1
4
2

C4520 1
1uF

10%
35V 2
X7R
805

C4525
1uF

10%
2 35V
X7R
805

CRITICAL

R4525

10.0202

FWLATEVG_3V_REF:
2.95V when port power is on
2.81V when port power is off

1%
0.25W
MF
805

PPFW_PORTB_ISENSE

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

0.020
0.025
0.030
0.033

PPFW_PORTB_VP_UF
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

4 44

SOT23-3

SI2318DS

Q4525

Current Limits

4 44

MAX5944

PP3V3_FWPHY

PPFW_PORTA_VP_UF
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

U4520

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

1%
0.25W
MF
805

PP2V4_FWLATEVG

ohm
ohm
ohm
ohm

=>
=>
=>
=>

2.4A
2A
1.66A (Ideal)
1.5A

NO STUFF

FireWire Port Power

R4526
1

SYNC_MASTER=(M1_MLB)

5%
1/8W
MF-LF
805

MAX5944 current limiter trips if integrator (counter)

reaches 16. A new sample (taken every 125 us) is weighted
as +1 if over the limit (at any point during the period)
and -1/128 if under the limit. As a result, the device
tends to trip easily on devices that produce periodic current
spikes. Current limit has been set higher to compensate.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

SYNC_DATE=(11/03/2005)

NOTICE OF PROPRIETARY PROPERTY

06
86

8
ELECTRICAL_CONSTRAINT_SET

PROVIDED
BY
PHY
PAGE

NET_TYPE
SPACING
PHYSICAL
FW
FW
FW
FW
FW
FW
FW
FW

FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D

FW_PORT1_TPA_FL_P
FW_PORT1_TPA_FL_N
FW_PORT1_TPB_FL_P
FW_PORT1_TPB_FL_N
FW_PORT2_TPA_FL_P
FW_PORT2_TPA_FL_N
FW_PORT2_TPB_FL_P
FW_PORT2_TPB_FL_N

AREF needs to be isolated from

all local grounds per 1394b spec

44
44

Cable Power

When a bilingual device is

connected to a beta-only device,
there is no DC path between them
(to avoid ground offset issue)

44
44
44
44

43 4

L4620

PPFW_PORTA_VP_UF

FERR-250-OHM
1
1

BREF should be hard-connected to

logic ground for speed signaling
and connection detection currents
per 1394b V1.33

Page Notes
Power aliases required by this page:
- =PPFW_PORT1
- =PP3V3_S5_FWLATEVG
- =GND_CHASSIS_FW_PORT1

44 43

PPFW_PORT1_VP
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

"Snapback" & "Late VG" Protection

C4624
0.001uF

PP2V4_FWLATEVG

20%
2 50V
CERM
402

DP4620
BAV99DW-X-F
0.001uF

20%
50V
CERM 2
402

FL4622

Termination
38
38

44 38

FW_B_TPBIAS
FW_A_TPBIAS

44 38

NOTE: FireWire TPA/TPB pairs are NOT

constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.

C4650

1uF

C4660
1uF

10%
2 6.3V
CERM
402

TI PHYs require 1uF even though

FW spec calls out 0.33uF

90-OHM-300mA
2012H
SYM_VER-2

R46511

R4660

56.2

1%
1/16W
MF-LF
2 402

56.2

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

FW_PORT1_TPB_P

38
44

44 38

FW_PORT1_TPA_P

R46611
56.2

C4622

FW_PORT2_TPA_P

FW_PORT2_TPA_N

44 38

FW_PORT2_TPB_P

44 38

FW_PORT2_TPB_N

44 38

FW_PORT1_TPA_P

44 38

FW_PORT1_TPA_N

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

SOT-363
5

20%
50V
CERM 2
402

38 44

NC 7

C4623

90-OHM-300mA
2012H
SYM_VER-2

514S0121

NO STUFF

C4627
0.01uF

0.01uF

20%
2 16V
CERM
402

20%
16V
2 CERM
402

C4626

5%
1/16W
MF-LF
402

38 44

INPUT

20%
50V
CERM 2
603

R4621
1

0.01uF

5%
1/16W
MF-LF
2 402

C4625 1

OUTPUT

R4629

20%
50V
CERM 2
402

38 44

0.001uF
38 44

FL4620

10%
50V
X7R 2
603-1

BAV99DW-X-F

(GND_FW_PORT1_VG)
44 FW_PORT1_TPA_FL_N
FW_PORT1_AREF
44 FW_PORT1_TPA_FL_P

NO STUFF
CRITICAL

0.1uF

DP4621
6

TPBTPB<R>
TPB+
VP
NC
VG
TPATPA<R>
TPA+

(PPFW_PORT1_VP)

5%
1/16W
MF-LF
402

C4629 1

0.001uF

44 38

R4620

FW_PORT1_TPA_N

SOT-363
2

44 38

5%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402 2

FW_PORT1_TPB_FL_N

(FW_PORT1_BREF)
44 FW_PORT1_TPB_FL_P

DP4621

56.2

F-RT-SM
10

R4623

BAV99DW-X-F

R4650

J4620
1394B-M9

FW_PORT1_TPB_N

1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)
1

CRITICAL
4

6
1

Place close to FireWire PHY

BOM options provided by this page:

(NONE)

20%
50V
CERM 2
402

PORT 1
BILINGUAL

NO STUFF
CRITICAL

SOT-363
2

C4620 1
0.001uF

5%
1/16W
MF-LF
402

BAV99DW-X-F

Signal aliases required by this page:

(NONE)
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.

DP4620

R4622

SOT-363
5

C4621 1

GND_CHASSIS_DVI_BOT

6 40 44 79

38 44

MAKE_BASE=TRUE
38 44

MAKE_BASE=TRUE
44 38

FW_PORT1_TPB_P

44 38

FW_PORT1_TPB_N

FW_PORT1_TPB_P
MAKE_BASE=TRUE

FW_PORT1_TPB_N
MAKE_BASE=TRUE

38 44

Cable Power
38 44

"Snapback" & "Late VG" Protection

43 4

R46531

R4652
56.2

R4662

56.2

1%
1/16W
MF-LF
2 402

56.2

1%
1/16W
MF-LF
402 2

44 43

FERR-250-OHM
1

1%
1/16W
MF-LF
402 2

DP4630

1
C4654 R4654
4.99K

220pF

20%
50V
CERM 2
402

1
C4664 R4664
4.99K

220pF

1%
1/16W
MF-LF
402 2

5%
2 25V
CERM
402

SOT-363
2

1%
1/16W
MF-LF
402 2

44 38

PPFW_PORT2_VP
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

C4634

0.001uF

SOT-363
5

20%
50V
CERM 2
402

BAV99DW-X-F

C4631 1

0.001uF

2
SM

DP4630

BAV99DW-X-F

C4630 1

FW_PORT2_TPA_C

0.001uF
1

L4630

PPFW_PORTB_VP_UF

PP2V4_FWLATEVG

56.2

1%
1/16W
MF-LF
2 402

FW_PORT1_TPA_C

R46631

20%
2 50V
CERM
402

PORT 2
1394A

3
4
1

FW_PORT2_TPA_P

SYM_VER-2

44 38

J4630

FW_PORT2_TPA_N

1394A

2012

F-RT-TH-LF

120-OHM

FL4630
44 43 42 38 5 4

44 38

FW_PORT2_TPB_P

44 38

FW_PORT2_TPB_N

44
38

3
2012

DP4631

120-OHM

DP4631

BAV99DW-X-F

5%
1/16W
MF-LF
402 2

FW_PC0

SYM_VER-2

CRITICAL
1K

44 38

PP3V3_FWPHY

R46001

BAV99DW-X-F

SOT-363
2

SOT-363
5

FL4631

FW_PORT2_TPA_FL_P

FW_PORT2_TPA_FL_N

FW_PORT2_TPB_FL_P

FW_PORT2_TPB_FL_N

TPO# (TPA-)
TPI (TPB+)
TPI# (TPB-)

(PPFW_PORT2_VP)

C4632 1

VGND

(GND_FW_PORT2_VG)

0.001uF

20%
50V
CERM 2
402

C4633 1
0.001uF

20%
50V
CERM 2
402

C4635

C4636 1

0.01uF

20%
2 50V
CERM
603

(TPA+)

TPO

FW_PC0

MAKE_BASE=TRUE

CRITICAL
CRITICAL

20%
16V
CERM 2
402

514-0255

GND_CHASSIS_USB

6 44 46

GND_CHASSIS_DVI_BOT

6 40 44
79

Late-VG Protection Power

44 43 42 38 5 4

PP3V3_FWPHY

332

1%
1/16W
MF-LF
402

400-OHM-EMI
1

PP2V4_FWLATEVG_R
VOLTAGE=2.4V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

C4691 1

PP2V4_FWLATEVG needs to be biased

0.1uF
20%
to at least 2.1V for FW signal integrity
10V
CERM
and should be biased to 2.4V for margin
402
R4690 should be 390 Ohms max for a 3.3V rail

PP2V4_FWLATEVG
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.4V

2
SM-1
3

C4692 1
10%
50V
CERM 2
402

CRITICAL

D4690

0.001uF
2

FireWire Ports

R4699

L4690

R4690

MMBZ5227B
1

43 44

5%
1/16W
MF-LF
402

ESD and late-VG rail

for snap-back diodes
(Common to all ports)

SYNC_MASTER=(MASTER)

GND_CHASSIS_USB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

SOT23

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

6 44 46

06
86

Top-Case Connector

D
62 59 58 56 51 41 37 32 27 5
80 66 64 63
66 65 54 52 51 50 35 27 26 5
68 67
80 66 61 51 45 5

PP3V3_S3
PP3V42_G3H
PP5V_S3

54 51 50 5

22 6
22 6

OUT

BI
BI

SMC_LID
SMC_ONOFF_L

USB_TRACKPAD_P
USB_TRACKPAD_N
CRITICAL

M-ST-SM
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16

LIO_TEMP
CRITICAL

CRITICAL

J4900

OUT

LIO Temp Sensor Connector

QT500166-L020
51 50

J4990
88460-0401
KBDLED_RETURN
KBDLED_ANODE

OUT

F-RT-SM
6

4
3
2

SMBUS_SB_SCL
SMBUS_SB_SDA

BI
BI

D4900
SC-75

29 33
5 23
27 28
47
5 23 27 28 29 33 47

1
3
2

516S0350

SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL

RCLAMP0502B

27 50

Camera Connector
NO STUFF

L4930

C4931 1

FERR-220-OHM

0.001uF

20%
50V
CERM 2
402

PP5V_S3_CAMERA_F

VOLTAGE=5V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

PLACEMENT_NOTE=Place next to J4931 pin 7

PP5V_S3

0402
1

CRITICAL

0.01uF

165-OHM

J4931

SM
SYM_VER-2

C4932

20%
2 16V
CERM
402

FL4935

CRITICAL
CAMERA-M1-CUS

5 45 51 61 66 80

USB2_CAMERA_N

5 6 22

USB2_CAMERA_P

5 6 22

SMBUS_SMC_0_S0_SDA
BI

SMBUS_SMC_0_S0_SCL_R
BI

F-RT-SM
7

Connector shield

2
1
2
3
4
5
6

Twin-Ax Pair 1
(40 AWG)
Twin-Ax Pair 2
(40 AWG)
Standard wires
(28 AWG)
Connector shield

USB2_CAMERA_N_F
USB2_CAMERA_P_F
SMBUS_ATS_SDA_F
SMBUS_ATS_SCL_F

CRITICAL

FL4936
165-OHM
1

SM
SYM_VER-2

NO STUFF

5 27 50 53

D4930
RCLAMP0502B

SC-75

518S0371

CRITICAL
GND_CAMERA

NO STUFF

C4930 1

VOLTAGE=0V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

L4931

FERR-220-OHM
1

2
0402

0.001uF

20%
50V
CERM 2
402

PLACEMENT_NOTE=Place next to J4931 pin 8

Internal USB Connections

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Port Power Switch

Right USB Port

CRITICAL

U5290
70 67 66 65 64 63 61 51 25 5

PM_SLP_S4_L

IN_0

OUT_0

IN_1

OUT_1 7

EN*
GND
1

C5290 1
10uF

20%
6.3V 2
CERM
805-1

C5291
0.1UF

20%
2 10V
CERM
402

OC*
THRML

FERR-250-OHM

PP5V_S3_RTUSB_ILIM

MSOP
2

OUT_2
65 63 50 47 41 23 5

L5205

TPS2051

PP5V_S5

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

RTUSB_OC_L

C5295 1
10uF

20%
6.3V 2
CERM
805-1

C5296

NO STUFF
1

OUT

22 6

C5292

20%
2 6.3V
CERM-X5R
402

20%
2 6.3V
POLY
B2

20%
16V
CERM 2
402

CRITICAL

6 22

0.47uF

100UF

L5200
165-OHM

5%
1/16W
MF-LF
402

PAD

C5205
0.01uF

R5292
RTUSB_OC_L_RC

PP5V_S3_RTUSB_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

22 6

USB2_RT_N
USB2_RT_P

SM
SYM_VER-2

CRITICAL

J5200
UAR2X

F-RT-SM-USB-RGT1
5
6
1 VBUS

USB2_RT_F_N
USB2_RT_F_P

RTUSB_ESD

D5200

C5206

RCLAMP0502B
CRITICAL

D+

GND

20%
16V
CERM 2
402

D-

0.01uF

SC-75

514S0115

L5206

FERR-250-OHM
1

2
SM

GND_CHASSIS_USB

6 44

GND_RTUSB
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=0V

Place L5200, L5205 and L5206 across moat

External USB Connector

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Left I/O Board Connector

CRITICAL

J5500

QT510806-L111-7F
NC

22 6 5
22 6 5

34 5
34 5

49 22 5
49 22 5

49 5
49 5

34 5
34 5

49 22 5
49 22 5

49 5
49 5

66 65 25 24 19 17 16 13 9 8 5

USB2_LT2_N
USB2_LT2_P
USB2_LT_N
USB2_LT_P
USB2_EXCARD_N
USB2_EXCARD_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_P
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_C_P
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P

PP1V5_S0

NC
PPBUS_G3H

66 64 63 61 60 54 43 41 5 4
78 70 68

XW5505
SM
PP5V_S0

57 56 54 52 42 36 31 25 5 4
80 79 78 70 67 66 65 61 60

Place XW5505 at 5V switcher

(500 mA)

PP5V_S0_AUDIO
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

F-ST-SM
84
81
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
83

NC
SMC_BC_ACOK
LT2USB_OC_L
LTUSB_OC_L

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
82

5 50 51 67 68
4 5 22
5 6 22

SYS_ONEWIRE
ALS_GAIN

5 50 51

LTALS_OUT
LIO_PLT_RESET_L

5 6 50

5 56
5 26

EXCARD_CLKREQ_L
MINI_CLKREQ_L
EXCARD_OC_L
SMC_EXCARD_CP
PM_SLP_S3_LS5V
SMC_EXCARD_PWR_EN
PM_SLP_S4_L
PCIE_WAKE_L

5 33 34
5 33 34
5 6 22 51
5 50 51
5 61 65
5 50
5 23 41 46 50 63 65
5 23 39

ACZ_SDATAOUT
ACZ_BITCLK
ACZ_SDATAIN<0>
ACZ_SYNC

5 21 86
5 21 86
5 21 86
5 21 86

ACZ_RST_L
SMBUS_SB_SCL
SMBUS_SB_SDA

5 21 86
5 23 27 28 29 33 45
5 23 27 28 29 33 45

B
XW5515
SM
5

516S0361

GND_AUDIO

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

(500 mA)
Place XW5515 at 5V switcher

Left I/O Board Connector

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Battery Current Sense

DCIn Current Sense

CHGR_CSOP_R

CHGR_CSIN_R

CHGR_CSON_R

CHGR_CSI_P

Placement Note:

Place near R8308

Placement Note:

Place near R8307

VIN+ VIN-

U5615

U5605

INA193

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

PP3V3_S0
5
1

V+ SOT23-5 OUT
CRITICAL

LIO_BATT_ISENSE

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

1uF
10%
6.3V

INA193

PP3V3_S0
5
1

C5615

2 CERM

VIN+ VIN-

C5605
1uF

GND

SOT23-5

OUT

LIO_DCIN_ISENSE

CRITICAL
GND

10%
6.3V

2 CERM

402

V+

402

TMP106 Thermal Sensor

65 64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66

PP3V3_S0

1NO STUFF

R5651

V+

U5650

5%
1/16W
MF-LF
2 402

TMP106
WCSP-6

50 27 10 4

SMBUS_SMC_B_S0_SDA

SDA

50 27 10 4

SMBUS_SMC_B_S0_SCL

SCL

ALERT

CRITICAL

TMPSNSR_A0

Temp Sensor has address x90,x91

R5650

0
GNDS

C5650
0.1uF

5%
1/16W
MF-LF
2 402

20%

Place sensor on
bottom side
near L8300 and
Q8301 and Q8302

2 10V
CERM
402

Current & Thermal Sensors

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

PCI-E x1 Port "A" = Ethernet (Yukon)

PCI-E x1 Port "B" = PCI-E Mini Card
C5710
0.1uF

49 47 5

49
47 5

PCIE_MINI_R2D_C_P

PCIE_B_R2D_C_P

MAKE_BASE=TRUE

49
47 5

PCIE_MINI_R2D_C_N

10%
16V
X5R
402

PCIE_MINI_R2D_C_N

C5711
0.1uF
1

PCIE_B_R2D_C_N

MAKE_BASE=TRUE

PCIE_MINI_D2R_P

49 47 22 5

PCIE_MINI_D2R_N

10%
16V
X5R
402

PCIE_MINI_D2R_P

Place caps close to SB

PCIE_MINI_D2R_P

5 22 47 49

PCIE_MINI_D2R_N

5 22 47 49

MAKE_BASE=TRUE

PCIE_MINI_D2R_N
MAKE_BASE=TRUE

PCI-E x1 Port "C" = ExpressCard

C5720

0.1uF

49 47 5

49
47 5

PCIE_EXCARD_R2D_C_P

PCIE_C_R2D_C_P

MAKE_BASE=TRUE

49
47 5

PCIE_EXCARD_R2D_C_N

10%
16V
X5R
402

C5721
0.1uF
1

Place caps close to SB

PCIE_C_R2D_C_N

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_P

49 47 22 5

PCIE_EXCARD_D2R_N

49 47 22 5

PCIE_EXCARD_D2R_P

10%
16V
X5R
402

PCIE_EXCARD_D2R_P

5 22 47 49

PCIE_EXCARD_D2R_N

5 22 47 49

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_N
MAKE_BASE=TRUE

PCI-E x1 Port "D" = Unused

49 22

TP_PCIE_D_R2DP

49 22

TP_PCIE_D_R2DN

49 22

TP_PCIE_D_D2RP

49 22

TP_PCIE_D_D2RN

49 22

TP_PCIE_E_R2DP

49 22

TP_PCIE_E_R2DN

TP_PCIE_D_R2DP

22 49

TP_PCIE_D_R2DN

22 49

TP_PCIE_D_D2RP

22 49

TP_PCIE_D_D2RN

22 49

TP_PCIE_E_R2DP

22 49

TP_PCIE_E_R2DN

22 49

TP_PCIE_E_D2RP

22 49

TP_PCIE_E_D2RN

22 49

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

PCI-E x1 Port "E" = Unused

MAKE_BASE=TRUE
MAKE_BASE=TRUE

49 22

TP_PCIE_E_D2RP

49 22

TP_PCIE_E_D2RN

MAKE_BASE=TRUE
MAKE_BASE=TRUE

PCI-E x1 Port "F" = Unused

49 22

TP_PCIE_F_R2DP

49 22

TP_PCIE_F_R2DN

49 22

TP_PCIE_F_D2RP

49 22

TP_PCIE_F_D2RN

TP_PCIE_F_R2DP

22 49

TP_PCIE_F_R2DN

22 49

TP_PCIE_F_D2RP

22 49

TP_PCIE_F_D2RN

22 49

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

PCI-E Connections
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

UNUSED PINS HAVE THE FORMAT

SMC_XXX WHERE XXX IS THE PORT NUMBER.
THEY ARE SET BY SOFTWARE TO BE
DRIVEN OUTPUTS ALWAYS SO THEY
CAN BE LEFT NO-CONNECTED.

PP3V42_G3H

65 54 52 51 50 45 35 27 26 5
68 67 66

OMIT

OUT

P66/IRQ6*/KIN6*
P67/IRQ7*/KIN7*

P20

P70/AN0

P21

P71/AN1

P22
P23

P72/AN2
P73/AN3

68 51

OUT

68 51

OUT

59 52 21 5
59 52 21 5

59 52 21 5

26 5

59 52 23 5

OUT

52 51 5

OUT

52 51 5

IN
BI

P74/AN4
P75/AN5

P26

P76/AN6

P27

P77/AN7

P30/LAD0
P31/LAD1

P80/PME*
P81/GA20

P32/LAD2

P82/CLKRUN*

P33/LAD3
P34/LFRAME*

P83/LPCPD*
P84/IRQ3*/TXD1

P35/LRESET*

P85/IRQ4*/RXD1

P36/LCLK
P37/SERIRQ

P86/IRQ5*/SCK1/SCL1
P90/IRQ2*

P40/TMIO

P91/IRQ1*

P41/TMO0
P42/SDA1

P92/IRQ0*
P93/IRQ12*

P43/TMI1/EXSCK1

P94/IRQ13*

P44/TMO1
P45

P95/IRQ14*
P96/EXCL

P46/PWX0/PWM0

P97/IRQ15*/SDA0

C7
A7
B7
D6
C6
A6
B6
K4
J2
J1
J3
J4
H2
H1
G2

22 55

20%
2 10V
CERM
402

LAYOUT NOTE:
PLACE C5807 NEAR PIN F1

22 55
51

5 21 51 52

SMC_VCL

54
54

C5807

LAYOUT NOTE:
VCL IS INTERNAL RAIL 0.47UF
20%
PLACE R5899 AND C5820 NEAR SMC PIN N14,N15
2 6.3V
CERM-X5R

54
54

402

54
54
54

PP3V42_G3H

65 54 52 51 50 45 35 27 26 5
68 67 66

PP3V3_AVREF_SMC

R5899
4.7

5%
1/16W
MF-LF
402

5 23 52 59

5 23 51 52 59
51

C5820
0.1UF

20%
2 10V
CERM
402

51
27

5 45 51 54

56 54 51 50

OMIT

(3 OF 4)
IN

5 23 41 46 47 63 65
51

5 23 51
51

5%
1/16W
MF-LF
2402

BGA
MD2

E2
K1

NMI

ETRST*

MD1

5 51 67

SMC_RST_L
SMC_XTAL
SMC_EXTAL

1R5801
R5809
10K
10K

SMC_H8S2116

GND_SMC_AVSS
52 51 5

PP3V42_G3H

66 65 54
35 27 26 5
52 51 50 45
68 67

U5800

5 47 51 67 68

5 23 32 39 43 54 64 65

PP3V3_AVCC_SMC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

RES*

A2
B2

XTAL
EXTAL

5%
1/16W
MF-LF
2402

SMC_MD1

5 52

KBC_MDE
SMC_NMI

5 52

SMC_TRST_LIN

5 52

35
5 27 45 53

P47/PWX1/PWM1
P50
P51

AVSS

P52/SCL0

VSS

D1
P4
R4
F12
F13
B13
A13
A4
B4
D2

53 27 5

P24
P25

N12
R13
P13
R14
P14
R15
N13
P15

20%
2 10V
CERM
402

22 55

M14
M15

P65/KIN5*

P16
P17

AVREF

OUT

P15

1 C58031 C58041 C58051 C5806

C5802
22UF
0.1UF
0.1UF
0.1UF
0.1UF

20%
2 6.3V
CERM
805

43 51 67

VCL

OUT

60 5

P63/KIN3*
P64/KIN4*

AVREF

23 5

P13
P14

SMC_PM_G2_EN
OUT
SMC_ADAPTER_EN OUT
SPI_ARB
IN
SPI_SCLK
IN
SPI_SI
OUT
SPI_SO
IN
SMC_PROCHOT_3_3_L
IN
FWH_INIT_L
IN
SMC_CPU_ISENSE IN
SMC_CPU_VSENSE IN
SMC_GPU_ISENSE IN
SMC_GPU_VSENSE IN
SMC_DCIN_ISENSE IN
SMC_PBUS_VSENSE IN
SMC_BATT_ISENSE IN
SMC_FWIRE_ISENSEIN
SMC_WAKE_SCI_L IN
SMC_TPM_GPIO
OUT
PM_CLKRUN_L
BI
PM_SUS_STAT_L
IN
SC_TX_L
OUT
SC_RX_L
IN
SMBUS_SMC_BSB_SCL
BI
SMC_ONOFF_L
IN
SMC_BC_ACOK
IN
SMC_BS_ALRT_L
IN
PM_SLP_S3_L
IN
PM_SLP_S4_L
IN
PM_SLP_S5_L
IN
SMC_CLK32K_SUSCLK
IN
SMBUS_SMC_0_S0_SDA
BI

VCC

OUT

L13
L14
L15
K12
K13
K14
J12
J13

P2
P1
J15
A1
F1

BGA
(1 OF 4)

P61/KIN1*
P62/KIN2*

VCC
VCC

64 51

P60/KIN0*

SMC_H8S2116

P11
P12

VCC

OUT

U5800

P10

N14
N15

37 4

PM_LAN_ENABLE
B12
SMC_RSTGATE_L
C13
ALL_SYS_PWRGD
A15
RSMRST_PWRGD
B14
SMC_SB_NMI
B15
PM_RSMRST_L
C14
IMVP_VR_ON
D12
PM_PWRBTN_L
C15
TP_SMC_P20
D13
TP_SMC_P21
D14
TP_SMC_P22
D15
TP_SMC_P23
E12
SMC_BATT_TRICKLE_EN_L
E14
SMC_BATT_CHG_EN
E15
TP_SMC_P26
E13
TP_SMC_P27
F14
LPC_AD<0>
D9
LPC_AD<1>
C9
LPC_AD<2>
A9
LPC_AD<3>
B9
LPC_FRAME_L
D8
SMC_LRESET_L
C8
PCI_CLK_SMC
A8
INT_SERIRQ
D7
TP_SMC_XDP_TMS
A5
SMC_SYS_LED_16B
B5
SMBUS_SMC_BSB_SDA
D5
SMC_TPM_PP
C3
TP_SMC_XDP_TRST_L
B1
TP_SMC_XDP_TCK
C2
TP_SMC_SYS_LED
D3
SMC_SYS_KBDLED
C1
SMC_TX_L
G1
SMC_RX_L
G4
SMBUS_SMC_0_S0_SCL F2

AVCC

OUT

AVCC

23 5

65 26

P12
R12

NOSTUFF

1R5803
1R5802
R5898
10K
0
10K

5%
1/16W
MF-LF
2402

OMIT
21
52 22 5
26 23 5
59 51
51 29 28 14

IN
IN
OUT
IN

51 47 5

OUT

54 5
51 47 5
47 5

OUT

OUT
IN
OUT

OUT

54 51

SMC_RCIN_L
BOOT_LPC_SPI_L
PM_SYSRST_L
SMC_TPM_RESET_L
PM_EXTTS_L
PM_THRM_L
SYS_ONEWIRE
PM_BATLOW_L
SMC_EXTSMI_L
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
ISENSE_CAL_EN
SMC_EXCARD_CP
SMC_EXCARD_PWR_EN
SMC_EXCARD_OC_L
SMC_XDP_TDO_3_3
SMC_FAN_0_CTL
SMC_FAN_1_CTL
TP_SMC_FAN_2_CTL
TP_SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
TP_SMC_FAN_2_TACH
TP_SMC_FAN_3_TACH
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
TP_SMC_ANALOG_ID
SMC_P1V05S0_ISENSE
SMC_P1V8S3_ISENSE
ALS_LEFT
ALS_RIGHT

R3
P3
R2
N3
R1
N2
M4
N1
B10
A10
D10
A11
B11
C11
A12
D11
G14
G15
G13
G12
H14
H15
H13
H12
M11
P11
R11
N11
P10
R10
N10
M10

PA0/KIN8*/PA2DC

U5800

SMC_H8S2116

PA1/KIN9*/PA2DD

PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD

PE0

BGA

PE1*/ETCK

(2 OF 4)

PE2*/ETDI
PE3*/ETDO

PA4/KIN12*/PS2BC
PA5/KIN13*/PS2BD
PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD
PB0/LSMI*
PB1/LSCI

PE4*/ETMS
PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3
PF2/IRQ10*/TMOY
PF3/IRQ11*/TMOX
PF4/PWM4

PB2

PF5/PWM5

PB3
PB4

PF6/PWM6
PF7/PWM7

PB5
PB6

PG0/EXIRQ8*/TMIX

PB7

PG1/EXIRQ9*/TMIY
PG2/EXIRQ10*/SDA2

PC0/TIOCA0/WUE8*

PG3/EXIRQ11*/SCL2

PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10*

PG4/EXIRQ12*/EXSDAA
PG5/EXIRQ13*/EXSCLA

PC3/TIOCD0/TCLKB/WUE11*

PG6/EXIRQ14*/EXSDAB

PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13*

PG7/EXIRQ15*/EXSCLB

PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*

PH0/EXIRQ6*
PH1/EXIRQ7*

PD0/AN8

PH2/FWE
PH3/EXEXCL

PD1/AN9

PH4

PD2/AN10
PD3/AN11

PH5

M3
M2
M1
L4
L2
M7
P6
R6
N6
M6
R5
P5
N5
P9
R9
N9
P8
R8
M8
P7
R7
E1
F3
K2
C4
D4
B3

SMC_CASE_OPEN
IN
SMC_TCK
IN
SMC_TDI
IN
SMC_TDO
OUT
SMC_TMS
IN
TP_SMC_PF0
TP_SMC_PF1
SMC_LID
IN
SMC_CPU_RESET_3_3_L
IN
SMC_BATT_ISET
OUT
TP_SMC_BATT_VSETOUT
SMC_SYS_ISET
OUT
TP_SMC_SYS_VSET OUT
SPI_CE_L
BI
SMC_XDP_TCK_3_3 IN
SMBUS_SMC_BSA_SDA
BI
SMBUS_SMC_BSA_SCL
BI
SMBUS_SMC_A_S3_SDA
BI
SMBUS_SMC_A_S3_SCL
BI
SMBUS_SMC_B_S0_SDA
BI
SMBUS_SMC_B_S0_SCL
BI
SMC_PROCHOT
OUT
SMC_THRMTRIP
OUT
SMC_FWE
IN
ALS_GAIN
OUT
SMS_INT_L
OUT
SMS_ONOFF_L
OUT
51

XW5800
SM

5 51 52
5 51 52

5 51 52

GND_SMC_AVSS

50 51 54 56

5 51 52

45 51
51

68
51
68
51

22 55

5 27 67

5 27 67
27 45
27 45

4 10 27 48
4 10 27 48

51
51

5 6 47
23 51
58

PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15

OMIT

U5800
SMC_H8S2116
BGA

SMC

(4 OF 4)

G3
H3
K3
L3
N4
M5
N7
M12
M13
L12
K15
J14

NC0

NC12

NC1
NC2

NC13
NC14

NC3

NC15

NC4
NC5

NC16
NC17

NC6
NC7

NC18
NC19

NC8

NC20

NC9
NC10

NC21
NC22

F15
A14
C12
C10
C5
A3
B8
E4
H4
M9
N8

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

NC11

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

06
86

FWH_INIT_L

SMC Reset Button / Brownout Detect

FWH_INIT_L

5 21 50 51 52

MAKE_BASE=TRUE
54 51 50

SMC_P1V05S0_ISENSE

79 78 70 66 65 64 60 59
48 43 37 36 34 33 29 28 27 26
22 21 20 19 17 14 10 5 4
50 51 54 25 24 23
57 56 53

SMC_P1V05S0_ISENSE
MAKE_BASE=TRUE

65 54 52 51 50 45 35 27 26 5
68 67 66

PP3V42_G3H

54 51 50

C5900

R5900

0.1uF

SMC 1.05V to 3.3V Level Shifting

50 51 54

5%
1/16W
MF-LF
2 402

U5900
RN5VD30A-F
SOT23-5

SMC_MANUAL_RST_L
OMIT
1

R5901

C5901

5
4

PM_EXTTS_L

51 50

TP_SMC_SYS_LED

51 50

TP_SMC_ANALOG_ID

TP_SMC_SYS_LED

SMC_RST_L

OUT

51 50

TP_SMC_BATT_VSET

5%
1/16W
MF-LF
402 2

10%
16V
CERM 2
402

51 50

TP_SMC_FAN_2_CTL

TP_SMC_BATT_VSET

50 51
51 7

TP_SMC_SYS_VSET

TP_SMC_FAN_3_CTL

51 50

TP_SMC_FAN_3_TACH

51 50

TP_SMC_XDP_TCK

CPU_PROCHOT_L

V-

R59711

TP_SMC_FAN_2_CTL

51 50

LMC7211
SM-LF
1
SMC_PROCHOT_3_3_L

V+

50 51

MAKE_BASE=TRUE

TP_SMC_FAN_2_TACH

U5977

2
4

50 51

MAKE_BASE=TRUE

51 50

1.05V Mid-Reference
P0V46_SMC_LSREF

MAKE_BASE=TRUE

TP_SMC_SYS_VSET

20%
10V
CERM 2
402

VOLTAGE=0.46V

50 51

MAKE_BASE=TRUE

51 50

0.1uF

6.2K

50 51

TP_SMC_ANALOG_ID

5 50 52

C5977 1

R59701

14 28 29 50 51

MAKE_BASE=TRUE

GND
3
CRITICAL

0.01UF

5%
1/10W
MF-LF
2 603

OUT

CD
NC

PM_EXTTS_L
MAKE_BASE=TRUE

VDD

20%
10V
CERM 2
402

Silk: "SMC RST"

SMC_P1V8S3_ISENSE

PP3V3_S0

MAKE_BASE=TRUE
51 50 29 28 14

SMC_P1V8S3_ISENSE

TP_SMC_FAN_2_TACH

5%
1/16W
MF-LF
402 2

50 51

MAKE_BASE=TRUE

TP_SMC_FAN_3_CTL

50 51

MAKE_BASE=TRUE

TP_SMC_FAN_3_TACH

50 51

MAKE_BASE=TRUE

TP_SMC_XDP_TCK

50 51

MAKE_BASE=TRUE
51

SMC Crystal Circuit

CRITICAL

Y5920

20.00MHZ
5X3.2-SM

51 50

TP_SMC_XDP_TRST_L

51 50

TP_SMC_P20

TP_SMC_XDP_TRST_L

50 51

TP_SMC_P20

CPU_PROCHOT_L

50 51

5%
1/10W
MF-LF
2 603

51 50

TP_SMC_P21

51 50

TP_SMC_P22

TP_SMC_P21

2N7002DW-X-F

50 51

TP_SMC_P23

51 50

TP_SMC_P26

TP_SMC_P23

SMC_PROCHOT

MAKE_BASE=TRUE

TP_SMC_P26

50 51

MAKE_BASE=TRUE
51 50

TP_SMC_P27

51 50

TP_SMC_PF0

51 50

TP_SMC_PF1

TP_SMC_P27

50 51

MAKE_BASE=TRUE

TP_SMC_PF0

PM_THRMTRIP_L

50 51

SMC AVREF Supply

TP_SMC_PF1

50 51

MAKE_BASE=TRUE

SMC_TPM_GPIO

PP3V3_AVREF_SMC

2N7002DW-X-F

SOT23-3

OUT

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

SMC_TPM_PP

0.47uF

20%
2 16V
CERM
402

20%
2 6.3V
CERM-X5R
402

TPM_GPIO2

TPM_PP

59
65 54 52 51 50 45 35 27 26 5
68 67 66
59 58 56 51 45 41 37 32 27 5
80 66 64 63 62
59 58 56 51 45 41 37 32 27 5
80 66 64 63 62

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

SC_TX_L

50 54 56

SMC_RX_L

50 23
5 50 51 52
59 50

5%
1/16W
MF-LF
402

R5993
50

GND_SMC_AVSS

SMC_TX_L

54 51 50 45 5
5 50 51 52
50 45

5%
1/16W
MF-LF
402

50
52 51 50 5

R5994

SMC_EXCARD_OC_L

52 51 50 5

EXCARD_OC_L

50 47 5
67 50 5
52 50 5

SMC PWRGD Circuit

52 50 5
52 50 5
52 50 5

Reports when 5V S5 and 3.3V S5 are in regulation

50
70 67 66 65 64 63 61 46 25 5
65 54 52 51 50 45 35 27 26 5
68 67 66

PP5V_S3

PP5V_S5
PP3V42_G3H

50
50

68 50

2.2K

5%
1/16W
MF-LF
402 2

C5960 1

R5950

R59611

100

10K

5%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
402 2

SYS_LED_ILIM

R5963
16.2K

1%
1/16W
MF-LF
2 402

67 50 43

20%
10V
CERM 2
402

P1V71_SMC_REF

1.71V Reference

68 50

0.1uF

50
68 67 50 47 5

2
4

SYS_LED_L_VDIV

Q5950

R5952
4.7K

R5962
10K

OUT

1%
1/16W
MF-LF
402 2

50 23 5

SM-LF
1

V-

R5930
R5931

10K
10K

SMC_ONOFF_L
SMC_LID
SMC_FWE
SMC_TX_L
SMC_RX_L

R5932
R5933
R5934
R5935
R5936

10K
100K
10K
10K
100K

SYS_ONEWIRE
SMC_BS_ALRT_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_CPU_RESET_3_3_L
SMC_XDP_TCK_3_3
SMC_XDP_TDO_3_3

R5937
R5938
R5939
R5940
R5941
R5942
R5980
R5981
R5982

ONEWIRE_PU
2.0K 1
2
5%
100K 1
2
5%
10K 1
2
5%
10K 1
2
5%
10K 1
2
5%
10K 1
2
5%
10K 1
2
5%
10K 1
2
5%
10K 1
2

SMC_BATT_TRICKLE_EN_L
SMC_BATT_CHG_EN
SMC_ADAPTER_EN
SMC_CASE_OPEN
SMC_BC_ACOK
SMC_EXCARD_CP
PM_SUS_STAT_L
PM_SLP_S5_L

R5943
R5944
R5945
R5946
R5947
R5948
R5983
R5984

10K
10K
10K
10K
470K
10K
100K
100K

P5VS5_PGOOD

OUT

R5964

Q5952

64 51 50

2N7002

1%
1/16W
MF-LF
2 402

402
402
402
402
402

1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W

MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF

402
402
402
402
402
402
402
402
402

5%
5%
5%
5%
5%
5%
5%
5%

1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W

MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF

402
402
402
402
402
402
402
402

SMC Support
SYNC_MASTER=M1_MLB

SOT23-LF

RSMRST_PWRGD
ISL6269 undervoltage threshold 81-87% (2.67 - 2.87V)
NOTE: R5965 acts as 10K pull-up for PGOOD signal

SYNC_DATE=02/10/2006

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

RSMRST_PWRGD
MAKE_BASE=TRUE
1

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

OUT

50 51 64

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

C5969
0.0022uF

SIZE

10%
2 50V
CERM
402

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

MF-LF
MF-LF
MF-LF
MF-LF
MF-LF

10K

5%
1/16W
MF-LF
2 402

10K

1/16W
1/16W
1/16W
1/16W
1/16W

NOTICE OF PROPRIETARY PROPERTY

SMC_SYS_LED_16B

5%
5%
5%
5%
5%

R5965

5V Comp threshold set to 4.480V (89.6%)

1/16W MF-LF 402

64 65

SYS_LED_L

5%
5%

1
5

SYS_LED_ANODE

5%
1/16W
MF-LF
402 2

P5VS5_COMP_POS

2N3906
SOT23-LF

59 52 50 23 5

LMC7211
V+

50 47 5

U5960

PP3V42_G3H
PP3V3_S3
PP3V3_S3

SMS_INT_L
SMC_TPM_RESET_L

5 6 22 47

5%
1/16W
MF-LF
402

System (Sleep) LED Circuit

SOT-363

5%
1/16W
MF-LF
402

SC_RX_L

20%
6.3V 2
X5R
603

R5992

10uF

5%
1/16W
MF-LF
402

C5967
0.01uF

C5965 C5966 1

SMC_THRMTRIP

R5991

R5995
50

GND

TPM_GPIO1
SMC_TPM_GPIO2

SMC_TPM_PP
50

Q5995

REF3133
1

5%
1/16W
MF-LF
402

VR5965
PP3V42_G3H

CRITICAL

R59511

7 14 21

MAKE_BASE=TRUE

R5990

66 61 45 5
80

SOT-363

50 51

SMC_TPM_GPIO1

65 54 52 51 50 45 35 27 26 5
68 67 66

Q5995

50 51

TP_SMC_P22
MAKE_BASE=TRUE

51 50

7 51

MAKE_BASE=TRUE

5%
50V
CERM
402

SMC 3.3V to 1.05V Level Shifting

50 51

MAKE_BASE=TRUE

R5910

15pF

SMC_EXTAL

OUT

5 45 50 51 54

Silk: "PWR BTN"

C5921

2
50

TP_SMC_XDP_TMS
MAKE_BASE=TRUE
MAKE_BASE=TRUE

SMC_ONOFF_L
OMIT

5%
50V
CERM
402

MAKE_BASE=TRUE

15pF

SMC_XTAL

TP_SMC_XDP_TDO_L

TP_SMC_XDP_TMS

Debug Power Button

C5920
50

TP_SMC_XDP_TDO_L

06
86

CRITICAL
LPCPLUS

J6000

QT500306-L021-9F
NC
51 50 21 5
34 5

59 50 21 5
59 50 21 5

59 50 23 5
59 51 50 23 5
51 50 5
51 50 5
51 50 5
50 5
51 50 5

23 5

FWH_INIT_L
PCI_CLK_PORT80_LPC
LPC_AD<2>
LPC_AD<3>
INT_SERIRQ
PM_SUS_STAT_L
SMC_TDI
SMC_TCK
SMC_RST_L
SMC_NMI
SMC_RX_L
SV_SET_UP (GPIO15)
NC

M-ST-SM
31

PP3V42_G3H
PP5V_S0
LPC_AD<0>
LPC_AD<1>
LPC_FRAME_L
PM_CLKRUN_L
BOOT_LPC_SPI_L
SMC_TMS
DEBUG_RST_L
SMC_TRST_L
SMC_TDO
SMC_MD1
SMC_TX_L

5 26 27 35 45 50 51 54 65 66 67
68
4 5 25 31 36 42 47 54 56 57 60
61 65 66 67 70 78 79 80

5 21 50 59
5 21 50 59

5 21 50 59
5 23 50 59
5 22 50
5 50 51
5 26
5 50
5 50 51
5 50
5 50 51

516S0384

LPC+ Debug Connector

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

GPU / Heat Pipe Thermal Sensor

ATI_TDIODE_P
ATI_TDIODE_N
GPUTHM_A_GPU

R61111

GPUTHM_A_GPU
1

R6110

5%
1/16W
MF-LF
402 2

0
5%
1/16W
78 70
MF-LF 43 37 79
36 34 33
20 19 17 14 10 5
2 402
28 27 26 25 24 23 22

66
29
4
21
65 64 60 59 57 56 53 51 48

R6100

PP3V3_S0

GPUTHM_A_DIODE

Placement note:
Q6115

2N3904LF

Layout note:

GPUTHM_A_DIODE

SOT23

GPUTHMSNS_DX_A_P

5%
1/16W
MF-LF
402

GPUTHMSNS_DX_A_DIO_N

Minimize stubs

J6120

0.0022uF

88460-0201
F-RT-SM

HSTHMSNS_DX_P
HSTHMSNS_HAS

Placement note:

Place in between VRAM

MAX6695AUB
UMAX

GPUTHMSNS_DXP1
GPUTHMSNS_DXN
GPUTHMSNS_DXP2

2 DXP1
3 DXN
4 DXP2

SMBDATA
SMBCLK
ALERT*

2
OT1*

CRITICAL

OT2*

C6120 1

SYM_1

20%
10V
2 CERM
402

U6100

XW6111
SM
1

0.0022uF

XW6121
SM

HSTHMSNS_DX_N

9
7
8

SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCL
NC

5
10

NC
NC

5 27 45 50 53
5 27 50 53

GND

10%
50V
CERM 2
402

C6100
0.1uF

XW6120
SM
5

402

VCC

GPUTHMSNS_DX_A_N

10%
50V
CERM 2
402

5%
1/16W
MF-LF
402

CRITICAL

C6110

R6116

PP3V3_S0_GPUTHMSNS_R

GPUTHMSNS_DX_A_DIO_P

5%
1/16W
XW6110
MF-LF
SM

R6115

Place near GPU center

Placement note:
Keep all 4 XWs as close
to U6100 as possible

518S0226

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

116S0004

RES,0,1/16W,0402

C6120

CRITICAL

BOM OPTION
HSTHMSNS_NOT

Right-Side/Fin Stack Thermal Sensor

65 64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66

C6150 1

CRITICAL

88460-0201
SYM_1

Placement note:
Place near speaker hole

RSFSTHMSNS_D_P

499

RSFSTHMSNS_D_N

518S0226

499

VDD
1

C6160

0.001UF

R6161

5%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
402

10K

10%
16V 2
X5R
402

R6160

F-RT-SM

R61511

0.1UF

J6160
3

PP3V3_S0

20%
50V
2 CERM
402

RSFSTHMSNS_D_R_P
RSFSTHMSNS_D_R_N

2 D+
3 D-

ALERT*/ 6
THM2*
THM* 4

U6150
ADT7461
MSOP

CRITICAL

1%
1/16W
MF-LF
402

SCLK 8
SDATA 7

R6152
10K

5%
1/16W
MF-LF
2 402

RSTHMSNS_ALERT_L
RSTHMSNS_THM_L
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA

5 27 50 53

5 27 45 50 53

GND
5

Placement note:
Place U6150 below and to the
left of the speaker hole.

CPU Back-Up Thermal Diode

CPUTHM_DIODE

R6190

Placement note:

CPUTHMSNS_DIO_P

Place near CPU center

Q6190

THRM_CPU_DX_P

CPUTHM_DIODE

SOT23

Layout note:

2N3904LF

Minimize stubs between

these Rs and R1001 & R1002

Thermal Sensors

R6191

5%
1/16W
MF-LF
402

CPUTHMSNS_DIO_N

SYNC_MASTER=M1_MLB
THRM_CPU_DX_N

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

5%
1/16W
MF-LF
402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

R1001 / R1002 are not currently BOMOPTIONed. Can not

programatically unstuff those parts to stuff these.

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

XW6209
SM

PPVCORE_S0_CPU

R6209
CPUVSENSE_IN

4.53K2

SMC_CPU_VSENSE

1%
1/16W
MF-LF
402

Place short near U0700 center

OUT

Q6215

FDG6332C_NL

C6209
0.22UF

66 64 63 61 60 47 43 41 5 4
78 70 68

GND_SMC_AVSS
Place RC close to SMC

66 65 52 51 50 45 35 27 26 5
68 67
50 51 54 56

XW6259
SM

PBUSVSENS_PWRBTN_L

GPUVSENSE_IN

4.53K2
1

SMC_GPU_VSENSE

1%
1/16W
MF-LF
402

Place short near U8400 center

27.4K

1%
1/16W
MF-LF
402 2

SMC_PBUS_VSENSE

Q6216

2N7002DW-X-F

R62861

SOT-363

20%
2 6.3V
X5R
402

PM_SLP_S3_L

65 64 50 43 39 32 23 5

2 G

C6285

GND_SMC_AVSS

Q6215

20%
6.3V
2 X5R
402

6
N-CHN

0.22UF

OUT

0.22UF

1%
1/16W
MF-LF
402 2

This half of Q6216 acts as a

diode to keep Q6215 from
pulling SMC_ONOFF_L low.

C6259

5.49K

R5808 is pull-up
OUT

Rthevanin = 4573 ohms

PBUSVSENS_EN_L

1
S

Enables PBUS VSense divider when

SMC_ONOFF_L is low (power button
pressed or driven low by SMC)

R6259

R62851

1%
1/16W
MF-LF
402 2
D

GPU Voltage Sense / Filter

PPBUS_G3H_VSENSE

G
5

100K

Q6216
D

VOLTAGE=12.6V

2N7002DW-X-F

4 S

R62151

SOT-363

SMC_ONOFF_L

51 50 45 5

P-CHN

PPBUS_G3H

This half of Q6216 acts

as a level-shifter
between PBUS and 3.42V

PP3V42_G3H

PPVCORE_S0_GPU

SC70-6
1

20%
2 6.3V
X5R
402

76 71 70 66 54 5

PBUS Voltage Sense Enable & Filter

CPU Voltage Sense / Filter

66 60 54 9 8 5

50 51 54 56

Place RC close to SMC

FDG6332C_NL
SC70-6

GND_SMC_AVSS
Place RC close to SMC

Enables PBUS VSense divider when high.

50 51 54 56

C
FireWire Current Sense Filter

DCIN Current Sense Filter

R6230
43

R6280

4.53K2

FWPWR_IOUT

SMC_FWIRE_ISENSE

1%
1/16W
MF-LF
402

OUT

LIO_DCIN_ISENSE

R6290

4.53K2

SMC_DCIN_ISENSE

1%
1/16W
MF-LF
402

C6230
0.22UF

SMC_CPU_ISENSE

1%
1/16W
MF-LF
402

OUT

1%
1/16W
MF-LF
402

C6270
0.22UF

50 51 54 56

OUT

P1V8S3_IOUT

50 51 54 56

1.05V S0 (NB) Current Sense Filter

OUT

50 51

P1V05S0_IOUT

4.53K2
1%
1/16W
MF-LF
402

C6235
0.22UF

SMC_P1V05S0_ISENSE

50 51

0.22UF

20%
6.3V
2 X5R
402

GND_SMC_AVSS
Place RC close to SMC

50 51 54 56

OUT

C6240

20%
6.3V
2 X5R
402
50 51 54 56

0.22UF

GND_SMC_AVSS
Place RC close to SMC

50 51 54 56

SMC_P1V8S3_ISENSE

1%
1/16W
MF-LF
402

0.22UF

OUT

C6290

R6240

4.53K2

C6275

SMC_BATT_ISENSE
1

20%
6.3V
2 X5R
402

GND_SMC_AVSS
Place RC close to SMC

SMC_GPU_ISENSE

4.53K2

20%
6.3V
2 X5R
402

R6235

4.53K2

GPUVCORE_IOUT

LIO_BATT_ISENSE

1%
1/16W
MF-LF
402

1.8V S3 (Memory) Current Sense Filter

R6275

4.53K2

C6280

GND_SMC_AVSS
Place RC close to SMC

50 51 54 56

GPU Current Sense Filter

R6270
CPUVCORE_IOUT

20%
6.3V
2 X5R
402

GND_SMC_AVSS
Place RC close to SMC

OUT

0.22UF

20%
6.3V
2 X5R
402

CPU Current Sense Filter

Battery Current Sense Filter

50 51 54 56

Current Sense Calibration Circuit

Switches in fixed load on power supplies to calibrate current sense circuits

Q6229

FDG6332C_NL
SC70-6
66 60 54 9 8 5
80 79 78
52 47 42 36 31 25 5 4
70 67 66 65 61 60 57 56

PPVCORE_S0_CPU

76 71 70 66 54 5

PPVCORE_S0_GPU

ISENSE_CAL_EN_LS5V

R62291

G
5

R6220

470K

5%
1/16W
MF-LF
402 2

R6228
470K

5%
1/16W
MF-LF
2 402

ISENSE_CAL_EN_L

ISENSE_CAL_EN

N-CHN

2 G

Q6229

MICROFET3X3

FDG6332C_NL
SC70-6

FDM6296

MICROFET3X3

CRITICAL

Q6222
4

FDM6296

MICROFET3X3

1.05A / 1.1W

CRITICAL

S
1 2

P1V05S0_ISENSE_CAL
MIN_LINE_WIDTH=0.50 mm
MIN_NECK_WIDTH=0.20 mm

1.0A / 1.8W

CRITICAL

S
1 2

P1V8S3_ISENSE_CAL

Q6221
4

R62271

FDM6296

1%
1/4W
MF-LF
1206 2

MIN_LINE_WIDTH=0.50 mm
MIN_NECK_WIDTH=0.20 mm

1.2A / 1.44W

Q6220

50 5

GPUVCORE_ISENSE_CAL

CRITICAL

1.00

1%
1/4W
MF-LF
1206 2

MIN_LINE_WIDTH=0.50 mm
MIN_NECK_WIDTH=0.20 mm

R62231

1.82

1%
1/4W
MF-LF
1206 2

CPUVCORE_ISENSE_CAL

PP1V05_S0

R6222

1.00

MIN_LINE_WIDTH=0.50 mm
MIN_NECK_WIDTH=0.20 mm

21 19 17 16 13 12 11 9 8 7 5
66 64 34 25 24

R6221

1%
1/4W
MF-LF
1206 2

PP1V8_S3

1.00

37 32 31 29 28 19 16 14 5 4
66 63

P-CHN

PP5V_S0

Current & Voltage Sensing

Q6223
4

SYNC_MASTER=M1_MLB

FDM6296

NOTICE OF PROPRIETARY PROPERTY

2 3

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

100K
5%
1/16W
MF-LF
402 2

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

SYNC_DATE=01/05/2006

MICROFET3X3

06
86

65 64 62 26 25 24 23 22 11 5
78 66

PP3V3_S5

D
1

1
1
R6302
R6301
3.3K
3.3K

20%

2 10V
CERM

5%
1/16W
MF-LF
4022

402

5%
1/16W
MF-LF
4022

C6312
0.1UF

CRITICAL
8 OMIT

U6301

SPI_CE_L

5%
1/16W
MF-LF
402

C6309
22pF
5%

2 50V
CERM

402

NOSTUFF

16MBIT

SPI_SCLK_R

SOI

1 CE*

SPI_WP_L3
7
SPI_HOLD_L

C6308
22pF R6309
10K

5%
2 50V
CERM
402

6 SCK

SI 5

SST25VF016B

50 22

SPI_SCLK

5%
1/16W
MF-LF
402

SO 2

WP*
HOLD*

R6306
47
1

5%
1/16W
R6303
402
47 MF-LF

1
SPI_SO_R

5%
1/16W
MF-LF
402

VSS

C6301
22pF
5%

2 50V
CERM

5%
1/16W
MF-LF
402

SPI_SI_R

402

SPI_SI

22 50

SPI_SO

22 50

C6311
22pF
5%

2 50V
CERM

402

50 22

R6307
47

R6308
10K
1

VDD

C
R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH
R6307
AND
R6306
SHOULD
BE
PLACED
LESS
THAN
100
MILS
FORM ICH7M
ICH7M AND TEKOA(LAN CHIP)
R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM

SPI BOOTROM
SYNC_MASTER=M1_MLB
SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Right ALS Circuit

62 59 58 51 45 41 37 32 27 5
80 66 64 63

PP3V3_S3

C6405 1
0.1UF

20%
10V
CERM 2
402

Left ALS Filter

CRITICAL

U6405

RTALS_OP_IN and RTALS_OP_COMP need to be matched

4
V+

R6401

Left ALS circuit has 1K series-R

RTALS_PHOTODIODE

R6430
47 5

LTALS_OUT

3.48K2

ALS_LEFT

1%
1/16W
MF-LF
402

OUT

PD6400

20%
2 6.3V
X5R
402

GND_SMC_AVSS

R64001

BS520EOF

0.22UF

5.1M

SOT23-6-LF
1

R6410
ALS_RT_OUT

4.53K2

ALS_RIGHT

1%
1/16W
MF-LF
402

V-

OUT

C6410
0.22UF

20%
2 6.3V
X5R
402

C6400

GND_SMC_AVSS

0.01UF

5%
1/16W
MF-LF
402 2

MAX4236EUTT
5

RTALS_OP_IN

1%
1/16W
MF-LF
402

CRITICAL

C6430

20%
2 16V
CERM
402

C6406 1
0.22UF

20%
6.3V 2
X5R
402

50 51 54 56

R6406
120K

5%
1/16W
MF-LF
2 402

RTALS_OP_COMP

R64081

R6407

15.0K

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

RTALS_GAIN_L
3

Q6408

2N7002

RTALS_GAIN

SOT23-LF

Keyboard LED Driver

B
CRITICAL

L6450
57 54 52 47 42 36 31 25 5 4
80 79 78 70 67 66 65 61 60

66 65 64 60 59 57 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70

22uH

PP5V_S0

1
2
3.8x3.8x1.5MM

1
R64511 C6450
1uF

10K

SMC_SYS_KBDLED
KBDLED_HAS

VDD

10%
6.3V
CERM 2
402

5%
1/16W
MF-LF
402 2

KBDLED_SW

PP3V3_S0
KBDLED_NOT
CRITICAL

U6450
MM3120
NC

3 CNTRLLLP VOUT 8

KBDLED_ANODE

6 NC

KBDLED_RETURN

R64521

FB 4
THRML_PAD 9

10K

PGND

5%
1/16W
MF-LF
402 2

AGND

NC
1

OUT

1
C6455 R6455
25.5

0.22uF

20%
2 25V
X5R
603

1%
1/8W
MF-LF
2 805

ALS Support
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Left Fan

C
80
56 54 52 47 42 36 31 25 5 4
79 78 70 67 66 65 61 60 57
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
64 60 59 57 56 53 51 48 43
79 78 70 66 65

Right Fan
80
79 78 70 67 66 65 61 60 57
56 54 52 47 42 36 31 25 5 4
64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

PP5V_S0
PP3V3_S0

CRITICAL
47K
5%
1/16W
MF-LF
402 2

R6555
50

SMC_FAN_0_TACH

47K

5%
1/16W
MF-LF
402

100K
5%
1/16W
MF-LF
402 2
50

SMC_FAN_0_CTL

Q6560
2N7002DW-X-F

G
4 S

SOT-363
3
5

J6560

R65601
47K

5%
1/16W
MF-LF
402 2

R6565

1
2
3
4

FAN_LT_TACH

R65511

CRITICAL

J6550
SM-2MT-LF

R65501

SMC_FAN_1_TACH

47K

1
2
3
4

FAN_RT_TACH

5%
1/16W
MF-LF
402

R65611

100K
5%
1/16W
MF-LF
402 2

518S0293

FAN_LT_PWM

SMC_FAN_1_CTL

2
G
1 S

Q6560
2N7002DW-X-F
SOT-363
D 6
5

SM-2MT-LF
5

518S0293

FAN_RT_PWM

Fan Connectors
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

62 59 56 51 45 41 37 32 27 5
80 66 64 63

PP3V3_S3

R66201

5%
1/16W
MF-LF
402 2

C6620

0.1uF

20%
2 10V
CERM
402

10K

VDD

U6620
KXM52-2050
QFN

SMS_ACC_SELFTEST

OUTPUTX 2

SMS_X_AXIS

9 PS

OUTPUTY 13

SMS_Y_AXIS

5 PARITY

OUTPUTZ 14

SMS_Z_AXIS

10 SELF
TEST

SMS_ONOFF_L
NC

4
6
7
11

R6621
10K

5%
1/16W
MF-LF
1 402

CRITICAL

RSVD
RSVD

DNC 1

GND

THRML
PAD

3 12 15

Desired orientation when

placed on board top-side:
Package Top

RSVD
RSVD

C6604

0.033UF

20%
2 10V
X7R
402

C6606

0.033UF

20%
2 10V
X7R
402

Top-through View
+Y

+Z (up)

Desired orientation when

placed on board bottom-side:

+Y
+X

C6605

0.033UF

20%
2 10V
X7R
402

+X
+Z (dn)

M1 placement: Bottom-side

Sudden Motion Sensor (SMS)

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

PP3V3_S0

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

NOSTUFF

1 C6701
1 C6702
C6700
0.1UF 0.1UF 0.1UF

10%
2 16V
X5R
402

5%
1/8W
MF-LF
2805

OMIT

R6700

0
LAYOUT NOTE:
5%
1/16W
PLACE WHERE ACCESSIBLE
MF-LF
2402

52 50 21 5

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>

52 50 21 5

52 51 50 23 5

52 50 23 5

26
23
20
17

PCI_CLK_TPM
LPC_FRAME_L

21
22
16
PM_SUS_STAT_L 28
INT_SERIRQ
27
PM_CLKRUN_L
15

TPM_PP
51

TPM_GPIO1

TPM_GPIO2

7
6
NC 1
2

TPM_XTALI
TPM_XTALO

13
14

LAD1
LAD2
LAD3

U6700
TPM

TSSOP

3V0

VDD
3V1
VDD
3V2
VDD
3VSB

VNC

VSB

LCLK

LFRAME*

VBAT

LRESET*
LPCPD*

10
19
24

26 5

TPM_LRESET_L

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.15MM

R6702
10K

CLKRUN*
PP/GPIO (INT PD)
PP
GPIO_EXPRESS_00
GPIO
GPIO/SM_DAT
NC
TESTBI/BADD/GPIO
GPIO/SM_CLK
TESTBI/BADD
GPIO2
TESTI

5%
1/16W
MF-LF
2402

C6703
0.1UF

10%
2 16V
X5R
402

12 NC

SERRIRQ
CLKRUN/GPIO*

PP3V3_S3

5%
1/8W
MF-LF
805

5 27 32 37 41 45 51 56 58 62 63
64 66 80

BASE ADDR = 0X4E/4F

LAYOUT NOTE:
PLACE R6702-03 WHERE ACCESSIBLE

9 TPM_BADD
8
NOSTUFF

XTALI/32K_IN
XTALO

R6704
0

PP3V3_TPM_3VSB

GND

R6703

10K
5%

1/16W
MF-LF
2402

4
11
18
25

LAD0

GND2
GND3

NOSTUFF

52 50 21 5

GND0
GND1

PP3V3_S0

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

52 50 21 5

NOTE:
SINCE CURRENT OF VSB IS NOT YET ON SPEC,
1/8W (R6704/R6705) IS USED FOR NOW

R6705
0

10%
2 16V
X5R
402

BASE ADDR = 0X2E/2F

R6798
0
1

5%
1/16W
MF-LF
402

TPM_RST_L
NOSTUFF

B
51 50

SMC_TPM_RESET_L

R6799
0
1

5%
1/16W
MF-LF
402

TPM
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

PPBUS_G3H

64 63 61 60 54 47 43 41 5 4
78 70 68 66
56 54 52 47 42 36 31 25 5 4
80 79 78 70 67 66 65 61 57

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
1

R7544

PM_DPRSLPVR

499

0.1uF

10%
16V 2
X5R
402

C7528 1

9 5
9 5
9 5

(IMVP6_NTC)

9 5
9 5

9 5

CRITICAL
470K

10%
16V
CERM 2
402

0.01uF

402
2

21 7 5

IN
86 5

65 64 5

33 26

R7547

1%
1/16W
MF-LF
402 2

R7532

C7532 1

OUT

50 5

4.02K

26 14 5

IN
OUT

147K

0.015uF

1%
1/16W
MF-LF
2 402

10%
16V 2
X7R
402

CPU_DPRSTP_L
IMVP_DPRSLPVR
CPU_PSI_L
P1V5P1V05S0_PGOOD

46
45
2
3

VR_PWRGD_CK410_L
IMVP_VR_ON
VR_PWRGOOD_DELAY
IMVP6_VR_TT
IMVP6_NTC
(GND_IMVP6_SGND)
IMVP6_SOFT

48
47
44
1
5
6

VID6

R7536
2.0K

10%
50V
CERM 2
402

1%
1/16W
MF-LF
2 402

IMVP6_VDIFF_RC

VDD

OMIT

VID5

U7530

VID4

36
BOOT1
BOOT2 26

1-Phase

CCM

1-Phase

DCM

1-Phase

QFN

VID3
VID2

C7550 1

IMVP6_BOOT1
IMVP6_BOOT2

ISL6262

35
UGATE1

IMVP6_UGATE1

PHASE1 34

IMVP6_PHASE1

LGATE1 32

IMVP6_LGATE1

VID0

DPRSLPVR

0.22uF

20%
25V
2 X5R
603

PGND1 33

(GND)

ISEN1 24

PGD_IN

IMVP6_ISEN1

UGATE2
PHASE2

IMVP6_UGATE2

HAT2165H

CLK_EN*

LGATE2

VR_ON

0.22UF
1

1%
1/16W
MF-LF
402

Q7502
LFPAK

20%
6.3V
X5R
402

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

NO STUFF

C7501

0.0022UF

D7500
SMB

1 2 3

C7502

10%
2 50V
CERM
402

R7506
3.65K

1%
1/10W
MF-LF
2 603

B340LBXF

0.0022UF

10%
2 50V
CERM
402

(IMVP6_ISEN1)

IMVP6_PHASE2

IMVP6_LGATE2

PGND2 29

VR_TT*
ISEN2

C
CRITICAL

(GND)

PGOOD

IMVP6_ISEN2

19
8
18
16

IMVP6_VSUM
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP

Q7550
HAT2168H
LFPAK

NTC

CRITICAL
VSUM

7 SOFT
4 RBIAS
13 VDIFF

IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW

12
11
10
9

VO
DROOP

0.001uF

1%
1/16W
MF-LF
402

C7580 1

R7542

TPAD

HAT2165H

1%
1/16W
MF-LF
2 402

5%
50V
CERM 2
402

LFPAK

9.31K

180pF

1%
1/16W
MF-LF
2 402

Q7551

R7541 C7540 1
1K

10%
25V
CERM 2
402

5%
1/16W
MF-LF
402 2

CRITICAL
4

0.0068uF

R75571

10%
50V
CERM 2
402

3.01K2

RTN 15

HAT2165H
CRITICAL

10%
16V
2 CERM
402

330pF

10%
50V
CERM 2
402

R7543
11K

1%
1/16W
MF-LF
2 402

0.22UF
1

20%
6.3V
X5R
402

GND_IMVP6_SGND

C7543

10K

1%
1/16W
MF-LF
402

Q7552

1 2 3

(IMVP6_VO)
1

C7555

R7555
CRITICAL
LFPAK

2
SM-PCC

C7542 1

R7540

IMVP6_DFB

VSEN 14

COMP

0.36uH

(IMVP6_PHASE2)

NO STUFF

L7555

1 2 3

FB2

C7535

10K

HAT2165H

NO STUFF

3V3

VSS

10%
50V
2 CERM
402

C7505

R7505

CRITICAL

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

0.01uF

390pF

Q7501

DCM

0.22uF

20%
25V 2
X5R
603

(IMVP6_FB)

C7534

5%
1/16W
MF-LF
402 2

CRITICAL

C7500

PSI*

1.40K

R75071

5 8 9 54 66

Vout = Variable
36A max output
(Inductors limit)

DPRSTP*

IMVP6_RBIAS
(GND_IMVP6_SGND)
IMVP6_VDIFF

1%
1/16W
MF-LF
2 402

VID1

R7533

1%
1/16W
MF-LF
402 2

PVCC

1.82K

1 2 3

25 NC

R75351

DFB 17

470pF

CCM

CRITICAL

NO STUFF
1

2-Phase

LFPAK

OCSET
5

C7533

43
42
41
40
39
38
37

IMVP6_NTC_R

10%
16V 2
X5R
603

VIN

9 5

C7546 1

PPVCORE_S0_CPU
2

SM-PCC

1uF

1%
1/16W
MF-LF
402

R7546

0.36uH

(IMVP6_PHASE2)

IMVP6_VID<6>
IMVP6_VID<5>
IMVP6_VID<4>
IMVP6_VID<3>
IMVP6_VID<2>
IMVP6_VID<1>
IMVP6_VID<0>

10%
16V 2
X5R
603

L7505

DPRSLPVR DPRSTP* PSI* Operation Mode

1uF

CRITICAL

C7531

R7545
86 23 14 5

C7563 1

10%
16V 2
X5R
603

20%
16V 2
POLY
CASED2E-SM

HAT2168H

1 2 3

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12V
1

1%
1/16W
MF-LF
2 402

1uF

33uF

10%
16V 2
X5R
603

LFPAK

PPVIN_S0_IMVP6_R

499

C7562

C7560 1

1uF

10%
16V 2
X5R
603

Q7500

1uF

PP3V3_S0_IMVP6_R

1uF

20%
16V 2
CRITICAL
POLY
CASED2E-SM

10%
6.3V 2
CERM
402

5%
1/16W
MF-LF
402

C7530 1

C7512 1 C7513 1

33uF

20%
2 6.3V
CERM
603

CRITICAL

C7510 1

C7529
4.7uF

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

R7531

PPBUS_G3H

R7528

PP3V3_S0

PP5V_S0_IMVP6_VDD

5%
1/16W
MF-LF
402

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

These caps for Q7550

CRITICAL
5

These caps for Q7500

PP5V_S0

R7530

64 63 61 60 54 47 43 41 5 4
78 70 68 66

NO STUFF

R7548

3.92K

1%
1/16W
MF-LF
402 2

NO STUFF

C7551

0.0022UF

C7552

10%
2 50V
CERM
402

R7556
3.65K

1%
1/10W
MF-LF
2 603

B340LBXF

0.0022UF

10%
2 50V
CERM
402

D7550
SMB

1 2 3

IMVP6_VO_R

IMVP6_COMP_RC

(IMVP6_VW)

CRITICAL

R75341

C7537 1

182K

47pF

1%
1/16W
MF-LF
402 2

5%
50V
CERM 2
402

R7537

R7549

C7544 1

4.42K

1%
1/16W
MF-LF
2 402

10KOHM-5%

0.22uF

20%
6.3V 2
X5R
402

0603-LF
2

(IMVP6_ISEN2)

(IMVP6_COMP)

R7581

(IMVP6_VSUM)

(IMVP6_VO)
86
86

NO STUFF

XW7530
SM
2

C7541 1

C7582 1

0.22UF

0.01uF

20%
6.3V
X5R 2
402

0.01uF 78

10%
16V
CERM 2
402

C7598

10% 48 43 37 36
16V 26 25 24 23
2 CERM 17 14 10 5 4 PP3V3_S0
22 21 20 19
402 34 33 29 28 27

470pF
1

66 65 64 60 59 57 56 53 51
79

C7595

1uF

OUT

CPUVCORE_IOUT

CPUISENS_POS

C7592
1

8 86

30.1K2

SYNC_DATE=02/08/2006

NOTICE OF PROPRIETARY PROPERTY

IMVP6_DROOP

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1%
1/16W
MF-LF
402

SIZE

APPLE COMPUTER INC.

10%
50V
CERM
402

CPU_VCCSENSE_N

SYNC_MASTER=M1_MLB

1%
1/16W
MF-LF
402

<Rc>
1

R7591
2

470pF

0.1uF

IMVP6 CPU VCore Regulator

R7592

Vout @ 36A = 2.44V-2.60V

C7594

8 86

R7582

5%
1/16W
MF-LF
402

= Rc / (Ra + Rb)

Voffset worst-case ~2.3mV (+/- ~1A offset)

CPU_VCCSENSE_P

20%
10V
2 CERM
402

Voffset = (Vdrp_offset * Kdroop) + Vamp_offset

CPUISENS_NEG_RC
NO STUFF

SOT23-5
1

= Gain * ((2.1 mV/A * Iload) + Voffset)

Gain

1%
1/16W
MF-LF
402

U7595 5

<Rb>

R7594

R7598

LMV2011MF

<Ra>

<Rc>

5%
1/16W
MF-LF
402

R7593
30.1K2
1

CPUISENS_NEG

10%
50V
CERM
402

10%
6.3V
CERM 2
402

Vout

IMVP6_VSEN_P
IMVP6_VSEN_N

CPU VCore Current Sense

C7581

5%
1/16W
MF-LF
402

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

7
66 64 63 60 54 47 43 41 5 4
78 70 68

PPBUS_G3H
CRITICAL
1

CRITICAL
1

C7640

C7641

R7600

1uF

33uF

20%
2 16V
POLY
CASED2E-SM

C7680 1

C7681 1

20%
16V 2
POLY
CASED2E-SM

10%
16V 2
X5R
603

1uF

33uF

10%
2 16V
X5R
603

5%
1/16W
MF-LF
2 402

D
R76231

C7623

2.26K

0.1uF

1%
1/16W
MF-LF
402 2

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

C7620

PP5V_S5_P5VP1V5_INTVCC

R7620
3.65K

10%
16V
X5R 2
402

MICROFET3X3

1
3 2

C7624
0.1uF

L7620

20%
10V
2 CERM
402

1.8uH-10.4A
1

2
SM

20%
6.3V
CERM 2
805

SW1

P5VS5_BG

BG1

CRITICAL

Q7621

C7651

CRITICAL

22UF

B240-X-F
SMB

FDM6296

MICROFET3X3

D7621

20%
2 6.3V
CERM
805

C7622
G

0.001uF

NO STUFF

1
2

10%
50V
CERM 2
402

C7621
1000pF

10%
2 25V
X7R
402

65 5

QFN

30 SENSE1+

P1V5S0_BG
P5VP1V5_FSEL

SENSE2+
11
SENSE2-

SENSE1-

P5VS5_VOSNS

1 VOSENSE1

P5VS5_ITH

P5VS5_RUNSS

P1V5S0_SW

BG2 18

VOSENSE2

ITH1

28 RUN_SS1

52.3K

C7627

470pF

1%
1/16W
MF-LF
402 2

47pF

10%
2 50V
CERM
402

470pF

21 EXTVCC

10%
50V
CERM 2
402

5%
2 50V
CERM
402

22K

1000pF

1%
1/16W
MF-LF
402 2

C7630
0.1uF

5%
1/16W
MF-LF
2 402

10%
2 25V
X7R
402

SGND

10K

R7625

C7628

20%
2 10V
CERM
402

NC2 16

NO STUFF

NC3 29
NC4 32

PP1V5_S0_REG

CRITICAL

L7660

2.2uH-14A
1
2
IHLP2525CZ-SM

CRITICAL
1

7 8

P1V5S0_VOSNS

10%
2 50V
CERM
402

C7662

IRF7832PBF

1000pF

C7665 C7666 1
470pF

<Ra>
R7667

C7667 1

100pF

10%
2 50V
CERM
402

NC
NC
NC
NC

20%
6.3V 2
CERM
805

10%
25V
X7R 2
402

330uF

22UF

1
1 2

C7692

20%
2V
2 POLY
CASE-D2-SM

C7691

SO-8

NO STUFF

C7661

20%
6.3V
2 CERM
805

Q7661

0.001uF

C7690
22UF

CRITICAL

P1V5S0_SNS_R_P
P1V5S0_SNS_R_N

Vout = 1.49V
8A max output
(L7660 & Q7660 limit)

INTVCC 20

P5VS5_ITH_RC

<Rb>
R76281

MICROFET3X3

20%
10V
CERM 2
402

NC1 10

1%
1/16W
MF-LF
402 2

PGOOD 27

C7626 C7625 1

1.21K

FDM6296

0.1uF

P1V5S0_RUNSS

RUN_SS2 13

4 FCB
1

C7664

P1V5S0_ITH

ITH2 8

3_3VOUT 7

<Ra>
R76271

P1V5S0_BOOST

SW2

R76691
CRITICAL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P1V5S0_TG

PLLFLTR 2

PLLIN

P5VS5_SNS_P
P5VS5_SNS_N

LTC3728LXC

PGND

20%
6.3V 2
POLY
SMC-LF

150uF

P5VS5_SW

U7600

BOOST2

0.1uF

Q7660

5%
1/16W
MF-LF
2 402

TG2 14

CRITICAL

BOOST1

22UF

TG1

THRML_PAD

C7650 1

P5VS5_BOOST

C7660

10%
16V
2 X5R
402

VIN

P5VS5_TG

1%
1/16W
MF-LF
402 2

R7664

5%
1/16W
MF-LF
402 2

3.65K

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
1

5%
1/16W
MF-LF
2 402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

R76601

P1V5S0_BOOST_RC

34.0K

470pF

1%
1/16W
MF-LF
2 402

10%
50V
CERM 2
402

5%
50V
CERM 2
402

P1V5S0_ITH_RC

C7670 1

R76651

20%
10V
CERM 2
402

5%
1/16W
MF-LF
402 2

<Rb>
R7668

NO STUFF

C7668 1

10K

0.1uF

C7652 1

5%
1/16W
MF-LF
402 2

D7664
SOD-323

R76701

R7630

Q7620
FDM6296

CRITICAL

R76241

CRITICAL

1%
1/16W
MF-LF
2 402

CMDSH-3

10%
2 16V
X5R
603

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

CRITICAL

1%
1/16W
MF-LF
2 402

Vout = 4.98V
8A max output
(L7620 limit)

909

CRITICAL

1uF

P5VS5_BOOST_RC

R7629

C7600

6.04K

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12V
1

CMDSH-3

1%
1/16W
MF-LF
2 402

PP5V_S5_P5VP1V5_INTVCC

PPVIN_S5_P5VP1V5_R

D7624
SOD-323

1
1

0.1uF

PP5V_S5_REG

R7663

0.1uF

10%
16V
X5R 2
402

CRITICAL

C7663 1

10%
16V
2 X5R
402

39.2K

1000pF

1%
1/16W
MF-LF
2 402

10%
25V 2
X7R
402

GND_P5VP1V5_SGND
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

XW7600
SM

C7607
0.01uF

Connect to RUNSS pins to control outputs.

If unconnected, powers up with VIN.
NOTE: Be aware of pull-ups to VIN on these signals.

10%
2 16V
CERM
402

Vout = 0.8V * (1 + Ra / Rb)

TP_P5V_P1V5_PGOOD

PP5V_S5_P5VP1V5_INTVCC

VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P5VP1V5_SKIP

R7606

C7601 1

5%
1/16W
MF-LF
2 402

4.7uF

20%
6.3V 2
CERM
603

P5VP1V5_FCB

5V S0 FET

R7603
30K

5%
1/16W
MF-LF
2 402

Q7695
FDC638P
P5VP1V5_FSEL

67 66 65 64 63 61 51 46 25 5
70

PP5V_S5

SM-LF

C7605 1
1uF

10%
6.3V 2
CERM
402

R7607

5%
1/16W
MF-LF
2 402

R7604

C7602

10K

10%
6.3V
2 CERM
402

67 66 65 64 63 61 51 46 25 5
70

C7604

5
4

C7696 1

10%
2 16V
CERM
402

22UF

20%
6.3V
CERM 2
805
3

65 61 47 5

100K 2
1
PM_SLP_S3_LS5V
5%
1/16W
MF-LF
402

C7695

0.0022uF

R7695

5V S3 FET

80
4 5 25 31 36 42 47 52 54 56
57 60 61 65 66 67 70 78 79

PP5V_S5

0.01uF

5%
1/16W
MF-LF
2 402

1uF

PP5V_S0

P5VP1V5_CONT

P5VS0_EN2_L_RC

C7697
22UF

20%
6.3V
2 CERM
805

10%
50V
CERM
402

5V S0 FET
NO STUFF

Q7610

Q7615

FDC638P
67 66 65 64 63 61 51 46 25 5
70

FDC638P

SM-LF

PP5V_S5

PP5V_S3

SM-LF

67 66 65 64 63 61 51 46 25 5
70

NO STUFF

C7616 1

65 64

100K 2
1
PM_SLP_S4_LS5V

C7610

NO STUFF

0.0022uF

R7610

P5VS3_EN_L_RC

5%
1/16W
MF-LF
402

R7615

2
65 61 47 5

10%
50V
CERM
402

100K 2
1
PM_SLP_S3_LS5V

NO STUFF

C7615

0.0022uF
1

P5VS0_EN_L_RC

5%
1/16W
MF-LF
402

SYNC_MASTER=M1_MLB

20%
6.3V
CERM 2
805

NO STUFF
1

C7617
22UF

20%
2 6.3V
CERM
805

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

C7618
150uF

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

20%
2 6.3V
POLY
CASE-D2-LF

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

NO STUFF
CRITICAL

22UF

10%
50V
CERM
402

5V / 1.5V Power Supply

4 5 25 31 36 42 47 52 54 56 57
60 61 65 66 67 70 78 79 80

PP5V_S5

PP5V_S0

5 45 51 66 80

06
86

2.5V S3 Regulator
D

65 64 55 26 25 24 23 22 11 5
78 66

PP3V3_S5

R7700
1

R77011

C7701

2.5V S0 FET

SVIN PVIN

10%
2 6.3V
CERM
402
5

CRITICAL

U7700

L7700

LTC3411

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm 2.2uH-1.32A
4
1
2
P2V5S3_SW
CDRH4D18-SM
9
P2V5S3_VFB

MSOP-LF

P2V5S3_SHDNRT
P2V5S3_MODE

P2V5S3_P1V2S3_PGOOD

65 62

10UF

20%
2 6.3V
X5R
603

1uF

5%
1/16W
MF-LF
402 2

C7700

PPVIN_S3_P2V5S3_SVIN

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

5%
1/16W
MF-LF
402

SHDN/RT

SYNC/MODE VFB

PGOOD
PGND
5

ITH 10 P2V5S3_ITH
SGND
3
R77061
CRITICAL
4.99K

R7707
10K

22pF

1%
1/16W
MF-LF
2 402

5%
50V
CERM 2
402

R7705

324K

1%
1/16W
MF-LF
2 402

C7704

0.0033uF

5%
50V
CERM 2
402

10%
50V
2 CERM
402

GND_P2V5S3_SGND

PP2V5_S0

5 17 19 65 66 76 77

TSOP-LF

C7720

0.0022uF

70 65 62

4.7K

3
4

100K 2
1
PM_SLP_S3_LS5V_L

C7709

P2V5S0_EN_RC

5%
1/16W
MF-LF
402

22UF

1%
1/16W
MF-LF
2 402

100pF

SI3446DV

R7720

R7708

C7703 1

PP2V5_S3
1

<Rb>

5%
1/16W
MF-LF
402 2

66 39 5

10%
50V
CERM 2
402

P2V5S3_ITH_RC

R77041

20%
2 6.3V
CERM
805

XW7700
SM
1

VOLTAGE=0V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

P2V5S3_EN_L

<Ra>

C7706 1

Q7720

Vout = 2.52V
1.25A max output
(Switcher limit)

1%
1/16W
MF-LF
402 2

Continuous
Mode

PP2V5_S3_REG

Vout = 0.8V * (1 + Ra / Rb)

1.2V S3 Regulator
PP3V3_S3

5%
1/16W
MF-LF
402 2

P1V2S3_RUNSS
Connect RUNSS off-page to control
If unconnected, powers up with PVIN.
NOTE: Be aware of pull-up on this signal.

P1V2S3_ITH_RC
1

C7753

0.0022uF

10%
2 50V
CERM
402

C7754 1
22pF

5%
50V
CERM 2
402

5
7

RT
RUN/SS

P1V2S3_ITH
P1V2S3_MODE

3
6

ITH
SYNC/MODE

R7756
0

PGOOD 2

C7757 1
470pF

10%
50V
CERM 2
402

VFB

10
11
14
15

CRITICAL

L7750

P1V2S3_SW
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

1%
1/16W
MF-LF
402 2

C7755 1
22UF
1 C7750
20%
6.3V 2
22pF

5%
50V
2 CERM
402

CERM
805

PP1V2_S3

SI3446DV
1

PP1V2_S0

5 65 66 69 76

TSOP-LF

C7770 1

0.0022uF

10%
50V
CERM 2
402

R7770

22UF

70 65 62

100K 2
1
PM_SLP_S3_LS5V_L

P1V2S0_EN_RC

5%
1/16W
MF-LF
402

VOLTAGE=0V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

66 62 39 5

C7756

20%
2 6.3V
CERM
805

XW7750
SM
1

5 39 62 66

Vout = 1.205V
2.5A max output
(Switcher limit)

SM-LF

47.0K

309K

PP1V2_S3

<Ra>
R77501

R7754

GND_P1V2S3_SGND

Q7770

1.0UH-3.48A

1%
1/16W
MF-LF
2 402

1.2V S0 FET

P2V5S3_P1V2S3_PGOOD

THERM
SGND PGND PAD

5%
1/16W
MF-LF
2 402

20%
2 6.3V
CERM
805

TSSOP-LF

P1V2S3_RT

Burst

1%
1/16W
MF-LF
402 2

9
16

LTC3412

C7752
22UF

20%
6.3V 2
CERM
805

U7750

22UF

R77531
8.25K

C7751 1

SVIN PVIN

5%
1/16W
MF-LF
2 402

41 5

CRITICAL

R7755

NO STUFF
1

12
13

R77571

Continuous

59 58 56 51 45 41 37 32 27 5
80 66 64 63

P1V2S3_VFB

<Rb>
R77511
61.9K

1%
1/16W
MF-LF
402 2

P1V2S3_VFB_DIV

<Rc>
R77521
30.9K

1%
1/16W
MF-LF
402 2

2.5V & 1.2V Regulators

SYNC_MASTER=M1_MLB

Vout = 0.8V * (1 + Ra / (Rb + Rc))

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

1.8V S3 Current Sense

P1V8ISENS_NTC
1
70 67 66 65 64 61 51 46 25 5
64 63 61 60 54 47 43 41 5 4
78 70 68 66

CRITICAL

10%
16V 2
X5R
603

R7802

2.2UF

20%
6.3V
CERM1 2
603

5%
1/16W
MF-LF
2 402

R7809

C
65 50 47 46 41 23 5

12
PVCC

20%
6.3V
CERM1 2
603

U7800

P1V8S3_FSET

PM_SLP_S4_L

4
3
16
5

TP_P1V8S3_PGOOD
5

C7806 1
0.01UF

10%
16V
CERM 2
402

P1V8S3_COMP

R7808

1%
1/16W
MF-LF
2 402

64.9K

1%
1/16W
MF-LF
2 402

C7807 1

P1V8S3_FB

BOOT 13
PHASE 15
ISEN 9

EN
FCCM
PGOOD
COMP

649

1%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
2 402

P1V8S3_LG

20.0K2

L7820
1.0uH-20.5

Q7822

C7822

HAT2165H

LFPAK

1000pF

C7821

10%
25V
X7R 2
402

10%
25V
2 X7R
402

1 2 3

20.0K2

1uF

U7895
LMV2011MF
SOT23-5

P1V8S3_IOUT

CRITICAL

C7892

1%
1/16W
MF-LF
402

Placement Note:

470pF
2

Keep C7890, R7890,

R7894 and R7897
close to inductor

10%
50V
CERM
402

PP1V8_S3

1.62K

1%
1/16W
MF-LF
402 2

B340LBXF
1

R7892

<Rb>
R78221

OUT

P1V8ISENS_POS

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402 2

D7820
SMB

1000pF

P1V8ISENS_NEG

C7895

10%
2 6.3V
CERM
402

1%
1/16W
MF-LF
402

R7891

1 2 3

NO STUFF

3.32K

LFPAK

<Ra>
R78211

Q7821

10%
50V
CERM
402

HAT2165H

NO STUFF

1%
1/16W
MF-LF
402

CRITICAL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

C7808 1

GND_P1V8S3_SGND

C7890

1%
1/16W
MF-LF
402

XW7800
SM

R7893

SM1

3.01K2

PGND 10

10%
50V
CERM 2
402

1%
1/16W
MF-LF
402

CRITICAL

R7810

P1V8S3_ISEN

0.0022uF

CRITICAL

R7805

R78901

1 2 3

P1V8S3_COMP_R
1

R7898

P1V8ISENS_RC

Q7820

P1V8S3_PHASE

THRML
PAD
17

R7894

HAT2168H

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

2
2

1uF

10%
2 16V
X5R
603

LFPAK

8 VO

5%
50V
CERM 2
402

1uF

CRITICAL
4

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

6 FB

15PF

C7833

20%
2 6.3V
X5R
402

UG 14

LG 11
1

57.6K

P1V8S3_BOOT

R7806

NO STUFF

10%
6.3V
CERM
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

QFN

CRITICAL

C7809

P1V8S3_UG

7 FSET

P1V8S3_FCCM
65

C7832

10%
2 16V
X5R
603

0.22uF

5%
1/16W
MF-LF
402 2

2
VCC

ISL6269
1 VIN

0
2.2UF

5%
1/16W
MF-LF
402 2

470pF

0603-LF

P1V8S3_BOOT_R
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

C7898

10KOHM-5%

PP5V_S3_P1V8S3_VCC

R78041

1%
1/16W
MF-LF
402 2

20%
2 16V
POLY
CASED2E-SM

1uF

C7802 1

C7831
33uF

20%
2 16V
POLY
CASED2E-SM

NO STUFF

C7800 1

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

NO STUFF

C7830
33uF

C7801 1
1uF

CRITICAL
1

PP3V3_S3

R7897

1K
1

59 58 56 51 45 41 37 32 27 5
80 66 64 62

CRITICAL

R78961

PP5V_S5
PPBUS_G3H

R7820

C7840 1

C7842 1

22UF

330uF

20%
6.3V 2
CERM
805

5%
1/16W
MF-LF
2 402

4 5 14 16 19 28 29 31 32
37 54 63 66

Vout = 1.83V
17A max output
(Q7820 limit)

NO STUFF
20%
2V
POLY 2
CASE-D2-SM

P1V8S3_FB_RC
NO STUFF

C7820 1
0.0022uF

10%
50V
CERM 2
402

(P1V8S3_FB)

C7841

22UF

C7843
330uF

20%
2 6.3V
CERM
805

20%
2 2V
POLY
CASE-D2-SM

Vout = 0.6V * (1 + Ra / Rb)

1.8V S0 FET
CRITICAL

Q7845

PP1V8_S0

FDM6296

5 65 66

MICROFET3X3 3
37 32 31 29 28 19 16 14 5 4
66 63 54
64 63 61 60 54 47 43 41 5 4
78 70 68 66

PP1V8_S3
PPBUS_G3H

2
5

D
1

R7846

5%
1/16W
MF-LF
402 2
65

P1V8S0_EN

C7845

0.0022uF

470K

R7845
1

10%
50V
2 CERM
402

P1V8S0_EN_RC

S
G
4

C7846
22UF

20%
6.3V 2
CERM
805

C7847
22UF

20%
2 6.3V
CERM
805

1.8V Supply
SYNC_MASTER=M1_MLB

5%
1/16W
MF-LF
402

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

FDC638P
SM-LF

67 66 65 64 63 61 51 46 25 5
70
29 33 34 36 37 43 48 51 53 56
4 5 10 14 17 64 63 61 60 54 47 43 41 5 4
19 20 21 22 23 24 25 26 27 28 78 70 68 66
57 59 60 64 65 66 70 78 79

PP3V3_S0
6

PP3V3_S5

Q7945
C7901 1
1uF

10%
16V 2
X5R
603

C7900

P3V3S0_EN_L

R7902
0

P3V3S0_EN_L_RC

C7902 1

NO STUFF

20%
6.3V
CERM1 2
603

5%
1/16W
MF-LF
2 402

R7949
65 51

U7900

5%
1/16W
MF-LF
402 2

P3V3S5_FSET

QFN

P3V3S5_EN_RC
P3V3S5_FCCM

4
3
16
5

RSMRST_PWRGD
5

P3V3S5_COMP

C7906 1

57.6K

0.01UF

R7908

1%
1/16W
MF-LF
2 402

10%
16V
CERM 2
402

C7907

51.1K

P3V3S5_FB

6 FB

CRITICAL

L7920

470pF

1%
1/16W
MF-LF
2 402

THRML
PAD
17

P3V3S5_LG

R7905
0

5%
1/16W
MF-LF
2 402

C7908 1

0.022uF

CRITICAL

Q7921

C7949

D7920
SMB

<Rb>
R79221

MBRS140XXG

10%
25V 2
X7R
402

GND_P3V3S5_SGND

22UF

20%
2 6.3V
CERM
805

20%
2 6.3V
POLY
SMC-LF

5%
1/16W
MF-LF
402

732

C7942
150uF

R7920
C7941 1
22UF

20%
6.3V 2
CERM
805

1%
1/16W
MF-LF
402 2

XW7900
SM

C7940

P3V3S5_FB_RC

CRITICAL
1 2

Vout = 3.32V
4.5A max output
(L7920 limit)

MICROFET3X3

1000pF

20%
2 16V
CERM
402

10%
2 25V
CERM
402

FDM6296

C7920
0.0047uF

1%
1/16W
MF-LF
402 2

C7921

0.01uF

10%
16V
CERM-X5R 2
402

3.32K

NO STUFF

<Ra>
R79211

5.62K2

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P3V3S5_COMP_R

PP3V3_S5_REG
2

R7910

8 VO

10%
50V
CERM 2
402

4.7uH

2 3

IHLP

1%
1/16W
MF-LF
402

10%
50V
CERM
402

MICROFET3X3

PGND 10

P3V3S3_EN_L_RC

5%
1/16W
MF-LF
402

P3V3S5_ISEN

C7945
0.0022uF

PM_SLP_S4_LS5V 1 100K 2

FDM6296
S

P3V3S5_PHASE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

LG 11

R7906

D
3

Q7920

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

BOOT 13
PHASE 15
ISEN 9

EN
FCCM
PGOOD
COMP

65 61

CRITICAL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

7 FSET

R7945

20%
6.3V
2 X5R
402

20%
2 16V
POLY
CASED2E-SM

0.22uF

P3V3S5_UG

UG 14

CRITICAL

C7909

62 63 66 80
5 27 32 37
41 45 51 56 58 59

C7931

P3V3S5_BOOT

5%
1/16W
MF-LF
402
51 50

R79091

ISL6269
1 VIN

2
VCC

12
PVCC

2.2UF

R7904

33uF

10%
2 16V
X5R
603

P3V3S5_BOOT_R

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

C7930
1uF

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

P5VS5_PGOOD

CRITICAL
1

PP5V_S5_P3V3S5_VCC

10%
25V
CERM
402

5%
1/16W
MF-LF
402

PP3V3_S3
6

PP3V3_S5

64 62 55 26 25 24 23 22 11 5
78 66 65

5%
1/16W
MF-LF
2 402

0.0047uF

R7947

SM-LF

20%
6.3V
CERM1 2
603

C7947

FDC638P

NO STUFF

2.2UF

3.3V S3 FET

5
2

3.3V S5 Regulator

PP5V_S5
PPBUS_G3H

100K 2
1

Q7947

3.3V S0 FET
64 62 55 26 25 24 23 22 11 5
78 66 65

Vout = 0.6V * (1 + Ra / Rb)

1.05V Current Sense

P1V05ISENS_NTC
1
67 66 65 64 63 61 51 46 25 5
70
64 63 61 60 54 47 43 41 5 4
78 70 68 66

1.05V S0 Regulator

PP5V_S5
PPBUS_G3H

R79961
1

C7951

10%
16V 2
X5R
603

NO STUFF

C7950 1

R7952

2.2UF

20%
6.3V
CERM1 2
603

5%
1/16W
MF-LF
2 402

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

C7952 1

NO STUFF

2.2UF

R7954

20%
6.3V
CERM1 2
603

5%
1/16W
MF-LF
2 402

2
VCC

R79591

U7950

5%
1/16W
MF-LF
402 2

12
PVCC

ISL6269
QFN

1 VIN
5

P1V05S0_FSET

7 FSET

CRITICAL

UG 14

FDM6296
MICROFET3X3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

649

1%
1/16W
MF-LF
402 2

65 60 5

PM_SLP_S3_L
P1V05S0_FCCM
P1V5P1V05S0_PGOOD
5

C7956 1
0.01UF

10%
16V
CERM 2
402

P1V05S0_COMP

4
3
16
5

BOOT 13
PHASE 15
ISEN 9

EN
FCCM
PGOOD
COMP

LG 11

R7956

57.6K

R7958

1%
1/16W
MF-LF
2 402

30.9K

1%
1/16W
MF-LF
2 402

C7957 1
15PF

5%
50V
CERM 2
402

P1V05S0_FB

6 FB

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

P1V05S0_ISEN

2.8K 2

5%
1/16W
MF-LF
2 402

6 7

1%
1/16W
MF-LF
402

8 VO

P1V05S0_LG

Q7971
IRF7832PBF
SO-8

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
1

1000pF

20%
16V
CERM 2
402

C7995
1uF

10%
6.3V
2 CERM
402

1%
1/16W
MF-LF
402

P1V05ISENS_NEG

U7995
LMV2011MF
SOT23-5
1

P1V05S0_IOUT

OUT

R7991

CRITICAL
NC

L7970 3
1.53uH

20.0K2

P1V05ISENS_POS

1%
1/16W
MF-LF
402

R7992
1M

Placement Note:

C7992

1%
1/16W
MF-LF
402

470pF
2

Keep C7990, R7990,

R7994 and R7997
close to inductor

10%
50V
CERM
402

PP1V05_S0

<Ra>
R79711
3.32K

NO STUFF
1

R7970

1%
1/16W
MF-LF
402 2

C7985
22UF

5%
1/16W
MF-LF
2 402

20%
2 6.3V
CERM
805

P1V05S0_FB_RC
NO STUFF

C7970 1

C7986 1

(P1V05S0_FB)

20%
6.3V 2
CERM
805

10%
50V
CERM 2
402

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 66

Vout = 1.05V
10A max output
(Q7970 & L7970 limit)
1
C7989
330uF

20%
2 2V
POLY
CASE-D2-SM

0.0022uF

4.42K

XW7950
SM
GND_P1V05S0_SGND

1%
1/16W
MF-LF
402

20.0K2

<Rb>
R79721

10%
25V 2
X7R
402

0.01uF

C7990

1%
1/16W
MF-LF
402 2

NO STUFF

10%
50V
CERM
402

CRITICAL
4

C7958 1

R7993

R7960

C7971 1
R7955

1%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

P1V05S0_COMP_R
1

2 3

P1V05S0_PHASE

PGND 10
THRML
PAD
17

R79901

P1V05S0_BOOT
65 54
32 23 5
50 43 39

P1V05ISENS_RC

CRITICAL

Q7970
G

R7998

10%
6.3V
CERM
402

20%
6.3V
2 X5R
402

R7994

0.22uF

2
2

1uF

10%
2 16V
X5R
603

C7959

P1V05S0_UG

C7981
1uF

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

PP5V_S0_P1V05S0_VCC

P1V05S0_BOOT_R

470pF

0603-LF

20%
2 16V
POLY
CASED2E-SM

C7998

10KOHM-5%
NO STUFF

33uF

1uF

C7980

1%
1/16W
MF-LF
402 2

PP3V3_S0

R7997

CRITICAL

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

CRITICAL

22UF

3.3V / 1.05V Power Supplies

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

Vout = 0.6V * (1 + Ra / Rb)

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Power Control Signals

66 65 64 63 61 51 46 25 5
70 67

State

3.425V "G3Hot" Supply

PP5V_S5

SMC_PM_G2_ENABLE

PM_SLP_S4_L

PM_SLP_S3_L

1
1
1
0

1
1
0
0

1
0
0
0

Run (S0)
Sleep (S3)

Supply needs to guarantee 3.31V delivered to SMC VRef generator

Soft-Off (S5)

R80501 R80511
10K

5%
1/16W
MF-LF
402 2
70 65 62

R8052

10K

5%
1/16W
MF-LF
402 2

68 67 66 4

5%
1/16W
MF-LF
2 402

Battery Off (G3Hot)

PPDCIN_G3H
P3V42G3H5_BOOST

GPU requires 1.2V, 1.8V, 2.5V and

3.3V rise after VCore is up.

C8000 1

PM_SLP_S3_LS5V_L
PM_SLP_S3_LS5V_L

70 65 62

Need to ensure that

ISL6269 PGOOD does not
deassert while GPU
PowerPlay is changing
GPU core voltage.

PM_SLP_S3_LS5V_L
PM_SLP_S3_LS5V_L

MAKE_BASE=TRUE

P3V3S0_EN_L

65 64

P3V3S0_EN_L

64 65

P1V8S0_EN

63 65

MAKE_BASE=TRUE
65 63

P1V8S0_EN

MAKE_BASE=TRUE
6

Q8055

TSOT23-8
SHDN*

L8010
33uH

PP3V42_G3H

1
2
CDPH4D19F-SM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

C8010 1

348K

22pF

1%
1/16W
MF-LF
2 402

5%
50V
CERM 2
402

4
5

<Rb>
R8011

SOT-363

PM_SLP_S3_LS5V
PM_SLP_S3_LS5V

PM_SLP_S3_LS5V

65 61 47 5

MAKE_BASE=TRUE
3

R8054
100K

SOT-363

64 62 55 26 25 24 23 22 11 5
78 66

Q8057

66 47 25 24 19 17 16 13 9 8 5

R80611
27.4K

PM_SLP_S3_L
PM_SLP_S3_L
PM_SLP_S3_L
PM_SLP_S3_L

(PM_SLP_S3_L)

MAKE_BASE=TRUE
IN
IN

5 23 32 39 43 50 54 64 65

70
65

R8062
10K

GPUVCORE_EN

1%
1/16W
MF-LF
402 2

65 70

Ensure 1.2V and 2.5V S3 supplies are up

before enabling GPU VCore to support
removing ethernet power in battery sleep.

PP5V_S5

PM_SLP_S4_LS5V

PM_SLP_S4_LS5V
PM_SLP_S4_LS5V

MAKE_BASE=TRUE

61 64 65
61 64 65

Q8055

2N7002DW-X-F

PM_SLP_S4_L

R80571

2.5V S3 and 1.2V S3 supplies are controlled

by ethernet power control circuit.

100K

5%
1/16W
MF-LF
402 2

P5VS5_PGOOD

(P5VS5_PGOOD)

MAKE_BASE=TRUE

5 23 41 46 47 50 63 65

SMC_PM_G2_EN_L

C8070 1

0.1uF
1

R8072
124K

20%
10V
CERM 2
402

U8070
7 V3

1%
1/16W
MF-LF
2 402

SC70

U8080 4

ALL_SYS_PWRGD

OUT

26 50

3 V4

LTC2908

0.1uF

20%
2 10V
CERM
402

LLP

CRITICAL

S0PGOOD_1V2_DIV

6 VADJ1

S0PGOOD_0V9_DIV

8 VADJ2

1%
1/16W
MF-LF
402 2

R8073

C8071

S0PGOOD_PWROK
LTC2908 sources 6uA at 5.0V
R8076 R8076 serves as pull-down
549K
and 3.3V level-shifter.

RST* 2

GND
1

THRML
PAD
9

1%
1/16W
MF-LF
2 402

100K

1%
1/16W
MF-LF
2 402

3.3V G3Hot Supply & Power Control

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

LTC2908 threshold is 95% (4.75V, 3.135V, 2.375V, 1.71V, 1.14V, 0.86V)

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

R80581

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

100K

5%
1/16W
MF-LF
402 2

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

MC74VHC1G08

20%
10V
CERM 2
402

100K

SOT-363

37 43 48 51 53 56 57 59 60 64
4 5 10 14 17 19 20 21 22
23 24 25 26 27 28 29 33 34 36
65 66 70 78 79

0.1UF

R80751

2N7002DW-X-F

SMC_PM_G2_EN

PP3V3_S0

Q8059

P1V5P1V05S0_PGOOD

5 60 64 65

MAKE_BASE=TRUE

51 64 65

SOT-363

OUT

C8080 1

1%
1/16W
MF-LF
402 2

2N7002DW-X-F

5%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
2 402

PP5V_S0
PP3V3_S0
PP2V5_S0
PP1V8_S0
PP1V2_S0
PP0V9_S0

68.1K

5 23 41 46 47 50 63 65

Q8059

10K

R8074

5 23 41 46 47 50 63 65

5%
1/16W
MF-LF
2 402

R8065

R8064

Other S0 Rails PWRGD Circuit

P5VS5_RUNSS
5 61
5V Enable has pull-up to PBUS

R8059
470K

Reports when 5V S0, 3.3V S0, 2.5V S0, 1.8V S0, 1.2V S0 and 0.9V S0 are in regulation
65 64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66
5
77 76 66 62 19 17
66 63 5

PP3V42_G3H

V-

66 31 30 5

PM_SLP_S4_L
PM_SLP_S4_L
PM_SLP_S4_L

(PM_SLP_S4_L)

P1V5P1V05S0_PGOOD
ISL6269 undervoltage threshold 81-87% (0.85 - 0.91V)
NOTE: R8065 acts as 10K pull-up for PGOOD signal

76 69 66 62 5

MAKE_BASE=TRUE

65 64 51

80 79 78 70 67 66 61 60 57
56 54 52 47 42 36 31 25 5 4

SOT-363

LMC7211
SM-LF
1
P1V5S0_PGOOD

P1V5P1V05S0_PGOOD

3
D

63 65

1.5V Comp threshold set to 1.32V (88%)

65 64 60 5

65 64 61

TP_P1V8S3_PGOOD
MAKE_BASE=TRUE

U8060

5
1

5%
1/16W
MF-LF
402 2

65 54 52 51 50 45 35 27 26 5
68 67 66

4
V+

10K

P1V0_P1V5PG_REF

5 23 32 39 43 50 54 64 65

R80551

65
46 41 23 5
63 50 47

1%
1/16W
MF-LF
2 402

P1V5S0_COMP_POS

MAKE_BASE=TRUE

5%
1/16W
MF-LF
402

TP_P1V8S3_PGOOD

C
61 65

20%
10V
CERM 2
402

4.99K

0.89V Reference

5 23 32 39 43 50 54 64 65

5%
1/16W
MF-LF
2 402

NO STUFF

P2V5S3_P1V2S3_PGOOD

67 66 65 64 63 61 51 46 25 5
70

5 23 32 39 43 50 54 64 65

R8063

10K

MAKE_BASE=TRUE

65 63

TP_P5V_P1V5_PGOOD
MAKE_BASE=TRUE

0.1uF

R8053

R8060
65 62

1%
1/16W
MF-LF
402 2

P2V5S3_P1V2S3_PGOOD
P2V5S3_P1V2S3_PGOOD

TP_P5V_P1V5_PGOOD

C8060 1

5%
1/16W
MF-LF
402 2

65 62

65 61

PP1V5_S0

SOT-363

100K

65 62

PP3V3_S5

2N7002DW-X-F

R80561

Unused PGOOD Signals

Reports when 1.5V S0 and 1.05V S0 are in regulation

2N7002DW-X-F

PM_SLP_S3

PM_SLP_S3_L

1.5V / 1.05V PWRGD Circuit

Q8057

3
65 64
39 32 23 5
54 50 43

5 47 61 65

5%
1/16W
MF-LF
2 402

SOT-363

Vout = 1.25V * (1 + Ra / Rb)

5 47 61 65

P1V5S0_RUNSS
5 61
1.5V Enable has pull-up to PBUS

Q8050

2N7002DW-X-F

20%
2 6.3V
CERM
805

1%
1/16W
MF-LF
2 402

PP3V42_G3H

C8015

200K

54 52 51 50 45 35 27 26 5
68 67 66 65

22UF

P3V42G3H_FB

2N7002DW-X-F

5 26 27 35 45 50 51 52 54 65 66
67 68

Vout = 3.425
200mA max output
(Switcher limit)

<Ra>
R8010

GND
4

Q8050

CRITICAL

P3V42G3H_SW

5
7

CRITICAL

SOT-363

SW
BIAS

2N7002DW-X-F

SOT-363

20%
6.3V 2
X5R
402

LT3470

1.8V Enable has pull-up to PBUS

0.22uF

U8000

Q8056

2N7002DW-X-F

10%
25V 2
X5R
1206

62 65 70

C8005 1

6
BOOST

3
VIN

10uF

62 65 70

06
86

PP3V42_G3H
PP0V9_S0

65 31 30 5
66

PP0V9_S0

65 54 52 51 50 45 35 27 26 5
68 67 66

PP0V9_S0

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

PP1V05_S0

PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66
5 7 8
25 34
5 7 8
25 34
5 7 8
25 34

PP3V3_S5_REG

5 7 8 9 11 12 13 16
19 21 24 25 34 54 64 66
66 64

66 61

PP1V5_S0_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

PP1V5_S0_REG

5 39 62 66

2
JUMPER
OPEN

PLACEMENT_NOTE=Place on top-side of board

PP1V2_S0

5 62 65 66 69 76

5 62 65 66 69 76
5 62 65 66 69 76
5 62 65 66 69 76
5 62 65 66 69 76

66 65 63 5

PP3V3_S3

B
66 65 63 5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_S0

5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66

PP3V3_S0

PLACEMENT_NOTE=Place on top-side of board

66 62

PP2V5_S3_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=2.5V
MAKE_BASE=TRUE

66 62

PP2V5_S3_REG

4 5 14 16 19 28 29 31 32 37 54
63 66
4 5 14 16 19 28 29 31 32 37 54
63 66
4 5 14 16 19 28 29 31 32 37 54
63 66
4 5 14 16 19 28 29 31 32 37 54
63 66
4 5 14 16 19 28 29 31 32 37 54
63 66

66 71 72 74 75

PP1V8_S0_GPU
PP1V8_S0_GPU
PP1V8_S0_GPU

66 71 72 74 75
66 71 72 74 75
66 71 72 74 75

PP2V5_S3

5 39 62 66

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.5V
MAKE_BASE=TRUE

XW8125
1

PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0

4 5 14 16 19 28 29 31 32 37 54
63 66

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE

JUMPER
OPEN

PP3V3_S0
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66
56 53 51 48 43 37 36
21 20 19 17 14 10 5 4
34 33 29 28 27 26 25 24 23 22
79 78 70 66 65 64 60 59 57

PP1V8_S0_GPU
XW8119

PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3

59 58 56 51 45 41 37 32 27 5
5 8 9 13 80 66 64 63 62
16 17 19 24 25 47 65 66
5 8 9 13 16 17 19 24 25 47 65
66
5 8 9 13 16 17 19 24 25 47 65
66

PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0

PP1V8_S3
PP1V8_S3
PP1V8_S3
PP1V8_S3
PP1V8_S3

PP1V8_S0

2
JUMPER
OPEN

PP2V5_S3
PP2V5_S3

5 39 62 66

PP2V5_S0

5 17 19 62 65 66 76 77

5 39 62 66

PLACEMENT_NOTE=Place on top-side of board

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0
MAKE_BASE=TRUE
62 19 17 5
77 76 66 65

PP2V5_S0

PP2V5_S0
PP2V5_S0
PP2V5_S0
PP2V5_S0
PP2V5_S0

5 17 19 62 65 66 76 77
5 17 19 62 65 66 76 77
5 17 19 62 65 66 76 77
5 17 19 62 65 66 76 77
5 17 19 62 65 66 76 77

PPVCORE_S0_GPU

5 54 66 70 71 76

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE
70 66 54 5
76 71

PPVCORE_S0_GPU

PPVCORE_S0_GPU
PPVCORE_S0_GPU

5 54 66 70 71 76
5 54 66 70 71 76

PPDCIN_G3H

PP3V3_S0_GPU

4 65 66 67 68

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
MAKE_BASE=TRUE
67 66 65 4
68

PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

5 8 9 13 16 17 19 24 25 47 65
66

PP1V8_S3

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE
63 54 37 32
16 14 5 4
31 29 28 19
66

5 39 62 66

PP1V5_S0

1
JUMPER
OPEN

PP1V2_S3
PP1V2_S3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0
MAKE_BASE=TRUE

XW8115

XW8133

PLACEMENT_NOTE=Place on top-side of board

PP1V2_S0
PP1V2_S0
PP1V2_S0
PP1V2_S0

PP1V2_S0

PP3V3_S5_REG

5 39 62 66

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE
66 65 62 5
76 69

PP3V3_S5

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
17 MAKE_BASE=TRUE

PP1V2_S3

9 11 12 13 16 17 19 21 24
54 64 66
9 11 12 13 16 17 19 21 24
54 64 66
9 11 12 13 16 17 19 21 24
54 64 66

5 7 8 9 11 12 13 16 17 19 21 24
25 34 54 64 66
66
5 7 8 9 11 12 13 16 17
19 21 24 25 34 54 64
66
5 7 8 9 11 12 13 16 17
19 21 24 25 34 54 64

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.22 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE
66 62 39 5

PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H

PP3V42_G3H

5 30 31 65 66

PP1V05_S0

25 24 21 19
11 9 8 7 5
17 16 13 12
66 64 54 34

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.425V
MAKE_BASE=TRUE

5 30 31 65 66

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

R8133

PPDCIN_G3H

4 65 66 67 68

5%
1/8W
MF-LF
805

GND
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

PLACEMENT_NOTE=Place on top-side of board

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S0_GPU
PP3V3_S0_GPU
PP3V3_S0_GPU
PP3V3_S0_GPU
PP3V3_S0_GPU
PP3V3_S0_GPU
PP3V3_S0_GPU

"S3AC" rail is ON in S3 on AC, OFF in S3 on battery

5 26 27 35 45 50 51 52 54 65 66
67 68

PP3V3_S3AC
5 26 27 35 45 50
67 68
5 26 27 35 45 50
54 65 66 67 68
5 26 27 35 45 50
67 68
5 26 27 35 45 50
67 68
5 26 27 35 45 50
67 68

51 52 54 65 66
51 52

PP3V3_S3AC

51 52 54 65 66

PNBB_S0_GPU

5 26 27 35 45 50 51 52 54 65 66
67 68
5 26 27 35 45 50 51 52 54 65 66
67 68

PPBB_S0_GPU

PPVCORE_S0_CPU

PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H

PPBUS_G3H

5 11 22 23 24 25 26 55 62 64 65
66 78
5 11 22 23 24 25 26 55 62 64 65
66 78
5 27 32 37 41 45 51 56 58 59 62
63 64 66 80

5 27 32 37 41 45 51 56 58 59 62
63 64 66 80
5 27 32 37 41 45 51 56 58 59 62
63 64 66 80
5 27 32 37 41 45 51 56 58 59 62
63 64 66 80
5 27 32 37 41 45 51 56 58 59 62
63 64 66 80
5 27 32 37 41 45 51 56 58 59 62
63 64 66 80
5 27 32 37 41 45 51 56 58 59 62
63 64 66 80
66 80
5 27 32 66 43 42 38 4
37 41 45 51 56 58 59 62 63 64

PPBUS_S5_FW_FET
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=33V
MAKE_BASE=TRUE

PPBUS_S5_FW_FET

5 27 32 37 41 45 51 56 58 59 62
63 64 66 80
66 80
5 27 32 37 41 45 66 61
51 56 58 59 62 63 64
5 27 32 37 41 45 51 56
58 59 62 63 64 66 80

PP5V_S5_REG

2
JUMPER
OPEN

PLACEMENT_NOTE=Place on top-side of board

48 51 53 56
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
57 59 60 64 65 66 70 78 79

66 80
5 45
51 61

5 45
51 61
66 80
80
61 66
5 45
51
80
67 70
60 61
52 54
4 5 25 31 36
42 47
56 57
65 66
78 79

PP5V_S0
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
MAKE_BASE=TRUE

PP5V_S0

80
67 70
60 61
52 54
4 5 25
42 47
56 57
65 66
78 79
4 5 25
42 47
56 57
65 66
78 79
4 5 25
8042 54
67 70
60 61
52 54
4 5 25
42 47
56 57
65 66
78 79
4 5 25
42 47
52 54
56 57
60 61
65 4 66
675 70
8025
31
36
42
47
52
54
56
57
60
61
65
66
67
70
78
79
80

PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0

48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79 70 78 79
48 51 53 56 57 59 60 64 65 66
25 26 27 28 29 33 34 36 37 43
4 5 10 14 17 19 20 21 22 23 24
48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79 70 78 79
48 51 53 56 57 59 60 64 65 66
25 26 27 28 29 33 34 36 37 43
4 5 10 14 17 19 20 21 22 23 24
48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79 70 78 79
48 51 53 56 57 59 60 64 65 66
25 26 27 28 29 33 34 36 37 43
4 5 10 14 17 19 20 21 22 23 24
48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79
70 78 79
48 51 53 56 57 59 60 64 65 66
25 26 27 28 29 33 34 36 37 43
4 5 10 14 17 19 20 21 22 23 24
48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79
70 78 79
48 51 53 56 57 59 60 64 65 66
25 26 27 28 29 33 34 36 37 43
4 5 10 14 17 19 20 21 22 23 24
48 51 53 56 57 59 60 64 65 66
4 5 10 14 17 19 20 21 22 23 24
25 26 27 28 29 33 34 36 37 43
70 78 79

31
80
67
60
52
31
80
67
60
47
31
56
65
78

36
70
61
54
36
70
61
52
36
57
66
79

31 36

31 36
78 79

Power Aliases
SYNC_MASTER=M1_MLB

SYNC_DATE=12/19/2005

66 70 73 76

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

66 70 73 76
66 70 73 76

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

66 70 73 76

II NOT TO REPRODUCE OR COPY IT

66 70 73 76

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

66 70 73 76

SIZE

66 70 73 76
66 70 73 76

46
51
6661
5163
5
4564
65
6166
8067
70

PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3

70 78 79
48 51 53 56 57 59 60 64 65 66
25 26 27 28 29 33 34 36 37 43
4 5 10 14 17 19 20 21 22 23 24

68 70
43 47
63 64
54 60
43 47
70 78

66 67
61 63
5 25
46 51
64 65
70 5
25

PP5V_S3

43 47
63 64
54 60
43 47
70 78

66 67
61 63
5 25
46 51
64 65
70 5
25
4646
5 51
2561 70
5163 61 63 64
6164 5
6365 25 46 51
6466 65 66 67
6567
6670
67
70 66
61 63
5 25
46 51
64 65
67 70

PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
MAKE_BASE=TRUE

64 66
43 47
68 70
60 61

66 67
61 63
5 25
46 51
64 65
70

PP5V_S5
XW8150

70 78
54 60
64 66

66
4 38
42 43

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
MAKE_BASE=TRUE

DRAWING NUMBER

REV.

051-7023

SHT
NONE

61
43 68
784 5
7041 47
6878 63
6670
6468
6366 78
6164 63
6063 41
5461 4
4760 5
4154 54
4 47
5 43
4341
4
68 5 70
61 63
4 5 41
54 60
64 66
784
5 41
4161 68
4 66
5
43 47
54 60
61 63
64 66
68 70
7861 66
4 5 41
54 60
63 64
784
5 41
61 68
66
66
4 38
42 43

PPBUS_G3H

5 11 22 23 24 25 26 55 62 64 65
66 78
5 11 22 23 24 25 26 55 62 64 65
66 78

56 54 52 47 42 36 31 25 5 4
80 79 78 70 67 66 65 61 60 57

66
5 8 9
54 60

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

5 11 22 23 24 25 26 55 62 64 65
66 78
5 11 22 23 24 25 26 55 62 64 65
66 78
5 11 22 23 24 25 26 55
62 64 65 66 78

PP5V_S5_REG

66
5 8 9
54 60

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.1V
MAKE_BASE=TRUE

5 11 22 23 24 25 26 55
62 64 65 66 78
5 11 22 23 24 25 26 55 62 64 65
66 78
5 11 22 23 24 25 26 55 62 64 65
66 78

5 27 32 37 41 45 51
58 59 62 63 64 66 80
5 27 32 37 41 45 66 61
51 56 58 59 62 63 64 66 80
5 27 32 37 41 45 51 56 58 59 62
63 64 66 80

66 70
71

PPVCORE_S0_CPU

5 11 22 23 24 25 26 55 62 64 65
66 78
5 11 22 23 24 25 26 55 62 64 65
66 78
5 11 22 23 24 25 26 55 62 64 65
66 78

66 70
71

PPBB_S0_GPU

5 11 22 23 24 25 26 55 62 64 65
66 78

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=5V
56 MAKE_BASE=TRUE

66 70
71

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.9V
MAKE_BASE=TRUE

5 11 22 23 24 25 26 55 62 64 65
66 78
71 70 66

66 70
71

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=-0.7V
MAKE_BASE=TRUE

51 52 54 65 66

5 26 27 35 45 50 51 52 54 65 66
67 68
5 26 27 35 45 50 51 52
54 65 66 67 68
5 26 27 35 45 50 51 52 54 65 66
67 68

SCALE

5 39
41 66

51 52 54 65 66

APPLE COMPUTER INC.

5 39
41 66

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.22 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

5 26 27 35 45 50 51 52 54 65 66
67 68

06
86

DC-In Connector
D

Place XW8200/8210 at 5V switcher

CRITICAL

J8290

(2 Amps)
PP5V_S0_AUDIO_PWR

XW8200
SM
1

PP5V_S0

4 5 25 31 36 42 47 52 54 56 57
60 61 65 66 70 78 79 80

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=5V

87438-0832
M-RT-SM
1
2

XW8210
SM

(2 Amps)
GND_AUDIO_PWR

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=0V

3
4
5
6

PP5V_S5

5 25 46 51 61 63 64 65 66 70

PP18V5_DCIN

5 67

7
8

VOLTAGE=18.5V
MIN_LINE_WIDTH=0.60mm
MIN_NECK_WIDTH=0.20mm

D8201

518S0146

R8207

1SS355
1

SOD-323

PPDCIN_G3H_R
VOLTAGE=18.5V
MIN_LINE_WIDTH=0.50mm
MIN_NECK_WIDTH=0.20mm

PPDCIN_G3H

4 65 66 68

5%
1/8W
MF-LF
805

Inrush Limiter

Battery Connector

CRITICAL

Q8250

SI4405DY-E3

B
67 5

SO-8

PP18V5_DCIN

R82211

470K
66
52
45
26 5
35 27
51 50
65 54
68 67

68 67 66
65 54 52 51 50 45 35 27
26
5

PP3V42_G3H

0.22uF

1%
1/16W
MF-LF
402 2

ACIN Detection

PP3V42_G3H

C8250

3
2
1

S3
S2

PP18V5_G3H_CHGR
D4
D3
D2
D1

J8250
87438-1043
M-RT-SM

PP18V5_G3H_CHGR

67 68

PP18V5_G3H_CHGR

3
67 68

ACIN_ENABLE_DIV_L

0.1uF

<R1b>
R82121
102K

1%
1/16W
MF-LF
402 2

<R1a>
R8214

51 50 43

102K

1%
1/16W
MF-LF
2 402

ACIN_1V20_REF

BATT_NEG
SMC_BS_ALRT_L
OUT
SMBUS_SMC_BSA_SDA BI
SMBUS_SMC_BSA_SCL BI
(HOST_DETECT_L)
BATT_POS

BATT_NEG

5 67 68

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

5 50 51
5 27 50

BATT_NEG

5 67 68

BATT_POS

5 67 68

5 27 50

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

9
10

BATT_POS

5 67 68

U8200

LMC7211
V+

330K

68
67 5

ACIN_ENABLE_DIV2_L

SMC_ADAPTER_EN

CRITICAL
2

R8250

5%
1/16W
MF-LF
402 2

20%
2 10V
CERM
402

C8210

4
5

MIN_LINE_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2mm
1

1
2

VOLTAGE=18.5V

CRITICAL

67 68

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

GATE

20%
2 25V
X5R
603

8
7
6
5

SM-LF
1

SC70
4

U8250

518S0391

Q8210

MC74VHC1G08

2N7002

ACOK_AND_PS_ON

SOT23-LF

ACIN_DIV

<R2b>
R82131
10K

1%
1/16W
MF-LF
402 2

<R2a>
R8215

DC-In & Battery Connectors

R8216

54.9K

1%
1/16W
MF-LF
2 402

SMC_BC_ACOK

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

5 47 50 51 68

NOTICE OF PROPRIETARY PROPERTY

5%
1/16W
MF-LF
402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

Vref = 3.42V * (R2a / (R1a + R2a))

Vth = (Vref / (R2b / (R1b + R2b))

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

Vref = 1.20V
Vth = 13.4V

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

CRITICAL

PBUS SUPPLY

Q8300

SI4405DY-E3
SO-8
8
7
6
5

C8311
1uF

IRLML5203-2.6A

118K

R8342

1%
1/16W
MF-LF
2 402

93.1K

1%
1/16W
MF-LF
402 2

R8341
10K

1%
1/16W
MF-LF
2 402

CHGR_DCIN
68
NO STUFF C8300
C8340 1 C8307 0.033uF
0.1uF
0.1UF
1
2

20%
2 25V
X5R
402

CHGR_ACSET 68

20%
25V
2 CERM
603

CHGR_ICM_R

5%
1/16W
MF-LF
402

10%
16V
X5R
402

34.8K2

SOT23

CHGR_CSON_R

1
48 68

1%
1/16W
MF-LF
402

CHGR_VCOMP_C1

10%
16V
CERM-X5R
402

NO STUFF

CHGR_ACSET_D

10K

R83441

C8314
1

C8341

100K

1%
1/16W
MF-LF
402 2

0.1uF

CHGR_VREF

8
3
4
9
2

CHGR_DCSET 68

CHGR_VDD

C8302

CHGR_EN

10%
2 16V
CERM
402

C8370

0.1uF

C8322 C8325
0.01UF

10%
2 16V
X5R
402

10%
2 16V
CERM
402

R8330

3
2
1

S3
S2

1%
1/16W
MF-LF
2 402

10%
10V
CERM 2
402

11K

CHGR_SGND

C8361

R8324

Using PWM drive

1%
1/16W
MF-LF
2 402
68

CHGR_VREF

Q8322
SOT-363

CHGR_SGND

SMC_BC_ACOK

CHGR_CHLIM 68
1

R8366
6.04K

1%
1/16W
MF-LF
2 402

10K

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
2 402

24.3K2
1

As shown, Ichg = 3.9A max

Q8324

C8362

3
2
1

S3
S2

8
7
6
5

D4
D3
D2
D1

0.01 2

XW8304
SM

XW8303
SM
0.5%

C8310

R8304
68 48

CHGR_CSON_R

5%
1/8W
MF-LF
805

4 65 66 67

CHGR_CSOP_R

CRITICAL
1

L8320

PPVBATT_G3H_FUSE

BATT_POS
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

SM-LF
1

5 67

C8327

0.001UF

10%
2 50V
CERM
402

TCHG_EN_DIV_L
MIN_LINE_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2mm
1

R8323

GND_BATT_CHGND

C8330
0.001UF

TCHG_EN_DIV2_L

10%
2 50V
CERM
402

L8321

1
6

Q8324

BATT_NEG

5 67

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

SM-LF
D

2N7002DW-X-F

SMC_BATT_TRICKLE_EN_L

PBus Supply & Batt. Charger

SYNC_MASTER=M1_LIO

50
51

SYNC_DATE=12/19/2005

NOTICE OF PROPRIETARY PROPERTY

SMC_BATT_CHG_EN

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

0.1UF

20%
2 10V
CERM
402

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

CHGR_CSO_P 68

FERR-50-OHM
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

1206

2.2

5%
1/16W
MF-LF
402

F8302

CHGR_CSO_N 68

R8306
PPDCIN_G3H

8AMP-24V
PPVBATT_G3H_FET

270

5%
1/16W
MF-LF
402

Using PWM drive

10%
16V
2 X5R
603

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.25mm

C8323 1
20%
10V
CERM 2
402

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

FERR-50-OHM

0.1UF

PPVBAT_G3H_CHGR_OUT

0.5%
1W
MF
0612

PPVBATT_G3H_DIO

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

GATE

SOT-363

SMC_BC_ACOK_R

R8308

20%
16V
ELEC
6.3X5.5SM1

SOT-363

67 51 50 47 5

24.3K

1%
1/16W
MF-LF
402

100uF

3
D

R8325

R8367

SMC_BATT_ISET

C8309

1SS355

SO-8

SOT-363

20%
2
POLY
CASED2E-SM

2N7002DW-X-F

R8362

33uF

1%
1/16W
MF-LF
2 402

2N7002DW-X-F

CHGR_ACPRN

Q8322

C8308

35.7K

6
D

C8324

CHG_EN_DIV2_L

100K

20%
2 10V
CERM
402

NO STUFF
20%
2 16V
CERM
402

5%
1/16W
MF-LF
2 402

PP3V42_G3H

54 52 51 50 45 35 27 26 5
67 66 65

0.1UF

1%
1/16W
MF-LF
2 402

R8321

Q8321

R83221

0.01UF

330K

CHGR_ACLIM 68

4 5 41 43 47 54 60 61 63 64
66 70 78

CRITICAL

D8321
SOD-323

SI4405DY-E3

1%
1/16W
MF-LF
402 2

R8331

R8360
R8363

Q8302

VOLTAGE=12.6V

CRITICAL
8
7
6
5

GATE
4

5%
3W
MF
2525

D4
D3
D2
D1

470K

0.22uF

Q8320

PPBUS_G3H

CRITICAL

HAT2165H

CRITICAL

MIN_LINE_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2mm

1%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

LFPAK

39.2K

5
1

PPVBATT_G3H_PRE

CHGR_SGND

C8321

10A max, limited by L8300, Q8301

SWITCH_NODE=TRUE

R8320

CHG_EN_DIV_L

10K

BATTERY CHARGER

NO STUFF

4.7UH

1uF

PPVBAT_G3H_CHGR_OUT
0.01uF

10UF

10%
2 25V
X5R
1206

HAT2168H

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

SO-8

C8320

10UF

10%
2 25V
X5R
1206

Q8301

CHGR_PHASE

SI4405DY-E3

C8305 1 C8306

If stuffed, R8364+R8365 > 70K

so Iref < 100uA

CHGR_SGND

CRITICAL

4
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

L8300 3

10%
50V
603

5%
1/16W
MF-LF
402 2

SOT23-LF

C8316

10%
2 25V
X5R
1206

1 2 3

CHGR_VADJ

10UF

1 2 3

49.9 2

0.0022uF

Q8350

SMC_SYS_ISET

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

2 CERM

CHGR_ACPRN 68
CHGR_DCPRN 68

PPVDCIN_G3H_R

LFPAK

1/16W
MF-LF
603

B0530WXF

R8370

R8365

2
68

DCSET 28

CHGR_VDDP

2
20%
25V
X5R
402

CHGR_DCPRN 68
CHGR_DCSET 68

DCPRN 24

NO STUFF1

CHGR_LGATE
CHGR_EN 68

XW8302
SM

CHGR_CSIN_R

2N7002

2 CHGR_BOOT_R

5%
1/16W
MF-LF
402

C8303

0.5%
1W
MF
2 0612

2 16V

5%
1/16W
MF-LF
402 2

2.2

0.02

0.1uF

LGATE 12

CHGR_SGND

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

R8307

D8300
SOD-123

1%
1/16W
MF-LF
2 402

UGATE 15
PHASE 16

CHGR_VREF
NO STUFF1

100K

1%
1/16W
MF-LF
2 402

CHGR_BOOT
CHGR_UGATE

BOOT 14

1/16W
MF-LF
402

R8303
1

18
5%

20%
2 10V
CERM
402

NO_TEST=TRUE

R8305

0.1UF

NC_CHGR_BGATE
CHGR_DCIN 68

BGATE 17
DCIN 25

XW8300
SM

R8350

100K

CSIN 20

U8300

C8304

R8364

R8352

CRITICAL

QFN

23 ACPRN
27 ACSET

CHGR_SGATE
CHGR_CSI_P
CHGR_CSI_N

SGATE 18

XW8301
SM

MIN_LINE_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2mm
1

ISL6255AHRZ
CELLS

10%
2 25V
X7R
402

C8312

VDDP

6 VREF

VCOMP
VADJ

0.0082uF

10%
50V
CERM
402

ICOMP

1%
1/16W
MF-LF
2 402

1uF

CSIP 19

100K

10%
2 6.3V
CERM
402

ACLIM

CHGR_SGND
680pF

21 CSOP
22 CSON
7 CHLIM

CHGR_ACPRN
CHGR_ACSET

C8315

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

R8310

CHGR_VDDP

5 ICM

CHGR_ACLIM
CHGR_ICOMP
CHGR_VCOMP
CHGR_VADJ

NO STUFF

VDD

68
68

1%
1/16W
MF-LF
402

10%
10V
CERM
402

10%
2 16V
X5R
402

CHGR_CSO_P
CHGR_CSO_N
CHGR_CHLIM

0.068UF

1%
1/16W
MF-LF
402 2

100

CHGR_ICM

C8301
R8301 0.022uF

MMBD914XXG

R8302
1

R8311

CHGR_ICOMP_R

D8340

R83431

10%
50V
CERM 2
402

PPVDCIN_G3H_PRE
1NO STUFF

5%
1/16W
MF-LF
402

0.0033uF

R8340

4.7

C8319 1

S
1

R8300

CHGR_VDD

3
2
1

S3
S2

GATE

CHGR_VDD

THRML_PAD

10%
6.3V
CERM
402

CHGR_PHASE_R

Q8340

CHGR_SGND

PGND

PP18V5_G3H_CHGR

10 GND

3
67

D4
D3
D2
D1

06
86

OMIT

U8400
M56P

BGA
(1 OF 7)
13

C8420

PEG_R2D_C_P<0>

0.1uF

2
10% 16V X5R 402

C8421

PEG_R2D_C_N<0>

0.1uF

PEG_R2D_P<0>
PEG_R2D_N<0>

AJ31
AH31

PCIE_TX0P
PCIE_TX0N

PCIE_RX0P
PCIE_RX0N

AK27
AJ27

PEG_D2R_C_P<0>
PEG_D2R_C_N<0>

C8422

PEG_R2D_C_P<1>

0.1uF

2
10% 16V X5R 402

C8423

PEG_R2D_C_N<1>

0.1uF

PEG_R2D_P<1>
PEG_R2D_N<1>

AH30
AG30

PCIE_TX1P
PCIE_TX1N

PCIE_RX1P
PCIE_RX1N

PEG_R2D_C_P<2>

C8424

PEG_R2D_C_N<2>

C8425

0.1uF

2
10% 16V X5R 402

0.1uF

C8426

PEG_R2D_C_P<3>

0.1uF

C8427

PEG_R2D_C_N<3>

0.1uF

PEG_R2D_P<2>
PEG_R2D_N<2>

AG32
AF32

C8428

PEG_R2D_C_P<4>

0.1uF

C8429

PEG_R2D_C_N<4>

0.1uF

PEG_R2D_P<3>
PEG_R2D_N<3>

AF31
AE31

PCIE_RX3P
PCIE_RX3N

PEG_R2D_P<4>
PEG_R2D_N<4>

AE30
AD30

PCIE_RX4P
PCIE_RX4N

2
10% 16V X5R 402

C8430

PEG_R2D_C_P<5>

0.1uF

2
10% 16V X5R 402

C8431

PEG_R2D_C_N<5>

0.1uF

PEG_R2D_P<5>
PEG_R2D_N<5>

AD32
AC32

PCIE_RX5P
PCIE_RX5N

2
10% 16V X5R 402

C8432

PEG_R2D_C_P<6>

0.1uF

2
10% 16V X5R 402

C8433

PEG_R2D_C_N<6>

0.1uF

AJ25
AH25

PEG_D2R_C_P<1>
PEG_D2R_C_N<1>

AH28
AG28

PEG_D2R_C_P<2>
PEG_D2R_C_N<2>

PEG_R2D_P<6>
PEG_R2D_N<6>

AC31
AB31

PCIE_RX6P
PCIE_RX6N

PCIE_TX3P
PCIE_TX3N

AG27
AF27

PEG_D2R_C_P<3>
PEG_D2R_C_N<3>

76 69 66 65 62 5

PP1V2_S0
PP1V2_S0

C8435

PEG_R2D_C_N<7>

0.1uF

PCIE_TX4P
PCIE_TX4N

AF25
AE25

PEG_D2R_C_P<4>
PEG_D2R_C_N<4>

L8400

PCIE_TX5P
PCIE_TX5N

AE28
AD28

PEG_D2R_C_P<5>
PEG_D2R_C_N<5>

PEG_R2D_C_P<8>

C8436

0.1uF

PEG_R2D_C_N<8>

C8437

0.1uF

BGA
(2 OF 7)

OMIT
PCIE_PVDD_12
(1.2V)

N23
P23
U23
V23

C8402

PCI EXPRESS POWER & GROUND

PCIE_VDDR_12
(1.2V)

PCIE_VSS

PCIE_PVSS

C8438

PEG_R2D_C_P<9>

1uF

10%
6.3V
CERM 2
402

C8401

1uF

10%
6.3V
CERM 2
402

C8400

0.1uF

2
10% 16V X5R 402

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.2V

PCIE_TX6P
PCIE_TX6N

AD27
AC27

PEG_D2R_C_P<6>
PEG_D2R_C_N<6>

C8439

PEG_R2D_C_N<9>

0.1uF

22UF

20%
6.3V
2 CERM
805

PEG_R2D_C_P<10>

C8440

0.1uF

PEG_R2D_C_N<10>

C8441

0.1uF

PEG_R2D_P<7>
PEG_R2D_N<7>

AB30
AA30

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

AC25
AB25

PEG_D2R_C_P<7>
PEG_D2R_C_N<7>

C8407 1 C8406

1uF

10%
6.3V
CERM 2
402

C8405

PEG_R2D_C_P<11>

C8442

0.1uF

22UF

PEG_R2D_C_N<11>

C8443

0.1uF

PEG_R2D_P<8>
PEG_R2D_N<8>

AA32
Y32

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

AB28
AA28

PEG_D2R_C_P<8>
PEG_D2R_C_N<8>

PEG_R2D_C_P<12>

C8444

0.1uF

10% 16V X5R 402

C8413 1 C8412

1uF

10%
6.3V 2
CERM
402

C8411

1uF

10%
6.3V 2
CERM
402

C8410

PEG_R2D_C_N<12>

C8445

0.1uF

20%
2 6.3V
CERM
805

PEG_R2D_C_P<13>

C8446

0.1uF

2
10% 16V X5R 402

PEG_R2D_C_N<13>

C8447

0.1uF

Y31
W31

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

AA27
Y27

PEG_D2R_C_P<9>
PEG_D2R_C_N<9>

N24
N30
P24
P25
P26
P28
P29
P30
R23
R24
R25
R26
R29
R31
T24
T26
T27
T29
U24
U26
U28
U29
U30
V24
V25
V26
V29
V31
W24
W26

PEG_R2D_P<10>
PEG_R2D_N<10>

W30
V30

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

Y25
W25

PEG_D2R_C_P<10>
PEG_D2R_C_N<10>

C8448

0.1uF

PEG_R2D_C_N<14>

C8449

0.1uF

PEG_R2D_C_P<15>

C8450

0.1uF

2
10% 16V X5R 402

PEG_R2D_C_N<15>

C8451

0.1uF

C8462

0.1uF

IN
IN

OUT

PEG_D2R_N<2>

OUT

PEG_D2R_P<3>

OUT

PEG_D2R_N<3>

OUT

PEG_D2R_P<4>

OUT

PEG_D2R_N<4>

OUT

PEG_D2R_P<5>

OUT

PEG_D2R_N<5>

OUT

PEG_D2R_P<6>

OUT

PEG_D2R_N<6>

OUT

PEG_D2R_P<7>

OUT

PEG_D2R_N<7>

OUT

PEG_D2R_P<8>

OUT

PEG_D2R_N<8>

OUT

PEG_D2R_P<9>

OUT

PEG_D2R_N<9>

OUT

PEG_D2R_P<10>

OUT

PEG_D2R_N<10>

OUT

PEG_D2R_P<11>

OUT

PEG_D2R_N<11>

OUT

PEG_D2R_P<12>

OUT

PEG_D2R_N<12>

OUT

PEG_D2R_P<13>

OUT

PEG_D2R_N<13>

OUT

PEG_D2R_P<14>

OUT

PEG_D2R_N<14>

OUT

PEG_D2R_P<15>

OUT

PEG_D2R_N<15>

OUT

C8463

0.1uF

C8464

0.1uF

C8465

0.1uF

C8466

0.1uF

C8467

0.1uF

C8468

0.1uF

10% 16V X5R 402

C8469

0.1uF

C8470

0.1uF

C8471

0.1uF

2
10% 16V X5R 402

10% 16V X5R 402

C8472

0.1uF

C8473

0.1uF

C8474

0.1uF

10% 16V X5R 402

C8475

0.1uF

C8476

0.1uF

10% 16V X5R 402

PEG_R2D_P<11>
PEG_R2D_N<11>

V32
U32

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

W28
V28

PEG_D2R_C_P<11>
PEG_D2R_C_N<11>

C8477

0.1uF

C8478

0.1uF

C8479

0.1uF

C8480

0.1uF

C8481

0.1uF

C8482

0.1uF

10% 16V X5R 402

PEG_R2D_P<12>
PEG_R2D_N<12>

U31
T31

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

V27
U27

PEG_D2R_C_P<12>
PEG_D2R_C_N<12>

10% 16V X5R 402

PEG_R2D_P<13>
PEG_R2D_N<13>

T30
R30

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

U25
T25

PEG_D2R_C_P<13>
PEG_D2R_C_N<13>

10% 16V X5R 402

PEG_R2D_P<14>
PEG_R2D_N<14>

R32
P32

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

T28
R28

PEG_D2R_C_P<14>
PEG_D2R_C_N<14>

C8483

0.1uF

C8484

0.1uF

10% 16V X5R 402

PEG_R2D_P<15>
PEG_R2D_N<15>

P31
N31

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

R27
P27

PEG_D2R_C_P<15>
PEG_D2R_C_N<15>

C8485

0.1uF

C8486

0.1uF

10% 16V X5R 402

PP1V2_S0

PEG_CLK100M_GPU_P
PEG_CLK100M_GPU_N

AL28
AK28

PCIE_REFCLKP
PCIE_REFCLKN

5 62 65 66 69 76

R8495
2.0K

26 5

PEG_RESET_L

AG24
AF24

PERST*
PERST*_MASK

AA24

PCIE_TEST

PCIE_CALRP
PCIE_CALRN

AD24
AE24

GPU_PCIE_CALRP
GPU_PCIE_CALRN

PCIE_CALI

AB24

GPU_PCIE_CALI

R84971
1.47K
1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

R8496
562

1%
1/16W
MF-LF
2 402

ATI M56 PCI-E

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

10% 16V X5R 402

PEG_D2R_P<2>

10% 16V X5R 402

0.1uF

PEG_R2D_C_P<14>

10% 16V X5R 402

W23

C8461

10% 16V X5R 402

PCIE_VSS

PEG_R2D_P<9>
PEG_R2D_N<9>

10% 16V X5R 402

22UF

OUT

10% 16V X5R 402

20%
6.3V
2 CERM
805

C8460

0.1uF

OUT

PEG_D2R_N<1>

10% 16V X5R 402

2000mA

10% 16V X5R 402

PEG_D2R_P<1>

10% 16V X5R 402

N25
N26
N27
N28
N29
AL29
AL30
AL31
AL32
AM27
AM28
AM29
AM30
AM31

PP1V2_S0_PCIE_GPU_PVDD_F

100mA

0.1uF

10% 16V X5R 402

M56P

C8459

OUT

10% 16V X5R 402

U8400
W27
W29
Y24
Y26
Y28
Y29
Y30
AA23
AA25
AA26
AA29
AA31
AB23
AB26
AB27
AB29
AC23
AC24
AC26
AC28
AC29
AC30
AD25
AD26
AD29
AD31
AE26
AE27
AE29
AF26
AF28
AF29
AF30
AG25
AG26
AG29
AG31
AH24
AH26
AH27
AH29
AJ26
AJ28
AJ29
AJ30
AJ32
AK26
AK29
AK30
AK31
AK32
AL27

10% 16V X5R 402

0402

PEG_D2R_N<0>

10% 16V X5R 402

200-OHM-EMI

0.1uF

10% 16V X5R 402

C8434

PEG_R2D_C_P<7>

0.1uF

10% 16V X5R 402

76 69 66 65 62 5

C8458

OUT

10% 16V X5R 402

PCIE_TX2P
PCIE_TX2N

PCIE_RX2P
PCIE_RX2N

10% 16V X5R 402

C8457

0.1uF

PEG_D2R_P<0>

10% 16V X5R 402

PCI-EXPRESS BUS INTERFACE

0.1uF

10% 16V X5R 402

0.1uF

C8456

2
10% 16V X5R 402

C8455

06
86

GPU VCore Current Sense

GPUISENS_NTC
1

64 63 61 60 54 47 43 41 5
78 68

C8501

R8502

2.2UF

20%
6.3V
CERM1 2
603

5%
1/16W
MF-LF
2 402

GPUVCORE_BOOT_R

R8509
12
PVCC

20%
6.3V
CERM1 2
603

U8500

GPUVCORE_FSET

4
3
16
5

PM_SLP_S3_LS5V_L
GPUVCORE_COMP

R8508

C8507

150K

C8506 1
0.01UF

10%
16V
CERM 2
402

R8506

1%
1/16W
MF-LF
2 402

NO STUFF
1

R8505

FCCM
PGOOD
COMP

CRITICAL

649

GPUVCORE_LG

10%
25V 2
X7R
402

CRITICAL

C8521

3.01K

1%
1/16W
MF-LF
402 2

GPUVCORE_IOUT

10%
2 25V
X7R
402

OUT

R8592
1M

C8592

1%
1/16W
MF-LF
402

470pF
2

10%
50V
CERM
402

R8520

20%
2V
POLY 2
CASE-D2-SM

330uF

GPUVCORE_FB_RC
NO STUFF

C8520 1

0.0022uF

10%
50V
CERM 2
402

1%
1/16W
MF-LF
402 2

C8542 1

20%
6.3V 2
CERM
805

22UF

5%
1/16W
MF-LF
2 402

5.11K

B340LBXF

C8540 1

5 54 66 70 71 76

Vout = 1.10V / 0.95V

17A max output
(Q8520 limit)

NO STUFF
1

<Rb>
R85221

D8520
SMB

1000pF

1 2 3

SOT23-5
1

GPUISENS_POS

1 2 3

NO STUFF
1

LFPAK

1000pF

<Ra>
R85211

Q8521

PPVCORE_S0_GPU

LFPAK

C8522 1

1uF

U8595
LMV2011MF

Keep C8590, R8590,

R8594 and R8597
close to inductor

HAT2165H

Placement Note:

CRITICAL

Q8522

GPUISENS_NEG

C8595

10%
2 6.3V
CERM
402

NO STUFF

GND_GPUVCORE_SGND

L8520

1.0uH-20.5

1%
1/16W
MF-LF
402

SM1

3.01K2
1%
1/16W
MF-LF
402

XW8500
SM

20.0K2

CRITICAL
NC

1%
1/16W
MF-LF
402 2

R8591

R85901

10%
50V
CERM
402

GPUISENS_RC

Q8520

CRITICAL

5%
1/16W
MF-LF
2 402

10%
6.3V
CERM
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

10%
50V
CERM 2
402

1%
1/16W
MF-LF
402

1uF

R8510

PGND 10

470pF

C8590

20.0K2

GPUVCORE_ISEN

THRML
PAD
17

R8593

GPUVCORE_PHASE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

1%
1/16W
MF-LF
402

10%
2 16V
X5R
603

20%
2 16V
POLY
CASED2E-SM

1 2 3

C8508 1

C8532
1uF

33uF

HAT2168H

GPUVCORE_COMP_R

57.6K

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

8 VO

5%
50V
CERM 2
402

C8531

LFPAK

BOOT 13
PHASE 15
ISEN 9

6 FB

15pF

1%
1/16W
MF-LF
2 402

GPUVCORE_FB

GPUVCORE_BOOT

LG 11
1

20%
2 6.3V
X5R
402

UG 14

7 FSET

GPUVCORE_EN

0.22UF

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

QFN

1 VIN

C8530

10%
2 16V
X5R
603

C8509

GPUVCORE_UG

ISL6269

GPUVCORE_FCCM
65 62

5%
1/16W
MF-LF
402 2

2
VCC

CRITICAL
65

1uF

2.2UF

R8598

CRITICAL

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

C8502 1
5%
1/16W
MF-LF
2 402

2
2

R8594

470pF

0603-LF

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

R8504

C8598

10KOHM-5%

NO STUFF

C8500 1

PP5V_S0_GPUVCORE_VCC

1%
1/16W
MF-LF
402 2

NO STUFF

10%
16V 2
X5R
603

PP3V3_S0

R8597

1uF

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 66 65

CRITICAL

R85961

GPU VCore Supply

PP5V_S5
4 PPBUS_G3H
66

67 66 65 64 63 61 51 46 25 5

C8541

22UF

330uF

20%
2 6.3V
CERM
805

(GPUVCORE_FB)

C8543

20%
2 2V
POLY
CASE-D2-SM

<Rc>
R8523
12.4K2

Vout(low) = 0.6V * (1 + Ra / Rb)

Vout(high) = 0.6V * (1 + Ra / Req)
Req = Rb || Rc

Back-Bias Positive Supply

Back-bias positive supply provides VDDC + 0.5V when active.
When inactive, provides VDDC to BBP pins.
NOTE: BBP tracks VDDC based on GPU voltage GPIO.
76 71 70 66 54 5

Q8575
TSOP-LF

GPUBB_EN

2.2uF

24.9K

20%
6.3V
CERM1 2
603

GPUBBP_ADJ
NO STUFF

22UF

20%
6.3V 2
CERM
805

<Rb>
R8556

R8554
174K

16.2K

1%
1/16W
MF-LF
2 402

NO STUFF

Q8554
2N7002

GPU_VCORE_HIGH

SOT23-LF

C8557

Pull-up voltage must be high enough to

satisfy BBP FET Vgs (where Vs = 1.2V)
SI3446DV max Vgs is 1.6V
Vin must be > 2.8V

R8561
76

GPU_GENERICD

5%
1/16W
MF-LF
402

2N7002

GPUBB_EN

68.1K

GPUBBN_CAPP
1

SOT23-LF

1%
1/16W
MF-LF
402 2

8
4

SHDN_L

CAP+

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

C8581

IN
FB

OUT

Vout = -Vin * Rb / Ra
<Rb> Recommended values:
1
R8588
11.3K
Ra = Vin / 50 uA
1%
1/16W
MF-LF
Rb = -Vout / 50 uA
402

GPUBBN_FB

U8580

MAX1673
SOI

C8570

0.0022uF

10%
2 50V
CERM
402

CAP-

LIN/SKIP_L
GND
7

PNBB_S0_GPU
1

C8589

SYNC_MASTER=M1_MLB

20%
6.3V
2 CERM
805

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

10K

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

5%
1/16W
MF-LF
402 2

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

SYNC_DATE=02/10/2006

66 71

Vout = -0.55V
125mA max output
(Regulator limit)

22UF

R85601

GPU (M56) Core Supplies

CRITICAL

GPUBBN_CAPN
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

Q8570

GPUBB_EN

<Ra>
R85871

20%
6.3V
2 CERM1
603

GPU_BB_CTL

PP3V3_S0_GPU

2.2uF

GPUBB_EN_L

SOT-363

Back-bias negative supply provides VSS - 0.55V when active.

When inactive, provides VSS to BBN pins.

5%
1/16W
MF-LF
402 2

10%
16V
CERM-X5R 2
402

Back-Bias Negative Supply

20%
6.3V 2
X5R
603

100K

10uF

R8570

SOT-363

0.022uF

Q8523

C8580 1

PP5V_S0

For proper M56 power sequence, this

pull-up must be powered before VCore

10K

76 73 70 66

56 54 52 47 42 36 31 25 5 4
80 79 78 67 66 65 61 60 57

C8523

5%
1/16W
MF-LF
402 2

Vout(low) = 0.59V * (1 + Ra/Rb)

Vout(high) = 0.59V * (1 + Ra/Req)
Req = Rb || Rc

R8524

20%
6.3V
2 CERM
805

GPUBBP_ADJ_LOW

GPU_VCORE_LOW
1

22UF

1%
1/16W
MF-LF
2 402

<Rc>

76 73

66 71

Vout = (1.58V /) 1.50V

180mA max output
(LDO limit)

C8556 1

1%
1/16W
MF-LF
2 402

10%
16V
CERM 2
402

2N7002DW-X-F

GPU_VCORE_HIGH_RC

2N7002DW-X-F

<Ra>
R8555

0.01UF

GND
2

C8551 1

5%
1/16W
MF-LF
402

3
D

C8555 1

10K

Q8523

R8525
1

PPBB_S0_GPU

SOT23-6-LF
1 VIN
VOUT 6
4 PG
3 EN
ADJ 5

GPU_VCORE_HIGH

U8550

FAN2558

PP3V3_S0_GPU

76 73 70 66

10K

5%
1/16W
MF-LF
402 2

GPUBB_EN_L

R85261

1
2

GPUVCORE_FB_LOW

1%
1/16W
MF-LF
402

PP3V3_S0_GPU

SI3446DV

PPVCORE_S0_GPU

CRITICAL

76 73 70 66

06
86

Page Notes
Power aliases required by this page:
- =PP1V5_GPU_VDD15
- =PP1VR1V3_GPU_VCORE
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

U8400
M56P
BGA
(7 OF 7)

PPBB_S0_GPU

C8690

100mA (Preliminary)
1

22UF

20%
6.3V
CERM 2
805

76 70 66 54 5

PPVCORE_S0_GPU

C8600

C8691
1uF

10%
6.3V
2 CERM
402

C8692
0.1uF

10%
16V
2 X5R
402

14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI

22UF

20%
6.3V
CERM 2
805

C8601 1

22UF

C8604
1uF

20%
6.3V
CERM 2
805

10%
6.3V
2 CERM
402

C8611

1uF

10%
6.3V
2 CERM
402

1uF

10%
6.3V
2 CERM
402

C8605

C8606
1uF

10%
6.3V
2 CERM
402

C8612

1uF

10%
6.3V
2 CERM
402

C8613

1uF

10%
6.3V
2 CERM
402

1uF

10%
6.3V
2 CERM
402

C8607

C8614

1uF

10%
6.3V
2 CERM
402

1uF

10%
6.3V
2 CERM
402

C8608

C8615

1uF

10%
6.3V
2 CERM
402

1uF

10%
6.3V
2 CERM
402

C8609

C8610
1uF

10%
6.3V
2 CERM
402

C8616
1uF

10%
6.3V
2 CERM
402

R86301
0

5%
1/10W
MF-LF
603 2

K18
M23
V10
AC14

OMIT
BBP

BBN

VDDC
(1.0V/1.2V)

PPVCORE_S0_GPU_VDDCI
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

C8630 1
22UF

20%
6.3V
CERM 2
805

75 74 72 66

PP1V8_S0_GPU

C8631
1uF

10%
6.3V
2 CERM
402

C8632
1uF

10%
6.3V
2 CERM
402

C8633
1uF

10%
6.3V
2 CERM
402

C8634
1uF

10%
6.3V
2 CERM
402

2.0A @ 500MHz 1.8V GDDR3

C8650
22UF

20%
6.3V 2
CERM
805

C8651

22UF

20%
6.3V 2
CERM
805

C8652
22UF

20%
6.3V 2
CERM
805

C8653
22UF

20%
6.3V 2
CERM
805

C8655
1uF

10%
2 6.3V
CERM
402

C8661
1uF

C8667

C8668
1uF

10%
6.3V
2 CERM
402

C8673
1uF

10%
6.3V
2 CERM
402

C8662

10%
6.3V
2 CERM
402

1uF

10%
6.3V
2 CERM
402

C8656
1uF

10%
2 6.3V
CERM
402

C8674
1uF

10%
6.3V
2 CERM
402

C8679
1uF

10%
6.3V
2 CERM
402

C8680
1uF

10%
6.3V
2 CERM
402

C8657
1uF

10%
2 6.3V
CERM
402

C8663
1uF

10%
6.3V
2 CERM
402

C8669
1uF

10%
6.3V
2 CERM
402

C8675
1uF

10%
6.3V
2 CERM
402

C8681
1uF

10%
6.3V
2 CERM
402

C8658
1uF

10%
2 6.3V
CERM
402

C8664
1uF

10%
6.3V
2 CERM
402

C8670
1uF

10%
6.3V
2 CERM
402

C8676
1uF

10%
6.3V
2 CERM
402

C8682
1uF

10%
6.3V
2 CERM
402

C8659
1uF

10%
2 6.3V
CERM
402

C8665
1uF

10%
6.3V
2 CERM
402

C8671
1uF

10%
6.3V
2 CERM
402

C8677
1uF

10%
6.3V
2 CERM
402

C8683
1uF

10%
6.3V
2 CERM
402

C8660
1uF

10%
2 6.3V
CERM
402

C8666
1uF

10%
6.3V
2 CERM
402

C8672
1uF

10%
6.3V
2 CERM
402

C8678
1uF

10%
6.3V
2 CERM
402

K15
R10
Y23
AC17

C8697

0.1uF

10%
16V 2
X5R
402

C8696 1
1uF

10%
6.3V 2
CERM
402

100mA (Preliminary)
P14
P18
P19
R15
R17
R18
R19
T16
T17
T18
U15
U16
U17
V14
V15
V16
V18
W14
W15
W19
AC11
AC12
AD11

MEMORY & CORE POWER / GROUND

70 66

K14
P16
T14
T23
U19
W10
W17
A3
A9
A12
A15
A18
A21
A24
A30
C1
C32
F32
H13
H19
J1
J10
J11
J13
J18
J19
J20
J32
K11
K13
K19
K20
K21
K24
L23
L24
L32
M1
M10
N9
N10
P8
P9
P10
R1
R9
V1
Y8
Y9
Y10
AA1

VDDCI
(1.0V/1.2V)

VSS
VDDR1
(1.8V/2.0V)

K23
A2
A8
A11
A13
A16
A19
A22
A25
A31
B1
B32
C4
C5
C6
C9
C10
C15
C18
C20
C21
C24
C27
D11
D30
E5
E8
E9
E12
E13
E16
E19
E25
E28
E30
E32
F3
F6
F10
F13
F15
F16

F18
F19
F21
F22
F24
F27
F30
G13
G16
G19
G20
G21
G22
G25
H1
H5
H7
H16
H20
H21
H28
H32
J3
J6
J9
J12
J16
J21
J24
J28
J30
K10
K12
K16
K17
K27
K30
L1
L6
L7
L29
M3

VSS

C8695
22UF

20%
2 6.3V
CERM
805

PNBB_S0_GPU

66 70

M6
M7
M8
M9
M24
M28
M32
N3
N7
N8
P1
P5
P6
P7
P15
P17
R3
R6
R14
R16
T10
T15
T19
U1
U5
U6
U7
U8
U9
U10
U14
U18
V3
V6
V17
V19
W16
W18
Y1
Y5
Y6
Y7
AA4
AA6
AC9
AC10
AD6
AD7
AD8
AD9
AD10
AD13
AD14
AD15
AD16
AD17
AE8
AE14
AE15
AE16
AE17
AF14
AF16
AG11
AG16
AG23
AH10
AH11
AH16
AJ10
AK16
AL1
AL13
AM2
AM13

ATI M56 Core Power

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Page Notes

74 72 71 66
75

PP1V8_S0_GPU

B
R87101

R8712

40.2

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

FB_A_DQ<0>
FB_A_DQ<1>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<4>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<14>
FB_A_DQ<15>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<18>
FB_A_DQ<19>
FB_A_DQ<20>
FB_A_DQ<21>
FB_A_DQ<22>
FB_A_DQ<23>
FB_A_DQ<24>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<28>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<31>
FB_A_DQ<32>
FB_A_DQ<33>
FB_A_DQ<34>
FB_A_DQ<35>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<44>
FB_A_DQ<45>
FB_A_DQ<46>
FB_A_DQ<47>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<53>
FB_A_DQ<54>
FB_A_DQ<55>
FB_A_DQ<56>
FB_A_DQ<57>
FB_A_DQ<58>
FB_A_DQ<59>
FB_A_DQ<60>
FB_A_DQ<61>
FB_A_DQ<62>
FB_A_DQ<63>
GPU_MVREFD0
GPU_MVREFS0

R87111 C8711 1
100

R8713
100

0.1uF

1%
1/16W
MF-LF
402 2

C31
C30
A27
A28

C8713
0.1uF

1%
1/16W
MF-LF
2 402

10%
16V 2
X5R
402

M31
M30
L31
L30
H30
G31
G30
F31
M27
M29
L28
L27
J27
H29
G29
G27
M26
L26
M25
L25
J25
G28
H27
H26
F26
G26
H25
H24
H23
H22
J23
J22
E23
D22
D23
E22
E20
F20
D19
D18
B19
B18
C17
B17
C14
B14
C13
B13
D17
E18
E17
F17
E15
E14
F14
D13
H18
H17
G18
G17
G15
G14
H14
J14

M56P

BGA
(3 OF 7)

BGA
(4 OF 7)

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15

MVREFD_0
MVREFS_0
(1.8V/
VDDRH0 2.0V)
VSSRH0

FB_A_MA<0>
FB_A_MA<1>
FB_A_MA<2>
FB_A_MA<3>
FB_A_MA<4>
FB_A_MA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>
NC_FB_A_MA12
FB_A_BA<2>
FB_A_BA<0>
FB_A_BA<1>

D26
F28
D28
D25
E24
E26
D27
F25
C26
B26
D29
B27
E27
E29
B25
C25

DQMA_0*
DQMA_1*
DQMA_2*
DQMA_3*
DQMA_4*
DQMA_5*
DQMA_6*
DQMA_7*

H31
J29
J26
G23
E21
B15
D14
J17

FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>
FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>

QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7

J31
K29
K25
F23
D20
B16
D16
H15

FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>

QSA_0*
QSA_1*
QSA_2*
QSA_3*
QSA_4*
QSA_5*
QSA_6*
QSA_7*

K31
K28
K26
G24
D21
C16
D15
J15

FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>
FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>

CLKA0
CLKA0*

D31
E31

FB_A_CLK_P<0>
FB_A_CLK_N<0>

CSA0_0*
CSA0_1*

B29
C28

FB_A_CS_L<0>

OUT

75
74

OUT

CKEA0

B30

FB_A_CKE<0>

OUT

RASA0*

B28

FB_A_RAS_L<0>

OUT

CASA0*

C29

FB_A_CAS_L<0>

OUT

WEA0*

B31

FB_A_WE_L<0>

OUT

ODTA0

F29

TP_FB_A_ODT<0>

OUT

CLKA1
CLKA1*

B20
C19

FB_A_CLK_P<1>
FB_A_CLK_N<1>

CSA1_0*
CSA1_1*

B23
C23

FB_A_CS_L<1>

OUT

75 74 72 71 66

PP1V8_S0_GPU

R87201

R8722

40.2

CKEA1

C22

FB_A_CKE<1>

OUT

RASA1*

B24

FB_A_RAS_L<1>

OUT

CASA1*

B22

FB_A_CAS_L<1>

OUT

WEA1*

B21

FB_A_WE_L<1>

OUT

ODTA1

D24

TP_FB_A_ODT<1>

OUT

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

GPU_MVREFD1
GPU_MVREFS1

R87211 C8721
100
1%
1/16W
MF-LF
402 2

10%
2 16V
X5R
402

40.2

FB_B_DQ<0>
FB_B_DQ<1>
FB_B_DQ<2>
FB_B_DQ<3>
FB_B_DQ<4>
FB_B_DQ<5>
FB_B_DQ<6>
FB_B_DQ<7>
FB_B_DQ<8>
FB_B_DQ<9>
FB_B_DQ<10>
FB_B_DQ<11>
FB_B_DQ<12>
FB_B_DQ<13>
FB_B_DQ<14>
FB_B_DQ<15>
FB_B_DQ<16>
FB_B_DQ<17>
FB_B_DQ<18>
FB_B_DQ<19>
FB_B_DQ<20>
FB_B_DQ<21>
FB_B_DQ<22>
FB_B_DQ<23>
FB_B_DQ<24>
FB_B_DQ<25>
FB_B_DQ<26>
FB_B_DQ<27>
FB_B_DQ<28>
FB_B_DQ<29>
FB_B_DQ<30>
FB_B_DQ<31>
FB_B_DQ<32>
FB_B_DQ<33>
FB_B_DQ<34>
FB_B_DQ<35>
FB_B_DQ<36>
FB_B_DQ<37>
FB_B_DQ<38>
FB_B_DQ<39>
FB_B_DQ<40>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<43>
FB_B_DQ<44>
FB_B_DQ<45>
FB_B_DQ<46>
FB_B_DQ<47>
FB_B_DQ<48>
FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<51>
FB_B_DQ<52>
FB_B_DQ<53>
FB_B_DQ<54>
FB_B_DQ<55>
FB_B_DQ<56>
FB_B_DQ<57>
FB_B_DQ<58>
FB_B_DQ<59>
FB_B_DQ<60>
FB_B_DQ<61>
FB_B_DQ<62>
FB_B_DQ<63>

R8723

100

0.1uF

1%
1/16W
MF-LF
2 402

10%
16V 2
X5R
402

PP1V8R2V0_S0_GPU_VDDRH1

C8723
0.1uF

10%
2 16V
X5R
402

GPU_TEST_MCLK
GPU_TEST_YCLK
GPU_MEMTEST

B12
C12
B11
C11
C8
B7
C7
B6
F12
D12
E11
F11
F9
D8
D7
F7
G12
G11
H12
H11
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
K9
L9
K5
L4
K4
L5
N5
N6
P4
R4
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
V7
W7
W8
W9
B3
C3
F1
E1
AA5
AA2
AA7

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15

G4
E6
E4
H4
J5
G5
F4
H6
G3
G2
D4
F2
F5
D5
H2
H3

FB_B_MA<0>
FB_B_MA<1>
FB_B_MA<2>
FB_B_MA<3>
FB_B_MA<4>
FB_B_MA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>
NC_FB_B_MA12
FB_B_BA<2>
FB_B_BA<0>
FB_B_BA<1>

DQMB_0*
DQMB_1*
DQMB_2*
DQMB_3*
DQMB_4*
DQMB_5*
DQMB_6*
DQMB_7*

B8
D9
G9
K7
M5
V2
W4
T9

FB_B_DQM_L<0>
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_B_DQM_L<4>
FB_B_DQM_L<5>
FB_B_DQM_L<6>
FB_B_DQM_L<7>

QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7

B9
D10
H10
K6
N4
U2
U4
V8

FB_B_RDQS<0>
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_B_RDQS<4>
FB_B_RDQS<5>
FB_B_RDQS<6>
FB_B_RDQS<7>

QSB_0*
QSB_1*
QSB_2*
QSB_3*
QSB_4*
QSB_5*
QSB_6*
QSB_7*

B10
E10
G10
J7
M4
U3
V4
V9

FB_B_WDQS<0>
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_B_WDQS<4>
FB_B_WDQS<5>
FB_B_WDQS<6>
FB_B_WDQS<7>

CLKB0
CLKB0*

B4
B5

FB_B_CLK_P<0>
FB_B_CLK_N<0>

CSB0_0*
CSB0_1*

D2
E3

MEMORY INTERFACE B

OMIT

U8400

READ STROBE

BOM options provided by this page:

(NONE)

OMIT

WRITE STROBE

Signal aliases required by this page:

(NONE)

U8400

MEMORY INTERFACE A

Power aliases required by this page:

- =PP1V8R2V0_S0_FB_GPU

READ STROBE

WRITE STROBE

MVREFD_1
MVREFS_1
(1.8V/
VDDRH1 2.0V)
VSSRH1
TEST_MCLK
TEST_YCLK
MEMTEST

PP1V8_S0_GPU

75 74 72 71 66

PP1V8R2V0_S0_GPU_VDDRH0

PP1V8_S0_GPU

FERR-220-OHM
1

0402

C8715 1 C8716

C8725 1

1uF

10%
6.3V
CERM 2
402

1uF

10%
6.3V
CERM 2
402

C8726

1uF

10%
6.3V
CERM 2
402

R8730
4.7K

5%
1/16W
MF-LF
2 402

OUT

FB_B_CS_L<0>

OUT

FB_B_CKE<0>

OUT

FB_B_RAS_L<0>

OUT

CASB0*

FB_B_CAS_L<0>

OUT

WEB0*

FB_B_WE_L<0>

OUT

ODTB0

TP_FB_B_ODT<0>

OUT

CLKB1
CLKB1*

N2
P3

FB_B_CLK_P<1>
FB_B_CLK_N<1>

CSB1_0*
CSB1_1*

K2
K3

OUT

FB_B_CS_L<1>

OUT

CKEB1

FB_B_CKE<1>

OUT

RASB1*

FB_B_RAS_L<1>

OUT

CASB1*

FB_B_CAS_L<1>

OUT

WEB1*

FB_B_WE_L<1>

OUT

ODTB1

TP_FB_B_ODT<1>

OUT

FB_DRAM_RST

OUT

DRAM_RST

AA3

74 75

R8733
4.7K

5%
1/16W
MF-LF
402 2

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V

OUT

CKEB0

4.7K

L8725

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V

OUT

RASB0*

R8731
L8715

FERR-220-OHM

OUT

75
71 66
74 72

OUT

5%
1/16W
MF-LF
2 402
1

R8732
243

1%
1/16W
MF-LF
2 402

ATI M56 Frame Buffer I/F

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

ROMCFGID[3..0]

76 73 70 66

0000
0010
0100
0110

PP3V3_S0_GPU
NO STUFF

R88001

10K

5%
1/16W
MF-LF
402 2

TESTIN[0]

TX_PWRS_ENb

TESTIN[1]

TX_DEEMPH_EN

GPU_GPIO_1

IPD

GPU_GPIO_2

TESTIN[2]

Reserved

GPU_GPIO_3

GPU_GPIO_4

R8803

Reserved
DEBUG_ACCESS

GPU_GPIO_5

TESTIN[5]

Reserved

GPU_GPIO_6

TESTIN[6]
TESTIN[7]
TESTWR

GPU_GPIO_8

ROMSO

GPU_GPIO_9

IPD

TP_GPU_GPIO_10
IPD
GPU_GPIO_11
GPU_GPIO_12

IPD

GPU_GPIO_13

IPD

76 73

10K

5%
1/16W
MF-LF
2 402

R8808
10K

5%
1/16W
MF-LF
2 402

GPU_MEM_64M
1

R8813

NO STUFF

GPU_MEM_HYNIX

R8811

10K

5%
1/16W
MF-LF
2 402

R8827
10K

5%
1/16W
MF-LF
2 402

ROMSCK

GPU_VCORE_LOW

76 73 34

GPU_CLK27MSS_IN

GPU_BLON

TP_GPU_GPIO_10

TESTOUT[10]

ROMIDCFG[1]

TESTOUT[11]

NC_GPU_GPIO_18

76 73

NC_GPU_GPIO_19

NC_GPU_GPIO_14
MAKE_BASE=TRUE

PWRCNTL

GPU_VCORE_LOW
MAKE_BASE=TRUE

SS_IN

GPU_CLK27MSS_IN
MAKE_BASE=TRUE

Thm Mon Int

76 73

NC_GPU_GPIO_20

76 73

NC_GPU_GPIO_21

76 73

NC_GPU_GPIO_22

76 73

NC_GPU_GPIO_23

76 73

GPU_MEM_256M

76 73

NC_GPU_GPIO_25

MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE

NC_GPU_GPIO_17

NC_GPU_GPIO_18

73 76

NC_GPU_GPIO_19

73 76

76 73

NC_GPU_GPIO_26

76 73

GPU_MEMID

76 73

NC_GPU_GPIO_28

76 73

NC_GPU_GPIO_29

76 73

NC_GPU_GPIO_30

76 73

NC_GPU_GPIO_31

76 73

NC_GPU_GPIO_32

76 73

NC_GPU_GPIO_33

76 73

NC_GPU_GPIO_34

73 72

NC_FB_A_MA12

73 72

NC_FB_B_MA12

MAKE_BASE=TRUE

Required for debug access

76 73

NC_GPU_GENERICC

Required for debug access

77 73

NC_GPU_VGA_R

Required for debug access

77 73

NC_GPU_VGA_G

77 73

NC_GPU_VGA_B

70 73 76

77 73

TP_GPU_VGA_HSYNC

34 73 76

77 73

TP_GPU_VGA_VSYNC

77 73

NC_GPU_TV_Y

77 73

NC_GPU_TV_C

NO_TEST=TRUE

73 76

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

73 77

NC_GPU_VGA_G

73 77

NC_GPU_VGA_B

73 77

TP_GPU_VGA_HSYNC

73 77

TP_GPU_VGA_VSYNC

73 77

NC_GPU_TV_Y

73 77

NC_GPU_TV_C

73 77

NC_GPU_TV_COMP

73 77

NC_LVDS_U_DATAP<3>

73 77

NC_LVDS_U_DATAN<3>

73 77

NC_LVDS_L_DATAP<3>

73 77

NC_LVDS_L_DATAN<3>

73 77

NC_ATI_DVPCLK

73 76

MAKE_BASE=TRUE
MAKE_BASE=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

73 76

77 73

NC_LVDS_U_DATAN<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GPIO_22

73 76

77 73

NC_LVDS_L_DATAP<3>

NC_GPU_GPIO_23

73 76

77 73

NC_LVDS_L_DATAN<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ATI_DVPCLK
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ATI_DVPCNTL<2..0>

ATI_DVPCNTL<2..0>

NC_ATI_DVPDATA<15..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

GPU_MEMID

73 76

NC_GPU_VGA_R

NO_TEST=TRUE

73 76

76 73

73 76

NC_GPU_GENERICC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_21

73 76

NC_GPU_GENERICB

NO_TEST=TRUE

NC_LVDS_U_DATAP<3>

NC_GPU_GPIO_26

NC_GPU_GENERICA

NO_TEST=TRUE

NC_GPU_TV_COMP

76 73

72 73

NO_TEST=TRUE

77 73

73 76

72 73

NC_FB_B_MA12
NO_TEST=TRUE

MAKE_BASE=TRUE

GPU_MEM_256M

73 76

NC_FB_A_MA12
NO_TEST=TRUE

NC_GPU_GENERICB

73 76

NC_ATI_ROMCS_L
NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GENERICA

NO_TEST=TRUE

NC_GPU_XTALOUT
NO_TEST=TRUE

NC_GPU_GPIO_20

NC_GPU_GPIO_25

34 73 76

NO_TEST=TRUE

MAKE_BASE=TRUE

76 73

MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE

NC_ATI_ROMCS_L

76 73

ROMIDCFG[2]

MAKE_BASE=TRUE

76 73

73 76

MAKE_BASE=TRUE

TESTIN[8]

NC_GPU_GPIO_17

NC_GPU_XTALOUT

Required for debug access

ROMIDCFG[3]

TESTIN[9]

76 73

73 76 78

MAKE_BASE=TRUE

TESTOUT[8]
ROMIDCFG[0]

GPU_CLK27M

MAKE_BASE=TRUE

Reserved

TESTOUT[9]

GPU_CLK27M

MAKE_BASE=TRUE

Renamed signals

Reserved

ROMSI

NC_GPU_GPIO_14

76 73 70

76 73

5%
1/16W
MF-LF
2 402

R8805

Unused signals

TESTIN[3]
TESTIN[4]

IPD

ENA_BL

76 73

10K

NO STUFF
1

76 73 34

VDD_VCL

GPU_BLON

78 76 73

NO STUFF
1

R88241

10K

5%
1/16W
MF-LF
402 2

Straps

IPD

GPU_MEM_256M

R88121

10K

5%
1/16W
MF-LF
2 402

GPU_GPIO_0

GPU_MEM_256M

5%
1/16W
MF-LF
402 2

10K

R88091

10K

R8801

Misc

NO STUFF

R88061

5%
1/16W
MF-LF
402 2

GPU_DEEPMH_EN

TestBus

NO STUFF

R88041

128MB
256MB
64MB
Reserved

10K

Serial ROM

NO STUFF

R88021

=
=
=
=

ATI_DVPDATA<15..0>
NO_TEST=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE

NC_GPU_GPIO_28

73 76

NC_GPU_GPIO_29

73 76

NC_GPU_GPIO_30

73 76

NC_GPU_GPIO_31

73 76

NC_GPU_GPIO_32

73 76

NC_GPU_GPIO_33

73 76

NC_GPU_GPIO_34

73 76

Required for debug access

TP_ATI_DVPDATA<23..16>

ATI_DVPDATA<23..16>

MAKE_BASE=TRUE

Also required: GPIO10 - GPIO13

76 73 70 66

PP3V3_S0_GPU

R93901 R93911
4.7K

5%
1/16W
MF-LF
402 2

77
77

4.7K

5%
1/16W
MF-LF
402 2

GPU_DDC_B_CLK
GPU_DDC_B_DATA

GPU Straps
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

C8903
0.1uF

10%
2 16V
X5R
402

C8904

0.1uF

10%
2 16V
X5R
402

M12 VDD5
V2 VDD6
V11 VDD7

L8910

FERR-220-OHM
1

PP1V8_S0_FB_A0_VDDA0

K1 VDDA0
K12 VDDA1

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V

0402

L8915

FERR-220-OHM
1

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V

0402

Connect to designated pin, then GND

72 71 66
75 74

C8910
0.1uF

PP1V8_S0_FB_A0_VDDA1

C8915

0.1uF

10%
2 16V
X5R
402
U8900.J12

10%
2 16V
X5R
402
U8900.J1

PP1V8_S0_GPU

C8920 1
22UF

20%
6.3V 2
CERM
805

C8921
0.1uF

C8922

0.1uF

C8923
0.1uF

10%
2 16V
X5R
402

C8924
0.1uF

10%
2 16V
X5R
402

C8925

0.1uF

C8926
0.1uF

10%
2 16V
X5R
402

A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4
C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9
J4 VDDQ10
J9 VDDQ11
N1 VDDQ12
N4 VDDQ13
N9 VDDQ14
N12 VDDQ15

R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20

R8930

R8932

2.37K

1%
1/16W
MF-LF
402 2

FB_A0_VREF0

V12

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
1

R8931
5.49K

R89421

121

R8941
1K

5%
1/16W
MF-LF
2 402

74 72

121

R8945
60.4

1%
1/16W
MF-LF
2 402

121

OUT

74 72

74 72
74 72

IN
IN

U8900

DM0

FBGA

DM1

(1 OF 2)

DM2
DM3

N10

DQ0

B2
B3

FB_A_CKE<0>
FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_CS_L<0>
FB_A_WE_L<0>
FB_A_CAS_L<0>
FB_A_RAS_L<0>

H9
J11

M9
K4
H2
K3
L4
K2
M4
K11
L9

J10
F4
H4
F9
H10
A4
A9
V4
V9

FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>

D3
D10
P10
P3

FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>

R8948
243

1%
1/16W
MF-LF
402 2

R8949
100

NC
NC

A7
A8/AP
A9
A10
A11
CKE
CK
CK*

DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10

CS*
WE*
CAS*
RAS*

DQ11
DQ12
DQ13
DQ14

ZQ
MF

DQ15
DQ16

SEN

DQ17

RESET
RDQS0
RDQS1
RDQS2
RDQS3

DQ18
DQ19
DQ20
DQ21
DQ22

WDQS0

D11
P11

WDQS1

DQ25

WDQS2
WDQS3

DQ26
DQ27
DQ28

G9
G4

DQ23
DQ24

FB_A_BA<0>
FB_A_BA<1>
FB_A_BA<2>

A4
A5

BA0
BA1

BA2

RFU1

RFU2

DQ29
DQ30
DQ31

E3
E10
N3

C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

10%
2 16V
X5R
402

Connect to designated pin, then GND

75 74 72 71 66

C8960
0.1uF

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V

0402

VSSQ3 B12
VSSQ4 D1
VSSQ5 D4

M12 VDD5
V2 VDD6
V11 VDD7

C8965

0.1uF

10%
2 16V
X5R
402
U8900.J1

10%
2 16V
X5R
402
U8900.J12

PP1V8_S0_GPU

VSSQ9 G11
VSSQ10 L2
VSSQ11 L11

C8970 1
22UF

20%
6.3V 2
CERM
805

VSSQ12 P1
VSSQ13 P4
VSSQ14 P9

C8971
0.1uF

C8972

0.1uF

C8973
0.1uF

10%
2 16V
X5R
402

C8974
0.1uF

10%
2 16V
X5R
402

C8975

0.1uF

C8976
0.1uF

10%
2 16V
X5R
402

VSSQ17 T4
VSSQ18 T9
VSSQ19 T12

C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9
J4 VDDQ10
J9 VDDQ11
N1 VDDQ12

R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20

R8980

R8982

2.37K

1%
1/16W
MF-LF
402 2

FB_A1_VREF0

V12

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

FB_A1_VREF1
1

R89901

R89921

121

R8991

74 72

72
74 72

BI
BI
BI

IN
OUT

OUT

72
74 72

R89941

R8993
121

74 72
74 72

OUT

IN
IN

R8995

1%
1/16W
MF-LF
2 402

VSS5
VSS6
VSS7

VSSA0

VSSA1

J12

VSSQ0

VSSQ1
VSSQ2

B4
B9

VSSQ3
VSSQ4

B12

VSSQ5
VSSQ6
VSSQ7

VSSQ9
VSSQ10

G11
L2

VSSQ11

L11

VSSQ12
VSSQ13

P1
P4

VSSQ14
VSSQ15

VSSQ19

D1
D4
D12
G2

VSSQ17
VSSQ18

BOM options provided by this page:

(NONE)

V10

VSSQ8

VSSQ16

Signal aliases required by this page:

(NONE)

L1
L12

P12
T1
T4
T9
T12

10%
2 16V
X5R
402

R8997
121

CRITICAL
OMIT

1%
1/16W
MF-LF

2 402

U8950

DM0

FBGA

DM1

A2
A3

(1 OF 2)

DM2
DM3

N10

DQ0

B2
B3

FB_A_CKE<1>
FB_A_CLK_P<1>
FB_A_CLK_N<1>
FB_A_CS_L<1>
FB_A_WE_L<1>
FB_A_CAS_L<1>
FB_A_RAS_L<1>

H9
J11

M9
K4
H2
K3
L4
K2
M4
K11
L9

J10
F4
H4
F9
H10
A4
A9
V4
V9

FB_DRAM_RST
FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>

D3
D10
P10
P3

FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>
FB_A_BA<0>
FB_A_BA<1>
FB_A_BA<2>

R8999
100

NC
NC

A7
A8/AP
A9
A10
A11
CKE

DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

CK
CK*

DQ9
DQ10

CS*
WE*
CAS*

DQ11

RAS*

DQ12
DQ13
DQ14

ZQ
MF

DQ15
DQ16

SEN

DQ17

RESET

DQ18
DQ19

RDQS0
RDQS1

DQ20
DQ21

RDQS2
RDQS3

DQ22

WDQS0

D11
P11

WDQS1

DQ25

WDQS2
WDQS3

DQ26
DQ27
DQ28

G9
G4

A4
A5

DQ23
DQ24

1%
1/16W
MF-LF
402 2

G12

0.1uF

K10

243

5%
1/16W
MF-LF
2 402

VSS3
VSS4

C8983

K9
H11

R8998

A10
G1

VDDQ21

FB_A_MA<0>
FB_A_MA<1>
FB_A_MA<2>
FB_A_MA<3>
FB_A_MA<4>
FB_A_MA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>

VSS1
VSS2

1%
1/16W
MF-LF
402 2

60.4

1%
1/16W
MF-LF
2 402

(2 OF 2)

VSS0

60.4

1%
1/16W
MF-LF
402 2
1

FBGA

R89961

121

FB_A1_ZQ
FB_A1_MF
FB_A1_SEN

75 74 72
72

10%
2 16V
X5R
402

1%
1/16W
MF-LF
402 2

C8981
0.1uF

5.49K

121

1%
1/16W
MF-LF
402 2

R8983

U8950

Power aliases required by this page:

- =PP1V8_S0_FB_VDD
- =PP1V8_S0_FB_VDDQ

H1 VREF0
H12 VREF1

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

FB_A_DQ<0>
FB_A_DQ<1>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<4>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<15>
FB_A_DQ<14>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<19>
FB_A_DQ<16>
FB_A_DQ<18>
FB_A_DQ<17>
FB_A_DQ<23>
FB_A_DQ<21>
FB_A_DQ<20>
FB_A_DQ<22>
FB_A_DQ<24>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<28>
FB_A_DQ<31>

A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4

N4 VDDQ13
N9 VDDQ14
N12 VDDQ15

VSSQ15 P12
VSSQ16 T1

FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>

A2 VDD0
A11 VDD1
F1 VDD2
F12 VDD3
M1 VDD4

K1 VDDA0
K12 VDDA1

PP1V8_S0_FB_A1_VDDA1

5%
1/16W
MF-LF
2 402

A2
A3

C8954

0.1uF

10%
2 16V
X5R
402

FERR-220-OHM

5.49K

C8953
0.1uF

L8965

VSSQ0 B1
VSSQ1 B4
VSSQ2 B9

R8981

K10

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V

K9
H11

FB_DRAM_RST

10%
2 16V
X5R
402

VDDQ21

FB_A_MA<0>
FB_A_MA<1>
FB_A_MA<2>
FB_A_MA<3>
FB_A_MA<4>
FB_A_MA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>

0.1uF

PP1V8_S0_FB_A1_VDDA0

0402

CRITICAL
OMIT

1%
1/16W
MF-LF
2 402

FB_A0_ZQ
FB_A0_MF
FB_A0_SEN
75 74 72

1%
1/16W
MF-LF
402 2

K4J52324QC-BC20

R8943

C8952

FERR-220-OHM

VSSA0 J1
VSSA1 J12

NOTE: U8900 DQ0-7 MUST connect to GPU

DQA0-7 or DQA8-15. Bits can be swapped
within byte-lane, but software must know
how these bits are mapped for GPU to support
GDDR3 vendor/device identification scheme.
1
R8947

MFHIGH

74 72

1%
1/16W
MF-LF
402 2

L8960

10%
2 16V
X5R
402

16MX32-GDDR3-500MHZ

74 72

60.4

1%
1/16W
MF-LF
402 2

VSS6 V3
VSS7 V10

VSSQ6 D9
VSSQ7 D12
VSSQ8 G2

0.1uF

20%
6.3V 2
CERM
805

0.1uF

MFHIGH

74 72

R89461

121

VSS3 G12
VSS4 L1
VSS5 L12

C8951

22UF

C8933

MFHIGH

74 72

R89441

1%
1/16W
MF-LF
402 2

10%
2 16V
X5R
402

1%
1/16W
MF-LF
402 2

121

1%
1/16W
MF-LF
402 2

C8931
0.1uF

5.49K

1%
1/16W
MF-LF
402 2

R89401

R8933

C8950 1

H1 VREF0
H12 VREF1

FB_A0_VREF1

(2 OF 2)

K4J52324QC-BC20

C8902
0.1uF

10%
2 16V
X5R
402

20%
6.3V 2
CERM
805

VSS0 A3
VSS1 A10
VSS2 G1

MFHIGH

0.1uF

FBGA

16MX32-GDDR3-500MHZ

C8901

22UF

U8900

Page Notes

CRITICAL
OMIT

PP1V8_S0_GPU

MFHIGH

C8900 1

A2 VDD0
A11 VDD1
F1 VDD2
F12 VDD3
M1 VDD4

K4J52324QC-BC20

75 74 72 71 66

16MX32-GDDR3-500MHZ

CRITICAL
OMIT

PP1V8_S0_GPU

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

72 71 66
75 74

MFHIGH

BA0
BA1

BA2

RFU1

RFU2

DQ29
DQ30
DQ31

E3
E10
N3

C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>
FB_A_DQ<32>
FB_A_DQ<34>
FB_A_DQ<33>
FB_A_DQ<35>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<46>
FB_A_DQ<44>
FB_A_DQ<47>
FB_A_DQ<45>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<55>
FB_A_DQ<54>
FB_A_DQ<53>
FB_A_DQ<60>
FB_A_DQ<59>
FB_A_DQ<61>
FB_A_DQ<57>
FB_A_DQ<62>
FB_A_DQ<56>
FB_A_DQ<63>
FB_A_DQ<58>

GDDR3 Frame Buffer A

BI
BI

SYNC_MASTER=M1_MLB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

5%
1/16W
MF-LF
2 402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

06
86

C9003
0.1uF

10%
2 16V
X5R
402

C9004

0.1uF

10%
2 16V
X5R
402

M12 VDD5
V2 VDD6
V11 VDD7

L9010

FERR-220-OHM
1

PP1V8_S0_FB_B0_VDDA0

K1 VDDA0
K12 VDDA1

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V

0402

L9015

FERR-220-OHM
1

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V

0402

Connect to designated pin, then GND

72 71 66
75 74

C9010
0.1uF

PP1V8_S0_FB_B0_VDDA1

C9015

0.1uF

10%
2 16V
X5R
402
U9000.J1

10%
2 16V
X5R
402
U9000.J12

PP1V8_S0_GPU

C9020 1
22UF

20%
6.3V 2
CERM
805

C9021
0.1uF

10%
2 16V
X5R
402

C9022

0.1uF

C9023
0.1uF

10%
2 16V
X5R
402

C9024
0.1uF

10%
2 16V
X5R
402

C9025

0.1uF

C9026
0.1uF

10%
2 16V
X5R
402

A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4
C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9
J4 VDDQ10
J9 VDDQ11
N1 VDDQ12
N4 VDDQ13
N9 VDDQ14
N12 VDDQ15

R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20

R9030

R9032

2.37K

1%
1/16W
MF-LF
402 2

FB_B0_VREF0

V12

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
1

R9031
5.49K

R90421

121

R9041
1K

5%
1/16W
MF-LF
2 402

75 72

1%
1/16W
MF-LF
2 402

OUT

75 72

75 72
75 72

IN
IN

22UF

20%
6.3V 2
CERM
805

VSSQ12 P1
VSSQ13 P4
VSSQ14 P9

DM0
DM1
DM2
DM3

N10

DQ0

B2
B3

FB_B_CKE<0>
FB_B_CLK_P<0>
FB_B_CLK_N<0>
FB_B_CS_L<0>
FB_B_WE_L<0>
FB_B_CAS_L<0>
FB_B_RAS_L<0>

H9
J11

M9
K4
H2
K3
L4
K2
M4
K11
L9

J10
F4
H4
F9
H10
A4
A9
V4
V9
D3
D10
P10
P3

FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_B_WDQS<0>
FB_B_BA<0>
FB_B_BA<1>
FB_B_BA<2>

A7
A8/AP
A9
A10
A11
CKE
CK
CK*

DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10

CS*
WE*
CAS*
RAS*

DQ11
DQ12
DQ13
DQ14

ZQ
MF

DQ15
DQ16

SEN

DQ17

RESET
RDQS0
RDQS1
RDQS2
RDQS3

DQ18
DQ19
DQ20
DQ21
DQ22

WDQS0

D11
P11

WDQS1

DQ25

WDQS2
WDQS3

DQ26
DQ27
DQ28

G9
G4

NC
NC

A4
A5

DQ23
DQ24

100

0.1uF

10%
2 16V
X5R
402

BA0
BA1

BA2

RFU1

RFU2

DQ29
DQ30
DQ31

E3
E10
N3

C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

C9065

0.1uF

10%
2 16V
X5R
402
U9000.J1

10%
2 16V
X5R
402
U9000.J12

C9072

0.1uF

C9073
0.1uF

10%
2 16V
X5R
402

C9074
0.1uF

10%
2 16V
X5R
402

C9075

0.1uF

C9076
0.1uF

10%
2 16V
X5R
402

VSSQ15 P12
VSSQ16 T1

VSSQ17 T4
VSSQ18 T9
VSSQ19 T12

R9080

R9082

2.37K

1%
1/16W
MF-LF
402 2

FB_B1_VREF0

J4 VDDQ10
J9 VDDQ11
N1 VDDQ12

V12

FB_B1_VREF1
1

R90921

75 72

72
75 72

74 72
75

IN
OUT

OUT

72
75 72

R90941

R9093
121

75 72
75 72

OUT

IN
IN

R9095

1%
1/16W
MF-LF
2 402

VSS5
VSS6
VSS7

VSSA0

VSSA1

J12

VSSQ0

VSSQ1
VSSQ2

B4
B9

VSSQ3
VSSQ4

B12

VSSQ5
VSSQ6
VSSQ7

VSSQ9
VSSQ10

G11
L2

VSSQ11

L11

VSSQ12
VSSQ13

P1
P4

VSSQ14
VSSQ15

VSSQ19

D1
D4
D12
G2

VSSQ17
VSSQ18

BOM options provided by this page:

(NONE)

V10

VSSQ8

VSSQ16

Signal aliases required by this page:

(NONE)

L1
L12

P12
T1
T4
T9
T12

10%
2 16V
X5R
402

R9097
121

CRITICAL
OMIT

1%
1/16W
MF-LF

2 402

U9050

DM0

FBGA

DM1

A2
A3

(1 OF 2)

DM2
DM3

N10

DQ0

B2
B3

FB_B_CKE<1>
FB_B_CLK_P<1>
FB_B_CLK_N<1>
FB_B_CS_L<1>
FB_B_WE_L<1>
FB_B_CAS_L<1>
FB_B_RAS_L<1>

H9
J11

M9
K4
H2
K3
L4
K2
M4
K11
L9

J10
F4
H4
F9
H10
A4
A9
V4
V9

FB_DRAM_RST
FB_B_RDQS<6>
FB_B_RDQS<5>
FB_B_RDQS<4>
FB_B_RDQS<7>

D3
D10
P10
P3

FB_B_WDQS<6>
FB_B_WDQS<5>
FB_B_WDQS<4>
FB_B_WDQS<7>
FB_B_BA<0>
FB_B_BA<1>
FB_B_BA<2>

R9099
100

NC
NC

A7
A8/AP
A9
A10
A11
CKE

DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

CK
CK*

DQ9
DQ10

CS*
WE*
CAS*

DQ11

RAS*

DQ12
DQ13
DQ14

ZQ
MF

DQ15
DQ16

SEN

DQ17

RESET

DQ18
DQ19

RDQS0
RDQS1

DQ20
DQ21

RDQS2
RDQS3

DQ22

WDQS0

D11
P11

WDQS1

DQ25

WDQS2
WDQS3

DQ26
DQ27
DQ28

G9
G4

A4
A5

DQ23
DQ24

1%
1/16W
MF-LF
402 2

G12

0.1uF

K10

243

5%
1/16W
MF-LF
2 402

VSS3
VSS4

C9083

K9
H11

R9098

A10
G1

VDDQ21

FB_B_MA<0>
FB_B_MA<1>
FB_B_MA<2>
FB_B_MA<3>
FB_B_MA<4>
FB_B_MA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>

VSS1
VSS2

1%
1/16W
MF-LF
402 2

60.4

1%
1/16W
MF-LF
2 402

(2 OF 2)

VSS0

60.4

1%
1/16W
MF-LF
402 2
1

FBGA

R90961

121

1%
1/16W
MF-LF
402 2

10%
2 16V
X5R
402

1%
1/16W
MF-LF
402 2

121

C9081
0.1uF

5.49K

FB_B1_ZQ
FB_B1_MF
FB_B1_SEN
72

R9083

U9050

Power aliases required by this page:

- =PP1V8_S0_FB_VDD
- =PP1V8_S0_FB_VDDQ

H1 VREF0
H12 VREF1

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

FB_B_DQ<15>
FB_B_DQ<12>
FB_B_DQ<14>
FB_B_DQ<13>
FB_B_DQ<8>
FB_B_DQ<9>
FB_B_DQ<11>
FB_B_DQ<10>
FB_B_DQ<18>
FB_B_DQ<17>
FB_B_DQ<19>
FB_B_DQ<16>
FB_B_DQ<20>
FB_B_DQ<22>
FB_B_DQ<23>
FB_B_DQ<21>
FB_B_DQ<29>
FB_B_DQ<30>
FB_B_DQ<28>
FB_B_DQ<31>
FB_B_DQ<27>
FB_B_DQ<24>
FB_B_DQ<26>
FB_B_DQ<25>
FB_B_DQ<1>
FB_B_DQ<6>
FB_B_DQ<0>
FB_B_DQ<5>
FB_B_DQ<3>
FB_B_DQ<7>
FB_B_DQ<2>
FB_B_DQ<4>

C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9

R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_B_DQM_L<0>

A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4

N4 VDDQ13
N9 VDDQ14
N12 VDDQ15

5%
1/16W
MF-LF
2 402

FBGA

R9049

C9071

U9000

R9091

(1 OF 2)

1%
1/16W
MF-LF
402 2

C9070 1

A2
A3

243

VSSQ9 G11
VSSQ10 L2
VSSQ11 L11

CRITICAL
OMIT

M12 VDD5
V2 VDD6
V11 VDD7

PP1V8_S0_GPU

5.49K

R9048

R9081

K10

FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_B_RDQS<0>

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V

K9
H11

75 74 72 71 66

C9060
0.1uF

Connect to designated pin, then GND

R9047

FB_DRAM_RST

VDDQ21

FB_B_MA<0>
FB_B_MA<1>
FB_B_MA<2>
FB_B_MA<3>
FB_B_MA<4>
FB_B_MA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>

10%
2 16V
X5R
402

A2 VDD0
A11 VDD1
F1 VDD2
F12 VDD3
M1 VDD4

K1 VDDA0
K12 VDDA1

PP1V8_S0_FB_B1_VDDA1

0402

VSSQ3 B12
VSSQ4 D1
VSSQ5 D4

FB_B0_ZQ
FB_B0_MF
FB_B0_SEN
75 74 72

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

C9054

0.1uF

10%
2 16V
X5R
402

FERR-220-OHM

121

C9053

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V

1%
1/16W
MF-LF
402 2

K4J52324QC-BC20

R9045

10%
2 16V
X5R
402

0.1uF

L9065

VSSQ0 B1
VSSQ1 B4
VSSQ2 B9

R90901

MFHIGH

75 72

0.1uF

PP1V8_S0_FB_B1_VDDA0

0402

10%
2 16V
X5R
402

16MX32-GDDR3-500MHZ

75 72

1%
1/16W
MF-LF
402 2

60.4

1%
1/16W
MF-LF
2 402

C9052

FERR-220-OHM

VSSA0 J1
VSSA1 J12

0.1uF

MFHIGH

75 72

121

L9060

60.4

1%
1/16W
MF-LF
402 2

R9043

VSS6 V3
VSS7 V10

VSSQ6 D9
VSSQ7 D12
VSSQ8 G2

0.1uF

20%
6.3V 2
CERM
805

R90461

121

VSS3 G12
VSS4 L1
VSS5 L12

C9051

22UF

C9033

MFHIGH

75 72

R90441

1%
1/16W
MF-LF
402 2

10%
2 16V
X5R
402

1%
1/16W
MF-LF
402 2

121

1%
1/16W
MF-LF
402 2

C9031
0.1uF

5.49K

1%
1/16W
MF-LF
402 2

R90401

R9033

C9050 1

H1 VREF0
H12 VREF1

FB_B0_VREF1

(2 OF 2)

K4J52324QC-BC20

C9002
0.1uF

10%
2 16V
X5R
402

20%
6.3V 2
CERM
805

VSS0 A3
VSS1 A10
VSS2 G1

MFHIGH

0.1uF

FBGA

16MX32-GDDR3-500MHZ

C9001

22UF

U9000

Page Notes

CRITICAL
OMIT

PP1V8_S0_GPU

MFHIGH

C9000 1

A2 VDD0
A11 VDD1
F1 VDD2
F12 VDD3
M1 VDD4

K4J52324QC-BC20

75 74 72 71 66

16MX32-GDDR3-500MHZ

CRITICAL
OMIT

PP1V8_S0_GPU

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

72 71 66
75 74

MFHIGH

BA0
BA1

BA2

RFU1

RFU2

DQ29
DQ30
DQ31

E3
E10
N3

C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

FB_B_DQM_L<6>
FB_B_DQM_L<5>
FB_B_DQM_L<4>
FB_B_DQM_L<7>
FB_B_DQ<54>
FB_B_DQ<53>
FB_B_DQ<52>
FB_B_DQ<55>
FB_B_DQ<50>
FB_B_DQ<48>
FB_B_DQ<49>
FB_B_DQ<51>
FB_B_DQ<44>
FB_B_DQ<47>
FB_B_DQ<45>
FB_B_DQ<46>
FB_B_DQ<43>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<40>
FB_B_DQ<37>
FB_B_DQ<32>
FB_B_DQ<39>
FB_B_DQ<34>
FB_B_DQ<36>
FB_B_DQ<35>
FB_B_DQ<38>
FB_B_DQ<33>
FB_B_DQ<63>
FB_B_DQ<61>
FB_B_DQ<62>
FB_B_DQ<60>
FB_B_DQ<56>
FB_B_DQ<59>
FB_B_DQ<58>
FB_B_DQ<57>

GDDR3 Frame Buffer B

BI
BI

SYNC_MASTER=M1_MLB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

5%
1/16W
MF-LF
2 402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

06
86

Page Notes
Power aliases required by this page:
- =PP3V3_GPU_GPIOS
- =PP2V5_PVDD
- =PP1V8_GPU_LVDS_PLL
76 73 70 66

Signal aliases required by this page:

- =I2C_GPU_TMDS_SDA - I2C data line for
external TMDS transmitters
- =I2C_GPU_TMDS_SCL - I2C clock line for
external TMDS transmitters

499

1%
1/16W
MF-LF
2 402

BGA
(6 OF 7)

73
73
73
73
73
73
73
73
73
73
73
73
73
73

PP3V3_S0_GPU

Typically <50mA

C9100 1
22UF

20%
6.3V
CERM 2
805

77 76 66 65 62 19 17 5

C9101

1uF

10%
6.3V
2 CERM
402

PP2V5_S0

C9103
1uF

10%
6.3V
2 CERM
402

70mA total for VDD25

C9110

22UF

C9111
1uF

20%
6.3V 2
CERM
805

77 76 66 65 62 19 17 5

C9102

10%
2 6.3V
CERM
402

C9112
0.1uF

10%
2 16V
X5R
402

AE13
AF13
AF9
AG7
AE10
AE9
AF7
AF8
AH6
AF10
AG10
AH9
AJ8
AH8
AG9
AH7
AG8
AA9
AB9
AB10
AC19
AC20
AD18
AD19
AD20
K22
L10
AA10
AC13
AC16
AC18

GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34

22UF

C9116
1uF

20%
6.3V
CERM 2
805

VDD25
(2.5V)

10%
6.3V
2 CERM
402

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

C9120

22UF

C9121
1uF

20%
6.3V
CERM 2
805

76 73 70 66

10%
6.3V
2 CERM
402

C9122
0.1uF

10%
16V
2 X5R
402

FERR-220-OHM Typically <50mA

1
2
PP1V8R3V3_S0_GPU_VDDR5_F

PP3V3_S0_GPU

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

0402

GENERICA
GENERICB
GENERICC
GENERICD

AK22
AF23
AE23
AD23

NC_GPU_GENERICA
NC_GPU_GENERICB
NC_GPU_GENERICC
GPU_GENERICD

PANEL
DIGON
CONTROL VARY_BL

AE11
AD12

GPU_DIGON
GPU_VARY_BL

C9125

22UF

L9130

C9126
1uF

20%
6.3V
CERM 2
805

10%
6.3V
2 CERM
402

C9127
0.1uF

10%
16V
2 X5R
402

AJ5
AK5
AL5
AM5
AE2
AE3
AE4
AE5

VDDR4
(1.8V/3.3V)

PP1V2_S0_GPU_VDDPLL
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

0402

C9130 1
22UF

20%
6.3V 2
CERM
805

20mA
1

C9131
1uF

10%
2 6.3V
CERM
402

C9132

(PP2V5_S0_GPU_PVDD_F)

1uF

10%
2 6.3V
CERM
402

(PP1V0R1V2_S0_GPU_MPVDD)

L9135

VDDPLL (1.2V)

AJ14
AH14

PVDD
PVSS

(2.5V)

MPVDD
MPVSS

(2.5V)

A6
A5

FERR-220-OHM

PP2V5_S0

PP2V5_S0_GPU_PVDD_F
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.5V

0402

73 34

100mA

C9135 1
22UF

20%
6.3V
CERM 2
805

C9136
1uF

10%
6.3V
2 CERM
402

C9137

GPU_CLK27M
NC_GPU_XTALOUT
NC

0.1uF

AL26
AM26

XTALIN
XTALOUT

AG14

PLLTEST

10%
16V
2 X5R
402

0.1uF

10%
16V
X5R 2
402

73
73

R9191
499

1%
1/16W
MF-LF
2 402

73
73
73 78
73
73
73
73
73
73
73
70 73
34 73
73

73
73
73
70

78
78

AK4
AL4

NC
NC

DVPCLK

AG1

NC_ATI_DVPCLK

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2

AF2
AF1
AF3

NC_ATI_DVPCNTL<0>
NC_ATI_DVPCNTL<1>
NC_ATI_DVPCNTL<2>

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11

AG2
AG3
AH2
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AL3
AM3

NC_ATI_DVPDATA<0> 73
NC_ATI_DVPDATA<1> 73
NC_ATI_DVPDATA<2> 73
NC_ATI_DVPDATA<3> 73
NC_ATI_DVPDATA<4> 73
NC_ATI_DVPDATA<5> 73
NC_ATI_DVPDATA<6> 73
NC_ATI_DVPDATA<7> 73
NC_ATI_DVPDATA<8> 73
NC_ATI_DVPDATA<9> 73
NC_ATI_DVPDATA<10> 73
NC_ATI_DVPDATA<11> 73

DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH5
AF6
AE7
AG6

NC_ATI_DVPDATA<12>
NC_ATI_DVPDATA<13>
NC_ATI_DVPDATA<14>
NC_ATI_DVPDATA<15>
TP_ATI_DVPDATA<16>
TP_ATI_DVPDATA<17>
TP_ATI_DVPDATA<18>
TP_ATI_DVPDATA<19>
TP_ATI_DVPDATA<20>
TP_ATI_DVPDATA<21>
TP_ATI_DVPDATA<22>
TP_ATI_DVPDATA<23>

DPLUS
DMINUS

AG12
AH12

ATI_TDIODE_P
ATI_TDIODE_N

ROM

ROMCS*

AC7

NC_ATI_ROMCS_L

TEST

TESTEN

AG22

ATI_TESTEN

THERMAL
DIODE

AB6

VDDR5
(1.8V/3.3V)

AC15

C9191 1

NC0

200-OHM-EMI

PP1V2_S0

NC_DVOVMODE_0
NC_DVOVMODE_1

1uF

L9125

GPU_GPIO_0
GPU_GPIO_1
GPU_GPIO_2
GPU_GPIO_3
GPU_GPIO_4
GPU_GPIO_5
GPU_GPIO_6
GPU_BLON
GPU_GPIO_8
GPU_GPIO_9
TP_GPU_GPIO_10
GPU_GPIO_11
GPU_GPIO_12
GPU_GPIO_13
NC_GPU_GPIO_14
GPU_VCORE_LOW
GPU_CLK27MSS_IN
NC_GPU_GPIO_17

C9117

L9120
0402

ATI_VREFG

VDDR3
(3.3V)

FERR-220-OHM Typically <50mA

1
2
PP1V8R3V3_S0_GPU_VDDR4_F

PP3V3_S0_GPU

AC8
AD4
AD2
AD1
AD3
AC1
AC2
AC3
AB2
AC6
AC5
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7

PP2V5_S0

C9115

76 73 70 66

VREFG
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17

VIP HOST / EXTERNAL TMDS

76 73 70 66

NC_GPU_GPIO_18
NC_GPU_GPIO_19
NC_GPU_GPIO_20
NC_GPU_GPIO_21
NC_GPU_GPIO_22
NC_GPU_GPIO_23
GPU_MEM_256M
NC_GPU_GPIO_25
NC_GPU_GPIO_26
GPU_MEMID
NC_GPU_GPIO_28
NC_GPU_GPIO_29
NC_GPU_GPIO_30
NC_GPU_GPIO_31
NC_GPU_GPIO_32
NC_GPU_GPIO_33
NC_GPU_GPIO_34

GENERAL PURPOSE I/O

77 76 66 65 62 19 17 5

R9190

M56P

BOM options provided by this page:

(NONE)

69 66 65 62 5

U8400

PLL & XTAL

PP3V3_S0_GPU

OMIT

73
73
73

73
73
73
73
73
73
73
73
73
73
73
73

53
53

R9195
1K

5%
1/16W
MF-LF
2 402

L9140

71 70 66 54 5

PPVCORE_S0_GPU

FERR-220-OHM
1

2
0402

PPVCORE_S0_GPU_MPVDD
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

ATI M56 GPIO/DVO/Misc

20mA

SYNC_MASTER=M1_MLB

C9140 1
22UF

20%
6.3V 2
CERM
805

C9141
1uF

10%
2 6.3V
CERM
402

C9142

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

0.1uF

10%
2 16V
X5R
402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Page Notes
Power aliases required by this page:
- =PP2V5_S0_GPU
- =PP1V8R2V5_S0_GPU_LVDDR
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

L9300

FERR-220-OHM
PP2V5_S0_GPU_TPVDD

OMIT

20mA peak

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=2.5V

U8400
C9300

22UF

20%
6.3V 2
CERM
805

L9305

C9301
1uF

10%
2 6.3V
CERM
402

M56P

C9302

BGA
(5 OF 7)

1uF

10%
2 6.3V
CERM
402

AM8
AL8

FERR-220-OHM
1

PP2V5_S0_GPU_TXVDDR

150mA peak

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.5V

0402

C9305

22UF

20%
6.3V
CERM 2
805

L9310

C9306

10%
6.3V
402

2 X5R

1uF

2 CERM

AJ6
AK6
AL6
AM6
AJ7
AK7
AK8
AL7
AM7

C9307
0.1uF
10%
16V
402

FERR-220-OHM

PP2V5_S0_GPU_AVDD

65mA peak

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.5V

0402

C9310

22UF

20%
6.3V 2
CERM
805

L9315

C9311

1uF
10%

2 6.3V
CERM

402

PP2V5_S0_GPU_VDD1DI

C9315

22UF

20%
6.3V 2
CERM
805

0.1uF

AL25
AM25

10%
402

20mA peak

1uF

10%
2 6.3V
CERM
402

TXVSSR

AVDD
(2.5V)

AJ24
AK25

AVSS

AK23

AVSSQ

0402

C9316

TXVDDR
(2.5V)

C9312

2 16V
X5R

FERR-220-OHM
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=2.5V

TPVDD (2.5V)
TPVSS

C9317

L9320

0.1uF

130mA peak

FERR-220-OHM

10%
2 16V
X5R
402

C9320 1

PP2V5_S0_GPU_A2VDD

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.5V

0402

22UF

20%
6.3V
CERM 2
805

L9325

C9321
1uF

10%
6.3V
2 CERM
402

ATI_RSET

C9322

AM23
AL23

VDD1DI (2.5V)
VSS1DI

AL22

RSET

AL16
AM16

0.1uF

10%
16V
2 X5R
402

A2VDD
(2.5V)

AL17
AM17

A2VSS

AL14
AK13

NC_A2VDDQ
A2VSSQ

AJ16
AJ17

VDD2DI (2.5V)
VSS2DI

AK14

R2SET

AE19
AE18

LPVDD (2.5V)
LPVSS

FERR-220-OHM
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=2.5V

C9325

22UF

20%
6.3V
CERM 2
805

0402

20mA peak

C9326
1uF

10%
6.3V
402

2 CERM

C9327
0.1uF
10%
16V
402

L9330

ATI_R2SET

FERR-220-OHM

2 X5R

PP2V5_S0_GPU_LPVDD

20mA peak

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=2.5V

0402

C9330

22UF

20%
6.3V
CERM 2
805

L9345

C9331

10%
6.3V
402

2 CERM

1uF

2 CERM

C9332
1uF

10%
6.3V
402

FERR-220-OHM
1

0402

PP2V5_S0_GPU_LVDDR

200mA peak

MIN_LINE_WIDTH=0.35 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.5V

C9340 1
22UF

20%
6.3V
CERM 2
805

ATI_RSET
ATI_R2SET
1

R9350
499

1%
1/16W
MF-LF
2 402

C9345 1
22UF

20%
6.3V
CERM 2
805

C9341
1uF

10%
6.3V
2 CERM
402

C9342
0.1uF

10%
16V
2 X5R
402

C9346
0.1uF

10%
16V
2 X5R
402

C9347
0.1uF

10%
16V
2 X5R
402

AC21
AC22
AD21
AD22
AE20
AE21
AE22
AF19
AF20
AF17
AF18
AF21
AF22
AG17
AG19
AH17
AH19
AJ19
AK17

LVDDR
(2.5V)

LVDS

PP2V5_S0_GPU_VDD2DI

LVSSR

77
77

R9351

715

INTEGRATED TMDS

GPU_HPD

AF11

DAC (CRT)

0402

DAC2 (TV/CRT2)

HPD1

MONITOR
IDENTIFICATION

PP2V5_S0
76 66 65 62 19 17 5
Sum of peak currents on this page: 605mA

TXCP
TXCM

AM9
AL9

TMDS_CLK_P
TMDS_CLK_N

TX0P
TX0M
TX1P
TX1M
TX2P
TX2M

AL10
AK10
AM11
AL11
AM12
AL12

TMDS_DATA0_P
TMDS_DATA0_N
TMDS_DATA1_P
TMDS_DATA1_N
TMDS_DATA2_P
TMDS_DATA2_N

TX3P
TX3M
TX4P
TX4M
TX5P
TX5M

AJ9
AK9
AJ11
AK11
AJ12
AK12

TMDS_DATA3_P
TMDS_DATA3_N
TMDS_DATA4_P
TMDS_DATA4_N
TMDS_DATA5_P
TMDS_DATA5_N

R
G
B

AK24
AM24
AL24

NC_GPU_VGA_R
NC_GPU_VGA_G
NC_GPU_VGA_B

HSYNC
VSYNC

AJ23
AJ22

TP_GPU_VGA_HSYNC
TP_GPU_VGA_VSYNC

R2
G2
B2

AK15
AM15
AL15

GPU_R2
GPU_G2
GPU_B2

H2SYNC
V2SYNC

AF15
AG15

Y
C

OUT

78 79 86

OUT

78 79 86

OUT

78 79

OUT

78 79

OUT

78 79

GPU_H2SYNC
GPU_V2SYNC

OUT

AJ15
AJ13

NC_GPU_TV_Y
NC_GPU_TV_C

OUT

COMP

AH15

NC_GPU_TV_COMP

TXCLK_UP
TXCLK_UN

AJ21
AK21

LVDS_U_CLK_P
LVDS_U_CLK_N

TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

AG18
AH18
AK20
AJ20
AG20
AH20
AH21
AG21

LVDS_U_DATA_P<0> OUT
LVDS_U_DATA_N<0> OUT
LVDS_U_DATA_P<1> OUT
LVDS_U_DATA_N<1> OUT
LVDS_U_DATA_P<2> OUT
LVDS_U_DATA_N<2> OUT
NC_LVDS_U_DATAP<3>
OUT
NC_LVDS_U_DATAN<3>
OUT

TXCLK_LP
TXCLK_LN

AM18
AL18

LVDS_L_CLK_P
LVDS_L_CLK_N

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

AL19
AK19
AM20
AL20
AM21
AL21
AJ18
AK18

LVDS_L_DATA_P<0> OUT
LVDS_L_DATA_N<0> OUT
LVDS_L_DATA_P<1> OUT
LVDS_L_DATA_N<1> OUT
LVDS_L_DATA_P<2> OUT
LVDS_L_DATA_N<2> OUT
NC_LVDS_L_DATAP<3>
OUT
NC_LVDS_L_DATAN<3>
OUT

AH23
AH22

GPU_DDC_A_CLK
GPU_DDC_A_DATA

DDC1CLK
DDC1DATA

Composite/S-Video

VGA

Y
C

G
R

Component
Y
Pr

OUT

Comp

OUT

78 81

OUT

78 81

78 81
78 81
78 81
78 81
78 81
78 81
73
73

OUT

78 81

OUT

78 81

78 81
78 81
78 81
78 81
78 81
78 81
73
73

ATI M56 Video Interfaces

SYNC_MASTER=M1_MLB

DDC2CLK
DDC2DATA

AG13
AH13

GPU_DDC_B_CLK
GPU_DDC_B_DATA

DDC3CLK
DDC3DATA

AF12
AE12

GPU_DDC_C_CLK
GPU_DDC_C_DATA

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

1%
1/16W
MF-LF
2 402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

06
86

ELECTRICAL_CONSTRAINT_SET

NET_TYPE
SPACING PHYSICAL

LCD (LVDS) INTERFACE

VGA
VGA
VGA

GPU_R2
GPU_G2
GPU_B2

LVDS
LVDS
LVDS
LVDS

LVDS_U_CLK_P
LVDS_U_CLK_N
LVDS_U_DATA_P<2..0>
LVDS_U_DATA_N<2..0>

LVDS
LVDS
LVDS
LVDS

LVDS_L_CLK_P
LVDS_L_CLK_N
LVDS_L_DATA_P<2..0>
LVDS_L_DATA_N<2..0>

LVDS
LVDS
LVDS
LVDS

LVDS_U_CLK_P
LVDS_U_CLK_N
LVDS_U_DATA_CONN_P<2..0>
LVDS_U_DATA_CONN_N<2..0>

LVDS
LVDS
LVDS
LVDS

LVDS_L_CLK_P
LVDS_L_CLK_N
LVDS_L_DATA_CONN_P<2..0>
LVDS_L_DATA_CONN_N<2..0>

TMDS
TMDS
TMDS
TMDS
TMDS
TMDS

TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA_P<5..3>
TMDS_DATA_N<5..3>
TMDS_DATA_P<2..0>
TMDS_DATA_N<2..0>

77 79
64 62 55 26 25 24 23 22 11 5
66 65

77 79

PP3V3_S5

77 79

C9400

77 78 81

0.0022uF

R94001

77 78 81

100K

5%
1/16W
MF-LF
402 2

77 78 81
77 78 81

10%
50V
CERM
402

R9401
100K

77 78 81
77 78 81

LCD_PWREN_L_RC

L9400

FERR-250-OHM

6
5
2
1

5%
1/16W
MF-LF
402

77 78 81
77 78 81

LCD_PWREN_L

PP3V3_LCD_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

0.001uF

TSOP-LF

20%
50V
CERM 2
402

SI3443DV

77 78 81
77 78 81

Q9400

78 81

Q9401

D
78 81

C9401 1

78 6

GND_CHASSIS_LVDS

78 6

GND_CHASSIS_LVDS

CRITICAL

2N7002DW-X-F

77 78 81

GPU_DIGON

SOT-363

77 78 81

R94941

78 81

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

5%
1/16W
MF-LF
402 2

77 79 86

402 2

86
86

F-RT-SM
34

20%
50V
CERM 2
402

R9410
100K pull-ups are for
100K
no-panel case (development)
5%
1/16W
Panel has 2K pull-ups
MF-LF

MSC-RB30-5-FA

0.001uF

PP3V3_S0

100K

78 81

77 79 86

J9400

C9420 1

R9411
100K

5%
1/16W
MF-LF
2 402

PP3V3_LCD_CONN
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

GPU_DDC_C_CLK
GPU_DDC_C_DATA
81 78 77

C9410 1

81 78 77

20%
50V
CERM 2
402

81 78

LVDS_L_DATA_N<0>
LVDS_L_DATA_P<0>

0.001uF

78 6

GND_CHASSIS_LVDS

81 78

81 78
81 78

81 78 77
81 78 77

81 78
81 78

81 78 77

INVERTER INTERFACE

81 78 77

LVDS_L_DATA_CONN_N<1>
LVDS_L_DATA_CONN_P<1>
LVDS_L_DATA_CONN_N<2>
LVDS_L_DATA_CONN_P<2>
LVDS_L_CLK_N
LVDS_L_CLK_P
LVDS_U_DATA_N<0>
LVDS_U_DATA_P<0>
LVDS_U_DATA_CONN_N<1>
LVDS_U_DATA_CONN_P<1>
LVDS_U_DATA_CONN_N<2>
LVDS_U_DATA_CONN_P<2>
LVDS_U_CLK_N
LVDS_U_CLK_P

C9421
2

FERR-1K-OHM-EMI

PPBUS_G3H

Q9450

PP5V_S0

FDG6332C_NL

L9452

SC70-6

R94501

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

5%
1/16W
MF-LF
402 2

PP5V_INVERTER_SW_F

100K

C9450

20%
6.3V 2
X5R
603

PP5V_INVERTER_SW
N-CHN

R9489

FDG6332C_NL
SC70-6

400-OHM-EMI

10K

2
SM-1

C9454 1

0.001uF

20%
50V
CERM 2
402

PP3V3_S0
6

C9452

0.001uF

L9454

5%
1/16W
MF-LF
402 2

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

SM-2MT-LF
5

1
2
3
4

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

Q9450

S
1

J9450

2 G

GND_CHASSIS_LVDS

CRITICAL

SM-1

GPU_BLON

518S0289

10UF

FP_PWR_EN_L

76 73

78 6

20%
2 50V
CERM
402

C9451 1

G
5

0.001uF

400-OHM-EMI

P-CHN

20%
50V
CERM
402

PPBUS_S0_INVERTER
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V

SM
56 54 52 47 42 36 31 25 5 4
80 79 70 67 66 65 61 60 57

0.001uF

L9450

64 63 61 60 54 47 43 41 5 4
70 68 66

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

20%
2 50V
CERM
402

518S0293

INVERTER_PWM
GND_INVERTER
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
1

C9455

0.001uF

20%
2 50V
CERM
402

L9455

60-OHM-EMI
SM

GND_CHASSIS_INVERTER

INVERTER_BUF
5
1

GPU_VARY_BL
INVERTER_BUF

MC74VHC1G08
SC70

INVERTER_PWM_F

U9453 4
2

INVERTER EXPECTS ACTIVE HIGH PWM SIGNAL

Internal Display Connectors

SYNC_MASTER=M1_MLB

C9453 1
20%
10V
CERM 2
402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

INVERTER_UNBUF

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

R9496
1

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

5%
1/16W
MF-LF
402

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

D
SCALE

SYNC_DATE=01/09/2006

NOTICE OF PROPRIETARY PROPERTY

0.1uF

06
86

TMDS Filtering
Place series Rs and common-mode filtering close to GPU, common mode chokes near connector.
CRITICAL

L9700

79 77

TMDS_DATA0_N

R9760

79 77

TMDS_DATA0_N

MAKE_BASE=TRUE

79 77

2012H

TMDS_DATA1_N

R9764

79 77

TMDS_DATA1_N

79 77

TMDS_DATA1_P

MAKE_BASE=TRUE

1%
1/16W
MF-LF
402 2

MAKE_BASE=TRUE
79 77

TMDS_DATA1_F_N

C9766
2

TMDS_DATA1_F_P

79 77

TMDS_DATA2_N

R9768
1

MAKE_BASE=TRUE

79 77

TMDS_DATA2_P

79 77

TMDS_DATA2_P

MAKE_BASE=TRUE

L9702

90.9

86 78 77

TMDS_CLK_P

TMDS_CLK_R_P

MAKE_BASE=TRUE

B
79 77

TMDS_DATA3_P

79 77

TMDS_DATA3_P

MAKE_BASE=TRUE

79 77

TMDS_DATA4_N

MAKE_BASE=TRUE

79 77

TMDS_DATA4_P

79 77

TMDS_DATA4_P

MAKE_BASE=TRUE

79 77

TMDS_DATA5_N
MAKE_BASE=TRUE

79 77

TMDS_DATA5_P
MAKE_BASE=TRUE

79 77

TMDS_DATA5_P

5%
1/16W
MF-LF
402

TMDS_DATA5_F_N

4
12

TMDS_DATA5_F_P

13
6

86 79

TMDS_DATA4_F_N

TMDS_CLK_F_P

7
15

TMDS_DATA4_F_P

TMDS_CLK_F_N

8
16

VGA_B

VGA_HSYNC

TMDS_DATA2_F_N
TMDS_DATA1_F_N
TMDS_DATA2_F_P
TMDS_DATA1_F_P

TMDS_DATA4_F_N
TMDS_DATA3_F_N
TMDS_DATA4_F_P
TMDS_DATA3_F_P
DVI_DDC_CLK_R
(PP5V_S0_DDC)
DVI_DDC_DATA_R
VGA_VSYNC
DVI_HPD_R

R9720

4.7K

5%
1/16W
MF-LF
2 402

Q9711

2N7002DW-X-F

100

SOT-363

C9711

2N7002DW-X-F
SOT-363

R9713

100

DVI_DDC_DATA

VGA_G

GND_CHASSIS_DVI_TOP

514-0278

CRITICAL

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

TMDS_DATA5_F_N

2
79

5%
1/16W
MF-LF
402

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN
3

TMDS_DATA5_F_P

Q9714
SOT-363

R9714
100

3 D

DVI_HPD

GPU_DDC_A_DATA

100K

5%
1/16W
MF-LF
2 402

C9714

G
S 4

GPU_HPD

20K

5%
1/16W
MF-LF
402 2

GND_CHASSIS_DVI_BOT
GND

GND_CHASSIS_DVI_TOP

External Display Connector

SYNC_MASTER=M1_MLB

SYNC_DATE=11/18/2005

6 79

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

90.9

1%
1/16W
MF-LF
402 2

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TMDS_D5_CMF

SIZE

VOLTAGE=0.275V

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7023

SCALE

5%
2 50V
CERM
402

10%
50V
CERM
402

R9715

R97871

1%
1/16W
MF-LF
2 402

S 1

PLACE NEAR 3, 11 & 19

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

6 D

100pF

20%
50V
CERM 2
603

5%
1/16W
MF-LF
402

R9731

2012H
SYM_VER-1

R9730
2

L9705
90-OHM-300mA

0.01uF

5%
1/16W
MF-LF
2 402

R9722

5%
1/16W
MF-LF
402

C9710 1

2N7002DW-X-F
1

100pF

VGA_R

10K

5%
1/16W
MF-LF
402

C9713

5%
2 50V
CERM
402

GPU_DDC_A_CLK

R9721

Q9711

5%
2 50V
CERM
402

S 4

100pF

5%
1/16W
MF-LF
2 402

3 D

DVI_DDC_CLK

10K

5%
1/16W
MF-LF
402

PP3V3_S0

R9712

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

R9711

PLACE NEAR C5A & C5B

79 6

TMDS_DATA5_R_P

0.25%
2 50V
CERM
402

VOLTAGE=5V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

5%
1/16W
MF-LF
402 2

C1
C5A

C3
C5B

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

3.3pF

PP5V_S0_DDC_PULLUPS

R97101

3
11

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

TMDS_D4_CMF

90.9

1%
1/16W
MF-LF
402 2

R9786

C9786

9
2

TMDS_DATA0_F_P

90.9

1%
1/16W
MF-LF
2 402

C9742

3V LEVEL SHIFTERS

B0530WXF

R9783

0.001uF

Isolation required for DVI power switch

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

5%
1/16W
MF-LF
402

86 79

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

R9785
0

TMDS_DATA3_F_P

2012H
SYM_VER-1

TMDS_DATA5_R_N

L9704

90.9

TMDS_DATA3_F_N

TMDS_DATA0_F_N

CRITICAL

TMDS_DATA4_R_P

VGA_R
1

D9710
SOD-123

4.7K

90-OHM-300mA

10%
50V
CERM
402

R9784

2
3 4

PP5V_S0_DDC
VOLTAGE=5V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

VOLTAGE=0.275V

TMDS_DATA5_N

1%
1/16W
MF-LF
402 2

R9782

0.001uF

2
SM-1

GND_CHASSIS_DVI_BOT

90.9

C9782

79 77

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

5%
1/16W
MF-LF
402

33
79 44 40 6

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

TMDS_D3_CMF

R9781
0

VOLTAGE=5V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

J9700

R97791

1%
1/16W
MF-LF
2 402

TMDS_DATA4_R_N

5%
1/16W
MF-LF
402

SM-LF

79 86

PP5V_S0_DDC_F

F-RT-TH-DVI

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

10%
50V
CERM
402

R9780

QH11121-RIG02-4F

VOLTAGE=0.275V

79 77

TMDS_CLK_F_P

400-OHM-EMI

0.5AMP-13.2V

CRITICAL

TMDS_DATA3_R_P

0.25%
2 50V
CERM
402

LCFILTER
SM-220MHZ-LF

GPU_R2
(DAC2 C)

C9741
3.3pF

FL9742

L9710

F9710

PP5V_S0

2012H
SYM_VER-1

90.9

80
54 52 47 42 36 31 25 5 4
70 67 66 65 61 60 57 56

1%
1/16W
MF-LF
402 2

R9778

C9778

79 86

CRITICAL

DVI INTERFACE

90.9

0.001uF
1

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

5%
1/16W
MF-LF
402

TMDS_CLK_F_N

L9703
90-OHM-300mA

R9777

CRITICAL

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

TMDS_CLK_CMF

VGA_G

R9775

1%
1/16W
MF-LF
2 402

TMDS_DATA3_R_N

5%
1/16W
MF-LF
402

R9742

90.9

2
3 4

(55mA requirement per DVI spec)

SM-220MHZ-LF
1

1%
1/16W
MF-LF
402 2
78 77

0.25%
2 50V
CERM
402

LCFILTER

R9741

C9740

1%
1/16W
MF-LF
402 2

NET_SPACING_TYPE=TMDSCONN 78
NET_PHYSICAL_TYPE=TMDSCONN

VOLTAGE=0.275V

TMDS_DATA3_N

SM
1

10%
50V
CERM
402

R9776

3
1

DVI DDC CURRENT LIMIT

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

R9774

VGA_HSYNC

5%
1/16W
MF-LF
402

20%
10V
CERM 2
402

CRITICAL

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

C9774

79 77

TMDS_DATA2_F_P

L9706
370-OHM

0.001uF

TMDS_DATA3_N

0.1uF

SYM_VER-1

5%
1/16W
MF-LF
402

79 77

C9751

VGA_HSYNC_R

3.3pF

FL9741

1%
1/16W
MF-LF
402 2

TMDS_D2_CMF

R9773

5%
1/16W
MF-LF
402

TMDS_DATA2_F_N

U9751

90.9

1%
1/16W
MF-LF
2 402

TMDS_CLK_R_N

SC70
4

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

VOLTAGE=0.275V

GPU_H2SYNC

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

10%
50V
CERM
402

R9772

R9751

MC74VHC1G08

VGA_B
1

CRITICAL

GPU_G2
(DAC2 Y)

R97711

R9770

0.001uF

TMDS_CLK_N

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS
1

C9770

86 78 77

90-OHM-300mA

TMDS_DATA2_R_P

R9740

1%
1/16W
MF-LF
402 2

2
3 4

78 77

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

FL9740

GPU_B2
(DAC2 Comp)

PP3V3_S0

2012H
SYM_VER-1

5%
1/16W
MF-LF
402

78 77

PLACE R9750 & R9751 CLOSE TO DVI CONNECTOR

CRITICAL

TMDS_DATA2_R_N

ANALOG FILTERING
PLACE CLOSE TO CONNECTOR
LCFILTER

TMDS_D1_CMF

R9769

CRITICAL

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

402

5%
1/16W
MF-LF
402

3
1

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

VOLTAGE=0.275V

79 77

VGA_VSYNC

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

1%
1/16W
MF-LF
402 2

10%
50V
CERM

5%
1/16W
MF-LF
402

SM-220MHZ-LF

90.9

1%
1/16W
MF-LF
2 402

R97671

90.9

0.001uF
1

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

R9766

VGA_VSYNC_R

20%
10V
CERM 2
402

2012H
SYM_VER-1

SC70

0.1uF

L9701

90-OHM-300mA

TMDS_DATA1_R_P

R9750

MC74VHC1G08

U9750 4

C9750

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

5%
1/16W
MF-LF
402

TMDS_DATA1_P

GPU_V2SYNC

CRITICAL

TMDS_DATA1_R_N
1

D
5

TMDS_D0_CMF

R9765

5%
1/16W
MF-LF
402

90.9

1%
1/16W
MF-LF
2 402

10%
50V
CERM
402

TMDS_DATA0_F_P

PP3V3_S0

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

VOLTAGE=0.275V

79 77

64 60 59 57 56 53 51 48 43
23 22 21 20 19 17 14 10 5 4
37 36 34 33 29 28 27 26 25 24
79 78 70 66 65

R9763

90.9

0.001uF

R9762

C9762
1

TMDS_DATA0_R_P
1

TMDS_DATA0_F_N

NET_SPACING_TYPE=TMDSCONN
NET_PHYSICAL_TYPE=TMDSCONN

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

5%
1/16W
MF-LF
402

TMDS_DATA0_P

NET_SPACING_TYPE=TMDS
NET_PHYSICAL_TYPE=TMDS

R9761

MAKE_BASE=TRUE
79 77

VGA SYNC BUFFERS

SYM_VER-1

TMDS_DATA0_R_N

5%
1/16W
MF-LF
402

TMDS_DATA0_P

90-OHM-300mA

06
86

IR & Sleep LED Connector

CRITICAL

J9800

53780-0670
M-RT-SM
7

NC
PP5V_S3

5 45 51 61 66

USB_IR_N
USB_IR_P

2
3

6 22

SYS_LED_ANODE

518S0388

Bluetooth (M13P) & SATA HDD Flex Connector

PLACEMENT_NOTE=Place C4960 close to southbridge

PLACEMENT_NOTE=Place C4961 next to C4960

B
PLACEMENT_NOTE=Place FL4965 close to J4960

C4960

FL4965

0.0047uF
21

SATA_C_R2D_C_P

SATA_C_R2D_UF_P

90-OHM-300mA
2012H
SYM_VER-2

CRITICAL

J4960
QT500166-L020

M-ST-SM

C4961
0.0047uF
21

OUT

SATA_C_R2D_C_N

SATA_C_D2R_N

10%
25V
CERM
402

SATA_C_R2D_UF_N

10%
25V
CERM
402

SYM_VER-2

SATA_C_D2R_UF_N

C4965

OUT

SATA_C_D2R_P

SATA_C_D2R_C_N
SATA_C_D2R_C_P

0.0047uF
2

0.0047uF
SATA_C_D2R_UF_P

PLACEMENT_NOTE=Place FL4960 close to southbridge

10%
25V
CERM
402

C4966

FL4960
90-OHM-300mA
2012H

SATA_C_R2D_P
SATA_C_R2D_N

64
56
32
45
62

63
51
27 5
41 37
59 58
66

PP3V3_S3

PP5V_S0

4 5 25 31 36 42 47 52 54 56 57
60 61 65 66 67 70 78 79

NC
USB_BT_N
USB_BT_P

6 22

10%
25V
CERM
402

PLACEMENT_NOTE=Place C4966 next to C4965

PLACEMENT_NOTE=Place C4965 close to J4960

516S0350
M9 Specific Connectors
SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

LVDS Interface Pull-downs

NOTE: These parts are to counter an invalid state caused by the

M56 part. Bias voltage is present on LVDS interface pins even
when they should be tri-stated to meet panel power sequence
requirements. Resulting pump-up in LCD panel can cause startup
and long-term reliability issues. Pull-down resistors reduce
the pump-up in the panel, though some voltage will still be seen
on LVDS signals when they should be 0V.
LVDS_PD

RP9901
81 78 77

LVDS_L_DATA_P<0>

81 78
77

LVDS_L_DATA_P<0>

8.2K

MAKE_BASE=TRUE

LVDS_PD

5%
1/16W
SM-LF
81 78 77

LVDS_L_DATA_N<0>

81 78
77

RP9901

LVDS_L_DATA_N<0>

MAKE_BASE=TRUE

LVDS_PD

LVDS_L_DATA_P<1>

LVDS_L_DATA_CONN_P<1>

8.2K

MAKE_BASE=TRUE

LVDS_PD

5%
1/16W
SM-LF
78 77

LVDS_L_DATA_N<1>

RP9900

LVDS_L_DATA_CONN_N<1>

MAKE_BASE=TRUE

LVDS_PD

LVDS_L_DATA_P<2>

LVDS_L_DATA_CONN_P<2>

8.2K

LVDS_L_DATA_N<2>

MAKE_BASE=TRUE

LVDS_PD

5%
1/16W
SM-LF
78 77

8.2K
5%
1/16W
SM-LF

RP9900
78 77

5%
1/16W
SM-LF

RP9900
78 77

8.2K

RP9900

LVDS_L_DATA_CONN_N<2>

8.2K

MAKE_BASE=TRUE
5%
1/16W
SM-LF

LVDS_PD

RP9901
81 78 77

81 78
77

LVDS_L_CLK_P

8.2K

MAKE_BASE=TRUE

LVDS_PD

5%
1/16W
SM-LF
81 78 77

81 78
77

LVDS_L_CLK_N

RP9901

LVDS_L_CLK_N

8.2K

MAKE_BASE=TRUE
5%
1/16W
SM-LF

LVDS_PD

RP9902
81 78 77

LVDS_U_DATA_P<0>

81 78
77

LVDS_U_DATA_P<0>

8.2K

MAKE_BASE=TRUE

LVDS_PD

5%
1/16W
SM-LF
81 78 77

LVDS_U_DATA_N<0>

81 78
77

RP9902

LVDS_U_DATA_N<0>

MAKE_BASE=TRUE

LVDS_PD

LVDS_U_DATA_P<1>

LVDS_U_DATA_CONN_P<1>

8.2K

MAKE_BASE=TRUE

LVDS_PD

5%
1/16W
SM-LF
78 77

LVDS_U_DATA_N<1>

RP9902

LVDS_U_DATA_CONN_N<1>

MAKE_BASE=TRUE

LVDS_PD

78 77

LVDS_U_DATA_P<2>

LVDS_U_DATA_CONN_P<2>

LVDS_U_DATA_N<2>

MAKE_BASE=TRUE

LVDS_PD

5%
1/16W
SM-LF
78 77

8.2K
5%
1/16W
SM-LF

RP9903
8.2K
2

5%
1/16W
SM-LF

RP9902
78 77

8.2K

RP9903

LVDS_U_DATA_CONN_N<2>

8.2K

MAKE_BASE=TRUE
5%
1/16W
SM-LF

LVDS_PD

RP9903
81 78 77

81 78
77

LVDS_U_CLK_P

8.2K

MAKE_BASE=TRUE
5%
1/16W
SM-LF

81 78 77

81 78
77

LVDS_U_CLK_N

LVDS_PD

RP9903
3

8.2K

MAKE_BASE=TRUE
5%
1/16W
SM-LF

LVDS Interface Pull-downs

SYNC_MASTER=M1_MLB

SYNC_DATE=12/19/2005

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

Revision History
Proto
11-29-05: -Release for Proto
11-30-05: -Turned on M56_REV_B24 BOMOPTION
12-01-05: -Added CRITICAL property to 3-pin caps, ESD diodes, and FW chokes
-Added ITPCONN BOMOPTION
-RC value changes on CPU Core current sense
-Changed IDE reset pulldown to 15K

EVT

12-01-05: -Changed L4400 to Pb-free part

-Changed J4620 to M9 part
-Added ESD/EMI protection to camera connector
-Removed dual voltage support for trackpad
-Added PM_SUS_STAT_L and PM_SLP_S5_L pulldowns

Revision History
SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

FSB (Front-Side Bus) Constraints

PCI-Express / DMI Bus Constraints

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

FSB_55S

=55_OHM_SE

=STANDARD

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

PCIE_100D

=100_OHM_DIFF

DMI_100D

=100_OHM_DIFF

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT

=3:1_SPACING

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=3:1_SPACING

TABLE_SPACING_RULE_ITEM

FSB_ADDR

TABLE_SPACING_RULE_ITEM

FSB_DATA

TABLE_SPACING_RULE_ITEM

FSB_ADDR2ADDR

=2:1_SPACING

FSB_ADSTB

=3:1_SPACING

FSB_DATA2DATA

=2:1_SPACING

FSB_DSTB

=3:1_SPACING

TABLE_SPACING_RULE_ITEM

PCIE

20 MIL

DMI

20 MIL

TABLE_SPACING_RULE_ITEM

=3:1_SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

FSB_ADDR2ADSTB

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

FSB_DATA2DSTB

=3:1_SPACING

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 7.2, 9.2 & 10.5.2

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=2:1_SPACING

Disk Interface Constraints

TABLE_SPACING_RULE_ITEM

FSB_COMMON

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

IDE_55S

=55_OHM_SE

=STANDARD

SATA_100D

=100_OHM_DIFF

SPACING_RULE_SET

LAYER

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

TABLE_PHYSICAL_RULE_ITEM

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

FSB_ADDR

TABLE_PHYSICAL_RULE_ITEM

FSB_ADDR2ADDR
TABLE_SPACING_ASSIGNMENT_ITEM

FSB_ADDR

FSB_ADSTB

FSB_ADDR2ADSTB

FSB_DATA

FSB_DATA2DATA

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

FSB_DATA

FSB_DSTB

FSB_DATA2DSTB

IDE

=1.8:1_SPACING

SATA

20 MIL

TABLE_SPACING_RULE_ITEM

All FSB signals with impedance requirements are 55-ohm single-ended.

Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.
Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.
DSTB complementary pairs are spaced 3:1, even in constraint areas.

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 10.6 & 10.7.2

Audio Interface Constraints

TABLE_PHYSICAL_RULE_HEAD

Design Guide recommends each strobe/signal group is routed on the same layer.
Design Guide recommends FSB signals be routed only on internal layers.

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

AUDIO_55S

=55_OHM_SE

=STANDARD

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.
NOTE: Design Guide allows closer spacing if signal lengths can be shortened.

TABLE_SPACING_RULE_HEAD

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.2 & 4.3

LINE-TO-LINE SPACING

WEIGHT

=1.8:1_SPACING

TABLE_SPACING_RULE_ITEM

AUDIO

C CPU Signal Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

USB 2.0 Interface Constraints

TABLE_PHYSICAL_RULE_ITEM

CPU_27P4S

=27P4_OHM_SE

=STANDARD

CPU_55S

=55_OHM_SE

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

USB2_90D

=90_OHM_DIFF

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=2:1_SPACING

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

CPU_2TO1

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

CPU_COMP

DG recommends at least 25 mils, >50 mils preferred

25 MIL

USB2

=4:1_SPACING

USB2_2CLK

25 MIL

?
TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

CPU_GTLREF

25 MIL

CPU_ITP

=2:1_SPACING

CPU_VCCSENSE

25 MIL

DG ?says minimum spacing 50 mils to clocks

TABLE_SPACING_RULE_ITEM

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.10.1.2

TABLE_SPACING_RULE_ITEM

Internal Interface Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended.

Some signals require 27.4-ohm single-ended impedance.

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

SMB_55S

=55_OHM_SE

=STANDARD

SPI_55S

=55_OHM_SE

=STANDARD

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.4, 4.6.2, & 5.8.2.4

TABLE_PHYSICAL_RULE_ITEM

DDR2 Memory Bus Constraints

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

WEIGHT

DIFFPAIR NECK GAP

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MEM_45S

=45_OHM_SE

=STANDARD

MEM_55S

=55_OHM_SE

=STANDARD

MEM_70D

=70_OHM_DIFF

SMB

=3:1_SPACING

SPI

=1.8:1_SPACING

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.17.1.1

TABLE_PHYSICAL_RULE_ITEM

MEM_85D

=85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

MEM_CLK

MEM_CLK2MEM

TABLE_SPACING_RULE_ITEM

MEM_CTRL2CTRL

=2:1_SPACING

MEM_CTRL2MEM

=3:1_SPACING

MEM_CLK

MEM_CTRL

MEM_CLK2MEM

MEM_CLK

MEM_CMD

MEM_CLK2MEM

MEM_CLK

MEM_DATA

MEM_CLK2MEM

TABLE_SPACING_RULE_ITEM

MEM_CMD2MEM

=3:1_SPACING

MEM_DATA2DATA

=1.5:1_SPACING

AREA_TYPE

MEM_CTRL

MEM_CLK

MEM_DQS

MEM_CLK2MEM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

CLK_FSB_100D

=100_OHM_DIFF

CLK_PCIE_100D

=100_OHM_DIFF

CLK_MED_55S

=55_OHM_SE

=STANDARD

CLK_SLOW_55S

=55_OHM_SE

=STANDARD

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

MEM_CTRL2CTRL

MEM_CTRL

MEM_CMD

MEM_CTRL2MEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

MEM_DATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

TABLE_PHYSICAL_RULE_HEAD

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

=1.5:1_SPACING

NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MEM_CMD2CMD

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

=4:1_SPACING

Clock Signal Constraints

TABLE_SPACING_ASSIGNMENT_HEAD

WEIGHT
TABLE_SPACING_RULE_ITEM

MEM_CLK2MEM

=85_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

MEM_DQS

MEM_CTRL2MEM
TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

MEM_DATA2MEM

=3:1_SPACING

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CMD

MEM_CLK

MEM_CMD2MEM

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_DATA

MEM_CLK

MEM_DATA2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MEM_DQS2MEM

=3:1_SPACING

MEM_CMD

TABLE_SPACING_RULE_ITEM

25 MIL

MEM_CTRL

MEM_CMD2MEM

MEM_CMD

MEM_CMD2CMD

MEM_DATA

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_CMD2MEM

MEM_CMD

MEM_DQS

MEM_CMD2MEM

MEM_DATA

MEM_CMD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_DQS

MEM_CLK

MEM_DQS2MEM

MEM_DQS

MEM_CTRL

MEM_DQS2MEM

MEM_DQS

MEM_CMD

MEM_DQS2MEM

MEM_DQS

MEM_DATA

MEM_DQS2MEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CLK

MEM_2OTHER

MEM_CTRL

MEM_2OTHER

CLK_MED

20 MIL

CLK_SLOW

10 MIL

TABLE_SPACING_RULE_ITEM

MEM_DATA2MEM

TABLE_SPACING_RULE_ITEM

MEM_DATA2MEM

MEM_DATA

MEM_DATA2DATA

MEM_DATA

MEM_DQS

MEM_DATA2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

Napa Platform Constraints

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

TABLE_SPACING_ASSIGNMENT_ITEM

*
*

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

20 MIL

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DATA

25 MIL

TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1

TABLE_SPACING_ASSIGNMENT_ITEM

Need to support MEM_*-style wildcards!

TABLE_SPACING_RULE_ITEM

CLK_FSB
CLK_PCIE

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

WEIGHT

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_2OTHER

LINE-TO-LINE SPACING

TABLE_SPACING_ASSIGNMENT_HEAD

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

TABLE_SPACING_ASSIGNMENT_ITEM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_2OTHER

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_DQS2MEM

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 6.2

REV.

051-7023

06
86

GDDR3 (Frame Buffer) Memory Bus Constraints

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

TABLE_PHYSICAL_RULE_HEAD

DIFFPAIR NECK GAP

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

ENET_100D

=100_OHM_DIFF

FW_110D

=110_OHM_DIFF

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

FB_35S_TO_55S

=35_OHM_SE

=55_OHM_SE

=35_55_OHM_SE

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD
TABLE_PHYSICAL_RULE_ITEM

FB_40S

=40_OHM_SE

High-Speed I/O Interface Constraints

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD
TABLE_PHYSICAL_RULE_ITEM

FB_55S

=55_OHM_SE

=STANDARD

FB_75D

=75_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

ENET

=3:1_SPACING

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

WEIGHT
TABLE_SPACING_RULE_ITEM

FB_ADCTRL

=2.5:1_SPACING

FB_CLK

=2.5:1_SPACING

note

TABLE_SPACING_RULE_ITEM

FB_DATA

=2.5:1_SPACING

PCI Bus Constraints

ADDR/CTRL lines should route 35-ohms to T, then 55-ohms to each VRAM device.
CTRL lines are 55-ohm single-ended impedence.
DQ/DQM/DQS lines are 40-ohm single-ended impedence.

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

PCI_55S

=55_OHM_SE

=STANDARD

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

NOTE: CLK lines are specified in Layout Guide as 40-ohm single-ended. We treat as 75-ohm differential.
NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT

=2:1_SPACING

TABLE_SPACING_RULE_ITEM

SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.

PCI

Video Signal Constraints

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

LVDS_100D

=100_OHM_DIFF

TMDS_100D

=100_OHM_DIFF

VGA_75S

=75_OHM_SE

=STANDARD

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

LVDS

=3:1_SPACING

TABLE_SPACING_RULE_ITEM

LVDS_PAIR2PAIR

25 MIL

TMDS_PAIR2PAIR

25 MIL

TABLE_SPACING_RULE_ITEM

TMDS

=3:1_SPACING

TABLE_SPACING_RULE_ITEM

?
TABLE_SPACING_RULE_ITEM

VGA

15 MIL

C
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

LVDS

LVDS_PAIR2PAIR

TMDS

TMDS_PAIR2PAIR

TABLE_SPACING_ASSIGNMENT_ITEM

LVDS and TMDS signals are 100-ohm +/- 10% differential impedence.
LVDS and TMDS pairs should be kept at least 25 mils apart.
Ground shields can be used around each pair if spacing cannot be met.
VGA should be routed as close to 75-ohms single-ended impedence as possible.
VGA signals should be kept at least 15 mils from other traces.
Ground shields recommended around VGA signals.
NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"
SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.

More System Constraints

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

M1 Board-Specific Spacing & Physical Constraints

TABLE_BOARD_INFO

TABLE_SPACING_RULE_HEAD

BOARD LAYERS

BOARD AREAS

BOARD UNITS
(MIL or MM)

ALLEGRO
VERSION

SPACING_RULE_SET

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

NO_TYPE,BGA

15.2

DEFAULT

LAYER

LINE-TO-LINE SPACING

WEIGHT

0.1 MM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

BGA

BGA_P1MM

MEM_CLK

BGA

BGA_P2MM

CLK_FSB

BGA

BGA_P2MM

CLK_PCIE

BGA

BGA_P2MM

CLK_MED

BGA

BGA_P2MM

CLK_SLOW

BGA

BGA_P2MM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

STANDARD

TABLE_SPACING_ASSIGNMENT_ITEM

=DEFAULT

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

DEFAULT

=55_OHM_SE

30 MM

0 MM

STANDARD

=DEFAULT

12.7 MM

=DEFAULT

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_SPACING_RULE_ITEM

BGA_P1MM

TABLE_SPACING_ASSIGNMENT_ITEM

=DEFAULT

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

BGA_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

=DEFAULT

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

BGA_P3MM

TABLE_SPACING_ASSIGNMENT_ITEM

=DEFAULT

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

55_OHM_SE

TOP,BOTTOM

TABLE_SPACING_ASSIGNMENT_ITEM

FB_CLK

BGA

BGA_P2MM

FSB_DSTB

BGA

BGA_P3MM

TABLE_PHYSICAL_RULE_ITEM

0.100 MM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

55_OHM_SE

0.076 MM

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

50_OHM_SE

TOP,BOTTOM

0.124 MM

TABLE_PHYSICAL_RULE_HEAD

Allow 0.1 MM on blind-to-buried via dogbones (layers 2 & 11)

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_PHYSICAL_RULE_ITEM

50_OHM_SE

0.090 MM

=STANDARD

TABLE_SPACING_RULE_ITEM

1.5:1_SPACING

0.15 MM

TABLE_SPACING_RULE_ITEM

1.5:1_SPACING

ISL2,ISL11

1.8:1_SPACING

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

TOP,BOTTOM

0.18 MM

0.150 MM

1.8:1_SPACING

ISL2,ISL11

2:1_SPACING

0.2 MM

2.5:1_SPACING

0.25 MM

45_OHM_SE

0.105 MM

=STANDARD

3:1_SPACING

0.3 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

2:1_SPACING

ISL2,ISL11

0.1 MM

2.5:1_SPACING

ISL2,ISL11

0.1 MM

4:1_SPACING

CLK_PCIE

ISL2,ISL11

0.1 MM

?
TABLE_SPACING_RULE_ITEM

CLK_MED

ISL2,ISL11

0.1 MM

CLK_SLOW

ISL2,ISL11

0.1 MM

CPU_COMP

ISL2,ISL11

0.1 MM

CPU_GTLREF

ISL2,ISL11

0.1 MM

CPU_VCCSENSE

ISL2,ISL11

0.1 MM

DMI

ISL2,ISL11

0.1 MM

LVDS_PAIR2PAIR

ISL2,ISL11

0.1 MM

MEM_2OTHER

ISL2,ISL11

0.1 MM

PCIE

ISL2,ISL11

0.1 MM

SATA

ISL2,ISL11

0.1 MM

TMDS_PAIR2PAIR

ISL2,ISL11

0.1 MM

VGA

ISL2,ISL11

0.1 MM

TABLE_SPACING_RULE_ITEM

3:1_SPACING

0.4 MM

TABLE_SPACING_RULE_ITEM

ISL2,ISL11

TABLE_SPACING_RULE_ITEM

0.1 MM

TABLE_SPACING_RULE_ITEM

DIFFPAIR NECK GAP

0.1 MM

TABLE_SPACING_RULE_ITEM

ALLOW ROUTE
ON LAYER?

ISL2,ISL11

TABLE_SPACING_RULE_ITEM

0.1 MM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

CLK_FSB
TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

45_OHM_SE

DIFFPAIR NECK GAP

TABLE_SPACING_RULE_ITEM

0.1 MM

TABLE_SPACING_RULE_ITEM

4:1_SPACING

ISL2,ISL11

TABLE_SPACING_RULE_ITEM

0.1 MM

TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE

TOP,BOTTOM

0.185 MM

TABLE_SPACING_RULE_ITEM

0.185 MM
TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE

0.131 MM

0.100 MM

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

35_OHM_SE

TOP,BOTTOM

0.230 MM

35_OHM_SE

0.165 MM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

27P4_OHM_SE

TOP,BOTTOM

0.335 MM

27P4_OHM_SE

0.240 MM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Rules for "Topology #3" for FSB signals, Napa DG tables 4-7 & 4-12.
TABLE_PHYSICAL_RULE_ITEM

=STANDARD

TABLE_SPACING_RULE_HEAD

=STANDARD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_OVERRIDE

FSB_ADDR

TABLE_SPACING_RULE_OVERRIDE

=2:1_SPACING

FSB_DATA

OVERRIDE

=2:1_SPACING

OVERRIDE

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

OVERRIDE

DIFFPAIR NECK GAP

OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

FSB_ADDR2ADDR

TABLE_PHYSICAL_RULE_ITEM

35_55_OHM_SE

TOP,BOTTOM

0.230 MM

0.100 MM

35_55_OHM_SE

0.165 MM

0.076 MM

OVERRIDE

*
OVERRIDE

FSB_DATA2DATA

OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

TABLE_SPACING_RULE_OVERRIDE

=STANDARD

*
OVERRIDE

=STANDARD

OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

=STANDARD

FSB_ADSTB

OVERRIDE

Unsupported rule

TABLE_SPACING_RULE_OVERRIDE

=2:1_SPACING

FSB_DSTB

OVERRIDE

=2:1_SPACING

OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

FSB_ADDR2ADSTB
OVERRIDE

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

75_OHM_SE

0.076 MM

=STANDARD

TABLE_SPACING_RULE_OVERRIDE

=2:1_SPACING

FSB_DATA2DSTB

OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

=2:1_SPACING

OVERRIDE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE

AREA_TYPE

PHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LVDS

LVDS_100D

TMDS

TMDS_100D

TMDSCONN

TMDS_100D

MEM_2OTHER

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_OVERRIDE

OVERRIDE

*
OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

0.5 MM

PCI_2PCI

OVERRIDE

*
OVERRIDE

0.1 MM

OVERRIDE

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

70_OHM_DIFF

0.149 MM

=STANDARD

0.125 MM

70_OHM_DIFF

TOP,BOTTOM

0.185 MM

0.125 MM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

75_OHM_DIFF

0.131 MM

=STANDARD

0.125 MM

75_OHM_DIFF

TOP,BOTTOM

0.161 MM

0.125 MM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

PCI

PCI_2PCI

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

VGA

TABLE_SPACING_ASSIGNMENT_ITEM

VGA_75S

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

ENETCONN

ENET

TMDSCONN

TMDS

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

80_OHM_DIFF

0.115 MM

0.111 MM

=STANDARD

0.125 MM

"Stale" physical / spacing types

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

FSB_ANALOG

FSB_COMMON

FSB_P2MM

FSB_COMMON

I2C

SMB

GND

STANDARD

MEM_PP1V8_S3

STANDARD

FB_PP1V8

STANDARD

TABLE_PHYSICAL_RULE_ITEM

80_OHM_DIFF

TOP,BOTTOM

0.140 MM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.125 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

MAXIMUM NECK LENGTH

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

85_OHM_DIFF

0.101 MM

85_OHM_DIFF

TOP,BOTTOM

0.125 MM

=STANDARD

0.125 MM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

TABLE_SPACING_ASSIGNMENT_ITEM

DIFFPAIR NECK GAP

TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF

0.102 MM

90_OHM_DIFF

TOP,BOTTOM

0.130 MM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

100_OHM_DIFF

0.080 MM

100_OHM_DIFF

TOP,BOTTOM

0.099 MM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.220 MM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

=STANDARD

0.200 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

=STANDARD

FSB_ANALOG
FSB_P2MM
I2C
GND
MEM_PP1V8_S3
FB_PP1V8
PCI

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PCI_55S

M1 Spacing & Physical Constraints

TABLE_PHYSICAL_RULE_HEAD

MAXIMUM NECK LENGTH

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_ITEM

110_OHM_DIFF

0.077 MM

=STANDARD

0.330 MM

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

110_OHM_DIFF

TOP,BOTTOM

0.089 MM

0.330 MM

MEM_45S

OVERRIDE

0.100 MM
OVERRIDE

OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MEM_70D

OVERRIDE

0.100 MM
OVERRIDE

SYNC_DATE=02/10/2006

DIFFPAIR NECK GAP

TABLE_PHYSICAL_RULE_ITEM

SYNC_MASTER=M1_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

TABLE_PHYSICAL_RULE_ITEM

MEM_85D

OVERRIDE

0.100 MM
OVERRIDE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

8
ELECTRICAL_CONSTRAINT_SET

FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON
FSB_COMMON

FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
FSB_BREQ0_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DPWR_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_RS_L<2..0>
FSB_TRDY_L
FSB_CPURST_L

FSB_55S
FSB_55S
FSB_55S
FSB_55S

FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB

FSB_D_L<63..0>
FSB_DINV_L<3..0>
FSB_DSTBP_L<3..0>
FSB_DSTBN_L<3..0>

FSB_55S
FSB_55S
FSB_55S

FSB_ADDR
FSB_ADDR
FSB_ADSTB

FSB_A_L<31..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<3..0>

CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_27P4S
CPU_55S
CPU_27P4S

CPU_2TO1
CPU_2TO1
CPU_2TO1
CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP

FSB_IERR_L
FSB_FERR_L
CPU_PWRGD
CPU_INTR
CPU_NMI
CPU_A20M_L
CPU_DPSLP_L
CPU_IGNNE_L
CPU_INIT_L
CPU_SMI_L
CPU_STPCLK_L
CPU_THERMTRIP_L
PM_DPRSLPVR
IMVP_DPRSLPVR
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>

CPU_55S
CLK_FSB_100D
CLK_FSB_100D
CPU_55S

CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP

XDP_BPM_L<5..0>
CPU_XDP_CLK_P
CPU_XDP_CLK_N
ITPRESET_L

CPU_55S
CPU_55S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S

CPU_2TO1
CPU_2TO1
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE

CPU_VID<6..0>
CPU_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N

FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S
FSB_55S

THERM
THERM

7
5 7 12
5 7 12
7 12
5 7 12
5 7 12
7 12
5 7 12
5 7 12

NET_TYPE
SPACING
PHYSICAL

MEM_CLK
MEM_CTRL
MEM_CMD
MEM_DATA
MEM_DQS

MEM_70D
MEM_45S
MEM_55S
MEM_55S
MEM_85D

FB_CLK
FB_ADCTRL
FB_ADCTRL
FB_DATA

FB_75D
FB_35S_TO_55S
FB_55S
FB_40S

LVDS
TMDS
VGA

LVDS_100D
TMDS_100D
VGA_75S

PCIE
DMI

PCIE_100D
DMI_100D

SATA
IDE

SATA_100D
IDE_55S

USB2
ENET
FW

USB2_90D
ENET_100D
FW_110D

SMB
SPI

SMB_55S
SPI_55S

CLK_FSB
CLK_PCIE
CLK_MED
CLK_SLOW

CLK_FSB_100D
CLK_PCIE_100D
CLK_MED_55S
CLK_SLOW_55S

5 7 12
5 7 12
5 7 12
7 12

7 12
5 7 11 12

5 7 12
5 7 12
5 7 12
5 7 12

5 7 12
5 7 12
5 7 12

5 7 21
7 21
7 21
7 21
5 7 21
7 21
7 21
7 21
5 7 21

5 14 23 60

5 60
7
7
7
7
7

7 11
11 34
11 34
11

8 9 86
8 9 86
8 60
8 60
60
60

I70
I71

I72
I73

AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S
AUDIO_55S

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

SB_ACZ_BITCLK
ACZ_BITCLK
SB_ACZ_SYNC
ACZ_SYNC
SB_ACZ_RST_L
ACZ_RST_L
ACZ_SDATAIN<0>
SB_ACZ_SDATAOUT
ACZ_SDATAOUT

TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN

TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA_P<5..3>
TMDS_DATA_N<5..3>
TMDS_DATA_P<2..0>
TMDS_DATA_N<2..0>
TMDS_CLK_F_P
TMDS_CLK_F_N
TMDS_DATA_F_P<5..3>
TMDS_DATA_F_N<5..3>
TMDS_DATA_F_P<2..0>
TMDS_DATA_F_N<2..0>

21
5 21 47
21
5 21 47

21
5 21 47
5 21 47
21
5 21 47

77 78 79
77 78 79
78
78
78
78
79
79

M1 Net Properties
SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-7023

06
86

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