Apple Proprietary Engineering Document
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CK ENG
APPD
FINO M33
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
19 397422 ENGINEERING RELEASED 08/30/05 ?
DVT2 - 8/30/05
D PDF CSA CONTENTS
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SYNC MASTER DATE PDF CSA CONTENTS
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SYNC MASTER DATE PDF CSA CONTENTS
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SYNC MASTER DATE D
y
2
TABLE_TABLEOFCONTENTS_ITEM
2 System Block Diagram FINO-M23 08/26/2005 38
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54 CPU AVDD VREG FINO-M23 08/26/2005 74
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131 Shasta Ethernet Q63 08/26/2005
3
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4 Power Block Diagram FINO-M23 08/26/2005 39
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55 T,V,I SENSORS FINO-M23 08/26/2005 75
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132 Vesta Ethernet PHY Q63 08/26/2005
r
4
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5 Table Items FINO-M23 08/26/2005 40
TABLE_TABLEOFCONTENTS_ITEM
56 CPU ALIASES & MISC FINO-M23 08/26/2005 76
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136 ETHERNET CONNECTOR FINO-M23 08/26/2005
5 6 FUNC TEST 1 OF 2 FINO-M23 08/26/2005 41 58 KODIAC NBMEM PWR & CAPS Q63 08/26/2005 77 138 Shasta FireWire Q63 08/26/2005
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
6 7 POWER CONN / ALIAS M33-PC 06/20/2005 42 59 Kodiak Memory Dq/Ctl FINO-M23 08/26/2005 78 139 Vesta FireWire PHY Q63 08/26/2005
a
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7
TABLE_TABLEOFCONTENTS_ITEM
8 Signal Alias FINO-M23 08/26/2005 43
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61 Parallel Term FINO-M23 08/26/2005 79
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140 FIREWIRE CONNECTORS FINO-M23 08/26/2005
8
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9 FUNC TEST 2 OF 2 FINO-M23 08/26/2005 44
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62 Main Memory Clock Buffer FINO-M23 08/26/2005 80
TABLE_TABLEOFCONTENTS_ITEM
142 USB Host Interfaces FINO-M23 08/26/2005
9 11 1.8V VREG M33-PC 06/20/2005 45 63 MEMORY ADDR BRANCHING FINO-M23 08/26/2005 81 143 USB Device Interfaces FINO-M23 08/26/2005
n
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
10
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12 1.5V Vreg FINO-M23 08/26/2005 46
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67 Memory Dimm A FINO-M23 08/26/2005 82
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144 Flash Media Ctrl FINO-M23 08/26/2005
i
11 13 1.2V Vreg FINO-M23 08/26/2005 47 68 MLB Mem Series Term FINO-M23 08/26/2005 83 145 Flash Connector FINO-M23 08/26/2005
C
TABLE_TABLEOFCONTENTS_ITEM
12 15 2.5V Vreg FINO-M23 08/26/2005
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48 69 On-Board DDR SDRAM FINO-M23 08/26/2005
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84 147 AUDIO: CODEC FINO-SO 08/26/2005
C
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
13
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16 5V & 3.3V Fets FINO-M23 08/26/2005 49
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70 On-Board DDR SDRAM FINO-M23 08/26/2005 85
TABLE_TABLEOFCONTENTS_ITEM
148 AUDIO: LINE INPUT AMP FINO-SO 08/26/2005
14
TABLE_TABLEOFCONTENTS_ITEM
17 Vesta Core / Misc FINO-M23 08/26/2005 50
TABLE_TABLEOFCONTENTS_ITEM
82 KODIAK PCI-E X16 Q63 08/26/2005 86
TABLE_TABLEOFCONTENTS_ITEM
150 AUDIO: LINE OUT AMP FINO-SO 08/26/2005
m
15
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19 KODIAK CORE & BYPASS Q63 08/26/2005 51
TABLE_TABLEOFCONTENTS_ITEM
84 GPU PCIe FINO-M23 08/18/2005 87
TABLE_TABLEOFCONTENTS_ITEM
152 AUDIO: SPEAKER AMP FINO-SO 08/26/2005
16 20 KODIAK & SHASTA MISC FINO-M23 08/26/2005 52 85 Graphics Vregs M33-DD 06/20/2005 88 153 AUDIO: CONNECTORS FINO-SO 08/26/2005
il
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
17 23 Shasta Core Power Q63 08/26/2005 53 86 GPU Core Power FINO-M23 08/26/2005 89 154 AUDIO: POWER SUPPLIES FINO-SO 08/26/2005
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
18
TABLE_TABLEOFCONTENTS_ITEM
24 Shasta Serial / Misc FINO-M23 08/26/2005 54
TABLE_TABLEOFCONTENTS_ITEM
87 GPU Frame Buffer FINO-M23 08/26/2005
19
TABLE_TABLEOFCONTENTS_ITEM
25 PULSAR2 POWER Q63 08/26/2005 55
TABLE_TABLEOFCONTENTS_ITEM
88 FB Series Termination FINO-M23 08/26/2005
20 26 PULSAR2 CLOCKS FINO-M23 08/26/2005 56 89 GPU GDDR SDRAM A FINO-M23 08/26/2005
e
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
21
TABLE_TABLEOFCONTENTS_ITEM
27 Pulsar Aliases FINO-M23 08/26/2005 57
TABLE_TABLEOFCONTENTS_ITEM
90 GPU GDDR SDRAM B FINO-M23 08/26/2005
B 22 28 System Management Unit Q63 08/26/2005 58 91 FB Parallel Termination M33-DD 06/20/2005 B
r
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
23
TABLE_TABLEOFCONTENTS_ITEM
29 SMU SUPPLEMENTAL (2) FINO-M23 08/26/2005 59
TABLE_TABLEOFCONTENTS_ITEM
92 GPU Straps FINO-M23 08/26/2005
24
TABLE_TABLEOFCONTENTS_ITEM
30 SMU SUPPLEMENTAL (3) FINO-M23 08/26/2005 60
TABLE_TABLEOFCONTENTS_ITEM
93 GPU DVI & DACs FINO-M23 08/26/2005
25 31 SMU SUPPLEMENTAL (4) FINO-M23 08/26/2005 61 96 TMDS / ExtVGA M33-DD 06/20/2005
P
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
26
TABLE_TABLEOFCONTENTS_ITEM
32 Fan 0, 1 & System Temp FINO-M23 08/26/2005 62
TABLE_TABLEOFCONTENTS_ITEM
97 KODIAK PCI-E CONST FINO-M23 08/26/2005
27
TABLE_TABLEOFCONTENTS_ITEM
33 Fan 2 & HD Temp M33-HS 08/04/2005 63
TABLE_TABLEOFCONTENTS_ITEM
98 KODIAK HT16 Q63 08/26/2005
28
TABLE_TABLEOFCONTENTS_ITEM
39 I2C Connections FINO-M23 08/26/2005 64
TABLE_TABLEOFCONTENTS_ITEM
101 HT ALIASES FINO-M23 08/26/2005
29
TABLE_TABLEOFCONTENTS_ITEM
41 KODIAK EI PWR & CAPS Q63 08/26/2005 65
TABLE_TABLEOFCONTENTS_ITEM
103 Shasta HyperTransport Q63 08/26/2005
30
TABLE_TABLEOFCONTENTS_ITEM
42 KODIAK EI A Q63 08/26/2005 66
TABLE_TABLEOFCONTENTS_ITEM
119 Shasta PCI Interface Q63 08/26/2005
31 43 CPU EI AND IO FINO-M23 08/26/2005 67 120 PCI SERIES TERMINATION FINO-M23 08/26/2005 DIMENSIONS ARE IN MILLIMETERS
Apple Computer Inc.
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
XX
METRIC
32 44 KODIAK EI B Q63 08/26/2005 68 121 AIRPORT & BLUETOOTH FINO-M23 08/26/2005
A TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
33 47 CPU STRAPS FINO-M23 08/26/2005 69 122 USB 2.0 PCI Interface Q63 08/26/2005 X.XXX
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
AGREES TO THE FOLLOWING
ENG APPD MFG APPD
34 48 CPU POWER AND BYPASS FINO-M23 08/26/2005 70 125 BootROM Q63 08/26/2005 ANGLES
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
QA APPD DESIGNER TITLE
35 49 PROC DECOUPLING FINO-M23 08/26/2005 71 127 Shasta Disk M33-DC 06/20/2005 DO NOT SCALE DRAWING
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
RELEASE SCALE SCH,MLB,FINO,M33
36
TABLE_TABLEOFCONTENTS_ITEM
50 CPU VCORE VREG M33-HS 06/20/2005 72
TABLE_TABLEOFCONTENTS_ITEM
129 Disk Connectors M33-DC 06/20/2005 NONE
SIZE DRAWING NUMBER REV.
37 52 CPU VCORE MORE BYPASS FINO-M23 08/26/2005 73 130 ENET SERIES TERM FINO-M23 08/26/2005 MATERIAL/FINISH
NOTED AS D 051-6863 19
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U4300
CPU U2800
U2801
NEO 10S FANS
PAGE 43,48
TEMP SENSORS SMU RTC
J9602, J9603
PAGES 32,33 PAGE 28
PAGE 28
TMDS
EXT VGA 32-BIT
APPLE PI U6200
D PAGE 96 ELASTIC INTERFACE CLOCK
SMU SUPPLEMENTAL
D
667MHZ OR 733MHZ
BUFFER
y
BUTTONS
PAGE 62 J6700 ONBOARD MEMORY ALS
SYSTEM LED
APPLE PI
BATTERY
MAIN MEMORY
PAGE 42
r
U8400
U8900, U8901
U1900 PARALLEL
DIMM SERIES 64MX8 PAGES 29,30
PAGE 59
FRAME 64-BIT GPU PCIE
64-BIT
MAIN MEMORY TERM TERM MEMORY
BUFFER A
FRAME BUFFER
M23:RV370 XT
PCIE X16
2.5GHZ PAGE
KODIAK 1.8V/533MHZ
PAGE 61 PAGES 68 PAGES 67,70
82 CORE
PAGE 89 M23:1.8V/600MHZ M33:RV380 XT
M33:1.8V/700MHZ PAGE 19
a
PAGES 84,86,87,93 PAGE 67
MISC HYPERTRANSPORT
PAGE 20 PAGE 98
64-BIT
JE310/JE320/JE330 JE350
FRAME BUFFER
M23:1.8V/600MHZ 8-BIT USB BNDI
M33:1.8V/700MHZ HYPERTRANSPORT
1.2V/800MHZ
CONNECTORS INTERFACE
n
PAGE 143 PAGE 143
CONTROL = 2.5V
U2500 U9000, U9001
PULSAR2 FRAME I2C UE401 UE400
i
POWER CLOCKS BUFFER B PAGE 39
USB FLASH
HUB CTLR
C PAGE 25 PAGE 26 PAGE 90
1 2 3 4 5
PAGE 144 PAGE 144
C
USB
PAGE 142
UC200
UC500 JC150
USB 2.0 JE500
uPD720101 WIRELESS MEDIA CARD CONNECTOR
BOOTROM
m
PCI CONNECTOR CF SD
PAGE 145
PAGE 125 PAGE 122 PAGE 121
JC900
il
SATA
PAGE 119
HYPERTRANSPORT
SATA1
HARD DRIVE SATA/150
CONNECTOR
PCI
PAGE 103
1.2V/1.5GHZ
PAGE 127
SATA
PAGE 129 32-bit PCI (5V-3.3V/33MHz)
U2300
SATA2
GPIO/PCI64
SHASTA
e PAGE 24
PAGE 127
UATA
JC901
B B
r
UATA UATA/133 CORE NCs
OPTICAL
CONNECTOR 3.3V/133MHZ PAGE 23 PAGE 142
PAGE 129 ETHERNET FIREWIRE
I2S
PAGE 24
PAGE 131 PAGE 138 SCCA SCCB
I2S0 I2S1 I2S2
1394 OHCI (3.3V/98MHz)
8-bit TX & 8-bit RX
GMII (3.3V/125MHz)
P
8-bit TX/RX
UE700
S/PDIF OPTICAL OUT
JF303
AUDIO CODEC COMBO OUT
CONNECTOR
PCM3052A LINE OUT
PAGE 153
U1701
AMP LINE OUT
VESTA PAGE 147 PAGE 150
JF301
GIG ETHERNET FIREWIRE A SPEAKER System Block Diagram
PAGE 132 PAGE 139
AMP
SPEAKER
LINE IN CONNECTOR
A 0 1
AMP
PAGE 152
PAGE 153
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
PAGE 148
4 Diff pairs 2 Diff pairs
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
JD600 JEC00, JEC01
JF300 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
BNDI
ETHERNET FIREWIRE A LINE IN INTERFACE
II NOT TO REPRODUCE OR COPY IT
CONNECTOR CONNECTORS CONNECTOR
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
PAGE 136 PAGE 140
SIZE DRAWING NUMBER REV.
PAGE 153
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 2 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SYS_POWERUP_L
SMU
POWER SEQUENCE PIN
6 NC_SMU_PWRSEQ_P1_0 SMU_PWRSEQ_P1_0 28
6 NC_SMU_PWRSEQ_P1_4 SMU_PWRSEQ_P1_4 28
J700 SYS_POWERUP_L
PAGE 7
POWER CONNECTOR 13 12 TURN_ON_PP1V2_L SMU_PWRSEQ_P1_1 28
PWR_GOOD_PP1V5 SMU_PWRSEQ_P9_5 28
PP3V3_PWRON
D PP12V_ALL PP12V_RUN PP5V_RUN PP5V_ALL PP3V3_ALL PP3V3_RUN 16 15
PWR_GOOD_PP1V8
TURN_ON_PP3V3_PWRON_L
SMU_PWRSEQ_P9_6
SMU_PWRSEQ_P1_2
28
28
D
SMU_PWRSEQ_P1_3 28
y
FW CONN 20" PANEL POWER OPTICAL PCI BUS
17" LCD INVERTER AUDIO CODEC
PP1V5_PWRON
SWITCHER
a
PP1V2_ALL
SWITCHER
PAGE 13
r
VESTA CORE
PP2V5_ALL
1
R431
10K
5%
1/16W
MF-LF
2 402
n
PAGE 12
PULSAR
KODIAK CORE
i
PP2V5_RUN_CPU_AVDD PP2V5_GPU_A2VDD
CPU CORE PP4V5_RUN_AUDIO PP5V_PWRON PP3V3_PWRON
LINEAR LINEAR
C
C PP1V5_RUN SWITCHER LINEAR FET SWITCH FET SWITCH
PAGE 54 PAGE 85
FET SWITCH PAGE 50
PAGE 154 PAGE 16 PAGE 16
USB CONN MODEM & BT
PAGE 12 AUDIO CODEC USB2 HOST
EI
PP1V2_TPVDD
3
LINEAR PP1V5_PWRON 4 PS_1V_REF 8 LM339A
SOI-LF
PP1V8_TPVDD PP1V5_VDDC_CT V+
14
R430
m
PAGE 85 U400
GPU CORE PP1V8_PWRON PP2V5_ALL LINEAR LINEAR 1
100K 2
COMPARE_PP1V5 9
GND
SWITCHER SWITCHER LINEAR PAGE 85 PAGE 85
IN
5%
1/16W
12
il
MF-LF
PAGE 85 PAGE 11 PAGE 15 402 1 C430
VESTA 0.01UF
MAIN MEMORY PP1V2_PWRON PP1V2_RUN 20%
2 16V
CERM
PP1V8_GPU FET SWITCH FET SWITCH IN 402
PP1V8_RUN
LINEAR PAGE 13 PAGE 13
IN HT BUS
PAGE 85 SHASTA CORE
PP1V8_RUN
POWER SW
PP2V5_PWRON PP2V5_RUN
e
PAGE 11 PP2V5_ALL
GPU MEMORY
FET SWITCH FET SWITCH
PP2V5_ALL
PAGE 15 PAGE 15 PP5V_ALL
1
R442
B B
r
150K 1
PP0V9_GPU_VTT 5%
1/16W
R441
MF-LF 10K
LINEAR 2 402 3
5%
1/16W
6 LM339A MF-LF
4 PS_1V_REF 2 402
PAGE 91 V+ SOI-LF
1
R440 U400
1
100K 2 7
GND
COMPARE_PP1V8
5% 1 C441
P
12
1/16W
MF-LF 1 C440 0.1UF
1 20%
402
0.01UF R443 2 10V
CERM
20% 100K
2 16V
CERM 1% 402
402 1/16W
MF-LF
2 402
PP2V5_ALL
U400P2
4
3
LM339A Power Block Diagram
V+ SOI-LF
A U400
GND
2 SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
5
12 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 4 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROCESSORS ASICS
NEED TO UPDATED BIN CODES AS NOTES
TABLE_5_HEAD
TABLE_11_HEAD
PART # QTY DEVICE PACKAGE DESCRIPTION VALUE VOLT. WATT. TOL. REFERENCE DESIGNATOR(S) BOM OPTION PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_ITEM
TABLE_11_HEAD
343S0379 1 IC,KODIAK,V1.2,PBGA,200MM U1900 CRITICAL
D
337S3224
337S3220
1
1
PROCESSOR CBGA-576-1MM IC,GPUL,DD3.1,1.9G,85C
PROCESSOR CBGA-576-1MM IC,GPUL,DD3.1,2.1G,85C
1.9GHZ
2.1GHZ
1.10V
1.10V
45W
45W
50MV
50MV
U4300
U4300
17_INCH_LCD
20_INCH_LCD
TABLE_11_HEAD
CRITICAL
343S0377 1 IC,ASIC,SHASTA,V1.1,PBGA,LF U2300
TABLE_5_ITEM
CRITICAL
D
CRITICAL TABLE_5_ITEM
y
343S0356 1 IC,ASIC,VESTA,V1.3,LF U1701 CRITICAL
TABLE_5_ITEM
TABLE_ALT_HEAD
343S0319 1 IC,PULSAR2,100P,P8MM,BGA U2500 CRITICAL
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TABLE_ALT_ITEM
r
337S3225 337S3224 17_INCH_LCD U4300 IC,DD3.1,1.9G,1.15V
TABLE_ALT_ITEM
337S3226 337S3224 17_INCH_LCD U4300 IC,DD3.1,1.9G,1.20V
TABLE_ALT_ITEM
337S3227 337S3224 17_INCH_LCD U4300 IC,DD3.1,1.9G,1.25V
TABLE_ALT_ITEM
337S3228 337S3224 17_INCH_LCD U4300 IC,DD3.0X,1.9G,1.15V
TABLE_ALT_ITEM
337S3229 337S3224 17_INCH_LCD U4300 IC,DD3.0X,1.9G,1.20V
a
TABLE_ALT_ITEM
337S3230 337S3224 17_INCH_LCD U4300 IC,DD3.0X,1.9G,1.25V
TABLE_ALT_ITEM
337S3231 337S3224 17_INCH_LCD U4300 IC,DD3.0X,1.9G,1.30V
TABLE_ALT_ITEM
337S3221 337S3220 20_INCH_LCD U4300 IC,DD3.1,2.1G,1.15V
337S3222 337S3220 20_INCH_LCD U4300
TABLE_ALT_ITEM
IC,DD3.1,2.1G,1.20V
TABLE_ALT_ITEM
MISC PARTS TABLE_5_HEAD
337S3223 337S3220 20_INCH_LCD U4300 IC,DD3.1,2.1G,1.25V PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
n
TABLE_5_ITEM
051-6790 1 PCB,SCHEM,MLB,M23 SCH1 17_INCH_LCD
TABLE_5_ITEM
051-6863 1 PCB,SCHEM,MLB,M33 SCH1 20_INCH_LCD
i
TABLE_5_ITEM
820-1783 1 PCB,FAB,MLB,M23 MLB1 17_INCH_LCD CRITICAL
TABLE_5_ITEM
C 820-1766
062-2082
1
1
PCB,FAB,MLB,M33
SPEC,VENDOR PACKAGING PROCEDURE
MLB1
VPP1
20_INCH_LCD
TABLE_5_ITEM
CRITICAL
C
TABLE_5_ITEM
825-6447 1 BARCODE LABEL, MLB LBL1
TABLE_5_ITEM
341T1751 1 IC,FLASH,1MX8,3.3V,90NS UC500 CRITICAL
TABLE_5_ITEM
341T1752 1 PURCH ASSY, SMU BIG U2800 CRITICAL
TABLE_5_ITEM
603-7318 1 M23 CPU HEATSINK MECH1 17_INCH_LCD CRITICAL
m
TABLE_5_ITEM
603-7321 1 M33 CPU HEATSINK MECH1 20_INCH_LCD CRITICAL
TABLE_5_ITEM
603-7319 1 M23 GPU HEATSINK MECH2 17_INCH_LCD CRITICAL
TABLE_5_ITEM
il
603-7322 1 M33 GPU HEATSINK MECH2 20_INCH_LCD CRITICAL
TABLE_5_ITEM
603-7320 1 M23 NB HEATSINK MECH3 17_INCH_LCD CRITICAL
TABLE_5_ITEM
603-7323 1 M33 NB HEATSINK MECH3 20_INCH_LCD CRITICAL
TABLE_5_ITEM
875-1905 1 CPU GAP FILLER GAP1
TABLE_5_ITEM
860-0708 2 M33 ODD NUTS SDFC900,SDFC901 20_INCH_LCD CRITICAL
e
ALTERNATES
TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
LED700,LED702 TABLE_ALT_ITEM
B 378S0140 378S0141 KINGBRIGHT LED
B
r
TABLE_ALT_ITEM
343S0388 343S0356 U1701 VESTA A4
TABLE_ALT_ITEM
126S0078 126S0086 C722 EL CAP
TABLE_ALT_ITEM
126S0068 126S0088 CF000 EL CAP
A
P SYNC_MASTER=FINO-M23
Table Items
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
A
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 5 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NO TEST XW NETS
NO_TEST=YES TP_FBBCS1_L
NO_TEST=YES GND_U1100 11 NO_TEST=YES GND_GPU_TPVSS 93 NO_TEST=YES GND_NEC_AVSS_R 142
I307
I826 NO_TEST=YES
NO_TEST=YES
AUD_4V5_FB
ITS_RUNNING
87
154
7
FUNC TEST NETS
I947 I998 I1012 I837
NO_TEST=YES GND_U1200 12 NO_TEST=YES GND_GPU_TXVSSR NO_TEST=YES GND_AUDIO_SPKRAMP_PLANE 152 154 NO_TEST=YES LED801_1
I948
I949 NO_TEST=YES GND_U1300 13
I1000
I999 NO_TEST=YES GND_GPU_VSSDI
93
93
I1014
I1013 NO_TEST=YES GND_AUDIO_CODEC 147 148 150 154
I836
I839 NO_TEST=YES LED802_1
8
8
NOTES FROM TOM FUSSELMAN
NO_TEST=YES PP_2V5PWRONNBMISC 20 NO_TEST=YES GND_GPU_AVSSN 93 NO_TEST=YES KPGND2_FMAX 55 NO_TEST=YES PCI_CLK66M_SB_INT_R 26
I950
NO_TEST=YES PP_1V2PWRONSBVCORE 23
I1002
NO_TEST=YES GND_GPU_AVSSQ 93
I1016
NO_TEST=YES TDIODE_POS_FMAX 55
I841
NO_TEST=YES Q800_D 8
PLACE TWO TEST POINTS ON TOP SIDE
I951 I1001 I1015 I846
I952 NO_TEST=YES PP_3V3PWRONSBPCI64 23 I1003 NO_TEST=YES GND_GPU_A2VSSN 93 I1017 NO_TEST=YES TDIODE_NEG_FMAX 55 I847 NO_TEST=YES Q800_G 8 FOR PP3V3_ALL AND GND
NO_TEST=YES PP_2V5PWRONSB 23 NO_TEST=YES GND_GPU_A2VSSQ 93 NO_TEST=YES DAGND 55 NO_TEST=YES Q801_B 8
I953
NO_TEST=YES PP_1V2PWRONSBPLL45VDD 24
I1004
NO_TEST=YES KOD_L15_GND 98 101
I1018
NO_TEST=YES INA138_OUT 55
I848
NO_TEST=YES Q802_B 8
PLACE WITHIN 1 INCH OF EACH OTHER
D
I954
I984 NO_TEST=YES PP_OVDD_PULSAR1 25
I1005
I1007 NO_TEST=YES PP_3V3SBPCI_B9
I1019 I849
I850 NO_TEST=YES Q802_E 8 USE FAT TRACES D
I985 NO_TEST=YES PP_1V2PWRONPULSAR1 25 I1006 NO_TEST=YES PP_2V5PWRONSB_B9 119 I1020 NO_TEST=YES RAMCLK_AVSS 62 I851 NO_TEST=YES Q803_B 8
y
I986 NO_TEST=YES PP_1V5PULSAR2 25 I1008 NO_TEST=YES PP_VIOPCIUSB2_C2 122 I1022 NO_TEST=YES PP12V_AUDIO_SPKRAMP 7 152 I429 NO_TEST=YES TP_USB2_PWREN<0> 143
I987 NO_TEST=YES PP_1V5PWRONPULSAR2 25 I1010 NO_TEST=YES PP_1V2PWRONDISKSB_CC 127 I1024 NO_TEST=YES GND_AUDIO 7 154 I428 NO_TEST=YES TP_USB2_PWREN<1> 143
I988 NO_TEST=YES GND_SMU_AVSS 28 55 I1009 NO_TEST=YES PP2V5_VESTA_BIASVDD1 132 I1023 NO_TEST=YES GND_AUDIO_SPKRAMP 7 152 154 I375 NO_TEST=YES TP_SB_FSTEST 24
I1080 FUNC_TEST=TRUE PPVCORE_CPU 50
I989 NO_TEST=YES PP_3V3ALLSMUAVCC 28 I1011 NO_TEST=YES PP2V5_VESTA_XTALVDD1 132 I376 NO_TEST=YES TP_SB_PLLTEST 24
I1088 FUNC_TEST=TRUE =PP3V3_ALL_SMU 7 28 29
I990 NO_TEST=YES PP_3V3ALLSMU 28 I1027 NO_TEST=YES PP1V2_VESTA_PLLVDD1 132 I1035 NO_TEST=YES KOD_H05_GND 82 97 I348 NO_TEST=YES TP_USB2_PWREN<2> 143
r
I1089 FUNC_TEST=TRUE =PP5V_RUN_CPU 7 8
I991 NO_TEST=YES PP_VEINB 41 I1026 NO_TEST=YES PP1V2_VESTA_PLLVDD2 139 I1034 NO_TEST=YES KOD_K07_GND 82 97 I350 NO_TEST=YES TP_USB2_PWREN<3> 143
I992 NO_TEST=YES GND_CPU_AVDD 48 I1029 NO_TEST=YES PP2V5_VESTA_BIASVDD2 139 I1037 NO_TEST=YES KOD_G10_GND 82 97 I349 NO_TEST=YES TP_USB2_PWREN<4> 143
I1091 FUNC_TEST=TRUE SYS_POWER_BUTTON_L 28 29
I993 NO_TEST=YES VC_AGND 50 I1028 NO_TEST=YES PP2V5_VESTA_XTALVDD2 139 I1036 NO_TEST=YES KOD_J13_GND 82 97 I356 NO_TEST=YES TP_NEC_NTEST1 122
I1092 FUNC_TEST=TRUE POWER_BUTTON_L 29
I994 NO_TEST=YES VC_OUTSEN_R 50 I1031 NO_TEST=YES PP1V2_VESTA_FAVDDL 139 I1039 NO_TEST=YES KOD_L13_GND 82 97 I357 NO_TEST=YES TP_NEC_SMC 122
I1093 FUNC_TEST=TRUE RESET_BUTTON_L 29
I995 NO_TEST=YES KPVDD2_FMAX 55 I1030 NO_TEST=YES PP2V5_VESTA_FAVDDM 139 I1038 NO_TEST=YES KOD_H08_GND 82 97 I358 NO_TEST=YES TP_NEC_SMI_L 122
I1094 FUNC_TEST=TRUE SMU_RESET_L 28 29
I996 NO_TEST=YES GND_GPU_PVSS 86 I1033 NO_TEST=YES PP3V3_VESTA_FAVDDH 139 I1041 NO_TEST=YES PCIE_SLOTA_PRSNT_L 82 84 I360 NO_TEST=YES TP_NEC_SRCLK 122
I1095 FUNC_TEST=TRUE SYS_POWERUP_L 7 12 28 50 85
NO_TEST=YES GND_GPU_MPVSS NO_TEST=YES PP3V3_PWRON_NEC_AVDD NO_TEST=YES U8500_GND NO_TEST=YES TP_NEC_SRMOD
a
I997 87 I1032 142 I1040 85 I362 122
I1043 NO_TEST=YES GND_AUD_LOAMP 150 154 I1044 NO_TEST=YES GND_AUD_LOAMP_CHGPMP 150 154 I361 NO_TEST=YES TP_NEC_TEST 122
I1042 NO_TEST=YES GND_AUDIO_MIC 153 154
I883 NO_TEST=YES UATA_DASP_L_DS 129
TOP SIDE ONLY
I1263 NO_TEST=YES RFBD<19> 88 89
EE IDENTIFIED NO TEST NETS I1264 NO_TEST=YES RFBD<18> 88 89 I1335 FUNC_TEST=TRUE SMU_BOOT_SCLK 28 29
I1336 FUNC_TEST=TRUE SMU_BOOT_RXD 28 29
I1266 NO_TEST=YES RFBD<16> 88 89 I1337 FUNC_TEST=TRUE SMU_BOOT_CE 28 29
n
I1267 NO_TEST=YES RFBD<15> 88 89 I1338 FUNC_TEST=TRUE SMU_BOOT_CNVSS 28 29
I955 NO_TEST=YES NC_EI_NB_TO_CPU_B_CLK_P 56 I1096 NO_TEST=YES KPVDD2 48 50 55
I1268 NO_TEST=YES RFBD<14> 88 89 I1339 FUNC_TEST=TRUE SMU_BOOT_TXD 28 29
I957 NO_TEST=YES NC_EI_NB_TO_CPU_B_CLK_N 56 I1097 NO_TEST=YES KPGND2 48 50 55 I1197 NO_TEST=YES RFBD<126> 88 90
I1269 NO_TEST=YES RFBD<13> 88 89 I1340 FUNC_TEST=TRUE SMU_BOOT_BUSY 28 29
NO_TEST=YES NC_EI_NB_TO_CPU_B_AD<0..43> 56 NO_TEST=YES CPU_DIODE_POS 48 55 NO_TEST=YES RFBD<125> 88 90
i
I958 I1098 I1200
SMU_MANUAL_RESET_L
NC_EI_NB_TO_CPU_B_SR_P<0..1> CPU_DIODE_NEG RFBD<124> I1090 FUNC_TEST=TRUE 29
I959 NO_TEST=YES 56 I1099 NO_TEST=YES 48 55 I1199 NO_TEST=YES 88 90
I1271 NO_TEST=YES RFBD<11> 88 89
I960 NO_TEST=YES NC_EI_NB_TO_CPU_B_SR_N<0..1> 56 I1100 NO_TEST=YES FMAXT_P 55
C I961 NO_TEST=YES
NO_TEST=YES
NC_EI_CPU_B_TO_NB_CLK_P
NC_EI_CPU_B_TO_NB_CLK_N
56
56
I1101 NO_TEST=YES
NO_TEST=YES
FMAXT_M
CORE_ISNS_P
55
55
I1202 NO_TEST=YES
NO_TEST=YES
RFBD<122>
RFBD<121>
88 90
88 90
I1272 NO_TEST=YES RFBD<10> 88 89
C
I962 I1102 I1203
I1273 NO_TEST=YES RFBD<8> 88 89
I963 NO_TEST=YES NC_EI_CPU_B_TO_NB_AD<0..43> 56 I1103 NO_TEST=YES CORE_ISNS_M 55 I1204 NO_TEST=YES RFBD<120> 88 90
NO_TEST=YES RFBD<7> 88 89 PP1V2_ALL PP3V3_ALL PP5V_ALL
I1275
I964 NO_TEST=YES NC_EI_CPU_B_TO_NB_SR_P<0..1> 56 I1104 NO_TEST=YES PPV_RUN_CPU_AVDD_R_L 48
I1277 NO_TEST=YES RFBD<6> 88 89
I965 NO_TEST=YES NC_EI_CPU_B_TO_NB_SR_N<0..1> 56 I1105 NO_TEST=YES NC_CLK_RAI_GIGE_25MHZ 27 I1206 NO_TEST=YES RFBD<118> 88 90
I1276 NO_TEST=YES RFBD<5> 88 89 7 PP1V2_ALL FUNC_TEST=TRUE
I1106 NO_TEST=YES NC_CLK_RAI_REFCLK_66M 27 I1207 NO_TEST=YES RFBD<117> 88 90
7 PP3V3_ALL FUNC_TEST=TRUE
I1107 NO_TEST=YES NC_CPU_B_TBEN_CLK_US 26 I1208 NO_TEST=YES RFBD<116> 88 90
I1278 NO_TEST=YES RFBD<3> 88 89 7 PP5V_ALL FUNC_TEST=TRUE
I1108 NO_TEST=YES NC_PMR_CLK_DIS_L 20
I1280 NO_TEST=YES RFBD<2> 88 89
NO_TEST=YES NC_NB_CPU_A1_INT_L NO_TEST=YES NC_I2S2_MCLK NO_TEST=YES RFBD<114>
m
I969 56 I1109 154 I1210 88 90
I1281 NO_TEST=YES RFBD<1> 88 89
NO_TEST=YES NC_NB_CPU_B0_INT_L 56 NO_TEST=YES NC_SATA_RXD_N2_C 129 NO_TEST=YES RFBD<113> 88 90 PP1V8_RUN PP2V5_RUN PP3V3_RUN PP12V_RUN
I971 I1110 I1211
RAM_DQ_R<63>
NC_NB_CPU_B1_INT_L NC_SATA_RXD_P2_C RFBD<112> I1283 NO_TEST=YES 61 68 70
I972 NO_TEST=YES 56 I1111 NO_TEST=YES 129 I1212 NO_TEST=YES 88 90
I973 NO_TEST=YES NC_CPU_A1_QACK_L 56 I1112 NO_TEST=YES NC_SATA_TXD_N2 129 7 PP1V8_RUN FUNC_TEST=TRUE
il
I975 NO_TEST=YES NC_CPU_B0_QACK_L 56 I1113 NO_TEST=YES NC_SATA_TXD_P2 129 I1214 NO_TEST=YES RFBD<110> 88 90 7 PP2V5_RUN FUNC_TEST=TRUE
I1286 NO_TEST=YES RAM_DQ_R<60> 61 68 70
I974 NO_TEST=YES NC_CPU_B1_QACK_L 56 I1114 NO_TEST=YES TP_SB<29> 142 I1215 NO_TEST=YES RFBD<109> 88 90 16 7 PP3V3_RUN FUNC_TEST=TRUE
I1285 NO_TEST=YES RAM_DQ_R<59> 61 68 70
I976 NO_TEST=YES NC_HT_MB_TO_NB_CAD_P<8..15> 101 I1115 NO_TEST=YES TP_SB<28> 142 I1216 NO_TEST=YES RFBD<108> 88 90 7 PP12V_RUN FUNC_TEST=TRUE
I1288 NO_TEST=YES RAM_DQ_R<58> 61 68 70
I978 NO_TEST=YES NC_HT_MB_TO_NB_CAD_N<8..15> 101 I1116 NO_TEST=YES TP_SB<27> 142
I1287 NO_TEST=YES RAM_DQ_R<57> 61 68 70
I977 NO_TEST=YES NC_HT_NB_TO_MB_CAD_P<8..15> 101 I1117 NO_TEST=YES TP_SB<26> 142 I1218 NO_TEST=YES RFBD<106> 88 90
I1289 NO_TEST=YES RAM_DQ_R<56> 61 68 70
NO_TEST=YES NC_HT_NB_TO_MB_CAD_N<8..15> 101 NO_TEST=YES TP_SB<25> 142 NO_TEST=YES RFBD<105> 88 90 PP1V5_PWRON
I982 I1118 I1220
I1045 NO_TEST=YES NC_CLK_RAI_200M_N<0> 27 I1120 NO_TEST=YES TP_SB<24> 142 I1219 NO_TEST=YES RFBD<104> 88 90
I1292 NO_TEST=YES RAM_DQ_R<54> 61 68 70 7 PP1V5_PWRON FUNC_TEST=TRUE
I1046 NO_TEST=YES NC_CLK_RAI_200M_P<0> 27 I1121 NO_TEST=YES TP_SB<23> 142
I1291 NO_TEST=YES RAM_DQ_R<53> 61 68 70
I1047 NO_TEST=YES NC_CLK_RAI_PCIEA_N<0> 27 I1122 NO_TEST=YES TP_SB<22> 142 I1221 NO_TEST=YES RFBD<102> 88 90
I1293 NO_TEST=YES RAM_DQ_R<52> 61 68 70
I1048 NO_TEST=YES NC_CLK_RAI_PCIEA_P<0> 27 I1123 NO_TEST=YES TP_SB<21> 142 I1223 NO_TEST=YES RFBD<101> 88 90
e
I1049 NO_TEST=YES NC_CLK_RAI_PCIEB_N<0> 27 I1124 NO_TEST=YES TP_SB<20> 142 I1224 NO_TEST=YES RFBD<100> 88 90 GND FUNC_TEST=TRUE
I1294 NO_TEST=YES RAM_DQ_R<50> 61 68 70
I1050 NO_TEST=YES NC_CLK_RAI_PCIEB_P<0> 27 I1125 NO_TEST=YES TP_SB<19> 142
I1297 NO_TEST=YES RAM_DQ_R<49> 61 68 70
I1051 NO_TEST=YES NC_CLK_RAI_PCIEC_N<0> 27 I1126 NO_TEST=YES TP_SB<18> 142 I1226 NO_TEST=YES RFBD<98> 88 90
I1296 NO_TEST=YES RAM_DQ_R<48> 61 68 70
I1052 NO_TEST=YES NC_CLK_RAI_PCIEC_P<0> 27 I1127 NO_TEST=YES TP_SB<17> 142 I1227 NO_TEST=YES RFBD<97> 88 90
B NO_TEST=YES NC_A_AVREG_0 NO_TEST=YES TP_SB<16> NO_TEST=YES RFBD<96>
B
r
I1054 82 I1128 142 I1228 88 90
I1299 NO_TEST=YES RAM_DQ_R<46> 61 68 70
I1053 NO_TEST=YES NC_A_AVREG_1 82 I1129 NO_TEST=YES TP_SB<15> 142 I1229 NO_TEST=YES RFBD<95> 88 90
I1301 NO_TEST=YES RAM_DQ_R<45> 61 68 70
I1055 NO_TEST=YES NC_A_AVREG_2 82 I1130 NO_TEST=YES TP_SB<14> 142 I1230 NO_TEST=YES RFBD<94> 88 90
I1300 NO_TEST=YES RAM_DQ_R<44> 61 68 70
I1057 NO_TEST=YES NC_CPU_B_APSYNC 27 I1131 NO_TEST=YES TP_SB<13> 142
I1302 NO_TEST=YES RAM_DQ_R<43> 61 68 70 I1341 NO_TEST=YES RAM_DQ_R<9> 61 68 69
I1056 NO_TEST=YES NC_EI_CPU_B_SYSCLK_N 27 I1132 NO_TEST=YES TP_SB<12> 142 I1232 NO_TEST=YES RFBD<92> 88 90
I1060 NO_TEST=YES NC_EI_CPU_B_SYSCLK_P 27 I1133 NO_TEST=YES TP_SB<11> 142 I1233 NO_TEST=YES RFBD<91> 88 90
I1303 NO_TEST=YES RAM_DQ_R<41> 61 68 70 I1343 NO_TEST=YES RAM_DQ_R<8> 61 68 69
I1058 NO_TEST=YES NC_HT_NB_TO_MB_CLK_N<1> 101 I1134 NO_TEST=YES TP_SB<10> 142 I1234 NO_TEST=YES RFBD<90> 88 90
I1306 NO_TEST=YES RAM_DQ_R<40> 61 68 70 I1344 NO_TEST=YES RAM_DQ_R<7> 61 68 69
I1059 NO_TEST=YES NC_HT_NB_TO_MB_CLK_P<1> 101 I1135 NO_TEST=YES TP_SB<9> 142
I1305 NO_TEST=YES RAM_DQ_R<37> 61 68 70 I1345 NO_TEST=YES RAM_DQ_R<6> 61 68 69
NO_TEST=YES NC_J2904_11 NO_TEST=YES TP_SB<8> NO_TEST=YES RFBD<88>
P
I1062 29 I1136 142 I1236 88 90
I1307 NO_TEST=YES RAM_DQ_R<38> 61 68 70 I1346 NO_TEST=YES RAM_DQ_R<5> 61 68 69
I1061 NO_TEST=YES NC_J2904_12 29 I1137 NO_TEST=YES TP_SB<7> 142 I1237 NO_TEST=YES RFBD<87> 88 90
I1063 NO_TEST=YES NC_NCV1009_1 55 I1138 NO_TEST=YES TP_SB<6> 142 I1238 NO_TEST=YES RFBD<86> 88 90
I1310 NO_TEST=YES RAM_DQ_R<36> 61 68 70 I1348 NO_TEST=YES RAM_DQ_R<3> 61 68 69
I1065 NO_TEST=YES NC_NCV1009_2 55 I1139 NO_TEST=YES TP_SB<5> 142 I1239 NO_TEST=YES RFBD<85> 88 90
I1349 NO_TEST=YES RAM_DQ_R<2> 61 68 69
I1064 NO_TEST=YES NC_NCV1009_3 55 I1140 NO_TEST=YES TP_SB<4> 142
I1311 NO_TEST=YES RAM_DQ_R<34> 61 68 70 I1350 NO_TEST=YES RAM_DQ_R<1> 61 68 69
I1068 NO_TEST=YES NC_NCV1009_4 55 I1141 NO_TEST=YES TP_SB<3> 142 I1242 NO_TEST=YES RFBD<83> 88 90
I1313 NO_TEST=YES RAM_DQ_R<33> 61 68 70
I1066 NO_TEST=YES NC_NCV1009_5 55 I1142 NO_TEST=YES TP_SB<2> 142 I1241 NO_TEST=YES RFBD<82> 88 90
I1312 NO_TEST=YES RAM_DQ_R<32> 61 68 70
I1067 NO_TEST=YES NC_NCV1009_ADJ 55 I1143 NO_TEST=YES TP_SB<1> 142 I1244 NO_TEST=YES RFBD<81> 88 90
I1069 NO_TEST=YES NC_RAM_ARB0_REF25MHZ 27 I1155 NO_TEST=YES TP_SB<0> 142
I1314 NO_TEST=YES RAM_DQ_R<30> 61 68 69
I1070 NO_TEST=YES NC_RAM_ARB1_REF25MHZ 27 I1156 NO_TEST=YES RFBD<61> 88 89 I1245 NO_TEST=YES RFBD<79> 88 90
I1316 NO_TEST=YES RAM_DQ_R<29> 61 68 69
I1071 NO_TEST=YES NC_SMU_PWRSEQ_P1_0 4 I1157 NO_TEST=YES RFBD<60> 88 89 I1246 NO_TEST=YES RFBD<78> 88 90
I1317 NO_TEST=YES RAM_DQ_R<28> 61 68 69
I1072 NO_TEST=YES NC_SMU_PWRSEQ_P1_4 4 I1158 NO_TEST=YES RFBD<59> 88 89
I1248 NO_TEST=YES RFBD<76> 88 90
I1318 NO_TEST=YES RAM_DQ_R<31> 61 68 69
I1160 NO_TEST=YES RFBD<38> 88 89 I1179 NO_TEST=YES RFBD<57> 88 89 I1249 NO_TEST=YES RFBD<75> 88 90
I1320 NO_TEST=YES RAM_DQ_R<25> 61 68 69
I1161 NO_TEST=YES RFBD<37> 88 89 I1181 NO_TEST=YES RFBD<56> 88 89 I1250 NO_TEST=YES RFBD<74> 88 90
I1322 NO_TEST=YES RAM_DQ_R<24> 61 68 69
I1162 NO_TEST=YES RFBD<36> 88 89
I1183 NO_TEST=YES RFBD<54> 88 89 I1252 NO_TEST=YES RFBD<72> 88 90
I1324 NO_TEST=YES RAM_DQ_R<22> 61 68 69
FUNC TEST 1 OF 2
I1164 NO_TEST=YES RFBD<34> 88 89 I1182 NO_TEST=YES RFBD<53> 88 89 I1253 NO_TEST=YES RFBD<71> 88 90
NO_TEST=YES RAM_DQ_R<21>
A I1165 NO_TEST=YES
NO_TEST=YES
RFBD<33>
RFBD<32>
88 89
88 89
I1184 NO_TEST=YES RFBD<52> 88 89 I1254 NO_TEST=YES
NO_TEST=YES
RFBD<70>
RFBD<69>
88 90
88 90
I1323
I1325 NO_TEST=YES RAM_DQ_R<20>
61 68 69
61 68 69
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
I1166 I1255
I1326 NO_TEST=YES RAM_DQ_R<19> 61 68 69
I1167 NO_TEST=YES RFBD<31> 88 89 I1185 NO_TEST=YES RFBD<50> 88 89
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
I1168 NO_TEST=YES RFBD<30> 88 89 I1188 NO_TEST=YES RFBD<49> 88 89 I1257 NO_TEST=YES RFBD<67> 88 90 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
I1327 NO_TEST=YES RAM_DQ_R<17> 61 68 69 AGREES TO THE FOLLOWING
I1187 NO_TEST=YES RFBD<48> 88 89 I1258 NO_TEST=YES RFBD<66> 88 90
I1329 NO_TEST=YES RAM_DQ_R<16> 61 68 69 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
I1170 NO_TEST=YES RFBD<28> 88 89 I1189 NO_TEST=YES RFBD<47> 88 89 I1259 NO_TEST=YES RFBD<65> 88 90
II NOT TO REPRODUCE OR COPY IT
I1171 NO_TEST=YES RFBD<27> 88 89
I1330 NO_TEST=YES RAM_DQ_R<14> 61 68 69 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I1172 NO_TEST=YES RFBD<26> 88 89 I1190 NO_TEST=YES RFBD<45> 88 89
I1333 NO_TEST=YES RAM_DQ_R<13> 61 68 69
I1173 NO_TEST=YES RFBD<25> 88 89 I1192 NO_TEST=YES RFBD<44> 88 89 I1262 NO_TEST=YES RFBD<62> 88 89 SIZE DRAWING NUMBER REV.
NO_TEST=YES RAM_DQ_R<12>
NO_TEST=YES RFBD<23> NO_TEST=YES RFBD<42>
I1332
I1334 NO_TEST=YES RAM_DQ_R<11>
61 68 69
61 68 69 D 051-6863 19
I1175 88 89 I1193 88 89
APPLE COMPUTER INC.
NO_TEST=YES RFBD<22> NO_TEST=YES RFBD<41> SCALE SHT OF
I1176
I1177 NO_TEST=YES RFBD<21>
88 89
88 89
I1196
I1195 NO_TEST=YES RFBD<40>
88 89
88 89 NONE 6 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RUN RAILS
ONLY ON IN RUN PWRON RAILS ALL RAILS
ON IN RUN AND SLEEP ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
PP5V_PWRON PP12V_ALL
PP12V_RUN PP12V_ALL =PP12V_ALL_GPU 85
62 PP5V_PWRON =PP5V_PWRON_USB 143 MAKE_BASE=TRUE
CRITICAL VOLTAGE=5V VOLTAGE=12V =PP12V_ALL_FW 140
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
VOLTAGE=12V MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.2MM
PP3V3_ALL PP12V_RUN PP5V_RUN PP3V3_RUN J700 PP3V3_ALL PP5V_ALL PP12V_ALL 6 PP12V_RUN
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
PP5V_ALL =PP12V_CPU
HM9607E-P2 50 55
D 1
M-RT-TH1
2
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER =PP12V_GPU 96
PP3V3_PWRON
=PP5V_PWRON_BNDI 143
6 PP5V_ALL
D
1 VOLTAGE=5V
R702 MIN_LINE_WIDTH=0.6MM
y
3 4 MIN_NECK_WIDTH=0.2MM
10K 5 6
MAKE_BASE=TRUE =PP5V_ALL_GPU 85
5% PP3V3_PWRON =PP3V3_PWRON_SB 20 23 24 56 119 NET_SPACING_TYPE=POWER
1/16W VOLTAGE=3.3V PP3V3_ALL
MF-LF 7 8 MIN_LINE_WIDTH=0.6MM =PP3V3_PWRON_SB_PCI64 23
2 402 9 10 MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE =PP3V3_PWRON_SB_PCI32 23 6PP3V3_ALL =PP3V3_ALL_SMU 6 28 29
28 SYS_POWERFAIL_L 11 12
1
C722 NET_SPACING_TYPE=POWER
=PP3V3_PWRON_PULSAR 25
MAKE_BASE=TRUE
VOLTAGE=3.3V =PP3V3_ALL_CPU 55
330UF
r
13 14 MIN_LINE_WIDTH=0.6MM
92 LCD_PWM INV_CUR_HI 20% =PP3V3_PWRON_USB MIN_NECK_WIDTH=0.2MM
92
2 6.3V
ELEC
XW701
SM =PP3V3_PWRON_BT
142 144 145
121
NET_SPACING_TYPE=POWER
6.3X8-SM
1 2 PP12V_AUDIO_SPKRAMP 6 152 =PP3V3_PWRON_CPU 55 =PP3V3_FW 140
XW705 XW708
SM
PP2V5_ALL =PP3V3_ENETFW 17 132 139
SM =PP3V3_ENET 132 136 =PP3V3_ALL_GPU 85
1 2
NET_SPACING_TYPE=POWER 1 2 =PP3V3_PWRON_SMU 28 30 43
VOLTAGE=0V PP2V5_ALL =PP2V5_ENETFW
MIN_LINE_WIDTH=0.60MM XW700 =PP3V3_PWRON_BNDI MAKE_BASE=TRUE
17 132 139
a
MIN_NECK_WIDTH=0.20MM SM PP2V5_PWRON VOLTAGE=2.5V
PP5V_RUN MIN_LINE_WIDTH=0.6MM
P/N 518-0188 1 2 PP5V_AUDIO_ANALOG 150 153 154 MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
PP1V2_ALL
PP5V_RUN VOLTAGE=5V =PP5V_PATA 129 PP2V5_PWRON =PP2V5_PWRON_SB 23 24 119 138
MAKE_BASE=TRUE VOLTAGE=2.5V
MIN_LINE_WIDTH=0.6MM =PP2V5_PWRON_PULSAR 25 6 PP1V2_ALL
PP3V3_ALL MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM =PP5V_GPU MAKE_BASE=TRUE =PP2V5_ENET 136 VOLTAGE=1.2V =PP1V2_ENETFW 17 132 139
NET_SPACING_TYPE=POWER NET_SPACING_TYPE=POWER MIN_LINE_WIDTH=0.6MM
=PP5V_RUN_CPU 6 8 =PP2V5_PWRON_NB_HT 98 MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
=PP2V5_PWRON_NB_PCIE 82
1 C700 =PP2V5_PWRON_HT GND RAILS
n
98 103
PP1V8_PWRON
CRITICAL 0.1UF =PP2V5_PWRON_NB_MISC 20 28 30 39
20%
U700 10V
2 CERM PP3V3_RUN
PP1V8_PWRON =PP1V8_PWRON_NBMEM
XW702
SM
14 74LC125 402
MIN_LINE_WIDTH=0.6MM
20 39 58 59
i
VOLTAGE=3.3V MIN_NECK_WIDTH=0.2MM =PP1V8_PWRON_RAM_I2C_VDD 67 154 6 GND_AUDIO 1 2
85 50 28 12 6 SYS_POWERUP_L 2 3 SYS_POWERUP_L_BUF 7 16 96 16 6 PP3V3_RUN =PP3V3_GPU 85 92 93 96 VOLTAGE=2.5V
MIN_LINE_WIDTH=0.6MM MAKE_BASE=TRUE =PP1V8_PWRON_RAM
125 MIN_NECK_WIDTH=0.2MM =PP3V3_AUDIO 147 152 153 154 NET_SPACING_TYPE=POWER
62
XW706
C 7 1 TSSOP MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER =PP3V3_RUN_CPU
=PP3V3_PATA
54 55
=PP1V8_PWRON_DIMM
NOSTUFF
67 69 70
1
SM
2 C
129
PP1V5_PWRON R711
=PP3V3_SB_PCI
1
0 2 =PP1V5_PWRON_PULSAR
=PP3V3_PCI 121 125
6 PP1V5_PWRON 5%
7 25
XW703
SM
=PPVIO_PCI_USB2 122 MAKE_BASE=TRUE 1/16W
VOLTAGE=1.5V MF-LF 154 152 6 GND_AUDIO_SPKRAMP 1 2
PP5V_ALL PP3V3_PWRON PP3V3_RUN =PP3V3_RUN_PULSAR 25 MIN_NECK_WIDTH=0.2MM 402
MIN_LINE_WIDTH=0.6MM =PPVCORE_PWRON_NB
DEVELOPMENT PP3V3_RUN_SB 119 NET_SPACING_TYPE=POWER
19
XW707
R710 R700 R701 =PP3V3_RUN_SB_PCI 24
PP1V2_PWRON =PPVCORE_PWRON_NB_PCIE 82 SM
1
1.5K 2 ITS_PLUGGED_IN 1
820 2 ITS_ALIVE 330 =PP3V3_RUN_I2C
=PPVCORE_PWRON_NB_HT 98 1 2
m
39
1 2 6 ITS_RUNNING PP1V2_PWRON =PP1V2_PWRON_SB_HT 103
5% 5% PP2V5_RUN =PP3V3_RUN_SMU 20 28 30 MIN_LINE_WIDTH=0.6MM
1/10W 1/10W 5% MIN_NECK_WIDTH=0.2MM =PP1V2_PWRON_DISK_SB 127
MF-LF 1 MF-LF 1 1/10W DEVELOPMENT VOLTAGE=1.2V
603 LED702 603 LED700 MF-LF
603 LED701
1
6 PP2V5_RUN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
=PP1V2_PWRON_SB 24 CHASSIS GND
il
GREEN-3.6MCD GREEN-3.6MCD =PP2V5_RUN_I2C =PP1V2_PWRON_SB_VCORE 23
2.0X1.25MM-SM 2.0X1.25MM-SM GREEN-3.6MCD VOLTAGE=2.5V 39
2.0X1.25MM-SM
MIN_LINE_WIDTH=0.6MM
2 2 MIN_NECK_WIDTH=0.2MM =PP1V2_PWRON_PULSAR 25
2 NET_SPACING_TYPE=POWER
PP1V8_RUN =PP1V2_PWRON_HT_NBTX 98 96 GND_CHASSIS_RIGHT
SILKSCREEN:1 SILKSCREEN:2 SILKSCREEN:RUN MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
VOLTAGE=0
6 PP1V8_RUN =PPV_GPU_MEM 87 89 90 91 MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.8V 12 PP1V5_PWRON_PULSAR =PP1V5_PWRON_PULSAR 7 25 NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE =PP1V8_RUN_RAM 61 62 VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.5MM =PP1V5_PULSAR 25
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=POWER MAKE_BASE=TRUE =PPV_PWRON_NB_REFCLK 42 59 96 GND_CHASSIS_VGA NOSTUFF
136 GND_CHASSIS_RJ45 R721
GND_CHASSIS_FIREWIRE 1
0 2
140
5%
e
PP1V5_RUN 1/16W
MF-LF
OMIT 96 GND_CHASSIS_TMDS 402
PP1V5_RUN MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE
VOLTAGE=1.5V MIN_LINE_WIDTH=0.60MM
MAKE_BASE=TRUE =PPOVDD_PULSAR 25 GPU MOUNTING ZH700 VOLTAGE=0V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM =PPV_EI_CPU 29 30 47 48 56
4P75R4
NET_SPACING_TYPE=POWER ZH700P1 1 GND_CHASSIS_LEFT
B =PPV_EI_NB NOSTUFF MIN_NECK_WIDTH=0.2MM
B
r
41 42 56
MAKE_BASE=TRUE
OMIT OMIT VOLTAGE=0
CHASSIS MOUNTING
ZH704 1 C704 ZH701 MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=POWER
4P25R3P5 0.01UF 4P75R4 143 GND_CHASSIS_USB OUT
20%
ZH704P1 2 16V
CERM
1 154 153 GND_CHASSIS_AUDIO_EXTERNAL
402
OMIT OMIT
NOSTUFF ZH705 ZH702
1 C705 4P25R3P5 4P75R4
0.01UF ZH705P1 ZH702P1 1
P
20%
PPVCORE_GPU 16V
86 85 2 CERM
MAKE_BASE=TRUE 402 OMIT OMIT
GND_CHASSIS_BNDI HS_SDF801
=PP1V2_GPU_PCIE 84 NOSTUFF ZH706 NOSTUFF ZH703 143
MIN_NECK_WIDTH=0.2MM
8
1 C706ZH706P14P25R3P5
1
1 C702 ZH703P14P75R4
1
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0
MAKE_BASE=TRUE
0.01UF 0.01UF NET_SPACING_TYPE=POWER
20% 20%
16V 16V
2 CERM NOSTUFF 2 CERM NOSTUFF
PP3V3_RUN 402 1 C707 402 1 C703
0.01UF 0.01UF
20% 20%
16V 16V
2 CERM 2 CERM
1 402 402
R790
33
5%
1/4W
MF-LF
2 1206
LEAKAGE HACK Q790_D
3 POWER CONN / ALIAS
A D
Q790 SYNC_MASTER=M33-PC SYNC_DATE=06/20/2005
1
2N7002
SOT23-LF NOTICE OF PROPRIETARY PROPERTY
A
96 16 7 SYS_POWERUP_L_BUF G S
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 7 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CHKSTOP LED
DIAG LED PLL LOCK LED
(OVERTEMP LED) 8 7 6 =PP5V_RUN_CPU
8 7 6 =PP5V_RUN_CPU
PP5V_ALL
D 1 DEVELOPMENT
DEVELOPMENT
1
R833 D
R850 1 180
R837DEVELOPMENT 5%
y
2.0K 1/16W
5% 180 MF-LF
1/16W
MF-LF
5%
1/16W Q802 2
2 402
2 402 MF-LF 2N3906
2 402
SOT23-LF 6 LED801_1
LED850P1
6 Q802_B 1 DEVELOPMENT
1
1 LED801
r
LED850 DEVELOPMENT RED-4.0MCD
RED-4.0MCD 3 1 2X1.25MM-SM
2X1.25MM-SM 6 Q802_E R834 2
2 DEVELOPMENT 4.7K Q800_D
1 DEVELOPMENT 5% 6
LED850P2 R838 1
R835
1/16W
MF-LF
3
1K 2 402
3
DEVELOPMENT
R851 5% 1K
1K
1/16W
MF-LF
5%
1/16W
D
Q800
DIAG_LED 1 2 DIAG_LED_R 1 Q850 2N7002
a
28
MAKE_BASE=TRUE 2 402 MF-LF
SOT23-LF
5% 2N3904LF 2 402 6 Q800_G 1 G S
1/16W SOT23 9 Q803_C
MF-LF 2 DEVELOPMENT 6 LED802_1
402 2
3 DEVELOPMENT
R839 DEVELOPMENT 1
DEVELOPMENT
R836 3
180 LED802
43 9 PLLLOCK 1 6 2 Q803_B 1 Q803 GREEN-3.6MCD
56 43 CPU_CHKSTOP_L 1
10K 2 6 Q801_B 1
DEVELOPMENT
Q801
5% 2N3904LF 2.0X1.25MM-SM
1/16W SOT23 2 5% 2N3904LF
MF-LF 2 1/16W SOT23
402 MF-LF 2
n
402
i
C C
il m
CPU HEATSINK MOUNTING HOLES
OMIT OMIT OMIT OMIT
ZH800 ZH801 ZH802 ZH803
SERIAL DEBUG 4P75R4 4P75R4 4P75R4 4P75R4
HS_SDF800 1 7 HS_SDF801 1 HS_SDF802 1 HS_SDF803 1
PP5V_PWRON
1 C880 1 C881 1 C882
1 C883
0.01UF
DEVELOPMENT 0.01UF 0.01UF 0.01UF 20%
e
20% 20% 20% 16V
J800 16V
2 CERM
16V
2 CERM
16V
2 CERM
2 CERM
M-ST-5087 402
SM-LF 402 402 402
SCC_TXD_L 24 I2S1_SB_TO_DEV_DTO 1 10 I2S1_RESET_L 24 SCC_DTR_L
SCC_TRXC 24 I2S1_BITCLK 2 9 I2S1_MCLK 24 SCC_RTS_L
B B
r
3 8
SCC_GPIO_L 24 I2S1_SYNC 4 7 I2S1_DEV_TO_SB_DTI 24 SCC_RXD
5 6
A
P SYNC_MASTER=FINO-M23
Signal Alias
NOTICE OF PROPRIETARY PROPERTY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER
SYNC_DATE=08/29/2005
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
REV.
A
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 8 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE FOLLOWING NETS DO NOT HAVE
THE FOLLOWING NETS ARE USED ONLY TEST POINT BECAUSE OF ROUTING DENSITY
WHEN THE DEVELOPMENT BOM OPTION IS ENABLED AND SIGNAL INTEGRITY.
TEST COVERAGE WILL BE BY FCT
NOTE FOR SHARING: DO NOT INCLUDE THIS LIST UNTIL
ENET_TXD_R<7> TP_VESTA_TVCO_24
PCB LAYOUT ADDS TEST POINTS. THIS LIST IS A RESULT OF PCB
I1 NO_TEST=YES 130 131 I91 NO_TEST=YES 139
ENET_TXD_R<6> TP_VESTA_TXC_RXC_DELAY
LAYOUT HAVING DIFFICULTY PLACING TEST POINTS ON THESE NETS
I2 NO_TEST=YES 130 131 I92 NO_TEST=YES 132
I3 NO_TEST=YES ENET_TXD_R<5> 130 131 I93 NO_TEST=YES TP_I2S2_SB_TO_DEV_DTO 154 I106 NO_TEST=YES Q803_C 8 I173 NO_TEST=YES 100M_N<0> 82 97
I4 NO_TEST=YES ENET_TXD_R<4> 130 131 I94 NO_TEST=YES TP_NB_APSYNC 44 I174 NO_TEST=YES 100M_P<0> 82 97
ENET_TXD_R<3> TP_SB_WATCHDOG CKA_N<0>
JTAG TEST POINTS NEED TO BE ON THE BOTTOM
I5 NO_TEST=YES 130 131 I95 NO_TEST=YES 24 I175 NO_TEST=YES 84 97
ENET_TXD_R<2> NC_CPU_TBEN_CLK PLLLOCK CKA_P<0>
OF THE BOARD
I6 NO_TEST=YES 130 131 I96 NO_TEST=YES I109 NO_TEST=YES 8 43 I176 NO_TEST=YES 84 97
ENET_TXD_R<1> NC_J3108_10 HT_NB_N<0>
ADDING FUNC_TEST=TRUE TO THESE NETS
NO_TEST=YES 130 131 NO_TEST=YES 31 NO_TEST=YES 98 101
D
I7
I8 NO_TEST=YES ENET_TXD_R<0> 130 131
I97
I98 NO_TEST=YES NC_J3108_11 31
I177
I178 NO_TEST=YES HT_NB_P<0> 98 101 D
I9 NO_TEST=YES ENET_TXD<7> 130 131 132 I99 NO_TEST=YES NC_J3108_12 31 I179 NO_TEST=YES HT_NB_REFCLK_NF<0> 98 101
y
I10 NO_TEST=YES ENET_TXD<6> 130 131 132 I100 NO_TEST=YES NC_J3108_8 31 I180 NO_TEST=YES HT_NB_REFCLK_PF<0> 98 101 I226 FUNC_TEST=TRUE TP_JTAG_SB_TCK 20
I12 NO_TEST=YES ENET_TXD<5> 130 131 132 I101 NO_TEST=YES NC_J3108_9 31 I114 NO_TEST=YES LED_PP1V8_RUN_P 11 I181 NO_TEST=YES HT_NB_TO_SB_CAD_N<0..7> 101 I227 FUNC_TEST=TRUE TP_JTAG_SB_TDI 20
I11 NO_TEST=YES ENET_TXD<4> 130 131 132 I102 NO_TEST=YES NC_JTAGMUX_3 30 I117 NO_TEST=YES LED_PP1V8_RUN_N 11 I182 NO_TEST=YES HT_NB_TO_SB_CAD_P<0..7> 101 I228 FUNC_TEST=TRUE TP_JTAG_SB_TDO 20
I13 NO_TEST=YES ENET_TXD<3> 130 131 132 I103 NO_TEST=YES NC_PP1V5_PULSAR 12 I116 NO_TEST=YES PP1V5_RUN_FOR_LED 12 I183 NO_TEST=YES HT_NB_TO_SB_CLK_P<0> 101 I229 FUNC_TEST=TRUE TP_JTAG_SB_TMS 20
I14 NO_TEST=YES ENET_TXD<2> 130 131 132 I115 NO_TEST=YES LED_PP1V5_RUN_N 12 I184 NO_TEST=YES HT_NB_TO_SB_CLK_N<0> 101 I230 FUNC_TEST=TRUE JTAG_SB_TRST_L 20 24
r
I15 NO_TEST=YES ENET_TXD<1> 130 131 132 I118 NO_TEST=YES LED_PP1V5_RUN_P 12 I185 NO_TEST=YES HT_SB_TO_NB_CAD_N<0..7> 101
I16 NO_TEST=YES ENET_TXD<0> 130 131 132 I119 NO_TEST=YES PULSAR_1V5_RUN_SWITCH 12 I186 NO_TEST=YES HT_SB_TO_NB_CAD_P<0..7> 101
I18 NO_TEST=YES ENET_RXD_R<7> 130 131 132 I120 NO_TEST=YES PP1V2_RUN_FOR_LED 13 I187 NO_TEST=YES HT_SB_TO_NB_CLK_P<0> 101
I17 NO_TEST=YES ENET_RXD_R<6> 130 131 132 I121 NO_TEST=YES LED_PP1V2_RUN_N 13 I189 NO_TEST=YES HT_SB_TO_NB_CLK_N<0> 101
I19 NO_TEST=YES ENET_RXD_R<5> 130 131 132 I124 NO_TEST=YES LED_PP1V2_RUN_P 13 I188 NO_TEST=YES PCIE_SLOTA_TO_NB_N<0..15> 9 82 84 97
I20 NO_TEST=YES ENET_RXD_R<4> 130 131 132 I123 NO_TEST=YES KP_V<1> 55 I191 NO_TEST=YES PCIE_SLOTA_TO_NB_P<0..15> 9 82 84 97
NO_TEST=YES ENET_RXD_R<3> NO_TEST=YES KP_V<2> NO_TEST=YES UATA_DA<0>
a
I21 130 131 132 I122 55 I192 127 129
I232 FUNC_TEST=TRUE JTAG_NB_TCK 20 30
I22 NO_TEST=YES ENET_RXD_R<2> 130 131 132 I125 NO_TEST=YES CPU_SENSE_KP_V 55 I193 NO_TEST=YES UATA_DD<1> 127 129
I234 FUNC_TEST=TRUE JTAG_NB_TDI 20 30
I24 NO_TEST=YES ENET_RXD_R<1> 130 131 132 I126 NO_TEST=YES NB_PLL_OUT_TRG_R I194 NO_TEST=YES UATA_DD<14> 127 129
I233 FUNC_TEST=TRUE JTAG_NB_TDO 20 30
I23 NO_TEST=YES ENET_RXD_R<0> 130 131 132 I127 NO_TEST=YES NB_PLL_OUT_TRG 59 I195 NO_TEST=YES PCIE_NB_TO_SLOTA_N<0> 9 82 84 97
I236 FUNC_TEST=TRUE JTAG_NB_TMS 20 30
I25 NO_TEST=YES ENET_RXD<7> 130 131 I128 NO_TEST=YES PP5V_T555 I196 NO_TEST=YES PCIE_NB_TO_SLOTA_N<3> 9 82 84 97
I235 FUNC_TEST=TRUE JTAG_NB_TRST_L 20
I26 NO_TEST=YES ENET_RXD<6> 130 131 I131 NO_TEST=YES T555_DISC I197 NO_TEST=YES PCIE_NB_TO_SLOTA_NF<13> 9 82 97
I27 NO_TEST=YES ENET_RXD<5> 130 131 I130 NO_TEST=YES T555_THRES I198 NO_TEST=YES PCIE_NB_TO_SLOTA_NF<7> 9 82 97
I28 NO_TEST=YES ENET_RXD<4> 130 131 I129 NO_TEST=YES T555_OUT I199 NO_TEST=YES PCIE_NB_TO_SLOTA_P<1> 9 82 84 97
n
I30 NO_TEST=YES ENET_RXD<3> 130 131 I132 NO_TEST=YES T555_PWM I200 NO_TEST=YES PCIE_NB_TO_SLOTA_P<10> 9 82 84 97
I29 NO_TEST=YES ENET_RXD<2> 130 131 I133 NO_TEST=YES PP3V3_GPU_TSENSE 93 I201 NO_TEST=YES PCIE_NB_TO_SLOTA_PF<13> 9 82 97
I238 FUNC_TEST=TRUE TP_JTAG_VESTA_TDI 17
I31 NO_TEST=YES ENET_RXD<1> 130 131 I134 NO_TEST=YES TSENSE_GPU_OVERTEMP_L 93 I202 NO_TEST=YES PCIE_NB_TO_SLOTA_PF<14> 9 82 97
FUNC_TEST=TRUE TP_JTAG_VESTA_TDO 17
i
I240
I32 NO_TEST=YES ENET_RXD<0> 130 131 I135 NO_TEST=YES TSENSE_GPU_ADD0 93 I203 NO_TEST=YES PCIE_NB_TO_SLOTA_NF<12> 9 82 97
I239 FUNC_TEST=TRUE TP_JTAG_VESTA_TCK 17
I33 NO_TEST=YES ENET_TX_EN_R 130 131 I138 NO_TEST=YES TSENSE_GPU_ADD1 93 I204 NO_TEST=YES PCIE_NB_TO_SLOTA_PF<10> 9 82 97
I242 FUNC_TEST=TRUE TP_JTAG_VESTA_TMS 17
C I34
I36
NO_TEST=YES
NO_TEST=YES
ENET_TX_ER_R
ENET_TX_EN
130 131
130 131 132
I137
I136
NO_TEST=YES
NO_TEST=YES
GPU_DIODE_PLUS
GPU_DIODE_MINUS
93
93
I205
I206
NO_TEST=YES
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<4> 9 82 97
HT_MB_TO_NB_CTL_N<1> 98 I241 FUNC_TEST=TRUE TP_JTAG_VESTA_TRST_L 17 C
I35 NO_TEST=YES ENET_TX_ER 130 131 132 I139 NO_TEST=YES LED8700_P 136 I208 NO_TEST=YES HT_MB_TO_NB_CTL_P<1> 98
I37 NO_TEST=YES TP_HT_MB_TO_NB_CLK_N<1> 101 I140 NO_TEST=YES LED8701_P 136 I207 NO_TEST=YES HT_NB_TO_MB_CTL_N<1> 98
I38 NO_TEST=YES TP_HT_MB_TO_NB_CLK_P<1> 101 I210 NO_TEST=YES HT_NB_TO_MB_CTL_P<1> 98
THE FOLLOWING PULSAR NETS WILL BE
I39 NO_TEST=YES NC_CPU_AFN 56 TESTED VIA TEST JET I209 NO_TEST=YES HT_NB_TO_SB_CTL_N<0> 101 I244 FUNC_TEST=TRUE JTAG_CPU_TCK 30 43
I40 NO_TEST=YES NC_I2C_SMU_CPU_SCL_IN 31 I211 NO_TEST=YES HT_SB_TO_NB_CTL_P<0> 101 I246 FUNC_TEST=TRUE JTAG_CPU_TDI 30 43
I141 NO_TEST=YES CPU_A_TBEN_CLK_R 26
I42 NO_TEST=YES NC_PSRO 56 I213 NO_TEST=YES CLK_KOD_100M_NF<0> 82 97 I245 FUNC_TEST=TRUE JTAG_CPU_TDO 30 43 47
I142 NO_TEST=YES CPU_B_TBEN_CLK_R 26
I41 NO_TEST=YES NC_PSRO_ENABLE 56 I212 NO_TEST=YES CLK_KOD_100M_PF<0> 82 97 I248 FUNC_TEST=TRUE JTAG_CPU_TMS 30 43
NO_TEST=YES CPU_A_APSYNC_R
m
I143 26
I43 NO_TEST=YES NC_SLOT_TOTAL_PWR 31 I214 NO_TEST=YES EI_CPU_TO_NB_CLK_N 43 56 I247 FUNC_TEST=TRUE JTAG_CPU_TRST_L 43 47
I144 NO_TEST=YES CPU_B_APSYNC_R 26
I44 NO_TEST=YES NC_SMU_CPU_VID_LE0 31 I216 NO_TEST=YES EI_CPU_TO_NB_CLK_P 43 56
I145 NO_TEST=YES NB_APSYNC_R 26
I45 NO_TEST=YES NC_SMU_CPU_VID_LE1 31 I215 NO_TEST=YES EI_CPU_TO_NB_SR_N<1> 9 43 56
I146 NO_TEST=YES HT_SB_REFCLK_R 26
il
I46 NO_TEST=YES NC_SMU_FAN_RPM3 31 I218 NO_TEST=YES EI_CPU_TO_NB_SR_P<1> 9 43 56
I147 NO_TEST=YES HT_NB_REFCLK_H0_R 26
I48 NO_TEST=YES NC_SMU_FAN_RPM4 31 I217 NO_TEST=YES EI_NB_TO_CPU_CLK_N 43 56
I148 NO_TEST=YES HT_NB_REFCLK_L0_R 26
I47 NO_TEST=YES NC_SMU_FAN_RPM5 31 I219 NO_TEST=YES EI_NB_TO_CPU_CLK_P 43 56
I149 NO_TEST=YES CLK_RAIREF_200M_P_R 26
I49 NO_TEST=YES NC_SMU_FAN_TACH3 31 I221 NO_TEST=YES EI_NB_TO_CPU_SR_N<0> 9 43 56
I150 NO_TEST=YES CLK_RAIREF_200M_N_R 26
I50 NO_TEST=YES NC_SMU_FAN_TACH4 31 I220 NO_TEST=YES EI_NB_TO_CPU_SR_P<0> 9 43 56
I151 NO_TEST=YES NB_PMR_CLK_P_R 26
I51 NO_TEST=YES NC_SMU_FAN_TACH5 31
I152 NO_TEST=YES NB_PMR_CLK_N_R 26 I257 NO_TEST=YES PLLTESTOUT 43 47
I52 NO_TEST=YES NC_SMU_FAN_TACH7 31
I153 NO_TEST=YES NB_PCIE_REFCLK_P_C 26 I258 NO_TEST=YES UATA_DD<13> 127 129
I54 NO_TEST=YES NC_SMU_SER_SEL 31
I154 NO_TEST=YES NB_PCIE_REFCLK_N_C 26 I259 NO_TEST=YES CPU_SPARE2 43 47
I53 NO_TEST=YES NC_SYS_DOOR_AJAR_L 31
I155 NO_TEST=YES GFX_SLOT_PCIE_REFCLK_P_C 26
I260 NO_TEST=YES RFBD<51> 88 89
I55 NO_TEST=YES TP_VESTA_2_5V_EN 17
I156 NO_TEST=YES GFX_SLOT_PCIE_REFCLK_N_C 26
I261 NO_TEST=YES TP_CPU_TRIGGER_OUT 56
e
I56 NO_TEST=YES TP_VESTA_AN_EN 132
I157 NO_TEST=YES PCIE_A_REFCLKIN_P_C 26 I262 NO_TEST=YES UATA_DD<12> 127 129
I57 NO_TEST=YES TP_VESTA_DNC_C9 17
I158 NO_TEST=YES PCIE_A_REFCLKIN_N_C 26
I58 NO_TEST=YES TP_VESTA_DNC_E9 17 I263 NO_TEST=YES EI_CPU_SYSCLK_P 43 56
I159 NO_TEST=YES PCIE_B_REFCLKIN_P_C 26
I60 NO_TEST=YES TP_VESTA_EN_10B 132 I264 NO_TEST=YES EI_CPU_TO_NB_SR_N<1> 9 43 56
I160 NO_TEST=YES PCIE_B_REFCLKIN_N_C 26
NO_TEST=YES TP_VESTA_ER 132 NO_TEST=YES EI_CPU_TO_NB_SR_P<1> 9 43 56
B I59
NO_TEST=YES PCIE_C_REFCLKIN_P_C 26 I265
B
r
I162
I61 NO_TEST=YES TP_VESTA_F1000 132 I266 NO_TEST=YES EI_NB_TO_CPU_SR_N<0> 9 43 56
I161 NO_TEST=YES PCIE_C_REFCLKIN_N_C 26
I62 NO_TEST=YES TP_VESTA_FDX 132 I267 NO_TEST=YES EI_NB_TO_CPU_SR_P<0> 9 43 56
I164 NO_TEST=YES NB_DDR_REFCLK_P_R 26
I63 NO_TEST=YES TP_VESTA_FDXLED_L 132
I163 NO_TEST=YES NB_DDR_REFCLK_N_R 26
I64 NO_TEST=YES TP_VESTA_HUB 132
I165 NO_TEST=YES CLK_RAI_GIGE_25MHZ_R 26
I66 NO_TEST=YES TP_VESTA_LINK1_L 132
I168 NO_TEST=YES QUA0_REF_25MHZ_R 26
I65 NO_TEST=YES TP_VESTA_LINK2_L 132
I167 NO_TEST=YES SB_CLK25M_SATA_R 26
I67 NO_TEST=YES TP_VESTA_MANMS 132
I166 NO_TEST=YES QUA1_REF_25MHZ_R 26
I68 NO_TEST=YES TP_VESTA_PHYA<0> 132
NO_TEST=YES PCI_CLK33M_SB_EXT_R 26
P
I169
I69 NO_TEST=YES TP_VESTA_PHYA<1> 132
I170 NO_TEST=YES SB_AIRPRT_CLK_33MHZ_R 26
I70 NO_TEST=YES TP_VESTA_PHYA<2> 132
I171 NO_TEST=YES CLK_RAI_REFCLK_66M_R 26
I72 NO_TEST=YES TP_VESTA_PHYA<3> 132
I172 NO_TEST=YES SB_USB2_CLK_33MHZ_R 26
I71 NO_TEST=YES TP_VESTA_PHYA<4> 132
I73 NO_TEST=YES TP_VESTA_RBC0 132
I74 NO_TEST=YES TP_VESTA_RBC1 132
I75 NO_TEST=YES TP_VESTA_REGCTL1 17
I76 NO_TEST=YES TP_VESTA_REGCTL2 17
I78 NO_TEST=YES TP_VESTA_REGSEN1 17
I77 NO_TEST=YES TP_VESTA_REGSEN2 17
ADDING NO_TEST TO ALL PCIE NETS
I79 NO_TEST=YES TP_VESTA_REGSUP1 17
TO AVOID STUBS
I80 NO_TEST=YES TP_VESTA_REGSUP2 17
WILL GET COVERAGE IN FCT WITH A DIAG
I81 NO_TEST=YES TP_VESTA_RGMIIEN 132
THAT CHECKS THAT THE BUS IS 16 LANES WIDE
I82 NO_TEST=YES TP_VESTA_SPD0 132
I249 NO_TEST=YES PCIE_NB_TO_SLOTA_NF<0..15> 9 82 97
I84 NO_TEST=YES TP_VESTA_TDBL<0> 139
I250 NO_TEST=YES PCIE_NB_TO_SLOTA_PF<0..15> 9 82 97
I83
I85
NO_TEST=YES
NO_TEST=YES
TP_VESTA_TDBL<1>
TP_VESTA_TDBL<2>
139
139
I251 NO_TEST=YES PCIE_NB_TO_SLOTA_N<0..15> 9 82 84 97 FUNC TEST 2 OF 2
I252 NO_TEST=YES PCIE_NB_TO_SLOTA_P<0..15> 9 82 84 97
NO_TEST=YES TP_VESTA_TEST<0>
A I86
I87 NO_TEST=YES TP_VESTA_TEST<1>
132
132
I253 NO_TEST=YES
NO_TEST=YES
PCIE_SLOTA_TO_NB_NF<0..15> 84 97
PCIE_SLOTA_TO_NB_PF<0..15> 84 97
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
I254
I88 NO_TEST=YES TP_VESTA_TEST_1394<0> 139
I255 NO_TEST=YES PCIE_SLOTA_TO_NB_N<0..15> 9 82 84 97
I90 NO_TEST=YES TP_VESTA_TEST_1394<1> 139 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
I256 NO_TEST=YES PCIE_SLOTA_TO_NB_P<0..15> 9 82 84 97 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
I89 NO_TEST=YES TP_VESTA_TVCO 132 AGREES TO THE FOLLOWING
I222 NO_TEST=YES CARD_READER_ACTIVITY_R 144 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
I223 NO_TEST=YES TP_VESTA_FAVDDL 139 II NOT TO REPRODUCE OR COPY IT
I224 NO_TEST=YES TP_NB_A_TRIGGER_OUT 56 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I225 NO_TEST=YES TP_NB_B_TRIGGER_OUT 56
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 9 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
1.8V VOLTAGE REGULATOR
PP5V_ALL
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
1
R1100
D1100
2
MBR0520LXXG
SOD-123
1
PP12V_ALL
1
D1102
MBR0520LXXG
1 C1111 C1102
10UF
10%
1
680UF
20%
1
C1103
680UF
20%
r y NOTE:
SET OUTPUT=1.85V FOR FRAMEBUFFER.
IRU3037ACS VREF=0.8VDC
VOUT=VREF*(R903+R905)/R905=1.85VDC
a
4.7 SOD-123 2 16V
CERM 2 16V 2 16V
5% 2 ELEC ELEC
1/8W
MF-LF
D1101 1210 TH-MCZ TH-MCZ POWER BUDGET CURRENT OF TOTAL RAILS
2 805
U1100_VC_R 2 1 MIN_LINE_WIDTH=0.45MM U1100_VC_D
MIN_NECK_WIDTH=0.25MM
10.9A PEAK
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM MBR0520LXXG
7.2A CONTINUOUS
U1100_VC SOD-123
1 C1104 1 C1116
1UF D 4
10% 1UF
2 6.3V
CERM
2 6 20%
25V
R1102 Q1101 1 C1117
0 PP1V8_PWRON
n
2 CERM NTD60N02R 1UF
402 VCC VC 805
1 2 Q1101_GATE 1
CASE369-LF 20%
11 6 GND_U1100 U1100 5% MIN_LINE_WIDTH=0.45MM
G
S3
25V
2 CERM
IRU3037ACS 1/8W MIN_NECK_WIDTH=0.25MM
MF-LF 805 CRITICAL
SOI-LF 805 L1101
i
HD 5 U1100_GATE_H 1.5UH
8
MIN_NECK_WIDTH=0.25MM
U1100_SS SS MIN_LINE_WIDTH=0.45MM
Q1102_DRAIN 1 2
C U1100_COMP 7 COMP
LD 3 U1100_GATE_L
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
1
IHLP C
R1104 NOSTUFF
1
C1107 R1103
FB 1 U1100_FEEDBACK
1
5.11 1 PP12V_RUN
3 R1101 1% 3300PF 12.4K
1/4W 1%
9.31K GND D 4 MF-LF 10% 1/16W
D
Q1100 1% 2 1206 2 50V MF-LF NOSTUFF
2N7002 1/16W
4
Q1102 CERM
603 2 402 C1110
1 C1140
SOT23-LF
MF-LF
2 402
1 NTD60N02R MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
1
C1109 10UF
1
C1119 1
R1140 0.001UF
16 15 13 12 PWRON_L 1 G S 1 C1115 1 C1113 1 C1106 G
CASE369-LF R904_P2 1500UF
20% 20%
330UF
20%
470K
5%
20%
50V
2 CERM
0.1UF R1101_P2 100PF 220PF S3 2 6.3V
6.3V
2 2.5V-ESR9V 1/16W 5 6 7 8
2 20%
25V
5%
50V
5%
25V
1 C1105 1 C1112 ELEC
TH-MCZ
CERM
1206
POLY
CASE-D2E-LF
MF-LF 402
m
2 CERM 2 CERM 2 CERM 0.0018UF 1000PF 2 402
603
1 C1114 805 402 10% 5%
1
R1105 Q1103 POWER BUDGET CURRENT OF FET
6800PF 50V
2 CERM
50V
2 CERM 9.31K HIGH TO ENABLE IRF7413PBF 2.7A PEAK
10% 1%
2 50V
CERM XW1100
SM
402 1206 1/16W
MF-LF Q903_GATE 4
SO-8
2.3A CONTINUOUS
603
il
11 6 GND_U1100 1 2 2 402
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=0 V 1 2 3
PP1V8_RUN
U1100_FEEDBACK
11 6 GND_U1100
TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
e
TABLE_ALT_ITEM
376S0340 376S0388 Q1101,Q1102 3
D
Q1140
2N7002
1 SOT23-LF
54 30 26 16 15 13 12 SYS_SLEEP G S
B B
r
2
P
PP3V3_RUN
DEVELOPMENT
1
R1160
330
5%
1/16W
MF-LF
2 402
9 LED_PP1V8_RUN_P
PP1V8_RUN DEVELOPMENT
1
LED1100
DEVELOPMENT GREEN-3.6MCD
3 2.0X1.25MM-SM
8 LM339A 2
U1201
V+ SOI-LF
14 9 LED_PP1V8_RUN_N 1.8V VREG
A 85 13 12 1V1_REF 9 GND
12
PLACE LED NEAR VREG
SYNC_MASTER=M33-PC
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=06/20/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 11 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE:
D D
KODIAK CORE VOLTAGE REGULATOR IRU3037ACS VREF=0.8VDC
y
VOUT=VREF*(R1203+R1205)/R1205=1.25VDC
1.35V R1205=2.87K
LOAD FROM POWER BUDGET 1.30V R1205=3.24K
8.5A PEAK CURRENT DRAW 1.25V R1205=3.65K
7.2A CONTINUOUS CURRENT DRAW
r
PP5V_ALL PP12V_ALL
TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
D1200
TABLE_ALT_ITEM
2 1
376S0340 376S0388 Q1201,Q1202
1
MBR0520LXXG 1
R1200 SOD-123
a
10
D1202
5% MBR0520LXXG
1/8W SOD-123
MF-LF
D1201 2 1 C1201 1 C1210 1
C1202
2 805 10UF 10UF 680UF
U1200_VC_R 2 1 U1200_VC_D 10% 10% 20%
U1200_VC 16V 16V
MIN_LINE_WIDTH=0.45MM 2 CERM 2 CERM 2 16V
MIN_LINE_WIDTH=0.45MM MIN_NECK_WIDTH=0.25MM ELEC
MIN_NECK_WIDTH=0.25MM MBR0520LXXG 1210 1210 TH-MCZ
SOD-123
1 C1204 1 C1216 PP1V5_PWRON
1UF 1UF
n
10% 2 6 20% D 4 CRITICAL
2 6.3V
CERM VCC VC 2 10V
CERM
R1202 Q1201 1 C1217
402 603 0 NTD60N02R 1UF
U1200 1 2 Q1201_GATE 1
CASE369-LF 20%
G 25V
12 6 GND_U1200 IRU3037ACS 5% 2 CERM CRITICAL
i
1/8W S3
SOI-LF
5
MF-LF MIN_LINE_WIDTH=0.45MM 805
3 L1201
CRITICAL HD U1200_GATE_H 805 MIN_NECK_WIDTH=0.25MM 1.53UH
MIN_LINE_WIDTH=0.45MM
C U1200_SS 8 SS
LD 3
MIN_NECK_WIDTH=0.25MM
U1200_GATE_L
MIN_LINE_WIDTH=0.45MM
Q1202_DRAIN
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
SM
2
C
U1200_COMP 7 COMP MIN_NECK_WIDTH=0.25MM
1 1 NOSTUFF 1
FB 1 U1200_FEEDBACK R1204 R1203
1 5.11
1 C1207 2.05K
R1201 D 4 CRITICAL
1% 1UF 1%
3 1%
15.8K GND Q1202 1/4W
MF-LF
20%
10V
2 CERM
1/16W
MF-LF CRITICAL CRITICAL
NOSTUFF 1/16W
4 1 NTD60N02R
1 C1214 CASE369-LF 2 1206 603 2 402 1 1 1 C1218
R1206
D Q1200 0.1UF
MF-LF
2 402
G
MIN_LINE_WIDTH=0.45MM C1208 C1209 10UF
0
2N7002
SOT23-LF 20%
1 C1213 1 C1206 S3 R2204_P2 MIN_NECK_WIDTH=0.25MM 1500UF
20%
1500UF
20% 20%
PWRON_L 1 2 TURN_ON_PP1V5_L 1 G 16V 56PF 220PF 6.3V
m
S 2 CERM R1201_P2 2 6.3V 2 6.3V 2 CERM
16 15 13 11
5% 603
5%
2 50V
5%
25V
1 C1205 1 C1212
ELEC
TH-MCZ
ELEC
TH-MCZ 805-1
1 C1215 CERM 2 CERM
0.0018UF 1
1/16W
MF-LF
2
6800PF
402 402 10% 1000PF R1205
402
10% 2 50V
CERM
5%
50V 2.87K
R1207 50V 402 2 CERM 1%
il
2 CERM 1/16W
TURN_ON_PP1V2_L 1
0 2 603 XW1200
SM
1206 MF-LF
13 4
2 402
5% 12 6 GND_U1200 1 2
1/16W MIN_LINE_WIDTH=0.45MM
MF-LF MIN_NECK_WIDTH=0.25MM
402 VOLTAGE=0 V
TURNING ON PP2V5_PWRON WITH 1V2_PWRON
SO THAT 1.5V IS THE FIRST RAIL UP ON KODIAK U1200_FEEDBACK
12 6 GND_U1200
e
PP3V3_RUN PP1V5_PWRON_PULSAR CRITICAL
B B
r
PP3V3_PWRON U1270
DEVELOPMENT MM1571FN
1
PP1V5_PWRON_PULSAR 7
R1260 SOT-25A
330
LOAD FROM POWER BUDGET 5% VIN VOUT
1/16W
1.3A PEAK CURRENT DRAW PP1V5_RUN MF-LF
U1270_NOISE
1.0A CONTINUOUS CURRENT DRAW 2 402 1 C1270 R1270 1 CONT NOISE
9 LED_PP1V5_RUN_P 1UF 10K GND C1271 1 1 C1272
20% 5%
PP1V5_PWRON 10V
2 CERM 1/16W 0.01UF 10UF
20% 10%
P
805 MF-LF 16V 6.3V
1
DEVELOPMENT 2 402 CERM 2 2 X5R
DEVELOPMENT 402 805
CRITICAL LED1200
R1261 3
DEVELOPMENT GREEN-3.6MCD U1270_CONT PP12V_RUN DEVELOPMENT
Q1250 1
0 2 9 PP1V5_RUN_FOR_LED 6 LM339A 2
2.0X1.25MM-SM
C1275
SI3446DV V+ SOI-LF 0.01UF
TSOP-LF 5% DEVELOPMENT 3
1 1 9 LED_PP1V5_RUN_N 2 1
2
1/16W
MF-LF
402
U1201 1
R1273
7 GND 20% D DEVELOPMENT
5 85 13 11 1V1_REF 10K 16V
PLACE LED NEAR VREG
6 3 12
5%
1/16W CERM
402
Q1271
PP5V_PWRON C1250 1 RDSON=0.012 OHM
MF-LF 1 G IRLM2402PBF
@ VGS=3.5 V 2 402 SOT23
0.1UF 4 S
20% 9 PULSAR_1V5_RUN_SWITCH
10V
CERM 2
402 2
DEVELOPMENT PP1V5_RUN_PULSAR NC_PP1V5_PULSAR 9
R1250 VOLTAGE=1.5V MAKE_BASE=TRUE
1
2
100K
1 Q1250G 3
DEVELOPMENT R1274 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
5%
10K
5%
1/16W
MF-LF
402
3
D
Q1270
2N7002
1/16W
MF-LF
2 402
1.5V Vreg
D SOT23-LF
Q1251 SYS_POWERUP_L 1 G S
A 2N7002
SOT23-LF
S G 1 SYS_SLEEP 11 13 15 16 26 30 54
85 50 28 7 6
2
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 12 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP1V2_ALL VOLTAGE REGULATOR
PP12V_ALL
PP5V_ALL
D1300 NOTE:
MIN_LINE_WIDTH=0.45MM SET OUTPUT=1.22-1.23V
D MIN_NECK_WIDTH=0.25MM 2 1
1 IRU3037ACS VREF=0.8VDC D
MBR0520LXXG D1302 VOUT=VREF*(R1003+R1005)/R1005=1.22-1.23VDC
MBR0520LXXG C1301 C1302 C1303
1 1 1 1
R1302 SOD-123
y
4.7 SOD-123 10UF 10UF 10UF
5%
1/8W D1301 2 10%
16V
2 CERM
10%
16V
2 CERM
10%
16V
2 CERM
POWER BUDGET CURRENT OF TOTAL RAILS
MF-LF
U1300_VC_R 2 1
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MMU1300_VC_D 1210 1210 1210 3.2A PEAK
2 805 2.6A CONTINUOUS
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM MBR0520LXXG 5 6 7 8
r
U1300_VC SOD-123
1 C1304 1 C1300
1UF CRITICAL
10% 1UF
2 6.3V
CERM
2 6 20%
25V
R1300 Q1301 1 C1317
2 CERM 0 PP1V2_ALL
402 VCC VC 805
1 2 Q1301_GATE 4
IRF7807ZPBF 1UF
20%
U1300 5% SO-8 25V
2 CERM
13 6 GND_U1300 IRU3037ACS 1/8W
MIN_NECK_WIDTH=0.25MM
MF-LF
MIN_LINE_WIDTH=0.45MM 805
SOI-LF
CRITICAL HD 5 U1300_GATE_H
805 L1301
3.8UH
a
MIN_NECK_WIDTH=0.25MM 1 2 3
U1300_SS 8 SS MIN_LINE_WIDTH=0.45MM
Q1302_DRAIN 1 2
LD 3 U1300_GATE_L MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.6MM SM2 CRITICAL
U1300_COMP 7 COMP MIN_LINE_WIDTH=0.45MM 1
R1304 NOSTUFF
1
1
C1309
C1307 R1303
FB 1 U1300_FEEDBACK 5 6 7 8
1
5.11 1 1800UF
R1301 1% 5.36K
3300PF 20%
1/4W 1% 2 6.3V
18K GND CRITICAL MF-LF 10% 1/16W ELEC
5% 4 2 1206 2 50V MF-LF TH-KZJ-LF
1/16W Q1302 CERM
603 2 402
n
MF-LF
2 402
IRF7807ZPBF MIN_NECK_WIDTH=0.25MM
1 C1315 1 C1313 1 C1306 4
SO-8 R1304_P2 MIN_LINE_WIDTH=0.45MM
0.1UF R1301_P2 56PF 220PF
20%
16V
2 CERM
5%
50V
2 CERM
5%
25V
2 CERM
1 C1305 1 C1312 NOSTUFF
C1314 0.0018UF 1000PF
i
1 1
603
0.0068UF
402 402 10%
50V
1 2 3 5%
50V
R1305 1R1306
10% 2 CERM 2 CERM 10K 10K
1% 1%
2 25V XW1300 402 1206
C 13 6 GND_U1300
CERM
402 SM
1 2
1/16W
MF-LF
2 402
1/16W
MF-LF
2 402
C
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
VOLTAGE=0 V
U1300_FEEDBACK
13 6 GND_U1300
PP1V2_PWRON FET SWITCH
PEAK CURRENT 1.3A
1.0A CONTINUOUS
PP1V2_ALL
PP1V2_PWRON
il m PP1V2_RUN FET SWITCH
PEAK CURRENT 1.3A IF KODIAK 1.2V CAN BE TURNED OFF IN SLEEP.
CRITICAL
DEVELOPMENT
Q1303
SI3446DV
PP1V2_ALL
PP1V2_RUN
PP3V3_RUN
0.6A/M33 0.0A/M23 IF NOT
PP5V_RUN
1
DEVELOPMENT
C1350
PP3V3_RUN
DEVELOPMENT
1
R1350
330
e
5%
PP5V_ALL TSOP-LF 1/16W
1 0.1UF MF-LF
1
2
5
6
20%
DEVELOPMENT 2 DEVELOPMENT 10V
2 CERM 2 402
CRITICAL R1308 5
R13511 402 9 LED_PP1V2_RUN_P
1 C1321 Q1306 2
100K 1
Q1003_G 3 6 100K
0.01UF
B PP5V_ALL SI3446DV B
r
20% 5%
16V RDSON=0.04 OHM 5% 1/16W DEVELOPMENT
2 CERM TSOP-LF @ VGS=2.5 V 1/16W 4 DEVELOPMENT MF-LF 1
402
MF-LF 402 2 LED1300
402
RDSON=0.04 OHM R1353 3
DEVELOPMENT GREEN-3.6MCD
@ VGS=2.5 V
1
0 2 PP1V2_RUN_FOR_LED 4 LM339A
2.0X1.25MM-SM
3
9 2
DEVELOPMENT V+ SOI-LF
R1309 C1322 5%
1/16W
U1201 2 9 LED_PP1V2_RUN_N
100K 1 0.01UF MF-LF
402 GND
2 Q1006_G 1 2 85 12 11 1V1_REF 5
PLACE LED NEAR VREG
5% 12
1/16W 20% DEVELOPMENT
P
MF-LF 16V
CERM 1
402
R1312 402 R1352
47K
0 3 5%
13 12 4 TURN_ON_PP1V2_L 1 2 1/16W
5%
D Q1305 3 DEVELOPMENT NOSTUFF 3 MF-LF
402 2
1/16W 2N7002
NOSTUFF
MF-LF
402 Q1305_G 1 G S
SOT23-LF D Q1304 Q1307 D
2N7002 2N7002
R1313 2 1 G S
SOT23-LF SOT23-LF
S G 1 SYS_SLEEP 11 12 15 16 26 30 54
PWRON_L 1
0 2
16 15 12 11
2 2
5%
1/16W NOSTUFF
MF-LF
402 R1314
TURN_ON_PP1V2_L 1
0 2 Q1304_G
13 12 4
5%
1/16W
MF-LF
402
DEVELOPMENT DEVELOPMENT
R1315 1 C1320
85 GPU_POWERUP_L 1
47K 2 0.01UF
20%
1.2V Vreg
5% 16V
A 1/16W
MF-LF
402
2 CERM
402
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
PP1V2_PWRON COMES UP BEFORE GPU_POWERUP_L SO THAT SHASTA CORE GETS POWER BEFORE ANYTHING ELSE
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 13 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP2V5_ALL VOLTAGE REGULATOR
NOTE:
SET OUTPUT=2.5V
D IRU3037CS VREF=1.24VDC D
CRITICAL
VOUT=VREF*(R1581+R1582)+1=5.505VDC
y
PP2V5_ALL
PP3V3_ALL U1580 POWER BUDGET CURRENT OF TOTAL RAILS
MIC39102 0.2A PEAK
SOP-8-LF
3
0.1A CONTINUOUS
2
IN OUT
r
1
EN ADJ 4 U1580_ADJ 1
CRITICAL
1 C1580 1 R1581 1
C1583
R1580 GND 1.02K
10UF 3.3K 5 6 7 8 1% 330UF
20% 5% 1/16W 20%
6.3V
2 CERM 1/16W MF-LF 2 6.3V
MF-LF 402 ELEC
1206 402
2 6.3X8-SM
2
1
R1582
a
U1580_EN 1K
1%
1/16W
MF-LF
2 402
i n C
PP2V5_PWRON FET SWITCH
PEAK CURRENT 0.1A
PP2V5_ALL
PP2V5_PWRON
il m PP2V5_RUN FET SWITCH
PEAK CURRENT 0.1A
CRITICAL
Q1503
SI3446DV
PP2V5_ALL
PP2V5_RUN
e
PP5V_ALL TSOP-LF 1
1
2
5
6
1 C1581CRITICAL 2
0.01UF R1508 5
2
20%
16V Q1506 2
100K 1
Q1503_G 3 6
B PP5V_ALL CERM SI3446DV B
r
402 RDSON=0.04 OHM 5%
TSOP-LF @ VGS=2.5 V 1/16W 4
MF-LF
402
RDSON=0.04 OHM
@ VGS=2.5 V
3
R1509
100K 1
2 Q1506_G C1582
5%
1/16W
0.01UF
MF-LF 1 2
402
P
NOSTUFF 20%
NOSTUFF OPTION TO DELAY 2.5V PWRON TO COME UP WITH 3.3V PWRON 16V
R1512 CERM
0 3 402
16 4 TURN_ON_PP3V3_PWRON_L 1 2
5%
D Q1505 Q1504 3 6
Q1504
1/16W 2N7002
MF-LF SOT23-LF 2N7002DW-X-FD D 2N7002DW-X-F
402 Q1505_G 1 G S SOT-363 SOT-363
R1513 2 5 G S S G 2 SYS_SLEEP 11 12 13 16 26 30 54
PWRON_L 1
0 2
16 13 12 11
4 1
5%
1/16W
MF-LF
402
2.5V Vreg
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 15 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
PP12V_ALL
PP5V_ALL
r y
a
1 C1600
R16021 0.01UF
20% 5 6 7 8
3.6K 16V
5% 2 CERM CRITICAL
1/16W
MF-LF
402 2
402
Q1600
IRF7413PBF
SO-8
n
GATE_5V_PWRON 4
6 1
R1601 1 2 3
i
7 6 PP3V3_RUN
D
Q1601 47K
5%
2N7002DW-X-F 1/16W
C R16051
PP3V3_ALL 2 G S
SOT-363 MF-LF
2 402
PP5V_PWRON C
10K 1
5%
1/16W
MF-LF
402 2
1 C1603
0.1UF
20%
SYS_POWERUP 10V
2 CERM
402
PP3V3_ALL
PWRON_L 11 12 13 15
5
SN74LVC1G02
m
1 SOT23-5-LF PP12V_ALL
4
3 2
U1601
54 30 26 15 13 12 11 SYS_SLEEP 02
C1601
il
1
D
Q1603 3 1
R1607 0.1UF
2N7002 5 6 7 8
SOT23-LF NOSTUFF 3.6K 20% CRITICAL
96 7 SYS_POWERUP_L_BUF 1 G S 5% 2 10V
1
R1604 1
R1608 1/16W
MF-LF
CERM
402 Q1602
2 0 10K 2 402
IRF7413PBF
5% 5% SO-8
1/16W 1/16W 4
MF-LF MF-LF GATE_3V3_PWRON
2 402 2 402
3
1
NOSTUFF
D Q1601 R1600 1 2 3
R1603 2N7002DW-X-F 47K
5%
TURN_ON_PP3V3_PWRON_L 1
0 2 Q1601G 5 G
SOT-363 1/16W
15 4 S MF-LF
e
PP3V3_PWRON
5% 2 402
1 NOSTUFF
1/16W
MF-LF R1609 4
402 3.3K
POWER SEQUENCING PIN TO DELAY TO BRING UP 3.3V LAST FOR SHASTA 5%
1/16W
MF-LF
2 402
B B
A
P r 5V & 3.3V Fets
SYNC_MASTER=FINO-M23 SYNC_DATE=08/26/2005
A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 16 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
- VESTA1V2_BURST / VESTA1V2_PULSE
Controls operating mode of Vesta 1.2V
D regulator. If both options are off the
regulator will be in continuous mode.
D
r y
C
VESTA JTAG
139 132 17 7 =PP3V3_ENETFW
i n a C
m
1
VESTA HAS INTERNAL PULLUPS. MLB R1741 1R1742 1R1743
1K 1K 1K
PULLUPS MAY BE NOSTUFFED IN EVT. 5% 5% 5%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
il
2 402 2 402 2 402
9
TP_JTAG_VESTA_TCK =JTAG_VESTA_TCK 17
9
TP_JTAG_VESTA_TDI MAKE_BASE=TRUE
=JTAG_VESTA_TDI 17
9 TP_JTAG_VESTA_TDO MAKE_BASE=TRUE
=JTAG_VESTA_TDO 17
MAKE_BASE=TRUE
9
TP_JTAG_VESTA_TMS =JTAG_VESTA_TMS 17
9 TP_JTAG_VESTA_TRST_L
MAKE_BASE=TRUE
=JTAG_VESTA_TRST_L
17
MAKE_BASE=TRUE
1
R1740 M23: ADDED C1726 AND C1744 PER BROADCOM RECOMMENDATIONS
1K
e
5%
1/16W
MF-LF
2 402
=PP2V5_ENETFW 7 132 139
L1700 PP1V2_VESTA_AVDDL
139 132 7 =PP1V2_ENETFWFERR-EMI-600-OHM MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.25 MM C1720 1 C1721 1 C1722 1 C1723 1 C1724 1 C1725 1 C1726 1
B B
r
1 2 VOLTAGE=1.2V
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10UF
20% 20% 20% 20% 20% 20% 10%
SM 10V 10V 10V 10V 10V 10V 6.3V
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 X5R 2
M23: PP3V3_ENETFW IS AN ALL RAIL 1 C1708 1 C1700 1 C1701 1 C1702 1 C1703 402 402 402 402 402 402 805
139 132 17 7 =PP3V3_ENETFW 10UF 0.1uF 0.1uF 0.1uF 0.1uF
10% 20% 20% 20% 20%
6.3V 10V 10V 10V 10V
2 X5R 2 CERM 2 CERM 2 CERM 2 CERM
805 402 402 402 402
L6/M6 L9/M9 N5/N6 N9/N10 C1730 1 C1731 1
R17501 0.1uF 0.1uF
10K 20% 20%
P
10V 10V
M23: PP3V3_ENETFW IS AN ALL RAIL 5% CERM 2 CERM 2
1/16W 402 402
B15
C15
N10
P10
P11
R12
A15
MF-LF
=PP3V3_ENETFW C1714 C1710 C1711 C1712 C1713
B1
J1
L6
L9
M6
M9
N5
N6
N9
P4
P5
R3
N4
139 132 17 7 402 2 1 1 1 1 1
10UF 0.1uF 0.1uF 0.1uF 0.1uF
1
R1751 10%
6.3V
20%
10V
20%
10V
20%
10V
20%
10V
DVDD AVDDL AVDD PVDD =PP3V3_ENETFW 7 17 132 139
2 X5R 2 CERM 2 CERM 2 CERM 2 CERM
47K 805 402 402 402 402
5%
1/16W
MF-LF 6 A1
C1740 1 C1741 1 C1742 1 C1743 1 C1744 1
0.1uF 0.1uF 0.1uF 0.1uF 10UF
2 402 =PP3V3_ENETFW
OVDD
20% 20% 20% 20% 10%
D Q1750 7 17 132 139 A7
10V
CERM 2
10V
CERM 2
10V
CERM 2
10V
CERM 2
6.3V
X5R 2
VESTA_RESET_RC 2N7002DW-X-F F15
2 G S
SOT-363 VESTA_RESET_L
SCHMITT TRIGGER W/ INTERNAL PULLUP
H4 RESET* IPU VESTA MISC K1
402 402 402 402 805
1
1 C1750 1
R1752 17 =JTAG_VESTA_TDI D7 TDI IPU 2.5V_EN
1UF 10K SEE_TABLE
5% 17 =JTAG_VESTA_TDO E10 TDO 0 - OVDD=3.3V
10% 1/16W IPD 2.5V_EN M3 TP_VESTA_2_5V_EN 9
2 6.3V
CERM MF-LF 17 =JTAG_VESTA_TCK E7 TCK IPU U1701 1 - OVDD=2.5V
402 2 402 17 =JTAG_VESTA_TMS E8 TMS IPU VESTA-V1.3 WHEN OVDD=2.5V GMII PINS ARE NOT 3.3V TOLERANT
FBGA-200-LF
17 =JTAG_VESTA_TRST_L D8 TRST* IPU 1 OF 3
RESET ASSERT REQUIREMENT IS 20MS TO 100MS REGSUP1 E1 TP_VESTA_REGSUP1 9
3 REGSEN1 F1 TP_VESTA_REGSEN1 9 Vesta Core / Misc
NOSTUFF REGCTL1 G5 TP_VESTA_REGCTL1 9
A D
Q1750 SYNC_MASTER=FINO-M23 SYNC_DATE=08/26/2005
R1720
0
2N7002DW-X-F
SOT-363
9
9
TP_VESTA_DNC_C9
TP_VESTA_DNC_E9
C9
E9
DNC
DNC NOTICE OF PROPRIETARY PROPERTY
A
24 ENETFW_RESET 1 2 132 VESTA_RESET_H 5 G S
REGSUP2 E2 TP_VESTA_REGSUP2 9
5% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1/16W 4 NC C3 NC REGSEN2 F2 TP_VESTA_REGSEN2 9 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
MF-LF AGREES TO THE FOLLOWING
402 NC M13 NC REGCTL2 G4 TP_VESTA_REGCTL2 9
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
AGND GND III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
H11
H12
J11
J12
L7
L8
M7
M8
N7
N8
P6
P7
P8
P9
A2
B2
B7
C14
F14
J2
K2
SIZE DRAWING NUMBER REV.
To keep Vesta from being held
in reset when system is off
APPLE COMPUTER INC.
D 051-6863 19
NOTE: Reset GPIO is active HIGH
SCALE SHT OF
NONE 17 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
r y
a
7 =PPVCORE_PWRON_NB
1 C1900 1 C1901 1 C1902 1 C1903 1 C1904
1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V
n
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402
i
C1905 C1906 C1907 C1908 C1909
C SEE_TABLE 1
1UF
10%
1
1UF
10%
1
1UF
10%
1
1UF
10%
1
1UF
10%
C
U1900 2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
CERM CERM CERM CERM CERM
KODIAK CORE KODIAK-ASIC-040812 402 402 402 402 402
CORE & PCI-E POWER
PP1900 BGA
P4MM (9 OF 10)
SM
1
1.6V PP
(1.6V-1.2V)
N15
VDD_CORE CORE_GND N14 1
C1910 1
C1911 1
C1912 1
C1913 1
C1914
Q63 = PP1V6 P17 P16 1UF 1UF 1UF 1UF 1UF
m
VDD_CORE CORE_GND 10% 10% 10% 10% 10%
P21 P20 6.3V 6.3V 6.3V 6.3V 6.3V
VDD_CORE CORE_GND 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
R14 R15 402 402 402 402 402
VDD_CORE CORE_GND
R18 R19
VDD_CORE CORE_GND
il
R22 R23
VDD_CORE CORE_GND
T16 T17
VDD_CORE CORE_GND
T20 T21
VDD_CORE CORE_GND
U15 U14
1
C1915 1
C1916 1
C1917 1
C1918 1
C1919
VDD_CORE CORE_GND 1UF 1UF 1UF 1UF 1UF
U19 U18 10% 10% 10% 10% 10%
VDD_CORE CORE_GND 6.3V 6.3V 6.3V 6.3V 6.3V
V17 V16 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
VDD_CORE CORE_GND 402 402 402 402 402
V21 V20
VDD_CORE CORE_GND
W14 W15
VDD_CORE CORE_GND
W18 W19
VDD_CORE CORE_GND
W22 W23
VDD_CORE CORE_GND
e
Y16 Y17 1 1 1 1 1
VDD_CORE CORE_GND C1920 C1921 C1922 C1923 C1924
Y20
VDD_CORE CORE_GND Y21 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
AA15 AA14 6.3V 6.3V 6.3V 6.3V 6.3V
VDD_CORE CORE_GND 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
AA19 AA18 402 402 402 402 402
VDD_CORE CORE_GND
B AA23 VDD_CORE CORE_GND AA22
B
r
AB17 VDD_CORE CORE_GND AB16
AB21 VDD_CORE AB20
CORE_GND
AC14 VDD_CORE CORE_GND AC15
AC18 AC19
VDD_CORE CORE_GND
AC22 AC23
VDD_CORE CORE_GND
A
P PAGE 19
KODIAK CORE & BYPASS
SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
LAST_MODIFIED=Tue Aug 30 18:05:11 2005
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
A
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
2
NONE
19 154
8 7 6 5 4 3 2 1 DRAWING
8 7 6 5 4 3 2 1
D KODIAK ALIASES D
y
SHASTA GPIO TERMINATIONS
SHASTA ALIASES (SOME OF THESE ARE NOSTUFF
NC_PMR_CLK_DIS_L PMR_CLK_DIS_L 20
ON PAGE 24 ) 6
MAKE_BASE=TRUE
r
119 56 24 23 7 =PP3V3_PWRON_SB
PCI_RESET_L IS AN ’AND’ OF SB_PCI_RESET_L (SB) =PP2V5_PWRON_NB_MISC 7 20 28 30 39
AND SYS_IO_RESET_L (SMU)
a
R2073
1
119 92 PCI_RESET_L
=PCI_AIRPORT_RESET_L
4.7K
MAKE_BASE=TRUE 121 5%
1/16W NOSTUFF
MF-LF
=PCI_ROM_RESET_L 125 KODIAK JTAG_TRST PULLED HIGH 2 402
=PCI_USB2_RESET_L 122
R2074
TO ALLOW SMU DEBUG ACCESS 20 9 JTAG_NB_TRST_L 1
0 2 NB_PU_RST_L 20 30
5%
24 NB_SLOT_RESET_L =GPU_RESET_L 84 NOSTUFF 1/16W
n
MAKE_BASE=TRUE MF-LF
R2054
1 402
4.7K
5%
1/16W
MF-LF
i
2 402
SHASTA JTAG
R2061
C 24 9 JTAG_SB_TRST_L
24 RAI_EXP_INTR_L<3> 1
10K 2 =PP1V8_PWRON_NBMEM 7 39 58 59
C
5%
THESE PINS HAVE INTERNAL PULLUPS OR PULLDOWNS
1/16W
MF-LF R2062
402 10K
9 TP_JTAG_SB_TCK
MAKE_BASE=TRUE
JTAG_SB_TCK 24 1
R2053 24 RAI_EXP_INTR_L<2> 1 2 1 C2055
9 TP_JTAG_SB_TDI JTAG_SB_TDI 24 4.7K 5% 1UF
10%
9
MAKE_BASE=TRUE
TP_JTAG_SB_TDO JTAG_SB_TDO 24
5%
1/16W R2063 1/16W
MF-LF 6.3V
2 CERM
MAKE_BASE=TRUE MF-LF
1
10K 2
402 402
9 TP_JTAG_SB_TMS JTAG_SB_TMS 24
2 402 24 RAI_EXP_INTR_L<1>
MAKE_BASE=TRUE
5%
R2064
m
1/16W
MF-LF 39 30 28 20 7 =PP2V5_PWRON_NB_MISC
RAI_EXP_INTR_L<0>
402
1
10K 2
24
5%
1/16W P4MM
U1900
il
MF-LF SM
402 C2055 ADDED FOR KODIAK RAM DECOUPLING 1
PP
KODIAK-ASIC-040812 TP2002 R2003 1
PAGE 58 IS SHORT ONE CAP 1K
1%
BGA
1/16W
MF-LF
(10 OF 10) 402
2
NORTH_BRIDGE_RESET_L AL01 NB_PU_RST_L 20 30
JTAG_NB_TCK AJ04
POWER/TEST/MISC
30 9 CE1_LT_TCK AG01 NB_HRST_L
AG07
HRESET_L
30 9 JTAG_NB_TDI CE1_MC_TDI
30 9 JTAG_NB_TDO AG05 CE1_B_TDO SUSPENDACK_L AJ03 NB_SUSPEND_ACK_L 30 62
30 9 JTAG_NB_TMS AL02
CE1_DI1_TMS SUSPENDREQ_L AJ01 NB_SUSPEND_REQ_L 30
e
JTAG_NB_TRST_L AK06 CE1_DI2_TRST
20 9
SYS_ISCA0 AG04 I2C_NB_B_SDA 39
AK03 I2C_NB_B_SCL
SYS_ISCL0 39
CE0TEST AG08 CE0_TEST
SYS_ISCA1 AH06 I2C_NB_C_SDA 39
NB_OVERTEMP SYS_ISCL1 AJ05 I2C_NB_C_SCL 39
B NOSTUFF NB_THERM_A F15
SYS_THDIO_D
B
r
20
30 28 7 =PP3V3_RUN_SMU R2087 20 NB_THERM_K G15
SYS_THDIO_G API_ISCA AG03 I2C_NB_A_SDA 39
0
MIN_LINE_WIDTH=0.38mm TSENSE_NB_OVERTEMP_L 1 2 SYS_OVERTEMP_L API_ISCL AH03 I2C_NB_A_SCL
R2082 MIN_NECK_WIDTH=0.38MM
24 28 93 39
2.2 5% 39 30 28 20 7 =PP2V5_PWRON_NB_MISC AF02 VD5_0
1 2 TSENSE_NB_VCC 1/16W PMR_CLK_P AE09 NB_PMR_CLK_P 26 27
AF05
MF-LF VD5_1 AE10 NB_PMR_CLK_N
5% 402 PMR_CLK_N 26 27
1/16W 1
C2080 AH01
VD5_2
MF-LF
1UF 1 1
NOSTUFF
402
10% 2
CRITICAL R2083 R2084 AG02
NOSTUFF NOSTUFF
6.3V
PMR_CLK_STOP_L 1 1
2 CERM VCC 1K 1K R2001 R2002
402 5% 5% NEED TO CHECK ALL I2C ADDRESSES C2050 1
C2051 1
C2052 1
15 ALERT 11 60.4 60.4
P
STBY 1/16W 1/16W 1UF 1UF 1UF
U2080 MF-LF
402
MF-LF
402
A0 | A1 | ADDR
----+----+------
10% 10% 10% 1%
1/16W
1%
1/16W
2 2 6.3V 6.3V 6.3V
MAX6690MEE 0 | 0 | 30/31
CERM 2 CERM 2 CERM 2 1 MF-LF MF-LF
39 I2C_NB_TEMP_SDA 12 SMBDATA ADD0 10 TSENSE_NB_ADD0 0 | hiZ| 32/33
402 402 402 R2000 402 402
0 | 1 | 34/35
2 2
39 I2C_NB_TEMP_SCL 14 SMBCLK ADD1 6 TSENSE_NB_ADD1 hiZ | 0 | 52/53 0
hiZ | hiZ| 54/55 5% TERM_RC
20 NB_THERM_A QSOP 1NOSTUFF 1
hiZ | 1 | 56/57 1/16W
MIN_LINE_WIDTH=0.25mm C2081 NC_1 1 R2086 R2085 1 | 0 | 98/99 MF-LF
MIN_NECK_WIDTH=0.25MM 3 DXP (SYM_VER2)
1 | hiZ| 9A/9B 402 NOSTUFF
2
DIFFERENTIAL_PAIR=TSENSE_NB 0.0022UF NC_5 5 1K 1K 1 | 1 | 9C/9D
1 2
4 DXN 5% 5% 1 C2053
NET_PHYSICAL_TYPE=10MIL_WIDTH
NC_9 9 1/16W 1/16W 1.5PF
NET_SPACING_TYPE=TSENSE_DIFPAIR MF-LF MF-LF
+/-0.25PF
PLACE BY IC NC_13 13 2 402 2 402
SM
10% 50V
P4MM XW2000 2 CERM
50V
NC_16 16 SM
402
1
CERM 1 6 PP_2V5PWRONNBMISC
NB_THERM_K 402 PP
20
MIN_LINE_WIDTH=0.25mm GND TP2000
MIN_NECK_WIDTH=0.25MM 7 8 1
DIFFERENTIAL_PAIR=TSENSE_NB R2013
NET_SPACING_TYPE=TSENSE_DIFPAIR 10K PLACE TERM R/C CLOSE TO KODIAK
5%
NET_PHYSICAL_TYPE=10MIL_WIDTH 1/16W
MF-LF
NOSTUFF 2
402
R2012
20
PMR_CLK_DIS_L 1
0
2 NB_PMR_CLK_STOP_L KODIAK & SHASTA MISC
5% NOTE: LOW = DISABLE PMR_CLK
A NOTE:
1/16W
MF-LF
402
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
PMR_CLK_STOP CAN BE USED TO STOP ALL CLOCKS IN KODIAK
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
USED FOR DEBUG AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
PLACE R2012 IN AN ACCESSIBLE LOCATION
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
20 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
- =PP3V3_PWRON_SB_PCI64 (VIO1) (TO 5V OR 3.3V)
- =PP3V3_PWRON_SB_PCI32 (VIO2) (TO 5V OR 3.3V)
- =PP3V3_PWRON_SB
- =PP2V5_PWRON_SB
- =PP1V2_PWRON_SB_VCORE
SM
XW2300 P4MM
NOTE: PCI pads use the VIO supply to meet SM
PP_1V2PWRONSBVCORE
1
6 1
different drive timing
PP PP2300
characteristics required by the PCI
D spec for 5V vs. 3.3V operation.
CONNECT VIO2 TO
D
appropriate PCI bus voltage and
y
VIO1 TO SAME IF 64-BIT
SM
PCI, otherwise 3.3V. XW2303 P4MM
SM
PP_3V3PWRONSBPCI64
1
6 1
Signal aliases required by this page:
PP PP2303
SM
(NONE) XW2304 NO_TEST=YES P4MM
r
SM
1
6 PP_2V5PWRONSB 1
PP PP2304
BOM options provided by this page:
(NONE)
Power Sequencing:
Must power Shasta VCore rail before any
other Shasta supplies.
=PP2V5_PWRON_SB 7 23 24 119 138
a
7
=PP1V2_PWRON_SB_VCORE
1 1
C2350 C2351
0.1uF 0.1uF
20% 20%
H15
J12
J15
L15
M15
P15
R10
R12
T10
T15
1 C2300 1 C2301 1 C2302 1 C2303 1 C2304 10V 10V
H8
K8
L8
N8
R9
2 CERM 2 CERM
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 402 402
20% 20% 20% 20% 20% VDDC
10V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM AA1 D19
402 402 402 402 402
n
AA2 VDDO25 G15
AA3
U2300
SHASTA =PP3V3_PWRON_SB_PCI64 7
AB10
V1.1 H18
i
1
C2305 1
C2306 1
C2307 1
C2308 1
C2309 AB2 BGA-LF
H17
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF AB6 (1 OF 8) VIO1
20% 20% 20% 20% 20% K21 1
C2355 1
C2356 1
C2357
C 2
10V
CERM
402
2
10V
CERM
402
2
10V
CERM
402
2
10V
CERM
402
2
10V
CERM
402
B1
B2
POWER 2
0.1uF
20%
10V
2
0.1uF
20%
10V
2
0.1uF
20%
10V
C
VDDO33
B5 L21 CERM CERM CERM
402 402 402
D1 SEE_TABLE W22
VIO2
F4 Y19
For PCI_AD<63..32>
1
C2310 1
C2311 1
C2312 1
C2313 1
C2314 F8
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
20% 20% 20% 20% 20% H1
2
10V
2
10V
2
10V
2
10V
2
10V
VDDP_KL V8 =PP3V3_PWRON_SB_PCI32 7
CERM CERM CERM CERM CERM L7
402 402 402 402 402
M1
m
R2
U12
1
C2360 1
C2361 1
C2362
Shasta max (est 06/30/03) current:
0.1uF 0.1uF 0.1uF
U9 20% 20% 20%
119 56 24 20 7
=PP3V3_PWRON_SB 2
10V
2
10V
2
10V
il
V7 CERM CERM CERM
DIGITAL - 1.2V - 950 mA (1175 mW)
402 402 402
W4
ANALOG12 - 1.2V - 600 mA ( 760 mW)
VDDPs - 2.5V - 100 mA ( 250 mW) For PCI_AD<31..0>
1
C2320 1
C2321 1
C2322 1
C2323 1
C2324 A1
I/O 2.5 - 2.5V - 20 mA ( 60 mW)
W5
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF A2
I/O 3.3 - 3.3V - 220 mA ( 770 mW)
W19
20% 20% 20% 20% 20% =PP2V5_PWRON_SB 7 23 24 119 138
10V 10V 10V 10V 10V A22 U22
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
Total: 3015 mW
402 402 402 402 402 A5 U13
AA10 U10
1
AA6 T12
C2365
0.1uF
AB1 R19 20%
1
C2325 1
C2326 1
C2327 1
C2328 1
C2329 2
10V
e
AB22 P9 CERM
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 402
20% 20% 20% 20% 20% C19 P4
10V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM D2 GND P14
402 402 402 402 402 GND
E22 P13
F3 P12
B B
r
F7 P10
1
C2330 1
C2331 1
C2332 1
C2333 1
C2334 H2 N9
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF H9 N22
20% 20% 20% 20% 20%
10V 10V 10V 10V 10V J10 N13
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 J11 N12
J13 N11
J14 N10
J16 M2
1
C2335 1
C2336 1
C2337 1
C2338 1
C2339
P
GND
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
J22
K10
K11
K12
K13
K7
K9
L10
L11
L12
L13
L14
L16
L9
M10
M11
M12
M13
M14
20% 20% 20% 20% 20%
10V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402
Shasta Core Power
A SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
LAST_MODIFIED=Tue Aug 30 18:05:13 2005 23 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR =PP3V3_PWRON_SB
119 56 24 23 20 7
I2S0_TO_SB I2S0_DEV_TO_SB_DTI 24 147
I2S0_TO_DEV I2S0_SB_TO_DEV_DTO 24 147
R2464
I2S0_TO_DEV AUDIO I2S1_RESET_L 10K
I2S0_MCLK 24 154 24 8 1 2
I2S0_BIDIR I2S0_BITCLK 24 147 5%
1/16W
I2S0_BIDIR I2S0_SYNC 24 147 MF-LF
AUDIO PAGES IS RESPONSIBLE FOR TERMINATION OF I2S0 AND I2S2 402
I2S1_TO_SB I2S1_DEV_TO_SB_DTI 8 24 DO NOT ADD PULLUP/DOWN FOR I2S0 AND IS=2S2 IN THIS PAGE
I2S1_TO_DEV I2S1_SB_TO_DEV_DTO 8 24
SM
I2S1_TO_DEV 0.25mm SPACING XW2400 P4MM
I2S1_MCLK 8 24 6 PP_1V2PWRONSBPLL45VDD SM
1
1
I2S1_BIDIR I2S1_BITCLK PP PP2400
8 24
R2463
I2S1_BIDIR I2S1_SYNC 8 24 10K
D I2S2_TO_SB I2S2_DEV_TO_SB_DTI 24 154
PP1V2_PWRON_SB_PLL45VDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.50mm R2420 =PP1V2_PWRON_SB 7
24
SB_GPIO_H_3 1
5%
2
D
I2S2_TO_DEV MIN_NECK_WIDTH=0.38mm 3.3 1/16W
R2450
I2S2_SB_TO_DEV_DTO 24 154 1 2 MF-LF
y
I2S2_TO_DEV 0.25mm SPACING NB_CHP_FLT_N_B 402 10K
I2S2_MCLK 24 154 5% 24 1 2
1/8W
I2S2_BIDIR I2S2_BITCLK C2421 1
C2420 1 MF-LF 5%
24 154
805 R2451 1/16W
I2S2_BIDIR I2S2_SYNC 24 154
1uF 10UF 10K MF-LF
10% 10%
24
SB_SFC_RESET_L 1 2 402
SB_CLK18M_XTAL 0.38mm SPACING =PP2V5_PWRON_SB 7 23 119 138
6.3V
CERM 2
6.3V
X5R 2
SB_CLK18M_XTALI 5%
24 402 805 R2452
r
1/16W
0.38mm SPACING SB_CLK18M_XTALO 24 MF-LF 10K
28 24 SB_CPU_VDNAP1 402 1 2
0.38mm SPACING SB_CLK18M_XTALO_R 24
PP2V5_PWRON_SB_XTAL18VDD 5%
SB_CLK25M_ATA 0.38mm SPACING SB_CLK25M_SATA 1/16W
24 26
R2405 VOLTAGE=2.5V
MIN_LINE_WIDTH=0.50mm VOLTAGE=1.2V
R2453 MF-LF
P3MM SPACING NB_TO_SB_INT 24 3.3 MIN_NECK_WIDTH=0.38mm 10K 402
I586
1 2 MIN_LINE_WIDTH=0.50mm 28 24 SB_CPU_VDNAP2 1 2
P3MM SPACING SB_CPU_A0_INT_L
I587 24
5% MIN_NECK_WIDTH=0.38mm R2430 5%
P3MM SPACING SB_CPU_A1_INT_L 1/8W 1
C2400 1
C2401 3.3 1/16W
I588 24
MF-LF PP1V2_PWRON_SB_PLL49VDD 1 2 MF-LF R2454
P3MM SPACING SB_CPU_B0_INT_L 805 10UF 1uF 402 10K
a
24
I589 10% 10% 5% 28 24
SB_TO_SMU_INT_L 1 2
P3MM SPACING SB_CPU_B1_INT_L 24 2
6.3V
X5R 2
6.3V
CERM
1/8W
I590
PCI_AIRPORT_INT_L 805 402 C2431 1 C2430 1 MF-LF
R2455 5%
I591 P3MM SPACING 24 121
1uF 10UF 805 1/16W
LOGIC_BRD_GOOD 10K MF-LF
I592 P3MM SPACING PCI_USB2_INT_L 24 122
10%
6.3V
10%
6.3V
24 1 2 402
CERM 2 X5R 2
P3MM SPACING I2S0_RESET_L 5%
I593 24 147 402 805 1/16W R2404
P3MM SPACING I2S1_RESET_L 8 24 MF-LF 10K
I594
31 24
SB_VDNAP0 402 1 2
P3MM SPACING I2S2_RESET_L 24 154
I595
PP2V5_PWRON_SB_XTALVDD SAT_PWRON R2460 5%
P3MM SPACING MB_SLOT_RESET_L 1/16W
24 R2410 VOLTAGE=2.5V
n
I596
NB_SLOT_RESET_L MIN_LINE_WIDTH=0.50mm SYS_OVERTEMP_L 1K MF-LF
I597 P3MM SPACING 20 24 3.3 MIN_NECK_WIDTH=0.38mm 93 28 24 20 1 2 402
1 2
P3MM SPACING SB_CPU_A0_SRESET_L 1%
I598 24 56
5% =PP3V3_PWRON_SB 7 20 23 24 56 119 1/16W R2422
P3MM SPACING SB_CPU_A1_SRESET_L 24 56 1/8W MF-LF 10K
I599
MF-LF 1
C2410 1
C2411 143 24
SB_GPIO14 402 1 2
i
SB_CPU_B0_SRESET_L
AA13
P3MM SPACING 805
W14
Y13
Y12
W17
24 56
I600 10UF 1uF 1
C2440 5%
P3MM SPACING SB_CPU_B1_SRESET_L 24 56
10% 10% R2461 1/16W
I601
2
6.3V
2
6.3V 0.1uF 4.7K MF-LF
X5R CERM XTAL XTAL_18 PLL_45 PLL_49 VIO
C Re-pin within each RPAK as necessary
805 402
VDD VDD VDD VDD PME 2
20%
10V
CERM
402
P4MM
24 MB_SLOT_RESET_L 1
5%
1/16W
2 402
NOSTUFF
R2406
C
DO NOT swap between RPAKs
U2300 NET_SPACING_TYPE=P3MM SPACING SM MF-LF 4.7K
1 NB_SLOT_RESET_L
Page Notes SHASTA PP PP2405 24 20 402 1
5%
2
V1.1 1/16W
Power aliases required by this page: BGA-LF
GPIO
R2419 MF-LF
147 24
I2S0_DEV_TO_SB_DTI (I2S0_DEV_TO_SB_DTI) W7
I2S0DTI_H 6 PCI1REQ_3_L U17 NB_CHP_FLT_N_B 24 10K 402
(2 OF 8) PCIX_INT_L 1 2
- _PP3V3_PCI - _PP3V3_PWRON_SB
I2S0_SB_TO_DEV_DTO RP2410 3 6 33 I2S0_SB_TO_DEV_DTO_R Y5 AA19 SB_SFC_RESET_L 24
I2S0DTO_H PCI1GNT_3_L
I2S0: Audio DAC
147 24 7 24
I2S0
- _PP2V5_PWRON_SB - _PP1V2_PWRON_SB
=PP3V3_RUN_SB_PCI I2S0_MCLK RP2410 4 5 33 I2S0_MCLK_R U8
5%
7 24 154 24 I2S0MCLK_H AB21 SB_CPU_VDNAP1
1/16W
I2S0_BITCLK RP2420 1 8 33 8 PCI1REQ_4_L 24 28 MF-LF
Signal aliases required by this page: (NONE) 147 24 I2S0_BITCLK_R AA4
I2S0BITCLK_H 402
AA20 SB_CPU_VDNAP2
m
I2S0_SYNC RP2410 2 7 33 9 PCI1GNT_4_L 24 28 5%
I2S0_SYNC_R Y6
I2S0SYNC_H 402
BOM options provided by this page:
147 24
R2457 MF-LF
1
PCI1REQ_5_L U16 SB_TO_SMU_INT_L 10K 1/16W
- PCI_64BIT: Configures Shasta for 64-bit PCI
R2476 24 8
I2S1_DEV_TO_SB_DTI (I2S1_DEV_TO_SB_DTI) V10
I2S1DTI_H
10 24 28
24 GIGE_P1_INTA_L 1 2
10K Y20 LOGIC_BRD_GOOD
I2S1_SB_TO_DEV_DTO RP2420 3 6 33 11 PCI1GNT_5_L 24
NOTE: XGC required for Shasta GPIOs 5% 24 8 I2S1_SB_TO_DEV_DTO_R AB5
I2S1DTO_H
il
I2S1: Soft Modem
1/16W RP2430 R2413
I2S1
- MPIC_NB/MPIC_SB: Selects whether NorthBridge or MF-LF To SouthBridge -> 24 8
I2S1_MCLK 2 7 33 I2S1_MCLK_R V9
I2S1MCLK_H 12 PCI1AD_32_H D18 SB_VDNAP0 24 31
2 402 I2S1_BITCLK RP2430 3 6 33 SYS_OVERTEMP_L 10K
I2S1_BITCLK_R
(SCCA)
AA8 I2S1BITCLK_H A20 GIGE_P2_INTB_L 2 1
SouthBridge MPIC will be used for 24 8 13 PCI1AD_33_H 20 24 28 93 24
interrupt controller. NB_TO_SB_INT 24 RP2410
I2S1_SYNC 1 8 33 I2S1_SYNC_R AA7
I2S1SYNC_H PCI1AD_34_H F18 SB_GPIO14 5% 5%
24 8 14 24 143
R2414 1/16W 1/16W
MPIC_SB 3 I2S1_RESET_L (I2S1_RESET_L) V5
GPIO_H_0 PCI1AD_35_H F17 MB_SLOT_RESET_L R2432 10K MF-LF MF-LF
R2475 MPIC_SB
24 8 15 24
0 24 RAI_ALERT_L 2 1 402 402
10K 16 PCI1AD_36_H G16 NB_SLOT_RESET_L_R 1 2 NB_SLOT_RESET_L 20 24
42 NB_CPU_A0_INT_L 1 2 NB_INT_L_R 1
Q2476 154 24
I2S2_DEV_TO_SB_DTI (I2S2_DEV_TO_SB_DTI) AA5 I2S2DTI_H
FROM NORTHBRIDGE RP2430 17 PCI1AD_37_H F16 PCI_AIRPORT_INT_L 24 121 5%
5% 2N3904LF I2S2_SB_TO_DEV_DTO 4 5 33 I2S2_SB_TO_DEV_DTO_R Y8 I2S2DTO_H 1/16W
R2479 1 1/16W SOT23
154 24
RP2420 PCI1AD_38_H A21 PCIX_INT_L 24 MF-LF R2465
I2S2: S/P-DIF
I2S2
18
MF-LF 2 154 24
I2S2_MCLK 4 5 33 I2S2_MCLK_R Y7
I2S2MCLK_H 402 10K
MPIC_NB 0 402 PCI1AD_39_H B21 RAI_EXP_INTR_L<3> 20 RAI_FATAL_L 1 2
I2S2_BITCLK RP2420 2 7 33 I2S2_BITCLK_R AB4
19 24
(SCCB)
5% 154 24 I2S2BITCLK_H C20 RAI_EXP_INTR_L<2> 20 PLACE R2432 CLOSE TO SHASTA NOSTUFF
1/16W
I2S2_SYNC RP2430 1 8 33 20 PCI1AD_40_H 5%
I2S2_SYNC_R W9
I2S2SYNC_H 1/16W
MF-LF
402 2
R2478 MPIC_SB
154 24
21 PCI1AD_41_H G17 RAI_EXP_INTR_L<1> 20 R2462 MF-LF
I2S2_RESET_L
e
0 (I2S2_RESET_L) Y2 1K
SB_CPU_A0_INT_L 154 24 GPIO_H_1 RAI_EXP_INTR_L<0> 20 SYS_SLEWING_L
402
56 CPU_A0_INT_R_L 1 2 24 AUDIO GPIO - see note on right 22 PCI1AD_42_H G18
50 28 26 24 1 2
TO CPU FROM SOUTHBRIDGE
5% =PP3V3_PWRON_SB I2S0_RESET_L AB3
GPIO_H_2 PCI1AD_43_H E19 GIGE_P1_INTA_L 24 1%
GPIO
119 56 24 23 20 7 147 24 23
1/16W NorthBridge / SouthBridge MPIC Routing 1/16W
R2421
24 SB_GPIO_H_3 GIGE_P2_INTB_L 24
W8 F19
MF-LF GPIO_H_3 24 PCI1AD_44_H MF-LF
402
R2400 1 SB_PCI_SEL32BIT W6
PCI_SEL32BIT_H 25 PCI1AD_45_H D20 RAI_ALERT_L 24 24
SMU_TO_SB_INT_L
402
1
10K
2
10K
B B
PCI
E20 RAI_FATAL_L
r
5% 26 PCI1AD_46_H 24 5%
I2C_SB_SCL Y9
I2C
1/16W 39 I2CCLK_H C21 PCI_USB2_INT_L R2415 1/16W
MF-LF 27 PCI1AD_47_H 24 122 MF-LF
402 2 39 I2C_SB_SDA AB7
I2CDATA_H 10K 402
28 PCI1AD_48_H F20 FW_LOWPWR_R 24 24
MAKE_TBEN_SYNC_L 2 1
SHASTA_SYS_IO_RESET_L E9
RESET_L 29 PCI1AD_49_H G19 ENETFW_RESET 17 24 5%
1/16W
PWR_MGT
SB_STOPXTALS_L W10
STOPXTALS_L PCI1AD_50_H C22 MAKE_TBEN_SYNC_L MF-LF
R2402 28 30 24
402
0 43 30 28 SMU_SUSPENDREQ_L U11
SUSPENDREQ_L 31 PCI1AD_51_H D21 ENET_ENERGYDET 24 132
122 119 30 28 SYS_IO_RESET_L 1 2
SB_SUSPENDACK_L V11
SUSPENDACK_L PCI1AD_52_H G20 AUDIO_LO_DET_L
5%
28 32 153
R2407 NO STUFF
1/16W 122 28 SYS_PME_L W18
PCI1PME_L 33 PCI1AD_53_H D22 AUDIO_LO_OPTICAL_PLUG_L 153 0
MF-LF 1 2 FW_LOWPWR 139
402 TP_SB_WATCHDOG V12 INTRWD_H PCI1AD_54_H K18 AUDIO_LI_DET_L
P
9 34 153
PLACE R2402 CLOSE TO SHASTA H19 AUDIO_LI_OPTICAL_PLUG_L
5%
NOTE: It is the responsibility of
necessary pull-ups & pull-downs.
PCI1AD_55_H 154 1/16W
the audio circuit to provide the
35
JTAG_SB_TDI
AUDIO GPIOS
AA11 TDI MF-LF
20
36 PCI1AD_56_H J17 AUDIO_HP_DET_L 154 402
20 JTAG_SB_TDO W11
TDO
37 PCI1AD_57_H F21 AUDIO_MIC_ID 154
JTAG_SB_TCK AB11
TCK
20
PCI1AD_58_H G21 AUDIO_LO_MUTE_L R2466
TEST
38 150
119 56 24 23 20 7
=PP3V3_PWRON_SB 20 JTAG_SB_TMS Y11
TMS 10K
39 PCI1AD_59_H H20 AUDIO_HP_MUTE_L 154 24
FW_LOWPWR_R 1 2
10K JTAG_SB_TRST_L W12
TRST_L
24
SB_CPU_A0_INT_L R2408 1 2 MPIC_NB
20 9
40 PCI1AD_60_H J19 AUDIO_SPKR_MUTE_L 152 5%
1/16W
24
SB_CPU_A1_INT_L R2409 1 2 MPIC_NB SB_TEST_MODE_PD A3
TEST_MODE_H 41 PCI1AD_61_H F22 AUDIO_EXT_MCLK_SEL 154 MF-LF R2467
R2412 ENETFW_RESET 402 10K
24 SB_CPU_B0_INT_L 1 2 MPIC_NB 6 TP_SB_PLLTEST U14 PLLTEST 42 PCI1AD_62_H G22 AUDIO_SPDIFIN_INT_L 154 24 17 1 2
SB_CPU_B1_INT_L R2418 1 2 MPIC_NB 1 TP_SB_FSTEST V14
FSTEST PCI1AD_63_H H21 AUDIO_SPKR_ID 5%
24 R2480 6 43 153
1/16W
5% 4.7K R2468 MF-LF
1/16W 1% 24 SB_CLK18M_XTALI W13
XTAL_18_I 44 PCI1C_BE_4_L J20 SB_CPU_A0_INT_L 24 10K 402
MF-LF 1/16W 132 24
ENET_ENERGYDET 1 2
SB_CPU_A1_INT_L
XTALS
402 MF-LF 24 SB_CLK18M_XTALO_R V13
XTAL_18_O 45 PCI1C_BE_5_L H22
24
402 2 5%
46 PCI1C_BE_6_L K22 SB_CPU_B0_INT_L 24 1/16W
26 24 SB_CLK25M_SATA U15
XTALI MF-LF
47 PCI1C_BE_7_L K20 SB_CPU_B1_INT_L 24 402
NC
V15 XTALO
1
R2490 P4MM 48 PCI1REQ64_L K17 SYS_SLEWING_L 24 26 28 50
200 SM
24 7 =PP3V3_RUN_SB_PCI R2456 1%
1/16W
PP2406 PP
1 49 PCI1ACK64_L L17 SB_CPU_A0_SRESET_L 24 56 Shasta Serial / Misc
10K MF-LF 50 PCI1PAR64_H E18 SB_CPU_A1_SRESET_L 24 56
PCI_AIRPORT_INT_L
A 1
5%
1/16W
2 24 121 CRITICAL
Y2490
2 402
SB_CLK18M_XTALO
51 XGI_CLK_H Y4 SB_CPU_B0_SRESET_L 24 56
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
R2459 18.432M 24
U7 SB_CPU_B1_SRESET_L
XGI
MF-LF
1 2
52 XGI_DTO0_H 24 56
10K 402
1 2 PCI_USB2_INT_L 24 122 53 XGI_DTO1_H T9 NB_TO_SB_INT 24 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
SM W2 SMU_TO_SB_INT_L PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
5% 54 XGI_DTI_H 24 AGREES TO THE FOLLOWING
1/16W
MF-LF
SAT_RUN C2490 1 1 C2491
R2416 22pF 22pF XTAL_18 PLL_45 PLL_49 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
402
1K 5% 5% GND GND GND II NOT TO REPRODUCE OR COPY IT
SYS_OVERTEMP_L
AB12
AB13
AA12
1 2 50V 50V
20 24 28 93 CERM 2 2 CERM
402 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
NOSTUFF 1%
1/16W
R2417 MF-LF SIZE DRAWING NUMBER REV.
10K 402
MAKE_TBEN_SYNC_L
1
5%
2 24
SPEC SHOWS LOAD CAPACITANCE OF 16PF FOR 197S0004 APPLE COMPUTER INC.
D 051-6863 19
1/16W
MF-LF SCALE SHT OF
402
NONE
LAST_MODIFIED=Tue Aug 30 18:05:14 2005 24 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L2501 SEE_TABLE
25 7 =PP1V5_PWRON_PULSAR 180-OHM-1.5A MIN_LINE_WIDTH=0.5MM Q63 APPLICATION IS RUN
U2500
MIN_NECK_WIDTH=0.2MM PULSAR2
1 2 BGA
0603
25 7
=PPOVDD_PULSAR B11 B10
VDD_OVDD_1 VSS_OVDD_1
R2501 R2512 C9 B7
4.7 0 VDD_OVDD_2 VSS_OVDD_2
1 2 C2545_1 1 2 A5 A7
VDD_OVDD_3 VSS_OVDD_3
SM
B4
5% 5% P4MM XW2500 B5
D
1/16W 1
C2545 1/16W 1
C2509 VOLTAGE=1.5V SM
PP_OVDD_PULSAR1 A1
VDD_OVDD_4 VSS_OVDD_4
D
1
MF-LF MF-LF 1 6
402 2.2UF 402 0.1UF MIN_LINE_WIDTH=0.64mm PP2500 PP VDD_OVDD_5 VSS_OVDD_5 A3
20% 20%
1
C2511 2
6.3V
2
10V
MIN_NECK_WIDTH=0.2MM
y
CERM1 CERM =PP1V2_PWRON_PULSAR M3
25 7 K4
0.1UF 603 402 VDD_12_1 VSS_12_1
20% M7
10V PLACE NEAR PULSAR2 ON IN SLEEP VDD_12_2 VSS_12_2 K8
2 CERM M10
M12
402
P4MM VDD_12_3 VSS_12_3
SYM 2 OF 2
SM
K12
SM
1
P4MM XW2501 Q63 APPLICATION IS POWER ON VDD_12_4 VSS_12_4 K11
SM
L2503 PP2504 PP H11
1
PP2501 PP
1 6 PP_1V2PWRONPULSAR1 VDD_12_5 VSS_12_5 J10
r
180-OHM-1.5A E12
MIN_LINE_WIDTH=0.5MM VSS_12_6
1 2 MIN_NECK_WIDTH=0.2MM 25 7
=PP1V5_PULSAR K5
VDD_15_12_1
0603 J11
VDD_15_12_2
SM
A9
R2509 R2513 P4MM XW2502 VDD_15_12_3
SM
PP_1V5PULSAR2 C5
1
4.7 0 1 6
1 2 C2569_1 1 2 PP2502 PP VDD_15_12_4
5% 5% VOLTAGE=1.5V F2
1/16W 1
C2569 1/16W 1
C2517 =PP1V5_PWRON_PULSAR
a
25 7
MF-LF MF-LF MIN_LINE_WIDTH=0.64mm VDD_15_C1 VSS_15_C1
402 2.2UF 402 0.1UF ON IN SLEEP L6 M6
20% 20% MIN_NECK_WIDTH=0.2MM VDD_15_C2 VSS_15_C2
NO_TEST=YES
SM
F11
1 C2513 2
6.3V
CERM1 2
10V
CERM
P4MM
SM XW2503 VDD_15_C3 VSS_15_C3 G11
0.1UF 603 402 B8
1
20% PP2503 PP
1 6 PP_1V5PWRONPULSAR2 VDD_15_C4 VSS_15_C4 C8
PLACE NEAR PULSAR2
10V
2 CERM
402 D10
SHARED PIN
P4MM PP1V5_PSL_PLL1 VDD_15_PLL1 VSS_15_PLL1 D12
SM
1 PP1V5_PSL_PLL2 D2
P4MM PP2505 PP VDD_15_PLL2 VSS_15_PLL2 D1
L2505 SM
L4
180-OHM-1.5A PP2506 PP
1 PP1V5_PSL_PLL3 VDD_15_PLL3 VSS_15_PLL3 M4
n
PP1V5_PSL_PLL4 K9
L8
1 2 VDD_15_PLL4 VSS_15_PLL4
MIN_LINE_WIDTH=0.5MM PLL_VDD ON IN SLEEP
0603 MIN_NECK_WIDTH=0.2MM
=PP2V5_PWRON_PULSAR G2
25 7 G1
VDD_25 VSS_25
R2503 R2514
i
4.7 0 L2
1 2 C2503_1 1 2 26 25 PP3V3_PLSR_I VDD_33_BC VSS_33_BC K2
C 5%
1/16W
MF-LF
402
1
C2503
2.2UF
5%
1/16W
MF-LF
402
1
C2501
0.1UF
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.64mm
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.64MM
MIN_NECK_WIDTH=0.22MM
C2
VDD_33_I VSS_33_I E1 C
20% 20% B12 D11
1
C2515 6.3V 10V
MIN_NECK_WIDTH=0.2MM VDD_33_XTAL VSS_33_XTAL
2 CERM1 2 CERM R2510
0.1UF 603 402
0
20% PLACE NEAR PULSAR2 7 =PP3V3_RUN_PULSAR 1 2
10V
2 CERM
402 NOSTUFF 5%
1/16W
R2511 MF-LF
L2507 0 402
180-OHM-1.5A P4MM 25 7 =PP3V3_PWRON_PULSAR 1 2
SM
1 5%
1 2 MIN_LINE_WIDTH=0.5MM PP2507 PP
m
1/16W
0603
MIN_NECK_WIDTH=0.2MM MF-LF
402
R2505 R2515
4.7 0
il
1 2 C2507_1 1 2 PP3V3_PSL_XTAL
5% 5% VOLTAGE=1.5V
1/16W 1
C2507 1/16W 1
C2505
MF-LF
2.2UF MF-LF
0.1UF MIN_LINE_WIDTH=0.64mm
402 402
20% 20% MIN_NECK_WIDTH=0.2MM
1
C2519 2
6.3V
CERM1 2
10V
CERM P4MM =PP3V3_PWRON_PULSAR
25 7
0.1UF 603 402 SM
20% 1
2
10V
PLACE NEAR PULSAR2
PP2508 PP
CERM PP3V3_PLSR_I
402 26 25
L2509 1
C2551 1
C2575
180-OHM-1.5A 0.1UF 0.1UF
MIN_LINE_WIDTH=0.5MM 20% 20%
=PP3V3_PWRON_PULSAR
e
1 2 MIN_NECK_WIDTH=0.2MM 10V 10V
25 7 2 CERM 2 CERM
0603 402 402
R2507 R2516
4.7 0
1 2 C2521_1 1 2
VOLTAGE=3.3V
5% 5% MIN_LINE_WIDTH=0.64mm 25 7 =PP2V5_PWRON_PULSAR
B 1
C2521 1
C2522 MIN_NECK_WIDTH=0.2MM
B
r
1/16W 1/16W
MF-LF MF-LF
402 2.2UF 402 0.1UF 1 C2574
20% 20%
1
C2520 2
6.3V
2
10V 0.1UF
CERM1 CERM 20%
0.1UF 603 402
2
10V
20% CERM
PLACE NEAR PULSAR2
10V 402
2 CERM
402 Q63 APPLICATION IS RUN
Q63 APPLICATION IS PWRON
25 7
=PPOVDD_PULSAR
25 7
=PP1V5_PULSAR
P
1 C2531 1 C2532 1 C2533 1 C2534 1 C2535 1 C2536 1 C2537 1 C2538 1 C2530
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20%
10V 10V 10V 10V 10V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402
25 7 =PP1V5_PWRON_PULSAR
1 C2527 1 C2528 1 C2529 1 C2572
0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20%
10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402
=PP1V2_PWRON_PULSAR
25 7
PULSAR2 POWER
A 1
C2523
0.1UF
1
C2524
0.1UF
1
C2525
0.1UF
1
C2526
0.1UF
1
C2573
0.1UF
SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
20% 20% 20% 20% 20%
10V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
LAST_MODIFIED=Tue Aug 30 18:05:15 2005 25 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
EI_CPU_A_SYSCLK_P 56
PLACE ALL 0-OHM SERIES RESISTORSRES EI_CPU_A_SYSCLK_N 56
ON THIS PAGE NEAR PULSAR
P4MM
SM
1
PP2602 PP
EI_CPU_B_SYSCLK_P 27
R2628 PULLED UP TO PP3V3_RUN ON P.28
0 EI_CPU_B_SYSCLK_N 27
R2612 SLEWING* A12 SYS_SLEWING_L_R 1 2 SYS_SLEWING_L 24 28 50
0 5% 402
28 CLOCK_RESET_L 1 2 PLS2_RESET_L C3 RESET* 1/16W
A6 200MHZ, 1.5VOVDD MF-LF
5% 402 HCLKP_0
B6 200MHZ, 1.5VOVDD
D 25 PP3V3_PLSR_I 39
PLSR2_ASEL_INT_L
I2C_CLOCK_B_SCL
D3
ASEL_INT*
B1 SCLK
HCLKN_0
HCLKP_1 C4 200MHZ, 1.5VOVDD
EI_NB_SYSCLK_P 42 56
D
I2C_CLOCK_B_SDA
U2500 EI_NB_SYSCLK_N 42 56
NOSTUFF 39 B2 A4 200MHZ, 1.5VOVDD
y
SDATA HCLKN_1
1 1 PULSAR2 0 R2629
1 R2614 R2616 1 2 CPU_A_TBEN_CLK_US
R2613 10K 10K PLSR2_PD C1 BGA HCLKP_2 B3 200MHZ, 1.5VOVDD
5% 402
56
10K 5% 5%
PD A2 200MHZ, 1.5VOVDD 1/16W
5% 1/16W 1/16W
SYM 1 OF 2 HCLKN_2 MF-LF
1/16W MF-LF MF-LF PLSR2_TM E3
TEST_MODE NC_CPU_B_TBEN_CLK_US 6 REMOVED R2632 AND R2630
MF-LF 2 402 2 402 HTBEN_0 A11 66MHZ, 1.5VOVDD 9 CPU_A_TBEN_CLK_R MAKE_BASE=TRUE FROM UNUSED CLOCKS FOR EMC
2 402
r
PLSR2_OEMODE E2
OEMODE HTBEN_1 A10 66MHZ, 1.5VOVDD 9 CPU_B_TBEN_CLK_R R2631
0
HSYNC_0 A8 1.5VOVDD 9 CPU_A_APSYNC_R 1 2 CPU_A_APSYNC 56
1 HSYNC_1 B9 1.5VOVDD 9 CPU_B_APSYNC_R 5%
1/16W
R2623 C10 1.5VOVDD 9 NB_APSYNC_R MF-LF
0 HSYNC_2 402 CPU_B_APSYNC 27
NOSTUFF 5%
1 1/16W P4MM GPCLK12_C0 H12 66MHZ, 1.2V 9 HT_SB_REFCLK_R R2633
SM
R2618 1 MF-LF
1
(100MHZ FOR ASPEN)
0
1K R2621 2 402 PP2601 PP HT_NB_REFCLK_H0_R 1 2 NB_APSYNC
a
K3 200MHZ, 1.2V 9 42 56
1% 1K NOSTUFF GPCLK12P_A0
1/16W 1% P4MM GPCLK12N_A0 L3 200MHZ, 1.2V 9 HT_NB_REFCLK_L0_R R2634 5%
MF-LF 1/16W SM 1/16W
1 0 MF-LF
2 402 MF-LF
402
PP2600 PP
M5 200MHZ, 1.2V 9 CLK_RAIREF_200M_P_R 1 2 402 HT_CLK66M_SB 103
2 GPCLK12P_A1
L5 9 CLK_RAIREF_200M_N_R 5%
PLS2_X_IN C12 XIN
GPCLK12N_A1 200MHZ, 1.2V
R2635 1/16W
0 MF-LF
GPCLK12P_B0 L7 300MHZ, 1.2V 9 NB_PMR_CLK_P_R 1 2 402
PLS2_X_OUT C11
XOUT HT_NB_REFCLK_P<0> 98 101
GPCLK12N_B0 M8 300MHZ, 1.2V 9 NB_PMR_CLK_N_R 5%
R2636
1/16W
PLS2_REF15 H10 REF_15 MF-LF 0 HT_NB_REFCLK_N<0> 98 101
NB_PCIE_REFCLK_P_C
n
M9 100MHZ, 1.2V 9 402 1 2
R2600 GPCLK12P_C0
PLS2_REF25 F1 REF_25 GPCLK12N_C0 L9 100MHZ, 1.2V 9 NB_PCIE_REFCLK_N_C 5%
0 R2637 1/16W
54 30 16 15 13 12 11 SYS_SLEEP 1 2 MF-LF
PLS2_REF33 L1 REF_33 GPCLK12P_C1 L10 100MHZ, 1.2V 9 GFX_SLOT_PCIE_REFCLK_P_C 0 402
5% 402 1 2
i
GPCLK12N_C1 M11 100MHZ, 1.2V 9 GFX_SLOT_PCIE_REFCLK_N_C
5% CLK_RAI_200M_P<0> 27
1/16W
L11 9 PCIE_A_REFCLKIN_P_C MF-LF
GPCLK12P_C2 100MHZ, 1.2V
R2639
C
1
R2625
1K
1%
GPCLK12N_C2 L12 100MHZ, 1.2V 9 PCIE_A_REFCLKIN_N_C
402
1
0
2
CLK_RAI_200M_N<0> 27 C
1/16W GPCLK12P_C3 K10 100MHZ, 1.2V 9 PCIE_B_REFCLKIN_P_C R2641 5%
MF-LF 1/16W
402 GPCLK12N_C3 J12 100MHZ, 1.2V 9 PCIE_B_REFCLKIN_N_C 0 MF-LF
2 1 2 402
1
NB_PMR_CLK_P 20 27
R2626 GPCLK12P_C4 G12 9 PCIE_C_REFCLKIN_P_C 5%
R2643
1/16W
1K GPCLK12N_C4 F12 100MHZ, 1.2V 9 PCIE_C_REFCLKIN_N_C MF-LF 0 NB_PMR_CLK_N 20 27
1% 402 1 2
1/16W
MF-LF GPCLK12P_D0 E10 66MHZ, 1.2V 9 NB_DDR_REFCLK_P_R 5%
R2666
NO STUFF 2 402
1/16W
R2652 GPCLK12N_D0 E11 66MHZ, 1.2V 9 NB_DDR_REFCLK_N_R MF-LF 0
1
m
402 1 2
0 R2627 H1 25MHZ, 2.5V 9 CLK_RAI_GIGE_25MHZ_R CLK_KOD_100M_P<0> 82 97
NOSTUFF PLS2_EXTCLK 1 2 1K GPCLK25_E0 5%
NOSTUFF H3 9 QUA0_REF_25MHZ_R 1/16W
5%
1% GPCLK25_E1 25MHZ, 2.5V
R2667 MF-LF
J2600 1 1/16W R2654 1/16W
0 402 CLK_KOD_100M_N<0>
R2662 MF-LF 0
MF-LF
H2 9 SB_CLK25M_SATA_R 1 2
82 97
U.FL-R_SMT 2 402 GPCLK25_F0 25MHZ, 2.5V
il
F-ST-SM
24 402 1 2
3
5% GPCLK25_F1 J3 25MHZ, 2.5V 9 QUA1_REF_25MHZ_R R2674 5%
1/16W NO STUFF 5% 1/16W
MF-LF
R2658 1/16W 0 MF-LF
2 402
MF-LF
GPCLK33_E0 J1 66MHZ, 3.3V 6 PCI_CLK66M_SB_INT_R 1 2 402
330K 402 CLK_PCIE_SLOTA_P<0> 84 97
1 PLS2_INTERM 1 2 J2 9 PCI_CLK33M_SB_EXT_R 5%
GPCLK33_E1 33MHZ, 3.3V
R2675 1/16W
NOSTUFF 5% K1 9 SB_AIRPRT_CLK_33MHZ_R 0 MF-LF CLK_PCIE_SLOTA_N<0> 84 97
1/16W R2656 GPCLK33_F0 33MHZ, 3.3V
1 2 402
2 1 MF-LF 0 9 CLK_RAI_REFCLK_66M_R
R2664 402 1 2 GPCLK33_F1 M1 66MHZ, 3.3V
5%
24 GPCLK33_F2 M2 33MHZ, 3.3V 9 SB_USB2_CLK_33MHZ_R R2668 1/16W
5% 5% 0 MF-LF
1/16W 1/16W 1 2 402
MF-LF CRITICAL MF-LF CLK_RAI_PCIEA_P<0> 27
402 5%
2 402
Y2601 1/16W R2669
MF-LF 0 CLK_RAI_PCIEA_N<0> 27
25.0000M 402 1 2
e
1 2
5%
1/16W R2670
PLS2_X_IN_B 8X4.5MM-SM2 PLS2_X_OUT_B MF-LF 0
402 1 2
CLK_RAI_PCIEB_P<0> 27
5%
1/16W
C2607 1 1
C2605 MF-LF R2671
B 0 CLK_RAI_PCIEB_N<0>
B
r
402 27
33PF 33PF 1 2
5% 5%
50V 50V
5%
CERM 2 2 CERM 1/16W R2672
402 402 MF-LF 0
402 1 2
CLK_RAI_PCIEC_P<0> 27
5%
R2673 1/16W
0 MF-LF CLK_RAI_PCIEC_N<0> 27
1 2 402
5%
R2645 1/16W
0 MF-LF
1 2 402
P
NB_DDR_REFCLK_P 59
5%
1/16W
R2647 MF-LF
0 402 NB_DDR_REFCLK_N 59
1 2
5%
R2649 1/16W
0 MF-LF
1 2 402 CLK_RAI_GIGE_25MHZ 27
5%
R2651 1/16W
0 MF-LF QUASAR CLOCKS ARE RESISTOR DIVIDED DOWN
1 2 402 RAM_ARB0_REF25MHZ 27
TO 1.8V ON QUASAR PAGES
5%
R2653 1/16W
LAST MODIFIED: APR 26, 04
0 MF-LF
1 2 402 SB_CLK25M_SATA 24
5%
1/16W R2655
MF-LF 0
402 1 2 RAM_ARB1_REF25MHZ 27
5%
R2657 PCI_CLK66M_SB_INT 27 119
1/16W
MF-LF 0 PCI_CLK33M_SB_EXT_RR 27 119
402 1 2
5% 402
PULSAR2 CLOCKS
1/16W R2659 MF-LF
0
A MF-LF
402 1
5%
2
1/16W SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
R2660
0
1 2 PCI_CLK33M_AIRPORT 121 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
5% AGREES TO THE FOLLOWING
1/16W R2663
MF-LF 0 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
402 1 2 CLK_RAI_REFCLK_66M 27
II NOT TO REPRODUCE OR COPY IT
5%
1/16W MB_PCIX_REFCLK III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MF-LF
402
R2665 SIZE DRAWING NUMBER REV.
0
1 2 PCI_CLK33M_USB2
5%
27
APPLE COMPUTER INC.
D 051-6863 19
1/16W
MF-LF SCALE SHT OF
402
NONE
LAST_MODIFIED=Tue Aug 30 18:05:16 2005 26 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
N/C ALIASES CLOCK CONSTRAINTS
D D
N/C RAINIER CLOCKS DIFFERENTIAL_PAIR NET_PHYSICAL_TYPE NET_SPACING_TYPE ELECTRICAL_CONSTAINT_SET
y
26 20 NB_PMR_CLK_P NB_PMR_CLK NB_PMR_CLK NB_PMR_CLK_SP NB_PMR_CLK I67
26 20 NB_PMR_CLK_N NB_PMR_CLK NB_PMR_CLK NB_PMR_CLK_SP NB_PMR_CLK I68
6 NC_CLK_RAI_REFCLK_66M CLK_RAI_REFCLK_66M 26
MAKE_BASE=TRUE 119 26 PCI_CLK66M_SB_INT PCI_CLK_SB P3MM SPACING PCI_CLK_SB I69
119 26 PCI_CLK33M_SB_EXT_RR PCI_CLK_SB PCI_CLK_SB PCI_CLK_SB_CAP I70
r
6 NC_CLK_RAI_GIGE_25MHZ CLK_RAI_GIGE_25MHZ 26
MAKE_BASE=TRUE
6 NC_CLK_RAI_200M_P<0> CLK_RAI_200M_P<0> 26
MAKE_BASE=TRUE NOTE:
6 NC_CLK_RAI_200M_N<0>
MAKE_BASE=TRUE
CLK_RAI_200M_N<0> 26 ALL OTHER CLOCK CONTRAINTS ON THEIR
a
RESPECTIVE BUS PAGES
6 NC_CLK_RAI_PCIEA_P<0> CLK_RAI_PCIEA_P<0> 26
MAKE_BASE=TRUE
=PCI_CLK33M_USB2
n
26 PCI_CLK33M_USB2 122
6 NC_CLK_RAI_PCIEA_N<0> CLK_RAI_PCIEA_N<0> 26 MAKE_BASE=TRUE
MAKE_BASE=TRUE
i
6 NC_CLK_RAI_PCIEB_P<0> CLK_RAI_PCIEB_P<0> 26
MAKE_BASE=TRUE
C 6 NC_CLK_RAI_PCIEB_N<0>
MAKE_BASE=TRUE
CLK_RAI_PCIEB_N<0> 26
C
6 NC_CLK_RAI_PCIEC_P<0> CLK_RAI_PCIEC_P<0> 26
MAKE_BASE=TRUE
6 NC_CLK_RAI_PCIEC_N<0> CLK_RAI_PCIEC_N<0> 26
MAKE_BASE=TRUE
m
N/C CPUB CLOCKS
B
6
6
NC_EI_CPU_B_SYSCLK_P
MAKE_BASE=TRUE
NC_EI_CPU_B_SYSCLK_N
MAKE_BASE=TRUE
NC_CPU_B_APSYNC
MAKE_BASE=TRUE
EI_CPU_B_SYSCLK_P
EI_CPU_B_SYSCLK_N
CPU_B_APSYNC
26
26
26
e il B
A
N/C QUASAR CLOCKS
6
NC_RAM_ARB0_REF25MHZ
MAKE_BASE=TRUE
NC_RAM_ARB1_REF25MHZ
MAKE_BASE=TRUE
RAM_ARB0_REF25MHZ
RAM_ARB1_REF25MHZ
26
26
Pr Pulsar Aliases
SYNC_MASTER=FINO-M23 SYNC_DATE=08/26/2005
A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 27 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Real Time Clock
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
I456 SMU_RESET 0.25MM SPACING SYS_NORTH_RESET_L 28 30 29 =PP3V3_ALL_RTC
SMU_CLK10M_XTAL 0.38MM SPACING SMU_CLK10M_XIN 28
I457 SMU_RESET 0.25MM SPACING SYS_IO_RESET_L 24 30 119 122 29 28 7 6 =PP3V3_ALL_SMU
0.38MM SPACING SMU_CLK10M_XOUT 28
I472
P3MM SPACING CLOCK_RESET_L 26 28
0.38MM SPACING SMU_CLK10M_XOUT_R 28
I475
P3MM SPACING SYS_RESET_BUTTON_L 28 29
RTC_CLK32K_XTAL 0.38MM SPACING RTC_CLK32K_X1 28 C2808 1
8
CRITICAL
0.38MM SPACING RTC_CLK32K_X2 0.1uF
28
20% VCC RTC_CLK32K_X1 28
P3MM SPACING SMU_IO_RESET_L 10V
2
I473
28 30
CERM
402
U2801
0.25MM SPACING SYS_NORTH_RESET_L 28 30 PP3V3_ALL_SMU_AVCC DS1338U-33 CRITICAL
D
I474
29 28 7 6 =PP3V3_ALL_SMU
R2815
4.7
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38mm
39 I2C_RTC_SDA 5 SDA
MSOP
X1 1
1
Y2801
32.768K
D
1 2 X2 2
MIN_NECK_WIDTH=0.2MM 39 I2C_RTC_SCL 6 SCL SM-LF
SM
5%
XW2801 P4MM 4
SM
SQW/ VBAT
P4MM 1/16W SM 3
XW2802
1
1 1 1 1
SM C2800 C2801 C2802 MF-LF C2803 6 PP_3V3ALLSMUAVCC 1
PP PP2801 NC 7
OUT GND
1
PP2800 PP
1 6 PP_3V3ALLSMU 10UF 0.1uF 0.1uF 402
1uF RTC_CLK32K_X2 28
10% 20% 20% 10%
6.3V 10V 10V 6.3V 4
2 2 2 2
Page Notes X5R
805
CERM
402
CERM
402
CERM
402
1
C2809
0.1uF
r
GND_SMU_AVSS 6 28 55 20%
10V
Power aliases required by this page: 2 CERM
SMU_BOOT_BUSY 402
- =PP3V3_ALL_SMU 6 29
Entry Desktop
Entry Desktop
MAKE_BASE=TRUE
- =PP3V3_ALL_RTC
Y = Primary function 13 SEE_TABLE 78 SMU_BOOT_SCLK 6 29
- =PP3V3_PWRON_SMU
Portable
Consumer
Portable
Consumer
Desktop
Desktop
N = Alternate function
VCC AVCC
Server
Server
- =PPVREF_SMU (SMU AVCC OR 2.5V REFERENCE) (see aliases below) SMU_BOOT_CE 6 29
S = Spare
U2800
Signal aliases required by this page: M30280F8-LF
a
QFP-80 RTS0*/
CPU_SENSE_I Y Y Y S S Y Y Y N N CPU_VID<0>
(NONE) 55
67 P0[0] AN00 CTS0* P6[0] 43 28 31
CPU_SENSE_V Y Y Y S S
P0[1] Y Y Y N N CPU_VID<1>
55 66 AN01 CLK0 P6[1] 42 28 31
BOM options provided by this page: Y Y Y S S Y Y Y N N
55 CPU_TEMP 65 P0[2] AN02 RXD0 P6[2] 41 CPU_VID<2> 28 31
(NONE) Y Y Y S S Y Y Y S S
29 CPU_BYPASS 64 P0[3] AN03 TXD0 P6[3] 40 CPU_VID<3> 28 31
N S Y Y Y RTS1* Y
NOTE: CPU current/voltage monitoring 31 SMU_FAN_RPM3 63 P0[4] AN04 (BUSY) P6[4] 31 Y Y S S CPU_VID<4> 28 31
SMU_FAN_RPM4 N S Y Y Y Y Y Y S S CPU_VID<5>
(CPU_SENSE_I/CPU_SENSE_V) requires 62 P0[5] P6[5] 30
100K/10uF RC filter at SMU pins.
31
31 SMU_FAN_RPM5 N S Y Y Y 61 P0[6]
AN05
AN06
CLK1
RXD1 P6[6] 29 Y Y Y Y Y SMU_BOOT_RXD
31
6 29
SMU Pull-ups / pull-down
n
Caps should connect to GND_SMU_AVSS. 31 SMU_SER_SEL Y Y Y Y Y 60 P0[7] AN07 TXD1 P6[7] 28 Y Y Y Y Y SMU_BOOT_TXD 6 29
SMU_VREF should be same signal or 29 28 7 6 =PP3V3_ALL_SMU R2800
Y Y Y Y Y Y Y Y Y Y
10K
reference used by monitoring P1[0] NOT USED ---> 4 SMU_PWRSEQ_P1_0 59 P1[0] AN20 SDA P7[0] 27 I2C_SMU_B_SDA 39 1 2 SYS_POWERUP_L 6 7 12 28 50 85
i
circuit, but be aware that this will 4 SMU_PWRSEQ_P1_1 Y Y Y Y Y 58 P1[1] AN21 SCL P7[1] 26 Y Y Y Y Y I2C_SMU_B_SCL 39 5%
1/16W
SMU_PWRSEQ_P1_2 Y Y Y Y Y Y Y Y N N I2C_SMU_CPU_SDA_IN
affect other analog inputs such as 4
57 P1[2] AN22 TA1out P7[2] 25 28 31 MF-LF
402
C AC adapter ID.
NOTE: All analog inputs to SMU should have
4
4
SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P1_4
Y
Y
Y
Y Y
Y Y
Y
Y
Y
56
55
P1[3]
P1[4]
AN23 TA1in
TA2out
P7[3] 24
P7[4] 23
Y
Y
Y
Y
Y
Y
Y
N
Y
N
SMU_FAN_RPM0
I2C_SMU_CPU_SCL_IN
32
28 31
R2801
10K
C
SYS_POWERFAIL_L N Y Y Y Y Y Y Y Y Y SMU_FAN_RPM1 SYS_RESET_BUTTON_L
7
54 P1[5] INT3* TA2in P7[5] 22 32 1 2 28 29
a 100pF capacitor to the SMU AVSS N S S S Y N S S Y Y
31 SMU_FAN_TACH9 53 P1[6] INT4* TA3out P7[6] 21 SB_CPU_VDNAP2 24 5%
signal (GND_SMU_AVSS). None of N S Y Y Y Y Y Y Y Y
1/16W
31 SYS_DOOR_AJAR_L 52 P1[7] INT5* TA3in P7[7] 20 SMU_FAN_RPM2 33 MF-LF
those capacitors are provided on 402
this page. Y Y Y Y Y Y Y Y Y Y R2802
31 SMU_FAN_TACH6 51 P2[0] SDAmm TA4out P8[0] 19 SYS_LED 29
Y Y Y Y Y Y Y Y Y Y
10K
NOTE: Some primary and alternate functions 31 SMU_FAN_TACH7 50 P2[1] SCLmm TA4in P8[1] 18 SYS_NORTH_RESET_L 28 30 1 2 SYS_POWER_BUTTON_L 6 28 29
SMU_FAN_TACH0 Y Y Y Y Y P2[2] Y Y Y Y Y SYS_PME_L
reuire pull-ups that are not. 32 49 IOC2 INT0* P8[2] 17 24 28 122 5%
m
1/16W
provided on this page. Please. 32 SMU_FAN_TACH1 Y Y Y Y Y 48 P2[3] IOC3 INT1* P8[3] 16 S S S S S SB_CPU_VDNAP0_OR_QREQ_OR_SPDIF 31 MF-LF
402
SMU_FAN_TACH2 Y Y Y Y Y Y Y Y Y Y SYS_SLEWING_L
review the latest SMU specification 33
47 P2[4] IOC4 INT2* P8[4] 15 24 26 28 50
SMU_FAN_TACH3 S N Y Y Y Y Y Y S S I2C_SMU_CPU_SDA_OUT_L
to ensure missing pull-ups are 31 46 P2[5] IOC5 NMI* P8[5] 14 28 31
=PP3V3_PWRON_SMU
43 30 7
R2804
il
SMU_FAN_TACH4 S N Y Y Y Y Y Y Y Y SYS_POWERUP_L
provided on another page. 31
45 P2[6] IOC6 CE* P8[6] 8 6 7 12 28 50 85
S N Y Y Y Y Y Y Y Y MAKE_BASE=TRUE 10K
31 SMU_FAN_TACH5 44 P2[7] IOC7 P8[7] 7 SMU_SLEEP 28 30 2 1 SYS_PME_L 24 28 122
NOTE: Pinout matches SMU pinout v1.51.
5%
1/16W
I2C_SMU_A_SDA_IN Y Y Y Y Y Y Y Y Y Y CLOCK_RESET_L
31 28
39 P3[0] CLK3 TB0in P9[0] 5 26 28 MF-LF
402
Y Y Y Y Y Y Y Y S S
31 28 I2C_SMU_A_SDA_OUT_L 38 P3[1] Sin3 TB1in P9[1] 4 SMU_FAN_TACH8 31
I2C_SMU_A_SCL_IN Y Y Y Y Y Y Y Y Y Y SB_TO_SMU_INT_L =PP3V3_RUN_SMU
31 28 37 P3[2] Sout3 TB2in P9[2] 3 24 30 20 7
R2812
I2C_SMU_A_SCL_OUT_L Y Y Y Y Y Y Y Y Y Y SB_STOPXTALS_L
31 28
36 P3[3] AN24 P9[3] 2 24
1
2.0K
2 SYS_SLEWING_L 24 26 28 50
I2C_SMU_E_SDA Y Y Y Y Y Y Y Y Y Y SMU_PWRSEQ_P9_5
39 35 P3[4] AN25 P9[5] 1 4
1%
I2C_SMU_E_SCL Y Y Y Y Y Y Y Y Y Y SMU_PWRSEQ_P9_6
39 34 P3[5] AN26 P9[6] 80 4 1/16W
MF-LF
DIAG_LED Y S S S S S S Y Y S SYS_SLOT_PWR
8
33 P3[6] AN27 P9[7] 79 31 402
e
93 24 20 SYS_OVERTEMP_L Y S S S S 32 P3[7]
NOSTUFF
S S S S S SB_CPU_VDNAP1 =PP2V5_PWRON_NB_MISC
AN0 P10[0] 76 24 39 30 20 7
R2811
AN1 P10[1] 74 Y Y Y Y Y SMU_IO_RESET_L 28 30 2.0K
55 =PPVREF_SMU DRIVEN PUSH/PULL 1 2 SMU_SUSPENDREQ_L 24 28 30 43
AN2 P10[2] 73 Y Y Y Y Y NB_SUSPENDACK_L 30
B B
r
1%
SMU_BOOT_CNVSS PCNVSS Y Y Y Y Y SB_SUSPENDACK_L
P4MM
SM
29 6 6 AN3 P10[3] 72 24 1/16W
MF-LF
29 6 SMU_RESET_L Y Y Y Y Y SMU_SUSPENDREQ_L
P4MM PP2804 PP
1 9 RESET* KI0* P10[4] 71 24 28 30 43 402
SM
Y Y Y Y Y
NOSTUFF
PP2805 PP
1 28 SMU_CLK10M_XOUT_R 10 XOUT KI1* P10[5] 70 SYS_POWER_BUTTON_L 6 28 29
R2813
28 SMU_CLK10M_XIN Y Y Y Y Y SYS_RESET_BUTTON_L
PP2806 PP
1 12 XIN KI2* P10[6] 69 28 29
1
10K
2 SYS_NORTH_RESET_L
Y Y Y S S PULLUP AT LEVEL SHIFTER P.30 28 30
SM 77 VREF KI3* P10[7] 68 I2C_SMU_CPU_SCL_OUT_L 28 31
5%
P4MM 1/16W
MF-LF
R2825 1
1 402
R2816 1
C2825 VSS AVSS R2827
10M 10K 1uF 11 75 10K R2810
1 2
P
5% 10% 5%
1/16W 6.3V 1/16W 100K
5% MF-LF 2 MF-LF 1 2 SMU_SLEEP 28 30
1
1/16W 402
2
CERM
402
XW2800 2
402
MF-LF 1%
R2817 402
SM
1/16W
470 1 2 MF-LF
5% 402
1/16W CRITICAL
MF-LF
402
2
Y2800 GND_SMU_AVSS 6 28 55
VOLTAGE=0V
10.0000M
1 2
MIN_LINE_WIDTH=0.38mm
Keep crystal subcircuit close to SMU.
28 SMU_CLK10M_XOUT 8X4.5MM-SM
MIN_NECK_WIDTH=0.2MM
Y2800’S LOAD CAPACITANCE IS 12PF
C2804 1 C2805 1
18PF 18PF
5% 5%
50V 50V
CERM 2 CERM 2
402 402
System Management Unit
System Management Unit
A Alternate Functions SYNC_MASTER=Q63 SYNC_DATE=08/26/2005
NOTICE OF PROPRIETARY PROPERTY
A
Tower & Server THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Port Port PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
31 28 CPU_VID<0> 6.0 SAT_MRESET_L 31 28 CPU_VID<3> 6.3 SMU_FAN_RPM6
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
31 28 CPU_VID<1> 6.1 CPU_A_INSERTED_L 31 28 CPU_VID<4> 6.4 SMU_FAN_RPM7
II NOT TO REPRODUCE OR COPY IT
31 28 CPU_VID<2> 6.2 CPU_B_INSERTED_L 31 28 I2C_SMU_A_SCL_IN 3.2 NB_TDI
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
31 28 I2C_SMU_CPU_SDA_IN 7.2 SMU_FAN_PWM8 31 28 I2C_SMU_A_SCL_OUT_L 3.3 NB_TCK
31 28 I2C_SMU_CPU_SCL_IN 7.4 SMU_FAN_PWM9 31 28 I2C_SMU_CPU_SDA_OUT_L 8.5 NB_TMS SIZE DRAWING NUMBER REV.
I2C_SMU_A_SDA_IN I2C_SMU_A_SDA I2C_SMU_CPU_SCL_OUT_L NB_TDO_SMU
31 28
31 28 I2C_SMU_A_SDA_OUT_L
3.0
3.1 I2C_SMU_A_SCL
31 39
31 39
31 28 10.7
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
LAST_MODIFIED=Tue Aug 30 18:05:17 2005 28 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AMBIENT LIGHT SENSOR CONNECTOR RTC BATTERY
NOSTUFF
CRITICAL R2900 ALWAYS ON (TRICKLE)
J2901 1
0 2
53398-0476 CRITICAL
F-ST-SM 5%
5
PP3V3_PWRON DS2900 1/16W
MF-LF
R2902 J2902
I6 SOD-123 402 BB10209-A5
1 =PP3V3_ALL_RTC PP3V3_ALL_RTC 2 1 PP3V3_ALL_BATT_SAFETY 1
1K 2 PP3V3_ALL_BATT 1 2
28
I2C_ALS_SDA 2 VOLTAGE=3.3V VOLTAGE=3.3V VOLTAGE=3.3V
39 MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM 5% MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM B0530WXF MIN_NECK_WIDTH=0.2MM 1/16W MIN_NECK_WIDTH=0.2MM TH
39
I2C_ALS_SCL 3 MAKE_BASE=TRUE MF-LF
D 4
402
D
y
6
I2C ADDR:72(1001000)
518S0328 CRITICAL
SYS LED’S LED2901 PP5V_PWRON
POWER BUTTON HEADER
r
CRITICAL 2 1
J2903 WHITE-500MCD
53398-0276 3X2MM-SM
M-ST-SM
3 SYS_LED_DRV_K
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
29 6
POWER_BUTTON_L 1
2 17_INCH_LCD
a
1
R2903
4
56.2
1%
1/16W
MF-LF
518S0327 2 402
SYS_LED_DRV_C
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
SYS POWER AND RESET BUTTON
n
3
R2913 Q2901
1K FDV301N
SYS_POWER_BUTTON_L POWER_BUTTON_L 6 29 SYS_LED 1 SOT23-LF
28 6 1 2 28
i
5% NOSTUFF
DEVELOPMENT 1/16W 2
1
R2912
MF-LF R2908
C 28
SYS_RESET_BUTTON_L 1 1K 2
402
RESET_BUTTON_L 6 5%
4.7K
1/16W
C
DEVELOPMENT MF-LF
5% 2 402
1/16W
MF-LF
SW2901 SW2902
402 SPST SPST
SM-LF SM-LF
1 2 1 2
1 C2905 1 C2904
0.1UF 0.1UF
20% 20%
10V 10V
2 CERM 2 CERM
402 402
m
3 4 3 4
RESET POWER
B
29 6
SMU RESET BUTTON
SMU_MANUAL_RESET_L
DEVELOPMENT
SW2900
1
SPST
SM-LF
2
29 28 7 6
=PP3V3_ALL_SMU
MMBD914XXG
SOT23
D2900
DEVELOPMENT
R2931
1
0 2
3
1
1
R2929
30K
5%
1/16W
MF-LF
2 402
SMU_RESET_L 6 28
e
DRIVE STRONG HRESET AND BYPASS TO CPU
il B
r
3 4 5%
1/16W
MF-LF
402
1 C2900
1UF 56 48 47 30 7
=PPV_EI_CPU
10%
2 6.3V
CERM
402
R2983
1
1K 2
5% CPU_HRESET_L 43
P
1/16W
MF-LF
402
6
SMU DEBUG/DOWNLOAD CONNECTOR D
Q2984
SAME CONNECTOR AS Q63 CPU CARD FOR SAT DEVELOPMENT
2N7002DW-X-F
J2904 CPU_HRESET 2 SOT-363
DEVELOPMENT SM12B-SRSS-TB-LF 31 G S
R2930
100 29 28 7 6
=PP3V3_ALL_SMU F-RT-SM
14
1
1 2
PCB: PLACE Q2984 NEAR CPU
1% 1
1/16W R2984
28 6
SMU_BOOT_BUSY MF-LF
402 SMU_BOOT_BUSY_R 2
FROM SMU 1
1K 2
28 6 SMU_BOOT_SCLK 3
5% CPU_BYPASS_L 43
28 6 SMU_BOOT_RXD 4 1/16W
MF-LF
28 6
SMU_BOOT_CE 5 402
3
NC_J2904_6 6
7
D
Q2984
SMU_MANUAL_RESET_L 8
2N7002DW-X-F
29 6
28 6
SMU_BOOT_CNVSS 9 28
CPU_BYPASS 5 G S
SOT-363
SMU SUPPLEMENTAL (2)
SMU_BOOT_TXD 10
A 28 6
6
NC_J2904_11 11
4
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
6
NC_J2904_12 12 TABLE_5_ITEM
114S0081 1 RES, 39.2 OHM, 1%, 402, LF R2903 20_INCH_LCD
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
13 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
NOSTUFF NOSTUFF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1 1 1
R2923 R2924 R2925 II NOT TO REPRODUCE OR COPY IT
10K 10K 0 DIGITAL GND THROUGHOUT
5% 5% 5% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
402 402 402 SIZE DRAWING NUMBER REV.
2 2 2
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 29 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMU TO NB SUSPEND_REQ NB SUSPEND_ACK_L LEVEL 2.5V TO 3.3V LEVEL SHIFTER
MISC. SMU BUFFERS 43 30 28 7 =PP3V3_PWRON_SMU
SAME AS Q63
SAME AS (Q63). 1
R3091 1
R3093
=PP3V3_PWRON_SMU 1K 1K
43 30 28 7 5% 5%
=PP2V5_PWRON_NB_MISC =PP3V3_PWRON_SMU 1/16W
MF-LF 1/16W
7 20 28 30 39 7 28 30 43
MF-LF
2 402 2 402
1
R3000 NB_SUSPENDACK NB_SUSPENDACK_L
1 NB_SUSPEND_ACK_L_R 28
1K 1
R3001 R3021 3 6
5%
1/16W 100 4.7K
U700 IS POWERED BY PP3V3_ALL R3090
MF-LF 5% 5% 10K D
Q3021
2 402 1/16W
MF-LF
1/16W
MF-LF U700 62 20 NB_SUSPEND_ACK_L 2 1 1 Q3090 2N7002DW-X-F
1
R3003 5% 2N3904LF
2 402 2 402 14 74LC125 R3022 1/16W SOT23 2 G S
SOT-363
D 5%
4.7K
1/16W
PMU_SUSPEND_REQ
NB_SUSPEND_REQ_L
28 SMU_IO_RESET_L 9 8 30 SYS_IO_RST_L_R
125
2
100 1 SYS_IO_RESET_L 24 28 119 122
MF-LF
402
2
NOSTUFF 1
D
MF-LF 20 5%
2 402 7 10TSSOP 1/16W R3092
y
MF-LF 0
6
402 2 1
6 U700 5%
D
Q3005 D Q3000 14 74LC125 R3023 1/16W
MF-LF
2N7002DW-X-F 5 6 SYS_SLEEP_R 2 100 402
SMU_SUSPENDREQ_L 2 SOT-363 2N7002DW-X-F 28 SMU_SLEEP 1 SYS_SLEEP 11 12 13 15 16 26 30 54
43 28 24 G S SOT-363
2 125
r
G S 5%
7 4 TSSOP 1/16W
1
1
MF-LF
402
LEVEL SHIFT SMU TMS TO CPU (BACKUP PLAN)
56 48 47 30 29 7 =PPV_EI_CPU
NOSTUFF NOSTUFF
=PP3V3_PWRON_SMU
R3002 R3099 SMU JTAG TCK TO CPU (BACKUP PLAN)
43 30 28 7
1
0 0 1 R3027
1 2 SMU_SUSPENDREQ_L_R 1 2 =PPV_EI_CPU 7 29 30 47 48 56 R3026 1K
a
5% 5% 1K 5%
1 5%
1/16W
MF-LF
1/16W
MF-LF R3081 1/16W 1/16W
MF-LF
402
39 30 28 20 7 =PP2V5_PWRON_NB_MISC 402 1K
STUFF IF USING REGISTERED DIMM
MF-LF
2 402 2 402 R3028
5%
1/16W JTAG_CPU_TMS_2_L
33
JTAG_CPU_TMS_2_R 2 1 JTAG_CPU_TMS
=PP3V3_RUN_SMU
MF-LF
2 402
R3082 =PP3V3_PWRON_SMU 5%
9 43
R3038 30 28 20 7
JTAG_CPU_TCK_2_R 2
33 1 JTAG_CPU_TCK NOSTUFF
7 28 30 43
JTAG_SMU_TMS_2_R
3
3 1/16W
10K JTAG_NB_TDO 9 20 30 1 9 43
1 R3020 MF-LF
SYS_NORTH_RESET FROM SMU TO NB_PU_RST 2 1 R3080 5% R3040 10K
D Q3031 402
5% 4.7K 3 1/16W 1K SMU_CPU_TMS 2 1 1 Q3030 2N7002DW-X-F
SAME AS Q63 1/16W 5% MF-LF 5% 30
SOT-363
Q3081 402 2N3904LF
n
MF-LF 1/16W D 1/16W 5% 5 G S
=PP3V3_PWRON_SMU 402 MF-LF
2N7002DW-X-F MF-LF 1/16W SOT23
43 30 28 7
2 402 SOT-363 2 402 MF-LF 2
5 G S SMU_IO_RESET 67 402 4
=PP2V5_PWRON_NB_MISC 7 20 28 30 39
SMU_JTAG_TCK_L
i
3 4 3
1 NOSTUFF
R3006 1
D
D
Q3040
10K
C 5%
1/16W
MF-LF
R3007
5%
4.7K 31 30 SMU_JTAG_TCK 5 G S
30 SYS_IO_RST_L_R 1 G S
2N7002
SOT23-LF
C
2 402 1/16W
1
R3010
MF-LF
2 402
Q3080 4
2 LEFTOVER FROM UNUSED PRIMARY PLAN - NOT STUFFED
2N7002DW-X-F
4.7K NB_PU_RESET SOT-363 NOSTUFF
5%
1/16W U5640
8 SN74AUC2G125
MF-LF NB_PU_RST_L 20 VSSOP
2 402 VCC
2 6
3
3
A
125 Y
Q3005
m
D GND
2N7002DW-X-F
D
Q3000 4
1
SYS_NORTH_RESET_L 5
SOT-363 2N7002DW-X-F SHARE SMU JTAG TCK WITH CPU AND NB (PRIMARY PLAN)
28 G S SOT-363
5 G S
SHARE SMU JTAG TDI WITH CPU AND NB (PRIMARY PLAN)
il
4
4 NOTE: WE WENT WITH BACKUP PLAN, PRIMARY REMOVED
NOSTUFF NOSTUFF TO AVOID STUBS
R3008 R3098
1
0 2 1
0 2
SYS_NORTH_RESET_L_R
5% 5% 3 NOSTUFF
1/16W NOSTUFF 1/16W
MF-LF MF-LF D
Q3006 SMU_JTAG_TDI SMU_JTAG_TCK
402
R3009 402
2N7002
31 30
NB JTAG IS A DEVELOPMENT ONLY FEATURE
31 30
SYS_SLEEP 1
0 2
SYS_2SLEEP_R 1 G S
SOT23-LF PLACE O-OHM R3030 AND R3031 TO AVOID STUBS
54 30 26 16 15 13 12 11 DEVELOPMENT
1
5%
R3030
e
1/16W 2 DEVELOPMENT
MF-LF 0 1
402 CONSIDER COMBINING Q3040 AND Q3006 TO A DUAL PART 5%
1/16W R3031
MF-LF 0
SHARE CPU AND NB JTAG TDO WITH SMU 2 402 5%
1/16W
SMU JTAG TDI TO CPU =PPV_EI_CPU
(BACKUP PLAN) PCB: PLACE U3030 AND U3031 NEAR CPU AND KODIAK. MF-LF
2 402
B =PP3V3_PWRON_SMU PCB: PLACE 33 OHM RES NEAR U3030/31 PART.
B
r
7 29 30 47 48 56
43 30 28 7
PCB: PLACE U3070 NEAR SMU
1 =PP2V5_PWRON_NB_MISC =PP2V5_PWRON_NB_MISC
SMU DRIVES 3.3V PUSH-PULL ON CRITICAL R3084 28 20 7
39 30
39 30 28 20 7
ALL JTAG-RELATED PINS 1K
U3070 5%
1/16W DEVELOPMENT
SN74LVC2G157 1 SMU_JTAG_NB_TCK
8 TSSOP 30 28 20 7 =PP3V3_RUN_SMU
MF-LF
2 402
R3085 C3031 1 R3034 1
R3035 PULLUP
2
33 1 JTAG_CPU_TDI 9 43 0.1UF 10K 10K IF
VCC 1
JTAG_CPU_TDI_2_R 20% 5% 5% KODIAK JTAG IS NOSTUFFED
30 JTAG_CPU_TDO_3V3 1 A R3083 5%
10V
CERM 2 VCC RANGE 0.8V - 2.7V 1/16W
MF-LF VCC RANGE 0.8V - 2.7V 1/16W
MF-LF
JTAG_NB_TDO 2 B Y5 SMU_JTAG_TDO31 4.7K 6 1/16W 402 2 402 DEVELOPMENT
30 20 9
5% MF-LF DEVELOPMENT 2 402
D
Q3081 402 U3031
P
1/16W
VIH=2V MF-LF
2N7002DW-X-F 5
U3031 DEVELOPMENT VIH = 2.0V, 3.3V TOLERANT 5 DEVELOPMENT
31 30 SMU_CPU_NB_SEL 6 A*/B Y* 3 NC_JTAGMUX_3 9 2 402 SOT-363
SN74AUC2G34
SOT23-6 R3032 SN74AUC2G34
SOT23-6 R3033
2 G S VCC VCC
7 EN* SMU_JTAG_TDI_L
SMU_JTAG_NB_TDI 1 6 JTAG_NB_TDI_R 2
33 1 JTAG_NB_TDI 9 20 3 4 JTAG_NB_TCK_R 2
33 1 JTAG_NB_TCK 9 20
C3070 1 GND 6 1
A
34 Y
5%
A
34 Y
5%
0.1UF 4 VIH = 2.0V, 3.3V TOLERANT GND 1/16W GND 1/16W
D MF-LF MF-LF
20%
10V 2 402 2 402
CERM 2
402 31 30 SMU_JTAG_TDI 2 G S
Q3080 1
2N7002DW-X-F
SHARE CPU AND NB JTAG TMS WITH SMU SOT-363
PULLDOWNS TO BUFFERS/LOGIC GATES
=PP2V5_PWRON_NB_MISC R3036
39 30 28 20 7
PCB: PLACE U3071 NEAR SMU OR NEAR KODIAK.
LEVEL SHIFT TDO FROM CPU TO MUX 31 30 SMU_JTAG_TDI 1
100K 2
=PP3V3_PWRON_SMU 5%
C3071 1 43 30 28 7 1/16W
MF-LF
0.1UF 402
20% CRITICAL
10V
CERM 2 5 1
1
R3052 R3037 SMU SUPPLEMENTAL (3)
402 R3051 100 SMU_JTAG_TCK 100K 2
VCC 5% 31 30 1
U3071 1K
A 74LVC1G
SC70-6 TO LEVEL SHIFTER
5%
1/16W
MF-LF
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
1 A 402
SMU_CPU_TMS 2 402 JTAG_CPU_TDO_3V3
Y0 6 30 JTAG_CPU_TDO_L 30
R3070 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
100K 2
JTAG_CPU_TDO_R 3 31 30 SMU_JTAG_TMS 1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
3
3.3V TOLERANT R3050 D Q3021
5%
1/16W I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
JTAG_CPU_TDO 10K MF-LF
STRAIGHT TO NB 47 43 9 2 1 1 Q3050 2N7002DW-X-F
SOT-363
402 II NOT TO REPRODUCE OR COPY IT
Y1 4 JTAG_NB_TMS 9 20 5% 2N3904LF 5 G S R3071 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
31 30 SMU_JTAG_TMS 3 1/16W SOT23
100K 2
MF-LF 2 SMU_CPU_NB_SEL 1 SIZE DRAWING NUMBER REV.
E* GND 402 4 31 30
2 5%
1/16W
MF-LF
D 051-6863 19
402 APPLE COMPUTER INC.
SCALE SHT OF
PCB: PLACE R3050, Q3050, R3051 NEAR CPU. PLACE Q3021, R3052 NEAR SMU. NONE 30 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMU ALIASES
ALIASES ARE ONLY NECESSARY WHERE USE DIFFERS FROM Q63.
DS3100
SOD-123
2 1
PP3V3_RUN
MIN_NECK_WIDTH=0.2MM
PP3V3_CPU_VID_D MIN_LINE_WIDTH=0.6MM
COMMENT (ONLY IF USE DIFFERS FROM Q63) M23 NET NAME M23 SMU ALLOCATION Q63 NET NAME (SHARED PAGE) B0530WXF
CPU VID<0:5> 1
CPU_SENSE_I0 P0.0 R3114 1R3116 1R3117 1R3108 1R3109 1
R3104
CPU_SENSE_V0 P0.1 VID CONTROLLED BY SMU 1K 1K 1K 1K 1K 1K
Q63 NC’S THESE AS IT USES A SAT. 5% 5% 5% 5% 5% 5%
CPU_TEMP0 P0.2 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
CPU_BYPASS P0.3 2 402 2 402 2 402 2 402 2 402 2 402
9 NC_SMU_FAN_RPM3 FAN_CNTL0_4 P0.4 SMU_FAN_RPM3 28
R3119
MAKE_BASE=TRUE 0
M23/M33 DOESN’T HAVE THOSE FANS. 9 NC_SMU_FAN_RPM4 FAN_CNTL0_5 P0.5 SMU_FAN_RPM4 28 28 CPU_VID<0> 1 2 CPU_VID_R<0> 50
D 9 NC_SMU_FAN_RPM5 FAN_CNTL0_6
MAKE_BASE=TRUE
P0.6
MAKE_BASE=TRUE
SMU_FAN_RPM5 28
MAKE_BASE=TRUE
5%
1/16W R3120 D
Q63 USES SMU_SER_SEL FOR SPDIF-SMU-DEBUG. NOT M23/M33 FEATURE. 9 NC_SMU_SER_SEL SMU_SCCL_SEL P0.7 SMU_SER_SEL 28 MF-LF 0
MAKE_BASE=TRUE 28 CPU_VID<1> 402 1 2 CPU_VID_R<1> 50
y
M23/M33 DOESN’T USE. P1.0 NC ON PG 7. CPU_SENSE_I1 P1.0 MAKE_BASE=TRUE
CPU_SENSE_V1 P1.1 R3121 5%
1/16W
CPU_VID<2> 1
0 2
MF-LF
402 CPU_VID_R<2>
SMU USES P1.1, P1.2, P1.3, P9.5, P9.6 FOR PWRSEQ ON PG 7. CPU_TEMP1 P1.2 28 50
MAKE_BASE=TRUE
PS1_3 P1.3 5%
1/16W R3122
M23/M33 DOESN’T USE P1.4. NC ON PG 7. PS1_4 P1.4
CPU_VID<3>
MF-LF 0 CPU_VID_R<3>
r
28 402 1 2 50
POWERFAIL* P1.5 MAKE_BASE=TRUE
CPU_VID_LE0 FOR Q82. NOT M23/M33 FEATURE. 9 NC_SMU_CPU_VID_LE0 CPU_VID_LE0 P1.6 SMU_FAN_TACH9 28
R3123 5%
1/16W
MAKE_BASE=TRUE 0 MF-LF
CONSIDER DOOR_AJAR FOR M23/M33 DIMM ACCESS DOOR? 9 NC_SYS_DOOR_AJAR_L DOOR_AJAR* P1.7 SYS_DOOR_AJAR_L 28 28 CPU_VID<4> 1 2 402 CPU_VID_R<4> 50
MAKE_BASE=TRUE MAKE_BASE=TRUE
CPU_VID_LE1 FOR Q82. NOT M23/M33 FEATURE. 9 NC_SMU_CPU_VID_LE1 CPU_VID_LE1 P2.0 SMU_FAN_TACH6 28 5%
R3124
MAKE_BASE=TRUE 1/16W
M23/M33 DOESN’T HAVE THIS FAN. 9 NC_SMU_FAN_TACH7 FAN_TACH2_1 P2.1 SMU_FAN_TACH7 28 MF-LF 0
MAKE_BASE=TRUE 28 CPU_VID<5> 402 1 2 CPU_VID_R<5> 50
FAN_TACH2_2 P2.2 MAKE_BASE=TRUE
5%
NC_J3108_10 9
NC_J3108_11 9
NC_J3108_12 9
FAN_TACH2_3 P2.3 1/16W
NC_J3108_8 9
NC_J3108_9 9
a
MF-LF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
FAN_TACH2_4 P2.4 402
1
R3132 1R3131 1R3130 1R3129 1R3127 1R3111
BM12B-SRSS-TB
M23/M33 DOESN’T HAVE FAN TACHS P2.5, P2.6, P2.7. 9 NC_SMU_FAN_TACH3 FAN_TACH2_5 P2.5 SMU_FAN_TACH3 28
MAKE_BASE=TRUE 1K 1K 1K 1K 1K 2.0K
M23/M33 USES TACH0 (P2.2), TACH1 (P2.3), TACH2 (P2.4) ONLY. 9 NC_SMU_FAN_TACH4 FAN_TACH2_6 P2.6 SMU_FAN_TACH4 28 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
J3108
MAKE_BASE=TRUE
NOSTUFF
9 NC_SMU_FAN_TACH5 SMU_FAN_TACH5
14
10
11
12
13
FAN_TACH2_7 P2.7 MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
F-ST-SM
28
1
2
3
4
5
6
7
8
9
39 28 I2C_SMU_A_SDA IIC_A_DAT
MAKE_BASE=TRUE
P3.0 I2C_SMU_A_SDA_IN 28
2 402 2 402 2 402 2 402 2 402 2 402
M23/M33 ONLY CONNECTS I2C TO KODIAK NOW; CPU HAS PULLUPS ON ITS PG. MAKE_BASE=TRUE
39 28 I2C_SMU_A_SCL IIC_A_CLK P3.1 I2C_SMU_A_SDA_OUT_L 28
MAKE_BASE=TRUE
30 SMU_JTAG_TDI TDI P3.2 I2C_SMU_A_SCL_IN 28
n
MAKE_BASE=TRUE
30 SMU_JTAG_TCK TCK P3.3 I2C_SMU_A_SCL_OUT_L 28 NOTE:PULL UP CPU_VID<5>TO
MAKE_BASE=TRUE
IIC_E_DAT P3.4 2.2V FOR CPU VRM10.
IIC_E_CLK P3.5
i
DIAG_LED P3.6 NOTE: SC2642 VID PINS HAVE LEAKAGE TO GND.
OVERTEMP* P3.7 SO PULLUPS MUST BE 1K
C CPU_VID[0]
CPU_VID[1]
P6.0
P6.1
C
CPU_VID[2] P6.2
CPU_VID[3] P6.3
CPU_VID[4] P6.4
CPU_VID[5] P6.5
DEBUG_RXD P6.6
DEBUG_TXD P6.7
IIC_B_DAT P7.0
m
IIC_B_CLK P7.1
Q63 USE OF P7.2 IS PWM FAN SELECT BETWEEN CPU OR NB TMS AND TDO FROM/TO SMU 30 SMU_CPU_NB_SEL CPU_TMS P7.2 I2C_SMU_CPU_SDA_IN 28
MAKE_BASE=TRUE
FAN_CNTL7_3 P7.3
NC_I2C_SMU_CPU_SCL_IN I2C_SMU_CPU_SCL_IN
il
M23/M33 DOESN’T HAVE THIS FAN (P7.4) 9 FAN_CNTL7_4 P7.4 28
MAKE_BASE=TRUE
M23/M33 USES FAN_RPM0 (P7.3), FAN_RPM1 (P7.5), FAN_RPM2 (P7.7) ONLY. FAN_CNTL7_5 P7.5
VDNAP2 P7.6
FAN_CNTL7_7 P7.7
SYSTEM_LED P8.0
NB_RESET* P8.1
PME* P8.2
M23/M33 DOESN’T NEED TO MAKE VDNAP0 DO TRIPLE-DUTY. 24 SB_VDNAP0 VDNAP0 P8.3 SB_CPU_VDNAP0_OR_QREQ_OR_SPDIF 28
MAKE_BASE=TRUE
SLEWING* P8.4
30 SMU_JTAG_TMS NB_TMS P8.5 I2C_SMU_CPU_SDA_OUT_L 28
MAKE_BASE=TRUE
e
POWERUP* P8.6
SLEEP P8.7
CLK_RESET* P9.0
Q63 USE OF P9.1 IS TACH 8. 29 CPU_HRESET CPU_HRESET P9.1 SMU_FAN_TACH8 28
MAKE_BASE=TRUE
SMU_DOORBELL* P9.2
B B
r
STOP_XTAL* P9.3
PS9_5 P9.5
SMU USES P1.1, P1.2, P1.3, P9.5, P9.6 FOR PWRSEQ ON PG 7.
PS9_6 P9.6
M23/M33 HAS NO SLOTS. 9 NC_SLOT_TOTAL_PWR SLOT_TOTAL_PWR P9.7 SYS_SLOT_PWR 28
MAKE_BASE=TRUE
VDNAP1 P10.0
IO_RESET* P10.1
SUSPEND_ACK* P10.2
P
SUSPEND_IO_ACK* P10.3
SUSPEND_REQ* P10.4
PWR_BUTTON* P10.5
RST_BUTTON* P10.6
30 SMU_JTAG_TDO TDO P10.7 I2C_SMU_CPU_SCL_OUT_L 28
MAKE_BASE=TRUE
SMU SUPPLEMENTAL (4)
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 31 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP12V_RUN
FAN 0
1 NOSTUFF
R3205 R32071 1 C3202
1
R3202 1.5K 1.5K 0.1UF
5% 5%
1.0K 1/4W 1/8W 20%
5% MF-LF MF-LF 2 25V
CERM 5
1/8W 2 1206 805 2
D MF-LF
2 805 R3206
603
CRITICAL
M23: ODD FAN D
F0_VOLTAGE8R5
3.9K F0_GATESLOWDN 1206A-03-LF
M33: ODD FAN
y
F0_DRV 4
5% NTHS5443T1
1/8W
MF-LF Q3203
805
6
D
Q3201 CRITICAL
C3204
1
2
3
6
7
8
2N7002DW-X-F 1
r
2 SOT-363 0.47UF
J3200
28 SMU_FAN_RPM0 G S
10% 53261-0498
M-RT-SM
3 2 16V
X7R NOSTUFF 5
1
D Q3201 805
R3208 D3203
SMB
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
2N7002DW-X-F
SOT-363 F0_RCFEEDBK 1
0 2 FAN_0_OUT 1 2 FAN_0_PWR 1
5 MOTOR CONTROL
G S MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM NOSTUFF 5% MIN_LINE_WIDTH=0.5MM 2 TACH
1 1/8W B130LBT01XF
R3215 MF-LF 3 GND
a
4
805 3
PP3V3_RUN 1.0K
5% D3202 R3216 1
C3203 4 12V DC
1/8W MMBD914XXG 0 1 2
120UF
MF-LF 20%
2 805 1 SOT23 2 16V 6
5% ELEC
1/8W 6.3X11-TH-LF
1
R3210
10K
MF-LF
805
518S0193
5%
1/16W
MF-LF
n
2 402
28 SMU_FAN_TACH0
i
C C
m
PP12V_RUN
FAN 1
il
1
R3252
1.0K 1
R3255 NOSTUFF
5%
1/8W
MF-LF 5%
1.5K R32571 1 C3252
2 805 1/4W 1.5K 20%
0.1UF
MF-LF 5% 25V
2 1206 1/8W
MF-LF
2 CERM
805 2 603 5
R3256
e
F1_DRV
CRITICAL
3.9K
F1_VOLTAGE8R5 F1_GATESLOWDN 4 1206A-03-LF M23: HD FAN
5% NTHS5443T1
6 1/8W
MF-LF Q3253 M33: CPU FAN
D
Q3251 805 CRITICAL
B B
r
2N7002DW-X-F
SOT-363
1 C3254 J3201
28 SMU_FAN_RPM1 2 G S 0.47UF NOSTUFF 53261-0598
1
2
3
6
7
8
10% M-RT-SM
3 2 16V 6
1
X7R
805 R3258 D3253 MIN_LINE_WIDTH=0.5MM
D
Q3251 0 SMB
1 2
MIN_NECK_WIDTH=0.25MM
2N7002DW-X-F F1_RCFEEDBK 1 2 FAN_1_OUT FAN_1_PWR 1 MOTOR CONTROL
5 SOT-363 MIN_LINE_WIDTH=0.5MM MIN_LINE_WIDTH=0.5MM 2
G S MIN_NECK_WIDTH=0.25MM NOSTUFF 5% MIN_NECK_WIDTH=0.25MM TACH
1 1/8W B130LBT01XF
4
R3265 MF-LF
805
3 GND
1.0K 3 4 12V DC
5% R3266 1
C3253
P
1/8W
MF-LF
D3252
MMBD914XXG 0 120UF
5
PP3V3_RUN 1 2 20%
2 805 1 SOT23 2 16V
5% ELEC 7
1/8W 6.3X11-TH-LF
MF-LF
805
518S0326
1
R3259
10K
5%
1/16W
MF-LF
2 402
28 SMU_FAN_TACH1
Fan 0, 1 & System Temp
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 32 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FAN 2
PP12V_RUN
D D
y
1
R3302 1
R3305 R33071
NOSTUFF
1.0K
5% 1.5K 1.5K
1 C3302
1/8W 5% 5% 0.1UF
MF-LF 1/4W 1/8W 20%
25V
2 805 MF-LF MF-LF 2 CERM
r
2 1206 805 2 603 5
F2_DRV
R3306
F2_VOLTAGE8R5
3.9K F2_GATESLOWDN
M23: CPU FAN
1206A-03-LF
6
5%
4
NTHS5443T1 M33: HD FAN
D Q3301 1/8W
MF-LF
Q3303
2N7002DW-X-F 805 CRITICAL
SOT-363
SMU_FAN_RPM2 2 G S J3300
a
28
1 C3304 NOSTUFF 53398-0476
0.47UF
1
2
3
6
7
8
3 F-ST-SM
1 10% 5
D Q3301 16V
2 X7R R3308 D3303
SMB
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
2N7002DW-X-F 805 0 1 2 1
SOT-363 MIN_LINE_WIDTH=0.5MM F2_RCFEEDBK 1 2 FAN_2_OUT FAN_2_PWR MOTOR CONTROL
5 G S MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.5MM
NOSTUFF 5% MIN_NECK_WIDTH=0.25MM 2 TACH
1/8W B130LBT01XF
1 3
4 R3315 MF-LF
805
3
1
C3303
GND
PP3V3_RUN 1.0K D3302 120UF
4 12V DC
n
5%
1/8W
MMBD914XXG
SOT23 R3316 20%
MF-LF 1
1
0 2
2 16V
ELEC 6
2 805 6.3X11-TH-LF
5%
1
R3309 1/8W
i
MF-LF 518S0328
10K 805
5%
1/16W
C 28 SMU_FAN_TACH2
MF-LF
2 402 C
HD TEMP SENSOR
il m ODD TEMP SENSOR
I2C ADDR:0X92(1001001)
39
39
r e
I2C_HD_TEMP_SDA
I2C_HD_TEMP_SCL
PP3V3_RUN
CRITICAL
J3301
53261-0498
M-RT-SM
5
1
2
3
NOTE: BROKE SYNC ON THIS PAGE
TO ALLOW EMC CAPS ON M23 ONLY
I2C ADDR:0X90(1001000)
39 I2C_ODD_TEMP_SDA
PP3V3_RUN
CRITICAL
J3302
53261-0498
M-RT-SM
5
1
2
B
P
4 39 I2C_ODD_TEMP_SCL 3
4
6
6
518S0193
518S0193
Fan 2 & HD Temp
A SYNC_MASTER=M33-HS
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/04/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 33 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V3_PWRON
SMU AND NB I2C A BUS
SMU I2C B BUS
39 7 =PP3V3_RUN_I2C =PP2V5_RUN_I2C 7 39
SB I2C BUS PP3V3_RUN
R39031 1
R3902
2.0K 2.0K
5% 5%
1
R3953
1
R3969
1
R3958
1
R3959 SMU 1/16W
MF-LF
1/16W
MF-LF
1 1
5%
2.0K
5%
2.0K
5%
2.0K
5%
2.0K
SHASTA R3915 R3914 MASTER 402 2 2 402
SMU 1/16W 1/16W 1/16W 1/16W KODIAK 1K 1K U1300
MF-LF MF-LF MF-LF MF-LF MASTER 5% 5%
MASTER 2 402 2 402 2 402 2 402 1/16W 1/16W
D U2300 MF-LF
402 2
MF-LF
2 402 28 I2C_SMU_B_SDA
MAKE_BASE=TRUE
NET_SPACING_TYPE=I2C
D
28 I2C_SMU_A_SDA I2C_NB_A_SDA 20 NET_SPACING_TYPE=AUDIO NET_SPACING_TYPE=I2C
31 NET_SPACING_TYPE=I2C NET_SPACING_TYPE=I2C 24 I2C_SB_SDA 28 I2C_SMU_B_SCL
y
MAKE_BASE=TRUE MAKE_BASE=TRUE
NET_SPACING_TYPE=AUDIO
24 I2C_SB_SCL PINS 26, 27
MAKE_BASE=TRUE
VDIV=2.9V PINS Y9, AB7
28 I2C_SMU_A_SCL I2C_NB_A_SCL 20
r
31 NET_SPACING_TYPE=I2C NET_SPACING_TYPE=I2C
NOSTUFF
PULSAR2
1
R3955 AUDIO U2600
15K 26 I2C_CLOCK_B_SDA
NOSTUFF 5% U9500 / AU300
1/16W
1
R3954 MF-LF
402 R3904
15K 2 33
5% 147 I2C_AUDIO_SDA 26 I2C_CLOCK_B_SCL 1 2
1/16W NET_SPACING_TYPE=I2C
I2C_AUDIO_SCL 5%
a
MF-LF 147
402 1/16W
2 3 D S 2
I2C ADDR:0XD5 MF-LF
PINS 18, 19 402
Q3902
G SI2302ADSE3
SOT23-3
1
R3962
Q3902_1 1
0
2 =PP2V5_RUN_I2C
ALS HEADER
7 39
n
J2901
5%
1/16W 29 I2C_ALS_SDA
MF-LF
SMU I2C E BUS D S
402
R3908
33
i
3 2 I2C_ALS_SCL 1 2
29
NET_SPACING_TYPE=I2C
5%
PP3V3_ALL 1/16W
Q3901
C G SI2302ADSE3
SOT23-3
I2C ADDR:52 MF-LF
402 C
1
R3963
0
Q3901_1 1 2
R39071 1
R3906 5%
2.0K
5%
1/16W
2.0K
5%
1/16W
1/16W
MF-LF
402
NB I2C C BUS
MF-LF MF-LF
402 2 2 402 ODD TEMP SENSOR HEADER
m
J3302
R3965 I2C_ODD_TEMP_SDA 33
0 39 7 =PP2V5_RUN_I2C 39 7 =PP3V3_RUN_I2C
R3976
il
2 1
SMU ’E’ 5% RTC 1
33
2 I2C_ODD_TEMP_SCL 33
MASTER 1/16W
R3970 1 R3971 1 NET_SPACING_TYPE=I2C
U2800
MF-LF
402 U2801 2.0K 2.0K R3972 1 R3973 1 5%
1/16W I2C ADDR:90
5% 5% 2.0K 2.0K MF-LF
1/16W 1/16W 5% 5% 402
I2C_SMU_E_SDA
KODIAK I2C C MF-LF MF-LF 1/16W 1/16W
28 I2C R3964 I2C I2C_RTC_SDA 28
402 2 402 2 MF-LF
402 2
MF-LF
402 2 HD TEMP SENSOR HEADER
I2C_SMU_E_SCL 2
0 1 I2C_RTC_SCL
28 I2C I2C 28
J3301
5%
PINS 34,35 1/16W
MF-LF PINS 5, 6 I2C_HD_TEMP_SDA 33
402
R3977
e
20 I2C_NB_C_SDA 33
1 2 I2C_HD_TEMP_SCL 33
NET_SPACING_TYPE=I2C MAKE_BASE=TRUE I2C_NB_C_3V3_SDA NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C 5%
1/16W
MF-LF
I2C ADDR:92
402
B
NB I2C B BUS B
r
59 58 20 7 =PP1V8_PWRON_NBMEM GPU TEMP SENSOR
20 I2C_NB_C_SCL MAKE_BASE=TRUE I2C_NB_C_3V3_SCL U9390
NET_SPACING_TYPE=I2C
30 28 20 7 =PP2V5_PWRON_NB_MISC NET_SPACING_TYPE=I2C
Q3970 I2C_GPU_DIODE_SDA 93
R3924 SI2302ADSE3 R3978
0 SOT23-3 33
Q3903_G 1 2 1 2 I2C_GPU_DIODE_SCL 93
1
R3925 NET_SPACING_TYPE=I2C
5% 5%
2.0K 1/16W 2 S D 3 1/16W I2C ADDR:9C
P
5% MF-LF MF-LF
KODIAK I2C B 1/16W
MF-LF
402
R3931 1 402
2
402 Q3903 2.0K
MASTER 1 5% G
U1900
SI2302ADSE3
SOT23-3
1/16W
MF-LF
DDR2 DIMMS KODIAK TEMP SENSOR
G 402 2
1
R3974 U2080
3 D S 2
0 I2C_NB_TEMP_SDA 20
20 I2C_NB_B_SDA I2C_NB_RAM_SDA 67 Q3970_G 1 2
NET_SPACING_TYPE=I2C NET_SPACING_TYPE=I2C 5%
R3979
1/16W
R3937 MF-LF 33
0 402 1 2 I2C_NB_TEMP_SCL 20
Q3904_G 1 2 NET_SPACING_TYPE=I2C
5%
1 5% 2 S D 3 1/16W I2C ADDR:98
R3936 1/16W MF-LF
2.0K MF-LF 402
402
5%
1/16W Q3971
1
MF-LF
402 Q3904 R3938 SI2302ADSE3 G
2 2.0K SOT23-3
1 1
SI2302ADSE3 5%
R3975
SOT23-3 1/16W
G MF-LF 0
3 D S 2
402 2 Q3971_G 1
5%
2 =PP2V5_RUN_I2C 7 39
I2C Connections
20 I2C_NB_B_SCL I2C_NB_RAM_SCL 67 1/16W
A NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C MF-LF
402
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
PINS AG04, AK03
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 39 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Q63 APPLICATION IS PP1V5 PWRON
Q63 APPLICATION IS PP1V5 PWRON
56 42 41 7
=PPV_EI_NB
=PPV_EI_NB 7 41 42 56
1 1 1 1 1 1 1 1 1 1
C4168 C4146 C4143 C4139 C4137 C4113 C4112 C4106 C4122 C4100
0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
NO_TEST=YES
SM
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
XW4100 P4MM 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
SM
PP_VEINB 402 402 402 402 402 402 402 402 402 402
1
AB01 GND_0 VD2_0 AB02 6 1
PP PP4100
AB04 GND_1 VD2_1 AB05
D AB07
AB10
GND_2 VD2_2 AB08
AB11
D
GND_3 VD2_3 1 1 1 1 1 1 1 1 1 1
C4169 C4147 C4145 C4140 C4138 C4114 C4110 C4107 C4133 C4111
y
AB12 GND_4 VD2_4 AB13
U1900 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
AD02 AD01 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
GND_5 BGA VD2_5 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
AD05 AD04 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
GND_6 VD2_6 402 402 402 402 402 402 402 402 402 402
AD08
(7 OF 10) AD07
GND_7 PWR/GND VD2_7
AD11 AD10
GND_8 VD2_8
r
PART 0
AD13 GND_9 VD2_9 AD12
AD17 GND_10 VD2_10 AD16 1
C4170 1
C4149 1
C4148 1
C4142 1
C4141 1
C4115 1
C4109 1
C4108 1
C4155 1
C4144
AD21 GND_11 VD2_11 AD20 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
AE15 AE14 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
GND_12 VD2_12 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
AE19 AE18 402 402 402 402 402 402 402 402 402 402
GND_13 VD2_13
AF07 AF08
GND_14 VD2_14
AF10 AF11
GND_15 VD2_15
a
AF13 AF15
GND_16 VD2_16
AF17 AF19
1 C4171 1 C4161 1 C4159 1 C4152 1 C4150 1 C4125 1 C4118 1 C4116 1 C4181 1 C4166
GND_17 VD2_17 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
AG11 AG13 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
GND_18 VD2_18 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
AG15 AG17 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
GND_19 VD2_19 402 402 402 402 402 402 402 402 402 402
AG19 GND_20 AG21
VD2_20
AH02 GND_21 AH04
VD2_21
AH05 AH07
GND_22 VD2_22
n
AH08
GND_23 VD2_23 AH09 1 C4172 1 C4162 1 C4160 1 C4153 1 C4151 1 C4126 1 C4124 1 C4117 1 C4101 1 C4177
AJ13
GND_24 VD2_24 AJ11 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
AJ17 AJ15 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
GND_25 VD2_25 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
i
AJ21 AJ19 402 402 402 402 402 402 402 402 402 402
GND_26 VD2_26
AK01 AK02
GND_27 VD2_27
C
AK04
AK07
GND_28
GND_29
VD2_28
VD2_29
AK05
AK09
1
C4174 1
C4165 1
C4163 1
C4157 1
C4154 1
C4127 1
C4123 1
C4104 1
C4102
C
AK11 AK13
GND_30 VD2_30 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
AK15 AK17 20% 20% 20% 20% 20% 20% 20% 20% 20%
GND_31 VD2_31 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
AK19 GND_32 VD2_32 AK21
402 402 402 402 402 402 402 402 402
AM02 AM01
GND_33 VD2_33
AM05 AM04
GND_34 VD2_34
AM09 AM07
GND_35 VD2_35
AM13 GND_36 VD2_36 AM11 1 C4173 1 C4167 1 C4164 1 C4158 1 C4156 1 C4128 1 C4121 1 C4120 1 C4105 1 C4103
m
AM17
GND_37 VD2_37 AM15 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
AM21 AM19 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
GND_38 VD2_38 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
AN04 AN05 402 402 402 402 402 402 402 402 402 402
GND_39 VD2_39
KODIAK-ASIC-040812
il
AN07 GND_40 VD2_40 AN09
AN11 AN13
GND_41 VD2_41
AN15 GND_42 VD2_42 AN17
AN19 AN21
1
C4180 1
C4179 1
C4178 1
C4176 1
C4175 1
C4136 1
C4135 1
C4134 1
C4130 1
C4129
GND_43 VD2_43 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
AP01 GND_44 VD2_44 AP02 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
AR05 GND_45 VD2_45 AR03
402 402 402 402 402 402 402 402 402 402
AR09 AR07
GND_46 VD2_46
AR13 AR11
GND_47 VD2_47
AR17 AR15
GND_48 VD2_48
AR21 AR19 1 1
GND_49 VD2_49 C4132 C4131
0.22UF 0.22UF
e
AT03 AT05
GND_50 VD2_50 20% 20%
AT07 AT09 6.3V 6.3V
GND_51 VD2_51 2 X5R 2 X5R
AT11 AT13 402 402
GND_52 VD2_52
AT15 AT17
GND_53 VD2_53
AT19 AT21
GND_54 VD2_54
B B
r
K01 K02
GND_55 VD2_55
K04 K05
GND_56 VD2_56
M02 K08
GND_57 VD2_57
M05 M01
GND_58 VD2_58
M08 M04
GND_59 VD2_59
P01 M07
GND_60 VD2_60
P04 M10
GND_61 VD2_61
P07 GND_62 VD2_62 P02
P
P10 P05
GND_63 VD2_63
P12 P08
GND_64 VD2_64
T02 P11
GND_65 VD2_65
T05 P13
GND_66 VD2_66
T08 T01
GND_67 VD2_67
T11 T04
GND_68 VD2_68
T13 T07
GND_69 VD2_69
V01 GND_70 VD2_70 T10
V04 T12
GND_71 VD2_71
V07 GND_72 VD2_72 V02
V10 GND_73 V05
VD2_73
V12 V08
GND_74 VD2_74
Y02 GND_75 VD2_75 V11
Y05 V13
GND_76 VD2_76
Y08 GND_77 Y01
VD2_77
Y11 GND_78 VD2_78 Y04
Y13 GND_79 VD2_79 Y07
KODIAK EI PWR & CAPS
AF01 Y10
A AF04
GND_80
GND_81
VD2_80
VD2_81 Y12
SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
AF21
GND_82
AJ08 GND_83 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
AJ09
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
GND_84 AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
LAST_MODIFIED=Tue Aug 30 18:05:25 2005 41 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
y
P4MM
SM
56 26 EI_NB_SYSCLK_P 1
PP PP4216 P4MM
SM
r
56 26 EI_NB_SYSCLK_N 1
PP PP4201 P4MM
SM
1 P4MM
PP PP4202 SM
1
PP PP4203
AJ06 AJ07
EI OUTPUT TO CPU A API_REFCLK_N API_REFCLK_P EI INPUT FROM CPU A
56 EI_NB_TO_CPU_A_CLK_P L04
API0_BCLKIP API0_BCLKOP AA06 EI_CPU_A_TO_NB_CLK_P 56
EI_NB_TO_CPU_A_CLK_N L05 API0_BCLKIN API0_BCLKON AA07 EI_CPU_A_TO_NB_CLK_N
a
56 56
56 EI_NB_TO_CPU_A_AD<0> R01 API0_ADI0 API0_ADO0 AE03 EI_CPU_A_TO_NB_AD<0> 56
EI_NB_TO_CPU_A_AD<1> R02 U1900 AE04 EI_CPU_A_TO_NB_AD<1>
56 API0_ADI1 API0_ADO1 56
EI_NB_TO_CPU_A_AD<2> T06 BGA AE02 EI_CPU_A_TO_NB_AD<2> KODIAK DEFINES ADO
56 API0_ADI2 API0_ADO2 56
EI_NB_TO_CPU_A_AD<3> T03 (1 OF 10) AE01 EI_CPU_A_TO_NB_AD<3> AS AN INPUT AND ADI
56 API0_ADI3 API0_ADO3 56
EI_NB_TO_CPU_A_AD<4> U08 AD06 EI_CPU_A_TO_NB_AD<4> AS AN OUTPUT. NETS
56 API0_ADI4 API0_ADO4 56
API-PROC A
EI_NB_TO_CPU_A_AD<5> U07 AD03 EI_CPU_A_TO_NB_AD<5> NAMED APPROPRIATELY.
56 API0_ADI5 API0_ADO5 56
EI_NB_TO_CPU_A_AD<6> R03 AE05 EI_CPU_A_TO_NB_AD<6>
n
56 API0_ADI6 API0_ADO6 56
PLEASE FOLLOW THE NAMING CONVENTION OF BUSSES FOR DIRECTION
56 EI_NB_TO_CPU_A_AD<7> R04 API0_ADI7 API0_ADO7 AC04 EI_CPU_A_TO_NB_AD<7> 56
OF SIGNALS. BUSSES ARE NAMED FROM THE PERSPECTIVE OF THE CPU
56 EI_NB_TO_CPU_A_AD<8> R05 API0_ADI8 API0_ADO8 AC03 EI_CPU_A_TO_NB_AD<8> 56
PLEASE HAVE THE KODIAK TEAM REVIEW
56 EI_NB_TO_CPU_A_AD<9> T09
API0_ADI9 API0_ADO9 AC05 EI_CPU_A_TO_NB_AD<9> 56
i
56 EI_NB_TO_CPU_A_AD<10> R09 API0_ADI10 API0_ADO10 AC06 EI_CPU_A_TO_NB_AD<10> 56
56 EI_NB_TO_CPU_A_AD<11> R10 API0_ADI11 API0_ADO11 AC07 EI_CPU_A_TO_NB_AD<11> 56
C 56
56
EI_NB_TO_CPU_A_AD<12>
EI_NB_TO_CPU_A_AD<13>
P09
U10
API0_ADI12
API0_ADI13
API0_ADO12
API0_ADO13
AC08
AC02
EI_CPU_A_TO_NB_AD<12>
EI_CPU_A_TO_NB_AD<13>
56
56
C
56 EI_NB_TO_CPU_A_AD<14> P06 API0_ADI14 API0_ADO14 AA04 EI_CPU_A_TO_NB_AD<14> 56
56 EI_NB_TO_CPU_A_AD<15> P03 API0_ADI15 API0_ADO15 AA05 EI_CPU_A_TO_NB_AD<15> 56
56 EI_NB_TO_CPU_A_AD<16> N01 API0_ADI16 API0_ADO16 AB06 EI_CPU_A_TO_NB_AD<16> 56
EI_BUS SYS_CLK CONSTRAINTS MOVED TO PAGE 56 TO SUPPORT M23/M33
56 EI_NB_TO_CPU_A_AD<17> N02 API0_ADI17 API0_ADO17 AA03 EI_CPU_A_TO_NB_AD<17> 56
56 EI_NB_TO_CPU_A_AD<18> N03 API0_ADI18 API0_ADO18 AA02 EI_CPU_A_TO_NB_AD<18> 56
56 EI_NB_TO_CPU_A_AD<19> N04 API0_ADI19 API0_ADO19 AA01 EI_CPU_A_TO_NB_AD<19> 56
EI_NB_TO_CPU_A_AD<20> R08 AA08
P4MM
EI_CPU_A_TO_NB_AD<20>
m
56 API0_ADI20 API0_ADO20 56
1
SM
56 EI_NB_TO_CPU_A_AD<21> V06
API0_ADI21 API0_ADO21 AE06 EI_CPU_A_TO_NB_AD<21> 56
PP PP4204
56 EI_NB_TO_CPU_A_AD<22> M03 API0_ADI22 API0_ADO22 W06 EI_CPU_A_TO_NB_AD<22> 56
56 EI_NB_TO_CPU_A_AD<23> M06
API0_ADI23 API0_ADO23 W05 EI_CPU_A_TO_NB_AD<23> 56
il
56 EI_NB_TO_CPU_A_AD<24> N08 API0_ADI24 API0_ADO24 W07 EI_CPU_A_TO_NB_AD<24> 56
EI_NB_TO_CPU_A_AD<25> N07 API0_ADI25 API0_ADO25 W08 EI_CPU_A_TO_NB_AD<25>
KODIAK-ASIC-040812
56 56
56 EI_NB_TO_CPU_A_AD<26> N06 API0_ADI26 API0_ADO26 Y03 EI_CPU_A_TO_NB_AD<26> 56
56 EI_NB_TO_CPU_A_AD<27> N05 API0_ADI27 API0_ADO27 Y06 EI_CPU_A_TO_NB_AD<27> 56
56 EI_NB_TO_CPU_A_AD<28> L01 API0_ADI28 API0_ADO28 W04 EI_CPU_A_TO_NB_AD<28> 56
56 EI_NB_TO_CPU_A_AD<29> L02 API0_ADI29 API0_ADO29 W03 EI_CPU_A_TO_NB_AD<29> 56
56 EI_NB_TO_CPU_A_AD<30> L03 API0_ADI30 API0_ADO30 W02 EI_CPU_A_TO_NB_AD<30> 56
56 EI_NB_TO_CPU_A_AD<31> L09
API0_ADI31 API0_ADO31 AB09 EI_CPU_A_TO_NB_AD<31> 56
56 EI_NB_TO_CPU_A_AD<32> K06 API0_ADI32 API0_ADO32 AC09 EI_CPU_A_TO_NB_AD<32> 56
56 EI_NB_TO_CPU_A_AD<33> K09
API0_ADI33 API0_ADO33 AA10 EI_CPU_A_TO_NB_AD<33> 56
e
56 EI_NB_TO_CPU_A_AD<34> L10
API0_ADI34 API0_ADO34 AA09 EI_CPU_A_TO_NB_AD<34> 56
56 EI_NB_TO_CPU_A_AD<35> L08 API0_ADI35 API0_ADO35 Y09 EI_CPU_A_TO_NB_AD<35> 56
56 EI_NB_TO_CPU_A_AD<36> R07
API0_ADI36 API0_ADO36 U02 EI_CPU_A_TO_NB_AD<36> 56
56 EI_NB_TO_CPU_A_AD<37> R06 API0_ADI37 API0_ADO37 U01 EI_CPU_A_TO_NB_AD<37> 56
B EI_NB_TO_CPU_A_AD<38> L06
API0_ADI38 API0_ADO38 U03 EI_CPU_A_TO_NB_AD<38>
B
r
56 56
56 EI_NB_TO_CPU_A_AD<39> M09
API0_ADI39 API0_ADO39 U04 EI_CPU_A_TO_NB_AD<39> 56
56 EI_NB_TO_CPU_A_AD<40> N10
API0_ADI40 API0_ADO40 U05 EI_CPU_A_TO_NB_AD<40> 56
56 EI_NB_TO_CPU_A_AD<41> N09 API0_ADI41 API0_ADO41 V03 EI_CPU_A_TO_NB_AD<41> 56
Q63 APPLICATION IS PP1V5 PWRON
56 EI_NB_TO_CPU_A_AD<42> L07
API0_ADI42 API0_ADO42 W01 EI_CPU_A_TO_NB_AD<42> 56
56 EI_NB_TO_CPU_A_AD<43> K03 API0_ADI43 API0_ADO43 U06 EI_CPU_A_TO_NB_AD<43> 56
56 EI_NB_TO_CPU_A_SR_P<0> V09
API0_SRIP0 API0_SROP0 AC01 EI_CPU_A_TO_NB_SR_P<0> 56
=PPV_EI_NB 7 41 56
56 EI_NB_TO_CPU_A_SR_N<0> W10
API0_SRIN0 API0_SRON0 AB03 EI_CPU_A_TO_NB_SR_N<0> 56
P
1
56 EI_NB_TO_CPU_A_SR_P<1> W09 API0_SRIP1 API0_SROP1 AE08 EI_CPU_A_TO_NB_SR_P<1> 56 R4205
56 EI_NB_TO_CPU_A_SR_N<1> U09
API0_SRIN1 API0_SRON1 AE07 EI_CPU_A_TO_NB_SR_N<1> 56
4.7K
1%
1/16W
56 CPU_A0_QACK_L AH10 API_QACK0 API_QREQ0 AA11 CPU_A0_TO_NB_QREQ_L 42 56 MF-LF
402
2
56 CPU_A1_QACK_L AF12 API_QACK1 API_QREQ1 AF18 CPU_A1_TO_NB_QREQ_L 42 CPU_CHKSTOP_L IS SHARED BY BOTH CPUS
NB_APSYNC AC10 NB_CHKSTOP_L 56
56 26 API0_APSYNC
42 24 NB_CPU_A0_INT_L W11 IRQ0 AD09
R11
API_CSTP
56 42 NB_CPU_A1_INT_L IRQ1 MIN_LINE_WIDTH=0.2MM R4200
AL07 AG09 EI_REFCLK_AVDD 4.99 =PPV_PWRON_NB_REFCLK 7 59
56 NB_A_TRIGGER_OUT API0_SE API_REFCLK_AVDD 1 2
API_REFCLK_AGND 1% Q63 CONNECTS THIS TO KODIAK CORE
1/8W
AG10
1 C4200 1 C4201 MF-LF
P4MM 0.01UF 2.2UF
805
SM
1 10% 20%
PP4212 PP
2
16V
2
6.3V
CERM CERM1
P4MM 402 603
P4MM SM
SM 1
1 PP PP4206 KODIAK EI A
PP4213 PP
P4MM
P4MM
A PP4214
SM
PP
1
1
SM
PP PP4207
SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
P4MM
P4MM SM PULL DOWN QREQS TO NB
SM 1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 PP PP4208
PP4215 PP PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
P4MM R4207
SM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NET_SPACING_TYPE 1 10K
PP PP4209 56 42
CPU_A0_TO_NB_QREQ_L 1 2 II NOT TO REPRODUCE OR COPY IT
I290
NB_CPU_A0_INT_L P3MM SPACING 24 42
P4MM R4206 5% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I291
NB_CPU_A1_INT_L P3MM SPACING 42 56 SM 1/16W
1 10K MF-LF
PP PP4210 42
CPU_A1_TO_NB_QREQ_L 1 2 402 SIZE DRAWING NUMBER REV.
P4MM
1
SM
PP PP4211
5%
1/16W
MF-LF
APPLE COMPUTER INC.
D 051-6863 19
402
SCALE SHT OF
NONE
LAST_MODIFIED=Tue Aug 30 18:05:26 2005 42 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PG 49 & 52 HAVE MORE CAPS
D 56 9 EI_CPU_SYSCLK_P 56 55 52 50 49 48 =PPVCORE_CPU D
REMOVED BACKUP TERMINATION
y
OPTIONS TO OPTIMIZE ROUTING.
PCB: PLACE R4303 AND R4301 AT PROCESSOR PINS
1 C4353 1 C4347 1 C4345 1 C4339 1 C4337 1 C4328 1 C4324 1 C4320 1 C4314 1 C4312
1UF
10% 10%
1UF 1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
56 EI_CPU_SYSCLK_N 402 402 402 402 402 402 402 402 402 402
r
THIS RESISTOR IS HERE TO FIX A KODIAK BUG
IN TERM-OFF MODE 1 C4354 1 C4348 1 C4346 1 C4340 1 C4338 1 C4329 1 C4325 1 C4321 1 C4315 1 C4313
R4311 1UF
10% 10%
1UF 1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
110
1 2 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1%
T22
R22 402 402 402 402 402 402 402 402 402 402
1/16W SYSCLK* SYSCLK
MF-LF
402
EI_NB_TO_CPU_CLK_P EI_CPU_TO_NB_CLK_P
C4355 1 C4351 1 C4349 1 C4343 1 C4341 1 C4330 1 C4326 1 C4322 1 C4318 1 C4316
a
56 9 E24 EI_CLKI EI_CLKO D3
9 56
56 9 EI_NB_TO_CPU_CLK_N D24 EI_CLKI* CRITICAL EI_CLKO* E3 EI_CPU_TO_NB_CLK_N 9 56
1
56 EI_NB_TO_CPU_AD<0> H21
EI_ADI0 OMIT EI_ADO0 N3 EI_CPU_TO_NB_AD<0> 56
1UF
10% 10%
1UF 1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
EI_NB_TO_CPU_AD<1> EI_CPU_TO_NB_AD<1>
56
56
56
56
EI_NB_TO_CPU_AD<2>
EI_NB_TO_CPU_AD<3>
EI_NB_TO_CPU_AD<4>
J21
H22
J22
C13
EI_ADI1
EI_ADI2
EI_ADI3
EI_ADI4
U4300 EI_ADO1
EI_ADO2
EI_ADO3
EI_ADO4
H2
K3
L1
M3
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<4>
56
56
56
56
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
56 EI_NB_TO_CPU_AD<5> A13
EI_ADI5 EI_ADO5 K4 EI_CPU_TO_NB_AD<5> 56
56 EI_NB_TO_CPU_AD<6> K22
EI_ADI6
2.1GHZ-1.10V-45W-85C EI_ADO6 K2 EI_CPU_TO_NB_AD<6> 56
56 EI_NB_TO_CPU_AD<7> H23
EI_ADI7 (1 OF 3) EI_ADO7 H3 EI_CPU_TO_NB_AD<7> 56
EI_NB_TO_CPU_AD<8> EI_CPU_TO_NB_AD<8>
56
56 EI_NB_TO_CPU_AD<9>
EI_NB_TO_CPU_AD<10>
J24
G20
EI_ADI8
EI_ADI9 GPUL10S-DD3.1-CBGA EI_ADO8
EI_ADO9
H1
G4 EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<10>
56
56
1 C4356 1 C4352 1 C4350 1 C4344 1 C4342 1 C4331 1 C4327 1 C4323 1 C4319 1 C4317
56
56 EI_NB_TO_CPU_AD<11>
F23
G21
EI_ADI10
EI_ADI11
EI_ADO10
EI_ADO11
F2
F4 EI_CPU_TO_NB_AD<11>
56
56
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
n
56 EI_NB_TO_CPU_AD<12> D22
EI_ADI12 EI_ADO12 E2 EI_CPU_TO_NB_AD<12> 56 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
56 EI_NB_TO_CPU_AD<13> G24
EI_ADI13 EI_ADO13 G3 EI_CPU_TO_NB_AD<13> 56 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
56 EI_NB_TO_CPU_AD<14> G19
EI_ADI14 EI_ADO14 B8 EI_CPU_TO_NB_AD<14> 56 402 402 402 402 402 402 402 402 402 402
56 EI_NB_TO_CPU_AD<15> B15
EI_ADI15 EI_ADO15 D11 EI_CPU_TO_NB_AD<15> 56
56 EI_NB_TO_CPU_AD<16> A14
EI_ADI16 EI_ADO16 E12 EI_CPU_TO_NB_AD<16> 56
56 EI_NB_TO_CPU_AD<17> C15
EI_ADI17 EI_ADO17 A11 EI_CPU_TO_NB_AD<17> 56
56 EI_NB_TO_CPU_AD<18> D15
EI_ADI18 EI_ADO18 B10 EI_CPU_TO_NB_AD<18> 56
i
EI_NB_TO_CPU_AD<19> EI_CPU_TO_NB_AD<19>
56
56 EI_NB_TO_CPU_AD<20>
EI_NB_TO_CPU_AD<21>
A16
C22
EI_ADI19
EI_ADI20
EI_ADO19
EI_ADO20
C11
C1 EI_CPU_TO_NB_AD<20>
EI_CPU_TO_NB_AD<21>
56
56
1 C4300 1 C4360 1 C4359 1 C4358 1 C4357 1 C4336 1 C4335 1 C4334 1 C4333 1 C4332
56
56 EI_NB_TO_CPU_AD<22>
E20
E21
EI_ADI21
EI_ADI22
EI_ADO21
EI_ADO22
C5
B2 EI_CPU_TO_NB_AD<22>
56
56
1UF
10% 10%
1UF 1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
C 56
56
56
56
EI_NB_TO_CPU_AD<23>
EI_NB_TO_CPU_AD<24>
EI_NB_TO_CPU_AD<25>
EI_NB_TO_CPU_AD<26>
B23
B24
F21
B17
EI_ADI23
EI_ADI24
EI_ADI25
EI_ADO23
EI_ADO24
EI_ADO25
EI_ADO26
D6
A5
A2
D2
EI_CPU_TO_NB_AD<23>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<25>
EI_CPU_TO_NB_AD<26>
56
56
56
56
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
C
EI_ADI26
56 EI_NB_TO_CPU_AD<27> B19
EI_ADI27 EI_ADO27 D8 EI_CPU_TO_NB_AD<27> 56
56 EI_NB_TO_CPU_AD<28> C14
EI_ADI28 EI_ADO28 C12 EI_CPU_TO_NB_AD<28> 56
56 EI_NB_TO_CPU_AD<29> C17
EI_ADI29 EI_ADO29 A12 EI_CPU_TO_NB_AD<29> 56
EI_NB_TO_CPU_AD<30> EI_CPU_TO_NB_AD<30>
56
56 EI_NB_TO_CPU_AD<31>
EI_NB_TO_CPU_AD<32>
D18
B21
EI_ADI30
EI_ADI31
EI_ADO30
EI_ADO31
B6
B4 EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<32>
56
56
1 C4311 1 C4310 1 C4309 1 C4308 1 C4307 1 C4306 1 C4305 1 C4304 1 C4303 1C4302
56
56 EI_NB_TO_CPU_AD<33>
D20
A22
EI_ADI32
EI_ADI33
EI_ADO32
EI_ADO33
C4
C7 EI_CPU_TO_NB_AD<33>
56
56
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
56 EI_NB_TO_CPU_AD<34> C19
EI_ADO34 A7 EI_CPU_TO_NB_AD<34> 56
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
EI_ADI34
56 EI_NB_TO_CPU_AD<35> C18
EI_ADI35 EI_ADO35 C8 EI_CPU_TO_NB_AD<35> 56
56 EI_NB_TO_CPU_AD<36> A21 EI_ADO36 C6 EI_CPU_TO_NB_AD<36> 56
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
56 EI_NB_TO_CPU_AD<37> A23
EI_ADI36
EI_ADI37 EI_ADO37 A4 EI_CPU_TO_NB_AD<37> 56
402 402 402 402 402 402 402 402 402 402
56 EI_NB_TO_CPU_AD<38> A20
EI_ADI38 EI_ADO38 A9 EI_CPU_TO_NB_AD<38> 56
56 EI_NB_TO_CPU_AD<39> A18
EI_ADI39 EI_ADO39 C9 EI_CPU_TO_NB_AD<39> 56
m
56 EI_NB_TO_CPU_AD<40> A15
EI_ADI40 EI_ADO40 A10 EI_CPU_TO_NB_AD<40> 56
56 EI_NB_TO_CPU_AD<41> A17
EI_ADI41 EI_ADO41 C10 EI_CPU_TO_NB_AD<41> 56
56 EI_NB_TO_CPU_AD<42> C16
EI_ADI42 EI_ADO42 A8 EI_CPU_TO_NB_AD<42> 56
56 EI_NB_TO_CPU_AD<43> A19
EI_ADI43 EI_ADO43 A6 EI_CPU_TO_NB_AD<43> 56
56 9 EI_NB_TO_CPU_SR_P<0> L24
EI_SRI0 EI_SRO0 L3 EI_CPU_TO_NB_SR_P<0> 56
56 9 EI_NB_TO_CPU_SR_N<0> K24
EI_SRI0* EI_SRO0* L2 EI_CPU_TO_NB_SR_N<0> 56
il
56 EI_NB_TO_CPU_SR_P<1> L21
EI_SRI1 EI_SRO1 G1 EI_CPU_TO_NB_SR_P<1> 9 56
56 EI_NB_TO_CPU_SR_N<1> L22
EI_SRI1* EI_SRO1* F1 EI_CPU_TO_NB_SR_N<1> 9 56
56 CPU_QACK_L V21
QACK* QREQ* AB12 CPU_QREQ_L 43
56 8 CPU_CHKSTOP_L R20
CHKSTOP* INT* AB19 CPU_INT_L 56
56 EI_CPU_TBEN_CLK AD17
TBEN PCB: MATCH APSYNC LENGTH TO SYSCLK
56 CPU_APSYNCOUT AD14
APSYNCOUT APSYNCIN AA10 EI_CPU_APSYNC 56
29 CPU_HRESET_L V20
HRESET* IIC_SCL AA20 I2C_CPU_SCL 47
QREQ_L AND SUSPENDREQ_L AND HACK
IIC_SDA Y21 I2C_CPU_SDA 47 SAME AS Q45
56 CPU_SRESET_L AB4
SRESET*
I2CGO N22 I2CGO 47
47 PROC_THERM_INT_L V22
THERM_INT*
CKTERMDIS AA14 CKTERMDIS_L 47
47 PROCID0 L19
PROCID0
47 PROCID1 M19
PROCID1 EI_DISABLE P20 EI_DISABLE 47
e
47 PROCID2 M18
PROCID2
BUSCFG0 AA19 BUSCFG0 47 30 28 7 =PP3V3_PWRON_SMU
56 47 CPU_TRIGGER_IN N21
TRIGGER_IN BUSCFG1 AC19 BUSCFG1 47
56 CPU_TRIGGER_OUT N19
TRIGGER_OUT BUSCFG2 AB16 BUSCFG2 47
CRITICAL
56
47
47 BIMODE_L
CPU_AFN
AVPRESET_L
AA12
W23
AC24
AFN
AVPRESET*
ATTENTION
GPUL_DBG
SPARE2 JTAGMODE
AD12
AA22
W4
CPU_ATTENTION
UNDEFINED
56
GPUL_DBG
CPU_SPARE2
47
9 47
C4372
0.1UF
1
U4310
47 C1UNDGLOBAL AC16
BIMODE*
74LVC1G66DBVG4
B C2UNDGLOBAL
C1UNDGLOBAL
JTAG_CPU_TCK 20%
SOT23-5 B
r
AC15 TCK AD21
47 9 30
47 DI2_L U24
C2UNDGLOBAL
DI2* TDI AB21 JTAG_CPU_TDI 9 30
10V
CERM 2
5
TDO AD13 JTAG_CPU_TDO 9 30 47 402 TI
47 LSSDMODE AB5
LSSDMODE TMS AD22 JTAG_CPU_TMS 9 30 VCC
47 LSSDSCANENABLE U19
LSSDSCANENABLE TRST* W20 JTAG_CPU_TRST_L 9 47
LSSDSTOPC2ENABLE AD8
47
47 LSSDSTOPC2STARENABLE AD7
LSSDSTOPC2ENABLE
LSSDSTOPC2STARENABLE BYPASS* V24 CPU_BYPASS_L 29 43 CPU_QREQ_L 1 2 CPU_TO_NB_QREQ_L 56
47 LSSDSTOPENABLE AD11
LSSDSTOPENABLE PLLLOCK T20 PLLLOCK 8 9
56 CPU_MCP_L AD18
MCP* PLLMULT AA8 PLLMULT 47
PLLRANGE0 AB7 PLLRANGE0 47
56 CPU_PSRO V23
PSRO1 PLLRANGE1 AA9 PLLRANGE1 47 30 28 24 SMU_SUSPENDREQ_L 4
56 CPU_PSRO_ENABLE V5
PSRO2 PSRO_ENABLE PLLTEST W22 PLLTEST 47
47 PULSESEL0 AC9
PULSESEL0 PLLTESTOUT T19 PLLTESTOUT 9 47
47 PULSESEL1 AB11
47 PULSESEL2 AC10
PULSESEL1
PULSESEL2 SPARE AA13 CPU_SPARE 47
GND
47 RAMSTOPENABLE
RI_L
AB6
RAMSTOPENABLE 3 NOSTUFF
P
AA5
47 RI*
SYNCENABLE AB24
47 SYNCENABLE*
R4310
0 1 2
5%
1/16W
MF-LF
402
CPU EI AND IO
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 43 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P4MM
PLEASE FOLLOW THE NAMING CONVENTION OF BUSSES FOR DIRECTION SM
1
OF SIGNALS. BUSSES ARE NAMED FROM THE PERSPECTIVE OF THE CPU
PP PP4410
PLEASE HAVE THE KODIAK TEAM REVIEW P4MM
SM
1
PP PP4411
EI OUTPUT TO CPU B EI INPUT FROM CPU B
56
EI_NB_TO_CPU_B_CLK_P AT08
API1_BCLKIP API1_BCLKOP AT16 EI_CPU_B_TO_NB_CLK_P 56
D 56
EI_NB_TO_CPU_B_CLK_N AR08
API1_BCLKIN API1_BCLKON AR16 EI_CPU_B_TO_NB_CLK_N 56 D
56
EI_NB_TO_CPU_B_AD<0> AM12
API1_ADI0 API1_ADO0 AP20 EI_CPU_B_TO_NB_AD<0> 56
y
EI_NB_TO_CPU_B_AD<1> AN12
U1900 AN20 KODIAK DEFINES ADO
56 API1_ADI1 API1_ADO1 EI_CPU_B_TO_NB_AD<1> 56
EI_NB_TO_CPU_B_AD<2> AL12 BGA AR20 AS AN INPUT AND ADI
56 API1_ADI2 API1_ADO2 EI_CPU_B_TO_NB_AD<2> 56
EI_NB_TO_CPU_B_AD<3> AK12 (2 OF 10) AT20 AS AN OUTPUT. NETS
56 API1_ADI3 API1_ADO3 EI_CPU_B_TO_NB_AD<3> 56
EI_NB_TO_CPU_B_AD<4> AP11 AL19 NAMED APPROPRIATELY.
56 API1_ADI4 API1_ADO4 EI_CPU_B_TO_NB_AD<4> 56
API-PROC B
EI_NB_TO_CPU_B_AD<5> AP19
r
AL11 EI_CPU_B_TO_NB_AD<5> 56
56 API1_ADI5 API1_ADO5 WE MAY NEED A DIFFERENT
56
EI_NB_TO_CPU_B_AD<6> AP12
API1_ADI6 API1_ADO6 AM20 EI_CPU_B_TO_NB_AD<6> 56 ELECTRICAL_CONSTRAINT_SET
56
EI_NB_TO_CPU_B_AD<7> AR12
API1_ADI7 API1_ADO7 AM18 EI_CPU_B_TO_NB_AD<7> 56 FOR CPU_A AND CPU_B.
56
EI_NB_TO_CPU_B_AD<8> AT12
API1_ADI8 API1_ADO8 AL18 EI_CPU_B_TO_NB_AD<8> 56
56
EI_NB_TO_CPU_B_AD<9> AH12
API1_ADI9 API1_ADO9 AN18 EI_CPU_B_TO_NB_AD<9> 56
56
EI_NB_TO_CPU_B_AD<10> AG12
API1_ADI10 API1_ADO10 AP18 EI_CPU_B_TO_NB_AD<10> 56
56
EI_NB_TO_CPU_B_AD<11> AH13
API1_ADI11 API1_ADO11 AR18 EI_CPU_B_TO_NB_AD<11> 56
EI_BUS SYS_CLK CONSTRAINTS MOVED TO PAGE 56 TO SUPPORT M23/M33
a
56
EI_NB_TO_CPU_B_AD<12> AJ12
API1_ADI12 API1_ADO12 AT18 EI_CPU_B_TO_NB_AD<12> 56
56
EI_NB_TO_CPU_B_AD<13> AG14
API1_ADI13 API1_ADO13 AK18 EI_CPU_B_TO_NB_AD<13> 56
56
EI_NB_TO_CPU_B_AD<14> AM10
API1_ADI14 API1_ADO14 AP17 EI_CPU_B_TO_NB_AD<14> 56
56
EI_NB_TO_CPU_B_AD<15> AL10
API1_ADI15 API1_ADO15 AL17 EI_CPU_B_TO_NB_AD<15> 56
56
EI_NB_TO_CPU_B_AD<16> AN10
API1_ADI16 API1_ADO16 AH20 EI_CPU_B_TO_NB_AD<16> 56
56
EI_NB_TO_CPU_B_AD<17> AP10
API1_ADI17 API1_ADO17 AJ20 EI_CPU_B_TO_NB_AD<17> 56
56
EI_NB_TO_CPU_B_AD<18> AR10
API1_ADI18 API1_ADO18 AK20 EI_CPU_B_TO_NB_AD<18> 56
EI_NB_TO_CPU_B_AD<19> AT10 AH19 EI_CPU_B_TO_NB_AD<19> 56
n
56 API1_ADI19 API1_ADO19
EI_NB_TO_CPU_B_AD<20> AK10 AG20 P4MM
56 API1_ADI20 API1_ADO20 EI_CPU_B_TO_NB_AD<20> 56 SM
1
56
EI_NB_TO_CPU_B_AD<21> AJ10
API1_ADI21 API1_ADO21 AL20 EI_CPU_B_TO_NB_AD<21> 56 PP PP4413
56
EI_NB_TO_CPU_B_AD<22> AM08
API1_ADI22 API1_ADO22 AM16 EI_CPU_B_TO_NB_AD<22> 56
i
56
EI_NB_TO_CPU_B_AD<23> AN08
API1_ADI23 API1_ADO23 AN16 EI_CPU_B_TO_NB_AD<23> 56
56
EI_NB_TO_CPU_B_AD<24> AL08
API1_ADI24 API1_ADO24 AL16 EI_CPU_B_TO_NB_AD<24> 56
C 56
56
EI_NB_TO_CPU_B_AD<25>
EI_NB_TO_CPU_B_AD<26>
AP07
AT06
API1_ADI25
API1_ADI26
API1_ADO25
API1_ADO26
AK16
AP15
EI_CPU_B_TO_NB_AD<25> 56
EI_CPU_B_TO_NB_AD<26> 56
C
KODIAK-ASIC-040812
56
EI_NB_TO_CPU_B_AD<27> AR06
API1_ADI27 API1_ADO27 AL15 EI_CPU_B_TO_NB_AD<27> 56
56
EI_NB_TO_CPU_B_AD<28> AP08
API1_ADI28 API1_ADO28 AP16 EI_CPU_B_TO_NB_AD<28> 56
56
EI_NB_TO_CPU_B_AD<29> AT04
API1_ADI29 API1_ADO29 AM14 EI_CPU_B_TO_NB_AD<29> 56
56
EI_NB_TO_CPU_B_AD<30> AR04
API1_ADI30 API1_ADO30 AL14 EI_CPU_B_TO_NB_AD<30> 56
56
EI_NB_TO_CPU_B_AD<31> AP05
API1_ADI31 API1_ADO31 AN14 EI_CPU_B_TO_NB_AD<31> 56
56
EI_NB_TO_CPU_B_AD<32> AM06
API1_ADI32 API1_ADO32 AP14 EI_CPU_B_TO_NB_AD<32> 56
EI_NB_TO_CPU_B_AD<33> AN06 AR14 EI_CPU_B_TO_NB_AD<33> 56
m
56 API1_ADI33 API1_ADO33
56
EI_NB_TO_CPU_B_AD<34> AP06
API1_ADI34 API1_ADO34 AT14 EI_CPU_B_TO_NB_AD<34> 56
56
EI_NB_TO_CPU_B_AD<35> AP04
API1_ADI35 API1_ADO35 AK14 EI_CPU_B_TO_NB_AD<35> 56
56
EI_NB_TO_CPU_B_AD<36> AM03
API1_ADI36 API1_ADO36 AP13 EI_CPU_B_TO_NB_AD<36> 56
il
56
EI_NB_TO_CPU_B_AD<37> AN01
API1_ADI37 API1_ADO37 AL13 EI_CPU_B_TO_NB_AD<37> 56
56
EI_NB_TO_CPU_B_AD<38> AL06
API1_ADI38 API1_ADO38 AG16 EI_CPU_B_TO_NB_AD<38> 56
56
EI_NB_TO_CPU_B_AD<39> AL05
API1_ADI39 API1_ADO39 AH15 EI_CPU_B_TO_NB_AD<39> 56
56
EI_NB_TO_CPU_B_AD<40> AL04
API1_ADI40 API1_ADO40 AJ14 EI_CPU_B_TO_NB_AD<40> 56
56
EI_NB_TO_CPU_B_AD<41> AL03
API1_ADI41 API1_ADO41 AH14 EI_CPU_B_TO_NB_AD<41> 56
56
EI_NB_TO_CPU_B_AD<42> AN02
API1_ADI42 API1_ADO42 AH16 EI_CPU_B_TO_NB_AD<42> 56
56
EI_NB_TO_CPU_B_AD<43> AN03
API1_ADI43 API1_ADO43 AH17 EI_CPU_B_TO_NB_AD<43> 56
EI_NB_TO_CPU_B_SR_P<0> AP09 AG18 EI_CPU_B_TO_NB_SR_P<0>
56 API1_SRIP0 API1_SROP0 56
EI_NB_TO_CPU_B_SR_N<0> AL09 AJ16 EI_CPU_B_TO_NB_SR_N<0>
56 API1_SRIN0 API1_SRON0 56
e
EI_NB_TO_CPU_B_SR_P<1> AR02 AJ18 EI_CPU_B_TO_NB_SR_P<1>
56 API1_SRIP1 API1_SROP1 56
EI_NB_TO_CPU_B_SR_N<1> AP03 AH18 EI_CPU_B_TO_NB_SR_N<1>
56 API1_SRIN1 API1_SRON1 56
CPU_B0_QACK_L AF14 AF16 CPU_B0_TO_NB_QREQ_L 44
56 API_QACK2 API_QREQ2
CPU_B1_QACK_L AC11 AF20 CPU_B1_TO_NB_QREQ_L 44
56 API_QACK3 API_QREQ3
B B
r
56 44 NB_CPU_B0_INT_L N11 IRQ2
NB_CPU_B1_INT_L U11 P4MM
56 44 IRQ3
SM
1
9 TP_NB_APSYNC AH11
API1_APSYNC PP PP4400
AK08
P4MM
56 NB_B_TRIGGER_OUT API1_SE SM
1
PP PP4401
WIRE TP_NB_APSYNC TO A TEST POINT
P4MM
SM
1
P
PP PP4402
P4MM P4MM
SM SM
1 1
PP4406 PP PP PP4403
P4MM P4MM
SM SM
1 1
PP4407 PP PP PP4404
P4MM
SM
1
P4MM
SM
PP4408 PP 1
PP PP4405
NET_SPACING_TYPE
I48
NB_CPU_B0_INT_L P3MM SPACING 44 56
I49
NB_CPU_B1_INT_L P3MM SPACING 44 56
PULL DOWN QREQS TO NB
KODIAK EI B
R4407
A 44
CPU_B0_TO_NB_QREQ_L 1
10K
2
SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
5%
R4406 1/16W
CPU_B1_TO_NB_QREQ_L 10K MF-LF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
44 1 2 402 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
5%
1/16W I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF-LF
402 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
LAST_MODIFIED=Tue Aug 30 18:05:28 2005 44 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SELECT PROCESSOR CLOCK MULTIPLIER. PROCESSOR CLOCK(MHZ)= SYSTCLOCK * PLLMULT.
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
*
TABLE_5_ITEM
116S0066 1 RES,1K OHM,1/16W,5%,0402 R4734 EI_3TO1 SYSCLK * 12
TABLE_5_ITEM
116S0066 1 RES,1K OHM,1/16W,5%,0402 R4718 EI_2TO1 SYSCLK * 8
=PPV_EI_CPU 7 29 30 47 48 56 PULLUPS PULLDOWNS SELECT EI BUS DIVIDER. BUS DATA RATE(BPS)= (PROCESSOR CLOCK) / BUSCFG.
R4739 NOTES TABLE_5_HEAD
CPU_SPARE2 1
0 2
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
43 9
TABLE_5_ITEM
5% PROC / 2
1/16W JTAG DRIVEN ON SMU PG 30 116S0066 3 RES,1K OHM,1/16W,5%,0402 R4724,R4726,R4728 EI_2TO1
MF-LF
QREQ PULLDOWNS ON Q63 SHARED PAGE *
TABLE_5_ITEM
C1UNDGLOBAL R4709 402 116S0066 3 RES,1K OHM,1/16W,5%,0402 R4724,R4726,R4712 EI_3TO1 PROC / 3
43
4.7K 1 SRESET DRIVEN ON PG 56
D NOSTUFF
R4777 R4743
43 9
JTAG_CPU_TRST_L 2
5% LSSDMODE
R4745
4.7K 2 INT DRIVEN BY KODIAK 116S0066 3 RES,1K OHM,1/16W,5%,0402 R4724,R4710,R4728 NOSTUFF
TABLE_5_ITEM
PROC / 4 D
43 1 R4739 REQUIRED TO ACCESS THE RINGS TABLE_5_ITEM
4.7K 2 4.7K 2 1/16W
116S0066 3 RES,1K OHM,1/16W,5%,0402 R4724,R4710,R4712 NOSTUFF PROC / 6
y
1 1 MF-LF 5%
402 1/16W TABLE_5_ITEM
5% 5% MF-LF 4.7K RESISTORS FOR MANUFACTURING-TEST-TYPE PULLUPS OR PULLDOWNS. 116S0066 3 RES,1K OHM,1/16W,5%,0402 R4708,R4726,R4728 NOSTUFF PROC / 8
1/16W
MF-LF
1/16W
MF-LF
R4731 402
1K RESISTORS FOR IMPORTANT USE OR STRAPPING OPTIONS.
4.7K 2
TABLE_5_ITEM
C2UNDGLOBAL 402 402
43
BIMODE_L 1 R4741 116S0066 3 RES,1K OHM,1/16W,5%,0402 R4708,R4726,R4712 NOSTUFF PROC / 12
43
NOSTUFF 5% LSSDSCANENABLE 1
4.7K 2 TABLE_5_ITEM
1/16W 43 116S0066 3 RES,1K OHM,1/16W,5%,0402 R4708,R4710,R4728 NOSTUFF PROC / 16
r
R4779 R4769 MF-LF
402 5% TABLE_5_ITEM
1
4.7K 2 1
4.7K 2 1/16W 116S0066 3 RES,1K OHM,1/16W,5%,0402 R4708,R4710,R4712 NOSTUFF
MF-LF
5% 5%
R4733 402
DI2_L 4.7K 2
1/16W
MF-LF
1/16W
MF-LF 43 1 R4747 SELECT ELASTIC MODE OR BYPASS.
402 402 5% LSSDSTOPC2ENABLE 1
4.7K 2
43
PLLTEST 1/16W 43
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
MF-LF 5%
NOSTUFF 402 1/16W
*
TABLE_5_ITEM
R4763 R4761 MF-LF
a
116S0066 1 RES,1K OHM,1/16W,5%,0402 R4736
4.7K 2 4.7K 2
R4735 402
4.7K 2
TABLE_5_ITEM
1 1
43
RI_L 1 R4749 116S0066 1 RES,1K OHM,1/16W,5%,0402 R4720 NOSTUFF BYPASS MODE
5% 5% 5% LSSDSTOPC2STARENABLE 4.7K 2
1/16W
MF-LF
1/16W
MF-LF 1/16W 43 1 SELECT PLL FREQUENCY RANGE.
402 402 MF-LF 5%
CKTERMDIS_L
TABLE_5_HEAD
402 1/16W
43 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
MF-LF
NOSTUFF R4765 402 TABLE_5_ITEM
R4775 R4773 PROC_THERM_INT_L 1
4.7K 2
R4751
116S0066 2 RES,1K OHM,1/16W,5%,0402 R4730,R4732 CPU_PLL_LOW
4.7K 2 4.7K 2 43 TABLE_5_ITEM
1 1 4.7K 2 >= 1.8 GHZ *
n
5%
43
LSSDSTOPENABLE 1
116S0066 2 RES,1K OHM,1/16W,5%,0402 R4730,R4716 CPU_PLL_HIGH
5% 5% 1/16W TABLE_5_ITEM
1/16W 1/16W MF-LF 5%
402 116S0066 2 RES,1K OHM,1/16W,5%,0402 R4714,R4732 CPU_PLL_MEDIUM
MF-LF MF-LF 1/16W
402 402 MF-LF
GPUL_DBG
TABLE_5_ITEM
43 R4787 402 116S0066 2 RES,1K OHM,1/16W,5%,0402 R4714,R4716 NOSTUFF RESERVED
i
NOSTUFF I2CGO 4.7K 2
R4740 R4742 43 1 R4737
5% SYNCENABLE 4.7K 2
4.7K 2 4.7K 2
C 1
5%
1
5%
1/16W
MF-LF
402
43 1
5%
1/16W
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
TABLE_5_ITEM
C
1/16W 1/16W MF-LF 116S0066 1 RES,1K OHM,1/16W,5%,0402 R4722 AVPRESET OFF
MF-LF
402
MF-LF
402
R4788 402
4.7K 2
TABLE_5_ITEM
43
I2C_CPU_SCL 1 R4755 116S0066 1 RES,1K OHM,1/16W,5%,0402 R4738 NOSTUFF AVPRESET ON
5% RAMSTOPENABLE 1
4.7K 2
1/16W 43
MF-LF 5%
M23/M33 IS JTAG ONLY, NO I2C 402 1/16W =PPV_EI_CPU 7 29 30 47 48 56 * STUFF THESE ON M23.
MF-LF
R4789 402
1
I2C_CPU_SDA 4.7K 2 NOSTUFF
R4767 R4768
m
1
43 10K
5% CPU_SPARE 1
4.7K 2 5%
1/16W
MF-LF
43
5%
1/16W
MF-LF PROCESSOR BUS CONFIGURATION
402 1/16W 2 402
il
MF-LF
R4790 402 56 48 47 30 29 7
=PPV_EI_CPU
4.7K 2 SEE STUFFING OPTIONS ABOVE
43 30 9
JTAG_CPU_TDO 1 R4781
5% CPU_TRIGGER_IN 1
4.7K 2
1/16W 56 43
MF-LF 5% 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT
402 1/16W R4708 R4710 R4712 R4714 R4716 R4718 R4720 R4722
MF-LF 1K 1K 1K 1K 1K 1K 1K 1K
402 5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
R4703 MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
PULSESEL0 1
4.7K 2 BUSCFG0
43 43
5% 43
BUSCFG1
1/16W
BUSCFG2
e
MF-LF 43
402 PLLRANGE0
43
R4705 43
PLLRANGE1
PULSESEL1 1
4.7K 2 PLLMULT
43 43
5% 43
EI_DISABLE
B 1/16W
B
r
MF-LF 43
AVPRESET_L
402
R4707 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT
PULSESEL2 1
4.7K 2 R4724 R4726 R4728 R4730 R4732 R4734 R4736 R4738
43
1K 1K 1K 1K 1K 1K 1K 1K
5% 5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
402
2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402
R4702
4.7K 2
P
43
PROCID0 1
5%
1/16W
MF-LF
402
R4704
PROCID1 1
4.7K 2
43
5%
1/16W
MF-LF
402
R4706
PROCID2 1
4.7K 2
43
5%
1/16W
MF-LF
402
NOSTUFF
R4771
4.7K 2
43 9
PLLTESTOUT 1 CPU STRAPS
5%
1/16W
A MF-LF
402
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 47 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
56 55 52 50 49 43 =PPVCORE_CPU =PPV_EI_CPU 7 29 30 47 56
VOLTAGE=1.3V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
L4801 NET_PHYSICAL_TYPE=PROC_DIFF
1 C4817 1 C4816 1 C4815 1 C4814 1 C4811 1 C4806 1 C4805 1 C4803
R4832 60-OHM-EMI NET_SPACING_TYPE=PROC_DIFF
DIFFERENTIAL_PAIR=P_TDD
MIN_LINE_WIDTH=0.25MM 10UF 10UF 10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF
2.2 PPV_RUN_CPU_AVDD_R_L MIN_NECK_WIDTH=0.20MM
54 PPV_RUN_AVDD_CPU 1 2 PPV_RUN_CPU_AVDD_R 1 2 6
CPU_DIODE_POS 6 55
10%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V
20%
10V
20%
10V
20%
10V
20%
10V
VOLTAGE=2.8V
SM VOLTAGE=2.8V 2 X5R 2 X5R 2 X5R 2 X5R 2 CERM 2 CERM 2 CERM 2 CERM
5% MIN_LINE_WIDTH=0.60MM MIN_LINE_WIDTH=0.60MM
1/10W MIN_NECK_WIDTH=0.20MM 0805 MIN_NECK_WIDTH=0.20MM
805 805 805 805 402 402 402 402
MF-LF
603 P24 Y1 R2
D AVDD KPVDD1
DIODEPOS
KPVDD2
1 C4812 1 C4809 1 C4807 1 C4804 D
1 C4802 1 C4800
A1
A24
A3
B1
CRITICAL
OMIT 0.1UF 0.1UF 0.1UF 0.1UF
10UF
y
B11 B12 20% 20% 20% 20%
10%
6.3V
2 X5R
0.1UF
10%
16V
B13
B16
OMIT
CRITICAL
B14
B18
P1
P11 U4300 Z_OUT
P18
P2
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
805 2 X5R
402
B20
B3
B7
C2
U4300 B22
B5
B9
C21
P13
2.1GHZ-1.10V-45W-85C
P15
P17
P19
P22
P4
P6
P8
C20 2.1GHZ-1.10V-45W-85C C23 (3 OF 3)
P21 Z_SENSE R1
C24 (2 OF 3) C3 P23 GPUL10S-DD3.1-CBGA R11 1 C4813 1 C4810 1 C4808
r
D13 D1 P3 R13
D17 GPUL10S-DD3.1-CBGA D10 P5 R15 0.1UF 0.1UF 0.1UF
D19 D12 P7 R17 20% 20% 20%
D21 D14 P9 R19 10V 10V 10V
2 CERM 2 CERM 2 CERM
D23 D16 R10 R21
D5 D4 R12 R23 402 402 402
D7 E11 R14 R3
D9 E13 R16 R5
E1 E15 R18 R7
E10 E17 R4 R9
E14
E16
E19
E23
R6
R8
T10
T12
1 C4826 1 C4820 1 C4818
E18 E5 T1 T14 0.1UF 0.1UF 0.1UF
E22 E7 T11 T16 20% 20% 20%
a
E4 E9 T13 T18 2 10V
CERM 2 10V
CERM 2 10V
CERM
E6 F10 T15 T24
E8 F12 T17 T4 402 402 402
F11 F14 T21 T6
F13 F16 T23 T8
F15 F18 T3 U1
F17 F20 T5 U11
F19
F3
F22
F24
T7
T9
U13
U15
1 C4827 1 C4821 1 C4819
F5 F6 U10 U17 0.1UF 0.1UF 0.1UF
F7 F8 U12 U21 20% 20% 20%
F9 G11 U14 U23 10V 10V 10V
2 CERM 2 CERM 2 CERM
G10 G13 U16 U3
G12 G15 U18 U5 402 402 402
n
G14 G17 U2 U7
G16 G2 U20 U9
G18 G23 U22 V10
G22 G5 U4 V12
G6
G8
G7
G9
U6
U8
V14
V16
1 C4828 1 C4824 1 C4822
H11 H10 V1 V18 0.1UF 0.1UF 0.1UF
i
H13 H12 V11 V2 20% 20% 20%
H15 H14 V13 V4 2 10V
CERM 2 10V
CERM
10V
2 CERM
H17 H16 V15 V6
H19 H18 V17 V8 402 402 402
C H24
H5
H7
H9 VCORE GND
H20
H4
H6
H8
V19
V3
V7
V9
VCORE
X100
GND
X99
W1
W11
W13
W15
C
J1
J10
X105 X105 J11
J13
W10
W12
W17
W19
1 C4829 1 C4825 1 C4823
J12 J15 W14 W21 0.1UF 0.1UF 0.1UF
J14 J17 W16 W3 20% 20% 20%
J16 J19 W18 W5 10V 10V 10V
2 CERM 2 CERM 2 CERM
J18 J23 W2 W7
J2 J3 W24 W9 402 402 402
J20 J5 W6 Y10
J4 J7 W8 Y12
J6 J9 Y11 Y14
J8 K1 Y13 Y16
K11
K13
K10
K12
Y15
Y17
Y18
Y2
1 C4836 1 C4831 1 C4830
0.1UF 0.1UF 0.1UF
m
K15 K14 Y19 Y20
K17 K16 Y22 Y24 20% 20% 20%
K19 K18 Y23 Y4 2 10V
CERM 2 10V
CERM
10V
2 CERM
K21 K20 Y3 Y6
K23 K6 Y5 Y8 402 402 402
K5 K8 Y7 AA11
K7 L11 Y9 AA15
il
K9 L13 AA16 AA17
L10 L15 AA18 AA21
L12
L14
L17
L23
AA2
AA24
AA23
AA3
1 C4837 1 C4834 1 C4832
L16 L5 AA4 AA7 0.1UF 0.1UF 0.1UF
L18 L7 AA6 AB10 20% 20% 20%
L20 L9 AB1 AB14 10V 10V 10V
2 CERM 2 CERM 2 CERM
L4 M10 AB13 AB18
L6 M12 AB15 AB2 402 402 402
L8 M14 AB17 AB20
M1 M16 AB23 AB22
M11 M2 AB3 AB8
M13 M20 AB9 AC1
M15
M17
M22
M24
AC12
AC14
AC11
AC13
1 C4838 1 C4835 1 C4833
M21 M4 AC18 AC17 0.1UF 0.1UF 0.1UF
M23 M6 AC2 AC21 20% 20% 20%
M5 M8 AC20 AC23 2 10V
CERM 2 10V
CERM 2 10V
CERM
M7 SPARE_GND N1 AC22 AC3
M9 N11 AC4 AC5 402 402 402
e
N10 N13 AC6 AC7
N12 N15 AC8 AD10
N14 N17 AD1 AD16
N16 N23 AD15 AD2
N18
N2
N5
N7
AD19
AD23
AD20
AD24
1 C4845 1 C4841 1 C4839
N20 N9 AD3 AD4 0.1UF 0.1UF 0.1UF
N24 P10 AD5 AD6 20% 20% 20%
N4 P12 AD9 10V 10V 10V
2 CERM 2 CERM 2 CERM
B B
r
N6 P14
N8 P16 402 402 402
DIODENEG
AGND KPGND1 KPGND2
R24 AA1 T2
1 C4846 1 C4842 1 C4840
NOSTUFF PROCESSOR KELVIN POINT PROBE POINT 0.1UF 0.1UF 0.1UF
20% 20% 20%
6 GND_CPU_AVDD R4810 2 10V
CERM 2 10V
CERM 2 10V
CERM
1
100K 2 KPVDD2 6 50 55 402 402 402
2 OMIT DIFFERENTIAL_PAIR=P_KP2
5% MIN_LINE_WIDTH=0.25MM
XW4800 1/10W MIN_NECK_WIDTH=0.20MM
P
MF-LF NET_SPACING_TYPE=PROC_DIFF
SM 603 NET_PHYSICAL_TYPE=PROC_DIFF 1 C4847 1 C4844 1 C4843
REMEMBER TO CHANGE KPVDD TO NO_TEST ON PG 6. 0.1UF 0.1UF 0.1UF
1 20% 20% 20%
PCB:PUT R4810 AS CLOSE TO RESPECTIVE PINS AS POSSIBLE. 10V 10V 10V
2 CERM 2 CERM 2 CERM
55 6 CPU_DIODE_NEG KPGND2 6 50 55 402 402 402
DIFFERENTIAL_PAIR=P_TDD DIFFERENTIAL_PAIR=P_KP2
MIN_LINE_WIDTH=0.25MM MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PROC_DIFF NET_SPACING_TYPE=PROC_DIFF
NET_PHYSICAL_TYPE=PROC_DIFF NET_PHYSICAL_TYPE=PROC_DIFF
CPU POWER AND BYPASS
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 48 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
y
56 55 52 50 48 43 =PPVCORE_CPU
r
1 C4922 1 C4921 1 C4920 1 C4919 1 C4918 1 C4917 1 C4916 1 C4915 1 C4912 1 C4900
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402
1 C4993 1 C4968 1 C4961 1 C4959 1 C4935 1 C4932 1 C4926 1 C4924 1 C4945 1 C4923
a
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
1 C4994 1 C4969 1 C4964 1 C4960 1 C4936 1 C4933 1 C4927 1 C4925 1 C4956 1 C4934
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
n
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402
C4995 C4971 C4965 C4962 C4939 C4937 C4930 C4928 C4989 C4967
i
1 1 1 1 1 1 1 1 1 1
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
C CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402 C
1 C4996 1 C4970 1 C4966 1 C4963 1 C4940 1 C4938 1 C4931 1 C4929 1 C4901 1 C4978
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402
m
1 C4997 1 C4982 1 C4976 1 C4972 1 C4952 1 C4950 1 C4943 1 C4941 1 C4906 1 C4904
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
il
1 C4998 1 C4981 1 C4977 1 C4973 1 C4953 1 C4951 1 C4944 1 C4942 1 C4907 1 C4905
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402
1 C4999 1 C4984 1 C4979 1 C4974 1 C4957 1 C4954 1 C4948 1 C4946 1 C4910 1 C4908
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
e
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
402 402 402 402 402 402 402 402 402 402
1 C4902 1 C4983 1 C4980 1 C4975 1 C4958 1 C4955 1 C4949 1 C4947 1 C4911 1 C4909
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
B B
r
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402
1 C4903 1 C4992 1 C4991 1 C4990 1 C4988 1 C4987 1 C4986 1 C4985 1 C4914 1 C4913
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
A
P PROC DECOUPLING
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
A
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 49 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
55 7 =PP12V_CPU
TABLE_5_HEAD
VCORE SUPPLY PHASE 1 (GD1)
1
VCORE VOLTAGE CONTROLLER (VC) R5029 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION C5010 55 50 PP12V_CPU_R_L
10 TABLE_5_ITEM
1UF
5% 128S0078 2 EL CAP,330UF,20%,16V C5011,C5035 1 2
1/16W 50 GD1_BST_R
M23/M33: PP12V_CPU IS AN ALL RAIL MF-LF SYMBOL NOT READY FOR DVT2 RELEASE
2 402 20% CRITICAL
16V 1 OMIT 1 OMIT 1
VC_VCC 50 CERM C5011 C5035 C5012
50 GD1_DRN 1206 330UF 330UF 10UF
10%
20% 20% 16V
CRITICAL 2 16V 2 16V 2 CERM
SYS_POWERUP_L
1 C5019 ELEC
SM-3
ELEC
SM-3 1210
6 7 12 28 85
1UF
20% 55 50 PP12V_CPU_R_L U5010 4
2 16V SC1211
7
CERM 6 VIN SOIC-LF
R5000 1206 BG 8
50 6 VC_AGND
D VRM_EN 1
1.5K 2
50 VC_BGOUT 2
BGOUT
VCC
OUTSEN
19 VC_OUTSEN 50 50 VC_OUT1 4 CO VREG 7
D CRITICAL
Q5010 =PPVCORE_CPU 43 48 49 50 52 55
D
Q5012 3
5%
1 C5001 VC_OSCREF 15 OSCREF OUT1 17 VC_OUT1 1 DRN TG 2 GD1_TG 1 G IRLR7821PBF 56
1/16W 50 50
C5029 R5007 50
y
2N7002 MF-LF
1UF CRITICAL 1
S
TO-252AA
SOT23-LF D 402 OUT2 18 VC_OUT2 R5030 1UF 4.7
10%
6.3V
2 CERM
50 31 CPU_VID_R<0> 12 VID0 U5000 50
PGOOD IS OC 0 20%
1 2 50 GD1_BST 3 BST VPN 5 1
R5050 CRITICAL
1 G S 402 50 31 CPU_VID_R<1> 11 VID1 PGOOD 14 VC_PGOOD 1 2 SYS_SLEWING_L 24 26 28 2 16V
CERM
5%
1/10W
THMPAD 10K 3 L5010
50 31 CPU_VID_R<2> 10 VID2 SC2642 5% 1206 MF-LF 9 5%
1/16W
0.36UH-30A-0.80MOHM
ERROUT 3 1/16W 603 MF-LF
GD1_PN
2 50 31 CPU_VID_R<3> 9 VID3 MF-LF 3
R5010 2 402
50 1 2 PPVCORE_CPU 6 50
r
TSSOP 402
50 31 CPU_VID_R<4> 8 VID4 NOSTUFF D5010
BAS16-75V-0.25A 1
1 2
SM MAKE_BASE=TRUE
CPU_VID_R<5> 1 CRITICAL
50 31 13 VID5
R5003 1
SOT23-LF
5% C5018 1
C5017 1
C5032
2.7M 2 1/16W 4 1
R5011 330UF 330UF 1500UF
50 VC_DACSTEP 6 DACSTEP 50 VC_ERROUT 1 VC_VCC 50 50 GD1_VREG MF-LF 20% 20% 20%
402 1.0 2 2.5V-ESR9V 2 2.5V-ESR9V 2 6.3V
1
5% 50 GD1_VPN D 5% POLY POLY ELEC
50 6 VC_AGND 5
FB R5001 1/10W
MF-LF CRITICAL 1/4W CASE-D2E-LF CASE-D2E-LF TH-MCZ
4
GSENSE
20K 603
1
Q5011 MF-LF
2 1206
5%
1/16W R5012 50 GD1_BG 1 G IRLR7843PBF
a
4
50 VC_OS1 1 OS1 MF-LF NOSTUFF 200 S
TO-252AA
2 402 1 5% 50 GD1_FET_RC
50 VC_OS2 20 OS2 R5002 1/16W
MF-LF D CRITICAL
1
C5038
AGND 50 VC_ERROUT_RC
5%
0 1 C5013 2 402 3
Q5013 330UF
20%
16
1 C5000 1
R5028 1 C5002 1/16W
MF-LF
1UF
20% 1 G IRLR7843PBF 2 2.5V-ESR9V
POLY
0.1UF 221K 470PF 16V VC_AUX1 TO-252AA C5016 CASE-D2E-LF
2 402 2 CERM
20%
2 10V
1%
1/16W
10%
50V
2 CERM 1206
50
1 C5015 S
3300PF
CERM
402
MF-LF
402 OMIT 0.0022UF 10%
50V
2 402 10% 3
XW5000 1 C5014 2 50V
CERM
CERM
603
n
SM 470PF 402 NEED TO CHANGE TO 10MOHM CAPS - 8 PCS
1 2 10%
50V
2 CERM
VC_AGND 6 50 402
i
50 GD1_PN
VC_AUX1 50 VC_AUX2 50
C 1
R5013 1
R5016 VCORE SUPPLY PHASE 2 (GD2) C
20.5K 20.5K VCORE_SENSE_GND 50
C5020
1% 1% 55 50 PP12V_CPU_R_L
1/16W 1/16W 1UF
MF-LF MF-LF DIFFERENTIAL PAIR 1 2
2 402 2 402 FOR REMOTE SENSE
50 GD2_BST_R
NOSTUFF NOSTUFF VCORE_SENSE_VOUT 50
20%
16V
1
C5021 1 C5022
CERM 1000UF 10UF
1 C5004 1 1 1206
0.01UF
R5014 1 C5005 R5015 50 GD2_DRN
2
20%
16V
10%
16V
2 CERM
10%
20.5K 0.01UF20.5K CRITICAL ELEC
1210
m
1% 1% TH-KZJ-LF
2
16V
1/16W 10% 1/16W VC_OUTSEN
CERM
402 MF-LF 16V
2 CERM MF-LF
50
PP12V_CPU_R_L U5020
2 402 402 2 402 55 50
SC1211 4
6 VIN SOIC-LF BG 8
D
il
CRITICAL
VC_OUT2 4 CO VREG 7
R5005 R5004
50
Q5020
4.99K2 261 1 DRN TG 2 GD2_TG 1 G IRLR7821PBF
50 VC_VCC 1 50 VC_OS_HUB 1 2 R5006 50
S
TO-252AA
4.7 3 BST
1%
C5008 1% 1 50 2 GD2_BST VPN 5 1 CRITICAL
1/16W 1/16W R5051
MF-LF
402
0.33UF MF-LF
402
1 C5030 5%
1/10W
THMPAD 3 L5020
1 2 1UF MF-LF 9
10K
5%
0.36UH-30A-0.80MOHM
20% 603 1/16W
16V GD2_PN 1 2 PPVCORE_CPU
10% NOSTUFF
2 CERM 3
R5020 MF-LF
2 402
50 6 50
6.3V
CERM-X5R R5026 1206
D5020
BAS16-75V-0.25A 1
1 2
SM
402 301 1 CRITICAL 1 1
1 2 1
SOT23-LF
5% C5028 C5033 C5040
1/16W 4 1800UF 1800UF 1500UF
e
1% 50 GD2_VREG MF-LF
1
20% 20% 20%
AVP ADJUSTMENT NOSTUFF
1/16W
MF-LF 1
R5024 50 GD2_VPN
402
D
R5021 2 6.3V
ELEC
2 6.3V
ELEC
2 6.3V
ELEC
402 CRITICAL 1.0 TH-KZJ-LF TH-KZJ-LF TH-MCZ
330
5% 1
Q5021 5%
1/4W
NOSTUFF 1/16W
MF-LF R5022 50 GD2_BG1 G IRLR7843PBF MF-LF
2 1206
R5025 2 402
200 TO-252AA 4
B S
B
r
5%
1K 1/16W 50 GD2_FET_RC 1 CRITICAL
1 2 50 VC_OS_HUB_RC
1 C5023 MF-LF
2 402 3 D CRITICAL C5041 1
C5042
5% 330UF 330UF
1/16W
MF-LF
1UF
20%
Q5023 20% 20%
2 2.5V-ESR9V 2 2.5V-ESR9V
402 2 16V 50 VC_AUX2 1 G IRLR7843PBF POLY POLY
PCB:PLACE R5025 CLOSE TO INDUCTOR OUTPUT LEAD. CERM
1206 1 C5025 S
TO-252AA C5026 CASE-D2E-LF CASE-D2E-LF
NOSTUFF 3300PF
0.0022UF 10%
C5009 1 C5024 10% 3
50V
0.015UF 470PF 2 50V
CERM
CERM
603
1 2 10% 402
OMIT PHYSICAL CONSTRAINTS 2 50V NEED TO CHANGE TO 10MOHM CAPS - 8 PCS
P
CERM
R5027 10% 16V
X7R 402
XW5002
SM
402
1.5K 2 50 GD2_PN
1 50 6 VC_OUTSEN_R 1 2 =PPVCORE_CPU 43 48 49 50 52 55 56
1% PCB:CONNECT BETWEEN THE INDUCTOR & BULK CAPS.
VC PROCESSOR VOLTAGE SENSING 1/16W
MF-LF MIN_LINE_WIDTH MIN_NECK_WIDTH
402
CHOICE OF: VC_OSCREF 0.25 MM 0.20 MM
50 I375
1) VCORE PLANE SENSING
2) KELVIN POINT SENSING R5035 50 31
CPU_VID_R<0..5> 0.25 MM 0.20 MM I377
PPVCORE_CPU 1
0 2 VCORE_SENSE_VOUT 50 50
VC_DACSTEP 0.25 MM 0.20 MM I376
50 6
MIN_NECK_WIDTH=0.20MM 50 6
VC_AGND 0.50 MM 0.20 MM
MIN_LINE_WIDTH=0.50MM
UNDER PROCESSOR
R5036 5%
1/16W VC_BGOUT 0.25 MM 0.20 MM
I378
0 MF-LF 50 I380
1 2 402 VCORE_SENSE_GND 50
50
VC_OS1 0.25 MM 0.20 MM I379
5% 50
VC_OS2 0.25 MM 0.20 MM
1/16W I382
MF-LF NOSTUFF VC_VCC 0.25 MM 0.25 MM
50
402
R5041 VC_OS_HUB 0.25 MM 0.20 MM
I381
0 50 I383
55 48 6 KPVDD2 1 2
50
VC_OUTSEN 0.25 MM 0.20 MM I384
NOSTUFF
CPU SENSE SIDE R5042
5%
1/16W
MF-LF
50 6
VC_OUTSEN_R
VCORE_SENSE_GND
0.25
0.25
MM
MM
0.20
0.20
MM
MM
I385 CPU VCORE VREG
KPGND2 0 402 50 I386
1 2 VCORE_SENSE_VOUT 0.25 MM 0.20 MM
A 55 48 6
5%
1/16W
50
50
VC_AUX1 0.25 MM 0.25 MM
I387
I388
SYNC_MASTER=M33-HS
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=06/20/2005
A
MF-LF 50
VC_AUX2 0.25 MM 0.25 MM
402 I392
MIN_LINE_WIDTH MIN_NECK_WIDTH MIN_LINE_WIDTH MIN_NECK_WIDTH 50
VC_OUT1 0.45 MM 0.25 MM I391
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
50
GD1_DRN 0.25 MM 0.25 MM I432 50
GD2_DRN 0.25 MM 0.25 MM I400 50
VC_OUT2 0.45 MM 0.25 MM AGREES TO THE FOLLOWING
I390
50
GD1_BST 0.25 MM 0.25 MM I433 50
GD2_BST 0.25 MM 0.25 MM I401 50
VC_ERROUT 0.25 MM 0.20 MM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
I389
50
GD1_VREG 0.25 MM 0.25 MM I434 50
GD2_VREG 0.25 MM 0.25 MM I402 50
VC_ERROUT_RC 0.25 MM 0.20 MM I393
II NOT TO REPRODUCE OR COPY IT
50
GD1_VPN 0.25 MM 0.25 MM 50
GD2_VPN 0.25 MM 0.25 MM 50
VC_OS_HUB_RC 0.25 MM 0.20 MM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I436 I404 I397
50
GD1_TG 0.25 MM 0.25 MM I435 50
GD2_TG 0.25 MM 0.25 MM I403 SIZE DRAWING NUMBER REV.
GD1_BG 0.25 MM 0.25 MM GD2_BG 0.25 MM 0.25 MM
50
50
GD1_FET_RC 0.25 MM 0.25 MM
I438
I437
50
50
GD2_FET_RC 0.25 MM 0.25 MM
I406
I405
D 051-6863 19
GD1_PN 0.60 MM 0.25 MM GD2_PN 0.60 MM 0.25 MM APPLE COMPUTER INC.
50 I439 50 I407 SCALE SHT OF
50
GD1_BST_R 0.25 MM 0.25 MM I440 50
GD2_BST_R 0.25 MM 0.25 MM I408 NONE 50 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
56 55 50 49 48 43 =PPVCORE_CPU
y
CRITICAL
1 C5200 1 C5212 1 C5223 1 C5234 1 C5245 1 C5201 1 C5289 1 C5278 1 C5267 1 C5256
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
r
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805 805 805 805 805 805 805
1 C5213 1 C5211 1 C5210 1 C5209 1 C5208 1 C5207 1 C5206 1 C5205 1 C5204 1 C5203
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
805 805 805 805 805 805 805 805 805 805
a
1 C5224 1 C5222 1 C5221 1 C5220 1 C5219 1 C5218 1 C5217 1 C5216 1 C5215 1 C5214
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805 805 805 805 805 805 805
n
1 C5235 1 C5233 1 C5232 1 C5231 1 C5230 1 C5229 1 C5228 1 C5227 1 C5226 1 C5225
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
805 805 805 805 805 805 805 805 805 805
i
C 1 C5246
10UF
1 C5244
10UF
1 C5243
10UF
1 C5242
10UF
1 C5241
10UF
1 C5240
10UF
1 C5239
10UF
1 C5238
10UF
1 C5237
10UF
1 C5236
10UF
C
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805 805 805 805 805 805 805
1 C5257 1 C5255 1 C5254 1 C5253 1 C5252 1 C5251 1 C5250 1 C5249 1 C5248 1 C5247
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
m
805 805 805 805 805 805 805 805 805 805
1 C5268 1 C5266 1 C5265 1 C5264 1 C5263 1 C5262 1 C5261 1 C5260 1 C5259 1 C5258
il
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805 805 805 805 805 805 805
1 C5279 1 C5277 1 C5276 1 C5275 1 C5274 1 C5273 1 C5272 1 C5271 1 C5270 1 C5269
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
805 805 805 805 805 805 805 805 805 805
e
1 C5290 1 C5288 1 C5287 1 C5286 1 C5285 1 C5284 1 C5283 1 C5282 1 C5281 1 C5280
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805 805 805 805 805 805 805
B B
r
1 C5202 1 C5299 1 C5298 1 C5297 1 C5296 1 C5295 1 C5294 1 C5293 1 C5292 1 C5291
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
805 805 805 805 805 805 805 805 805 805
A
P CPU VCORE MORE BYPASS
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
A
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 52 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROCESSOR AVDD VREG
CRITICAL
U5470
MM1572JN PPV_RUN_AVDD_CPU 48
55 7 =PP3V3_RUN_CPU SOT-25A-LF MIN_LINE_WIDTH=0.60MM
D 1 VIN VOUT 5
MIN_NECK_WIDTH=0.25MM
VOLTAGE=2.8V
MAKE_BASE=TRUE
D
y
3 CONT NOISE 4 55 AVDDVC_NOISE
1 C5470 1R5470
1UF 10K GND C5471 1 1 C5472
10% 5%
6.3V 2 0.01UF 10UF
2 CERM 1/16W 20% 20%
402 MF-LF 16V
2 402 CERM 2 2 6.3V
CERM
402 805-1
r
55 AVDDVB_CONT
3
D Q5470
2N7002
SOT23-LF
11 SYS_SLEEP
30 26 16 15 13 12
1 G S
ZH5400 ZH5418 ZH5436 ZH5454
a
2 HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5401 ZH5419 ZH5437 ZH5455
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5402 ZH5420 ZH5438 ZH5456
n
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5403 ZH5421 ZH5439 ZH5457
i
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
C ZH5404 ZH5422 ZH5440 ZH5458 C
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5405 ZH5423 ZH5441 ZH5459
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5406 ZH5424 ZH5442 ZH5460
m
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5407 ZH5425 ZH5443 ZH5461
il
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5408 ZH5426 ZH5444 ZH5462
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5409 ZH5427 ZH5445 ZH5463
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5410 ZH5428 ZH5446 ZH5464
e
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5411 ZH5429 ZH5447 ZH5465
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
B B
r
1 1 1 1
ZH5412 ZH5430 ZH5448 ZH5466
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5413 ZH5431 ZH5449 ZH5467
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
P
ZH5414 ZH5432 ZH5450 ZH5468
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5415 ZH5433 ZH5451 ZH5469
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5416 ZH5434 ZH5452 ZH5470
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
ZH5417 ZH5435 ZH5453 ZH5471
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA
1 1 1 1
CPU AVDD VREG
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 54 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROCESSOR TEMP SENSE (TDIODE EXCITATION CIRCUIT AND OPAMP) PROCESSOR VCORE VOLTAGE SENSE 2.5V PRECISION VOLTAGE REFERENCE SOURCE
CHOICE OF SMU SENSING TDIODE CIRCUIT ALWAYS POWERED
R5560 55 50 7
=PP12V_CPU 1) VCORE PLANE TO ASSIST DIODECAL
2 OPTION 3 2) PROC KELVIN POINT 3.3 MS TIME CONSTANT
PP3V3_CPU_DIODE 1 2 PP3V3_OPAMP 1 3) 12V RAIL SO SMU ADC SAMPLING =PP3V3_ALL_CPU 7 =PP3V3_PWRON_CPU
55
5%
VOLTAGE=3.3V
55
R5540 WORKS WELL. NOSTUFF
7
10K
1/10W
MF-LF
1 C5561 OPTION 1 1% 1
R5550 1
OMIT 603 2.2UF
20% PCB: PLACE R5560,C5561 NEAR U5500 PIN 4 NOSTUFF 1/16W
MF-LF 0 DS5550
SOD-123
XW5560
SM
10V
2 CERM R5541 2 402 TO SMU 5%
1/10W B0530WXF
805 =PPVCORE_CPU 100K 2 CPU_SENSE_V MF-LF
1 2 DAGND 6 55 56 52 50 49 48 43 1 28 55
2 603
2
VOLTAGE=0V 5%
1
1/16W
MF-LF R5542 1 C5540 PCB: PLACE C5540 NEXT TO SMU 55 PP3V3_CPU_DIODE
2.0K
D R5511
DAGND 402
1%
1/16W
1UF
10%
2 6.3V =PPVREF_SMU 1
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=3.3V D
20.0K2
MF-LF
2 402
CERM
402
28
R5551
PP2V5_VREF 63.4
y
55 1 TD0_<2> 55 11 CRITICAL SCALE (12V) COUNT GND_SMU_AVSS
0.1%
3 U5500 R5502 6 V/V .01464 V/COUNT 6 28 55 1%
1/10W
1/16W 11 MF-LF
MF-LF 1 55 TD0_CURRENT 112.7K2 5 U5500 ADC IS 10BIT 0 TO 1023 DEVELOPMENT 2 603
603 0 TO 2.5V PP2V5_VREF
R5501 2 TSSOP-LF
1%
1/10W 7 55 TD0_BUFFERED C5541 55
MIN_LINE_WIDTH=0.25MM
DAGND 10.0K2 4 LVM2014MTX MF-LF 15PF MIN_NECK_WIDTH=0.20MM
r
5566 1 603 VOLTAGE=2.5V
55 6 1 2 MAKE_BASE=TRUE
TSSOP-LF
0.1%
1/16W
R5500 4 LVM2014MTX 1
R5504 OPTION 2
6
MF-LF 10.0K2 5% NOSTUFF
603
55 TD0_<1> 1 10.0K R5544 50V VREF
0.1% CERM 1
0.1%
1/16W
1/16W
1
10.0K2 402 R5543 CRITICAL
ADJ 5 NC_NCV1009_ADJ
MF-LF
MF-LF 3.3K U5550 6
2 603 DEVELOPMENT 5%
603
R5545
0.1%
1/16W 1/16W
MF-LF
NCV1009D
SO-8-LF 1
1 C5551
PP3V3_OPAMP 10.0K2
MF-LF NC1 NC_NCV1009_1 6 2.2UF
KPGND2 603 2 402 2 20%
a
1
55
R5512 55 50 48 6 1
11
NC2
3
NC_NCV1009_2 6 2 10V
CERM
20.0K 0.1%
1/16W
55 9 KP_V<1> 13 LVM2014MTX NC3 NC_NCV1009_3 6 805
100UA CURRENT SOURCE 0.1% TSSOP-LF 7
1/16W MF-LF NC4 NC_NCV1009_4 6
MF-LF 603 14 55
9 CPU_SENSE_KP_V 8
2 603 DEVELOPMENT NC5 NC_NCV1009_5 6
KP_V<2> 12
R5546 55 9
4
U5500 GND
KPVDD2 1
10.0K2 4
55 50 48 6
PP2V5_VREF 55 0.1% DAGND
n
1/16W
MF-LF R5547 6 55
603
1
10.0K2
1 1
R5509 R5526 DAGND 6 55
40.2K 100K 0.1%
1/16W C5542
i
0.1% 0.1% MF-LF 15PF
1/16W 1/16W 603
MF-LF MF-LF 1 2
2 603 2 603 C5505 PHYSICAL CONSTRAINTS C
C 0.01uF
1 2 DAGND 6 55
5% DEVELOPMENT
50V
CERM
402
10% MIN_LINE_WIDTH MIN_NECK_WIDTH
55 48 6
CPU_DIODE_POS 16V TD0_<1..4> 0.25 MM 0.25 MM
CERM 55 I325
402 PP12V_CPU_R 0.60 MM 0.25 MM
55 I376
55
TD0_CURRENT 0.25 MM 0.25 MM
FROM CPU 1 C5502 1 C5501 PCB: PLACE R5530 AND C5530
NEXT TO SMU. 55
TD0_BUFFERED 0.25 MM 0.25 MM
I323
0.0022UF 0.0022UF I321
10% 10% 55 9
KP_V<1..2> 0.25 MM 0.25 MM I355
2 50V 2 50V CPU_SENSE_KP_V 0.25 MM 0.25 MM
m
CERM CERM 55 9
402 402 R5505 11 PP3V3_OPAMP 0.60 MM 0.25 MM
I356
CPU_DIODE_NEG 10.0K2 TD0_<4> 10 U5500 TO SMU 55 I375
55 48 6 1 55
R5530 55 6
INA138_OUT 0.25 MM 0.25 MM
CRITICAL I357
0.1% CPU_TEMP_R 100K 2 CPU_TEMP 28 55 CPU_SENSE_I_R 0.25 MM 0.25 MM
il
8 55 55
1
R5510
1/16W
MF-LF R5507 1
CPU_SENSE_I 0.25 MM 0.25 MM
I360
603 40.2K2 5% 55 28 I359
0 1 9 TSSOP-LF
LVM2014MTX
1/16W
55 28
CPU_SENSE_V 0.25 MM 0.25 MM
5% 4 MF-LF I361
1/16W 0.1% 402 3.3 MS TIME CONSTANT 55 28
CPU_TEMP 0.25 MM 0.20 MM
MF-LF
2 402
1/16W
MF-LF R5506 1 C5530 SO SMU ADC SAMPLING CPU_TEMP_R 0.25 MM 0.20 MM
I362
603 100K 2 WORKS WELL.
55 I370
1 1UF 54
AVDDVC_NOISE 0.25 MM 0.20 MM I380
10%
0.1%
C5500 6.3V
2 CERM 54
AVDDVB_CONT 0.25 MM 0.20 MM
R5503 1/16W
MF-LF 0.01uF 402 PP12V_CPU_R 0.60 MM 0.25 MM
I381
10.0K2 TD0_<3>
603
1 2
55 I382
1 55
GND_SMU_AVSS 6 28 55 55 6
DAGND 0.60 MM 0.25 MM I385
0.1%
1/16W 10%
MF-LF 16V
CERM
e
603
PCB: PLACE R5510, C5501 NEAR 402
PROCESSOR. PLACE C5502 NEAR OPAMP
MAKE A GROUND LOOP AROUND DAGND 6 55
TDIODE_PAIR FROM PROCESSOR
B B
r
PROCESSOR VCORE CURRENT SENSE
FMAX CONNECTOR (USING 12V INPUT CURRENT TO DERIVE CPU CURRENT)
PLACE CLOSE
CRITICAL
TO U4300 PP12V_CPU_R_L 50
L5570
1UH-20A-4.5MOHM R5570 VOLTAGE=12V
MIN_LINE_WIDTH=0.60MM
=PP12V_CPU 1 55 2 PP12V_CPU_R 0.0252
1
MIN_NECK_WIDTH=0.25MM
R5522 0 NOSTUFF
KPVDD26 48 50 55
55 50 7
TH-VERT-LF VOLTAGE=12V
P
NOSTUFF 6 KPVDD2_FMAX 1 2 1%
1W PCB:KEEP SHORTS NEXT TO U55700
J5500 DIFFERENTIAL_PAIR=KP2_FMAX
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM
5% MF
2512-1 PCB:PLACE D5570,R5572,C5570 BY SMU
BM12B-SRSS-TB NET_SPACING_TYPE=PROC_DIFF
NET_PHYSICAL_TYPE=PROC_DIFF
1/16W
MF-LF
F-ST-SM
14 R5523 402
0 NOSTUFF
KPGND2 6 48 50 55 OMIT
6 KPGND2_FMAX 1 2 =PP3V3_RUN_CPU
DIFFERENTIAL_PAIR=KP2_FMAX
MIN_LINE_WIDTH=0.25MM 5%
XW5570
SM
7 54
1 MIN_NECK_WIDTH=0.20MM 3 4
NET_SPACING_TYPE=PROC_DIFF
1/16W
MF-LF 55 6 INA138_OUT 1 2 CORE_ISNS_P 3 NOSTUFF
6 55
2 NET_PHYSICAL_TYPE=PROC_DIFF
402 VIN+ VIN- D5570
R5524 0 NOSTUFF CPU_DIODE_POS 6 48 55 OMIT
BAS16-75V-0.25A TO SMU
3 6 TDIODE_POS_FMAX
DIFFERENTIAL_PAIR=TDIODE
1 2 U5570 XW5571 R5572 1
SOT23-LF
4 MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM
5% INA138 SM
100K 2
5 NET_SPACING_TYPE=PROC_DIFF
NET_PHYSICAL_TYPE=PROC_DIFF
1/16W
MF-LF 5 V+
SOT23-5-LF
OUT 1 1 2 55 CPU_SENSE_I_R 1 CPU_SENSE_I28 55
402
6 R5525 0 NOSTUFF
CPU_DIODE_NEG CRITICAL 5% 3.3 MS TIME CONSTANT
6 TDIODE_NEG_FMAX 1 2 6 48 55 1/16W
7 DIFFERENTIAL_PAIR=TDIODE MF-LF SO SMU ADC SAMPLING
8
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM
5%
1/16W
SCALE COUNT
.00675 A/COUNT
1
R5571 402 1 C5570 WORKS WELL.
NET_SPACING_TYPE=PROC_DIFF
NET_PHYSICAL_TYPE=PROC_DIFF MF-LF
2.73224 A/V GND 73.2K 1UF
9 402 1% 10%
ADC IS 10BIT 0 TO 1023 2 6.3V
10 1/16W 2 CERM
CORE_ISNS_M 6 55 0 TO 2.5V MF-LF 402
11 DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=0.25MM 2 402
12
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PROC_DIFF
NET_PHYSICAL_TYPE=PROC_DIFF
XW5572
OMIT GND_SMU_AVSS 6 28 55
T,V,I SENSORS
SM
A 13
CORE_ISNS_P
DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM
6 55
1 2 CORE_ISNS_M 6 55
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/29/2005
A
NET_SPACING_TYPE=PROC_DIFF
NET_PHYSICAL_TYPE=PROC_DIFF
NOSTUFF R5520 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
51 CPU_TEMP_R 55 AGREES TO THE FOLLOWING
6 FMAXT_P 1 2
DIFFERENTIAL_PAIR=P_FMAXT I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NET_SPACING_TYPE=PROC_DIFF 5%
NET_PHYSICAL_TYPE=PROC_DIFF 1/16W
MIN_LINE_WIDTH=0.20 MM II NOT TO REPRODUCE OR COPY IT
MIN_NECK_WIDTH=0.20 MM MF-LF
402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
NOSTUFF R5521
51 DAGND 6 55 SIZE DRAWING NUMBER REV.
6 FMAXT_M 1 2
DIFFERENTIAL_PAIR=P_FMAXT
NET_SPACING_TYPE=PROC_DIFF
NET_PHYSICAL_TYPE=PROC_DIFF
MIN_LINE_WIDTH=0.20 MM
5%
1/16W
APPLE COMPUTER INC.
D 051-6863 19
MIN_NECK_WIDTH=0.20 MM MF-LF
402 SCALE SHT OF
NONE 55 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CONNECT PULSAR CLKS TO CPU/NB EI BUS AND SYSCLK CONSTRAINT LABELS
56 43 9 EI_CPU_SYSCLK_P EI_CPU_A_SYSCLK_P 26 ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE NET_PHYSICAL_TYPE DIFFERENTIAL_PAIR
MAKE_BASE=TRUE
56 43 EI_CPU_SYSCLK_N EI_CPU_A_SYSCLK_N 26
MAKE_BASE=TRUE 56 43 9
EI_CPU_TO_NB_CLK_P EICNCLK EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK
I28
56 43 EI_CPU_APSYNC CPU_A_APSYNC 26
MAKE_BASE=TRUE 56 43 9
EI_CPU_TO_NB_CLK_N EICNCLK EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK
I27
EI_CPU_TBEN_CLK CPU_A_TBEN_CLK_US
43
MAKE_BASE=TRUE
26
56 43
EI_CPU_TO_NB_AD<0..21> EICNCAD EI_CPU_TO_NB_AD EI_CPU_TO_NB_AD
I31
56 EI_NB_APSYNC NB_APSYNC 26 42
MAKE_BASE=TRUE 56 43 9
EI_CPU_TO_NB_SR_P<0..1> EICNCSR EI_CPU_TO_NB_AD EI_CPU_TO_NB_AD
I34
EI_CPU_TO_NB_SR_N<0..1> EI_CPU_TO_NB_AD EI_CPU_TO_NB_AD
D CONNECT KODIAK EI A TO/FROM CPU
56 43 9
EI_NB_TO_CPU_CLK_P
EICNCSR
EINCCLK EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK
I32
D
56 43 9 I29
EI_NB_TO_CPU_CLK_N EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK
y
EI_NB_TO_CPU_CLK_P EI_NB_TO_CPU_A_CLK_P 56 43 9 EINCCLK I30
56 43 9 42
EI_NB_TO_CPU_AD<0..43> EINCCAD EI_NB_TO_CPU_AD EI_NB_TO_CPU_AD
56 43 9
EI_NB_TO_CPU_CLK_N MAKE_BASE=TRUE
EI_NB_TO_CPU_A_CLK_N 42
56 43 I35
EI_NB_TO_CPU_SR_P<0..1> EINCCAD EI_NB_TO_CPU_AD EI_NB_TO_CPU_AD
56 43
EI_NB_TO_CPU_AD<0..43> MAKE_BASE=TRUE EI_NB_TO_CPU_A_AD<0..43> 42 56 43 9 I36
EI_NB_TO_CPU_SR_P<0..1> MAKE_BASE=TRUE EI_NB_TO_CPU_A_SR_P<0..1> 42 56 43 9
EI_NB_TO_CPU_SR_N<0..1> EINCCAD EI_NB_TO_CPU_AD EI_NB_TO_CPU_AD I37
56 43 9
EI_NB_TO_CPU_SR_N<0..1> MAKE_BASE=TRUE EI_NB_TO_CPU_A_SR_N<0..1> 42
r
56 43 9
MAKE_BASE=TRUE EI_NB_TO_CPU_AD
56 EI_NB_APSYNC EIPNAPSYNC EI_NB_TO_CPU_AD
I33
56 43 9
EI_CPU_TO_NB_CLK_P EI_CPU_A_TO_NB_CLK_P 42 EI_CPU_APSYNC EIPCAPSYNC EI_NB_TO_CPU_AD EI_NB_TO_CPU_AD
56 43 I38
MAKE_BASE=TRUE
56 43 9
EI_CPU_TO_NB_CLK_N EI_CPU_A_TO_NB_CLK_N 42 EI_CPU_SYSCLK_P EI_NB_TO_CPU_CLK EI_CPU_SYSCLK
EIPCSYSCLK EI_NB_TO_CPU_CLK
56 43
EI_CPU_TO_NB_AD<0..43> MAKE_BASE=TRUE EI_CPU_A_TO_NB_AD<0..43> 42 56 43 9
EI_CPU_SYSCLK_N EI_NB_TO_CPU_CLK EI_CPU_SYSCLK
I40
56 43 EIPCSYSCLK EI_NB_TO_CPU_CLK
EI_CPU_TO_NB_SR_P<0..1> MAKE_BASE=TRUE
EI_CPU_A_TO_NB_SR_P<0..1> 42 I41
56 43 9
EI_NB_SYSCLK_P EIPNSYSCLK_P EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK EI_NB_SYSCLK
EI_CPU_TO_NB_SR_N<0..1> MAKE_BASE=TRUE EI_CPU_A_TO_NB_SR_N<0..1> 42 42 26 I39
56 43 9
MAKE_BASE=TRUE 42 26
EI_NB_SYSCLK_N EIPNSYSCLK_N EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK EI_NB_SYSCLK
I42
a
56 43
EI_CPU_TO_NB_AD<22> EICNCAD_PP EI_CPU_TO_NB_AD EI_CPU_TO_NB_AD
CONNECT CPU TO KODIAK QREQ A0 I195
EI_CPU_TO_NB_AD<23..43> EICNCAD EI_CPU_TO_NB_AD EI_CPU_TO_NB_AD
43
CPU_TO_NB_QREQ_L CPU_A0_TO_NB_QREQ_L 42
56 43 I196
MAKE_BASE=TRUE
CONNECT CPU TO KODIAK QACK A0, NC OTHERWISE
43
CPU_QACK_L CPU_A0_QACK_L 42
NC_CPU_A1_QACK_L CPU_A1_QACK_L
n
MAKE_BASE=TRUE
6 42
6
NC_CPU_B0_QACK_L MAKE_BASE=TRUE CPU_B0_QACK_L 44
6
NC_CPU_B1_QACK_L MAKE_BASE=TRUE CPU_B1_QACK_L 44
MAKE_BASE=TRUE
i
CONNECT CPU TO KODIAK/SHASTA INT A0, NC OTHERWISE NC KODIAK EI B OUTPUT PORT NC KODIAK EI B INPUT PORT
NC_EI_NB_TO_CPU_B_CLK_P EI_NB_TO_CPU_B_CLK_P NC_EI_CPU_B_TO_NB_CLK_P EI_CPU_B_TO_NB_CLK_P
C 43
CPU_INT_L
MAKE_BASE=TRUE
CPU_A0_INT_R_L 24 56 6
6
NC_EI_NB_TO_CPU_B_CLK_N MAKE_BASE=TRUE EI_NB_TO_CPU_B_CLK_N
44
44
6
6
NC_EI_CPU_B_TO_NB_CLK_N MAKE_BASE=TRUE EI_CPU_B_TO_NB_CLK_N
44
44
C
6
NC_NB_CPU_A1_INT_L NB_CPU_A1_INT_L 42 NC_EI_NB_TO_CPU_B_AD<0..43> MAKE_BASE=TRUE EI_NB_TO_CPU_B_AD<0..43> 44 NC_EI_CPU_B_TO_NB_AD<0..43> MAKE_BASE=TRUE EI_CPU_B_TO_NB_AD<0..43> 44
6 6
6
NC_NB_CPU_B0_INT_L MAKE_BASE=TRUE
NB_CPU_B0_INT_L 44 NC_EI_NB_TO_CPU_B_SR_P<0..1> MAKE_BASE=TRUE EI_NB_TO_CPU_B_SR_P<0..1> 44 NC_EI_CPU_B_TO_NB_SR_P<0..1> MAKE_BASE=TRUE
EI_CPU_B_TO_NB_SR_P<0..1> 44
6 6
6
NC_NB_CPU_B1_INT_L MAKE_BASE=TRUE NB_CPU_B1_INT_L 44 NC_EI_NB_TO_CPU_B_SR_N<0..1> MAKE_BASE=TRUE
EI_NB_TO_CPU_B_SR_N<0..1> 44 NC_EI_CPU_B_TO_NB_SR_N<0..1> MAKE_BASE=TRUE
EI_CPU_B_TO_NB_SR_N<0..1> 44
MAKE_BASE=TRUE 6 6
MAKE_BASE=TRUE MAKE_BASE=TRUE
CONNECT CPU TO SHASTA SRESET A0, NC OTHERWISE
CPU_SRESET_L_R SB_CPU_A0_SRESET_L 24 56
NOTUSED_CPU_A1_SRESET_L MAKE_BASE=TRUE SB_CPU_A1_SRESET_L PULLUPS FOR SRESET’S FROM SHASTA
m
24 56
NOTUSED_CPU_B0_SRESET_L MAKE_BASE=TRUE SB_CPU_B0_SRESET_L 24 56
=PP3V3_PWRON_SB NOSTUFF
NOTUSED_CPU_B1_SRESET_L MAKE_BASE=TRUE SB_CPU_B1_SRESET_L 24 56
119 24 23 20 7
R5608
MAKE_BASE=TRUE
2
10K 1 SB_CPU_A0_SRESET_L 24 56
ALL SHASTA GPIOS MUST
il
WIRE OUT KODIAK AND CPU SIGNALS FOR TP’S HAVE A PULL-UP WHEN SHASTA
IS STARTING UP. R5609
TP_NB_B_TRIGGER_OUT NB_B_TRIGGER_OUT 44 10K
9 2 1 SB_CPU_A1_SRESET_L 24 56 SRESET LEVEL-TRANSLATOR AND TWO-WAY GLITCH PROTECT
9
TP_NB_A_TRIGGER_OUT MAKE_BASE=TRUE NB_A_TRIGGER_OUT 42
BUFFER LEVEL-SHIFTS SHASTA’S 3.3V PUSH-PULL
TP_CPU_APSYNCOUT MAKE_BASE=TRUE
CPU_APSYNCOUT 43 R5610 SIGNAL TO CPU FOR FAST RISE/FALL TRANSITIONS. BUFFER HIGH-Z’S OUTPUT R5646
TP_CPU_TRIGGER_IN MAKE_BASE=TRUE
CPU_TRIGGER_IN 43 47 10K WHEN PROC VCORE NOT POWERED BUT OVDD IS, TO PROTECT 0
2 1 SB_CPU_B0_SRESET_L 24 56 OVDD-LEVEL OUTPUT FROM CPU SRESET PIN. 2 1
9
TP_CPU_TRIGGER_OUT MAKE_BASE=TRUE
CPU_TRIGGER_OUT 43 5%
9
NC_PSRO MAKE_BASE=TRUE CPU_PSRO 43 R5611 =PPV_EI_CPU
1/16W
MF-LF
NC_PSRO_ENABLE MAKE_BASE=TRUE
CPU_PSRO_ENABLE 43 2
10K 1 SB_CPU_B1_SRESET_L
56 48 47 30 29 7
402
9 24 56 VCC CAN BE 0.8V TO 2.7V
TP_CPU_ATTENTION MAKE_BASE=TRUE
CPU_ATTENTION 43 5% PP2V5_ALL 3.3V INPUT TOLERANT
1/16W NOSTUFF
e
9
NC_CPU_AFN MAKE_BASE=TRUE CPU_AFN 43 MF-LF U5640 DAMPEN OUTPUT
402 NOSTUFF 8 SN74AUC2G125
MAKE_BASE=TRUE
R5640 IS OPTIONAL R56411 PULL-UP PROVIDED VCC
VSSOP R5644
IF SHASTA SHOULD DRIVE OD 100 CPU_SRESET_L
22.1K NOSTUFF SB_CPU_A0_SRESET_L 5 56 3 SRCOM_SRESET 2 1
REMEMBER TO UPDATE NO_TEST PROPERTIES ON PG 6 56 48 47 30 29 7 =PPV_EI_CPU WITH EI LEVEL PULLUP, STUFF
R5612, NOSTUFF R5608, STUFF R5646
1%
1
24
56
A
125 Y
5%
43
1/16W
MF-LF R5643 C5640 1 GND CRITICAL 1/16W
B R5640 4.7K MF-LF
B
r
402 2 0.1UF 7
CPU CHKSTOP OR MCP TO NB 100 3 5%
NOSTUFF 20%
4 402
=PPVCORE_CPU 2 1 SRCOM_VCORE_R 10 LM339A 1/16W 10V
55 52 50 49 48 43
MIN_LINE_WIDTH=0.20 MM SOI-LF
MF-LF CERM 2
R5612 5%
1/16W
MIN_NECK_WIDTH=0.20 MM
V+
13
402 2
SRCOM_SRESET_EN_L
402
=PPV_EI_CPU 2
1K 1 SRCOM_SRESET MF-LF U400
56 48 47 30 29 7 56 402 GND
R5600 5% SRCOM_0V8_REF 11 TURN-ON VCORE > 0.80 V
TURN-OFF VCORE < 0.77 V
1
1K 2 NB_STOP_IS_CHKSTOP 1/16W 12 NOSTUFF
MF-LF
5% R5601 402 R56421 R5645
1/16W 0 10K 470K 1
MF-LF 1 2 1% 2
P
402 1/16W
TO/FROM CPU 43 8
CPU_CHKSTOP_L 5% MF-LF MIN_LINE_WIDTH=0.20 MM
5%
1/16W
MF-LF
TO/FROM NB 402 2 MIN_NECK_WIDTH=0.20 MM
1/16W
MF-LF
402 402
R5602 NB_CHKSTOP_L 42
1
4.7K 2 NOTE, NB UNUSED INTS DO NOT REQUIRE
NB_STOP_IS_MCP PULLUPS, ONLY SHASTA (SINCE
5%
ITS OUTPUTS ARE TEMPORARILY INPUTS
1/16W
MF-LF R5603 =PPV_EI_NB ON BOOTUP).
TO CPU CPU_MCP_L 402
1
0 2
42 41 7
43
INT PULLUP IS SO INT PIN IS NOT FLOATING
5% TO PROCESSOR BUT WEAK TO ALLOW
1/16W
MF-LF KODIAK TO DRIVE PUSH-PULL STRONGLY
402
R5604
2
10K 1 CPU_A0_INT_R_L 24 56
5%
1/16W
MF-LF
402 CPU ALIASES & MISC
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 56 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
A30
GND_85 VD3_0 A28 =PP1V8_PWRON_NBMEM 7 20 39 58 59
A34 A32
GND_86 VD3_1
AA26 AA27
GND_87 VD3_2
AA29
GND_88 VD3_3 AA30 59 58 39 20 7 =PP1V8_PWRON_NBMEM
AA32
GND_89 U1900 VD3_4 AA33
AA35 GND_90 BGA VD3_5 AA36 1
C5836 1
C5835 1
C5834 1
C5832 1
C5831 1
C5830 1
C5829 1
C5822 1
C5811 1
C5800
D
AB24
AC27
GND_91
GND_92
(8 OF 10)
VD3_6
VD3_7
AB25
AC26 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM
D
PART 1
PWR/GND
AC30 AC29 402 402 402 402 402 402 402 402 402 402
GND_93 VD3_8
y
AC33 GND_94 AC32
VD3_9
AC36 AC35
GND_95 VD3_10
AD25 AD24
GND_96 VD3_11
AE23 AE22
1
C5864 1
C5859 1
C5857 1
C5842 1
C5840 1
C5837 1
C5828 1
C5801 1
C5855 1
C5833
GND_97 VD3_12 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
r
AE26 GND_98 AE27 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
VD3_13 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
AE29 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
GND_99 AE30
VD3_14 402 402 402 402 402 402 402 402 402 402
AE32 GND_100 AE33
VD3_15
AE35 GND_101 AE36
VD3_16
AF25 GND_102 AF23
VD3_17
AG23 GND_103 VD3_18 AF26 1
C5863 1
C5860 1
C5858 1
C5843 1
C5841 1
C5838 1
C5827 1
C5802 1
C5866 1
C5844
AG27
GND_104 VD3_19 AG25 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
a
AG30 AG29 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
GND_105 VD3_20 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
AG33 AG32 402 402 402 402 402 402 402 402 402 402
GND_106 VD3_21
AG36 AG35
GND_107 VD3_22
AJ25 GND_108 AJ23
VD3_23
AJ29 GND_109 AJ27
VD3_24
AJ32 AJ30
1 C5865 1 C5862 1 C5861 1 C5846 1 C5845 1 C5839 1 C5826 1 C5803 1 C5887 1 C5877
GND_110 VD3_25 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
AJ35 GND_111 AJ33 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
VD3_26 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
AK23 AJ36
n
GND_112 VD3_27 402 402 402 402 402 402 402 402 402 402
AK27 GND_113 VD3_28 AK25
AL31 GND_114 VD3_29 AK29
AL33 AL32
GND_115 VD3_30
i
AL36 GND_116 VD3_31 AL35 1
C5874 1
C5869 1
C5867 1
C5852 1
C5850 1
C5847 1
C5825 1
C5810 1
C5806 1
C5804
AM25 GND_117 VD3_32 AM23 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
C AM29
AN23
GND_118
GND_119
VD3_33
VD3_34
AM27
AM31
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
C
AN27 GND_120 VD3_35 AN25
AN31 GND_121 VD3_36 AN29
AN35 GND_122 VD3_37 AN33
AR25 AN36
1
C5873 1
C5870 1
C5868 1
C5853 1
C5851 1
C5848 1
C5824 1
C5812 1
C5807 1
C5805
GND_123 VD3_38 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
AR29 GND_124 AP34 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
VD3_39 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
AR33 GND_125 VD3_40 AR23
402 402 402 402 402 402 402 402 402 402
AR35 AR27
m
GND_126 VD3_41
AT23 GND_127 VD3_42 AR31
AT27 GND_128 AT25
VD3_43
AT31 AT29 1 1 1 1 1 1 1 1 1 1
GND_129 VD3_44 C5875 C5872 C5871 C5856 C5854 C5849 C5823 C5813 C5809 C5808
KODIAK-ASIC-040812
il
B28 GND_130 VD3_45 AT33 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
B32 B30 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
GND_131 VD3_46 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
C36 B34 402 402 402 402 402 402 402 402 402 402
GND_132 VD3_47
D30 GND_133 VD3_48 C35
D33 GND_134 VD3_49 D28
E28 GND_135 VD3_50 D32
E32 E30
1
C5886 1
C5885 1
C5883 1
C5881 1
C5879 1
C5876 1
C5821 1
C5818 1
C5816 1
C5814
GND_136 VD3_51 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
E35 E33 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
GND_137 VD3_52 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
G30 GND_138 VD3_53 E36
402 402 402 402 402 402 402 402 402 402
G33 GND_139 VD3_54 G28
e
G36 G32
GND_140 VD3_55
H28 GND_141 VD3_56 G35
H29 GND_142 VD3_57 J28 1
C5884 1
C5882 1
C5880 1
C5878 1
C5820 1
C5819 1
C5817 1
C5815
J29 GND_143 VD3_58 J30 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10%
B J32 GND_144 VD3_59 J33 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
B
r
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
J35 J36 402 402 402 402 402 402 402 402
GND_145 VD3_60
K26 GND_146 VD3_61 L26
L27 GND_147 VD3_62 L29
L30 L32
GND_148 VD3_63
L33 GND_149 VD3_64 L35
L36 GND_150 VD3_65 M24
M25 N23
GND_151 VD3_66
N22 GND_152 VD3_67 N27
P
N26 GND_153 N30
VD3_68
N29 GND_154 N33
VD3_69
N32 GND_155 VD3_70 N36
Q63: SEE P.20 FOR MORE DECOUPLING CAPS FOR THESE PINS.
N35 GND_156 VD3_71 P25
P24 R26
GND_157 VD3_72
R27 R29
GND_158 VD3_73
R30 R32
GND_159 VD3_74
R33 R35
GND_160 VD3_75
R36 T24
GND_161 VD3_76
T25 U23
GND_162 VD3_77
U22 U27
GND_163 VD3_78
U26 U30
GND_164 VD3_79
U29 U33
GND_165 VD3_80
U32 U36
GND_166 VD3_81
U35 V25
GND_167 VD3_82
V24
GND_168 VD3_83 W26 KODIAC NBMEM PWR & CAPS
W27 W29
GND_169 VD3_84
A W30
W33
GND_170
GND_171
VD3_85
VD3_86
W32
W35
SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
W36 Y24
GND_172 VD3_87
Y25 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
GND_173 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
LAST_MODIFIED=Tue Aug 30 18:05:38 2005 58 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Kodiak 128bit CS/CKE/ODT mapping (Q63 style)
+-----------+-----+-----+-----+--------------+--------+
| DIMM RANK | CS* | CKE | ODT | M23 Function | D bits |
+-----------+-----+-----+-----+--------------+--------+
| A0 | 0 | 0 | 0 | onboard DRAM | 0:63 |
| A1 | 1 | 1 | - | *unused* | 0:63 |
P32 AP31 RAM_CLKA_P AR28 AL27 +-----------+-----+-----+-----+--------------+--------+
67 61 RAM_DQ<64> DDR_DQ64 DDR_DQ0 RAM_DQ<0> 61 68 62 61 DDR_CK_A DDR_CS0_QDM0 RAM_CS_L<0> 61 | B2 | 8 | 0 | 4 | J6700 rank 1 | 64:127 |
T36 AP32 RAM_CLKA_N AT28 AP33 | B3 | 9 | 1 | - | J6700 rank 2 | 64:127 |
67 61 RAM_DQ<65> DDR_DQ65 DDR_DQ1 RAM_DQ<1> 61 68 62 61 DDR_CK_AN DDR_CS1_QDM1 OUT +===========+=====+=====+=====+==============+========+
U31 AN32 AL26 AJ31 | C4 | 2 | 2 | 1 | *unused* | 0:63 |
67 61 RAM_DQ<66> DDR_DQ66 DDR_DQ2 RAM_DQ<2> 61 68 OUT DDR_CK_B DDR_CS2_QDM2 OUT | C5 | 3 | 3 | - | *unused* | 0:63 |
P31 AM30 AK26 AF31 +-----------+-----+-----+-----+--------------+--------+
67 61 RAM_DQ<67> DDR_DQ67 DDR_DQ3 RAM_DQ<3> 61 68 OUT DDR_CK_BN DDR_CS3_QDM3 OUT | D6 | 10 | 2 | 5 | *unused* | 64:127 |
T30 U1900 AN30 AH33
| D7 | 11 | 3 | - | *unused* | 64:127 |
67 61 RAM_DQ<68> DDR_DQ68 DDR_DQ4 RAM_DQ<4> 61 68 U1900 DDR_CS4_QDM4 RAM_CS_L<4> 61 +===========+=====+=====+=====+==============+========+
68 67 61
RAM_CAS_L AM24 DDR_CAS | E8 | 4 | 4 | 2 | *unused* | 0:63 |
67 61 RAM_DQ<69> T29 DDR_DQ69 DDR_DQ5 AP30 RAM_DQ<5> 61 68 BGA DDR_CS5_QDM5 AB32 RAM_CS_L<5> 61 | E9 | 5 | 5 | - | *unused* | 0:63 |
BGA 68 67 61
RAM_RAS_L AL24
DDR_RAS +-----------+-----+-----+-----+--------------+--------+
RAM_DQ<70> T28 DDR_DQ70 DDR_DQ6 AR30 RAM_DQ<6> V36
67 61 61 68
(3 OF 10) DDR_CS6_QDM6 OUT | F10 | 12 | 4 | 6 | *unused* | 64:127 |
D 67 61 RAM_DQ<71> W28 DDR_DQ71
(4 OF 10)
DDR_DQ7 AM32 RAM_DQ<7> 61 68
68 67 61
RAM_WE_L AP23 DDR_WE
DDR_CS7_QDM7 W31 OUT
| F11 | 13 | 5 | - | *unused* | 64:127 |
+===========+=====+=====+=====+==============+========+ D
INTERFACE - CONTROL
| G12 | 6 | 6 | 3 | *unused* | 0:63 |
INTERFACE - DATA
67 61 RAM_DQ<72> P34 DDR_DQ72 DDR_DQ8 AM36 RAM_DQ<8> 61 68 68 67 61
RAM_BA<0> AL22 DDR_BA0 DDR_CS8_QDM8 V29 RAM_CS_L<8> 61 | G13 | 7 | 7 | - | *unused* | 0:63 |
+-----------+-----+-----+-----+--------------+--------+
y
67 61 RAM_DQ<73> T34 DDR_DQ73 DDR_DQ9 AK31 RAM_DQ<9> 61 68 68 67 61
RAM_BA<1> AP28 DDR_BA1 DDR_CS9_QDM9 R34 RAM_CS_L<9> 61 | H14 | 14 | 6 | 7 | *unused* | 64:127 |
P33 AL34 RAM_BA<2> AN28 M32
| H15 | 15 | 7 | - | *unused* | 64:127 |
67 61 RAM_DQ<74> DDR_DQ74 DDR_DQ10 RAM_DQ<10> 61 68 68 67 61 DDR_BA2 DDR_CS10_QDM10 OUT +===========+=====+=====+=====+==============+========+
67 61 RAM_DQ<75> T35 DDR_DQ75 DDR_DQ11 AT34 RAM_DQ<11> 61 68 DDR_CS11_QDM11 M28 OUT Kodiak 128bit CS/CKE/ODT mapping (v1.1 only)
68 67 61
RAM_A<0> AN26
DDR_MAD0 +-----------+-----+-----+-----+--------------+--------+
67 61 RAM_DQ<76> P35 DDR_DQ76 DDR_DQ12 AR34 RAM_DQ<12> 61 68 DDR_CS12_QDM12 H35 OUT | DIMM RANK | CS* | CKE | ODT | M23 Function | D bits |
MEMORY
68 67 61
RAM_A<1> AP26 DDR_MAD1 +-----------+-----+-----+-----+--------------+--------+
67 61 RAM_DQ<77> P36 DDR_DQ77 DDR_DQ13 AN34 RAM_DQ<13> 61 68 DDR_CS13_QDM13 D36
OUT | A0 | 0 | 0 | 0 | onboard DRAM | 0:63 |
RAM_A<2>
r
68 67 61
AR26 DDR_MAD2 | A1 | 1 | 1 | - | *unused* | 0:63 |
67 61 RAM_DQ<78> R31 DDR_DQ78 DDR_DQ14 AM33 RAM_DQ<14> 61 68 DDR_CS14_QDM14 G29 OUT +-----------+-----+-----+-----+--------------+--------+
68 67 61
RAM_A<3> AT26 DDR_MAD3 | B2 | 4 | 4 | 2 | J6700 rank 1 | 64:127 |
T31 AM34
MEMORY
RAM_DQ<79> DDR_DQ79 RAM_DQ<15> E27
67 61 DDR_DQ15 61 68
RAM_A<4> AM26 DDR_CS15_QDM15 OUT | B3 | 5 | 5 | - | J6700 rank 2 | 64:127 |
K36 AH31 68 67 61 DDR_MAD4 +===========+=====+=====+=====+==============+========+
67 61 RAM_DQ<80> DDR_DQ80 DDR_DQ16 RAM_DQ<16> 61 68 | C4 | 2 | 2 | 1 | *unused* | 0:63 |
68 67 61
RAM_A<5> AL25 DDR_MAD5 DDR_CKE0_QCKE0 AJ24 RAM_CKE<0> 61 | C5 | 3 | 3 | - | *unused* | 0:63 |
67 61 RAM_DQ<81> M34 DDR_DQ81 DDR_DQ17 AK34 RAM_DQ<17> 61 68 +-----------+-----+-----+-----+--------------+--------+
68 67 61
RAM_A<6> AP25
DDR_MAD6 DDR_CKE1_QCKE1 AH24 RAM_CKE<1> 61 | D6 | 6 | 6 | 3 | *unused* | 64:127 |
67 61 RAM_DQ<82> K35 DDR_DQ82 DDR_DQ18 AH32 RAM_DQ<18> 61 68 | D7 | 7 | 7 | - | *unused* | 64:127 |
68 67 61
RAM_A<7> AH28 DDR_MAD7 DDR_CKE2_QCKE2 AL21 OUT +===========+=====+=====+=====+==============+========+
67 61 RAM_DQ<83> N31 DDR_DQ83 DDR_DQ19 AK33 RAM_DQ<19> 61 68
68 67 61
RAM_A<8> AL30
DDR_MAD8 DDR_CKE3_QCKE3 AP21
OUT
RAM_DQ<84> L31 DDR_DQ84 DDR_DQ20 AH30 RAM_DQ<20>
a
67 61 61 68
68 67 61
RAM_A<9> AR22 DDR_MAD9 DDR_CKE4_QCS_EN AT22 RAM_CKE<4> 61
67 61 RAM_DQ<85> L34 DDR_DQ85 DDR_DQ21 AH29 RAM_DQ<21> 61 68
68 67 61
RAM_A<10> AJ28 DDR_MAD10 DDR_CKE5_QCS0 AP22 RAM_CKE<5> 61
67 61 RAM_DQ<86> M31 DDR_DQ86 DDR_DQ22 AJ34 RAM_DQ<22> 61 68
68 67 61
RAM_A<11> AH27
DDR_MAD11 DDR_CKE6_QCS1 AN22
OUT
67 61 RAM_DQ<87> M33 DDR_DQ87 DDR_DQ23 AK32 RAM_DQ<23> 61 68
68 67 61
RAM_A<12> AH26 DDR_MAD12 DDR_CKE7_QCS2 AM22 OUT
67 61 RAM_DQ<88> M27 DDR_DQ88 DDR_DQ24 AE31 RAM_DQ<24> 61 68
68 67 61
RAM_A<13> AH25 DDR_MAD13
67 61 RAM_DQ<89> R28 DDR_DQ89 DDR_DQ25 AG34 RAM_DQ<25> 61 68 DDR_MUXEN0 AP27 OUT
68 67 61
RAM_A<14> AJ26 DDR_MAD14
67 61 RAM_DQ<90> U28 DDR_DQ90 DDR_DQ26 AE34 RAM_DQ<26> 61 68 DDR_MUXEN1 AM28 OUT
68 67 61
RAM_A<15> AK24 DDR_MAD15
67 61 RAM_DQ<91> T27 DDR_DQ91 DDR_DQ27 AH36 RAM_DQ<27> 61 68 DDR_MUXEN2 AL28 OUT
n
67 61 RAM_DQ<92> N28 DDR_DQ92 DDR_DQ28 AF36 RAM_DQ<28> 61 68
AF22 DDR_ARB_ADDR DDR_MUXEN3 AK28 OUT
67 61 RAM_DQ<93> P29 DDR_DQ93 DDR_DQ29 AF35 RAM_DQ<29> 61 68 DDR_MUXEN4 AK30 OUT
68 61
RAM_DQS_P<0> AR32 DDR_DQSP0 PLACE NEAR KODIAK
67 61 RAM_DQ<94> P30 DDR_DQ94 DDR_DQ30 AF34 RAM_DQ<30> 61 68 DDR_MUXEN5 AT30 OUT
68 61
RAM_DQS_N<0> AT32
DDR_DQSN0 NOSTUFF
N34 AG31
i
RAM_DQ<95> RAM_DQ<31> AL29
67 61 DDR_DQ95 DDR_DQ31 61 68 DDR_MUXEN6 OUT R5928
67 61 RAM_DQ<96> G34 DDR_DQ96 DDR_DQ32 AF29 RAM_DQ<32> 61 68 68 61
RAM_DQS_P<1> AP35
DDR_DQSP1 DDR_MUXEN7 AP29
OUT 1 2
J31 AF30 RAM_DQS_N<1>
C 67 61
67 61
RAM_DQ<97>
RAM_DQ<98> G31
DDR_DQ97
DDR_DQ98
DDR_DQ33
DDR_DQ34 AD31
RAM_DQ<33>
RAM_DQ<34>
61 68
61 68
68 61
RAM_DQS_P<2>
AP36
AK35
DDR_DQSN1
DDR_ODT0_QODT_EN AL23
AT24
RAM_ODT<0> 61
49.9
NOSTUFF
C
RAM_DQ<99> J34 DDR_DQ99 AG28 RAM_DQ<35>
68 61 DDR_DQSP2 DDR_ODT1_QODT0 OUT R5929
67 61 DDR_DQ35 61 68
RAM_DQS_N<2> AK36 AR24 1 2
H30 AD34 68 61 DDR_DQSN2 DDR_ODT2_QODT1 RAM_ODT<2> 61
67 61 RAM_DQ<100> DDR_DQ100 DDR_DQ36 RAM_DQ<36> 61 68
DDR_ODT3_QODT2 AN24 OUT 49.9
67 61 RAM_DQ<101> H36 DDR_DQ101 DDR_DQ37 AD35 RAM_DQ<37> 61 68 68 61
RAM_DQS_P<3> AF33 DDR_DQSP3
DDR_ODT4 AP24 RAM_ODT<4> 61 NOSTUFF
67 61 RAM_DQ<102> H31 DDR_DQ102 DDR_DQ38 AH35 RAM_DQ<38> 61 68 68 61
RAM_DQS_N<3> AF32 DDR_DQSN3 R5912
DDR_ODT5 AK22 OUT
H34 AH34 1 2
67 61 RAM_DQ<103> DDR_DQ103 DDR_DQ39 RAM_DQ<39> 61 68
68 61
RAM_DQS_P<4> AD33
DDR_DQSP4 DDR_ODT6_QDM16 AF28 OUT
RAM_DQ<104> B35 DDR_DQ104 DDR_DQ40 AB36 RAM_DQ<40> 49.9
KODIAK-ASIC-040812
67 61 61 68
68 61
RAM_DQS_N<4> AD32 DDR_DQSN4 DDR_ODT7_QDM17 M29
OUT
67 61 RAM_DQ<105> F31 DDR_DQ105 DDR_DQ41 AC34 RAM_DQ<41> 61 68
m
KODIAK-ASIC-040812
67 61 RAM_DQ<106> C33 DDR_DQ106 DDR_DQ42 AA31 RAM_DQ<42> 61 68 68 61
RAM_DQS_P<5> AB30
DDR_DQSP5
DDR_REFCLK_P AF24 NB_DDR_REFCLK_P 26
67 61 RAM_DQ<107> F34 DDR_DQ107 DDR_DQ43 AD36 RAM_DQ<43> 61 68 68 61
RAM_DQS_N<5> AB31
DDR_DQSN5 DIFFERENTIAL_PAIR=RAM_NB_DDR_REFCLK_DP NET_PHYSICAL_TYPE=RAM_NB_DDR_80 NET_SPACING_TYPE=RAM_NB_DDR_80
AG24 NB_DDR_REFCLK_N
C34 AB35 DDR_REFCLK_N 26
67 61 RAM_DQ<108> DDR_DQ108 DDR_DQ44 RAM_DQ<44> 61 68 DIFFERENTIAL_PAIR=RAM_NB_DDR_REFCLK_DP NET_PHYSICAL_TYPE=RAM_NB_DDR_80 NET_SPACING_TYPE=RAM_NB_DDR_80
68 61
RAM_DQS_P<6> Y31
DDR_DQSP6
D34 AB34
il
67 61 RAM_DQ<109> DDR_DQ109 DDR_DQ45 RAM_DQ<45> 61 68
RAM_DQS_N<6> Y30
DDR_DQSN6 CHP_FAULT_N AH22 NB_CHP_FLT_N
67 61 RAM_DQ<110> D35 DDR_DQ110 DDR_DQ46 AB33 RAM_DQ<46> 61 68
68 61
R5913
E34 AC31 RAM_DQS_P<7> Y27 AJ22
1K
67 61 RAM_DQ<111> DDR_DQ111 DDR_DQ47 RAM_DQ<47> 61 68 68 61 DDR_DQSP7 DDR_STOP NB_DDR_STOP_OUT 1 2
67 61 RAM_DQ<112> D31 DDR_DQ112 DDR_DQ48 V32 RAM_DQ<48> 61 68 68 61
RAM_DQS_N<7> Y28
DDR_DQSN7
OBSV AG22 9 NB_PLL_OUT_TRG
67 61 RAM_DQ<113> E31 DDR_DQ113 DDR_DQ49 Y32 RAM_DQ<49> 61 68
67 61
RAM_DQS_P<8> V28
DDR_DQSP8
67 61 RAM_DQ<114> C31 DDR_DQ114 DDR_DQ50 V31 RAM_DQ<50> 61 68 DDR_VREF_0_1 AG26
67 61
RAM_DQS_N<8> V27
DDR_DQSN8
67 61 RAM_DQ<115> F30 DDR_DQ115 DDR_DQ51 Y33 RAM_DQ<51> 61 68 DDR_VREF_2_3 AD26
67 61 RAM_DQ<116> A33 DDR_DQ116 DDR_DQ52 V33 RAM_DQ<52> 61 68 67 61
RAM_DQS_P<9> T33
DDR_DQSP9 DDR_VREF_4_16 AB26
67 61 RAM_DQ<117> B33 DDR_DQ117 DDR_DQ53 V34 RAM_DQ<53> 61 68 67 61
RAM_DQS_N<9> T32
DDR_DQSN9 DDR_VREF_5_6 Y26
67 61 RAM_DQ<118> C32 DDR_DQ118 DDR_DQ54 V35 RAM_DQ<54> 61 68 DDR_VREF_7_8 V26
67 61
RAM_DQS_P<10> M36
DDR_DQSP10
C30 Y29 =PP1V8_PWRON_NBMEM
e
RAM_DQ<119> RAM_DQ<55> T26
67 61 DDR_DQ119 DDR_DQ55 61 68
RAM_DQS_N<10> M35
DDR_VREF_9_10 7 20 39 58
D27 V30 67 61 DDR_DQSN10 P26
67 61 RAM_DQ<120> DDR_DQ120 DDR_DQ56 RAM_DQ<56> 61 68 DDR_VREF_11_17 1
67 61 RAM_DQ<121> F29 DDR_DQ121 DDR_DQ57 Y34 RAM_DQ<57> 61 68 67 61
RAM_DQS_P<11> P27
DDR_DQSP11 DDR_VREF_12_13 M26 R5910
E29 Y35 RAM_DQS_N<11> P28 F28
56.2
67 61 RAM_DQ<122> DDR_DQ122 DDR_DQ58 RAM_DQ<58> 61 68 67 61 DDR_DQSN11 DDR_VREF_14_15 1%
1/16W
67 61 RAM_DQ<123> D29 DDR_DQ123 DDR_DQ59 U34 RAM_DQ<59> 61 68 CHECK VREF CONNECTION
B RAM_DQS_P<12> H33 DDR_DQSP12
MF-LF
r
67 61 402
67 61 RAM_DQ<124> C29 DDR_DQ124 DDR_DQ60 AB28 RAM_DQ<60> 61 68
2
67 61
RAM_DQS_N<12> H32
DDR_DQSN12 DDR_VREF1_9
67 61 RAM_DQ<125> B29 DDR_DQ125 DDR_DQ61 AB27 RAM_DQ<61> 61 68 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
67 61 RAM_DQ<126> A29 DDR_DQ126 DDR_DQ62 W34 RAM_DQ<62> 61 68 67 61
RAM_DQS_P<13> F33
DDR_DQSP13 1 C5905 C5906 C5907 C5908
1 1 1
R5911 1
1
C5904
67 61 RAM_DQ<127> C28 DDR_DQ127 DDR_DQ63 AA28 RAM_DQ<63> 61 68 67 61
RAM_DQS_N<13> F32 DDR_DQSN13 1UF 1UF 1UF 1UF 56.2
10% 10% 10% 10% 1%
1UF
6.3V 6.3V 6.3V 6.3V 10%
RAM_DQS_P<14> A31
2 CERM 2 CERM 2 CERM 2 CERM 1/16W 6.3V
F36 AB29 67 61 DDR_DQSP14 402 402 402 402 MF-LF 2 CERM
DDR_DQ136 DDR_DQ128 RAM_DQS_N<14> B31
402
2 402
K31 AC28 67 61 DDR_DQSN14
DDR_DQ137 DDR_DQ129
K34 DDR_DQ138 DDR_DQ130 AF27 67 61
RAM_DQS_P<15> B27
DDR_DQSP15 1 C5909 1 C5910 1 C5911 1 C5912 1 C5913
P
F35 DDR_DQ139 DDR_DQ131 AE28 67 61
RAM_DQS_N<15> A27
DDR_DQSN15 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
M30 DDR_DQ140 DDR_DQ132 AD29 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
AD27 DDR_DQSP16 CERM CERM CERM CERM CERM
L28 AD30 402 402 402 402 402
DDR_DQ141 DDR_DQ133 AD28
K29 Y36 DDR_DQSN16
DDR_DQ142 DDR_DQ134
K30 DDR_DQ143 DDR_DQ135 AA34 K32 DDR_DQSP17
PLACE CLOSE TO KODIAK PIN
K33
WITHIN 20MIL FROM VIA FOR EACH VREF
DDR_DQSN17
R5927
R5914 2.2
=PPV_PWRON_NB_REFCLK 1 2 PPV_PWRON_NB_REFCLK_PLL_R 1 2 AH23 DDR_REFCLK_AVDD
DQ/DQS OKAY TO TIE TO GROUND FOR THERMALS 42 7
MIN_LINE_WIDTH=0.5MM 5%
DDR_REFCLK_AGND
4.7 1/16W
5%
MIN_NECK_WIDTH=0.2MM
Q63 APPLICATION IS PP1V6 MF-LF
1/16W 402
AH21
MF-LF
1 C5900 1 C5901
402 1UF 0.22UF
10% 20% U1900_RFCK_AVDD
6.3V 6.3V
2 CERM
2 X5R
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
402 402
Kodiak Memory Dq/Ctl
CHECK CAP SIZE (0603 OR 0402)
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
KODIAK MEMORY INTERFACE NONE
59 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ALL R PACKS ARE 1/16W 5%
ELECTRICAL_CONSTRAINT_SET NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR
62 61 7 =PP1V8_RUN_RAM 62 61 7 =PP1V8_RUN_RAM 62 59 RAM_CLKA_P RAM_KODIAK_CLK_EC RAM_CLK RAM_CLK RAM_KODIAK_CLK_DP I206
62 59 RAM_CLKA_N RAM_CLK RAM_CLK RAM_KODIAK_CLK_DP I207
5 8 5 5 8 5 8 8 8 5 5 1 C6108 67 62 RAM_DIMM_A_CLK_P0 RAM_DIMM_CLK_EC RAM_CLK RAM_CLK RAM_DIMM_CLK0_DP I210
RP6107 RP6106 RP6106 RP6105 RP6105 RP6104 RP6104 RP6103 1 C6100 1 C6102 RP6109 RP6110 RP6109 0.1UF 67 62 RAM_DIMM_A_CLK_N0 RAM_DIMM_CLK_EC RAM_CLK RAM_CLK RAM_DIMM_CLK0_DP I211
20%
240 240 240 240 240 240 240 240 0.1UF 0.1UF 240 240 240 2 10V 67 62 RAM_DIMM_A_CLK_P1 RAM_DIMM_CLK_EC RAM_CLK RAM_CLK RAM_DIMM_CLK1_DP I212
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 5% 5% 5% CERM
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 10V 10V 1/16W 1/16W 1/16W 402 RAM_DIMM_A_CLK_N1
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF
2 CERM 2 CERM
SM-LF SM-LF SM-LF
67 62 RAM_DIMM_CLK_EC RAM_CLK RAM_CLK RAM_DIMM_CLK1_DP I213
4 1 4 4 1 4 1 1 402 402 1 4 4 67 62 RAM_DIMM_A_CLK_P2 RAM_DIMM_CLK_EC RAM_CLK RAM_CLK RAM_DIMM_CLK2_DP I214
68 67 61 59 RAM_A<0> 67 62 RAM_DIMM_A_CLK_N2 RAM_DIMM_CLK_EC RAM_CLK RAM_CLK RAM_DIMM_CLK2_DP I215
68 67 61 59 RAM_RAS_L
68 67 61 59 RAM_A<1> 69 62 RAM_ONBOARD_CLK_P0_1 RAM_ONBOARD_CLK_EC RAM_CLK RAM_CLK RAM_ONBOARD_CLK0_DP I216
68 67 61 59 RAM_CAS_L
D 68 67 61 59
68 67 61 59
RAM_A<2>
RAM_A<3>
68 67 61 59 RAM_WE_L
69 62
69 62
RAM_ONBOARD_CLK_N0_1
RAM_ONBOARD_CLK_P2_3
RAM_ONBOARD_CLK_EC
RAM_ONBOARD_CLK_EC
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_ONBOARD_CLK0_DP
RAM_ONBOARD_CLK2_DP
I217
I218
D
68 67 61 59 RAM_A<4> 69 62 RAM_ONBOARD_CLK_N2_3 RAM_ONBOARD_CLK_EC RAM_CLK RAM_CLK RAM_ONBOARD_CLK2_DP
y
7 6 6 I219
68 67 61 59 RAM_A<6> 70 62 RAM_ONBOARD_CLK_P4_5 RAM_ONBOARD_CLK_EC RAM_CLK RAM_CLK RAM_ONBOARD_CLK4_DP I220
RP6109 RP6110 RP6109
68 67 61 59 RAM_A<5> 240 240 240 70 62 RAM_ONBOARD_CLK_N4_5 RAM_ONBOARD_CLK_EC RAM_CLK RAM_CLK RAM_ONBOARD_CLK4_DP I221
68 67 61 59 RAM_A<7> 5% 5% 5% 70 62 RAM_ONBOARD_CLK_P6_7 RAM_ONBOARD_CLK_EC RAM_CLK RAM_CLK RAM_ONBOARD_CLK6_DP
1/16W 1/16W 1/16W I222
SM-LF SM-LF SM-LF 70 62 RAM_ONBOARD_CLK_N6_7 RAM_ONBOARD_CLK_EC RAM_CLK RAM_CLK RAM_ONBOARD_CLK6_DP I223
2 3 3
r
6 7 6 6 7 6 7 7 62 RAM_CLK_FBIN_P RAM_FB_CLK_EC RAM_CLK RAM_CLK RAM_FBIN_CLK_DP I224
62 RAM_CLK_FBIN_N RAM_CLK RAM_CLK RAM_FBIN_CLK_DP I225
RP6107 RP6106 RP6106 RP6105 RP6105 RP6104 RP6104 RP6103
RPACK/RES NEAR/UNDER CONNECTOR RAM_CLK_FBOUT_P RAM_CLK RAM_CLK RAM_FBOUT_CLK_DP
240 240 240 240 240 240 240 240 62 I226
5% 5% 5% 5% 5% 5% 5% 5% 62 RAM_CLK_FBOUT_N RAM_CLK RAM_CLK RAM_FBOUT_CLK_DP
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W I227
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF 62 61 7 =PP1V8_RUN_RAM
3 2 3 3 2 3 2 2 68 59 RAM_DQ<7..0> RAM_DQS0_EC RAM_CAD RAM_CAD I248
68 59 RAM_DQS_P<0> RAM_DQS0_EC RAM_DQS RAM_DQS RAM_DQS_0_DP I246
8 8 5 1 C6109 RAM_DQS_N<0> RAM_DQS0_EC RAM_DQS RAM_DQS RAM_DQS_0_DP
a
68 59 I470
RPACK/RES NEAR/UNDER CONNECTOR RP6108 RP6107 RP6101 0.1UF 68 59 RAM_DQ<15..8> RAM_DQS1_EC RAM_CAD RAM_CAD I252
20%
240 240 240 2 10V 68 59 RAM_DQS_P<1> RAM_DQS1_EC RAM_DQS RAM_DQS RAM_DQS_1_DP
5% 5% 5% CERM I251
=PP1V8_RUN_RAM 1/16W 1/16W 1/16W 402 RAM_DQS_N<1>
62 61 7
SM-LF
68 59 RAM_DQS1_EC RAM_DQS RAM_DQS RAM_DQS_1_DP I471
SM-LF SM-LF
1 1 4 68 59 RAM_DQ<23..16> RAM_DQS2_EC RAM_CAD RAM_CAD I254
5 5 5 8 8 8 5 8 68 59 RAM_DQS_P<2> RAM_DQS2_EC RAM_DQS RAM_DQS RAM_DQS_2_DP I253
68 67 61 59 RAM_BA<0>
RAM_DQS_N<2> RAM_DQS2_EC RAM_DQS RAM_DQS RAM_DQS_2_DP
RP6103 RP6102 RP6108 RP6102 RP6101 RP6110 RP6100 RP6100 1 C6103 1 C6104 68 67 61 59 RAM_BA<1>
68 59
RAM_DQ<31..24> RAM_DQS3_EC RAM_CAD RAM_CAD
I472
240 240 240 240 240 240 240 240 0.1UF 0.1UF RAM_BA<2>
68 59 I256
n
68 67 61 59
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 68 59 RAM_DQS_P<3> RAM_DQS3_EC RAM_DQS RAM_DQS RAM_DQS_3_DP I255
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF 68 59 RAM_DQS_N<3> RAM_DQS3_EC RAM_DQS RAM_DQS RAM_DQS_3_DP
402 402 7 7 6 I473
4 4 4 1 1 1 4 1
68 59 RAM_DQ<39..32> RAM_DQS4_EC RAM_CAD RAM_CAD I258
68 67 61 59 RAM_A<8> RP6108 RP6107 RP6101
i
RAM_DQS_P<4> RAM_DQS4_EC RAM_DQS RAM_DQS RAM_DQS_4_DP
68 67 61 59 RAM_A<9> 240 240 240 68 59 I257
5% 5% 5% 68 59 RAM_DQS_N<4> RAM_DQS4_EC RAM_DQS RAM_DQS RAM_DQS_4_DP I474
68 67 61 59 RAM_A<10> 1/16W 1/16W 1/16W
C 68 67 61 59
68 67 61 59
RAM_A<11>
RAM_A<12>
2
SM-LF
2
SM-LF
3
SM-LF 68 59
68 59
RAM_DQ<47..40>
RAM_DQS_P<5>
RAM_DQS5_EC
RAM_DQS5_EC
RAM_CAD
RAM_DQS
RAM_CAD
RAM_DQS RAM_DQS_5_DP
I260
I259
C
68 59 RAM_DQS_N<5> RAM_DQS5_EC RAM_DQS RAM_DQS RAM_DQS_5_DP I475
68 67 61 59 RAM_A<13>
RPACK/RES NEAR/UNDER CONNECTOR 68 59 RAM_DQ<55..48> RAM_DQS6_EC RAM_CAD RAM_CAD I262
68 67 61 59 RAM_A<14>
68 59 RAM_DQS_P<6> RAM_DQS6_EC RAM_DQS RAM_DQS RAM_DQS_6_DP I261
68 67 61 59 RAM_A<15>
68 59 RAM_DQS_N<6> RAM_DQS6_EC RAM_DQS RAM_DQS RAM_DQS_6_DP I476
68 59 RAM_DQ<63..56> RAM_DQS7_EC RAM_CAD RAM_CAD I264
6 6 6 7 7 7 6 7 68 59 RAM_DQS_P<7> RAM_DQS7_EC RAM_DQS RAM_DQS RAM_DQS_7_DP I263
RP6103 RP6102 RP6108 RP6102 RP6101 RP6110 RP6100 RP6100 68 59 RAM_DQS_N<7> RAM_DQS7_EC RAM_DQS RAM_DQS RAM_DQS_7_DP I477
m
240 240 240 240 240 240 240 240 67 59 RAM_DQ<71..64> RAM_DQS8_EC RAM_CAD RAM_CAD I267
5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 67 59 RAM_DQS_P<8> RAM_DQS8_EC RAM_DQS RAM_DQS RAM_DQS_8_DP
SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF SM-LF I265
3 3 3 2 2 2 3 2 67 59 RAM_DQS_N<8> RAM_DQS8_EC RAM_DQS RAM_DQS RAM_DQS_8_DP I478
il
67 59 RAM_DQ<79..72> RAM_DQS9_EC RAM_CAD RAM_CAD I268
67 59 RAM_DQS_P<9> RAM_DQS9_EC RAM_DQS RAM_DQS RAM_DQS_9_DP I266
RPACK/RES NEAR/UNDER CONNECTOR 67 59 RAM_DQS_N<9> RAM_DQS9_EC RAM_DQS RAM_DQS RAM_DQS_9_DP I479
1V8_RUN_RAM_CKE 61 62 62 61 1V8_RUN_RAM_CKE 67 59 RAM_DQ<87..80> RAM_DQS10_EC RAM_CAD RAM_CAD I269
MIN_LINE_WIDTH=0.6MM
62 61 7 =PP1V8_RUN_RAM MIN_NECK_WIDTH=0.2MM 67 59 RAM_DQS_P<10> RAM_DQS10_EC RAM_DQS RAM_DQS RAM_DQS_10_DP I270
VOLTAGE=1.8V
NET_SPACING_TYPE=POWER RAM_DQS_N<10> RAM_DQS10_EC RAM_DQS RAM_DQS RAM_DQS_10_DP
5 8 8 5 8 1 C6105 1 C6106 67 59
RAM_DQ<95..88> RAM_DQS11_EC RAM_CAD RAM_CAD
I480
RP6150 RP6152 RP6151 RP6151 RP6150 0.1UF 0.1UF 67 59 I271
20% 20% RAM_DQS_P<11> RAM_DQS11_EC RAM_DQS RAM_DQS RAM_DQS_11_DP
240 240 240 240 240 10V
2 CERM
10V
2 CERM 62 61 7 =PP1V8_RUN_RAM 67 59 I272
5% 5% 5% 5% 5%
402 402 67 59 RAM_DQS_N<11> RAM_DQS11_EC RAM_DQS RAM_DQS RAM_DQS_11_DP I481
1/16W 1/16W 1/16W 1/16W 1/16W
SM-LF SM-LF SM-LF SM-LF SM-LF 5 8 RAM_DQ<103..96>
R6121 4 1 1 4 1
67 59 RAM_DQS12_EC RAM_CAD RAM_CAD I275
10 1 1 C6107
e
61 59 RAM_CS_L<4> 1 2
RAM_M23_128
RAM_CS_DIMM_A 61 67
RP6170
240
R6173 RP6170
240 0.1UF
67 59 RAM_DQS_P<12> RAM_DQS12_EC RAM_DQS RAM_DQS RAM_DQS_12_DP I273
R6161 5%
240 5% 20% 67 59 RAM_DQS_N<12> RAM_DQS12_EC RAM_DQS RAM_DQS RAM_DQS_12_DP I482
402 5%
10 1/16W 1/16W 10V RAM_DQ<111..104>
RAM_Q63_128 SERIES R NEAR KODIAK 1/16W 2 CERM 67 59 RAM_DQS13_EC RAM_CAD RAM_CAD I277
61 59 RAM_CS_L<8> 1 2
R6172 SM-LF MF-LF SM-LF
402
4 RAM_DQS_P<13> RAM_DQS13_EC RAM_DQS RAM_DQS RAM_DQS_13_DP
402 10 2 402 1 67 59 I274
SHARE PIN 2 PADS 61 59 RAM_CS_L<0> 1 2 67 59 RAM_DQS_N<13> RAM_DQS13_EC RAM_DQS RAM_DQS RAM_DQS_13_DP
B RAM_CS_L_R<0> I483
B
r
61 63 68 69 70
402 67 59 RAM_DQ<119..112> RAM_DQS14_EC RAM_CAD RAM_CAD I278
R6175 67 59 RAM_DQS_P<14> RAM_DQS14_EC RAM_DQS RAM_DQS RAM_DQS_14_DP I276
R6122 10 67 59 RAM_DQS_N<14> RAM_DQS14_EC RAM_DQS RAM_DQS RAM_DQS_14_DP I484
RAM_CS_L<5> 1
10 2
RAM_M23_128
RAM_CS_DIMM_B
61 59 RAM_CKE<0> 1 2
RAM_CKE_R<0> RAM_DQ<127..120>
61 59 61 67 61 62 63 68 69 70 67 59 RAM_DQS15_EC RAM_CAD RAM_CAD I279
R6162 402
402
67 59 RAM_DQS_P<15> RAM_DQS15_EC RAM_DQS RAM_DQS RAM_DQS_15_DP I280
10 RAM_Q63_128 R6178
61 59 RAM_CS_L<9> 1 2 67 59 RAM_DQS_N<15> RAM_DQS15_EC RAM_DQS RAM_DQS RAM_DQS_15_DP I485
402 RAM_ODT<0> 1
10 2 RAM_DQ_R<127..0>
61 59 70 69 68 6 RAM_CAD RAM_CAD I294
SHARE PIN 2 PADS RAM_ODT_R<0> 61 63 68 69 70
402 70 69 68 RAM_DQS_P_R<15..0> RAM_DQS RAM_DQS I305
P
6 1 7
R6174 70 69 68 RAM_DQS_N_R<15..0> RAM_DQS RAM_DQS I486
R6123 RP6170 240 RP6170
5% RAM_A<15..14> RAM_A_CTL_EC RAM_CAD RAM_CAD
10 RAM_M23_128 240 1/16W 240 68 67 61 59 I572
61 59 RAM_CKE<4> 1 2 RAM_CKE_DIMM_A 61 62 67 5% MF-LF 5% 68 67 61 59 RAM_A<13..0> RAM_A_CTL_EC RAM_CAD RAM_CAD I295
1/16W 1/16W
R6163 402 SM-LF 2 402 SM-LF 68 67 61 59 RAM_BA<1..0> RAM_A_CTL_EC RAM_CAD RAM_CAD I296
1
10 2
RAM_Q63_128 3 2
61 59 RAM_CKE<0> 68 67 61 59 RAM_BA<2> RAM_A_CTL_1_EC RAM_CAD RAM_CAD I573
402
SHARE PIN 2 PADS 68 67 61 59 RAM_RAS_L RAM_A_CTL_EC RAM_CAD RAM_CAD I297
RES NEAR BRANCH POINT
CS/CKE/ODT TERMINATION 68 67 61 59 RAM_CAS_L RAM_A_CTL_EC RAM_CAD RAM_CAD I298
FOR ONBOARD DRAM
68 67 61 59 RAM_WE_L RAM_A_CTL_EC RAM_CAD RAM_CAD I299
R6124 61 59 RAM_CS_L<0> RAM_CS_ONBOARD_EC RAM_CSCKEODT RAM_CSCKEODT I243 70 69 68 63 RAM_A_R<15..0> RAM_CAD RAM_CAD I300
10 RAM_M23_128
61 59 RAM_CKE<5> 1 2 RAM_CKE_DIMM_B 61 62 67 61 59 RAM_CS_L<4> RAM_CS_DIMM_EC RAM_CSCKEODT RAM_CSCKEODT I487 70 69 68 63 RAM_BA_R<2..0> RAM_CAD RAM_CAD I304
R6164 402 61 59 RAM_CS_L<5> RAM_CS_DIMM_EC RAM_CSCKEODT RAM_CSCKEODT I242 70 69 68 63 RAM_RAS_L_R RAM_CAD RAM_CAD I303
10 RAM_Q63_128
61 59 RAM_CKE<1> 1 2 61 59 RAM_CS_L<8> RAM_CSCKEODT RAM_CSCKEODT I245 70 69 68 63 RAM_CAS_L_R RAM_CAD RAM_CAD I302
402 61 59 RAM_CS_L<9> RAM_CSCKEODT RAM_CSCKEODT I244 70 69 68 63 RAM_WE_L_R RAM_CAD RAM_CAD I301
SHARE PIN 2 PADS
70 69 68 63 61 RAM_CS_L_R<0> RAM_CSCKEODT RAM_CSCKEODT I238
67 61
67 61
RAM_CS_DIMM_A
RAM_CS_DIMM_B
RAM_CSCKEODT
RAM_CSCKEODT
RAM_CSCKEODT
RAM_CSCKEODT
I241
I575 RAM_CLK PRIMARY SPACING SET BASED ON DIFF IMPEDANCE
Parallel Term
R6125 RAM_CKE<0>
A 61 59 RAM_ODT<2> 1
10 2
RAM_M23_128
RAM_ODT_DIMM_A 61 67
61 59
61 59 RAM_CKE<1>
RAM_CKE_DIMM_ONBOARD_EC
RAM_CKE_DIMM_EC
RAM_CSCKEODT
RAM_CSCKEODT
RAM_CSCKEODT
RAM_CSCKEODT
I234
I236
RAM_CLK LINE-LINE SPACING SET TO 15MIL
TOTAL LENGTH TOLERENCE = 20PS = 2.82MM
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
R6165 402 61 59 RAM_CKE<4> RAM_CSCKEODT RAM_CSCKEODT I235
10 RAM_Q63_128 6 7 7 6 7 RAM_CAD SPACING IS 10MIL
61 59 RAM_ODT<4> 1 2 61 59 RAM_CKE<5> RAM_CSCKEODT RAM_CSCKEODT I237 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
RP6150 RP6152 RP6151 RP6151 RP6150 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402 RAM_CKE_R<0> RAM_CSCKEODT RAM_CSCKEODT AGREES TO THE FOLLOWING
SHARE PIN 2 PADS 240 240 240 240 240 70 69 68 63 62 61 I230
5% 5% 5% 5% 5% 67 62 61 RAM_CKE_DIMM_B RAM_CSCKEODT RAM_CSCKEODT I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W 1/16W 1/16W 1/16W 1/16W I592
SM-LF SM-LF SM-LF SM-LF SM-LF 67 62 61 RAM_CKE_DIMM_A RAM_CSCKEODT RAM_CSCKEODT I232 II NOT TO REPRODUCE OR COPY IT
SERIES R NEAR KODIAK 3 2 2 3 2
61 59 RAM_ODT<0> RAM_ODT_ONBOARD_EC RAM_CSCKEODT RAM_CSCKEODT I574 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
61 59 RAM_ODT<2> RAM_ODT_DIMM_EC RAM_CSCKEODT RAM_CSCKEODT I576
RPACK/RES NEAR/UNDER CONNECTOR SIZE DRAWING NUMBER REV.
61 59 RAM_ODT<4> RAM_CSCKEODT RAM_CSCKEODT I577
70 69 68 63 61 RAM_ODT_R<0> RAM_CSCKEODT RAM_CSCKEODT I593 D 051-6863 19
CS/CKE/ODT TERMINATION APPLE COMPUTER INC.
FOR DIMM STICK 67 61 RAM_ODT_DIMM_A RAM_CSCKEODT RAM_CSCKEODT I594
SCALE SHT OF
NONE 61 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
r y
C
7 =PP1V8_PWRON_RAM
R6200
1
5%
1/10W
MF-LF
603
1 2 RAMCLK_AVDD_R
VOLTAGE=1.8V
1
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
L6200
600-OHM-EMI
XW6200
1
SM
SM
2
2
1
RAMCLK_AVDD
C6200
4.7UF
20%
2 6.3V
CERM
603
6
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
RAMCLK_AVSS
1
VOLTAGE=0V
C6201 1 C6202
0.1UF
20%
2 10V
CERM
402
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
2200PF
5%
2 50V
CERM
603
RAM_CLK_OE
1
R6230
5%
10K
1/16W
MF-LF
2 402
H1 D2 D3 D4 E2 E5 F2 G2 G3 G4 G5
AVDD
F5 OE
D5 OS
VDD
CRITICAL
U6200
CDCU877
BGA
1
i
Y0 A2
Y0* A3
Y1 A1
Y1* B1
Y2 D1
Y2* C1
Y3 J1
n a
C6210
0.1UF
20%
10V
2 CERM
402
1 C6211
0.1UF
20%
10V
2 CERM
402
RAM_DIMM_A_CLK_P0
RAM_DIMM_A_CLK_N0
RAM_DIMM_A_CLK_P1
RAM_DIMM_A_CLK_N1
RAM_DIMM_A_CLK_P2
RAM_DIMM_A_CLK_N2
RAM_ONBOARD_CLK_P0_1
1 C6212
0.1UF
20%
10V
2 CERM
402
1
20%
10V
61 67
61 67
61 67
61 67
61 67
61 67
61 69
C6213
0.1UF
2 CERM
402
m
R6220 Y3* K1 RAM_ONBOARD_CLK_N0_1 61 69
1 2
100 1% E1 CK Y4 K3 RAM_ONBOARD_CLK_P2_3 61 69
61 59 RAM_CLKA_P
Y4* K2 RAM_ONBOARD_CLK_N2_3 61 69
il
61 59 RAM_CLKA_N F1 CK*
Y5 A5 RAM_ONBOARD_CLK_P4_5 61 70
Y5* A4 RAM_ONBOARD_CLK_N4_5 61 70
E6 FBIN Y6 A6 RAM_ONBOARD_CLK_P6_7 61 70
61 RAM_CLK_FBIN_P
F6 FBIN* Y6* B6 RAM_ONBOARD_CLK_N6_7 61 70
61 RAM_CLK_FBIN_N
R6221 Y7 D6
1 2 Y7* C6
100 1%
NOSTUFF Y8 J6
R6201 Y8* K6
0
e
61 7 =PP1V8_RUN_RAM 1 2 1V8_RUN_RAM_CKE 61
Y9 K4
5%
1/16W Y9* K5
MF-LF
402
3 4 FBOUT H6 RAM_CLK_FBOUT_P 61
B FBOUT* G6 RAM_CLK_FBOUT_N
B
r
D S 61
Q6201 AGND
GND
G 2N7002DW-X-F R6210
SOT-363
G1 B2 B3 B4 B5 C2 C5 H2 H5 J2 J3 J4 J5 0
5 1 2
R6211
1
0 2
PP5V_PWRON
P
7
1
R6242
1
1K
R6241 5%
1/16W
1K MF-LF
5% 2 402
1/16W
MF-LF 67 61 RAM_CKE_DIMM_A
2 402
NB_SUSPENDACK_L_5V
67 61 RAM_CKE_DIMM_B
6 70 69 68 63 61 RAM_CKE_R<0>
R6240 3
D Q6201
2N7002DW-X-F
10K SOT-363
30 20 NB_SUSPEND_ACK_L 1 2 1 Q6200 2 G S 3 3 3
5% 2N3904LF D Q6243 D Q6244 D Q6245
1/16W SOT23 1
MF-LF 2 2N7002 2N7002 2N7002
402 SOT23-LF SOT23-LF SOT23-LF
1 G S 1 G S 1 G S
NB_SUSPEND_ACK_L_R_5V
2 2 2
Main Memory Clock Buffer
NB_SUSPENDACK_5V
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
Q6243_S Q6244_S Q6245_S
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1
R6243 R6244 R6245 AGREES TO THE FOLLOWING
0 0 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0 5% 5%
5% 1/16W 1/16W II NOT TO REPRODUCE OR COPY IT
1/16W MF-LF MF-LF
MF-LF 2 402 2 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
2 402
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 62 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
70 69 68 61 RAM_A_R<0> 1 ZTA0 70 69 68 61 RAM_A_R<6> 1 ZTA6 70 69 68 61 RAM_A_R<12> 1 ZTA12 70 69 68 61 RAM_BA_R<0> 1 ZTBA0 70 69 68 61 RAM_CS_L_R<0> 1 ZTCS
1 ZTA0_R 1 ZTA6_R 1 ZTA12_R 1 ZTBA0_R 1 ZTCS_R
1 ZTA0_RR 1 ZTA6_RR 1 ZTA12_RR 1 ZTBA0_RR 1 ZTCS_RR
1 ZTA0_RL 1 ZTA6_RL 1 ZTA12_RL 1 ZTBA0_RL 1 ZTCS_RL
1 ZTA0_L 1 ZTA6_L 1 ZTA12_L 1 ZTBA0_L 1 ZTCS_L
1 ZTA0_LR 1 ZTA6_LR 1 ZTA12_LR 1 ZTBA0_LR 1 ZTCS_LR
D D
1 ZTA0_LL 1 ZTA6_LL 1 ZTA12_LL 1 ZTBA0_LL 1 ZTCS_LL
y
70 69 68 61 RAM_A_R<1> 1 ZTA1 70 69 68 61 RAM_A_R<7> 1 ZTA7 70 69 68 61 RAM_A_R<13> 1 ZTA13 70 69 68 61 RAM_BA_R<1> 1 ZTBA1 70 69 68 62 61 RAM_CKE_R<0> 1 ZTCKE
1 ZTA1_R 1 ZTA7_R 1 ZTA13_R 1 ZTBA1_R 1 ZTCKE_R
1 ZTA1_RR 1 ZTA7_RR 1 ZTA13_RR 1 ZTBA1_RR 1 ZTCKE_RR
r
1 ZTA1_RL 1 ZTA7_RL 1 ZTA13_RL 1 ZTBA1_RL 1 ZTCKE_RL
1 ZTA1_L 1 ZTA7_L 1 ZTA13_L 1 ZTBA1_L 1 ZTCKE_L
1 1 1 1 1
a
ZTA1_LR ZTA7_LR ZTA13_LR ZTBA1_LR ZTCKE_LR
1 ZTA1_LL 1 ZTA7_LL 1 ZTA13_LL 1 ZTBA1_LL 1 ZTCKE_LL
70 69 68 61 RAM_A_R<2> 1 ZTA2 70 69 68 61 RAM_A_R<8> 1 ZTA8 70 69 68 61 RAM_A_R<14> 1 ZTA14 70 69 68 61 RAM_BA_R<2> 1 ZTBA2 70 69 68 61 RAM_ODT_R<0> 1 ZTODT
1 ZTA2_R 1 ZTA8_R 1 ZTA14_R 1 ZTBA2_R 1 ZTODT_R
n
1 ZTA2_RR 1 ZTA8_RR 1 ZTA14_RR 1 ZTBA2_RR 1 ZTODT_RR
i
1 ZTA2_RL 1 ZTA8_RL 1 ZTA14_RL 1 ZTBA2_RL 1 ZTODT_RL
C 1 ZTA2_L 1 ZTA8_L 1 ZTA14_L 1 ZTBA2_L 1 ZTODT_L
C
1 ZTA2_LR 1 ZTA8_LR 1 ZTA14_LR 1 ZTBA2_LR 1 ZTODT_LR
1 ZTA2_LL 1 ZTA8_LL 1 ZTA14_LL 1 ZTBA2_LL 1 ZTODT_LL
70 69 68 61 RAM_A_R<3> 1 ZTA3 70 69 68 61 RAM_A_R<9> 1 ZTA9 70 69 68 61 RAM_A_R<15> 1 ZTA15 70 69 68 61 RAM_RAS_L_R 1 ZTRAS
m
1 ZTA3_R 1 ZTA9_R 1 ZTA15_R 1 ZTRAS_R
1 ZTA3_RR 1 ZTA9_RR 1 ZTA15_RR 1 ZTRAS_RR
il
1 ZTA3_RL 1 ZTA9_RL 1 ZTA15_RL 1 ZTRAS_RL
1 ZTA3_L 1 ZTA9_L 1 ZTA15_L 1 ZTRAS_L
1 ZTA3_LR 1 ZTA9_LR 1 ZTA15_LR 1 ZTRAS_LR
1 ZTA3_LL 1 ZTA9_LL 1 ZTA15_LL 1 ZTRAS_LL
e
70 69 68 61 RAM_A_R<4> 1 ZTA4 70 69 68 61 RAM_A_R<10> 1 ZTA10 70 69 68 61 RAM_CAS_L_R 1 ZTCAS
1 ZTA4_R 1 ZTA10_R 1 ZTCAS_R
1 ZTA4_RR 1 ZTA10_RR 1 ZTCAS_RR
B B
r
1 ZTA4_RL 1 ZTA10_RL 1 ZTCAS_RL
1 ZTA4_L 1 ZTA10_L 1 ZTCAS_L
1 ZTA4_LR 1 ZTA10_LR 1 ZTCAS_LR
P
1 ZTA4_LL 1 ZTA10_LL 1 ZTCAS_LL
70 69 68 61 RAM_A_R<5> 1 ZTA5 70 69 68 61 RAM_A_R<11> 1 ZTA11 70 69 68 61 RAM_WE_L_R 1 ZTWE
1 ZTA5_R 1 ZTA11_R 1 ZTWE_R
1 ZTA5_RR 1 ZTA11_RR 1 ZTWE_RR
1 ZTA5_RL 1 ZTA11_RL 1 ZTWE_RL
1 ZTA5_L 1 ZTA11_L 1 ZTWE_L
1 ZTA5_LR 1 ZTA11_LR 1 ZTWE_LR
1 ZTA5_LL 1 ZTA11_LL 1 ZTWE_LL
MEMORY ADDR BRANCHING
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 63 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
70 69 67 7 =PP1V8_PWRON_DIMM
VDDQ=1.8V
VDDQ=1.8V
VDD=1.8V
VDD=1.8V
R6701 1
56.2
D 1%
1/16W
MF-LF
1
516-0128
121
D
RAM_DIMM_VREF
402
2 MIN_LINE_WIDTH=1MM VREF J6700 VSS
y
2 122 RAM_DQ<88>
MIN_NECK_WIDTH=0.25MM
VSS F-RT-TH-LF DQ4 59 61
61 59 RAM_DQ<92> 3 (1 OF 2) DQ5 123 RAM_DQ<95> 59 61
C6720 DQ0
R6702 1
1
61 59 RAM_DQ<93> 4 CRITICAL VSS 124
56.2 1UF DQ1
1%
10% 5 125 DM0
1/16W 2
6.3V VSS DM0/DQS9
MF-LF
CERM
61 59 RAM_DQS_N<11> 6 126 NC
402 DQS0_L NC/DQS9_L
r
402
2 61 59 RAM_DQS_P<11> 7 127
DQS0 VSS
8 128 RAM_DQ<89>
DDR2-DIMM
59 61
VSS DQ6
VDDQ=1.8V
VDDQ=1.8V
61 59 RAM_DQ<91> 9 129 RAM_DQ<94> 59 61
DQ2 DQ7
VDD=1.8V
VDD=1.8V
61 59 RAM_DQ<90> 10 130
DQ3 VSS
11 131 RAM_DQ<70> 59 61
VSS DQ12
61 59 RAM_DQ<67> 12 132 RAM_DQ<69> 59 61
DQ8 DQ13
RAM_DQ<71> 13 133
a
61 59
DQ9 VSS
NOSTUFF 1
R6700
14
VSS DM1/DQS10
134
135
DM1 KEY
61 59 RAM_DQS_N<8> 15 NC
4.7K
1% 61 59 RAM_DQS_P<8> 16
DQS1_L
DQS1
NC/DQS10_L
VSS
136
65
VSS J6700 CK0 185
186
RAM_DIMM_A_CLK_P0 61 62
1/16W 66 RAM_DIMM_A_CLK_N0 61 62
MF-LF 17 137 RAM_DIMM_A_CLK_P1 61 62
VSS CK0_L
402
VSS CK1/RFU 67 F-RT-TH-LF VDD 187
2 RAM_DIMM_RST_L 18 138 RAM_DIMM_A_CLK_N1 VDD
NC/RST_L CK1_L/RFU 61 62
68 (2 OF 2) 188 RAM_A<0> 59 61 68
NC 19 139 NC/PAR_IN A0
NC1 VSS 69 189
DDR2-DIMM
FOR REG DIMMS ONLY 3 20 140 VDD VDD
VSS DQ14 RAM_DQ<68> 59 61
190
RAM_A<10> 70 RAM_BA<1>
n
NOSTUFF 21 141 68 61 59 A10/AP BA1 59 61 68
D
Q6700 61 59 RAM_DQ<66> DQ10 DQ15 RAM_DQ<64> 59 61
191
68 61 59 RAM_BA<0> 71
2N7002 61 59 RAM_DQ<65> 22 142 BA0 VDDQ
SOT23-LF
DQ11 VSS 72 192 RAM_RAS_L 59 61 68
30 SMU_IO_RESET 1 G S 23 143 RAM_DQ<79> 59 61
VDDQ RAS_L
VSS DQ20 68 61 59 RAM_WE_L 73 193 RAM_CS_DIMM_A 61
WE_L S0_L
i
61 59 RAM_DQ<73> 24 144 RAM_DQ<78> 59 61
2
DQ16 DQ21 68 61 59 RAM_CAS_L 74 194
61 59 RAM_DQ<75> 25 145 CAS_L VDDQ
DQ17 VSS 75 195 RAM_ODT_DIMM_A 61
26 146 VDDQ ODT0
C 61 59 RAM_DQS_N<9> 27
VSS
DQS2_L
DM2/DQS11
NC/DQS11_L
147
DM2
NC
61 RAM_CS_DIMM_B
ODT
76
77
S1_L NC/A13
196
197
RAM_A<13> 59 61 68 C
61 59 RAM_DQS_P<9> 28 148 ODT1 VDD
DQS2 VSS 78 198
29 149 RAM_DQ<72> 59 61
VDDQ VSS
VSS DQ22 79 199 RAM_DQ<99> 59 61
61 59 RAM_DQ<76> 30 150 RAM_DQ<74> 59 61
VSS DQ36
DQ18 DQ23 61 59 RAM_DQ<100> 80 200 RAM_DQ<97> 59 61
61 59 RAM_DQ<77> 31 151 DQ32 DQ37
DQ19 VSS 61 59 RAM_DQ<102> 81 201
32 152 RAM_DQ<86> 59 61
DQ33 VSS
VSS DQ28 82 202 DM4
61 59 RAM_DQ<87> 33 153 RAM_DQ<83> 59 61
VSS DM4/DQS13
DQ24 DQ29 61 59 RAM_DQS_N<12> 83 203 NC
61 59 RAM_DQ<81> 34 154 DQS4_L NC/DQS13_L
DQ25 VSS RAM_DQS_P<12> 84 204
m
61 59 DQS4 VSS
35 155 DM3
VSS DM3/DQS12 85 205 RAM_DQ<98> 59 61
61 59 RAM_DQS_N<10> 36 156 NC VSS DQ38
DQS3_L NC/DQS12_L 61 59 RAM_DQ<101> 86 206 RAM_DQ<103> 59 61
61 59 RAM_DQS_P<10> 37 157 DQ34 DQ39
DQS3 VSS 61 59 RAM_DQ<96> 87 207
38 DQ35 VSS
il
158 RAM_DQ<84> 59 61
VSS DQ30 88 208 RAM_DQ<107> 59 61
61 59 RAM_DQ<80> 39 159 RAM_DQ<85> 59 61
VSS DQ44
DQ26 DQ31 61 59 RAM_DQ<111> 89 209 RAM_DQ<108> 59 61
61 59 RAM_DQ<82> 40 160 DQ40 DQ45
DQ27 VSS 61 59 RAM_DQ<105> 90 210
41 161 ECC DQ41 VSS
VSS CB4 91 211 DM5
ECC 42 162 ECC VSS DM5/DQS14
NC/CB0 CB5 61 59 RAM_DQS_N<13> 92 212 NC
ECC 43 163 DQS5_L NC/DQS14_L
NC/CB1 VSS 61 59 RAM_DQS_P<13> 93 213
44 164 DM8 DQS5 VSS
VSS DM8/DQS17 94 214 RAM_DQ<110> 59 61
ECC 45 165 NC VSS DQ46
DQS8_L NC/DQS17_L 61 59 RAM_DQ<109> 95 215 RAM_DQ<106> 59 61
ECC 46 166 DQ42 DQ47
DQS8 VSS 61 59 RAM_DQ<104> 96 216
47 167 ECC DQ43 VSS
VSS NC/CB6 97 217 RAM_DQ<115> 59 61
48 168 VSS DQ52
e
ECC NC/CB2 NC/CB7 ECC RAM_DQ<117> 98 218 RAM_DQ<116>
61 59 DQ48 DQ53 59 61
ECC 49 169
NC/CB3 VSS 61 59 RAM_DQ<114> 99 219
50 170 DQ49 VSS
VSS VDDQ 100 220 RAM_DIMM_A_CLK_P2 61 62
51 171 RAM_CKE_DIMM_B 61 62
VSS CK2/RFU
VDDQ CKE1 SA2 101 221 RAM_DIMM_A_CLK_N2 61 62
62 61 RAM_CKE_DIMM_A 52 172 SA2 CK2_L/RFU
B CKE0 VDD NC 102 222
B
r
53 173 RAM_A<15> 59 61 68
NCTEST VSS
VDD NC2 103 223 DM6
68 61 59 RAM_BA<2> 54 174 RAM_A<14> 59 61 68
VSS DM6/DQS15
NC/BA2 NC3 61 59 RAM_DQS_N<14> 104 224 NC
NC 55 175 DQS6_L NC/DQS15_L
NC/ERR_L VDDQ 61 59 RAM_DQS_P<14> 105 225
56 176 RAM_A<12> 59 61 68
DQS6 VSS
VDDQ A12 106 226 RAM_DQ<113> 59 61
68 61 59 RAM_A<11> 57 177 RAM_A<9> 59 61 68
VSS DQ54
A11 A9 61 59 RAM_DQ<118> 107 227 RAM_DQ<119> 59 61
68 61 59 RAM_A<7> 58 178 DQ50 DQ55
A7 VDD 61 59 RAM_DQ<112> 108 228
59 179 RAM_A<8> 59 61 68
DQ51 VSS
VDD A8 109 229 RAM_DQ<125> 59 61
68 61 59 RAM_A<5> 60 180 RAM_A<6> 59 61 68
VSS DQ60
A5 A6 RAM_DQ<127> 110 230 RAM_DQ<126>
P
61 59 59 61
68 61 59 RAM_A<4> 61 181 DQ56 DQ61
A4 VDDQ 61 59 RAM_DQ<122> 111 231
62 182 RAM_A<3> 59 61 68
DQ57 VSS
VDDQ A3 112 232 DM7
68 61 59 RAM_A<2> 63 183 RAM_A<1> 59 61 68
VSS DM7/DQS16
A2 A1 61 59 RAM_DQS_N<15> 113 233 NC
64 184 DQS7_L NC/DQS16_L
VDD VDD 61 59 RAM_DQS_P<15> 114 234
DQS7 VSS
115 235 RAM_DQ<121> 59 61
KEY 61 59 RAM_DQ<124> 116
VSS
DQ58
DQ62
DQ63
236 RAM_DQ<123> 59 61
61 59 RAM_DQ<120> 117 237
DQ59 VSS
118 238 =PP1V8_PWRON_RAM_I2C_VDD 7
VSS VDDSPD
39
I2C_NB_RAM_SDA 119 239 RAM_DIMM_A_SA0 R6704
SDA SA0 10K
39
I2C_NB_RAM_SCL 120 240 1 2 1
C6715
SCL SA1 SA1
5% 0.22UF
1/16W 20%
6.3V
ADDR=2 (A4/A5) MF-LF 2 X5R
402
402
Memory Dimm A
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PLACE CAPS CLOSE TO VDD/VDDQ PINS OF DIMM SOCKET PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
70 69 67 7 =PP1V8_PWRON_DIMM
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1
C6701 1
C6702 1
C6703 1
C6704 1
C6705 1
C6706 1
C6707 1
C6708 1
C6709 1
C6710 1
C6711 1
C6712 1
C6713 1
C6714 1
C6719 1
C6721 1
C6722
2.2UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 2.2UF 0.22UF 0.22UF 0.22UF SIZE DRAWING NUMBER REV.
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM1
603
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402
2 CERM1
603
2 X5R
402
2 X5R
402
2 X5R
402
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
67 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ONBOARD MEMORY SHOULD FOLLOW SPEC FOR RAW CARD VERSION A
1 8 RP6824
4 5 RP6800 67 61 59 RAM_A<0> 5.1 RAM_A_R<0> 61 63 69 70
61 59 RAM_DQ<0> 22 RAM_DQ_R<0> 61 69 RP6823 1 ZT6800
RAM_A<1> 5.1 1 8 RAM_A_R<1>
3 6 RP6800 67 61 59 61 63 69 70
61 59 RAM_DQ<1> 22 RAM_DQ_R<1> 6 61 69
2 7 RP6823 1 ZT6801
1 8 RP6801 67 61 59 RAM_A<2> 5.1 RAM_A_R<2> 61 63 69 70
61 59 RAM_DQ<2> 22 RAM_DQ_R<2> 6 61 69 RP6822 1 ZT6802
RAM_A<3> 5.1 4 5 RAM_A_R<3>
RAM_DQ<3> 22 3 6 RP6801 RAM_DQ_R<3>
67 61 59 61 63 69 70
1
61 59 6 61 69
3 6 RP6822 ZT6803
4 5 RP6801 67 61 59 RAM_A<4> 5.1 RAM_A_R<4> 61 63 69 70
61 59 RAM_DQ<4> 22 RAM_DQ_R<4> 61 69 RP6822 1 ZT6804
RAM_A<5> 5.1 2 7 RAM_A_R<5>
2 7 RP6800 67 61 59 61 63 69 70
1
61 59 RAM_DQ<5> 22 RAM_DQ_R<5> 6 61 69 RP6822 ZT6805
RAM_A<6> 5.1 1 8 RAM_A_R<6>
RAM_DQ<6> 22 2 7 RP6801 RAM_DQ_R<6>
67 61 59 61 63 69 70
1
61 59 6 61 69 RP6821 ZT6806
D 61 59 RAM_DQ<7> 22 1
3
8
6
RP6800
RP6802
RAM_DQ_R<7> 6 61 69
67 61 59
67 61 59
RAM_A<7>
RAM_A<8>
5.1
5.1
3
4
6
5 RP6821
RAM_A_R<7>
RAM_A_R<8>
61 63 69 70
61 63 69 70
1 ZT6807 D
61 59 RAM_DQ<8> 22 RAM_DQ_R<8> 6 61 69
1 8 RP6821 1 ZT6808
RP6803 67 61 59 RAM_A<9> 5.1 RAM_A_R<9> 61 63 69 70
y
RAM_DQ<9> 22 4 5 RAM_DQ_R<9> 1 ZT6809
61 59 6 61 69
RAM_A<10> 5.1 3 6 RP6824 RAM_A_R<10>
1 8 RP6803 67 61 59 61 63 69 70
1
61 59 RAM_DQ<10> 22 RAM_DQ_R<10> 61 69
2 7 RP6821 ZT6810
4 5 RP6802 67 61 59 RAM_A<11> 5.1 RAM_A_R<11> 61 63 69 70
61 59 RAM_DQ<11> 22 RAM_DQ_R<11> 6 61 69 RP6820 1 ZT6811
RAM_A<12> 5.1 4 5 RAM_A_R<12>
3 6 RP6803 67 61 59 61 63 69 70
61 59 RAM_DQ<12> 22 RAM_DQ_R<12> 6 61 69 RP6825 1 ZT6812
RAM_A<13> 5.1 4 5 RAM_A_R<13>
2 7 RP6802 67 61 59 61 63 69 70
1
61 59 RAM_DQ<13> 22 RAM_DQ_R<13> 6 61 69 RP6820 ZT6813
2 7
r
2 7 RP6803 67 61 59 RAM_A<14> 5.1 RAM_A_R<14> 61 63 69 70
61 59 RAM_DQ<14> 22 RAM_DQ_R<14> 6 61 69
1 8 RP6820 1 ZT6814
1 8 RP6802 67 61 59 RAM_A<15> 5.1 RAM_A_R<15> 61 63 69 70
61 59 RAM_DQ<15> 22 RAM_DQ_R<15> 61 69 1 ZT6815
3 6 RP6805
61 59 RAM_DQ<16> 22 RAM_DQ_R<16> 6 61 69
4 5 RP6805 VIAS FOR ECC STUB
61 59 RAM_DQ<17> 22 RAM_DQ_R<17> 6 61 69
1 8 RP6804
61 59 RAM_DQ<18> 22 RAM_DQ_R<18> 61 69
RAM_DQ<19> 22 2 7 RP6805 RAM_DQ_R<19>
61 59 6 61 69
RAM_DQ<20> 22 2 7 RP6804 RAM_DQ_R<20>
a
61 59 6 61 69
4 5 RP6804
61 59 RAM_DQ<21> 22 RAM_DQ_R<21> 6 61 69
RAM_DQ<22> 22 3 6 RP6804 RAM_DQ_R<22>
61 59 6 61 69
1 8 RP6805
61 59 RAM_DQ<23> 22 RAM_DQ_R<23> 61 69
4 5 RP6807
61 59 RAM_DQ<24> 22 RAM_DQ_R<24> 6 61 69
RAM_DQ<25> 22 2 7 RP6806 RAM_DQ_R<25>
61 59 6 61 69
4 5 RP6806
61 59 RAM_DQ<26> 22 RAM_DQ_R<26> 61 69
1 8 RP6807
61 59 RAM_DQ<27> 22 RAM_DQ_R<27> 61 69
n
RAM_DQ<28> 22 3 6 RP6807 RAM_DQ_R<28>
61 59 6 61 69
4 5 RP6824
RP6806 67 61 59 RAM_BA<0> 5.1 RAM_BA_R<0> 61 63 69
61 59 RAM_DQ<29> 22 3 6 RAM_DQ_R<29> 6 61 69 70 1 ZT6820
RAM_DQ<30> 22 2 7 RP6807 RAM_DQ_R<30>
61 59 6 61 69
RP6806
i
61 59 RAM_DQ<31> 22 1 8 RAM_DQ_R<31> 6 61 69
4 5 RP6809 2 7 RP6824
61 59 RAM_DQ<32> 22 RAM_DQ_R<32> 6 61 70 67 61 59 RAM_BA<1> 5.1 RAM_BA_R<1> 61 63 69 70
2 7 RP6808 1
ZT6821
C 61 59
61 59
RAM_DQ<33>
RAM_DQ<34>
22
22 3 6 RP6808
RAM_DQ_R<33>
RAM_DQ_R<34>
6 61 70
6 61 70
C
1 8 RP6809
61 59 RAM_DQ<35> 22 RAM_DQ_R<35> 61 70
3 6 RP6820
2 7 RP6809 67 61 59 RAM_BA<2> 5.1 RAM_BA_R<2> 61 63 69
61 59 RAM_DQ<36> 22 RAM_DQ_R<36> 6 61 70 70 1 ZT6822
1 8 RP6808
61 59 RAM_DQ<37> 22 RAM_DQ_R<37> 6 61 70
3 6 RP6809
61 59 RAM_DQ<38> 22 RAM_DQ_R<38> 6 61 70
RAM_DQ<39> 22 4 5 RP6808 RAM_DQ_R<39>
61 59 61 70
4 5 RP6810
61 59 RAM_DQ<40> 22 RAM_DQ_R<40> 6 61 70
RAM_DQ<41> 22 3 6 RP6811 RAM_DQ_R<41> RAM_RAS_L 5.1 1 8 RP6825 RAM_RAS_L_R
61 59 6 61 70 67 61 59 61 63 69
1
m
70 ZT6825
RAM_DQ<42> 22 1 8 RP6811 RAM_DQ_R<42>
61 59 61 70
2 7 RP6810
61 59 RAM_DQ<43> 22 RAM_DQ_R<43> 6 61 70
RAM_DQ<44> 22 4 5 RP6811 RAM_DQ_R<44>
61 59 6 61 70
3 6 RP6825
RP6810 67 61 59 RAM_CAS_L 5.1 RAM_CAS_L_R 61 63 69
il
61 59 RAM_DQ<45> 22 3 6 RAM_DQ_R<45> 6 61 70 70 1 ZT6826
2 7 RP6811
61 59 RAM_DQ<46> 22 RAM_DQ_R<46> 6 61 70
RAM_DQ<47> 22 1 8 RP6810 RAM_DQ_R<47>
61 59 61 70
3 6 RP6812 2 7 RP6825
61 59 RAM_DQ<48> 22 RAM_DQ_R<48> 6 61 70 67 61 59 RAM_WE_L 5.1 RAM_WE_L_R 61 63 69
RP6812 70 1 ZT6827
61 59 RAM_DQ<49> 22 4 5 RAM_DQ_R<49> 6 61 70
RAM_DQ<50> 22 2 7 RP6813 RAM_DQ_R<50>
61 59 6 61 70
1 8 RP6813
61 59 RAM_DQ<51> 22 RAM_DQ_R<51> 61 70
3 6 RP6813 VIAS FOR ECC STUB
61 59 RAM_DQ<52> 22 RAM_DQ_R<52> 6 61 70
RAM_DQ<53> 22 4 5 RP6813 RAM_DQ_R<53>
61 59 6 61 70
2 7 RP6812
61 59 RAM_DQ<54> 22 RAM_DQ_R<54> 6 61 70
1 8 RP6812
e
61 59 RAM_DQ<55> 22 RAM_DQ_R<55> 61 70
3 6 RP6814
61 59 RAM_DQ<56> 22 RAM_DQ_R<56> 6 61 70
4 5 RP6815
61 59 RAM_DQ<57> 22 RAM_DQ_R<57> 6 61 70
RAM_DQ<58> 22 2 7 RP6815 RAM_DQ_R<58>
61 59 6 61 70
3 6 RP6815
61 59 RAM_DQ<59> 22 RAM_DQ_R<59> 6 61 70
B B
r
2 7 RP6814
61 59 RAM_DQ<60> 22 RAM_DQ_R<60> 6 61 70
RAM_DQ<61> 22 1 8 RP6814 RAM_DQ_R<61>
61 59 61 70
1 8 RP6815
61 59 RAM_DQ<62> 22 RAM_DQ_R<62> 61 70
RAM_DQ<63> 22 4 5 RP6814 RAM_DQ_R<63>
61 59 6 61 70
61 59 RAM_DQS_P<0> 22 1 2 R6800 DIFFERENTIAL_PAIR=RAM_DQS_R_0_DP
RAM_DQS_P_R<0> 61 69
61 59 RAM_DQS_N<0> 22 1 2 R6810 DIFFERENTIAL_PAIR=RAM_DQS_R_0_DP
RAM_DQS_N_R<0> 61 69
RAM_DQS_P<1> 22 1 2 R6801 DIFFERENTIAL_PAIR=RAM_DQS_R_1_DP
RAM_DQS_P_R<1>
P
61 59 61 69
61 59 RAM_DQS_N<1> 22 1 2 R6811 DIFFERENTIAL_PAIR=RAM_DQS_R_1_DP
RAM_DQS_N_R<1> 61 69 PLACE NEAR KODIAK PLACE AT END POINT
1 2 R6802 DIFFERENTIAL_PAIR=RAM_DQS_R_2_DP PRIOR TO BRANCH TO SIMULATE ECC
61 59 RAM_DQS_P<2> 22 RAM_DQS_P_R<2> 61 69
61 59 RAM_DQS_N<2> 22 1 2 R6812 DIFFERENTIAL_PAIR=RAM_DQS_R_2_DP
RAM_DQS_N_R<2> 61 69 RAM_CS_L_R<0> 61 63 69 70
61 59 RAM_DQS_P<3> 22 1 2 R6803 DIFFERENTIAL_PAIR=RAM_DQS_R_3_DP
RAM_DQS_P_R<3> 61 69
C6870 C6871
RAM_DQS_N<3> 1 2 R6813 DIFFERENTIAL_PAIR=RAM_DQS_R_3_DP
RAM_DQS_N_R<3>
24PF 2PF
61 59 22 61 69
1 2 1 2
61 59 RAM_DQS_P<4> 22 1 2 R6804 DIFFERENTIAL_PAIR=RAM_DQS_R_4_DP
RAM_DQS_P_R<4> 61 70
61 59 RAM_DQS_N<4> 22 1 2 R6814 DIFFERENTIAL_PAIR=RAM_DQS_R_4_DP
RAM_DQS_N_R<4> 61 70
5% +/-0.25PF
50V 50V
61 59 RAM_DQS_P<5> 22 1 2 R6805 DIFFERENTIAL_PAIR=RAM_DQS_R_5_DP
RAM_DQS_P_R<5> 61 70
C0G
402
C0G
402-1
61 59 RAM_DQS_N<5> 22 1 2 R6815 DIFFERENTIAL_PAIR=RAM_DQS_R_5_DP
RAM_DQS_N_R<5> 61 70
R6806 DIFFERENTIAL_PAIR=RAM_DQS_R_6_DP RAM_CKE_R<0> 61 62 63 69 70
RAM_DQS_P<6> 22 1 2 RAM_DQS_P_R<6>
61 59
R6816 DIFFERENTIAL_PAIR=RAM_DQS_R_6_DP
61 70
C6880 C6881
61 59 RAM_DQS_N<6> 22 1 2 RAM_DQS_N_R<6> 61 70 24PF 2PF
61 59 RAM_DQS_P<7> 22 1 2 R6807 DIFFERENTIAL_PAIR=RAM_DQS_R_7_DP
RAM_DQS_P_R<7> 61 70
1 2 1 2
61 59 RAM_DQS_N<7> 22 1 2 R6817 DIFFERENTIAL_PAIR=RAM_DQS_R_7_DP
RAM_DQS_N_R<7> 61 70
5% +/-0.25PF
50V 50V
C0G C0G
402 402-1
C6890 C6891
RAM_ODT_R<0> 61 63 69 70 MLB Mem Series Term
24PF 2PF
A 1 2 1 2
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
5% +/-0.25PF
50V 50V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
C0G C0G PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402 402-1 AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 68 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V8_PWRON_DIMM
70 69 67 7 =PP1V8_PWRON_DIMM 1 C6901 1 C6902 1 C6903 1 C6904
70 69 67 7
1 C6911 1 C6912 1 C6913 1 C6914
2.2UF 0.22UF 0.22UF 0.22UF
2.2UF 0.22UF 0.22UF 0.22UF
E1
A1
E9
H9
L1
A9
C1
C3
C7
C9
DOES VDDL NEED A SPECIAL FILTER? 20% 20% 20% 20%
E1
A1
E9
H9
L1
A9
C1
C3
C7
C9
20%
10V
20%
6.3V
20%
6.3V
20%
6.3V 2 10V
CERM 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
1
2 CERM 2 X5R 2 X5R 2 X5R CHECK DECOUPLING - TRY TO MATCH SINGLE RANK DIMM VDDL VDD VDDQ 805 402 402 402
ZTCLK0_P VDDL VDD VDDQ 805 402 402 402
ZTCLK0_N 1
RAM_ONBOARD_CLK_P0_1 E8 CK B7 RAM_DQS_P_R<1>
RAM_ONBOARD_CLK_P0_1 E8 CK B7 RAM_DQS_P_R<0>
69 62 61 DQS 61 68
69 62 61 DQS 61 68
RAM_ONBOARD_CLK_N0_1 F8 CK* A8 RAM_DQS_N_R<1>
RAM_ONBOARD_CLK_N0_1 F8 CK* A8 RAM_DQS_N_R<0>
69 62 61
DQS* 61 68
69 62 61 DQS* 61 68
RAM_CKE_R<0> F2 CKE B3
RAM_CKE_R<0> F2 CKE B3 70 69 68 63 62 61
OMIT DM/RDQS
70 69 68 63 62 61
OMIT DM/RDQS A2
NU/RDQS*
RAM_A_R<0> H8 A0 U6900 NU/RDQS*
A2 70 69 68 63 61 RAM_A_R<0> H8 A0 U6910 D
D 70 69 68 63 61
70 69 68 63 61 RAM_A_R<1> H3
H7
A1 DQ0
SDRAM-64MX8-DDR2-533 DQ1
C8
C2
RAM_DQ_R<3> 6 61 68
70 69 68 63 61
70 69 68 63 61
RAM_A_R<1>
RAM_A_R<2>
H3
H7
A1
A2
DQ0
SDRAM-64MX8-DDR2-533 DQ1
C8
C2
RAM_DQ_R<12>
RAM_DQ_R<8>
6 61 68
6 61 68
70 69 68 63 61 RAM_A_R<2> A2 RAM_DQ_R<1> 6 61 68 HY5PS12821BPF-C4
y
RAM_A_R<3> J2 A3 DQ2 D7 RAM_DQ_R<14>
70 69 68 63 61 RAM_A_R<3> J2 A3 HY5PS12821BPF-C4 DQ2 D7 RAM_DQ_R<6> 6 61 68
70 69 68 63 61
J8 CSP D3
6 61 68
J8 CSP D3 70 69 68 63 61 RAM_A_R<4> A4 DQ3 RAM_DQ_R<15> 61 68
70 69 68 63 61 RAM_A_R<4> A4 DQ3 RAM_DQ_R<7> 6 61 68
J3 D1
J3 D1 70 69 68 63 61 RAM_A_R<5> A5 DQ4 RAM_DQ_R<13> 6 61 68
70 69 68 63 61 RAM_A_R<5> A5 DQ4 RAM_DQ_R<5> 6 61 68
J7 D9
J7 D9 70 69 68 63 61 RAM_A_R<6> A6 DQ5 RAM_DQ_R<10> 61 68
70 69 68 63 61 RAM_A_R<6> A6 DQ5 RAM_DQ_R<2> 6 61 68
K2 B1
K2 B1 70 69 68 63 61 RAM_A_R<7> A7 DQ6 RAM_DQ_R<11> 6 61 68
DQ6
r
70 69 68 63 61 RAM_A_R<7> A7 RAM_DQ_R<0> 61 68
K8 B9
K8 B9 70 69 68 63 61 RAM_A_R<8> A8 DQ7 RAM_DQ_R<9> 6 61 68
70 69 68 63 61 RAM_A_R<8> A8 DQ7 RAM_DQ_R<4> 61 68
K3
K3 70 69 68 63 61 RAM_A_R<9> A9 G8
70 69 68 63 61 RAM_A_R<9> A9 G8 RAM_CS_L_R<0> RAM_A_R<10> H2 CS* RAM_CS_L_R<0> 61 63 68 69 70
RAM_A_R<10> H2 CS* 61 63 68 69 70 70 69 68 63 61 A10
70 69 68 63 61 A10 RAM_A_R<11> K7 A11 F7 RAM_RAS_L_R
K7 F7 70 69 68 63 61 RAS* 61 63 68 69 70
70 69 68 63 61 RAM_A_R<11> A11 RAS* RAM_RAS_L_R 61 63 68 69 70
L2 G7
L2 G7 70 69 68 63 61 RAM_A_R<12> A12 CAS* RAM_CAS_L_R 61 63 68 69 70
70 69 68 63 61 RAM_A_R<12> A12 CAS* RAM_CAS_L_R 61 63 68 69 70
RAM_A_R<13> L8 F3 RAM_WE_L_R
RAM_A_R<13> L8 F3 RAM_WE_L_R
70 69 68 63 61 NC/A13 WE* 61 63 68 69 70
70 69 68 63 61 NC/A13 WE* 61 63 68 69 70
RAM_A_R<14> L3 NC/A14
a
70 69 68 63 61
70 69 68 63 61 RAM_A_R<14> L3 NC/A14
70 69 68 63 61 RAM_A_R<15> L7 NC/A15
RAM_A_R<15> L7 NC/A15 F9 RAM_ODT_R<0>
70 69 68 63 61
F9 RAM_ODT_R<0> ODT 61 63 68 69 70
ODT 61 63 68 69 70
70 69 68 63 61 RAM_BA_R<0> G2 BA0
70 69 68 63 61 RAM_BA_R<0> G2 BA0
70 69 68 63 61 RAM_BA_R<1> G3 BA1
70 69 68 63 61 RAM_BA_R<1> G3 BA1
70 69 68 63 61 RAM_BA_R<2> G1 NC/BA2 VREF E2 PPVREF_RAM_ONBOARD_0123 69
70 69 68 63 61 RAM_BA_R<2> G1 NC/BA2 VREF E2 PPVREF_RAM_ONBOARD_0123 69
VSSDL VSS VSSQ 1 C6910
VSSDL VSS VSSQ 1 C6900 R6919
1UF
E7
K9
J1
E3
A3
D8
D2
B8
B2
A7
n
R6909 1UF
E7
K9
J1
E3
A3
D8
D2
B8
B2
A7
1 2 10%
1 2 10%
6.3V TERM RESISTOR FOR DRAM 2 6.3V
CERM
2 CERM 200 402
200 402 C6919
ZTCLK0_L_P 1 1 ZTCLK0_L_N
C6909 2PF
i
2PF 1 2
1 2 INCREASE TO 2PF FOR NON-ECC
ZTCLK0_R_P 1 1 ZTCLK0_R_N OTHERWISE 1PF
C ZTCLK0_M_P 1
R6914
1 ZTCLK0_M_N C
TERM RESISTOR FOR ECC STUB 1 2
200
1 ZT6900
VIAS TO SIMULATE ECC STUB 1
ZT6910
70 69 67 7 =PP1V8_PWRON_DIMM
1 C6921
2.2UF
1 C6922
0.22UF
1 C6923
0.22UF
1
il m
C6924
0.22UF
70 69 67 7 =PP1V8_PWRON_DIMM
1 C6931
2.2UF
1 C6932
0.22UF
1 C6933
0.22UF
1 C6934
0.22UF
E1
A1
E9
H9
L1
A9
C1
C3
C7
C9
E1
A1
E9
H9
L1
A9
C1
C3
C7
C9
20% 20% 20% 20% 20% 20% 20% 20%
10V 6.3V 6.3V 6.3V 10V 6.3V 6.3V 6.3V
2 CERM 2 X5R 2 X5R 2 X5R 2 CERM 2 X5R 2 X5R 2 X5R
ZTCLK2_P 1
VDDL VDD VDDQ 805 402 402 402 VDDL VDD VDDQ 805 402 402 402
ZTCLK2_N 1
E8 B7 E8 B7
e
69 62 61 RAM_ONBOARD_CLK_P2_3 CK DQS RAM_DQS_P_R<2> 61 68 69 62 61 RAM_ONBOARD_CLK_P2_3 CK DQS RAM_DQS_P_R<3> 61 68
RAM_ONBOARD_CLK_N2_3 F8 CK* A8 RAM_DQS_N_R<2> RAM_ONBOARD_CLK_N2_3 F8 CK* A8 RAM_DQS_N_R<3>
69 62 61
DQS* 61 68 69 62 61
DQS* 61 68
RAM_CKE_R<0> F2 CKE B3 RAM_CKE_R<0> F2 CKE B3
70 69 68 63 62 61
OMIT DM/RDQS 70 69 68 63 62 61
OMIT DM/RDQS
A2 A2
NU/RDQS* NU/RDQS*
B
70 69 68 63 61 RAM_A_R<0> H8 A0 U6920 70 69 68 63 61 RAM_A_R<0> H8 A0 U6930 B
r
70 69 68 63 61 RAM_A_R<1> H3 A1 DQ0 C8 RAM_DQ_R<22> 6 61 68 70 69 68 63 61 RAM_A_R<1> H3 A1 DQ0 C8 RAM_DQ_R<28> 6 61 68
70 69 68 63 61 RAM_A_R<2> H7 A2
SDRAM-64MX8-DDR2-533 DQ1 C2 RAM_DQ_R<16> 6 61 68 70 69 68 63 61 RAM_A_R<2> H7 A2
SDRAM-64MX8-DDR2-533 DQ1 C2 RAM_DQ_R<29> 6 61 68
70 69 68 63 61 RAM_A_R<3> J2 A3 HY5PS12821BPF-C4 DQ2 D7 RAM_DQ_R<20> 6 61 68 70 69 68 63 61 RAM_A_R<3> J2 A3 HY5PS12821BPF-C4 DQ2 D7 RAM_DQ_R<30> 6 61 68
70 69 68 63 61 RAM_A_R<4> J8 A4 CSP DQ3 D3 RAM_DQ_R<23> 61 68 70 69 68 63 61 RAM_A_R<4> J8 A4 CSP DQ3 D3 RAM_DQ_R<31> 6 61 68
70 69 68 63 61 RAM_A_R<5> J3 A5 DQ4 D1 RAM_DQ_R<19> 6 61 68 70 69 68 63 61 RAM_A_R<5> J3 A5 DQ4 D1 RAM_DQ_R<25> 6 61 68
70 69 68 63 61 RAM_A_R<6> J7 A6 DQ5 D9 RAM_DQ_R<18> 61 68 70 69 68 63 61 RAM_A_R<6> J7 A6 DQ5 D9 RAM_DQ_R<27> 61 68
70 69 68 63 61 RAM_A_R<7> K2 A7 DQ6 B1 RAM_DQ_R<17> 6 61 68 70 69 68 63 61 RAM_A_R<7> K2 A7 DQ6 B1 RAM_DQ_R<26> 61 68
70 69 68 63 61 RAM_A_R<8> K8 A8 DQ7 B9 RAM_DQ_R<21> 6 61 68 70 69 68 63 61 RAM_A_R<8> K8 A8 DQ7 B9 RAM_DQ_R<24> 6 61 68
P
70 69 68 63 61 RAM_A_R<9> K3 A9 70 69 68 63 61 RAM_A_R<9> K3 A9
CS* G8 RAM_CS_L_R<0> 61 63 68 69 70 CS* G8 RAM_CS_L_R<0> 61 63 68 69 70
70 69 68 63 61 RAM_A_R<10> H2 A10 70 69 68 63 61 RAM_A_R<10> H2 A10
70 69 68 63 61 RAM_A_R<11> K7 A11 RAS* F7 RAM_RAS_L_R 61 63 68 69 70 70 69 68 63 61 RAM_A_R<11> K7 A11 RAS* F7 RAM_RAS_L_R 61 63 68 69 70
70 69 68 63 61 RAM_A_R<12> L2 A12 CAS* G7 RAM_CAS_L_R 61 63 68 69 70 70 69 68 63 61 RAM_A_R<12> L2 A12 CAS* G7 RAM_CAS_L_R 61 63 68 69 70
L8 F3 1 L8 F3
70 69 68 63 61 RAM_A_R<13>
L3
NC/A13 WE* RAM_WE_L_R 61 63 68 69 70 R6925 70 69 68 63 61 RAM_A_R<13>
L3
NC/A13 WE* RAM_WE_L_R 61 63 68 69 70
70 69 68 63 61 RAM_A_R<14> NC/A14 56.2 70 69 68 63 61 RAM_A_R<14> NC/A14
L7 1% L7
70 69 68 63 61 RAM_A_R<15> NC/A15 F9 1/16W 70 69 68 63 61 RAM_A_R<15> NC/A15 F9
ODT RAM_ODT_R<0> 61 63 68 69 70 MF-LF ODT RAM_ODT_R<0> 61 63 68 69 70
70 69 68 63 61 RAM_BA_R<0> G2 BA0 2 402 70 69 68 63 61 RAM_BA_R<0> G2 BA0
70 69 68 63 61 RAM_BA_R<1> G3 BA1 70 69 68 63 61 RAM_BA_R<1> G3 BA1
70 69 68 63 61 RAM_BA_R<2> G1 NC/BA2 VREF E2 69 PPVREF_RAM_ONBOARD_0123 70 69 68 63 61 RAM_BA_R<2> G1 NC/BA2 VREF E2 PPVREF_RAM_ONBOARD_0123 69
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VSSDL VSS VSSQ 1 C6920 1 VSSDL VSS VSSQ 1 C6930
R6929
1UF
R6926 R6939
1UF
E7
K9
J1
E3
A3
D8
D2
B8
B2
A7
E7
K9
J1
E3
A3
D8
D2
B8
B2
A7
1 2 10%
56.2 1 2 10%
6.3V 1% 6.3V
2 CERM 1/16W 2 CERM
200 402 MF-LF 200 402
C6929 2 402 C6939
1
2PF
2
ZTCLK2_L_P 1
1
2PF
2
1 ZTCLK2_L_N
On-Board DDR SDRAM
ZTCLK2_R_P 1 1 ZTCLK2_R_N
A ZTCLK2_M_P 1 1 ZTCLK2_M_N
SYNC_MASTER=FINO-M23 SYNC_DATE=08/26/2005
NOTICE OF PROPRIETARY PROPERTY
A
R6934
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
200
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1 ZT6920 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TABLE_5_HEAD
ZT6930 1
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM
SIZE DRAWING NUMBER REV.
333T0032 4 IC,SDRAM,DDR2,512MBIT,X8 U6900,U6910,U6920,U6930 CRITICAL
TABLE_5_ITEM
APPLE COMPUTER INC.
D 051-6863 19
333T0032 4 IC,SDRAM,DDR2,512MBIT,X8 U7040,U7050,U7060,U7070 CRITICAL
SCALE SHT OF
NONE 69 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V8_PWRON_DIMM =PP1V8_PWRON_DIMM
70 69 67 7
1 C7041 1 C7042 1 C7043 1 C7044 70 69 67 7
1 C7051 1 C7052 1 C7053 1 C7054
2.2UF 0.22UF 0.22UF 0.22UF 2.2UF 0.22UF 0.22UF 0.22UF
E1
A1
E9
H9
L1
A9
C1
C3
C7
C9
E1
A1
E9
H9
L1
A9
C1
C3
C7
C9
20% 20% 20% 20% DOES VDDL NEED A SPECIAL FILTER? 20% 20% 20% 20%
10V 6.3V 6.3V 6.3V 10V 6.3V 6.3V 6.3V
2 CERM 2 X5R 2 X5R 2 X5R 2 CERM 2 X5R 2 X5R 2 X5R
ZTCLK4_P 1 CHECK DECOUPLING - TRY TO MATCH SINGLE RANK DIMM
VDDL VDD VDDQ 805 402 402 402 VDDL VDD VDDQ 805 402 402 402
ZTCLK4_N 1
RAM_ONBOARD_CLK_P4_5 E8 CK B7 RAM_DQS_P_R<4> RAM_ONBOARD_CLK_P4_5 E8 CK B7 RAM_DQS_P_R<5>
70 62 61 DQS 61 68 70 62 61 DQS 61 68
RAM_ONBOARD_CLK_N4_5 F8 CK* A8 RAM_DQS_N_R<4> RAM_ONBOARD_CLK_N4_5 F8 CK* A8 RAM_DQS_N_R<5>
70 62 61 DQS* 61 68 70 62 61 DQS* 61 68
RAM_CKE_R<0> F2 CKE B3 RAM_CKE_R<0> F2 CKE B3
70 69 68 63 62 61
OMIT DM/RDQS 70 69 68 63 62 61
OMIT DM/RDQS
A2 A2
NU/RDQS* NU/RDQS*
D 70 69 68 63 61
70 69 68 63 61
RAM_A_R<0>
RAM_A_R<1>
H8
H3
A0
A1
U7040 DQ0 C8 RAM_DQ_R<38> 6 61 68
70 69 68 63 61
70 69 68 63 61
RAM_A_R<0>
RAM_A_R<1>
H8
H3
A0
A1
U7050 DQ0 C8 RAM_DQ_R<41> 6 61 68
D
70 69 68 63 61 RAM_A_R<2> H7 A2
SDRAM-64MX8-DDR2-533 DQ1 C2 RAM_DQ_R<34> 6 61 68 70 69 68 63 61 RAM_A_R<2> H7 A2
SDRAM-64MX8-DDR2-533 DQ1 C2 RAM_DQ_R<45> 6 61 68
y
70 69 68 63 61 RAM_A_R<3> J2 A3 HY5PS12821BPF-C4 DQ2 D7 RAM_DQ_R<36> 6 61 68 70 69 68 63 61 RAM_A_R<3> J2 A3 HY5PS12821BPF-C4 DQ2 D7 RAM_DQ_R<46> 6 61 68
70 69 68 63 61 RAM_A_R<4> J8 A4 CSP DQ3 D3 RAM_DQ_R<37> 6 61 68 70 69 68 63 61 RAM_A_R<4> J8 A4 CSP DQ3 D3 RAM_DQ_R<47> 61 68
70 69 68 63 61 RAM_A_R<5> J3 A5 DQ4 D1 RAM_DQ_R<33> 6 61 68 70 69 68 63 61 RAM_A_R<5> J3 A5 DQ4 D1 RAM_DQ_R<43> 6 61 68
70 69 68 63 61 RAM_A_R<6> J7 A6 DQ5 D9 RAM_DQ_R<35> 61 68 70 69 68 63 61 RAM_A_R<6> J7 A6 DQ5 D9 RAM_DQ_R<42> 61 68
K2 DQ6 B1 K2 DQ6 B1
r
70 69 68 63 61 RAM_A_R<7> A7 RAM_DQ_R<39> 61 68 70 69 68 63 61 RAM_A_R<7> A7 RAM_DQ_R<40> 6 61 68
70 69 68 63 61 RAM_A_R<8> K8 A8 DQ7 B9 RAM_DQ_R<32> 6 61 68 70 69 68 63 61 RAM_A_R<8> K8 A8 DQ7 B9 RAM_DQ_R<44> 6 61 68
70 69 68 63 61 RAM_A_R<9> K3 A9 70 69 68 63 61 RAM_A_R<9> K3 A9
CS* G8 RAM_CS_L_R<0> 61 63 68 69 70 CS* G8 RAM_CS_L_R<0> 61 63 68 69 70
RAM_A_R<10> H2 RAM_A_R<10> H2
70 69 68 63 61 A10 70 69 68 63 61 A10
70 69 68 63 61 RAM_A_R<11> K7 A11 RAS* F7 RAM_RAS_L_R 61 63 68 69 70 70 69 68 63 61 RAM_A_R<11> K7 A11 RAS* F7 RAM_RAS_L_R 61 63 68 69 70
70 69 68 63 61 RAM_A_R<12> L2 A12 CAS* G7 RAM_CAS_L_R 61 63 68 69 70 70 69 68 63 61 RAM_A_R<12> L2 A12 CAS* G7 RAM_CAS_L_R 61 63 68 69 70
L8 F3 L8 F3 1
70 69 68 63 61 RAM_A_R<13> NC/A13 WE* RAM_WE_L_R 61 63 68 69 70 70 69 68 63 61 RAM_A_R<13> NC/A13 WE* RAM_WE_L_R 61 63 68 69 70 R7055
a
70 69 68 63 61 RAM_A_R<14> L3 NC/A14 70 69 68 63 61 RAM_A_R<14> L3 NC/A14 56.2
L7 L7 1%
70 69 68 63 61 RAM_A_R<15> NC/A15 F9 70 69 68 63 61 RAM_A_R<15> NC/A15 F9 1/16W
ODT RAM_ODT_R<0> 61 63 68 69 70
ODT RAM_ODT_R<0> 61 63 68 69 70 MF-LF
70 69 68 63 61 RAM_BA_R<0> G2 BA0 70 69 68 63 61 RAM_BA_R<0> G2 BA0 2 402
70 69 68 63 61 RAM_BA_R<1> G3 BA1 70 69 68 63 61 RAM_BA_R<1> G3 BA1
70 69 68 63 61 RAM_BA_R<2> G1 NC/BA2 VREF E2 PPVREF_RAM_ONBOARD_4567 70 70 69 68 63 61 RAM_BA_R<2> G1 NC/BA2 VREF E2 70 PPVREF_RAM_ONBOARD_4567
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VSSDL VSS VSSQ 1 C7040 VSSDL VSS VSSQ 1 C7050 1
R7049 R7059 R7056
n
1UF 1UF
E7
K9
J1
E3
A3
D8
D2
B8
B2
A7
E7
K9
J1
E3
A3
D8
D2
B8
B2
A7
1 2 10% 1 2 10% 56.2
6.3V 6.3V 1%
2 CERM 2 CERM 1/16W
200 402 200 402 MF-LF
C7049 C7059 2 402
i
ZTCLK4_R_P 1 2PF 1 ZTCLK4_R_N 2PF
1 2 1 1 2 1
ZTCLK4_L_P ZTCLK4_L_N
C 1 1
C
ZTCLK4_M_P ZTCLK4_M_N
R7054
1 2
200
1 ZT7040
ZT7050 1
70 69 67 7 =PP1V8_PWRON_DIMM
1 C7061
2.2UF
1 C7062
0.22UF
1 C7063
0.22UF
1
il m
C7064
0.22UF
70 69 67 7 =PP1V8_PWRON_DIMM
1 C7071
2.2UF
1 C7072
0.22UF
1 C7073
0.22UF
1 C7074
0.22UF
E1
A1
E9
H9
L1
A9
C1
C3
C7
C9
E1
A1
E9
H9
L1
A9
C1
C3
C7
C9
20% 20% 20% 20% 20% 20% 20% 20%
10V 6.3V 6.3V 6.3V 10V 6.3V 6.3V 6.3V
2 CERM 2 X5R 2 X5R 2 X5R 2 CERM 2 X5R 2 X5R 2 X5R
ZTCLK6_P 1
VDDL VDD VDDQ 805 402 402 402 VDDL VDD VDDQ 805 402 402 402
ZTCLK6_N 1
E8 B7 E8 B7
e
70 62 61 RAM_ONBOARD_CLK_P6_7 CK DQS RAM_DQS_P_R<6> 61 68 70 62 61 RAM_ONBOARD_CLK_P6_7 CK DQS RAM_DQS_P_R<7> 61 68
RAM_ONBOARD_CLK_N6_7 F8 CK* A8 RAM_DQS_N_R<6> RAM_ONBOARD_CLK_N6_7 F8 CK* A8 RAM_DQS_N_R<7>
70 62 61 DQS* 61 68 70 62 61 DQS* 61 68
RAM_CKE_R<0> F2 CKE B3 RAM_CKE_R<0> F2 CKE B3
70 69 68 63 62 61
OMIT DM/RDQS 70 69 68 63 62 61
OMIT DM/RDQS
A2 A2
NU/RDQS* NU/RDQS*
B
70 69 68 63 61 RAM_A_R<0> H8 A0 U7060 70 69 68 63 61 RAM_A_R<0> H8 A0 U7070 B
r
70 69 68 63 61 RAM_A_R<1> H3 A1 DQ0 C8 RAM_DQ_R<52> 6 61 68 70 69 68 63 61 RAM_A_R<1> H3 A1 DQ0 C8 RAM_DQ_R<59> 6 61 68
70 69 68 63 61 RAM_A_R<2> H7 A2
SDRAM-64MX8-DDR2-533 DQ1 C2 RAM_DQ_R<48> 6 61 68 70 69 68 63 61 RAM_A_R<2> H7 A2
SDRAM-64MX8-DDR2-533 DQ1 C2 RAM_DQ_R<56> 6 61 68
70 69 68 63 61 RAM_A_R<3> J2 A3 HY5PS12821BPF-C4 DQ2 D7 RAM_DQ_R<50> 6 61 68 70 69 68 63 61 RAM_A_R<3> J2 A3 HY5PS12821BPF-C4 DQ2 D7 RAM_DQ_R<58> 6 61 68
70 69 68 63 61 RAM_A_R<4> J8 A4 CSP DQ3 D3 RAM_DQ_R<55> 61 68 70 69 68 63 61 RAM_A_R<4> J8 A4 CSP DQ3 D3 RAM_DQ_R<61> 61 68
70 69 68 63 61 RAM_A_R<5> J3 A5 DQ4 D1 RAM_DQ_R<54> 6 61 68 70 69 68 63 61 RAM_A_R<5> J3 A5 DQ4 D1 RAM_DQ_R<60> 6 61 68
70 69 68 63 61 RAM_A_R<6> J7 A6 DQ5 D9 RAM_DQ_R<51> 61 68 70 69 68 63 61 RAM_A_R<6> J7 A6 DQ5 D9 RAM_DQ_R<62> 61 68
70 69 68 63 61 RAM_A_R<7> K2 A7 DQ6 B1 RAM_DQ_R<49> 6 61 68 70 69 68 63 61 RAM_A_R<7> K2 A7 DQ6 B1 RAM_DQ_R<63> 6 61 68
70 69 68 63 61 RAM_A_R<8> K8 A8 DQ7 B9 RAM_DQ_R<53> 6 61 68 70 69 68 63 61 RAM_A_R<8> K8 A8 DQ7 B9 RAM_DQ_R<57> 6 61 68
P
70 69 68 63 61 RAM_A_R<9> K3 A9 70 69 68 63 61 RAM_A_R<9> K3 A9
CS* G8 RAM_CS_L_R<0> 61 63 68 69 70 CS* G8 RAM_CS_L_R<0> 61 63 68 69 70
70 69 68 63 61 RAM_A_R<10> H2 A10 70 69 68 63 61 RAM_A_R<10> H2 A10
70 69 68 63 61 RAM_A_R<11> K7 A11 RAS* F7 RAM_RAS_L_R 61 63 68 69 70 70 69 68 63 61 RAM_A_R<11> K7 A11 RAS* F7 RAM_RAS_L_R 61 63 68 69 70
70 69 68 63 61 RAM_A_R<12> L2 A12 CAS* G7 RAM_CAS_L_R 61 63 68 69 70 70 69 68 63 61 RAM_A_R<12> L2 A12 CAS* G7 RAM_CAS_L_R 61 63 68 69 70
70 69 68 63 61 RAM_A_R<13> L8 NC/A13 WE* F3 RAM_WE_L_R 61 63 68 69 70 70 69 68 63 61 RAM_A_R<13> L8 NC/A13 WE* F3 RAM_WE_L_R 61 63 68 69 70
70 69 68 63 61 RAM_A_R<14> L3 NC/A14 70 69 68 63 61 RAM_A_R<14> L3 NC/A14
70 69 68 63 61 RAM_A_R<15> L7 NC/A15 70 69 68 63 61 RAM_A_R<15> L7 NC/A15
F9 RAM_ODT_R<0> F9 RAM_ODT_R<0>
ODT 61 63 68 69 70 ODT 61 63 68 69 70
70 69 68 63 61 RAM_BA_R<0> G2 BA0 70 69 68 63 61 RAM_BA_R<0> G2 BA0
70 69 68 63 61 RAM_BA_R<1> G3 BA1 70 69 68 63 61 RAM_BA_R<1> G3 BA1
70 69 68 63 61 RAM_BA_R<2> G1 NC/BA2 VREF E2 PPVREF_RAM_ONBOARD_4567 70 70 69 68 63 61 RAM_BA_R<2> G1 NC/BA2 VREF E2 PPVREF_RAM_ONBOARD_4567 70
VSSDL VSS VSSQ 1 C7060 VSSDL VSS VSSQ 1 C7070
R7069 1UF
R7079 1UF
E7
K9
J1
E3
A3
D8
D2
B8
B2
A7
E7
K9
J1
E3
A3
D8
D2
B8
B2
A7
1 2 10% 1 2 10%
6.3V
2 CERM 6.3V
2 CERM
200 402 200 402
C7069 C7079
1
2PF
2
ZTCLK6_L_P 1
1
2PF
2
1 ZTCLK6_L_N
On-Board DDR SDRAM
ZTCLK6_R_P 1 1 ZTCLK6_R_N
A ZTCLK6_M_P 1 1 ZTCLK6_M_N
SYNC_MASTER=FINO-M23 SYNC_DATE=08/26/2005
NOTICE OF PROPRIETARY PROPERTY
A
R7074 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1 2 AGREES TO THE FOLLOWING
200 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 ZT7060
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ZT7070 1
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 70 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L8200
82 7 =PP2V5_PWRON_NB_PCIE 0.22UH PWR_PCIE_A_AVDD_2 82 97 KODIAK AVDD FILTERING
(LOCATE CLOSE TO POWER AND GROUND PINS)
1 2 L8203
0.22UH =PP2V5_PWRON_NB_PCIE 7 82
0805-1
PWR_PCIE_A_AVDD_2 97 PWR_PCIE_A_AVDD_A 97 PWR_PCIE_A_AVDD 1 2
97 82
C8200 1 C8201 1 C8202 1
0805-1
0.01UF 10UF 1UF 97 82 PWR_PCIE_A_AVDD_1 97 PWR_PCIE_A_AVDD_B
10% 10% 10%
16V 6.3V 6.3V 1
CERM 2 X5R 2 CERM 2
PWR_PCIE_A_AVDD_0 97 PWR_PCIE_A_AVDD_C
C8224
97 82
402 805 402 1
C8222 1
C8225 1
C8223 0.01UF
10%
1UF 1UF 10UF 2
16V
10% 10% 10% CERM
6.3V 6.3V 6.3V 402
2 CERM 2 CERM 2 X5R
97 82 6 KOD_G10_GND 402 402 805
J06 J07 H11 J12 K13 J09
D L8201
(THIS PAGE)
PCIE_AVDD_0
(1.65V-2.75V)
PCIE_AVDD_1 PCIE_AVDD_2 PCIE_REFCLK_AVDDA
(1.65V-2.75V) (1.65V-2.75V) (1.65V-2.75V)
PCIE_REFCLK_AVDDB
(1.65V-2.75V)
PCIE_REFCLK_AVDD2
(1.65V-2.75V)
D
82 7 =PP2V5_PWRON_NB_PCIE 0.22UH PWR_PCIE_A_AVDD_1 82 97
KOD_L13_GND 6 82 97
y
SERDES SERDES SERDES PLL PLL PLL
1 2
(THIS PAGE)
0805-1
U1900 KOD_J13_GND 6 82 97
C8203 1
C8204 1
C8205 1
KODIAK-ASIC-040812 (THIS PAGE)
0.01UF 10UF 1UF
r
10%
16V
2
10%
6.3V
2
6.3V
10%
2
PCI-E X16 INTERFACE L8205
CERM X5R CERM =PP2V5_PWRON_NB_PCIE
402 805 402 (1.6V-1.2V) BGA (1.6V-1.2V) 0.22UH 7 82
A04 PCIE_VDD F02
(5 OF 10) PCIE_VDD 1 2
A08 PCIE_VDD F05
PCIE_VDD 0805-1
A12
SEE_TABLE G08
97 82 6 KOD_K07_GND PCIE_VDD PCIE_VDD
(THIS PAGE) B06 PCIE_VDD PCIE_VDD G12 1
C8228 1
C8229 1
C8230
L8202 B10
PCIE_VDD PCIE_VDD H01 1UF 10UF 0.01UF
=PP2V5_PWRON_NB_PCIE PWR_PCIE_A_AVDD_0 10% 10% 10%
a
82 7 0.22UH 82 97
C03 PCIE_VDD H04 6.3V 6.3V 16V
PCIE_VDD 2 CERM 2 X5R 2 CERM
1 2 D01 H07 402 805 402
PCIE_VDD PCIE_VDD
0805-1 D04 H10
PCIE_VDD PCIE_VDD
D08 H14
1 1 1 PCIE_VDD PCIE_VDD
C8206 C8207 C8208 D12 K12
KOD_H08_GND 6 82 97
0.01UF 10UF 1UF PCIE_VDD PCIE_VDD (THIS PAGE)
10% 10% 10% E06 PCIE_VDD L11
16V 6.3V 6.3V PCIE_VDD
CERM 2 X5R 2 CERM 2
E10 PCIE_VDD PCIE_VDD L14
402 805 402
KODIAK PCI-E =PPVCORE_PWRON_NB_PCIE E14 M12 =PPVCORE_PWRON_NB_PCIE
n
82 7 PCIE_VDD PCIE_VDD 7 82
100MHZ REFCLK
KOD_H05_GND
PP8201 97 82 6
P4MM (THIS PAGE)
SM KODIAK PCI-E AC COUPLERS
i
1 97 9 CLK_KOD_100M_PF<0> J11 PCIE_REFCLK_P
100+ PP
(100MHZ) (LOCATE NEAR SOURCE PINS)
1 CLK_KOD_100M_NF<0> J10
100- PP 97 9 PCIE_REFCLK_N
C P4MM
PP8200
SM
97 84 9
97 84 9
PCIE_SLOTA_TO_NB_N<0>
PCIE_SLOTA_TO_NB_P<0>
G05
G04
PCIE_HSIN0
PCIE_HSIP0
PCIE_HSON0
PCIE_HSOP0
D03
E03
97 9
97 9
PCIE_NB_TO_SLOTA_NF<0>
PCIE_NB_TO_SLOTA_PF<0>
0.1UF
0.1UF
1
1
2
2
C8247
C8248
PCIE_NB_TO_SLOTA_N<0>
PCIE_NB_TO_SLOTA_P<0>
9 84 97
9 84 97
C
97 84 9 PCIE_SLOTA_TO_NB_N<1> G01 PCIE_HSIN1 PCIE_HSON1 J01 97 9 PCIE_NB_TO_SLOTA_NF<1> 0.1UF 1 2 C8249 PCIE_NB_TO_SLOTA_N<1> 9 84 97
97 84 9 PCIE_SLOTA_TO_NB_P<1> G02 PCIE_HSIP1 PCIE_HSOP1 J02 97 9 PCIE_NB_TO_SLOTA_PF<1> 0.1UF 1 2 C8250 PCIE_NB_TO_SLOTA_P<1> 9 84 97
97 84 9 PCIE_SLOTA_TO_NB_N<2> C04 PCIE_HSIN2 PCIE_HSON2 C01 97 9 PCIE_NB_TO_SLOTA_NF<2> 0.1UF 1 2 C8251 PCIE_NB_TO_SLOTA_N<2> 9 84 97
C8245 PCIE_SLOTA_TO_NB_P<2> C05
PCIE_HSIP2 PCIE_HSOP2 C02 97 9 PCIE_NB_TO_SLOTA_PF<2> 0.1UF 1 2 C8252 PCIE_NB_TO_SLOTA_P<2>
R8202 0.01UF
97 84 9 9 84 97
20.5 1 2
97 84 9 PCIE_SLOTA_TO_NB_N<3> C07 PCIE_HSIN3 PCIE_HSON3 A07 97 9 PCIE_NB_TO_SLOTA_NF<3> 0.1UF 1 2 C8253 PCIE_NB_TO_SLOTA_N<3> 9 84 97
97 26 CLK_KOD_100M_P<0> 1 2 97 9 100M_P<0>
97 84 9 PCIE_SLOTA_TO_NB_P<3> C06 PCIE_HSIP3 PCIE_HSOP3 B07 97 9 PCIE_NB_TO_SLOTA_PF<3> 0.1UF 1 2 C8254 PCIE_NB_TO_SLOTA_P<3> 9 84 97
1%
1 10% PCIE_SLOTA_TO_NB_N<4> E01 F03 PCIE_NB_TO_SLOTA_NF<4> 0.1UF 1 2 C8255 PCIE_NB_TO_SLOTA_N<4>
m
1/16W
R8203 16V
97 84 9 PCIE_HSIN4 PCIE_HSON4 97 9 9 84 97
MF-LF
NOSTUFF 402 29.4 CERM
402 97 84 9 PCIE_SLOTA_TO_NB_P<4> E02 PCIE_HSIP4 PCIE_HSOP4 G03 97 9 PCIE_NB_TO_SLOTA_PF<4> 0.1UF 1 2 C8256 PCIE_NB_TO_SLOTA_P<4> 9 84 97
1%
C8244 1/16W 97 84 9 PCIE_SLOTA_TO_NB_N<5> J05 PCIE_HSIN5 PCIE_HSON5 H03 97 9 PCIE_NB_TO_SLOTA_NF<5> 0.1UF 1 2 C8257 PCIE_NB_TO_SLOTA_N<5> 9 84 97
MF-LF
0.01UF 402 2 97 84 9 PCIE_SLOTA_TO_NB_P<5> J04
PCIE_HSIP5 PCIE_HSOP5 J03 97 9 PCIE_NB_TO_SLOTA_PF<5> 0.1UF 1 2 C8258 PCIE_NB_TO_SLOTA_P<5> 9 84 97
il
1 2 100M_G 97 84 9 PCIE_SLOTA_TO_NB_N<6> H06 PCIE_HSIN6 PCIE_HSON6 A03 97 9 PCIE_NB_TO_SLOTA_NF<6> 0.1UF 1 2 C8259 PCIE_NB_TO_SLOTA_N<6> 9 84 97
10% 97 84 9 PCIE_SLOTA_TO_NB_P<6> G06 PCIE_HSIP6 PCIE_HSOP6 B03 97 9 PCIE_NB_TO_SLOTA_PF<6> 0.1UF 1 2 C8260 PCIE_NB_TO_SLOTA_P<6> 9 84 97
16V R8204 1 97 84 9 PCIE_SLOTA_TO_NB_N<7> E05 PCIE_HSIN7 PCIE_HSON7 A05 97 9 PCIE_NB_TO_SLOTA_NF<7> 0.1UF 1 2 C8261 PCIE_NB_TO_SLOTA_N<7> 9 84 97
CERM 29.4
402
1% 97 84 9 PCIE_SLOTA_TO_NB_P<7> D05 PCIE_HSIP7 PCIE_HSOP7 B05 97 9 PCIE_NB_TO_SLOTA_PF<7> 0.1UF 1 2 C8262 PCIE_NB_TO_SLOTA_P<7> 9 84 97
1/16W
C8246 PCIE_SLOTA_TO_NB_N<8> D11 PCIE_HSIN8 PCIE_HSON8 C11 97 9 PCIE_NB_TO_SLOTA_NF<8> 0.1UF 1 2 C8263 PCIE_NB_TO_SLOTA_N<8>
R8205 MF-LF
402 2 0.01UF
97 84 9 9 84 97
20.5 1 2
97 84 9 PCIE_SLOTA_TO_NB_P<8> E11 PCIE_HSIP8 PCIE_HSOP8 C10 97 9 PCIE_NB_TO_SLOTA_PF<8> 0.1UF 1 2 C8264 PCIE_NB_TO_SLOTA_P<8> 9 84 97
97 26 CLK_KOD_100M_N<0> 2 1 97 9 100M_N<0>
97 84 9 PCIE_SLOTA_TO_NB_N<9> F12 PCIE_HSIN9 PCIE_HSON9 B11 97 9 PCIE_NB_TO_SLOTA_NF<9> 0.1UF 1 2 C8265 PCIE_NB_TO_SLOTA_N<9> 9 84 97
1%
1/16W 10%
97 84 9 PCIE_SLOTA_TO_NB_P<9> F13
PCIE_HSIP9 PCIE_HSOP9 A11 97 9 PCIE_NB_TO_SLOTA_PF<9> 0.1UF 1 2 C8266 PCIE_NB_TO_SLOTA_P<9> 9 84 97
KODIAK PCIE REFCLK MF-LF 16V
CERM PCIE_SLOTA_TO_NB_N<10> H09 F11 PCIE_NB_TO_SLOTA_NF<10> 0.1UF 1 2 C8267 PCIE_NB_TO_SLOTA_N<10>
402
402 97 84 9 PCIE_HSIN10 PCIE_HSON10 97 9 9 84 97
TERMINATION PCIE_SLOTA_TO_NB_P<10> G09 F10 PCIE_NB_TO_SLOTA_PF<10> 0.1UF 1 2 C8268 PCIE_NB_TO_SLOTA_P<10>
97 84 9 PCIE_HSIP10 PCIE_HSOP10 97 9 9 84 97
e
(LOCATE CLOSE TO INPUT PINS) F09 B09 0.1UF 1 2 C8269
97 84 9 PCIE_SLOTA_TO_NB_N<11> PCIE_HSIN11 PCIE_HSON11 97 9 PCIE_NB_TO_SLOTA_NF<11> PCIE_NB_TO_SLOTA_N<11> 9 84 97
97 84 9 PCIE_SLOTA_TO_NB_P<11> F08 PCIE_HSIP11 PCIE_HSOP11 A09 97 9 PCIE_NB_TO_SLOTA_PF<11> 0.1UF 1 2 C8270 PCIE_NB_TO_SLOTA_P<11> 9 84 97
97 84 9 PCIE_SLOTA_TO_NB_N<12> G13 PCIE_HSIN12 PCIE_HSON12 D13 97 9 PCIE_NB_TO_SLOTA_NF<12> 0.1UF 1 2 C8271 PCIE_NB_TO_SLOTA_N<12> 9 84 97
97 84 9 PCIE_SLOTA_TO_NB_P<12> H13 PCIE_HSIP12 PCIE_HSOP12 E13 97 9 PCIE_NB_TO_SLOTA_PF<12> 0.1UF 1 2 C8272 PCIE_NB_TO_SLOTA_P<12> 9 84 97
B =PP2V5_PWRON_NB_PCIE PCIE_SLOTA_TO_NB_N<13> C13 PCIE_HSIN13 PCIE_HSON13 B13 PCIE_NB_TO_SLOTA_NF<13> 0.1UF 1 2 C8273 PCIE_NB_TO_SLOTA_N<13>
B
r
82 7 97 84 9 97 9 9 84 97
97 84 9 PCIE_SLOTA_TO_NB_P<13> C12 PCIE_HSIP13 PCIE_HSOP13 A13 97 9 PCIE_NB_TO_SLOTA_PF<13> 0.1UF 1 2 C8274 PCIE_NB_TO_SLOTA_P<13> 9 84 97
R8200
1
97 84 9 PCIE_SLOTA_TO_NB_N<14> D07 PCIE_HSIN14 PCIE_HSON14 D09 97 9 PCIE_NB_TO_SLOTA_NF<14> 0.1UF 1 2 C8275 PCIE_NB_TO_SLOTA_N<14> 9 84 97
8.2K 97 84 9 PCIE_SLOTA_TO_NB_P<14> E07 PCIE_HSIP14 PCIE_HSOP14 E09 97 9 PCIE_NB_TO_SLOTA_PF<14> 0.1UF 1 2 C8276 PCIE_NB_TO_SLOTA_P<14> 9 84 97
5%
1/16W 97 84 9 PCIE_SLOTA_TO_NB_N<15> G07
PCIE_HSIN15 PCIE_HSON15 C08 97 9 PCIE_NB_TO_SLOTA_NF<15> 0.1UF 1 2 C8277 PCIE_NB_TO_SLOTA_N<15> 9 84 97
MF-LF
402 2 97 84 9 PCIE_SLOTA_TO_NB_P<15> F07 PCIE_HSIP15 PCIE_HSOP15 C09 97 9 PCIE_NB_TO_SLOTA_PF<15> 0.1UF 1 2 C8278 PCIE_NB_TO_SLOTA_P<15> 9 84 97
PCIE_SLOTA_PRSNT_L AJ02
84 6 PCIE_PRESENTN (DNU) G11
PCIE_AVREG_2 NC_A_AVREG_2 6 =PPVCORE_PWRON_NB_PCIE 7 82
PCIE_VCAL_RES0 F14 PCIE_UCAL_RES0 PCIE_AVREG_1 J08 NC_A_AVREG_1
P
6
PCIE_VCAL_RES1 J14 PCIE_UCAL_RES1 PCIE_AVREG_0 E04 NC_A_AVREG_0 6
KODIAK PCI-E DECOUPLING R8201 1 1 C8231 1 C8232 1 C8233 1 C8234 1 C8235 1 C8236
(LOCATE CLOSE TO POWER AND GROUND PINS) 200 1UF 1UF 1UF 1UF 1UF 1UF
1% 10% 10% 10% 10% 10% 10%
1/16W A06 F04 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
MF-LF
PCIE_GND PCIE_GND 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
=PPVCORE_PWRON_NB_PCIE 7 82 402 402 402 402 402 402
402 2 A10 PCIE_GND PCIE_GND F06
B02 PCIE_GND PCIE_GND G14
B04 H02
PCIE_GND PCIE_GND
1 C8209 1 C8210 1 C8211 1 C8212 B08 PCIE_GND PCIE_GND H12
1 1 1 1 1 1 1
1UF 1UF 1UF 1UF B12 K10
C8241 C8242 C8243 C8237 C8238 C8239 C8240
10% 10% 10% 10%
PCIE_GND PCIE_GND 1UF 1UF 1UF 1UF 1UF 1UF 1UF
6.3V 6.3V 6.3V 6.3V D02 K14 10% 10% 10% 10% 10% 10% 10%
2 CERM 2 CERM 2 CERM 2 CERM PCIE_GND PCIE_GND 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
D06 PCIE_GND PCIE_GND L12
402 402 402 402 402 402 402
D10 PCIE_GND PCIE_GND M11
D14 PCIE_GND PCIE_GND M13
E08 PCIE_GND
E12 PCIE_GND KODIAK PCI-E DECOUPLING
1 C8213 1 C8214 1 C8215 1 C8216
1UF 1UF 1UF 1UF
F01 PCIE_GND (LOCATE CLOSE TO POWER AND GROUND PINS) KODIAK PCI-E X16
10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V
A 2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402 AVDD_0_GND AVDD_1_GND AVDD_2_GND REFCLK_AGNDA REFCLK_AGNDB REFCLK_AGND2
SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
H05 K07 G10 J13 L13 H08
LAST_MODIFIED=Tue Aug 30 18:05:57 2005
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
97 82 6 KOD_H05_GND KOD_H08_GND 6 82 97 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
97 82 6 KOD_K07_GND KOD_L13_GND 6 82 97
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1 C8217 1 C8218 1 C8219 1 C8220 1 C8221 97 82 6 KOD_G10_GND KOD_J13_GND 6 82 97
1UF 1UF 1UF 1UF 1UF PAGE 82 II NOT TO REPRODUCE OR COPY IT
(THIS PAGE, X3) (THIS PAGE, X3)
10% 10% 10% 10% 10% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
6.3V 6.3V 6.3V 6.3V 6.3V 2 2 2 2 2 2
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 XW8200 XW8201 XW8202 XW8203 XW8204 XW8205 SIZE DRAWING NUMBER REV.
SM SM SM SM SM SM
1 1 1 1 1 1
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
5
NONE
82 154
8 7 6 5 4 3 2 1 DRAWING
8 7 6 5 4 3 2 1
TABLE_5_HEAD
REMOVED COMPLIANCE TEST POINTS
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
FINO WILL PLACE COUPLING CAPACITORS ON RECEIVING SIDE
TABLE_5_ITEM
7 =PP1V2_GPU_PCIE R8460 PP1V2_GPU_PCIE_VDDR 84
338S0239 1 IC,RV370 XT, GRAPHICS CTLR U8400 RV370XT CRITICAL VOLTAGE=1.2V (THIS IS ALLOWED FOR CHIP TO CHIP PCIE)
THIS IS ALIASED TO 1
0 2
MIN_LINE_WIDTH=0.5MM
TABLE_5_ITEM
MIN_NECK_WIDTH=0.25MM CAP PAD CAN BE USED FOR COMPLIANCE TEST
338S0265 1 IC,RV380 XT A23, GRAPHICS CTLR U8400 RV380XT CRITICAL PPVCORE_GPU ON PAGE 7
5%
1/8W
R8460 BRINGS VDDR FROM MF-LF
CORE (1.35) TO 1.2 805
NOSTUFF
R8461 GROUND VIAS FOR LAYER TRANSITIONS
0
1 2 1 C8460 1 C8461 1 C8462 1 C8463 1 C8464 1 C8465 1 C8466 ZH8400
5% 1UF 1UF 1UF 0.1UF 0.1UF 0.1UF 0.1UF HOLE-VIA
1/8W 10% 10% 10% 20% 20% 20% 20% 1
PP1V2_GPU_PCIE_PVDD 6.3V 6.3V 6.3V 10V 10V 10V 10V
85 84 SYS_POWERUP_L SHOULD CONTROL THE FET ONMF-LF
PP1V2_RUN 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
D
805 402 402 402 402 402 402 402
ZH8401
D
1 C8450 1 C8451 1 C8452 1 C8453 1 C8454 1 C8455 HOLE-VIA
y
1
1UF 1UF 0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 20% 20% 20% 20%
6.3V 6.3V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 ZH8402
PLACE R8470 CLOSE TO U9670 HOLE-VIA
1
U9670
r
14 74LC125 R8470 ZH8403
L8440 =GPU_RESET_L 12 11 ATI_RESET_L 1
33 2 HOLE-VIA
93 87 86 85 =PP1V8_GPU FERR-220-OHM 20
1
125 5%
1 2 PP1V8_GPU_PCIE_PVDD 7 13 TSSOP 1/16W
0805
VOLTAGE=1.8V R84691 MF-LF
402 ZH8404
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
1 C8440 1 C8441 1 C8442 1 C8443 1 C8444 1 C8445 8.2K
5% HOLE-VIA
1UF 1UF 0.1UF 0.1UF 0.1UF 0.1UF 1/16W 1
10% 10% 20% 20% 20% 20%
a
6.3V MF-LF
2 CERM 2 6.3V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 402 2
402 402 402 402 402 402
ZH8405
HOLE-VIA
AG26
AG27
AG28
AJ30
AK29
T23
U23
PCIE_PVDD_18 V23
W23
N23
N24
P23
1
ZH8406
PCIE_PVDD_12
PCIE_VDDR_12
PP1V2_GPU_PCIE_PVDD 84 85 97 CLK_PCIE_SLOTA_PF<0> AF27 PCIE_REFCLKP PERST* AD25 ATI_RESET_L_R HOLE-VIA
97 CLK_PCIE_SLOTA_NF<0> AE27 PCIE_REFCLKN GPU PCI-E AC COUPLERS (PLACE NEAR GPU) 1
1
n
R8471 97 82 9 PCIE_NB_TO_SLOTA_P<0> AH30 PCIE_RX0P PCIE_TX0P AF26 97 9 PCIE_SLOTA_TO_NB_PF<0> 0.1UF 1 2 C8400 PCIE_SLOTA_TO_NB_P<0> 9 82 97
301
PCIE_NB_TO_SLOTA_N<0> AG30 PCIE_RX0N PCIE_TX0N AE26 97 9 PCIE_SLOTA_TO_NB_NF<0> 0.1UF 1 2 C8401 PCIE_SLOTA_TO_NB_N<0> ZH8407
1%
1/16W
97 82 9 9 82 97
HOLE-VIA
MF-LF 97 82 9 PCIE_NB_TO_SLOTA_P<1> AG29 PCIE_RX1P PCIE_TX1P AC25 97 9 PCIE_SLOTA_TO_NB_PF<1> 0.1UF 1 2 C8402 PCIE_SLOTA_TO_NB_P<1> 9 82 97 1
R8472 2 402 R8473 0.1UF C8403
i
97 82 9 PCIE_NB_TO_SLOTA_N<1> AF29 PCIE_RX1N PCIE_TX1N AB25 97 9 PCIE_SLOTA_TO_NB_NF<1> 1 2 PCIE_SLOTA_TO_NB_N<1> 9 82 97
1
21
2 CKA_P<0>
97
9 1
21
2 97 82 9 PCIE_NB_TO_SLOTA_P<2> AE29 PCIE_RX2P U8400 PCIE_TX2P AC27 97 9 PCIE_SLOTA_TO_NB_PF<2> 0.1UF 1 2 C8404 PCIE_SLOTA_TO_NB_P<2> 9 82 97 ZH8408
RV370XT 0.1UF C8405 HOLE-VIA
C 1%
1/16W
MF-LF
402
1
R8474 1
C8472
1%
1/16W
MF-LF
402
97 82 9
97 82 9
PCIE_NB_TO_SLOTA_N<2>
PCIE_NB_TO_SLOTA_P<3>
AE30 PCIE_RX2N
AD30 PCIE_RX3P BGA
(1 OF 5)
PCIE_TX2N AB27
PCIE_TX3P AC26
97 9
97 9
PCIE_SLOTA_TO_NB_NF<2>
PCIE_SLOTA_TO_NB_PF<3> 0.1UF
1
1
2
2 C8406
PCIE_SLOTA_TO_NB_N<2>
PCIE_SLOTA_TO_NB_P<3>
9 82 97
9 82 97
1 C
60.4 97 82 9 PCIE_NB_TO_SLOTA_N<3> AD29 PCIE_RX3N PCIE_TX3N AB26 97 9 PCIE_SLOTA_TO_NB_NF<3> 0.1UF 1 2 C8407 PCIE_SLOTA_TO_NB_N<3> 9 82 97
1%
5PF
+/-0.25PF PCIE_NB_TO_SLOTA_P<4> AC29 PCIE_RX4P
OMIT
PCIE_TX4P Y25 97 9 PCIE_SLOTA_TO_NB_PF<4> 0.1UF 1 2 C8408 PCIE_SLOTA_TO_NB_P<4>
ZH8409
1/16W
MF-LF 2
50V 97 82 9 9 82 97
HOLE-VIA
2 402
CERM
402 97 82 9 PCIE_NB_TO_SLOTA_N<4> AB29 PCIE_RX4N PCI-E PCIE_TX4N W25 97 9 PCIE_SLOTA_TO_NB_NF<4> 0.1UF 1 2 C8409 PCIE_SLOTA_TO_NB_N<4> 9 82 97 1
97 26 CLK_PCIE_SLOTA_P<0> 97 82 9 PCIE_NB_TO_SLOTA_P<5> AB30 PCIE_RX5P PCIE_TX5P Y27 97 9 PCIE_SLOTA_TO_NB_PF<5> 0.1UF 1 2 C8410 PCIE_SLOTA_TO_NB_P<5> 9 82 97
97 26 CLK_PCIE_SLOTA_N<0> 97 82 9 PCIE_NB_TO_SLOTA_N<5> AA30 PCIE_RX5N PCIE_TX5N W27 97 9 PCIE_SLOTA_TO_NB_NF<5> 0.1UF 1 2 C8411 PCIE_SLOTA_TO_NB_N<5> 9 82 97 ZH8410
97 82 9 PCIE_NB_TO_SLOTA_P<6> AA29 PCIE_RX6P PCIE_TX6P Y26 97 9 PCIE_SLOTA_TO_NB_PF<6> 0.1UF 1 2 C8412 PCIE_SLOTA_TO_NB_P<6> 9 82 97
HOLE-VIA
1 1
R8476 1 C8473 97 82 9 PCIE_NB_TO_SLOTA_N<6> Y29 PCIE_RX6N PCIE_TX6N W26 97 9 PCIE_SLOTA_TO_NB_NF<6> 0.1UF 1 2 C8413 PCIE_SLOTA_TO_NB_N<6> 9 82 97
60.4
m
1%
5PF 97 82 9 PCIE_NB_TO_SLOTA_P<7> W29 PCIE_RX7P PCIE_TX7P U25 97 9 PCIE_SLOTA_TO_NB_PF<7> 0.1UF 1 2 C8414 PCIE_SLOTA_TO_NB_P<7> 9 82 97
1/16W
+/-0.25PF
50V PCIE_NB_TO_SLOTA_N<7> W30 PCIE_RX7N PCIE_TX7N T25 97 9 PCIE_SLOTA_TO_NB_NF<7> 0.1UF 1 2 C8415 PCIE_SLOTA_TO_NB_N<7>
ZH8411
MF-LF 2 CERM 97 82 9 9 82 97
HOLE-VIA
R8475 2 402 402 R8477 97 82 9 PCIE_NB_TO_SLOTA_P<8> V30 PCIE_RX8P PCIE_TX8P U27 97 9 PCIE_SLOTA_TO_NB_PF<8> 0.1UF 1 2 C8416 PCIE_SLOTA_TO_NB_P<8> 9 82 97 1
21 97 21 0.1UF C8417
il
1 2 CKA_N<0>
9 1 2 97 82 9 PCIE_NB_TO_SLOTA_N<8> V29 PCIE_RX8N PCIE_TX8N T27 97 9 PCIE_SLOTA_TO_NB_NF<8> 1 2 PCIE_SLOTA_TO_NB_N<8> 9 82 97
1% 1% 97 82 9 PCIE_NB_TO_SLOTA_P<9> U29 PCIE_RX9P PCIE_TX9P U26 97 9 PCIE_SLOTA_TO_NB_PF<9> 0.1UF 1 2 C8418 PCIE_SLOTA_TO_NB_P<9> 9 82 97 ZH8412
1/16W 1/16W
MF-LF 1
R8478 MF-LF 97 82 9 PCIE_NB_TO_SLOTA_N<9> T29 PCIE_RX9N PCIE_TX9N T26 97 9 PCIE_SLOTA_TO_NB_NF<9> 0.1UF 1 2 C8419 PCIE_SLOTA_TO_NB_N<9> 9 82 97
HOLE-VIA
402 402 1
301 97 82 9 PCIE_NB_TO_SLOTA_P<10> T30 PCIE_RX10P PCIE_TX10P P25 97 9 PCIE_SLOTA_TO_NB_PF<10> 0.1UF 1 2 C8420 PCIE_SLOTA_TO_NB_P<10> 9 82 97
1%
1/16W 97 82 9 PCIE_NB_TO_SLOTA_N<10> R30 PCIE_RX10N PCIE_TX10N N25 97 9 PCIE_SLOTA_TO_NB_NF<10> 0.1UF 1 2 C8421 PCIE_SLOTA_TO_NB_N<10> 9 82 97
MF-LF
PCIE_NB_TO_SLOTA_P<11> R29 PCIE_RX11P PCIE_TX11P P27 97 9 PCIE_SLOTA_TO_NB_PF<11> 0.1UF 1 2 C8422 PCIE_SLOTA_TO_NB_P<11> ZH8413
2 402
97 82 9 9 82 97
HOLE-VIA
97 82 9 PCIE_NB_TO_SLOTA_N<11> P29 PCIE_RX11N PCIE_TX11N N27 97 9 PCIE_SLOTA_TO_NB_NF<11> 0.1UF 1 2 C8423 PCIE_SLOTA_TO_NB_N<11> 9 82 97 1
97 82 9 PCIE_NB_TO_SLOTA_P<12> N29 PCIE_RX12P PCIE_TX12P P26 97 9 PCIE_SLOTA_TO_NB_PF<12> 0.1UF 1 2 C8424 PCIE_SLOTA_TO_NB_P<12> 9 82 97
PP1V2_GPU_PCIE_PVDD 84 85
97 82 9 PCIE_NB_TO_SLOTA_N<12> N30 PCIE_RX12N PCIE_TX12N N26 97 9 PCIE_SLOTA_TO_NB_NF<12> 0.1UF 1 2 C8425 PCIE_SLOTA_TO_NB_N<12> 9 82 97 ZH8414
PCIE_NB_TO_SLOTA_P<13> M30 PCIE_RX13P PCIE_TX13P L25 97 9 PCIE_SLOTA_TO_NB_PF<13> 0.1UF 1 2 C8426 PCIE_SLOTA_TO_NB_P<13> HOLE-VIA
PCI-E SLOTA 100MHZ 97 82 9 9 82 97
1
0.1UF C8427
e
PCIE_NB_TO_SLOTA_N<13> M29 PCIE_RX13N PCIE_TX13N K25 97 9 PCIE_SLOTA_TO_NB_NF<13> 1 2 PCIE_SLOTA_TO_NB_N<13>
REFCLK TERMINATION 97 82 9 9 82 97
97 82 9 PCIE_NB_TO_SLOTA_P<14> L29 PCIE_RX14P PCIE_TX14P L27 97 9 PCIE_SLOTA_TO_NB_PF<14> 0.1UF 1 2 C8428 PCIE_SLOTA_TO_NB_P<14> 9 82 97
(LOCATE CLOSE TO GPU)
PCIE_NB_TO_SLOTA_N<14> K29 PCIE_RX14N PCIE_TX14N K27 97 9 PCIE_SLOTA_TO_NB_NF<14> 0.1UF 1 2 C8429 PCIE_SLOTA_TO_NB_N<14>
ZH8415
97 82 9 9 82 97
HOLE-VIA
97 82 9 PCIE_NB_TO_SLOTA_P<15> K30 PCIE_RX15P PCIE_TX15P L26 97 9 PCIE_SLOTA_TO_NB_PF<15> 0.1UF 1 2 C8430 PCIE_SLOTA_TO_NB_P<15> 9 82 97 1
97 82 9 PCIE_NB_TO_SLOTA_N<15> J30 PCIE_RX15N PCIE_TX15N K26 97 9 PCIE_SLOTA_TO_NB_NF<15> 0.1UF 1 2 C8431 PCIE_SLOTA_TO_NB_N<15> 9 82 97
B B
r
ZH8416
84 PP1V2_GPU_PCIE_VDDR R8400 GPU_PCIE_CALRN AB24 PCIE_CALRN PCIE_CALI AB23 GPU_PCIE_CALI HOLE-VIA
1
100 2
1
GPU_PCIE_CALRP AC23 PCIE_CALRP PCIE_TEST AE25 GPU_PCIE_TEST
1%
1/16W ZH8417
MF-LF
402 1
R8401 K28 AH29 R84021 1
R8403 HOLE-VIA
10K 10K 1
150 L28 AF28 5% 1%
1% 1/16W 1/16W
1/16W M24 AE28 MF-LF MF-LF
MF-LF
M25 AD28
402 2 2 402 ZH8418
P
2 402 HOLE-VIA
M26 PCIE_VSS 1
PCIE_VSS AD27
M27 AD26
M28 AD24 ZH8419
N28 AC28 HOLE-VIA
1
P28 AB28
R23 AA28
PCIE_VSS
R24
R25
R26
R27
R28
T24
T28
U28
V24
V25
V26
V27
V28
W24
W28
Y28
AA23
AA24
AA25
AA26
AA27
XW8405
SM
82 6 PCIE_SLOTA_PRSNT_L 1 2 GPU PCIe
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/18/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 84 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE:
14
U700
74LC125
GPU VCORE VREG SET OUTPUT = 1.25V +/- 2% FOR RV370 XT
1.30V +/- 2% FOR RV380 XT
50 28 12 7 6 SYS_POWERUP_L 12 11 GPU_POWERUP_L 13 85
125 D8501 7 =PP12V_ALL_GPU
IRU3037ACS VREF = 0.8 VDC
7 13 TSSOP
GPU_VCORE_VREG_VC 2 1
VOUT=VREF*(R8503+R8505)/R8505 M23=1.272V
MIN_LINE_WIDTH=0.45MM M33=1.332V
MIN_NECK_WIDTH=0.25MM
C8510 1 OMIT PEAK CURRENT OF PPVCORE_GPU
=PP5V_ALL_GPU 1
R8500
MBR0520LXXG
SOD-123
1
D8502
1
C8502
7
10UF 330UF 7.2A WITH RV370 XT
10 MBR0520LXXG 10% 20%
5%
1/8W D8503 2
SOD-123 2 16V
CERM 2 16V
ELEC
8.3A WITH RV380 XT
MF-LF 1210 SM-3
C8504 1
2 805
2 1 GPU_VCORE_VC_D
MIN_LINE_WIDTH=0.45MM =PP3V3_GPU
1UF MIN_NECK_WIDTH=0.25MM
7 85 92 93 96
D
20%
25V
CERM 2
U8500_VC
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
1 C8516
1UF
MBR0520LXXG
SOD-123
5 6 7 8
2 NOSTUFF
96 93 92 85 7 =PP3V3_GPU
DEVELOPMENT
D
805
20%
1 C8515 D8500 1
1UF R8519
y
U8500_GND 2 6 25V SMB
85 6
VCC VC
2 CERM
805 R8502 Q8501 20%
25V
L8501 3 10BQ040PBF 330
0 IRF7807ZPBF 2 CERM 1.53UH 1 5%
U8500 1 2 Q8501_GATE4 SO-8
805
2
1/16W
MF-LF
IRU3037ACS PPVCORE_GPU 7 86
2 402
SOI-LF 5% SM VOLTAGE=1.25V
1/8W MIN_LINE_WIDTH=0.6MM
CRITICAL HD 5 U8500_GATE_H MF-LF MIN_NECK_WIDTH=0.25MM LED_GPU_CORE_P
r
MIN_LINE_WIDTH=0.45MM 805 MIN_LINE_WIDTH=0.45MM 1 2 3
85 7 =PP3V3_ALL_GPU U8500_SS 8 SS MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM Q8502_DRAIN 1
MIN_LINE_WIDTH=0.6MM
LD 3 U8500_GATE_L MIN_NECK_WIDTH=0.25MM DEVELOPMENT
1
MIN_LINE_WIDTH=0.45MM DEVELOPMENT
1 C8511 U8500_COMP 7 COMP MIN_NECK_WIDTH=0.25MM 1
R8504 NOSTUFF
C8508 C8517 LED8500
0.01UF FB 1 U8500_FEEDBACK 5 6 7 8 5.11 1
1
C8507 R8503
1
10UF
1
10UF
1
C8509 R8520 3
DEVELOPMENT GREEN-3.6MCD
20%
16V
3
1 1% 3300PF 6.98K 20% 20%
1800UF 0 LM339A
2.0X1.25MM-SM
2 GPU_CORE_FOR_LED 10
2 CERM
D
Q8500 R8501 1/4W
MF-LF 10% 1%
1/16W
6.3V
2 CERM
6.3V
2 CERM
20%
2 6.3V
1
SOI-LF
2
R8511 402 15K GND 2 1206 2 50V
CERM MF-LF 805-1 805-1
ELEC 5% V+
2N7002 5% 4 2 402
TH-KZJ-LF 1/16W
U1201 13 LED_GPU_CORE_N
100K 2 SOT23-LF Q8502 R8504_P2 603 MF-LF
a
1 1/16W
85 13 GPU_POWERUP_L 1 U8500_SS_L G S MF-LF 402 GND
5%
1 C8514 2 402
1 C8513 1 C8506 4
IRF7805ZPBF MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
13 12 11 1V1_REF 11
PLACE LED8500 NEAR VREG
1/16W 2 0.1UF R8501_2 56PF 220PF SO-8
12
20% 5% 5% 1
MF-LF
402 16V
2 CERM
50V
2 CERM
25V
2 CERM 1 C8505 R8505
2200PF 10K
603 1 C8523 402 402
5% 1 2 3
1 C8512 0.5%
D8511 0.0047UF 2 50V 1000PF 1/16W
MF-LF 1
C8519 1
C8520
MMBD914XXG 10%
25V
2 CERM
XW8500
SM
CERM
603
5%
50V
2 CERM 2 603 330UF 330UF
1 3 20% 20%
85 6 U8500_GND 402 1 2 1206 2 2.5V-ESR9V 2 2.5V-ESR9V
POLY POLY
n
VOLTAGE=0V
SOT23 MIN_LINE_WIDTH=0.6MM 85 6 U8500_GND CASE-D2E-LF CASE-D2E-LF
MIN_NECK_WIDTH=0.25MM
U5000_FEEDBACK
i
C GPU 1.20V PCIE PVDD C
GPU 1.7V VDDC_CT 96 93 92 85 7 =PP3V3_GPU
PP1V2_GPU_PCIE_PVDD 84
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
PP1V7_GPU_VDDC_CT 86
96 93 92 85 7 =PP3V3_GPU VOLTAGE=1.7V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
R85421 C8540 1 CRITICAL 1
1
R8597 C8590 1 CRITICAL 3.3K 4.7UF R8540
3.3K 4.7UF
1
R8590 5% 20%
6.3V
U8540 1 C8541 10K
1/16W 2 FAN2558 0.001UF 1%
20% U8590 1 C8591 10K CERM
m
5% 6.3V MF-LF 805 SOT23-6-LF 10% 1/16W
1/16W CERM 2 FAN2558 0.001UF 1% 402 2 1 50V MF-LF
MF-LF 805 SOT23-6-LF 10% 1/16W VIN VOUT 6 2 CERM 2 402
=PP3V3_ALL_GPU
2 402 1 VIN VOUT 6 50V
2 CERM
MF-LF 85 7
4 PG 402 1 C8542
2 402
=PP3V3_ALL_GPU 4 PG 402 1 C8592 U8540_EN 3 EN ADJ 5 U8540_ADJ 1uF
85 7
C8544
il
1 10%
U8590_EN 3 EN ADJ 5 FAN2558_ADJ 1uF 2 6.3V
10% 0.01UF GND 1 CERM
1 C8594 GND
6.3V
2 CERM 20% 3 R8541 402
0.22UF
1
R8591 402 2 16V
CERM
2 9.53K
20% 3 2 5.36K R8544 402 D Q8540 1%
1/16W
2 6.3V
X5R 1% 2N7002 MF-LF
402 D Q8590 1/16W
1
47K 2 1 G
SOT23-LF
2 402
R8594 MF-LF 85 13 GPU_POWERUP_L U8540_EN_L S
2N7002 2 402
GPU_POWERUP_L 1
100K 2 U8590_EN_L 1 G S
SOT23-LF 5%
85 13 1/16W 2
MF-LF
5% 402
1/16W 2 VOUT = 0.59V * [1 + R8540 / R8541]
MF-LF
402 VOUT = 0.59V * [1 + R8590 / R8591] VOUT = 1.209V
VOUT = 1.691V
e
GPU 2.5V A2VDD
B GPU 1.80V TPVDD TABLE_5_HEAD
r
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
U8570
MM1572FN
TABLE_5_ITEM
128S0078 1 EL CAP,330UF,20%,16V C8502 PP2V5_GPU_A2VDD 93
96 93 92 85 7 =PP3V3_GPU PP1V8_GPU_TPVDD 93 SOT-25A-LF VOLTAGE=2.5V
VOLTAGE=1.8V SYMBOL NOT READY FOR DVT2 RELEASE 96 93 92 85 7 =PP3V3_GPU CRITICAL MIN_LINE_WIDTH=0.5MM
MIN_LINE_WIDTH=0.5MM 1 5 MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM VIN VOUT
R85621 C8560 1 CRITICAL 1 3 4
3.3K 4.7UF R8560 1 C8570 R8570 1 CONT NOISE U8570_NOISE
5% 20% U8560 1 C8561 10K 1UF
1/16W
MF-LF
6.3V
CERM 2 FAN2558 0.001UF 1%
1/16W 20% 10K
5%
GND
2
C8571 1 1 C8572
402 2
805 SOT23-6-LF 10% MF-LF
10V
2 CERM 1/16W 0.01UF 10UF
1 VIN VOUT 6 2 50V 20% 20%
P
CERM 2 402 805 MF-LF 16V 6.3V
4 PG 402 1 C8562 2 402 CERM 2 2 CERM
402 805-1
U8560_EN 3 EN ADJ 5 U8560_ADJ 1uF
10% U8570_CONT
6.3V
2 CERM
GND 1
3 NOSTUFF
2
R8561 402
3 NOSTUFF
4.87K
D Q8560 1%
1/16W D Q8570
2N7002 MF-LF
2N7002
85 13 GPU_POWERUP_L 1 G S
2
SOT23-LF 2 402
GPU 1.8V VREG 85 13 GPU_POWERUP_L 1 G S
SOT23-LF
CRITICAL 2
VOUT = 0.59V * [1 + R8560 / R8561]
U8580 PP1V8_GPU =PP1V8_GPU 84 86 87 93
VOUT = 1.802V VOLTAGE=1.8V
MIC39102 MIN_LINE_WIDTH=0.6MM
96 93 92 85 7 =PP3V3_GPU SOP-8-LF
MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE
2
IN OUT 3
4
1
EN ADJ
1 C8580 1
R8580 GND
R85811 1
C8583
453 330UF
20%
10UF
6.3V
3.3K
5%
5 6 7 8 1%
1/16W
20%
2 6.3V
Graphics Vregs
2 CERM 1/16W MF-LF ELEC
6.3X8-SM
A 1206
2
MF-LF
402
U8580_ADJ
402 2 SYNC_MASTER=M33-DD
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=06/20/2005
A
1
R8582 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
U8580_EN 1K AGREES TO THE FOLLOWING
1%
3 NOSTUFF 1/16W I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF-LF
402 2 II NOT TO REPRODUCE OR COPY IT
D Q8580 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
2N7002
POWER SEQUENCING FOR RV370/80: =PP3V3_GPU > =PPV_GPU_MEM > VDDC_CT > PPVCORE_GPU GPU_POWERUP_L 1 G S
SOT23-LF
85 13 SIZE DRAWING NUMBER REV.
PP2V5_GPU_A2VDD > PP1V8_GPU > PCIE_PVDD
THE ENTIRE SEQUENCE SHOULD TAKE LESS THAN 40 MS (T1+T3 IN DATABOOK)
2
APPLE COMPUTER INC.
D 051-6863 19
HOWEVER IDEALLY ALL POWER RAILS SHOULD RAMP TOGETHER SCALE SHT OF
POWER DOWN SEQUENCE SHOULD BE IN REVERSE ORDER NONE 85 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
86 85 7 PPVCORE_GPU THERE ARE 45 CORE POWER PINS BETWEEN VDDC & VDDCI
AC13
AC15
AC17
AD13
AD15
M12
M13
M14
M17
M18
M19
N12
N13
N14
N17
N18
N19
P12
P13
P14
P17
P18
P19
U12
U13
U14
U17
U18
U19
V12
V13
V14
V17
V18
V19
W12
W13
W14
W17
W18
W19
1 C8600
10UF
VDDC 20%
D AK2
AJ1
6.3V
2 CERM
805-1 D
AG11
y
AG9
AG5
AD18 1 C8601 1 C8602 1 C8603 1 C8604 1 C8605 1 C8606 1 C8607 1 C8608 1 C8609 1 C8610
AD16 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
U8400 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
r
AD12 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
AC18 402 402 402 402 402 402 402 402 402 402
RV370XT AC16
AC14
BGA AC12
L8650 (2 OF 5) AC4
93 87 85 84 =PP1V8_GPU 1.8UH 1 C8611 1 C8612 1 C8613 1 C8614 1 C8615 1 C8616 1 C8617 1 C8618 1 C8619 1 C8620
1 2
AB8 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
PP1V8_GPU_PVDD
a
VOLTAGE=1.8V OMIT AB7 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
0805 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
MIN_LINE_WIDTH=0.5MM 1 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
MIN_NECK_WIDTH=0.25MM C8650 1 C8651 AB1 402 402 402 402 402 402 402 402 402 402
4.7UF 0.1UF CORE POWER Y4
XW8650
SM
20%
2 6.3V
20%
2 10V AK28 PVDD W15
CERM CERM
1 2 6 GND_GPU_PVSS 805 402 AJ28 PVSS W8
VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM W7
MIN_NECK_WIDTH=0.25MM
V16 1 C8621 1 C8622 1 C8623 1 C8624 1 C8625 1 C8626 1 C8627 1 C8628 1 C8629 1 C8630
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
n
V15 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
H11
PP1V7_GPU_VDDC_CT 85 U16 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
H20 402 402 402 402 402 402 402 402 402 402
U15
M23 VSS U8
C8660 C8661 C8662 C8663 C8664 C8665 C8666 C8667
i
1 1 1 1 1 1 1 1 P8
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF VDD15 U4
10% 10% 10% 10% 10% 10% 10% 10%
Y8
T19
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
C CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
Y23
AC11
T18
T17
C
AC20
T16
T15
T14
86 85 7 PPVCORE_GPU M15 T13
R19 T1
T12 VDDCI R18
m
W16 R17
R16
R15
R14
il
R13
R12
R8
R7
P16
P15
P4
N16
N15
M16
e
M8
M7
VSS
A2
A10
A16
A22
A29
C1
C3
C28
C30
D4
D6
D10
D12
D15
D18
D21
D24
D27
F27
G9
G12
G16
G18
G21
G24
H4
H8
H9
H12
H14
H16
H18
H21
H23
H27
J23
J24
K1
K7
K8
L4
B B
A
P r GPU Core Power
SYNC_MASTER=FINO-M23 SYNC_DATE=08/26/2005
A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 86 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
91 90 89 87 7 =PPV_GPU_MEM
1 C8700 1 C8701 1 C8702 1 C8703 1 C8704 1 C8705 1 C8706 1 C8707 1 C8708 1 C8709 1 C8710 1 C8711 1 C8712 1 C8713 1 C8714 1 C8715 1 C8716 1 C8717 1 C8718 1 C8719
10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805-1 805-1 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
L8730
93 86 85 84 =PP1V8_GPU 1.8UH
D 1 2 PP1V8_GPU_MPVDD D
H22
AA1
AA8
H19
K23
K24
L23
AA4
AA7
AD4
VOLTAGE=1.8V
0805
J4
J1
L8
J7
J8
M4
N7
R1
T7
T8
V7
V8
N4
N8
R4
V4
MIN_LINE_WIDTH=0.5MM
A15
A21
A28
B30
D11
D14
D17
D20
D23
D26
E27
G10
G13
G15
G19
G22
G27
H10
H13
H15
H17
F18
1 C8730 1 C8731
A3
A9
B1
D5
D8
F4
G7
N6
MIN_NECK_WIDTH=0.25MM
y
4.7UF 0.1UF
XW8730 20% 20%
VDDR1 MAB0 N5 FBBA<0> 88 90 91
VDDRH0
VDDRH1
FBD<47> H28 6.3V 10V A7
91 88 DQA0 SM 2 CERM 2 CERM MPVDD MAB1 M1 FBBA<1>
FBD<46> H29 VDDR1 805 402 A6 88 90 91
91 88 DQA1 1 2 6 GND_GPU_MPVSS MPVSS MAB2 M3 FBBA<2>
VOLTAGE=0V 88 90 91
91 88 FBD<44> J28 DQA2 MIN_LINE_WIDTH=0.5MM
MAA0 E22 FBA<0> 88 89 91 MIN_NECK_WIDTH=0.25MM 91 88 FBD<124> D7 DQB0 MAB3 L3 FBBA<3> 88 90 91
J29
r
91 88 FBD<45> DQA3 OMIT MAA1 B22 FBA<1> 88 89 91 91 88 FBD<127> F7 DQB1 MAB4 L2 FBBA<4> 88 90 91
91 88 FBD<43> J26 DQA4 OMIT
MAA2 B23 FBA<2> 88 89 91 91 88 FBD<125> E7 DQB2 MAB5 M2 FBBA<5> 88 90 91
91 88
91 88
FBD<41>
FBD<42>
H25
H26
DQA5
DQA6 U8400 MAA3
MAA4
B24
C23
FBA<3>
FBA<4>
88 89 91
88 89 91
91 88
91 88
FBD<121>
FBD<120>
G6
G5
DQB3
DQB4
U8400
RV370XT
MAB6
MAB7
M5
P6
FBBA<6>
FBBA<7>
88 90 91
88 90 91
91 88 FBD<40>
FBD<34>
G26
G30
DQA7
DQA8
RV370XT MAA5 C22 FBA<5> 88 89 91 91 88 FBD<123> F5 DQB5 BGA MAB8 N3 FBBA<8> 88 90 91
91 88
FBD<38> D29
BGA MAA6 F22 FBA<6> 88 89 91 91 88 FBD<122> E5 DQB6 (4 OF 5) MAB9 K2 FBBA<9> 88 90 91
91 88 DQA9 F21 C4 K3
(3 OF 5) MAA7 FBA<7> FBD<126> DQB7 MAB10 FBBA<10>
a
88 89 91 91 88 88 90 91
91 88 FBD<39> D28 DQA10
MAA8 C21 FBA<8> 88 89 91 91 88 FBD<113> B5 DQB8 MAB11 J2 FBBA<11> 88 90 91
FBD<37> E28 DQA11
MEMORY INTERFACE B
91 88
MAA9 A24 FBA<9> 88 89 91 91 88 FBD<112> C5 DQB9 MAB12 P5 FBBA<12> 88 90 91
91 88 FBD<36> E29 DQA12
MAA10 C24 FBA<10> 88 89 91 91 88 FBD<114> A4 DQB10 MAB13 P3 FBBA<13> 88 90 91
91 88 FBD<32> G29 DQA13
MEMORY INTERFACE A
MAA11 A25 FBA<11> 88 89 91 91 88 FBD<115> B4 DQB11 MAB14 P2 TP_FBBA<14>
91 88 FBD<33> G28 DQA14 MAA12 E21 FBA<12> 88 89 91 91 88 FBD<117> C2 DQB12
91 88 FBD<35> F28 DQA15
MAA13 B20 FBA<13> 88 89 91 91 88 FBD<119> D3 DQB13 DQMB0* E6 FBDQM<15> 88 91
91 88 FBD<62> G25 DQA16
MAA14 C19 TP_FBA<14> 91 88 FBD<116> D1 DQB14 DQMB1* B2 FBDQM<14> 88 91
FBD<63> F26 DQA17
n
91 88
91 88 FBD<118> D2 DQB15 DQMB2* J5 FBDQM<13> 88 91
91 88 FBD<61> E26 DQA18 DQMA0* J25 FBDQM<5> 88 91
91 88 FBD<111> G4 DQB16 DQMB3* G3 FBDQM<12> 88 91
91 88 FBD<60> F25 DQA19 DQMA1* F29 FBDQM<4> 88 91
91 88 FBD<110> H6 DQB17 DQMB4* W6 FBDQM<10> 88 91
91 88 FBD<56> E24 DQA20 DQMA2* E25 FBDQM<7> 88 91
i
91 88 FBD<109> H5 DQB18 DQMB5* W2 FBDQM<11> 88 91
91 88 FBD<59> F23 DQA21 DQMA3* A27 FBDQM<6> 88 91
91 88 FBD<108> J6 DQB19 DQMB6* AC6 FBDQM<8> 88 91
91 88 FBD<57> E23 DQA22 DQMA4* F15 FBDQM<0> 88 91
K5 AD2
C 91 88 FBD<58>
FBD<48>
D22
B29
DQA23 DQMA5*
DQMA6*
C15
C11
FBDQM<1>
FBDQM<3>
88 91
91 88
91 88
FBD<104>
FBD<105> K4
DQB20
DQB21
DQMB7* FBDQM<9> 88 91
C
91 88 DQA24 88 91
FBD<107> L6 QSB0 F6 FBDQS<15>
C29 E11 91 88 DQB22 88 91
91 88 FBD<50> DQA25 DQMA7* FBDQM<2> 88 91
L5 B3
FBD<55> C25 91 88 FBD<106> DQB23 QSB1 FBDQS<14> 88 91
91 88 DQA26 FBD<103> G2 QSB2 K6 FBDQS<13>
FBD<51> C27 QSA0 J27 FBDQS<5>
91 88 DQB24 88 91
91 88 DQA27 88 91
FBD<99> F3 QSB3 G1 FBDQS<12>
B28 F30 91 88 DQB25 88 91
91 88 FBD<49> DQA28 QSA1 FBDQS<4> 88 91
H2 V5
B25 F24 91 88 FBD<102> DQB26 QSB4 FBDQS<10> 88 91
91 88 FBD<54> DQA29 QSA2 FBDQS<7> 88 91
E2 W1
C26 B27 91 88 FBD<97> DQB27 QSB5 FBDQS<11> 88 91
91 88 FBD<52> DQA30 QSA3 FBDQS<6> 88 91
FBD<98> F2 AC5 FBDQS<8>
B26 E16 91 88 DQB28 QSB6 88 91
FBD<53> DQA31 QSA4 FBDQS<0>
m
91 88 88 91
91 88 FBD<100> J3 DQB29 QSB7 AD1 FBDQS<9> 88 91
91 88 FBD<5> F17 DQA32 QSA5 B16 FBDQS<1> 88 91
91 88 FBD<96> F1 DQB30
91 88 FBD<4> E17 DQA33 QSA6 B11 FBDQS<3> 88 91
91 88 FBD<101> H3 DQB31
91 88 FBD<7> D16 DQA34 QSA7 F10 FBDQS<2> 88 91 RASB* R2 FBBRAS_L 88 90 91
il
91 88 FBD<86> U6 DQB32
91 88 FBD<6> F16 DQA35
91 88 FBD<84> U5 DQB33 CASB* T5 FBBCAS_L 88 90 91
91 88 FBD<2> E15 DQA36 91 88 FBD<85> U3 DQB34
91 88 FBD<1> F14 DQA37 RASA* A19 FBARAS_L 88 89 91 WEB* T6 FBBWE_L 88 90 91
91 88 FBD<87> V6 DQB35
91 88 FBD<3> E14 DQA38
CASA* E18 FBACAS_L 88 89 91 91 88 FBD<82> W5 DQB36 CSB0* R5 FBBCS0_L 88 90 91
91 88 FBD<0> F13 DQA39 91 88 FBD<83> W4 DQB37
91 88 FBD<13> C17 DQA40 WEA* E19 FBAWE_L 88 89 91 CSB1* R6 TP_FBBCS1_L 6
91 88 FBD<80> Y6 DQB38
91 88 FBD<15> B18 DQA41 CSA0* E20 FBACS0_L 88 89 91 91 88 FBD<81> Y5 DQB39 CKEB R3 FBBCKE 88 90 91
91 88 FBD<14> B17 DQA42 91 88 FBD<88> U2 DQB40
B15 F20 1
91 88 FBD<9> DQA43 CSA1* TP_FBACS1_L
91 88 FBD<91> V2 DQB41 R8701
91 88 FBD<11> C13 DQA44 CLKB0 N1 FBBCLK1 88 90 10K
e
CKEA B19 FBACKE 88 89 91 91 88 FBD<90> V1 DQB42 5%
91 88 FBD<8> B14 DQA45 CLKB0* N2 FBBCLK1_L 88 90 1/16W
91 88 FBD<89> V3 DQB43 MF-LF
C14 1
91 88 FBD<10> DQA46
CLKA0 B21 FBACLK1 88 89
R8700 91 88 FBD<92> W3 DQB44 CLKB1 T2 FBBCLK0 88 90
2 402
91 88 FBD<12> C16 DQA47 C20
10K Y2 T3
FBD<24> A13 CLKA0* FBACLK1_L 88 89 5% 91 88 FBD<93> DQB45 CLKB1* FBBCLK0_L 88 90
91 88 DQA48 1/16W
FBD<94> Y3
MF-LF 91 88 DQB46
B FBD<26> A12 DQA49 CLKA1 C18 FBACLK0
B
r
91 88 88 89
2 402 91 88 FBD<95> AA2 DQB47 91 90 89 87 7 =PPV_GPU_MEM
91 88 FBD<25> C12 DQA50 CLKA1* A18 FBACLK0_L 88 89
91 88 FBD<71> AA6 DQB48 MEMVMODE 01 NOSTUFF
91 88 FBD<27> B12 DQA51 AA5 C6 1 1
91 88 FBD<28> C10 DQA52
91 88 FBD<69> DQB49
* 1.8V 01
MEMVMODE0 GPU_MEMVMODE0 R8724 R8726
FBD<31> C9 MVREFD B7 GPU_MVREFD =PPV_GPU_MEM 7 87 89 90 91 91 88 FBD<68> AB6 DQB50 4.7K 4.7K
91 88 DQA53 MIN_LINE_WIDTH=0.5MM
FBD<70> AB5 2.5V 10 5% 5%
FBD<30> B9 MIN_NECK_WIDTH=0.25MM 91 88 DQB51 C7 GPU_MEMVMODE1
1/16W 1/16W
91 88 DQA54 B8 1 AD6 2.8V 11 MEMVMODE1 MF-LF MF-LF
91 88 FBD<29> B10 DQA55
MVREFS GPU_MVREFS
MIN_LINE_WIDTH=0.5MM
R8720 91 88 FBD<66> DQB52 402 2 2 402
FBD<23> E13 MIN_NECK_WIDTH=0.25MM 100 91 88 FBD<64> AD5 DQB53
91 88 DQA56 1% AE5 C8 GPU_MEMTEST
FBD<22> E12 1/16W 91 88 FBD<65> DQB54 MEMTEST
DQA57 NOSTUFF
P
91 88 MF-LF MIN_LINE_WIDTH=0.5MM
FBD<67> AE4 DQB55
2 402 91 88 MIN_NECK_WIDTH=0.25MM
1
91 88 FBD<17> E10 DQA58 91 88 FBD<72> AB2 DQB56 R8728 R87251 1
R8727
91 88 FBD<21> F12 DQA59 DIMA_0 D30 TP_GPU_DIMA_0
FBD<73> AB3 DIMB_0 E3 TP_GPU_DIMB_0 47 4.7K 4.7K
F11 B13 1 91 88 DQB57 AA3 TP_GPU_DIMB_1 1% 5% 5%
91 88 FBD<20> DQA60 DIMA_1 TP_GPU_DIMA_1
C8721 1 R8721 91 88 FBD<75> AC2 DQB58
DIMB_1 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
91 88 FBD<16> E9 DQA61 0.1UF 100 FBD<74> AC3 2 402 402 2 2 402
FBD<18> F9 20% 1% 91 88 DQB59
91 88 DQA62 10V 1/16W
FBD<78> AD3
FBD<19> F8 CERM 2 MF-LF 91 88 DQB60
91 88 DQA63 VSSRH0 VSSRH1 402 2 402 FBD<79> AE1
91 88 DQB61
91 88 FBD<76> AE2 DQB62
F19
M6
91 88 FBD<77> AE3 DQB63
=PPV_GPU_MEM 7 87 89 90 91
1
R8722
100
1%
1/16W
MF-LF
2 402
GPU Frame Buffer
1
A R8723 SYNC_MASTER=FINO-M23 SYNC_DATE=08/26/2005
C8723
0.1UF
20%
1
100
1% NOTICE OF PROPRIETARY PROPERTY
A
10V 1/16W
CERM 2 MF-LF
402 2 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 87 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACE R’S CLOSE TO MEMORY
FRAME BUFFER A TERMINATION PLACE CLOCK TERMINATION AFTER MEMORY
GPU -> MEMORY -> TERMINATION
FBD<31> 22 3 6 RP8820 RFBD<31> FBD<32> 22 3 6 RP8828 RFBD<32>
91 88 87
22 4 5 RP8820
6 88 89 91 88 87
22 4 5 RP8828
6 88 89
91 88 87 FBDQS<0> 22 1 2 R8800 RFBDQS<0> 89
91 88 87 FBD<30> RFBD<30> 6 88 89 91 88 87 FBD<33> RFBD<33> 6 88 89
91 88 87 FBD<29> 22 1 8 RP8820 RFBD<29> 88 89 91 88 87 FBD<34> 22 2 7 RP8828 RFBD<34> 6 88 89 91 88 87 FBDQS<1> 22 1 2 R8801 RFBDQS<1> 89
RP8820 RP8828 89 88 87 FBACLK0
FBD<28> 22 2 7 RFBD<28> FBD<35> 22 1 8 RFBD<35>
91 88 87
22 3 6 RP8821
6 88 89 91 88 87
22 4 5 RP8816
88 89
91 88 87 FBDQS<2> 22 1 2 R8802 RFBDQS<2> 89
91 88 87 FBD<27> RFBD<27> 6 88 89 91 88 87 FBD<36> RFBD<36> 6 88 89
91 88 87 FBD<26> 22 4 5 RP8821 RFBD<26> 6 88 89 91 88 87 FBD<37> 22 3 6 RP8816 RFBD<37> 6 88 89 91 88 87 FBDQS<3> 22 1 2 R8803 RFBDQS<3> 89
R88201
D 91 88 87 FBD<25> 22
22
2
1
7
8
RP8821
RP8821
RFBD<25> 6 88 89 91 88 87 FBD<38> 22
22
2
1
7
8
RP8816
RP8816
RFBD<38> 6 88 89
91 88 87 FBDQS<4> 22 1 2 R8804 RFBDQS<4> 89
56.2
1%
1/16W
D
91 88 87 FBD<24> RFBD<24> 88 89 91 88 87 FBD<39> RFBD<39> 88 89 MF-LF
RP8822 RP8829 R8805 402 2
y
91 88 87 FBD<0> 22 1 8 RFBD<0> 88 89 91 88 87 FBD<40> 22 3 6 RFBD<40> 6 88 89 91 88 87 FBDQS<5> 22 1 2 RFBDQS<5> 89
2 7 RP8822 4 5 RP8829 FBACLK0_TERM
FBD<1> 22 RFBD<1> FBD<41> 22 RFBD<41>
91 88 87
4 5 RP8822
6 88 89 91 88 87
2 7 RP8829
6 88 89
91 88 87 FBDQS<6> 22 1 2 R8806 RFBDQS<6> 89
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
91 88 87 FBD<2> 22
22 3 6 RP8822
RFBD<2> 6 88 89 91 88 87 FBD<42> 22
22 1 8 RP8829
RFBD<42> 6 88 89
R8807 R88211 C8821 1
91 88 87 FBD<3> RFBD<3> 6 88 89 91 88 87 FBD<43> RFBD<43> 88 89 91 88 87 FBDQS<7> 22 1 2 RFBDQS<7> 89 56.2 0.01UF
1 8 RP8823 4 5 RP8830 1% 20%
91 88 87 FBD<17> 22 RFBD<17> 88 89 91 88 87 FBD<44> 22 RFBD<44> 6 88 89 1/16W 16V
r
22 2 7 RP8823 22 3 6 RP8830 MF-LF CERM 2
91 88 87 FBD<16> RFBD<16> 6 88 89 91 88 87 FBD<45> RFBD<45> 6 88 89 402 2 402
FBD<18> 22 3 6 RP8823 RFBD<18> FBD<46> 22 1 8 RP8830 RFBD<46>
91 88 87 6 88 89 91 88 87 88 89
FBD<19> 22 4 5 RP8823 RFBD<19> FBD<47> 22 2 7 RP8830 RFBD<47> FBACLK0_L
91 88 87
22 4 5 RP8824
6 88 89 91 88 87
22 4 5 RP8831
6 88 89
91 88 87 FBDQM<0> 22 1 2 R8830 RFBDQM<0> 89
89 88 87
91 88 87 FBD<15> RFBD<15> 6 88 89 91 88 87 FBD<48> RFBD<48> 6 88 89
91 88 87 FBD<14> 22 3 6 RP8824 RFBD<14> 6 88 89 91 88 87 FBD<49> 22 2 7 RP8831 RFBD<49> 6 88 89 91 88 87 FBDQM<1> 22 1 2 R8831 RFBDQM<1> 89
FBD<13> 22 2 7 RP8824 RFBD<13> FBD<50> 22 3 6 RP8831 RFBD<50>
91 88 87
22 1 8 RP8824
6 88 89 91 88 87
22 1 8 RP8831
6 88 89
91 88 87 FBDQM<2> 22 1 2 R8832 RFBDQM<2> 89 89 88 87 FBACLK1
FBD<12> RFBD<12> FBD<51> RFBD<51>
a
91 88 87 88 89 91 88 87 9 88 89
91 88 87 FBD<10> 22 3 6 RP8825 RFBD<10> 6 88 89 91 88 87 FBD<52> 22 3 6 RP8800 RFBD<52> 6 88 89 91 88 87 FBDQM<3> 22 1 2 R8833 RFBDQM<3> 89
91 88 87 FBD<11> 22 4 5 RP8825 RFBD<11> 6 88 89 91 88 87 FBD<53> 22 4 5 RP8800 RFBD<53> 6 88 89
R8834 R88221
22 1 8 RP8825 22 2 7 RP8800 91 88 87 FBDQM<4> 22 1 2 RFBDQM<4> 89 56.2
91 88 87 FBD<9> RFBD<9> 88 89 91 88 87 FBD<54> RFBD<54> 6 88 89 1%
91 88 87 FBD<8> 22 2 7 RP8825 RFBD<8> 6 88 89 91 88 87 FBD<55> 22 1 8 RP8800 RFBD<55> 88 89 91 88 87 FBDQM<5> 22 1 2 R8835 RFBDQM<5> 89
1/16W
MF-LF
22 2 7 RP8826 22 4 5 RP8801 402 2
91 88 87 FBD<5> RFBD<5> 6 88 89 91 88 87 FBD<56> RFBD<56> 6 88 89
R8836
22 3 6 RP8826 22 3 6 RP8801 91 88 87 FBDQM<6> 22 1 2 RFBDQM<6> 89 FBACLK1_TERM
91 88 87 FBD<6> RFBD<6> 6 88 89 91 88 87 FBD<57> RFBD<57> 6 88 89 MIN_LINE_WIDTH=0.5MM
91 88 87 FBD<4> 22 1 8 RP8826 RFBD<4> 88 89 91 88 87 FBD<58> 22 1 8 RP8801 RFBD<58> 88 89 91 88 87 FBDQM<7> 22 1 2 R8837 RFBDQM<7> 89 R88231
MIN_NECK_WIDTH=0.25MM
n
RP8826 RP8801
91 88 87 FBD<7> 22 4 5
RP8827
RFBD<7> 6 88 89 91 88 87 FBD<59> 22 2 7
RP8802
RFBD<59> 6 88 89 56.2
1%
C8823 1
91 88 87 FBD<20> 22 1 8 RFBD<20> 88 89 91 88 87 FBD<60> 22 4 5 RFBD<60> 6 88 89 1/16W 0.01UF
MF-LF 20%
FBD<21> 22 2 7 RP8827 RFBD<21> FBD<61> 22 2 7 RP8802 RFBD<61> 16V
91 88 87 6 88 89 91 88 87 6 88 89 402 2 CERM 2
3 6 RP8827 3 6 RP8802 402
i
91 88 87 FBD<22> 22 RFBD<22> 6 88 89 91 88 87 FBD<62> 22 RFBD<62> 6 88 89
FBD<23> 22 4 5 RP8827 RFBD<23> FBD<63> 22 1 8 RP8802 RFBD<63> FBACLK1_L
91 88 87 6 88 89 91 88 87 88 89 89 88 87
C C
FRAME BUFFER B TERMINATION
FBBCLK0
m
FBD<64> 22 1 8 RP8810 RFBD<64> FBD<96> 22 4 5 RP8815 RFBD<96>
90 88 87
91 88 87
22 4 5 RP8810
88 90 91 88 87
22 3 6 RP8815
6 88 90
91 88 87 FBDQS<8> 22 1 2 R8808 RFBDQS<8> 90
91 88 87 FBD<65> RFBD<65> 6 88 90 91 88 87 FBD<97> RFBD<97> 6 88 90
91 88 87 FBD<66> 22 2 7 RP8810 RFBD<66> 6 88 90 91 88 87 FBD<98> 22 2 7 RP8815 RFBD<98> 6 88 90 91 88 87 FBDQS<9> 22 1 2 R8809 RFBDQS<9> 90
R88241
22 3 6 RP8810 22 1 8 RP8815 56.2
il
91 88 87 FBD<67> RFBD<67> 6 88 90 91 88 87 FBD<99> RFBD<99> 88 90
R8810 1%
22 1 8 RP8809 22 4 5 RP8814 91 88 87 FBDQS<10> 22 1 2 RFBDQS<10> 90 1/16W
91 88 87 FBD<84> RFBD<84> 88 90 91 88 87 FBD<100> RFBD<100> 6 88 90 MF-LF
91 88 87 FBD<85> 22 2 7 RP8809 RFBD<85> 6 88 90 91 88 87 FBD<101> 22 3 6 RP8814 RFBD<101> 6 88 90 91 88 87 FBDQS<11> 22 1 2 R8811 RFBDQS<11> 90
402 2
RP8809 RP8814 FBBCLK0_TERM
FBD<86> 22 3 6 RFBD<86> FBD<102> 22 2 7 RFBD<102>
91 88 87
22 4 5 RP8809
6 88 90 91 88 87
22 1 8 RP8814
6 88 90
91 88 87 FBDQS<12> 22 1 2 R8812 RFBDQS<12> 90
1
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
91 88 87 FBD<87>
RP8819
RFBD<87> 6 88 90 91 88 87 FBD<103>
RP8812
RFBD<103> 88 90
R8813 R8825
91 88 87 FBD<72> 22 2 7
RP8819
RFBD<72> 6 88 90 91 88 87 FBD<104> 22 4 5
RP8812
RFBD<104> 6 88 90 91 88 87 FBDQS<13> 22 1 2 RFBDQS<13> 90 56.2
1%
C8825 1
FBD<73> 22 1 8 RFBD<73> FBD<105> 22 3 6 RFBD<105> 0.01UF
91 88 87
22 4 5 RP8819
88 90 91 88 87
22 2 7 RP8812
6 88 90
91 88 87 FBDQS<14> 22 1 2 R8814 RFBDQS<14> 90
1/16W
MF-LF 20%
16V
91 88 87 FBD<75> RFBD<75> 6 88 90 91 88 87 FBD<106> RFBD<106> 6 88 90 402 2 CERM 2
91 88 87 FBD<74> 22 3 6 RP8819 RFBD<74> 6 88 90 91 88 87 FBD<107> 22 1 8 RP8812 RFBD<107> 88 90 91 88 87 FBDQS<15> 22 1 2 R8815 RFBDQS<15> 90
402
FBD<68> 22 1 8 RP8808 RFBD<68> FBD<108> 22 4 5 RP8813 RFBD<108> FBBCLK0_L
91 88 87 88 90 91 88 87 6 88 90 90 88 87
22 2 7 RP8808 22 3 6 RP8813
e
91 88 87 FBD<70> RFBD<70> 6 88 90 91 88 87 FBD<109> RFBD<109> 6 88 90
FBD<69> 22 3 6 RP8808 RFBD<69> FBD<110> 22 2 7 RP8813 RFBD<110>
91 88 87 6 88 90 91 88 87 6 88 90
FBD<71> 22 4 5 RP8808 RFBD<71> FBD<111> 22 1 8 RP8813 RFBD<111>
91 88 87 6 88 90 91 88 87 88 90
RP8807 RP8811 R8838 90 88 87 FBBCLK1
91 88 87 FBD<80> 22 1 8 RFBD<80> 88 90 91 88 87 FBD<112> 22 3 6 RFBD<112> 6 88 90 91 88 87 FBDQM<8> 22 1 2 RFBDQM<8> 90
FBD<81> 22 2 7 RP8807 RFBD<81> FBD<113> 22 4 5 RP8811 RFBD<113>
91 88 87 6 88 90 91 88 87 6 88 90
R8839
B FBDQM<9> 22 1 2 RFBDQM<9> R88261 B
r
FBD<82> 22 3 6 RP8807 RFBD<82> FBD<114> 22 2 7 RP8811 RFBD<114>
91 88 87 90
91 88 87 6 88 90 91 88 87 6 88 90
22 4 5 RP8807 22 1 8 RP8811 R8840 56.2
91 88 87 FBD<83> RFBD<83> 6 88 90 91 88 87 FBD<115> RFBD<115> 88 90 91 88 87 FBDQM<10> 22 1 2 RFBDQM<10> 90 1%
2 7 RP8817 3 6 RP8806 1/16W
FBD<76> 22 RFBD<76> FBD<116> 22 RFBD<116>
91 88 87
22 1 8 RP8817
6 88 90 91 88 87
22 4 5 RP8806
6 88 90
91 88 87 FBDQM<11> 22 1 2 R8841 RFBDQM<11> 90
MF-LF
402 2
91 88 87 FBD<77> RFBD<77> 88 90 91 88 87 FBD<117> RFBD<117> 6 88 90
RP8817 RP8806 R8842 FBBCLK1_TERM
91 88 87 FBD<78> 22 4 5 RFBD<78> 6 88 90 91 88 87 FBD<118> 22 2 7 RFBD<118> 6 88 90 91 88 87 FBDQM<12> 22 1 2 RFBDQM<12> 90 MIN_LINE_WIDTH=0.5MM
3 6 RP8817 1 8 RP8806 MIN_NECK_WIDTH=0.25MM
91 88 87 FBD<79> 22
RP8818
RFBD<79> 6 88 90 91 88 87 FBD<119> 22
RP8804
RFBD<119> 88 90
FBDQM<13> 22 1 2 R8843 RFBDQM<13> R88271
91 88 87 FBD<91> 22 3 6 RFBD<91> 6 88 90 91 88 87 FBD<120> 22 3 6 RFBD<120> 6 88 90
91 88 87 90
56.2 C8827 1
91 88 87 FBD<90> 22 4 5 RP8818 RFBD<90> 6 88 90 91 88 87 FBD<121> 22 4 5 RP8804 RFBD<121> 6 88 90 91 88 87 FBDQM<14> 22 1 2 R8844 RFBDQM<14> 90
1%
1/16W 0.01UF
20%
P
1 8 RP8818 2 7 RP8804 MF-LF 16V
FBD<89> 22 RFBD<89> FBD<122> 22 RFBD<122>
91 88 87
22 2 7 RP8818
88 90 91 88 87
22 1 8 RP8804
6 88 90
91 88 87 FBDQM<15> 22 1 2 R8845 RFBDQM<15> 90
402 2 CERM 2
402
91 88 87 FBD<88> RFBD<88> 6 88 90 91 88 87 FBD<123> RFBD<123> 88 90
FBD<95> 22 3 6 RP8803 RFBD<95> FBD<124> 22 4 5 RP8805 RFBD<124> FBBCLK1_L
91 88 87 6 88 90 91 88 87 6 88 90 90 88 87
FBD<94> 22 4 5 RP8803 RFBD<94> FBD<125> 22 2 7 RP8805 RFBD<125>
91 88 87 6 88 90 91 88 87 6 88 90
FBD<93> 22 1 8 RP8803 RFBD<93> FBD<126> 22 3 6 RP8805 RFBD<126>
91 88 87 88 90 91 88 87 6 88 90
FBD<92> 22 2 7 RP8803 RFBD<92> FBD<127> 22 1 8 RP8805 RFBD<127>
91 88 87 6 88 90 91 88 87 88 90
ELECTRICAL_CONSTRAINT_SET NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR
91 88 87 FBD<127..0> GPU_FB GPU_FB I421
90 89 88 9 6 RFBD<127..0> GPU_FB GPU_FB I425
91 89 87 FBA<13..0> GPU_FB GPU_FB I426 FB Series Termination
91 90 87 FBBA<13..0> GPU_FB GPU_FB I427
A 91 88 87
91 88 87
FBDQM<15..0>
FBDQS<15..0>
GPU_FB
GPU_FB
GPU_FB
GPU_FBDQS
I428
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
I429
91 89 87 FBARAS_L GPU_FB GPU_FB I469 ELECTRICAL_CONSTRAINT_SET NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
91 89 87 FBACAS_L GPU_FB GPU_FB I470 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
89 88 87 FBACLK0 GPU_FBCLK GPU_FBCLK FBACLK0 I483 AGREES TO THE FOLLOWING
91 89 87 FBAWE_L GPU_FB GPU_FB I471
89 88 87 FBACLK0_L GPU_FBCLK GPU_FBCLK FBACLK0 I484 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
91 89 87 FBACS0_L GPU_FB GPU_FB I472
89 88 87 FBACLK1 GPU_FBCLK GPU_FBCLK FBACLK1 I489 II NOT TO REPRODUCE OR COPY IT
91 89 87 FBACKE GPU_FB GPU_FB I473
89 88 87 FBACLK1_L GPU_FBCLK GPU_FBCLK FBACLK1 I490 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
91 90 87 FBBRAS_L GPU_FB GPU_FB I494
90 88 87 FBBCLK0 GPU_FBCLK GPU_FBCLK FBBCLK0 I491
91 90 87 FBBCAS_L GPU_FB GPU_FB I493 SIZE DRAWING NUMBER REV.
90 88 87 FBBCLK0_L GPU_FBCLK GPU_FBCLK FBBCLK0 I487
FBBWE_L
91 90 87
91 90 87 FBBCS0_L
GPU_FB
GPU_FB
GPU_FB
GPU_FB
I495
I496
90 88 87 FBBCLK1 GPU_FBCLK GPU_FBCLK FBBCLK1 I488
APPLE COMPUTER INC.
D 051-6863 19
90 88 87 FBBCLK1_L GPU_FBCLK GPU_FBCLK FBBCLK1 I492
91 90 87 FBBCKE GPU_FB GPU_FB I497 SCALE SHT OF
NONE 88 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
91 90 89 87 7 =PPV_GPU_MEM 91 90 89 87 7 =PPV_GPU_MEM
1 C8900 1 C8901 1 C8902 1 C8903 1 C8904 1 C8905 1 C8906 1 C8907 1 C8908 1 C8909 1 C8920 1 C8921 1 C8922 1 C8923 1 C8924 1 C8925 1 C8926 1 C8927 1 C8928 1 C8929
10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
805-1 805-1 402 402 402 402 402 402 402 402 805-1 805-1 402 402 402 402 402 402 402 402
D D
91 90 89 87 7 =PPV_GPU_MEM
y
91 90 89 87 7 =PPV_GPU_MEM
U8900 U8901
8MX32-300MHZ-1.8V
8MX32-300MHZ-1.8V FBGA
FBGA D7
(2 OF 2)
E5
(2 OF 2)
D7 E5 OMIT
D8 E7
r
D8
OMIT
E7 U8900 E4 E8 U8901
E4 E8
8MX32-300MHZ-1.8V
FBGA 8MX32-300MHZ-1.8V
E11 E10
91 89 88 87 FBA<0> N5 A0 (1 OF 2)
E11 E10
N5 FBGA
N6 DQ0 B7 L4 VDD K6
91 89 88 87 FBA<0> A0 (1 OF 2)
VDD 91 89 88 87 FBA<1> A1 OMIT RFBD<23> 6 88
L4 K6 VSS 91 89 88 87 FBA<1> N6 A1 OMIT DQ0 B7 RFBD<41> 6 88
VSS 91 89 88 87 FBA<2> M6 A2 DQ1 C6 RFBD<21> 6 88 L7 K7
L7 K7 91 89 88 87 FBA<2> M6 A2 DQ1 C6 RFBD<42> 6 88
91 89 88 87 FBA<3> N7 A3 DQ2 B6 RFBD<22> 6 88 L8 K8
L8 K8 91 89 88 87 FBA<3> N7 A3 DQ2 B6 RFBD<40> 6 88
91 89 88 87 FBA<4> N8 A4 DQ3 B5 RFBD<20> 88 L11 K9
L11 K9 FBA<4> N8 A4 DQ3 B5 RFBD<43>
a
91 89 88 87 88
91 89 88 87 FBA<5> M9 A5 DQ4 C2 RFBD<19> 6 88 L5
L5 C3 91 89 88 87 FBA<5> M9 A5 DQ4 C2 RFBD<44> 6 88
C3 91 89 88 87 FBA<6> N9 A6 DQ5 D3 RFBD<18> 6 88
L10
L10 C5 91 89 88 87 FBA<6> N9 A6 DQ5 D3 RFBD<45> 6 88
C5 91 89 88 87 FBA<7> N10 A7 DQ6 D2 RFBD<16> 6 88
C7 F6 91 89 88 87 FBA<7> N10 A7 DQ6 D2 RFBD<47> 6 88
C7 F6 91 89 88 87 FBA<8> N11 A8/AP DQ7 E2 RFBD<17> 88
C8 F7 91 89 88 87 FBA<8> N11 A8/AP DQ7 E2 RFBD<46> 88
C8 F7 91 89 88 87 FBA<9> M8 A9 DQ8 K13 RFBD<14> 6 88
C10 F8 91 89 88 87 FBA<9> M8 A9 DQ8 K13 RFBD<50> 6 88
C10 F8 91 89 88 87 FBA<10> L6 A10 DQ9 K12 RFBD<15> 6 88
C12 F9 91 89 88 87 FBA<10> L6 A10 DQ9 K12 RFBD<48> 6 88
C12 F9 91 89 88 87 FBA<11> M7 A11 DQ10 J13 RFBD<12> 88
E3 G6 91 89 88 87 FBA<11> M7 A11 DQ10 J13 RFBD<51> 9 88
E3 G6 DQ11 J12 RFBD<13>
n
6 88
88 RFBDQS<2> B2 DQS0 E12 G7 DQ11 J12 RFBD<49> 6 88
E12 G7 DQ12 G13 RFBD<11> 6 88 VDDQ 88 RFBDQS<5> B2 DQS0
VDDQ 88 RFBDQS<1> H13 DQS1 F4 G8 DQ12 G13 RFBD<53> 6 88
F4 G8 DQ13 G12 RFBD<10> 6 88 88 RFBDQS<6> H13 DQS1
88 RFBDQS<3> H2 DQS2 F11 VSS_THERM G9 DQ13 G12 RFBD<52> 6 88
F11 VSS_THERM G9 DQ14 F13 RFBD<8> 6 88 88 RFBDQS<4> H2 DQS2
i
88 RFBDQS<0> B13 DQS3 G4 H6 DQ14 F13 RFBD<54> 6 88
G4 H6 DQ15 F12 RFBD<9> 88 88 RFBDQS<7> B13 DQS3
G11 H7 DQ15 F12 RFBD<55> 88
G11 H7 88 RFBDQM<2> B3 DM0 DQ16 F3 RFBD<30> 6 88
DQ16
C R8900 1
J11
J4 H8
H9
88
88
RFBDQM<1>
RFBDQM<3>
H12
H3
DM1
DM2
DQ17
DQ18
F2
G3
RFBD<31>
RFBD<28>
6 88
6 88
R89011
4.7K
J4
J11
H8
H9
88
88
RFBDQM<5>
RFBDQM<6>
B3
H12
DM0
DM1 DQ17
F3
F2
RFBD<32>
RFBD<33>
6 88
6 88
C
4.7K 1% K4 J6 88 RFBDQM<4> H3 DM2 DQ18 G3 RFBD<35> 88
1% K4 J6 88 RFBDQM<0> B12 DM3 DQ19 G2 RFBD<29> 88 1/16W
1/16W MF-LF K11 J7 88 RFBDQM<7> B12 DM3 DQ19 G2 RFBD<34> 6 88
MF-LF K11 J7 DQ20 J3 RFBD<27> 6 88 402 2
402 2 91 89 88 87 FBA<12> N4 BA0 J8 DQ20 J3 RFBD<37> 6 88
J8 DQ21 J2 RFBD<26> 6 88 FBA1_VREF N13 VREF 91 89 88 87 FBA<12> N4 BA0
FBA0_VREF N13 VREF 91 89 88 87 FBA<13> M5 BA1 VOLTAGE=0.9V J9 DQ21 J2 RFBD<36> 6 88
VOLTAGE=0.9V J9 DQ22 K2 RFBD<25> 6 88 MIN_LINE_WIDTH=0.5MM 91 89 88 87 FBA<13> M5 BA1
MIN_LINE_WIDTH=0.5MM
1 MIN_NECK_WIDTH=0.25MM DQ22 K2 RFBD<38> 6 88
1 MIN_NECK_WIDTH=0.25MM 88 87 FBACLK0 M11 CK DQ23 K3 RFBD<24> 88
R8951 B4
R8950 B4 FBACLK1 M11 CK DQ23 K3 RFBD<39>
4.7K 1 C8950 B11
88 87 FBACLK0_L M12 CK DQ24 E13 RFBD<7> 6 88 4.7K
1%
1 C8951 B11
88 87
FBACLK1_L M12 CK DQ24 E13 RFBD<56>
88
FBACKE N12 CKE DQ25 D13 RFBD<6> 0.01UF D4
88 87 6 88
m
1% 0.01UF 91 89 88 87 6 88 1/16W 20%
1/16W D4 MF-LF 91 89 88 87 FBACKE N12 CKE DQ25 D13 RFBD<57> 6 88
MF-LF 20%
16V 91 89 88 87 FBACS0_L N2 CS DQ26 D12 RFBD<5> 6 88 402 2 2 16V
CERM
D5
402 2 2 CERM D5
402 91 89 88 87 FBACS0_L N2 CS DQ26 D12 RFBD<59> 6 88
402 91 89 88 87 FBARAS_L M2 RAS DQ27 C13 RFBD<4> 88 D6
D6 91 89 88 87 FBARAS_L M2 RAS DQ27 C13 RFBD<58> 88
91 89 88 87 FBACAS_L L2 CAS DQ28 B10 RFBD<2> 6 88 D9
il
D9 91 89 88 87 FBACAS_L L2 CAS DQ28 B10 RFBD<60> 6 88
91 89 88 87 FBAWE_L L3 WE DQ29 B9 RFBD<1> 6 88 D10
D10 91 89 88 87 FBAWE_L L3 WE DQ29 B9 RFBD<61> 6 88
DQ30 C9 RFBD<3> 6 88
D11
D11 C4 DQ30 C9 RFBD<62> 6 88
DQ31 B8 RFBD<0> 88 E6 C4
E6 C11
VSSQ E9 C11
DQ31 B8 RFBD<63> 88
VSSQ E9 H4 MCL/NC M13
F5 H11
F5 H4 MCL/NC M13
RFU1/NC L9 NC F10 H11
F10 L12
NC RFU1/NC L9 NC
RFU2/NC M10 NC G5 L12
NC
G5 L13
G10 L13
RFU2/NC M10 NC
G10 M3
H5 M3
H5 M4
H10 M4
e
H10 N3
J5 N3
J5
J10
J10
K5
K5
K10
K10
B B
A
ZH8900
HOLE-VIA
1
ZH8901
HOLE-VIA
1
ZH8902
HOLE-VIA
1
ZH8903
HOLE-VIA
91 90 89 87 7 =PPV_GPU_MEM
ZH8906
HOLE-VIA
1
ZH8907
HOLE-VIA
1
ZH8908
HOLE-VIA
1
ZH8909
HOLE-VIA
1 C8910
0.1UF
20%
2 10V
CERM
402
GROUND VIAS FOR SIGNAL LAYER TRANSITIONS
1
ZH8912
C8911
0.1UF
20%
2 10V
CERM
402
HOLE-VIA
1
ZH8913
HOLE-VIA
1
ZH8914
HOLE-VIA
1
ZH8915
HOLE-VIA
1 C8912
0.1UF
20%
2 10V
CERM
402
ZH8918
HOLE-VIA
1
ZH8919
HOLE-VIA
1
ZH8920
HOLE-VIA
1
ZH8921
HOLE-VIA
1
P
C8913
0.1UF
20%
2 10V
CERM
402
1 C8914
0.1UF
20%
2 10V
CERM
402
1
r
C8915
0.1UF
20%
2 10V
CERM
402
1 C8916
0.1UF
20%
2 10V
CERM
402
1
20%
2 10V
C8917
0.1UF
CERM
402
1
20%
2 10V
C8918
CERM
402
0.1UF
1 C8919
0.1UF
20%
2 10V
CERM
402
91 90 89 87 7 =PPV_GPU_MEM
1 C8930
0.1UF
20%
2 10V
CERM
402
1 C8931
0.1UF
20%
2 10V
CERM
402
1 C8932
0.1UF
20%
2 10V
CERM
402
1 C8933
0.1UF
20%
2 10V
CERM
402
1 C8934
0.1UF
20%
2 10V
CERM
402
1 C8935
0.1UF
20%
2 10V
CERM
402
1 C8936
0.1UF
20%
2 10V
CERM
402
1 C8937
0.1UF
20%
2 10V
CERM
402
1 C8938
0.1UF
20%
2 10V
GPU GDDR SDRAM A
SYNC_MASTER=FINO-M23
CERM
402
1 C8939
0.1UF
20%
2 10V
CERM
402
SYNC_DATE=08/26/2005
A
1 1 1 1
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION NOTICE OF PROPRIETARY PROPERTY
333S0319 2 SDRAM,4MX32,GDDR,300MHZ,1.8V,SAM U8900,U8901 CRITICAL FB64MB_300MHZ_SAM SAMSUNG THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
ZH8904 ZH8910 ZH8916 ZH8922 333S0311 2 SDRAM,8MX32,GDDR,300MHZ,1.8V,SAM U8900,U8901 CRITICAL FB128MB_300MHZ_SAM
AGREES TO THE FOLLOWING
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1 1 1 1
333S0312 2 SDRAM,8MX32,GDDR,350MHZ,1.8V,SAM U8900,U8901 CRITICAL FB128MB_350MHZ_SAM II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ZH8905 ZH8911 ZH8917 ZH8923
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA 333S0320 2 SDRAM,4MX32,GDDR,300MHZ,1.8V,HYN U8900,U8901 CRITICAL FB64MB_300MHZ_HYN HYNIX SIZE DRAWING NUMBER REV.
1 1 1 1
333S0314 2 SDRAM,8MX32,GDDR,300MHZ,1.8V,HYN U8900,U8901 CRITICAL FB128MB_300MHZ_HYN
APPLE COMPUTER INC.
D 051-6863 19
333S0315 2 SDRAM,8MX32,GDDR,350MHZ,1.8V,HYN U8900,U8901 CRITICAL FB128MB_350MHZ_HYN SCALE SHT OF
NONE 89 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
91 90 89 87 7 =PPV_GPU_MEM 91 90 89 87 7 =PPV_GPU_MEM
1 C9000 1 C9001 1 C9002 1 C9003 1 C9004 1 C9005 1 C9006 1 C9007 1 C9008 1 C9009 1 C9020 1 C9021 1 C9022 1 C9023 1 C9024 1 C9025 1 C9026 1 C9027 1 C9028 1 C9029
10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
805-1 805-1 402 402 402 402 402 402 402 402 805-1 805-1 402 402 402 402 402 402 402 402
D D
91 90 89 87 7 =PPV_GPU_MEM
y
91 90 89 87 7 =PPV_GPU_MEM
U9000 U9001
8MX32-300MHZ-1.8V
8MX32-300MHZ-1.8V FBGA
FBGA D7
(2 OF 2)
E5
(2 OF 2)
D7 E5 OMIT
D8 E7
r
D8
OMIT
E7 U9000 E4 E8 U9001
E4 E8
8MX32-300MHZ-1.8V
FBGA 8MX32-300MHZ-1.8V
E11 E10
91 90 88 87 FBBA<0> N5 A0 (1 OF 2)
E11 E10
N5 FBGA
N6 DQ0 B7 L4 VDD K6
91 90 88 87 FBBA<0> A0 (1 OF 2)
VDD 91 90 88 87 FBBA<1> A1 OMIT RFBD<71> 6 88
L4 K6 VSS 91 90 88 87 FBBA<1> N6 A1 OMIT DQ0 B7 RFBD<121> 6 88
VSS 91 90 88 87 FBBA<2> M6 A2 DQ1 C6 RFBD<70> 6 88 L7 K7
L7 K7 91 90 88 87 FBBA<2> M6 A2 DQ1 C6 RFBD<122> 6 88
91 90 88 87 FBBA<3> N7 A3 DQ2 B6 RFBD<69> 6 88 L8 K8
L8 K8 91 90 88 87 FBBA<3> N7 A3 DQ2 B6 RFBD<120> 6 88
91 90 88 87 FBBA<4> N8 A4 DQ3 B5 RFBD<68> 88 L11 K9
L11 K9 FBBA<4> N8 A4 DQ3 B5 RFBD<123>
a
91 90 88 87 88
91 90 88 87 FBBA<5> M9 A5 DQ4 C2 RFBD<65> 6 88 L5
L5 C3 91 90 88 87 FBBA<5> M9 A5 DQ4 C2 RFBD<124> 6 88
C3 91 90 88 87 FBBA<6> N9 A6 DQ5 D3 RFBD<67> 6 88
L10
L10 C5 91 90 88 87 FBBA<6> N9 A6 DQ5 D3 RFBD<126> 6 88
C5 91 90 88 87 FBBA<7> N10 A7 DQ6 D2 RFBD<66> 6 88
C7 F6 91 90 88 87 FBBA<7> N10 A7 DQ6 D2 RFBD<125> 6 88
C7 F6 91 90 88 87 FBBA<8> N11 A8/AP DQ7 E2 RFBD<64> 88
C8 F7 91 90 88 87 FBBA<8> N11 A8/AP DQ7 E2 RFBD<127> 88
C8 F7 91 90 88 87 FBBA<9> M8 A9 DQ8 K13 RFBD<95> 6 88
C10 F8 91 90 88 87 FBBA<9> M8 A9 DQ8 K13 RFBD<97> 6 88
C10 F8 91 90 88 87 FBBA<10> L6 A10 DQ9 K12 RFBD<94> 6 88
C12 F9 91 90 88 87 FBBA<10> L6 A10 DQ9 K12 RFBD<96> 6 88
C12 F9 91 90 88 87 FBBA<11> M7 A11 DQ10 J13 RFBD<93> 88
E3 G6 91 90 88 87 FBBA<11> M7 A11 DQ10 J13 RFBD<99> 88
E3 G6 DQ11 J12 RFBD<92>
n
6 88
88 RFBDQS<8> B2 DQS0 E12 G7 DQ11 J12 RFBD<98> 6 88
E12 G7 DQ12 G13 RFBD<90> 6 88 VDDQ 88 RFBDQS<15> B2 DQS0
VDDQ 88 RFBDQS<11> H13 DQS1 F4 G8 DQ12 G13 RFBD<100> 6 88
F4 G8 DQ13 G12 RFBD<91> 6 88 88 RFBDQS<12> H13 DQS1
88 RFBDQS<9> H2 DQS2 F11 VSS_THERM G9 DQ13 G12 RFBD<101> 6 88
F11 VSS_THERM G9 DQ14 F13 RFBD<88> 6 88 88 RFBDQS<14> H2 DQS2
i
88 RFBDQS<10> B13 DQS3 G4 H6 DQ14 F13 RFBD<102> 6 88
G4 H6 DQ15 F12 RFBD<89> 88 88 RFBDQS<13> B13 DQS3
G11 H7 DQ15 F12 RFBD<103> 88
G11 H7 88 RFBDQM<8> B3 DM0 DQ16 F3 RFBD<78> 6 88
DQ16
C R90001 J11
J4 H8
H9
88
88
RFBDQM<11>
RFBDQM<9>
H12
H3
DM1
DM2
DQ17
DQ18
F2
G3
RFBD<79>
RFBD<76>
6 88
6 88
R90011
4.7K
J4
J11
H8
H9
88
88
RFBDQM<15>
RFBDQM<12>
B3
H12
DM0
DM1 DQ17
F3
F2
RFBD<113>
RFBD<112>
6 88
6 88
C
4.7K 1% K4 J6 88 RFBDQM<14> H3 DM2 DQ18 G3 RFBD<114> 6 88
1% K4 J6 88 RFBDQM<10> B12 DM3 DQ19 G2 RFBD<77> 88 1/16W
1/16W MF-LF K11 J7 88 RFBDQM<13> B12 DM3 DQ19 G2 RFBD<115> 88
MF-LF K11 J7 DQ20 J3 RFBD<74> 6 88 402 2
402 2 91 90 88 87 FBBA<12> N4 BA0 J8 DQ20 J3 RFBD<116> 6 88
J8 DQ21 J2 RFBD<75> 6 88 FBB1_VREF N13 VREF 91 90 88 87 FBBA<12> N4 BA0
FBB0_VREF N13 VREF 91 90 88 87 FBBA<13> M5 BA1 VOLTAGE=0.9V J9 DQ21 J2 RFBD<117> 6 88
VOLTAGE=0.9V J9 DQ22 K2 RFBD<72> 6 88 MIN_LINE_WIDTH=0.5MM 91 90 88 87 FBBA<13> M5 BA1
MIN_LINE_WIDTH=0.5MM
1 MIN_NECK_WIDTH=0.25MM DQ22 K2 RFBD<118> 6 88
1 MIN_NECK_WIDTH=0.25MM 88 87 FBBCLK0 M11 CK DQ23 K3 RFBD<73> 88
R9051 B4
R9050 B4 FBBCLK1 M11 CK DQ23 K3 RFBD<119>
4.7K 1 C9050 B11
88 87 FBBCLK0_L M12 CK DQ24 E13 RFBD<87> 6 88 4.7K
1%
1 C9051 B11
88 87
FBBCLK1_L M12 CK DQ24 E13 RFBD<104>
88
FBBCKE N12 CKE DQ25 D13 RFBD<86> 0.01UF D4
88 87 6 88
m
1% 0.01UF 91 90 88 87 6 88 1/16W 20%
1/16W D4 MF-LF 91 90 88 87 FBBCKE N12 CKE DQ25 D13 RFBD<105> 6 88
MF-LF 20%
16V 91 90 88 87 FBBCS0_L N2 CS DQ26 D12 RFBD<85> 6 88 402 2 2 16V
CERM
D5
402 2 2 CERM D5
402 91 90 88 87 FBBCS0_L N2 CS DQ26 D12 RFBD<106> 6 88
402 91 90 88 87 FBBRAS_L M2 RAS DQ27 C13 RFBD<84> 88 D6
D6 91 90 88 87 FBBRAS_L M2 RAS DQ27 C13 RFBD<107> 88
91 90 88 87 FBBCAS_L L2 CAS DQ28 B10 RFBD<83> 6 88 D9
il
D9 91 90 88 87 FBBCAS_L L2 CAS DQ28 B10 RFBD<108> 6 88
91 90 88 87 FBBWE_L L3 WE DQ29 B9 RFBD<81> 6 88 D10
D10 91 90 88 87 FBBWE_L L3 WE DQ29 B9 RFBD<110> 6 88
DQ30 C9 RFBD<82> 6 88
D11
D11 C4 DQ30 C9 RFBD<109> 6 88
DQ31 B8 RFBD<80> 88 E6 C4
E6 C11
VSSQ E9 C11
DQ31 B8 RFBD<111> 88
VSSQ E9 H4 MCL/NC M13
F5 H11
F5 H4 MCL/NC M13
RFU1/NC L9 NC F10 H11
F10 L12
NC RFU1/NC L9 NC
RFU2/NC M10 NC G5 L12
NC
G5 L13
G10 L13
RFU2/NC M10 NC
G10 M3
H5 M3
H5 M4
H10 M4
e
H10 N3
J5 N3
J5
J10
J10
K5
K5
K10
K10
B B
A
ZH9000
HOLE-VIA
1
ZH9001
HOLE-VIA
1
ZH9002
HOLE-VIA
1
ZH9003
HOLE-VIA
91 90 89 87 7 =PPV_GPU_MEM
ZH9006
HOLE-VIA
1
ZH9007
HOLE-VIA
1
ZH9008
HOLE-VIA
1
ZH9009
HOLE-VIA
1 C9010
0.1UF
20%
2 10V
CERM
402
GROUND VIAS FOR SIGNAL LAYER TRANSITIONS
1 C9011
0.1UF
20%
2 10V
CERM
402
ZH9012
HOLE-VIA
1
ZH9013
HOLE-VIA
1
ZH9014
HOLE-VIA
1
ZH9015
HOLE-VIA
1 C9012
0.1UF
20%
2 10V
CERM
402
ZH9018
1
P
HOLE-VIA
1
ZH9019
HOLE-VIA
1
ZH9020
HOLE-VIA
1
ZH9021
HOLE-VIA
C9013
0.1UF
20%
2 10V
CERM
402
1
20%
2 10V
C9014
0.1UF
CERM
402
1
r
C9015
0.1UF
20%
2 10V
CERM
402
1 C9016
0.1UF
20%
2 10V
CERM
402
1
20%
2 10V
C9017
0.1UF
CERM
402
1
20%
2 10V
C9018
CERM
402
0.1UF
1 C9019
0.1UF
20%
2 10V
CERM
402
91 90 89 87 7 =PPV_GPU_MEM
1 C9030
0.1UF
20%
2 10V
CERM
402
1 C9031
0.1UF
20%
2 10V
CERM
402
1 C9032
0.1UF
20%
2 10V
CERM
402
1 C9033
0.1UF
20%
2 10V
CERM
402
1
20%
2 10V
C9034
0.1UF
CERM
402
1 C9035
20%
2 10V
0.1UF
CERM
402
1 C9036
0.1UF
20%
2 10V
CERM
402
1 C9037
0.1UF
20%
2 10V
CERM
402
1 C9038
0.1UF
20%
2 10V
GPU GDDR SDRAM B
SYNC_MASTER=FINO-M23
CERM
402
1
20%
2 10V
C9039
0.1UF
CERM
402
SYNC_DATE=08/26/2005
A
1 1 1 1
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION NOTICE OF PROPRIETARY PROPERTY
333S0319 2 SDRAM,4MX32,GDDR,300MHZ,1.8V,SAM U9000,U9001 CRITICAL FB64MB_300MHZ_SAM SAMSUNG THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
ZH9004 ZH9010 ZH9016 ZH9022 333S0311 2 SDRAM,8MX32,GDDR,300MHZ,1.8V,SAM U9000,U9001 CRITICAL FB128MB_300MHZ_SAM
AGREES TO THE FOLLOWING
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1 1 1 1
333S0312 2 SDRAM,8MX32,GDDR,350MHZ,1.8V,SAM U9000,U9001 CRITICAL FB128MB_350MHZ_SAM II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ZH9005 ZH9011 ZH9017 ZH9023
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA 333S0320 2 SDRAM,4MX32,GDDR,300MHZ,1.8V,HYN U9000,U9001 CRITICAL FB64MB_300MHZ_HYN HYNIX SIZE DRAWING NUMBER REV.
1 1 1 1
333S0314 2 SDRAM,8MX32,GDDR,300MHZ,1.8V,HYN U9000,U9001 CRITICAL FB128MB_300MHZ_HYN
APPLE COMPUTER INC.
D 051-6863 19
333S0315 2 SDRAM,8MX32,GDDR,350MHZ,1.8V,HYN U9000,U9001 CRITICAL FB128MB_350MHZ_HYN SCALE SHT OF
NONE 90 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FRAME BUFFER A TERMINATION =PPV_GPU_MEM 7 87 89 90 91
FRAME BUFFER B TERMINATION =PPV_GPU_MEM 7 87 89 90 91
=PPV_GPU_VTT 1 C9190 1 C9191 91 =PPV_GPU_VTT 1 C9193 1 C9194
91
1UF 1UF
1UF 1UF 91 =PPV_GPU_VTT 10% 10%
=PPV_GPU_VTT 10% 10% 6.3V 6.3V
91 6.3V 6.3V 2 CERM 2 CERM
2 CERM 2 CERM NOSTUFF 56 1 8 RP9116 402 402
NOSTUFF RP9100 R9116 88 87 FBD<64>
FBD<0> 56 1 8 402 402
R9100 88 87
56 2 7 RP9100 56 88 87 FBD<65> 56 4 5 RP9116
1
56 2
88 87 FBD<1> 88 87 FBDQS<8> 1 2
56 2 7 RP9116
88 87 FBDQS<0> RP9100 88 87 FBD<66>
402
88 87 FBD<2> 56 3 6
RP9100
1 C9101 1 C9192 402
FBD<67> 56 3 6 RP9116 1 C9117 1 C9195
FBD<3> 56 4 5 88 87
1UF 1UF
R9101
88 87
56 1 8 RP9101 1UF
10%
1UF
10%
R9117 88 87 FBD<68> 56 1 8 RP9117 10%
6.3V
10%
6.3V
88 87 FBD<4> 56 RP9117 2 CERM 2 CERM
D 88 87 FBDQM<0> 1
56 2 88 87 FBD<5> 56
56
2
3
7
6
RP9101
RP9101
2 6.3V
CERM
402
2 6.3V
CERM
402
88 87 FBDQM<8> 1
402
2 88 87
88 87
FBD<69>
FBD<70>
56
56
3
2
6
7 RP9117
402 402 D
402 88 87 FBD<6> RP9117
FBD<71> 56 4 5
RP9101 88 87
y
88 87 FBD<7> 56 4 5 NOSTUFF RP9118
FBD<72> 56 2 7
NOSTUFF
R9102 88 87 FBD<8> 56 2 7 RP9102 R9118 88 87
56 1 8 RP9118
56 1 8 RP9102 56 88 87 FBD<73>
1
56 2
88 87 FBD<9> 88 87 FBDQS<9> 1 2
56 3 6 RP9118
FBDQS<1> RP9102 FBD<74>
88 87
402
88 87 FBD<10> 56 3 6
RP9102
1 C9103 402
88 87
FBD<75> 56 4 5 RP9118
1 C9119
FBD<11> 56 4 5 88 87
1UF
88 87
1UF R9119 56 2 7 RP9119 10%
r
FBD<76>
R9103 88 87 FBD<12> 56 1 8 RP9103 10% 56
88 87
1 8 RP9119
6.3V
2 CERM
56 2 7 RP9103 2 6.3V
CERM 88 87 FBDQM<9> 1 2 88 87 FBD<77> 56
402
88 87 FBDQM<1> 1 2 88 87 FBD<13> 56 RP9119
402 402 FBD<78> 56 4 5
402 FBD<14> 56 3 6 RP9103 88 87
88 87
FBD<79> 56 3 6 RP9119
FBD<15> 56 4 5 RP9103 88 87
NOSTUFF
NOSTUFF
88 87
FBD<16> 56 2 7 RP9104 R9120 88 87 FBD<80> 56 1 8 RP9120
GPU VTT VREG
R9104 88 87
56 1 8 RP9104 56 88 87 FBD<81> 56 2 7 RP9120 =PPV_GPU_MEM 7 87 89 90 91
1
56 2
88 87 FBD<17> 88 87 FBDQS<10> 1 2
56 3 6 RP9120
FBDQS<2> RP9104 FBD<82>
88 87
FBD<18> 56 3 6 402
88 87
1 C9121
a
RP9120
402
88 87
FBD<19> 56 4 5 RP9104
1 C9105 88 87 FBD<83> 56 4 5
1UF
R9105
88 87
1 8 RP9105 1UF R9121 88 87 FBD<84> 56 1 8 RP9121 10%
88 87 FBD<20> 56 10%
6.3V 56 2 7 RP9121 2 6.3V
CERM
56 RP9105 2 CERM 88 87 FBDQM<10> 1 2 88 87 FBD<85> 56 NOSTUFF
FBDQM<2> 1 2 FBD<21> 56 2 7 402
88 87 88 87
402 56 3 6 RP9121 1 NOSTUFF 1
C9186 C9181 1 C9184 1
402 88 87 FBD<22> 56 3 6 RP9105 402 88 87 FBD<86>
56 4 5 RP9121 47UF 10UF 0.1UF
R9180
56 4 5 RP9105 88 87 FBD<87> 20% 10% 20%
10K
88 87 FBD<23> NOSTUFF RP9122 5%
FBD<88> 56 2 7 2 6.3V 2 6.3V 2 16V
NOSTUFF
R9106 88 87 FBD<24> 56 1 8 RP9106 R9122 88 87
56 1 8 RP9122
X5R
1206-1
X5R
805
CERM
603
1/16W
MF-LF
56 2 7 RP9106 56 88 87 FBD<89> 2 402
FBDQS<3> 1
56 2
88 87 FBD<25> 88 87 FBDQS<11> 1 2
56 4 5 RP9122
FBD<90>
n
RP9106
88 87
402
88 87 FBD<26> 56 4 5
RP9106 1 C9107 402
88 87
FBD<91> 56 3 6 RP9122 1 C9123 U9180_REFOUT
FBD<27> 56 3 6 88 87
1UF U9180_EXT_REF
R9107
88 87
2 7 RP9107 1UF R9123 88 87 FBD<92> 56 2 7 RP9123 10%
88 87 FBD<28> 56 10% 56 RP9123 2 6.3V
56 6.3V 56 1 8 CERM
C9185 1
4
5
RP9107 2 CERM 88 87 FBDQM<11> 1 2 88 87 FBD<93>
1 8 402
i
FBDQM<3> 1 2 FBD<29> 56 RP9123
88 87 88 87
RP9107
402 402 88 87 FBD<94> 56 4 5 0.1UF
402 88 87 FBD<30> 56 4 5
RP9123 C9180 1 VDD VD 20%
16V
FBD<95> 56 3 6
56 3 6 RP9107 88 87
0.1UF U9180 CERM 2
C NOSTUFF
88 87
88 87
FBD<31>
FBD<32> 56 2 7 RP9108 NOSTUFF
R9124
88 87 FBD<96>
FBD<97>
56
56
1
2
8
7
RP9124
RP9124
20%
16V
CERM 2
NE57814
HSO8
603
C
R9108 88 87 FBD<33> 56 1 8 RP9108 56
88 87
56 3 6 RP9124
603 6 EXTREFIN REFOUT 8
56 RP9108 FBDQS<12> 1 2 FBD<98>
88 87 FBDQS<4> 1 2 88 87 FBD<34> 56 3 6
RP9108
1 C9109
88 87
402
88 87
FBD<99> 56 4 5 RP9124
1 C9125 CRITICAL
402 FBD<35> 56 4 5 88 87
RP9125
1UF
88 87
1UF FBD<100> 56 1 8 10% U9180_SBY7 STANDBY* 3
R9109 88 87 FBD<36> 56 1 8 RP9109 10%
6.3V
R9125 88 87
56 2 7 RP9125 2 6.3V
CERM
VTT VOLTAGE=0.9V
56 2 7 RP9109 2 CERM 56 88 87 FBD<101> 402 VTTSENSE
2 PPV_GPU_VTT MAKE_BASE=TRUE =PPV_GPU_VTT 91
1
56 2
88 87 FBD<37> 402 88 87 FBDQM<12> 1 2
56 3 6 RP9125 MIN_NECK_WIDTH=0.25MM
88 87 FBDQM<4> 3 6 RP9109 88 87 FBD<102> INT. 10K PULLUP MIN_LINE_WIDTH=0.5MM
88 87 FBD<38> 56 402 RP9125 THRML
402 RP9109 88 87 FBD<103> 56 4 5
88 87 FBD<39> 56 4 5 RP9126 PAD VSS 1
C9182 1 C9183
FBD<104> 56 1 8
m
RP9110 NOSTUFF 10UF
1
88 87
2 7 330UF
9
FBD<40> 56
NOSTUFF
R9110
88 87
56 1 8 RP9110
R9126 88 87 FBD<105> 56 2 7 RP9126 20% 10%
6.3V
88 87 FBD<41> 56 56 3 6 RP9126 2 2.5V-ESR9V 2 X5R
56 RP9110 FBDQS<13> 1 2 FBD<106> POLY
88 87 FBDQS<5> 1 2 88 87 FBD<42> 56 3 6
RP9110 1 C9111
88 87
402
88 87
FBD<107> 56 4 5 RP9126
1 C9127 CASE-D2E-LF 805
56 4 5 88 87
1UF
il
402 FBD<43> RP9127
88 87
1UF FBD<108> 56 1 8 10%
R9111 88 87 FBD<44> 56 1 8 RP9111 10%
6.3V
R9127 88 87
56 2 7 RP9127
6.3V
2 CERM
56 2 7 RP9111 2 CERM 56 88 87 FBD<109> 402
FBDQM<5> 1
56 2
88 87 FBD<45> 402 88 87 FBDQM<13> 1 2
56 3 6 RP9127
88 87 RP9111 88 87 FBD<110>
88 87 FBD<46> 56 4 5 402 RP9127
402 FBD<111> 56 4 5
FBD<47> 56 3 6 RP9111 88 87
88 87 NOSTUFF 56 2 7 RP9128
NOSTUFF RP9112 R9128 88 87 FBD<112>
FBD<48> 56 1 8
R9112 88 87
56 3 6 RP9112 56 88 87 FBD<113> 56 1 8 RP9128
FBDQS<6> 1
56 2
88 87 FBD<49> 88 87 FBDQS<14> 1 2
FBD<114> 56 3 6 RP9128
RP9112
88 87
402
88 87 FBD<50> 56 2 7
1 C9113
402
88 87
FBD<115> 56 4 5 RP9128
1 C9129
FBD<51> 56 4 5 RP9112 88 87
1UF
R9113
88 87
56 2 7 RP9113 1UF
10%
R9129 88 87 FBD<116> 56 2 7 RP9129 10%
6.3V
88 87 FBD<52> 6.3V 56 56 1 8 RP9129 2 CERM
56 56 1 8 RP9113 2 CERM 88 87 FBDQM<14> 1 2 88 87 FBD<117> 402
e
88 87 FBDQM<6> 1 2 88 87 FBD<53> 402 3 6 RP9129
RP9113 402 88 87 FBD<118> 56
402 FBD<54> 56 3 6
88 87
FBD<119> 56 4 5 RP9129
FBD<55> 56 4 5 RP9113 88 87
88 87 NOSTUFF 56 1 8 RP9130
FBD<120>
NOSTUFF
R9114 88 87 FBD<56> 56 1 8 RP9114 R9130 88 87
56 2 7 RP9130
56 2 7 RP9114 56 88 87 FBD<121>
56 88 87 FBD<57> 88 87 FBDQS<15> 1 2 RP9130
B FBDQS<7> 1 2 FBD<122> 56 4 5
B
r
RP9114
88 87
402
88 87 FBD<58> 56 4 5
1 C9115 402
88 87
FBD<123> 56 3 6 RP9130
1 C9131
FBD<59> 56 3 6 RP9114 88 87
1UF
R9115
88 87
56 1 8 RP9115
1UF R9131 88 87 FBD<124> 56 1 8 RP9131 10%
6.3V
88 87 FBD<60> 10%
6.3V 56 56 3 6 RP9131 2 CERM
FBDQM<7> 1
56 2 FBD<61> 56 3 6 RP9115 2 CERM 88 87 FBDQM<15> 1 2 88 87 FBD<125> 402
88 87 88 87
402 402 FBD<126> 56 2 7 RP9131
402 FBD<62> 56 2 7 RP9115 88 87
88 87
FBD<127> 56 4 5 RP9131
FBD<63> 56 4 5 RP9115 88 87
C9159 1
88 87
C9179 1
10UF
10UF 20%
20% 6.3V 2
P
6.3V
CERM 2
CERM FBBA<0> 56 1 2 R9160
FBA<0> 56 1 2 R9140 805-1 90 88 87
805-1 89 88 87
FBBA<1> 56 1 2 R9161
FBA<1> 56 1 2 R9141 90 88 87
89 88 87
R9142 FBBA<2> 56 1 2 R9162
89 88 87 FBA<2> 56 1 2
1 C9141
90 88 87
FBBA<3> 56 1 2 R9163
1 C9161
FBA<3> 56 1 2 R9143 90 88 87
1UF
89 88 87
1UF FBBA<4> 56 1 2 R9164 10%
FBA<4> 56 1 2 R9144 10% 90 88 87
2 6.3V
89 88 87
6.3V
2 CERM FBBA<5> 56 1 2 R9165 CERM
89 88 87 FBA<5> 56 1 2 R9145 402
90 88 87
R9166
402
R9146 90 88 87 FBBA<6> 56 1 2
FBA<6> 56 1 2
89 88 87
FBBA<7> 56 1 2 R9167
FBA<7> 56 1 2 R9147 90 88 87
89 88 87
FBBA<8> 56 1 2 R9168
FBA<8> 56 1 2 R9148 90 88 87
89 88 87
R9149 90 88 87 FBBA<9> 56 1 2 R9169
FBA<9> 56 1 2
89 88 87
FBBA<10> 56 1 2 R9170
FBA<10> 56 1 2 R9150 90 88 87
1 C9169
89 88 87
1 C9149 FBBA<11> 56 1 2 R9171
89 88 87 FBA<11> 56 1 2 R9151 1UF
90 88 87
R9172 1UF
10%
FBBA<12> 56 1 2
FBA<12> 56 1 2 R9152 10% 90 88 87
2 6.3V
89 88 87
6.3V
2 CERM FBBA<13> 56 1 2 R9173 CERM
89 88 87 FBA<13> 56 1 2 R9153 402
90 88 87
402
R9174
89 88 87 FBARAS_L 56 1 2 R9154
R9155
90 88 87
90 88 87
FBBRAS_L
FBBCAS_L
56
56
1
1
2
2 R9175 FB Parallel Termination
89 88 87 FBACAS_L 56 1 2
R9176
FBBWE_L 56 1 2
A 89 88 87 FBAWE_L
FBACS0_L
56
56
1
1
2
2
R9156
R9157
90 88 87
90 88 87 FBBCS0_L 56 1 2 R9177
1 C9177
SYNC_MASTER=M33-DD
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=06/20/2005
A
89 88 87
1 C9157 FBBCKE 56 1 2 R9178
89 88 87 FBACKE 56 1 2 R9158 1UF
90 88 87
1UF
10%
10% NOSTUFF 6.3V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
NOSTUFF 6.3V 2 CERM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
2 CERM 402 AGREES TO THE FOLLOWING
402
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 91 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ATI STRAPS APPLE GPIOS
=PP3V3_GPU 7 85 92 93 96 =PP3V3_GPU 7 85 92 93 96
96 93 92 85 7 =PP3V3_GPU
NOSTUFF
1 1
R9200 R9204 1 C9230
10K 10K 0.1UF
5% 5% 20%
1/16W 1/16W
MF-LF MF-LF 2 10V
CERM
2 402 2 402
D 93 GPU_GPIO<1> 93 GPU_GPIO<0>
402
D
5
R9235
y
119 92 20 PCI_RESET_L 1
1
R9201 R9256 4 LCD_PWM_R 1
47 2 LCD_PWM
10K 0 2
U9230 7
5% 93 GPU_PWM 1 2 GPU_PWM_R 5%
1/16W 1 1/16W
MF-LF
2 402
5%
1/16W
NOSTUFF 3 MC74VHC1G08
SOT23-5-LF R9232 MF-LF
402
MF-LF 1
R9230 10K
r
402 5%
10K 1/16W
5% MF-LF
1/16W 402 2
MF-LF NOSTUFF
GPIO<1> TRANSMITTER DE-EMPHASIS (ACTIVE LOW) GPIO<0> TRANSMITTER POWER SAVINGS 2 402
(FEATURE DOES NOT WORK - PULLED HIGH TO DISABLE) R9231
0
1 2
5%
1/16W
MF-LF
a
402
=PP3V3_GPU 7 85 92 93 96
RV370XT
1
R9212
5%
10K R9240
47
1/16W
MF-LF 93 GPU_DVPDATA<0> 1 2 INV_CUR_HI 7
n
2 402 5%
1/16W
93 GPU_GPIO<4> MF-LF
402
93 GPU_GPIO<5>
i
93 GPU_GPIO<6>
93 GPU_GPIO<8>
C GPIO<4> RV370: EXTRA TX OUTPUT CURRENT 1
R9207 1
R9209 1
R9211 1
RV380XT
R9213
=PP3V3_GPU
NOSTUFF
7 85 92 93 96
C
RV380 A23: LANE REVERSAL 10K 10K 10K 10K 1
GPIO<5> FORCE_COMPLIANCE
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W R9242
MF-LF MF-LF MF-LF MF-LF 10K
GPIO<6> CM_RANGE 2 402 2 402 2 402 2 402 5%
1/16W
GPIO<8> DEBUG_ACCESS MF-LF
2 402
93 GPU_DVPDATA<1> R9244
47
1 2 TMDS_EN 96
NOSTUFF
5%
m
1
R9243 1/16W
MF-LF
10K 402
5%
1/16W
MF-LF
il
93 GPU_GPIO<9> 2 402
93 GPU_GPIO<11>
93 GPU_GPIO<12>
93 GPU_GPIO<13>
1 1 1 1
R9215 R9217 R9219 R9221
10K 10K 10K 10K
5% 5% 5% 5%
ROMIDCFG 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF 96 93 92 85 7 =PP3V3_GPU
2 402 2 402 2 402 2 402 NOSTUFF
1 C9245
e
0.1UF
20%
2 10V
CERM
402
B MEMORY STRAPS NOSTUFF 5
B
r
119 92 20 PCI_RESET_L 1
=PP3V3_GPU 4 FPD_PWR_ON
7 85 92 93 96
2
U9245 96
93 GPU_DVPDATA<2>
FB64MB_300MHZ_HYN&FB128MB_300MHZ_HYN&FB128MB_350MHZ_HYN
NOSTUFF
FB128MB_300MHZ_SAM&FB128MB_300MHZ_HYN&FB128MB_350MHZ_SAM&FB128MB_350MHZ_HYN
RV380XT RV370XT 3 MC74VHC1G08
SOT23-5-LF
1
1
R9222 1
R9224 1
R9202 1
R9226 1
R9228 R9246
10K 10K 10K 10K 10K
10K
5%
5% 5% 5% 5% 5% 1/16W
1/16W 1/16W 1/16W 1/16W 1/16W MF-LF
402 2
P
MF-LF MF-LF MF-LF MF-LF MF-LF
GPU_GPIO<7>
2 402 2 402 2 402 2 402 2 402 R9245
0
93
1 2
93 GPU_GPIO<10>
5%
93 GPU_GPIO<14> 1/16W
MF-LF
93 GPU_DVPDATA<3> 402
93 GPU_DVPDATA<4>
FB64MB_300MHZ_SAM&FB128MB_300MHZ_SAM&FB128MB_350MHZ_SAM
FB64MB_300MHZ_SAM&FB64MB_300MHZ_HYN
RV370XT RV380XT
1 1 1 1 1
R9223 R9225 R9203 R9227 R9229
10K 10K 10K 10K 10K
5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402 2 402
GPIO<7> - MEMORY DIE REVISION GPU Straps
0 - ORIGINAL DIE REVISION
A 1 - NEW (FUTURE) DIE REV
GPIO<10> - MEMORY VENDOR
SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
0 - SAMSUNG
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 - HYNIX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
GPIO<14> - MEMORY DENSITY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0 - 4MX32
II NOT TO REPRODUCE OR COPY IT
1 - 8MX32
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DVPDATA<3,4> - SPEED
00 - 325E / 200M SIZE DRAWING NUMBER REV.
01 - 400E / 300M
10 - 500E / 350M APPLE COMPUTER INC.
D 051-6863 19
11 - RESERVED FOR FUTURE USE SCALE SHT OF
NONE 92 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU_SS 96 93 92 85 7 =PP3V3_GPU
L9380 SPREAD SPECTRUM SUPPORT
AC19
AC21
AC22
AD19
AD21
AC10
AD10
FERR-EMI-100-OHM S0=1;S1=M => -1.5% DOWN-SPREAD
AD7
AC8
AC9
AD9
AG7
=PP3V3_GPU 1 2
1 C9300 1 C9301 1 C9302 1 C9303
96 93 92 85 7 PP3V3_GPU_SS 4.7UF 1UF 1UF 1UF
MIN_LINE_WIDTH=0.5MM 20% 10% 10% 10%
SM GPU_SS GPU_SS 6.3V 6.3V 6.3V 6.3V
MIN_NECK_WIDTH=0.25MM 2 CERM 2 CERM 2 CERM 2 CERM
VOLTAGE=3.3V
GPU_SS 7 CRITICAL
C9380 1 1 C9381 AF5
VDDR3 VDDR4 805 402 402 402 DIFFERENTIAL IMPEDANCE SHOULD BE 100 OHM
NOSTUFF 10UF 0.1uF NC ROMCS*
GPU_SS 20% 20%
R93831
0
1
R9381
0
VDD
U9380
CY25811
6.3V 2
CERM
805-1
2 10V
CERM
402
92
92
GPU_GPIO<0>
GPU_GPIO<1>
AJ5
AH5
0
1 U8400 0
1
AH6
AJ6
GPU_DVPDATA<0>
GPU_DVPDATA<1>
92
92 96 93 TMDS_CKP
ELECTRICAL_CONSTRAINT_SET
TMDS_TCKM
NET_PHYSICAL_TYPE
GPU_TMDS
NET_SPACING_TYPE
GPU_TMDS
DIFFERENTIAL_PAIR
TMDS_CK
5%
1/16W
MF-LF
5%
1/16W
MF-LF SOI-LF
1 XIN/CLKIN
GPU_SS
R9385
TP_GPU_GPIO<2>
TP_GPU_GPIO<3>
AJ4
AK4
2
3
RV370XT 2 AK6 GPU_DVPDATA<2> 92 96 93 TMDS_CKM GPU_TMDS GPU_TMDS TMDS_CK
I572
I573
402 2 2 402 33 2 GPU_GPIO<4> AH4
BGA 3 AH7 GPU_DVPDATA<3> 92 96 93 TMDS_D0P TMDS0 GPU_TMDS GPU_TMDS TMDS_D0 I575
NC 8 XOUT SSCLK 5 GPU_SSCLK_UF 1 92 4
(5 OF 5) 4 AK7 GPU_DVPDATA<4> 92 96 93 TMDS_D0M GPU_TMDS GPU_TMDS TMDS_D0
D NC 6 FRSEL
NET_SPACING_TYPE=CLOCKS 5%
1/16W
MF-LF
92
92
GPU_GPIO<5>
GPU_GPIO<6>
AF4
AJ3
5
6 OMIT
5 AJ7 TP_GPU_DVPDATA<5>
AH8 TP_GPU_DVPDATA<6>
96 93 TMDS_D1P TMDS0 GPU_TMDS GPU_TMDS TMDS_D1
I574
I576 D
402 6 96 93 TMDS_D1M GPU_TMDS GPU_TMDS TMDS_D1
GPIO
AK3 I577
92 GPU_GPIO<7> 7
y
CY25811_S1 3 7 AJ8 TP_GPU_DVPDATA<7> TMDS_D2P TMDS0 GPU_TMDS GPU_TMDS TMDS_D2
S1 GPU_GPIO<8> AH3 8
96 93 I578
EXTERNAL TMDS
92
AH9 TP_GPU_DVPDATA<8> TMDS_D2M
CY25811_S0 4 S0 92 GPU_GPIO<9> AJ2 9
8 96 93 GPU_TMDS GPU_TMDS TMDS_D2 I579
VSS 9 AJ9 TP_GPU_DVPDATA<9> 96 93 ANALOG_GRN GPU_VGA GPU_VGA
NOSTUFF NOSTUFF 92 GPU_GPIO<10> AH2 10 I589
2 10 AK9 TP_GPU_DVPDATA<10> ANALOG_RED GPU_VGA GPU_VGA
DVPDATA
R93821 1
R9380 92 GPU_GPIO<11> AH1 11
11 AH10 TP_GPU_DVPDATA<11>
96 93
ANALOG_BLU GPU_VGA GPU_VGA
I590
0 0 AG3 96 93 I591
r
5% 5% 96 93 92 85 7 =PP3V3_GPU 92 GPU_GPIO<12> 12
12 AE6 TP_GPU_DVPDATA<12> 96 93 ANALOG_HSYNC GPU_VGA GPU_VGA I660
1/16W 1/16W 92 GPU_GPIO<13> AG1 13
MF-LF MF-LF AG6 TP_GPU_DVPDATA<13>
402 2 2 402 R93161 92 GPU_GPIO<14> AG2 14
13 96 93 ANALOG_VSYNC GPU_VGA GPU_VGA I661
1K AF3 14 AF6 TP_GPU_DVPDATA<14> 96 93 I2C_GPU_TMDS_SCL I2C I680
1% GPIO+PWRCNTL AE7 TP_GPU_DVPDATA<15>
GPU_CLK27M_OSC_SS 1/16W 15 96 93 I2C_GPU_TMDS_SDA I2C I681
MF-LF GPU_MEMSSIN AF2 GPIO_MEMSSIN
NET_SPACING_TYPE=CLOCKS 402 2 NET_SPACING_TYPE=CLOCKS 16 AF7 TP_GPU_DVPDATA<16> 96 93 I2C_GPU_MON_SCL I2C I682
GPU_VREFG AG4 VREFG 17 AE8 TP_GPU_DVPDATA<17> 96 93 I2C_GPU_MON_SDA I2C I683
27M OSC (PLACE R9371 CLOSE TO OSC)
MIN_LINE_WIDTH=0.5MM
18 AG8 TP_GPU_DVPDATA<18>
a
MIN_NECK_WIDTH=0.25MM
AJ29 =PP3V3_GPU
CLK
NC XTALOUT 7 85 92 93 96
R93171 1 C9317 GPU_CLK27M_IN AH28 XTALIN
19 AF8 TP_GPU_DVPDATA<19>
1
L9370 (PLACE R9371 AND R9372 1K 0.1UF NET_SPACING_TYPE=CLOCKS 20 AE9 TP_GPU_DVPDATA<20>
R9310
CLOSE TO OSCILLATOR PIN 8) 1%
FERR-EMI-100-OHM GPU_SS 1/16W 20% 21 AF9 TP_GPU_DVPDATA<21> 10K
MF-LF 2 10V
CERM NC AF25 PLLTEST 5%
=PP3V3_GPU AG10 TP_GPU_DVPDATA<22>
96 93 92 85 7 1 2 PP3V3_GPU_OSC 1
R9371 402 2 402 R9327 22 1/16W
MF-LF
SM MIN_LINE_WIDTH=0.5MM 0 1
1K 2 GPU_TESTEN AH27 23 AF10 TP_GPU_DVPDATA<23>
2 402
TESTEN
TEST
MIN_NECK_WIDTH=0.25MM
5%
NOSTUFF
VOLTAGE=3.3V
14
C9370 1 1 C9371 1/16W
MF-LF
5% E8 TEST_YCLK 0 AJ10 GPU_DVPCNTL
1 CRITICAL 0.1uF 4.7uF 1/16W
R9370 2 402 B6 TEST_MCLK AK10
n
20% 20% MF-LF 1
100K VCC 10V 2 6.3V
402
DVPCNTL
CERM 2 CERM OMIT 2 AJ11
5%
1/16W
MF-LF
G9370 402 805
R9372 93 9 GPU_DIODE_PLUS AF11 DPLUS 3 AH11 GPU THERMAL SENSOR
27.0000M 75 GPU_TEMP
2 402 1 2 93 9 GPU_DIODE_MINUS AE11 DMINUS R9390
i
OSC DVOMODE AE10 96 93 92 85 7 =PP3V3_GPU
ATI_GPU_OE 1 OE SM-1 8 GPU_CLK27M_OSC 1% 2.2
OUT
NET_SPACING_TYPE=CLOCKS
1/16W
MF-LF R93731 MON_DETECT_R AF12 HPD1 D9
1 2 9 PP3V3_GPU_TSENSE
MIN_LINE_WIDTH=0.5MM GPU_TEMP GPU_TEMP
49.9
C GND
402
1%
1/16W
AG15
AG16
D13
D19
5%
1/16W
MF-LF
402
MIN_NECK_WIDTH=0.25MM
VOLTAGE=3.3V
GPU_TEMP R93911
1K
1
R9393
1K
C
MF-LF CRITICAL
7 402 2 AG17 D25
1 C9390 GPU_TEMP
5%
1/16W
5%
1/16W
1UF MF-LF MF-LF NOSTUFF
PLACE R9373 CLOSE TO ATI PIN AH28 AG18 E4 10% 2 402 2
6.3V
2 CERM VCC 2 402 R9395
AG20 T4 0
402
TABLE_5_HEAD
AH15 AB4
15 STBY ALERT 11 9 TSENSE_GPU_OVERTEMP_L 1 2 SYS_OVERTEMP_L 20 24 28
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION 96 93 92 85 7 =PP3V3_GPU U9390 5%
TABLE_5_ITEM
AH16 AE12 MAX6690MEE 1/16W
1
114S0112 1 RES,80.6 OHM,1/16W,1%,0402 R9372 RV370XT R9318 AH17 AE15 39 I2C_GPU_DIODE_SDA 12 SMBDATA ADD0
9 10 TSENSE_GPU_ADD0 MF-LF
402
TABLE_5_ITEM
10K AH18 NC NC AE16 39 I2C_GPU_DIODE_SCL 14 SMBCLK ADD1 6
9 TSENSE_GPU_ADD1
m
114S0109 1 RES,75 OHM,1/16W,1%,0402 R9372 RV380XT 5%
1/16W
MF-LF AH19 NO CONNECTS AE17 QSOP
NC_1 1
GPU_DIODE_PLUS 3 (SYM_VER2)
NOSTUFF
402 2 AH24 AE18 93 9 DXP 1NOSTUFF
R9319 MIN_LINE_WIDTH=0.25mm
MIN_NECK_WIDTH=0.2MM 4 DXN
NC_5 5 R93921 R9394 A0 | A1 | ADDR
----+----+------
0 AJ16 AE19 NC_9 9 1K 1K 0 | 0 | 30/31
il
96 MON_DETECT 1 2 5% 5% 0 | hiZ| 32/33
AJ17 AF15 GPU_TEMP NC_13 13 1/16W 1/16W 0 | 1 | 34/35
5% MF-LF MF-LF
L9335 1/16W
MF-LF
AJ18 AF16 C9392 1 NC_16 16 402 2 2 402
hiZ | 0 | 52/53
hiZ | hiZ| 54/55
87 86 85 84 =PP1V8_GPU FERR-220-OHM 402 AJ19 AF17 0.0022UF hiZ | 1 | 56/57
1 | 0 | 98/99
10% GND 1 | hiZ| 9A/9B
1 2 PP1V8_GPU_TXVDDR AJ20 AF18 50V *
VOLTAGE=1.8V CERM 2 7 8 1 | 1 | 9C/9D
0805 AJ21 AF19 402
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM 1 C9335 1 C9336 1 C9337 AJ23 AF20 93 9 GPU_DIODE_MINUS
MIN_LINE_WIDTH=0.25mm
4.7UF 0.1UF 0.1UF MIN_NECK_WIDTH=0.2MM
XW9335
SM
20%
2 6.3V
20%
2 10V
20%
2 10V
AK18 AG12 GPU_PWM 92
CERM CERM CERM
805 402 402 AF13 AK12
1 2 6 GND_GPU_TXVSSR TXCP TMDS_CKP 93 96 PLACE C9392 CLOSE TO TEMP SENSOR
VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM AF14 TXVDDR TXCM* AJ12 TMDS_CKM 93 96
MIN_NECK_WIDTH=0.25MM
e
NOSTUFF TX0P AJ13 TMDS_D0P 93 96
AG13
L9330 PP1V8_GPU_TPVDD 85
AG14 TX0M* AK13 TMDS_D0M 93 96
1.8UH VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM TXVSSR TX1P AJ15 TMDS_D1P 93 96
AH14
1 2 MIN_NECK_WIDTH=0.25MM TMDS TX1M* AJ14 TMDS_D1M 93 96
0805 TX2P AK16 TMDS_D2P
B 1 C9330 1 C9331 1 C9332 1 C9333 93 96
r
TX2M* AK15 TMDS_D2M
4.7UF 0.1UF 0.1UF 0.1UF 93 96
XW9330
SM
20%
2 6.3V
20%
2 10V
20%
2 10V
20%
2 10V
AH13 TPVDD
DDC3CLK AG22 I2C_GPU_TMDS_SCL 93 96
CERM CERM CERM CERM
805 402 402 402 AH12 AG23
1 2 6 GND_GPU_TPVSS TPVSS DDC3DATA I2C_GPU_TMDS_SDA 93 96
VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
L9340 AE23 VDD1DI R AK27 NC
GPU_DAC1_VSYNC
FERR-220-OHM AE22 VDD2DI G AJ27 NC
DEVELOPMENT GPU_RSET
1 2 PP1V8_GPU_VDDDI B AJ26 NC MIN_LINE_WIDTH=0.5MM
AE24
0805 VOLTAGE=1.8V VSS1DI HSYNC AJ25 TP_GPU_HSYNC R93261 GPU_STEREOSYNC MIN_NECK_WIDTH=0.25MM
P
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
1 C9340 1 C9341 1 C9342 AE21 VSS2DI AK25
75
4.7UF 0.1UF 0.1UF DAC1 VSYNC 1%
1/16W R93251 1
R9320
XW9340
SM
20%
6.3V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM RSET AH26 MF-LF
402 2 10K 499
805 402 402 5% 1%
1 2 6 GND_GPU_VSSDI 1/16W 1/16W
VOLTAGE=0V AH23 AVDD DDC1CLK AF24 TP_GPU_DDC1CLK MF-LF MF-LF
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM DDC1DATA AG25 TP_GPU_DDC1DATA
402 2 XW9347
SM 2 402
L9345 GND_GPU_AVSSQ AD22 1 2 GND_GPU_AVSSQ
FERR-220-OHM 93 6 AVSSQ AG24 6 93
VOLTAGE=0V GPIO_AUXWIN NC
1 2 MIN_LINE_WIDTH=0.5MM
PP1V8_GPU_AVDD MIN_NECK_WIDTH=0.25MM AH22 AVSSN STEREOSYNC AH25
VOLTAGE=1.8V
0805 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM 1 C9345 1 C9346 AE20 Y_G AK21 ANALOG_GRN
4.7UF 0.1UF 93 96
XW9345
SM
20%
2 6.3V
20%
2 10V
AF21 A2VDD C_R AJ22 ANALOG_RED 93 96
CERM CERM AK22
1 2 6 GND_GPU_AVSSN 805 402 AG21 COMP_B ANALOG_BLU 93 96
VOLTAGE=0V H2SYNC AJ24 ANALOG_HSYNC 93 96
MIN_LINE_WIDTH=0.5MM AH20 A2VSSN
MIN_NECK_WIDTH=0.25MM DAC2 V2SYNC AK24 ANALOG_VSYNC 93 96
1
R9321 1R9322 1R9323
85 PP2V5_GPU_A2VDD R2SET AH21 100 100 100
AF23 A2VDDQ
DDC2CLK AE13 I2C_GPU_MON_SCL 93 96
1%
1/16W
MF-LF
1%
1/16W
MF-LF
1%
1/16W
MF-LF
GPU DVI & DACs
1 C9355 1 C9356 1 C9357 AF22 DDC2DATA AE14 I2C_GPU_MON_SDA 2 402 2 402 2 402
A2VSSQ
A XW9355 VOLTAGE=0V 20%
4.7UF 0.1UF
20% 20%
0.1UF
93 96 SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
6.3V 10V 10V
SM MIN_LINE_WIDTH=0.5MM 2 CERM 2 CERM 2 CERM
MIN_NECK_WIDTH=0.25MM 805 402 402
1 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PLACE R9321-3 & FL9600-2 NEAR MINI-VGA CONNECTOR PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
GND_GPU_A2VSSN 6 AGREES TO THE FOLLOWING
GPU_R2SET ROUTE GND IN BETWEEN RGB SIGNALS WITH A VIA EVERY INCH
L9365 MIN_LINE_WIDTH=0.5MM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
FERR-220-OHM MIN_NECK_WIDTH=0.25MM
II NOT TO REPRODUCE OR COPY IT
1 2 PP1V8_GPU_A2VDDQ III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1
0805
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM R9324
MIN_NECK_WIDTH=0.25MM 1 C9365 1 C9366 1%
715 SIZE DRAWING NUMBER REV.
4.7UF 0.1UF
XW9365
SM
20%
6.3V
2 CERM
20%
10V
2 CERM
1/16W
MF-LF
2 402 APPLE COMPUTER INC.
D 051-6863 19
1 2 GND_GPU_A2VSSQ 805 402
6 SCALE SHT OF
VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
NONE 93 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
INTERNAL LCD EXTERNAL VGA CONNECTOR
NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR
NET_PHYSICAL_TYPE NET_SPACING_TYPE
TCKP
96 GPU_TMDS GPU_TMDS TCK I885
96 93 92 85 7 =PP3V3_GPU R9682 PP3V3_DDC 96 96 FILT_ANALOG_GRN GPU_VGA GPU_VGA I955
96 TCKM GPU_TMDS GPU_TMDS TCK I887 0
1 2 96 ANALOG_GRN_LC GPU_VGA GPU_VGA I1035
96 TD0P GPU_TMDS GPU_TMDS TD0 I886 5% 96 ANALOG_GRN_LCL GPU_VGA GPU_VGA I1036
1 1
96 TD0M GPU_TMDS GPU_TMDS TD0 I888 R9605 R9607 1/8W
MF-LF 1 C9601
0.01UF 96 FILT_ANALOG_RED GPU_VGA GPU_VGA I956
96 TD1P GPU_TMDS GPU_TMDS TD1 I889 2.0K 2.0K 805
5% 5% 10%
96 ANALOG_RED_LC GPU_VGA GPU_VGA
D 96
96
TD1M
TD2P
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
TD1
TD2
I890
I892
1/16W
MF-LF
402 2
1/16W
MF-LF
2 402
2 16V
CERM
402 96 ANALOG_RED_LCL GPU_VGA GPU_VGA
I1037
I1038 D
96 FILT_ANALOG_BLU GPU_VGA GPU_VGA I957
96 TD2M GPU_TMDS GPU_TMDS TD2
y
I891 R9608 96 ANALOG_BLU_LC GPU_VGA GPU_VGA 96 93 92 85 7 =PP3V3_GPU
I1039
33
93 I2C_GPU_TMDS_SCL 1 2 I2C_TMDS_SCL 96 96 ANALOG_BLU_LCL GPU_VGA GPU_VGA I1040
5% 96 VGA_VSYNC GPU_VGA GPU_VGA
PLACE R9600-R9604, C9600 PLACE FILTER CLOSE
R9606
33
1/16W
MF-LF VGA_VSYNC_R GPU_VGA GPU_VGA
I958 1 C9670
93 I2C_GPU_TMDS_SDA 1 2 402 I2C_TMDS_SDA 96
96 I959
CRITICAL 0.1UF
AS CLOSE TO GPU AS POSSIBLE TO TMDS CONNECTOR VGA_HSYNC GPU_VGA GPU_VGA 20%
96 I961
U9670 10V
r
5% 2 CERM
1/16W VGA_HSYNC_R GPU_VGA GPU_VGA R9671
14 74LC125
96 I960 402
NOSTUFF MF-LF
R9626 402
2 3
33
TMDS_D2M 1
02 93 ANALOG_VSYNC VGA_VSYNC 96 1 2 VGA_VSYNC_R 96
93
125 5%
7 1 TSSOP 1/16W
MF-LF
L9602 SYM_VER-1 402
R96041 90-OHM 1 4 TD2M 96
143 PP5V_USB2 R9680 PP5V_VGA
VOLTAGE=5V
96
130 SM
1
0 2
MIN_LINE_WIDTH=0.6MM
a
1% MIN_NECK_WIDTH=0.25MM
1/16W
MF-LF
402 2 2 3 TD2P 96
INTERNAL TMDS CONNECTOR 5%
1/8W 1 C9602 U9670
NOSTUFF
R9627 SDF9600
MF-LF
805 0.01UF 14 74LC125 R9672
02 10% 33
93 TMDS_D2P 1 STDOFF-3MMOD4.6MMH-1.35-TH 2 16V
CERM 93 ANALOG_HSYNC 5 6 VGA_HSYNC 96 1 2 VGA_HSYNC_R 96
402 125 5%
1 NOSTUFF NOSTUFF
7 4 TSSOP 1/16W
NOSTUFF
(516S0241) GND_CHASSIS_VGA
MF-LF
402
C9607 1 1 C9608
R9628 02
CRITICAL 7 96
22PF 22PF
93 TMDS_D1M 1 J9602 5% 5%
50V 50V
n
53307-3072 CERM 2 2 CERM
L9608 F-ST-SM 402 402
SYM_VER-1
90-OHM GND_CHASSIS_VGA 7 96
R96031 4 1 SM
TD1M 96
1 2 PPVCC_TMDS 96
130 3 4
i
1% 6
1/16W 5
MF-LF 3 2 96 93 92 85 7 =PP3V3_GPU
402 2 TD1P 96 7 8 PP3V3_DDC 96 96 PP5V_VGA
C 93 TMDS_D1P
NOSTUFF
R9629
1
0
2
96
96
TD0M
TD0P
9
11
10
12
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
C
NOSTUFF
R9630 13 14 TCKM 96
R96731 1
R9674 R96771 1
R9678
TMDS_D0M 1
02 16
10K 10K 4.7K 4.7K
93 96 TD2M 15 TCKP 96 5% 5% 2 5% 5%
TD2P 17 18
1/16W
MF-LF
1/16W
MF-LF
Q9675 1/16W
MF-LF
1/16W
MF-LF
96
G 2N7002DW-X-F
L9609 SYM_VER-1 19 20 TD1M 96
402 2 2 402 SOT-363 R9675 402 2 2 402
R96021 90-OHM 1 4 TD0M 96 21 22 TD1P 96 93 I2C_GPU_MON_SCL 1 S D 6 I2C_MON_SCL 1
100 2 I2C_MON_SCL_R 96
130 SM
1% 96 I2C_TMDS_SDA 23 24 I2C_TMDS_SCL 96 5%
1/16W 1/16W
25 26
m
MF-LF MF-LF
402 2 2 3 TD0P 5 402
NOSTUFF
0
96
27 28
Q9675
R9631 29 30 1 C9616 1 C9615 G 2N7002DW-X-F
R9676
93 TMDS_D0P 1 2 SOT-363
NOSTUFF 10UF 0.01UF 100
il
10% 10% I2C_GPU_MON_SDA 4 S D 3 I2C_MON_SDA 1 2 I2C_MON_SDA_R 96
R9632 02 2 16V
CERM 2 16V
CERM
93
93 TMDS_CKM 1 5%
GND_CHASSIS_TMDS 1210 402 1/16W
7
MF-LF
R96011 SDF9601
402 C9677 1 1 C9678
165 INDUCTORS SHOULD BE 47 NH 47PF 47PF
1% L9610 STDOFF-3MMOD4.6MMH-1.35-TH 5% 5%
50V 50V
1/16W 90-OHM
SYM_VER-1
ANY ~8PF CAP SHOULD DO CERM 2 2 CERM
MF-LF 1
402 2
SM 1 4 TCKM 96
402 402
TMDS_CK_TERM NOSTUFF GND_CHASSIS_VGA 7 96
MIN_LINE_WIDTH=0.3MM FL9600
MIN_NECK_WIDTH=0.2MM
C9600 1
1
2 3 TCKP 96 L9640 L9641 LCFILTER
22PF R9600 47NH-0.20-OHM 47NH-0.20-OHM SM-220MHZ-LF
5%
50V 165 ANALOG_RED 1 2 1 2 1 2
e
CERM 2 1% 93 ANALOG_RED_LC
96
402 1/16W 0805 0805
MF-LF
402 2 NOSTUFF
0
1 C9640 3 4
R9633 8.2PF
+/-0.25PF
93 TMDS_CKP 1 2
2 50V
CERM R9640
B 402 0 M33: 514S0097
B
r
ANALOG_RED_LCL 96 1 2
U9670 1
402
14 74LC125
R9643 CRITICAL
PANEL POWER SEQUENCING FPD_PWR_ON 9 8 LED5900_PWR
301 J9603
96 92 1%
1/16W
DV01793-M33-4F
125 1
7 10 TSSOP R9612 MF-LF
402 2
F-ST-SM
15
NOSTUFF =PP12V_GPU 7 96 820 7 GND_CHASSIS_RIGHT
96 7 =PP12V_GPU Q9600 5%
1/10W
IRF7416BF 1 MF-LF NOSTUFF 1
SOI R9634 2 603 FL9601 2 VGA_VSYNC_R 96
P
8
0 LED5900_P1 L9642 L9643 LCFILTER 96 VGA_HSYNC_R 3
4 (RED_RTN)
3 S3 D4 5%
1/4W
47NH-0.20-OHM 47NH-0.20-OHM SM-220MHZ-LF
FILT_ANALOG_RED 96 5
7 1 6 (GRN_RTN)
2 S2 D3 MF-LF
ANALOG_GRN 1 2 1 2 1 2 7
6 2 1206 LED9600 93 ANALOG_GRN_LC
96 FILT_ANALOG_GRN 96 8 PP5V_VGA
1 D2 GREEN-3.6MCD 0805 0805 FILT_ANALOG_BLU 96 9 96
S1
NOSTUFF
D1 5 2.0X1.25MM-SM 1 C9643 3 4
I2C_MON_SCL_R 11
10 I2C_MON_SDA_R 96
NOSTUFF GATE 2
8.2PF 96
12(BLU_RTN)
1 +/-0.25PF 13
C9619 1 R9625 4 376S0385
50V
2 CERM R9641
93 MON_DETECT 14
0.01UF 100K SILKSCREEN: 3 402 C9605 1 C9604 1 C9603 1
20% 5% 0 0.01UF 0.01UF 0.01UF
16V 1/16W ANALOG_GRN_LCL 96 1 2
16 10% 10% 10%
CERM 2 MF-LF NOSTUFF
402 16V 16V 16V
402 2 402 2 2 2
C9618 PPVCC_TMDS 96
R96441 CERM
402
CERM
402
CERM
402
0.022UF VOLTAGE=12V 301
1 2 MIN_LINE_WIDTH=0.6MM 1%
FPD_PWR_SW_G MIN_NECK_WIDTH=0.25MM 96 7 =PP12V_GPU 1/16W
NOSTUFF NOSTUFF MF-LF
1 402 2 96 7 GND_CHASSIS_VGA
20% 1 1
R9613 16V D9614 C9617 1 R9660 1
R9690 1
R9691
100K CERM
402 MMBD914XXG 10UF 10K NOSTUFF
5% 10% 5% 300 300 FL9602
1/16W SOT23 1/16W 5% 5%
MF-LF 3
16V
CERM 2 MF-LF 1/8W 1/8W L9644 L9645 LCFILTER
2 402
FPD_PWR_ON_D
1210 2 402 MF-LF
2 805
MF-LF
2 805
47NH-0.20-OHM 47NH-0.20-OHM
1
SM-220MHZ-LF
2
TMDS / ExtVGA
Q9690_D 93 ANALOG_BLU 1 2 ANALOG_BLU_LC
96 1 2
TMDS_EN_R
A 3 NOSTUFF
3
0805
1 C9644
0805
3 4
SYNC_MASTER=M33-DD SYNC_DATE=06/20/2005
A
D
Q9601 1
R9614 D Q9690 8.2PF NOTICE OF PROPRIETARY PROPERTY
2N7002 +/-0.25PF
1 SOT23-LF 10K 2N7002 2 50V
CERM R9642 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
96 92 FPD_PWR_ON G S 5% SOT23-LF PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
SYS_POWERUP_L_BUF 1 G S 402 0
1/16W 16 7 AGREES TO THE FOLLOWING
MF-LF ANALOG_BLU_LCL 96 1 2
2 2 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
FOR PANEL VCC FALL TIME SPEC 2 402
TMDS_EN 92
1 II NOT TO REPRODUCE OR COPY IT
3 DZ9600 R9645 PLACE R9321-3 & FL9600-2 CLOSE TO J9603 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
301
MMBZ5227B 1%
1/16W SIZE DRAWING NUMBER REV.
SOT23 MF-LF
1 402 2
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 96 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KODIAK PCI-E PHYSICAL CONSTRAINT TABLE
SIG_NAME ELECTRICAL_CONSTRAINT_SET DIFFERENTIAL_PAIR NET_PHYSICAL_TYPE NET_SPACING_TYPE
SIG_NAME ELECTRICAL_CONSTRAINT_SET DIFFERENTIAL_PAIR NET_PHYSICAL_TYPE NET_SPACING_TYPE
84 26 CLK_PCIE_SLOTA_N<0> KODPCIE_CLK PCIE_CLK PCIE_CLK
9 100M_N<0> CLK_100M PCIE_CLK PCIE_CLK
82 84 26 CLK_PCIE_SLOTA_P<0> KODPCIE_CLK PCIE_CLK PCIE_CLK
9 100M_P<0> CLK_100M PCIE_CLK PCIE_CLK
82 84 CLK_PCIE_SLOTA_NF<0>
KODPCIE_CLKF PCIE_CLK PCIE_CLK
82 26 CLK_KOD_100M_N<0> CLK_KODPCIE_100M PCIE_CLK PCIE_CLK
84 CLK_PCIE_SLOTA_PF<0>
KODPCIE_CLKF PCIE_CLK PCIE_CLK
82 26 CLK_KOD_100M_P<0> CLK_KODPCIE_100M PCIE_CLK PCIE_CLK
9 CKA_P<0>
CLK_SLOTA_CKA PCIE_CLK PCIE_CLK
9 CLK_KOD_100M_NF<0> CLK_KODPCIE_100MF PCIE_CLK PCIE_CLK 84
82 9 CKA_N<0>
CLK_SLOTA_CKA PCIE_CLK PCIE_CLK
D 9
82
CLK_KOD_100M_PF<0> CLK_KODPCIE_100MF PCIE_CLK PCIE_CLK 84
PCIE_SLOTA_TO_NB_0_F PCIE_DATA PCIE_DATA
D
PCIE_NB_TO_SLOTA_0_F PCIE_DATA PCIE_DATA 9 PCIE_SLOTA_TO_NB_NF<0> PCIE_SA2NB0 I312
9 PCIE_NB_TO_SLOTA_NF<0> PCIE_NB2SA0 84
y
82 9 PCIE_SLOTA_TO_NB_PF<0> PCIE_SA2NB0 PCIE_SLOTA_TO_NB_0_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<0> PCIE_NB2SA0 PCIE_NB_TO_SLOTA_0_F PCIE_DATA PCIE_DATA 84 I313
82 9 PCIE_SLOTA_TO_NB_NF<1> PCIE_SA2NB1 PCIE_SLOTA_TO_NB_1_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<1> PCIE_NB2SA1 PCIE_NB_TO_SLOTA_1_F PCIE_DATA PCIE_DATA 84 I311
82 9 PCIE_SLOTA_TO_NB_PF<1> PCIE_SA2NB1 PCIE_SLOTA_TO_NB_1_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<1> PCIE_NB2SA1 PCIE_NB_TO_SLOTA_1_F PCIE_DATA PCIE_DATA 84 I316
82 9 PCIE_SLOTA_TO_NB_NF<2> PCIE_SA2NB2 PCIE_SLOTA_TO_NB_2_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<2> PCIE_NB2SA2 PCIE_NB_TO_SLOTA_2_F PCIE_DATA PCIE_DATA 84 I317
82 9 PCIE_SLOTA_TO_NB_PF<2> PCIE_SA2NB2 PCIE_SLOTA_TO_NB_2_F PCIE_DATA PCIE_DATA
PCIE_NB_TO_SLOTA_2_F PCIE_DATA PCIE_DATA I314
r
9 PCIE_NB_TO_SLOTA_PF<2> PCIE_NB2SA2 84
82 9 PCIE_SLOTA_TO_NB_NF<3> PCIE_SA2NB3 PCIE_SLOTA_TO_NB_3_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<3> PCIE_NB2SA3 PCIE_NB_TO_SLOTA_3_F PCIE_DATA PCIE_DATA 84 I315
82 9 PCIE_SLOTA_TO_NB_PF<3> PCIE_SA2NB3 PCIE_SLOTA_TO_NB_3_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<3> PCIE_NB2SA3 PCIE_NB_TO_SLOTA_3_F PCIE_DATA PCIE_DATA 84 I318
82 9 PCIE_SLOTA_TO_NB_NF<4> PCIE_SA2NB4 PCIE_SLOTA_TO_NB_4_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<4> PCIE_NB2SA4 PCIE_NB_TO_SLOTA_4_F PCIE_DATA PCIE_DATA 84 I319
82 9 PCIE_SLOTA_TO_NB_PF<4> PCIE_SA2NB4 PCIE_SLOTA_TO_NB_4_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<4> PCIE_NB2SA4 PCIE_NB_TO_SLOTA_4_F PCIE_DATA PCIE_DATA 84 I320
82 9 PCIE_SLOTA_TO_NB_NF<5> PCIE_SA2NB5 PCIE_SLOTA_TO_NB_5_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<5> PCIE_NB2SA5 PCIE_NB_TO_SLOTA_5_F PCIE_DATA PCIE_DATA 84 I321
82 9 PCIE_SLOTA_TO_NB_PF<5> PCIE_SA2NB5 PCIE_SLOTA_TO_NB_5_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<5> PCIE_NB2SA5 PCIE_NB_TO_SLOTA_5_F PCIE_DATA PCIE_DATA 84 I322
82 9 PCIE_SLOTA_TO_NB_NF<6> PCIE_SA2NB6 PCIE_SLOTA_TO_NB_6_F PCIE_DATA PCIE_DATA
a
9 PCIE_NB_TO_SLOTA_NF<6> PCIE_NB2SA6 PCIE_NB_TO_SLOTA_6_F PCIE_DATA PCIE_DATA 84
I323
82 9 PCIE_SLOTA_TO_NB_PF<6> PCIE_SA2NB6 PCIE_SLOTA_TO_NB_6_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<6> PCIE_NB2SA6 PCIE_NB_TO_SLOTA_6_F PCIE_DATA PCIE_DATA 84 I328
82 9 PCIE_SLOTA_TO_NB_NF<7> PCIE_SA2NB7 PCIE_SLOTA_TO_NB_7_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<7> PCIE_NB2SA7 PCIE_NB_TO_SLOTA_7_F PCIE_DATA PCIE_DATA 84
I327
82 9 PCIE_SLOTA_TO_NB_PF<7> PCIE_SA2NB7 PCIE_SLOTA_TO_NB_7_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<7> PCIE_NB2SA7 PCIE_NB_TO_SLOTA_7_F PCIE_DATA PCIE_DATA 84 I326
82 9 PCIE_SLOTA_TO_NB_NF<8> PCIE_SA2NB8 PCIE_SLOTA_TO_NB_8_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<8> PCIE_NB2SA8 PCIE_NB_TO_SLOTA_8_F PCIE_DATA PCIE_DATA 84
I325
82 9 PCIE_SLOTA_TO_NB_PF<8> PCIE_SA2NB8 PCIE_SLOTA_TO_NB_8_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<8> PCIE_NB2SA8 PCIE_NB_TO_SLOTA_8_F PCIE_DATA PCIE_DATA 84 I324
82 9 PCIE_SLOTA_TO_NB_NF<9> PCIE_SA2NB9 PCIE_SLOTA_TO_NB_9_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<9> PCIE_NB2SA9 PCIE_NB_TO_SLOTA_9_F PCIE_DATA PCIE_DATA 84 I332
82 9 PCIE_SLOTA_TO_NB_PF<9> PCIE_SA2NB9 PCIE_SLOTA_TO_NB_9_F PCIE_DATA PCIE_DATA
PCIE_NB_TO_SLOTA_PF<9> PCIE_NB_TO_SLOTA_9_F PCIE_DATA PCIE_DATA I333
n
9 PCIE_NB2SA9 84
PCIE_SLOTA_TO_NB_10_F PCIE_DATA PCIE_DATA
82 9 PCIE_SLOTA_TO_NB_NF<10> PCIE_SA2NB10
9 PCIE_NB_TO_SLOTA_NF<10> PCIE_NB2SA10 PCIE_NB_TO_SLOTA_10_F PCIE_DATA PCIE_DATA 84
I329
82 9 PCIE_SLOTA_TO_NB_PF<10> PCIE_SA2NB10 PCIE_SLOTA_TO_NB_10_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<10> PCIE_NB2SA10 PCIE_NB_TO_SLOTA_10_F PCIE_DATA PCIE_DATA 84 I330
82 9 PCIE_SLOTA_TO_NB_NF<11> PCIE_SA2NB11 PCIE_SLOTA_TO_NB_11_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<11> PCIE_NB2SA11 PCIE_NB_TO_SLOTA_11_F PCIE_DATA PCIE_DATA 84 I331
PCIE_SLOTA_TO_NB_11_F PCIE_DATA PCIE_DATA
i
82 9 PCIE_SLOTA_TO_NB_PF<11> PCIE_SA2NB11
9 PCIE_NB_TO_SLOTA_PF<11> PCIE_NB2SA11 PCIE_NB_TO_SLOTA_11_F PCIE_DATA PCIE_DATA 84 I337
82 9 PCIE_SLOTA_TO_NB_NF<12> PCIE_SA2NB12 PCIE_SLOTA_TO_NB_12_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<12> PCIE_NB2SA12 PCIE_NB_TO_SLOTA_12_F PCIE_DATA PCIE_DATA 84 I338
PCIE_SLOTA_TO_NB_12_F PCIE_DATA PCIE_DATA
C 82
9
82
9
PCIE_NB_TO_SLOTA_PF<12>
PCIE_NB_TO_SLOTA_NF<13>
PCIE_NB2SA12
PCIE_NB2SA13
PCIE_NB_TO_SLOTA_12_F
PCIE_NB_TO_SLOTA_13_F
PCIE_DATA
PCIE_DATA
PCIE_DATA
PCIE_DATA
9 PCIE_SLOTA_TO_NB_PF<12>
84
9 PCIE_SLOTA_TO_NB_NF<13>
84
PCIE_SA2NB12
PCIE_SA2NB13 PCIE_SLOTA_TO_NB_13_F PCIE_DATA PCIE_DATA
I334
I335
C
82 9 PCIE_SLOTA_TO_NB_PF<13> PCIE_SA2NB13 PCIE_SLOTA_TO_NB_13_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<13> PCIE_NB2SA13 PCIE_NB_TO_SLOTA_13_F PCIE_DATA PCIE_DATA 84 I336
82 9 PCIE_SLOTA_TO_NB_NF<14> PCIE_SA2NB14 PCIE_SLOTA_TO_NB_14_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<14> PCIE_NB2SA14 PCIE_NB_TO_SLOTA_14_F PCIE_DATA PCIE_DATA 84 I342
82 9 PCIE_SLOTA_TO_NB_PF<14> PCIE_SA2NB14 PCIE_SLOTA_TO_NB_14_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<14> PCIE_NB2SA14 PCIE_NB_TO_SLOTA_14_F PCIE_DATA PCIE_DATA 84 I341
82 9 PCIE_SLOTA_TO_NB_NF<15> PCIE_SA2NB15 PCIE_SLOTA_TO_NB_15_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_NF<15> PCIE_NB2SA15 PCIE_NB_TO_SLOTA_15_F PCIE_DATA PCIE_DATA 84 I340
82 9 PCIE_SLOTA_TO_NB_PF<15> PCIE_SA2NB15 PCIE_SLOTA_TO_NB_15_F PCIE_DATA PCIE_DATA
9 PCIE_NB_TO_SLOTA_PF<15> PCIE_NB2SA15 PCIE_NB_TO_SLOTA_15_F PCIE_DATA PCIE_DATA 84 I339
82
84
82
PCIE_NB_TO_SLOTA_N<0> PCIE_NB_TO_SLOTA_0 PCIE_DATA PCIE_DATA 84
PCIE_SLOTA_TO_NB_N<0> PCIE_SLOTA_TO_NB_0 PCIE_DATA PCIE_DATA
m
9 9
82
84
9 PCIE_NB_TO_SLOTA_P<0> PCIE_NB_TO_SLOTA_0 PCIE_DATA PCIE_DATA 84
82
9 PCIE_SLOTA_TO_NB_P<0> PCIE_SLOTA_TO_NB_0 PCIE_DATA PCIE_DATA
82
9 PCIE_NB_TO_SLOTA_N<1> PCIE_NB_TO_SLOTA_1 PCIE_DATA PCIE_DATA 84
9 PCIE_SLOTA_TO_NB_N<1> PCIE_SLOTA_TO_NB_1 PCIE_DATA PCIE_DATA
82 82
84 82 9
84 PCIE_NB_TO_SLOTA_P<1> PCIE_NB_TO_SLOTA_1 PCIE_DATA PCIE_DATA 9 PCIE_SLOTA_TO_NB_P<1>
PCIE_SLOTA_TO_NB_1 PCIE_DATA PCIE_DATA
il
82
84
82
9 PCIE_NB_TO_SLOTA_N<2> PCIE_NB_TO_SLOTA_2 PCIE_DATA PCIE_DATA 84 82 9
84 PCIE_SLOTA_TO_NB_N<2> PCIE_SLOTA_TO_NB_2 PCIE_DATA PCIE_DATA
84
9 PCIE_NB_TO_SLOTA_P<2> PCIE_NB_TO_SLOTA_2 PCIE_DATA PCIE_DATA 84
9 PCIE_SLOTA_TO_NB_P<2>
PCIE_SLOTA_TO_NB_2 PCIE_DATA PCIE_DATA
82 82
84
82
9 PCIE_NB_TO_SLOTA_N<3> PCIE_NB_TO_SLOTA_3 PCIE_DATA PCIE_DATA 9 PCIE_SLOTA_TO_NB_N<3>
PCIE_SLOTA_TO_NB_3 PCIE_DATA PCIE_DATA
82
84
9 PCIE_NB_TO_SLOTA_P<3> PCIE_NB_TO_SLOTA_3 PCIE_DATA PCIE_DATA 84 82 9
84 PCIE_SLOTA_TO_NB_P<3> PCIE_SLOTA_TO_NB_3 PCIE_DATA PCIE_DATA
82
84
82
9 PCIE_NB_TO_SLOTA_N<4> PCIE_NB_TO_SLOTA_4 PCIE_DATA PCIE_DATA 84
9 PCIE_SLOTA_TO_NB_N<4>
PCIE_SLOTA_TO_NB_4 PCIE_DATA PCIE_DATA
82
84
9 PCIE_NB_TO_SLOTA_P<4> PCIE_NB_TO_SLOTA_4 PCIE_DATA PCIE_DATA 9 PCIE_SLOTA_TO_NB_P<4>
PCIE_SLOTA_TO_NB_4 PCIE_DATA PCIE_DATA
82 82
84
82
9 PCIE_NB_TO_SLOTA_N<5> PCIE_NB_TO_SLOTA_5 PCIE_DATA PCIE_DATA 84 82 9
84 PCIE_SLOTA_TO_NB_N<5> PCIE_SLOTA_TO_NB_5 PCIE_DATA PCIE_DATA
84
9 PCIE_NB_TO_SLOTA_P<5> PCIE_NB_TO_SLOTA_5 PCIE_DATA PCIE_DATA 84
9 PCIE_SLOTA_TO_NB_P<5>
PCIE_SLOTA_TO_NB_5 PCIE_DATA PCIE_DATA
82 82
84
82
9 PCIE_NB_TO_SLOTA_N<6> PCIE_NB_TO_SLOTA_6 PCIE_DATA PCIE_DATA 9 PCIE_SLOTA_TO_NB_N<6>
PCIE_SLOTA_TO_NB_6 PCIE_DATA PCIE_DATA
82
84
9 PCIE_NB_TO_SLOTA_P<6> PCIE_NB_TO_SLOTA_6 PCIE_DATA PCIE_DATA 84 82 9
84 PCIE_SLOTA_TO_NB_P<6> PCIE_SLOTA_TO_NB_6 PCIE_DATA PCIE_DATA
e
82
84
82
9 PCIE_NB_TO_SLOTA_N<7> PCIE_NB_TO_SLOTA_7 PCIE_DATA PCIE_DATA 84
82
9 PCIE_SLOTA_TO_NB_N<7> PCIE_SLOTA_TO_NB_7 PCIE_DATA PCIE_DATA
84
9 PCIE_NB_TO_SLOTA_P<7> PCIE_NB_TO_SLOTA_7 PCIE_DATA PCIE_DATA 84
9 PCIE_SLOTA_TO_NB_P<7>
PCIE_SLOTA_TO_NB_7 PCIE_DATA PCIE_DATA
82 82
84
82
9 PCIE_NB_TO_SLOTA_N<8> PCIE_NB_TO_SLOTA_8 PCIE_DATA PCIE_DATA 84
82
9 PCIE_SLOTA_TO_NB_N<8> PCIE_SLOTA_TO_NB_8 PCIE_DATA PCIE_DATA
84
9 PCIE_NB_TO_SLOTA_P<8> PCIE_NB_TO_SLOTA_8 PCIE_DATA PCIE_DATA 84
9 PCIE_SLOTA_TO_NB_P<8>
PCIE_SLOTA_TO_NB_8 PCIE_DATA PCIE_DATA
82 82
B PCIE_NB_TO_SLOTA_N<9> PCIE_NB_TO_SLOTA_9 PCIE_DATA PCIE_DATA 9 PCIE_SLOTA_TO_NB_N<9>
PCIE_SLOTA_TO_NB_9 PCIE_DATA PCIE_DATA
B
r
84
82
9
82
84
9 PCIE_NB_TO_SLOTA_P<9> PCIE_NB_TO_SLOTA_9 PCIE_DATA PCIE_DATA 84 82 9
84 PCIE_SLOTA_TO_NB_P<9> PCIE_SLOTA_TO_NB_9 PCIE_DATA PCIE_DATA
82
9 PCIE_NB_TO_SLOTA_N<10> PCIE_NB_TO_SLOTA_10 PCIE_DATA PCIE_DATA 84
9 PCIE_SLOTA_TO_NB_N<10>
PCIE_SLOTA_TO_NB_10 PCIE_DATA PCIE_DATA
82 82
84 82 9
84 PCIE_NB_TO_SLOTA_P<10> PCIE_NB_TO_SLOTA_10 PCIE_DATA PCIE_DATA 84
82
9 PCIE_SLOTA_TO_NB_P<10> PCIE_SLOTA_TO_NB_10 PCIE_DATA PCIE_DATA
84
9 PCIE_NB_TO_SLOTA_N<11> PCIE_NB_TO_SLOTA_11 PCIE_DATA PCIE_DATA 84
9 PCIE_SLOTA_TO_NB_N<11>
PCIE_SLOTA_TO_NB_11 PCIE_DATA PCIE_DATA
82 82
84
82
9 PCIE_NB_TO_SLOTA_P<11> PCIE_NB_TO_SLOTA_11 PCIE_DATA PCIE_DATA 9 PCIE_SLOTA_TO_NB_P<11>
PCIE_SLOTA_TO_NB_11 PCIE_DATA PCIE_DATA
82
84
9 PCIE_NB_TO_SLOTA_N<12> PCIE_NB_TO_SLOTA_12 PCIE_DATA PCIE_DATA 84 82 9
84 PCIE_SLOTA_TO_NB_N<12> PCIE_SLOTA_TO_NB_12 PCIE_DATA PCIE_DATA
82
84
82
9 PCIE_NB_TO_SLOTA_P<12> PCIE_NB_TO_SLOTA_12 PCIE_DATA PCIE_DATA 84
9 PCIE_SLOTA_TO_NB_P<12>
PCIE_SLOTA_TO_NB_12 PCIE_DATA PCIE_DATA
82
84
PCIE_NB_TO_SLOTA_N<13> PCIE_NB_TO_SLOTA_13 PCIE_DATA PCIE_DATA 9 PCIE_SLOTA_TO_NB_N<13>
PCIE_SLOTA_TO_NB_13 PCIE_DATA PCIE_DATA
P
9
82 82
9 PCIE_NB_TO_SLOTA_P<13> PCIE_NB_TO_SLOTA_13 PCIE_DATA PCIE_DATA 84 82 9
84 PCIE_SLOTA_TO_NB_P<13> PCIE_SLOTA_TO_NB_13 PCIE_DATA PCIE_DATA
82
84
82
9
84 PCIE_NB_TO_SLOTA_N<14> PCIE_NB_TO_SLOTA_14 PCIE_DATA PCIE_DATA 84
9 PCIE_SLOTA_TO_NB_N<14>
PCIE_SLOTA_TO_NB_14 PCIE_DATA PCIE_DATA
82
84
9 PCIE_NB_TO_SLOTA_P<14> PCIE_NB_TO_SLOTA_14 PCIE_DATA PCIE_DATA 84
82
9 PCIE_SLOTA_TO_NB_P<14> PCIE_SLOTA_TO_NB_14 PCIE_DATA PCIE_DATA
82
84
82
9 PCIE_NB_TO_SLOTA_N<15> PCIE_NB_TO_SLOTA_15 PCIE_DATA PCIE_DATA 84
9 PCIE_SLOTA_TO_NB_N<15>
PCIE_SLOTA_TO_NB_15 PCIE_DATA PCIE_DATA
82
84
9 PCIE_NB_TO_SLOTA_P<15> PCIE_NB_TO_SLOTA_15 PCIE_DATA PCIE_DATA 9 PCIE_SLOTA_TO_NB_P<15>
PCIE_SLOTA_TO_NB_15 PCIE_DATA PCIE_DATA
82 82
84
KODIAK PCI-E POWER PHYSICAL CONSTRAINT TABLE
SIG_NAME MIN_LINE_WIDTH MIN_NECK_WIDTH VOLTAGE
82 6 KOD_G10_GND 0.3MM 0.25MM 0
82 6 KOD_H05_GND 0.3MM 0.25MM 0
82 6 KOD_H08_GND 0.3MM 0.25MM 0
82 6 KOD_J13_GND 0.3MM 0.25MM 0 KODIAK PCI-E CONST
82 6 KOD_K07_GND 0.3MM 0.25MM 0
A 82 6 KOD_L13_GND 0.3MM 0.25MM 0 SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
82 PWR_PCIE_A_AVDD 0.3MM 0.25MM 1.2
0.3MM 0.25MM 1.2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
97 82 PWR_PCIE_A_AVDD_2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
0.3MM 0.25MM 1.2 AGREES TO THE FOLLOWING
82 PWR_PCIE_A_AVDD_1
0.3MM 0.25MM 1.2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
97 82 PWR_PCIE_A_AVDD_0
0.3MM 0.25MM 1.2 II NOT TO REPRODUCE OR COPY IT
82 PWR_PCIE_A_AVDD_A
0.3MM 0.25MM 1.2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
82 PWR_PCIE_A_AVDD_B
82 PWR_PCIE_A_AVDD_C 0.3MM 0.25MM 1.2 SIZE DRAWING NUMBER REV.
PWR_PCIE_A_AVDD_2 0.3MM 0.25MM 1.2
97 82
97 82 PWR_PCIE_A_AVDD_0 0.3MM 0.25MM 1.2
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
8
NONE
97 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLANE-SPLIT AC RETURN PATHS 98 7 =PP1V2_PWRON_HT_NBTX
KODIAK HT DECOUPLING
LOCATE EACH CAPACITOR SO THAT
(LOCATE CLOSE TO PINS AS INDICATED)
THEY STRADDLE EACH PLANE SPLIT
KODIAK HT DECOUPLING (CAPACITORS ARE DOUBLED-UP WHERE POSSIBL;E)
(LOCATE CLOSE TO PINS AS INDICATED) 1 1 1 1 1
=PPVCORE_PWRON_NB_HT C9834 =PP1V2_PWRON_HT_NBTX
C9817 C9818 C9819 C9820 C9821
98 7 7 98
0.1UF 1UF 1UF 1UF 1UF 1UF 98 7 =PP1V2_PWRON_HT_NBTX
=PPVCORE_PWRON_NB_HT 10% 10% 10% 10% 10%
7 98 6.3V 6.3V 6.3V 6.3V 6.3V
1 2
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402
20% KODIAK CORES
10V
CERM
1
C9806 1
C9807 1
C9808 1
C9809 402 PP9806 1
C9827 1
C9828 1
C9829 1
C9830 1
C9831
P4MM
D 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM
1.6V
SM
PP
1
PP9807 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM 2
1UF
10%
6.3V
CERM
D
402 402 402 402
1
C9822 1
C9823 1
C9824 1
C9825 1
C9826 402 402 402 402 402
Q63 = PP1V6 P4MM
y
SM 1UF 1UF 1UF 1UF 1UF
1 10% 10% 10% 10% 10%
PP 1.2V 2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
CERM CERM CERM CERM CERM
402 402 402 402 402
98 7 =PPVCORE_PWRON_NB_HT Q63 = PP1V2
=PP2V5_PWRON_NB_HT
L9800
98 7 0.22UH
1 1 1 1 1 1 1 1 1
C9810 C9811 C9812 C9813 C9832 C9833 C9839 C9840 C9841
r
1 2 PWR_HT_AVDD
101 =PP1V2_PWRON_HT_NBTX 7 98
1UF 1UF 1UF 1UF L9801 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 0805-1 =PP2V5_PWRON_NB_HT 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 0.22UH 7 98
6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402
C9800 1 C9801 1 C9802 1 101 PWR_HT_AVDD2 1 2
0.01UF 10UF 1UF 0805-1
10% 10% 10%
16V 6.3V 6.3V
CERM 2 X5R 2 CERM 2
402 805 402
1
C9803 1
C9804 1
C9805
1UF 10UF 0.01UF
10% 10% 10%
a
1
C9814 1
C9815 2
6.3V
CERM 2
6.3V
X5R 2
16V
CERM C9847 1 1
C9842 1
C9843 1
C9844 1
C9845 1
C9846
1UF 1UF 402 805 402 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 101 98 6 KOD_L15_GND 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM CERM 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 (THIS PAGE) 402 402 402 402 402 402
PP9808 KOD_L15_GND 6 98 101
P4MM
SM (THIS PAGE)
1 K15 H15
HTM2NC0- PP
1 HT_REFCLK_AVDD HT_REFCLK_AVDD2
HTM2NC0+ PP
n
98 7 =PP1V2_PWRON_HT_NBTX SM (1.65V-2.75V) (1.65V-2.75V)
P4MM
(1.6V-1.2V) (1.6V-1.2V)
HT_MB_TO_NB_CLK_N<0>
PP9809 E25 A24 A16 J19 HT_NB_TO_MB_CLK_N<0>
101 HT_CLK_RXN0 HT_RX_VDD HT_VD4 HT_CLK_TXN0 101
i
HT_MB_TO_NB_CLK_P<0> D25 B22 A20 J20 HT_NB_TO_MB_CLK_P<0>
101 HT_CLK_RXP0 HT_RX_VDD HT_VD4 HT_CLK_TXP0 101
B26 B14
J27 HT_RX_VDD HT_VD4 J22
101 HT_MB_TO_NB_CTL_N<0> HT_CTL_RXN0 HT_CTL_TXN0 HT_NB_TO_MB_CTL_N<0> 101
C 101 HT_MB_TO_NB_CTL_P<0> K27
HT_CTL_RXP0
HT_RX_VDD
HT_RX_VDD
D24
E22
B18
D16
HT_VD4
HT_VD4
HT_CTL_TXP0 J21 HT_NB_TO_MB_CTL_P<0> 101 C
HT_MB_TO_NB_CAD_N<0> F26 E26 D20 F16 HT_NB_TO_MB_CAD_N<0>
PP9800 101 HT_CAD_RXN0 HT_RX_VDD HT_VD4 HT_CAD_TXN0 101
P4MM 101 HT_MB_TO_NB_CAD_P<0> F27 HT_CAD_RXP0 HT_RX_VDD G24 E18
HT_VD4 HT_CAD_TXP0 F17 HT_NB_TO_MB_CAD_P<0> 101
SM
1 HT_MB_TO_NB_CAD_N<1> F25 HT_CAD_RXN1 HT_RX_VDD H26 G16 HT_VD4 HT_CAD_TXN1 G17 HT_NB_TO_MB_CAD_N<1>
MHT0- PP 101 101
1 HT_MB_TO_NB_CAD_P<1> F24 HT_CAD_RXP1 HT_RX_VDD K24 G20 HT_VD4 HT_CAD_TXP1 H17 HT_NB_TO_MB_CAD_P<1>
MHT0+ PP 101 101
SM 101 HT_MB_TO_NB_CAD_N<2> A25 HT_CAD_RXN2 HT_RX_VDD L22 H18 HT_VD4 HT_CAD_TXN2 J18 HT_NB_TO_MB_CAD_N<2> 101
P4MM B25 H22 J17
101 HT_MB_TO_NB_CAD_P<2> HT_CAD_RXP2 HT_VD4 HT_CAD_TXP2 HT_NB_TO_MB_CAD_P<2> 101
PP9801 HT_MB_TO_NB_CAD_N<3> G25 K16 F18 HT_NB_TO_MB_CAD_N<3>
101 HT_CAD_RXN3 HT_VD4 HT_CAD_TXN3 101
m
101 HT_MB_TO_NB_CAD_P<3> H25 HT_CAD_RXP3 K20 HT_VD4 HT_CAD_TXP3 F19 HT_NB_TO_MB_CAD_P<3> 101
KODIAK HT RECEIVE CLOCKS HT_MB_TO_NB_CAD_N<4> L25 L18 G19 HT_NB_TO_MB_CAD_N<4>
101 HT_CAD_RXN4 HT_VD4 HT_CAD_TXN4 101
101 HT_MB_TO_NB_CAD_P<4> K25 HT_CAD_RXP4 M17 HT_VD4 HT_CAD_TXP4 H19 HT_NB_TO_MB_CAD_P<4> 101
PP9802
il
101 HT_MB_TO_NB_CAD_N<5> G27 HT_CAD_RXN5 M21 HT_VD4 HT_CAD_TXN5 G21 HT_NB_TO_MB_CAD_N<5> 101
P4MM H27 N19 H21
SM 101 HT_MB_TO_NB_CAD_P<5> HT_CAD_RXP5 HT_VD4 HT_CAD_TXP5 HT_NB_TO_MB_CAD_P<5> 101
1
MHT1- PP
101 HT_MB_TO_NB_CAD_N<6> J25 HT_CAD_RXN6 HT_CAD_TXN6 F21 HT_NB_TO_MB_CAD_N<6> 101
MHT1+ PP
1
R9806 1 101 HT_MB_TO_NB_CAD_P<6> J26 HT_CAD_RXP6 HT_CAD_TXP6 F20 HT_NB_TO_MB_CAD_P<6> 101
=PP1V2_PWRON_HT_NBTX 7 98
SM 8.2K C26 K21
NOSTUFF
P4MM 5% 101 HT_MB_TO_NB_CAD_N<7> HT_CAD_RXN7 HT_CAD_TXN7 HT_NB_TO_MB_CAD_N<7> 101
1
PP9803 1/16W
MF-LF 101 HT_MB_TO_NB_CAD_P<7> C27 HT_CAD_RXP7 HT_CAD_TXP7 L21 HT_NB_TO_MB_CAD_P<7> 101
R9808
402
2
8.2K
5%
HT_MB_TO_NB_CLK_N<1> F22 C16 HT_NB_TO_MB_CLK_N<1>
101 HT_CLK_RXN1 HT_CLK_TXN1 101 1/16W
MF-LF
101 HT_MB_TO_NB_CLK_P<1> F23
HT_CLK_RXP1 U1900 HT_CLK_TXP1 C17 HT_NB_TO_MB_CLK_P<1> 101
2 402
HT_MB_TO_NB_CTL_N<1> E21 KODIAK-ASIC-040812 E15 HT_NB_TO_MB_CTL_P<1>
9 HT_CTL_RXP1 HT_CTL_TXP1 9
HT X16 INTERFACE
e
HT_MB_TO_NB_CTL_P<1> D21 D15 HT_NB_TO_MB_CTL_N<1>
9 HT_CTL_RXN1 HT_CTL_TXN1 9
BGA
(6 OF 10) NOSTUFF
R9807 1 101 HT_MB_TO_NB_CAD_N<8> E23 HT_CAD_RXN8 HT_CAD_TXN8 D19 HT_NB_TO_MB_CAD_N<8> 101
1
8.2K 101 HT_MB_TO_NB_CAD_P<8> D23 HT_CAD_RXP8 SEE_TABLE HT_CAD_TXP8 E19 HT_NB_TO_MB_CAD_P<8> 101
R9809
5%
A23 D17
8.2K
1/16W 101 HT_MB_TO_NB_CAD_N<9> HT_CAD_RXN9 HT_CAD_TXN9 HT_NB_TO_MB_CAD_N<9> 101 5%
MF-LF 1/16W
B HT_MB_TO_NB_CAD_P<9> B23 HT_CAD_RXP9 HT_CAD_TXP9 E17 HT_NB_TO_MB_CAD_P<9>
B
r
402 2 101 101 MF-LF
402
101 HT_MB_TO_NB_CAD_N<10> H23 HT_CAD_RXN10 HT_CAD_TXN10 C19 HT_NB_TO_MB_CAD_N<10> 101
2
101 HT_MB_TO_NB_CAD_P<10> G23 HT_CAD_RXP10 HT_CAD_TXP10 C18 HT_NB_TO_MB_CAD_P<10> 101
101 HT_MB_TO_NB_CAD_N<11> C22 HT_CAD_RXN11 A14 HT_VD4_GND HT_CAD_TXN11 A15 HT_NB_TO_MB_CAD_N<11> 101
HT_MB_TO_NB_CAD_P<11> C23 A18 B15 HT_NB_TO_MB_CAD_P<11>
101 HT_CAD_RXP11 HT_VD4_GND HT_CAD_TXP11 101
101 HT_MB_TO_NB_CAD_N<12> K23 HT_CAD_RXN12 B16
HT_VD4_GND HT_CAD_TXN12 A17 HT_NB_TO_MB_CAD_N<12> 101
=PP2V5_PWRON_HT 7 103
101 HT_MB_TO_NB_CAD_P<12> L23 HT_CAD_RXP12 B20
HT_VD4_GND HT_CAD_TXP12 B17 HT_NB_TO_MB_CAD_P<12> 101
KODIAK HT REFCLK HT_MB_TO_NB_CAD_N<13> J23 D18 B19 HT_NB_TO_MB_CAD_N<13>
101 HT_CAD_RXN13 HT_VD4_GND HT_CAD_TXN13 101
TERMINATION HT_MB_TO_NB_CAD_P<13> J24 E16 A19 HT_NB_TO_MB_CAD_P<13>
HT_CAD_RXP13 HT_VD4_GND HT_CAD_TXP13
P
101 101
(LOCATE CLOSE TO INPUT PINS) A21 E20 C15 1 2 1
HT_MB_TO_NB_CAD_N<14> HT_CAD_RXN14 HT_VD4_GND HT_CAD_TXN14 HT_NB_TO_MB_CAD_N<14> R9810
1
R9811 R9813
101 101
R9812
HT_MB_TO_NB_CAD_P<14> B21 HT_CAD_RXP14 HT_RX_GND A22 G18
HT_VD4_GND HT_CAD_TXP14 C14 HT_NB_TO_MB_CAD_P<14> 1K 1K 1K
1
101 101 1K
101 26 HT_NB_REFCLK_P<0> R9800 101 HT_MB_TO_NB_CAD_N<15> C24 HT_CAD_RXN15 HT_RX_GND A26 G22
HT_VD4_GND HT_CAD_TXN15 C20 HT_NB_TO_MB_CAD_N<15> 101
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
100 C25 B24 H16 C21
MF-LF MF-LF MF-LF MF-LF
1% 101 HT_MB_TO_NB_CAD_P<15> HT_CAD_RXP15 HT_RX_GND HT_VD4_GND HT_CAD_TXP15 HT_NB_TO_MB_CAD_P<15> 101
2 402 2
402 1 402 2 402
1/16W
1 HT_RX_GND D22 H20
R9802 MF-LF
K19
HT_VD4_GND AF06
402 HT_KOD_PVTREF0 HT_PVTREF0 HT_LDTSTOP_L HT_LDTSTOP_L 103
20.5 2 HT_RX_GND D26 K18
L19 HT_VD4_GND AF09
1% HT_KOD_PVTREF1 HT_PVTREF1 HT_LDTREQ_L HT_LDTREQ_L 103
E24 L16
1/16W
L17
HT_RX_GND HT_VD4_GND AF03
MF-LF C9837 HT_KOD_PVTREF2_ALT HT_PVTREF2_ALT HT_PWROK HT_PWROK 103
402 HT_RX_GND G26 L20 HT_VD4_GND
2 HT_KOD_PVTREF3_ALT K17 AE11 HT_LDTRESET_L
0.01UF 1 HT_PVTREF3_ALT H24 M16
HT_RESET_L 103
101
1 2 R9801 HT_RX_GND HT_VD4_GND
HT_NB_P<0>
9
200 J16 K22 M20
HT_REFCLK_N HT_RX_GND HT_VD4_GND
1%
10% J15 HT_REFCLK_P HT_RX_GND L24 N18
1 16V
1/16W HT_VD4_GND
R9803 CERM
MF-LF
402 2 (200MHZ)
29.4 402
NOSTUFF 1%
1/16W HT_REFCLK_AGND
C9836 MF-LF
402
0.01UF 2
HT_NB_REFCLK_PF<0> L15
1 2 101 HT_NB_G
101 9
101 9 HT_NB_REFCLK_NF<0>
KODIAK HT16
10% KOD_L15_GND
A 16V
CERM
402
1
R9804
29.4
PP9804
P4MM
101 98 6
(THIS PAGE)
2
SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
1% SM
1 LAST_MODIFIED=Tue Aug 30 18:06:16 2005
1/16W HREF0- PP XW9800 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MF-LF C9838 1 SM
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
2 402 HREF0+ PP
0.01UF AGREES TO THE FOLLOWING
101 SM 1
HT_NB_N<0> 1 2 P4MM
9 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1 10%
PP9805 PAGE 98 II NOT TO REPRODUCE OR COPY IT
R9805 16V
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
CERM
20.5 402 KODIAK HT REFCLK
1%
1/16W SIZE DRAWING NUMBER REV.
MF-LF
2
402
APPLE COMPUTER INC.
D 051-6863 19
101 26 HT_NB_REFCLK_N<0>
SCALE SHT OF
9
NONE
98 154
8 7 6 5 4 3 2 1 DRAWING
8 7 6 5 4 3 2 1
SIG_NAME MAKE_BASE DIFFERENTIAL_PAIR EC_SET NET_PHYSICAL_TYPE NET_SPACING_TYPE
98 HT_NB_TO_MB_CLK_N<0> 9 HT_NB_TO_SB_CLK_N<0> TRUE HT_NB_TO_SB_CLK HT_NB_TO_SB_PP HT_CAD HT_NB_TO_SB_CLK HT_MB_TO_SB_CLK_N<0> 103
98 HT_NB_TO_MB_CLK_P<0> 9 HT_NB_TO_SB_CLK_P<0> TRUE HT_NB_TO_SB_CLK HT_NB_TO_SB_PP HT_CAD HT_NB_TO_SB_CLK HT_MB_TO_SB_CLK_P<0> 103
D 98
98
HT_NB_TO_MB_CAD_N<0>
HT_NB_TO_MB_CAD_P<0>
9
9
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CAD_P<0>
TRUE
TRUE
HT_NB_TO_SB_CAD0
HT_NB_TO_SB_CAD0
HT_NB_TO_SB_PP
HT_NB_TO_SB_PP
HT_CAD
HT_CAD
HT_NB_TO_SB_CAD
HT_NB_TO_SB_CAD
HT_MB_TO_SB_CAD_N<0>
HT_MB_TO_SB_CAD_P<0>
103
103
D
98 HT_NB_TO_MB_CAD_N<1> 9 HT_NB_TO_SB_CAD_N<1> TRUE HT_NB_TO_SB_CAD1 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_N<1> 103
y
98 HT_NB_TO_MB_CAD_P<1> 9 HT_NB_TO_SB_CAD_P<1> TRUE HT_NB_TO_SB_CAD1 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_P<1> 103
98 HT_NB_TO_MB_CAD_N<2> 9 HT_NB_TO_SB_CAD_N<2> TRUE HT_NB_TO_SB_CAD2 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_N<2> 103
98 HT_NB_TO_MB_CAD_P<2> 9 HT_NB_TO_SB_CAD_P<2> TRUE HT_NB_TO_SB_CAD2 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_P<2> 103
98 HT_NB_TO_MB_CAD_N<3> 9 HT_NB_TO_SB_CAD_N<3> TRUE HT_NB_TO_SB_CAD3 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_N<3> 103
98 HT_NB_TO_MB_CAD_P<3> 9 HT_NB_TO_SB_CAD_P<3> TRUE HT_NB_TO_SB_CAD3 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_P<3> 103
98 HT_NB_TO_MB_CAD_N<4> 9 HT_NB_TO_SB_CAD_N<4> TRUE HT_NB_TO_SB_CAD4 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_N<4> 103
r
98 HT_NB_TO_MB_CAD_P<4> 9 HT_NB_TO_SB_CAD_P<4> TRUE HT_NB_TO_SB_CAD4 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_P<4> 103
98 HT_NB_TO_MB_CAD_N<5> 9 HT_NB_TO_SB_CAD_N<5> TRUE HT_NB_TO_SB_CAD5 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_N<5> 103
98 HT_NB_TO_MB_CAD_P<5> 9 HT_NB_TO_SB_CAD_P<5> TRUE HT_NB_TO_SB_CAD5 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_P<5> 103
98 HT_NB_TO_MB_CAD_N<6> 9 HT_NB_TO_SB_CAD_N<6> TRUE HT_NB_TO_SB_CAD6 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_N<6> 103
98 HT_NB_TO_MB_CAD_P<6> 9 HT_NB_TO_SB_CAD_P<6> TRUE HT_NB_TO_SB_CAD6 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_P<6> 103
98 HT_NB_TO_MB_CAD_N<7> 9 HT_NB_TO_SB_CAD_N<7> TRUE HT_NB_TO_SB_CAD7 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_N<7> 103
98 HT_NB_TO_MB_CAD_P<7> 9 HT_NB_TO_SB_CAD_P<7> TRUE HT_NB_TO_SB_CAD7 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CAD_P<7> 103
a
98 HT_NB_TO_MB_CTL_N<0> 9 HT_NB_TO_SB_CTL_N<0> TRUE HT_NB_TO_SB_CTL0 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CTL_N<0> 103
98 HT_NB_TO_MB_CTL_P<0> HT_NB_TO_SB_CTL_P<0> TRUE HT_NB_TO_SB_CTL0 HT_NB_TO_SB HT_CAD HT_NB_TO_SB_CAD HT_MB_TO_SB_CTL_P<0> 103
98 HT_MB_TO_NB_CLK_N<0> 9 HT_SB_TO_NB_CLK_N<0> TRUE HT_SB_TO_NB_CLK HT_SB_TO_NB_PP HT_CAD HT_SB_TO_NB_CLK HT_SB_TO_MB_CLK_N<0> 103
98 HT_MB_TO_NB_CLK_P<0> 9 HT_SB_TO_NB_CLK_P<0> TRUE HT_SB_TO_NB_CLK HT_SB_TO_NB_PP HT_CAD HT_SB_TO_NB_CLK HT_SB_TO_MB_CLK_P<0> 103
98 HT_MB_TO_NB_CAD_N<0> 9 HT_SB_TO_NB_CAD_N<0> TRUE HT_SB_TO_NB_CAD0 HT_SB_TO_NB_PP HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_N<0> 103
98 HT_MB_TO_NB_CAD_P<0> 9 HT_SB_TO_NB_CAD_P<0> TRUE HT_SB_TO_NB_CAD0 HT_SB_TO_NB_PP HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_P<0> 103
n
98 HT_MB_TO_NB_CAD_N<1> 9 HT_SB_TO_NB_CAD_N<1> TRUE HT_SB_TO_NB_CAD1 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_N<1> 103
98 HT_MB_TO_NB_CAD_P<1> 9 HT_SB_TO_NB_CAD_P<1> TRUE HT_SB_TO_NB_CAD1 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_P<1> 103
98 HT_MB_TO_NB_CAD_N<2> 9 HT_SB_TO_NB_CAD_N<2> TRUE HT_SB_TO_NB_CAD2 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_N<2> 103
98 HT_MB_TO_NB_CAD_P<2> 9 HT_SB_TO_NB_CAD_P<2> TRUE HT_SB_TO_NB_CAD2 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_P<2> 103
i
98 HT_MB_TO_NB_CAD_N<3> 9 HT_SB_TO_NB_CAD_N<3> TRUE HT_SB_TO_NB_CAD3 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_N<3> 103
98 HT_MB_TO_NB_CAD_P<3> 9 HT_SB_TO_NB_CAD_P<3> TRUE HT_SB_TO_NB_CAD3 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_P<3> 103
98 HT_MB_TO_NB_CAD_N<4> 9 HT_SB_TO_NB_CAD_N<4> TRUE HT_SB_TO_NB_CAD4 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_N<4> 103
C 98
98
98
HT_MB_TO_NB_CAD_P<4>
HT_MB_TO_NB_CAD_N<5>
HT_MB_TO_NB_CAD_P<5>
9
9
9
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<5>
TRUE
TRUE
TRUE
HT_SB_TO_NB_CAD4
HT_SB_TO_NB_CAD5
HT_SB_TO_NB_CAD5
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_CAD
HT_CAD
HT_CAD
HT_SB_TO_NB_CAD
HT_SB_TO_NB_CAD
HT_SB_TO_NB_CAD
HT_SB_TO_MB_CAD_P<4>
HT_SB_TO_MB_CAD_N<5>
HT_SB_TO_MB_CAD_P<5>
103
103
103
C
98 HT_MB_TO_NB_CAD_N<6> 9 HT_SB_TO_NB_CAD_N<6> TRUE HT_SB_TO_NB_CAD6 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_N<6> 103
98 HT_MB_TO_NB_CAD_P<6> 9 HT_SB_TO_NB_CAD_P<6> TRUE HT_SB_TO_NB_CAD6 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_P<6> 103
98 HT_MB_TO_NB_CAD_N<7> 9 HT_SB_TO_NB_CAD_N<7> TRUE HT_SB_TO_NB_CAD7 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_N<7> 103
98 HT_MB_TO_NB_CAD_P<7> 9 HT_SB_TO_NB_CAD_P<7> TRUE HT_SB_TO_NB_CAD7 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CAD_P<7> 103
98 HT_MB_TO_NB_CTL_N<0> HT_SB_TO_NB_CTL_N<0> TRUE HT_SB_TO_NB_CTL0 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CTL_N<0> 103
98 HT_MB_TO_NB_CTL_P<0> 9 HT_SB_TO_NB_CTL_P<0> TRUE HT_SB_TO_NB_CTL0 HT_SB_TO_NB HT_CAD HT_SB_TO_NB_CAD HT_SB_TO_MB_CTL_P<0> 103
9
NC_HT_MB_TO_NB_CAD_P<8..15>
NC_HT_MB_TO_NB_CAD_N<8..15>
TP_HT_MB_TO_NB_CLK_N<1>
TP_HT_MB_TO_NB_CLK_P<1>
TRUE
TRUE
TRUE
TRUE
il m I97
HT_MB_TO_NB_CAD_P<8..15>
HT_MB_TO_NB_CAD_N<8..15>
HT_MB_TO_NB_CLK_N<1> 98
HT_MB_TO_NB_CLK_P<1> 98
98
98
e
6 NC_HT_NB_TO_MB_CAD_P<8..15> TRUE HT_NB_TO_MB_CAD_P<8..15> 98
6 NC_HT_NB_TO_MB_CAD_N<8..15> TRUE HT_NB_TO_MB_CAD_N<8..15> 98
6 NC_HT_NB_TO_MB_CLK_N<1> TRUE HT_NB_TO_MB_CLK_N<1> 98
6 NC_HT_NB_TO_MB_CLK_P<1> TRUE HT_NB_TO_MB_CLK_P<1> 98
B B
r
98 26 HT_NB_REFCLK_P<0> HT_NB_REFCLK0 HT_NB_REFCLK HT_CLK HT_CLK IN
98 26 HT_NB_REFCLK_N<0> HT_NB_REFCLK0 HT_CLK HT_CLK IN
98 9 HT_NB_P<0> HT_NB0 HT_CLK HT_CLK IN
98 9 HT_NB_N<0> HT_NB0 HT_CLK HT_CLK IN
98 9 HT_NB_REFCLK_PF<0> HT_NB_REFCLK_F0 HT_CLK HT_CLK IN
98 9 HT_NB_REFCLK_NF<0> HT_NB_REFCLK_F0 HT_CLK HT_CLK IN
A
98
98
98 6
98
SIG_NAME
PWR_HT_AVDD
PWR_HT_AVDD2
KOD_L15_GND
HT_NB_G
MIN_LINE_WIDTH
0.4MM
0.4MM
0.4MM
KEEP DIFF CLOCK FROM BEING A SINGLE XNET
P
MIN_NECK_WIDTH
0.2MM
0.2MM
0.2MM
VOLTAGE
2.5
2.5
0
IN
IN
IN
IN
FINO-M23
HT ALIASES
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER
08/26/2005
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
REV.
A
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 101 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
0.38mm SPACING HT_CLK66M_SB_C 103
I187 HT_CLK66M_SB 0.38mm SPACING HT_CLK66M_SB 26 103
I192
P3MM SPACING HT_LDTRESET_L 98 103
PP1V2_PWRON_HT_PLLDVDD
103 7 =PP1V2_PWRON_SB_HT RA300 VOLTAGE=1.2V
MIN_LINE_WIDTH=0.50mm
3.3 MIN_NECK_WIDTH=0.38mm
1 2
D
5%
1/8W
MF-LF 1 CA300 1 CA301
D
805
10UF 1uF =PP2V5_PWRON_HT 7 98
y
10% 10%
6.3V 6.3V
2 X5R 2 CERM
805 402
1 CA320
0.1uF
20%
10V
2 CERM
r
Page Notes PP1V2_PWRON_HT_PLLAVDD
402
Power aliases required by this page:
RA310 VOLTAGE=1.2V
MIN_LINE_WIDTH=0.50mm
3.3 MIN_NECK_WIDTH=0.38mm
=PP2V5_PWRON_HT 1 2
=PP1V2_PWRON_SB_HT 7 103
=PP1V2_PWRON_HT 5%
1/8W
MF-LF
805
1
CA310 1
CA311
Signal aliases required by this page:
10UF 1uF
10% 10% 1
CA302 1
CA330 1
CA331 1
CA332
a
(NONE) 6.3V 6.3V
2 2
X5R CERM 10UF 0.1uF 0.1uF 0.1uF
805 402 10% 20% 20% 20%
BOM options provided by this page: 6.3V 10V 10V 10V
2 X5R 2 CERM 2 CERM 2 CERM
- SB_HT_200M 805 402 402 402
Stuffs resistor to select 200MHz HT I/F.
=PP1V2_PWRON_SB_HT 7 103
n
1 P4MM SM
HTS2MC0+ PPA300 PP
1 P4MM SM
HTS2MC0- PPA301 PP
B19
B15
B17
G13
B12
G11
1
CA340 1
CA341 1
CA342
C7
B6
B9
1
CA309 0.1uF 0.1uF 0.1uF
i
AVDD DVDD VDDP HT_RXVDD HT_TXVDD 10UF 20% 20% 20%
1 P4MM 10% 10V 10V 10V
HTS2MC0+ PPA303 PP SM HT_PLL HT 6.3V
2 CERM 2 CERM 2 CERM
2 X5R 402 402 402
C HTS2MC0- PPA304 PP
1 P4MM SM U2300
SHASTA
SEE_TABLE 805
C
V1.1
BGA-LF
101
HT_MB_TO_SB_CLK_P<0> D15 HT_CLKIN_P (3 OF 8) HT_CLKOUT_P
B10 HT_SB_TO_MB_CLK_P<0> 101
HT_MB_TO_SB_CLK_N<0> C15 HT_CLKIN_N HT_CLKOUT_N A10 HT_SB_TO_MB_CLK_N<0>
HYPERTRANSPORT
101 101
101
HT_MB_TO_SB_CAD_P<0> D17 HT_CADIN_0_P HT_CADOUT_0_P D10 HT_SB_TO_MB_CAD_P<0> 101
101
HT_MB_TO_SB_CAD_N<0> C17 HT_CADIN_0_N HT_CADOUT_0_N C10 HT_SB_TO_MB_CAD_N<0> 101
101
HT_MB_TO_SB_CAD_P<1> B18 HT_CADIN_1_P HT_CADOUT_1_P B8 HT_SB_TO_MB_CAD_P<1> 101
m
101
HT_MB_TO_SB_CAD_N<1> A18 HT_CADIN_1_N HT_CADOUT_1_N A8 HT_SB_TO_MB_CAD_N<1> 101
101
HT_MB_TO_SB_CAD_P<2> F15
HT_CADIN_2_P HT_CADOUT_2_P E11 HT_SB_TO_MB_CAD_P<2> 101
101
HT_MB_TO_SB_CAD_N<2> E15 HT_CADIN_2_N HT_CADOUT_2_N F11 HT_SB_TO_MB_CAD_N<2> 101
HT_MB_TO_SB_CAD_P<3> HT_SB_TO_MB_CAD_P<3>
il
101
D16 HT_CADIN_3_P HT_CADOUT_3_P D11 101
101
HT_MB_TO_SB_CAD_N<3> C16
HT_CADIN_3_N HT_CADOUT_3_N C11 HT_SB_TO_MB_CAD_N<3> 101
101
HT_MB_TO_SB_CAD_P<4> B16 HT_CADIN_4_P HT_CADOUT_4_P A11 HT_SB_TO_MB_CAD_P<4> 101
101
HT_MB_TO_SB_CAD_N<4> A16 HT_CADIN_4_N HT_CADOUT_4_N B11 HT_SB_TO_MB_CAD_N<4> 101
101
HT_MB_TO_SB_CAD_P<5> D14 HT_CADIN_5_P HT_CADOUT_5_P C12 HT_SB_TO_MB_CAD_P<5> 101
101
HT_MB_TO_SB_CAD_N<5> C14 HT_CADIN_5_N HT_CADOUT_5_N D12 HT_SB_TO_MB_CAD_N<5> 101
101
HT_MB_TO_SB_CAD_P<6> E14 HT_CADIN_6_P HT_CADOUT_6_P E12 HT_SB_TO_MB_CAD_P<6> 101
101
HT_MB_TO_SB_CAD_N<6> F14 HT_CADIN_6_N HT_CADOUT_6_N F12 HT_SB_TO_MB_CAD_N<6> 101
101
HT_MB_TO_SB_CAD_P<7> B14 HT_CADIN_7_P HT_CADOUT_7_P A13 HT_SB_TO_MB_CAD_P<7> 101
101
HT_MB_TO_SB_CAD_N<7> A14
HT_CADIN_7_N HT_CADOUT_7_N B13 HT_SB_TO_MB_CAD_N<7> 101
e
P4MM 101
HT_MB_TO_SB_CTL_P<0> F13
HT_CTLIN_P HT_CTLOUT_P C13 HT_SB_TO_MB_CTL_P<0> 101
SM
1 HT_MB_TO_SB_CTL_N<0> E13 HT_CTLIN_N HT_CTLOUT_N D13 HT_SB_TO_MB_CTL_N<0>
PPA302 PP 101 101
98 HT_PWROK E16 HT_PWROK_H
103 98 HT_LDTRESET_L C18 HT_RESET_L RA301
B 0
B
r
HT_LDTSTOP_L E17 HT_LDTSTOP_L HT_LDTREQ_L A19 HT_LDTREQ_SB_L 1 2 HT_LDTREQ_L
RA355 98 98
0 C8 E10
5%
103 26 HT_CLK66M_SB 2 1 103 HT_CLK66M_SB_C HT_REFCLK HT_R100P SB_HT_R100_P 1/16W
MF-LF
SB_HT_S100M66M D8 HT_S100M66M F10 SB_HT_R100_N
5% HT_R100N 402
1/16W
SB_SELHT100 V6
MF-LF SEL_HT00_H
402
RA350
HT_PLL 82.5
1 2
1.0V pk-pk
AGND DGND HT_RXGND HT_TXGND
C6
A6
A15
A17
G12
A12
A9
G10
1%
1/16W
CA350 1 MF-LF 1
CA351
P
402
47pF 47pF
5% 5%
50V 50V
CERM 2 2 CERM
=PP1V2_PWRON_SB_HT 402 402
103 7
NOSTUFF NOSTUFF
RA352 1 RA354 1
4.7K 10K
1 = 100MHz 1% 5% 1 = 100MHz
1/16W 1/16W
MF-LF MF-LF
402 402
2 2
RA353 1 RA351 1
4.7K 1K
0 = 66MHz 1% 1% 0 = 200MHz
1/16W 1/16W
MF-LF
402 2
MF-LF
402 2
Shasta HyperTransport
A SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
HT RefClk HT I/F Speed PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
DETERMINES THE OPERATING FREQUENCY OF HT CORE AGREES TO THE FOLLOWING
1 = 100MHz 1 = 100MHz 1: THE HT SLAVE, HTGS AND THE HT SIDE OF THE PCI BRIDGES OPERATE AT 100 MHZ I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0 = 66MHz 0 = 200MHz 0: THE HT SLAVE, HTGS AND THE HT SIDE OF THE PCI BRIDGES OPERATE AT 200 MHZ II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
LAST_MODIFIED=Tue Aug 30 18:04:43 2005 103 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
PCI_AD<31..28> 120 121 122 125
PCI_AD<27> 120 121 122 125
PCI_AD<26..24> 120 121 122 125
PCI_AD<23> 120 121 122
PCI_AD<22> 120 121 122
PCI_AD<21> 120 121 122
PCI_AD<20> 120 121 122 125
PCI_AD<19..18> 120 121 122 125
PCI_AD<17> 120 121 122 125
PCI_AD<16..0> 120 121 122 125
D PCI_CBE_L<3..0> 120 121 122
D
PCI_PAR 120 121 122
y
PCI_DEVSEL_L 119 120 121 122
PCI_FRAME_L 119 120 121 122
PCI_IRDY_L 119 120 121 122
PCI_TRDY_L 119 120 121 122
r
PCI_STOP_L 119 120 121 122
I181 P3MM SPACING PCI_CLK66M_SB_INT 26 27 119
Q63 APPLICATION OF POWER NET "=PP3V3_SB_PCI" IS RUN
SM
P4MM
a
SM XWB900
PP_3V3RUNSB_B9
1
1
PPB905 PP
119 7 PP3V3_RUN_SB
Page Notes
SM
XWB901 P4MM
SM
CB910 CB900 CB901 CB902 CB903 CB904
1
1 1 1 1 1 1 6 PP_2V5PWRONSB_B9 1
Power aliases required by this page: PP PPB906
- =PP3V3_PCI 10UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
10% 20% 20% 20% 20% 20%
6.3V 10V 10V 10V 10V 10V
- =PP3V3_SB_PCI (CAN BE _PP3V3_PCI) 2 X5R 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
n
805 402 402 402 402 402
- =PP3V3_PWRON_SB
=PP2V5_PWRON_SB 7 23 24 138
- =PP2V5_PWRON_SB
Signal aliases required by this page: NO STUFF
i
(NONE)
1
CB911 1
CB905 1
CB906 1
CB907 1
CB908 1
CB909 CB920 1
CB921 1
CB922 1
CB923 1
10UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C BOM options provided by this page:
(NONE)
2
10%
6.3V
X5R
805
2
20%
10V
CERM
402
2
20%
10V
CERM
402
2
20%
10V
CERM
402
2
20%
10V
CERM
402
2
20%
10V
CERM
402
20%
10V
CERM
402
2
20%
10V
CERM
402
2
20%
10V
CERM
402
2
20%
10V
CERM
402
2 C
PCI Devices implemented on this page:
AA22
AD11 - PCI0 (0x106B/0x0053)
B22
E21
H16
J21
M16
N21
R20
U21
V19
B20
J18
N20
U20
AD11 - PCI1 (0x106B/0x0054)
VDDOPC PCIVDDP
AD11 - PCI2 (0x106B/0x0055)
AD23 - KeyLargo (0x106B/0x004F, PCI1) SEE_TABLE U2300
AD28 - SATA 150 (0x1166/0x0240, PCI0 or 2)
PPB900 SHASTA
m
V1.1
AD29 - UATA 133 (0x106B/0x0050, PCI0 or 2) P4MM P3MM SPACING
SM BGA-LF
1 PCI_CLK66M_SB_INT AB9 L18 PCI_SB_AD<0>
AD30 - FireWire (0x106B/0x0052, PCI0 or 2) PP 119 27 26 PCIBR_CLK_H (4 OF 8) PCI1AD_0_H 120
P4MM K19 PCI_SB_AD<1>
AD31 - Ethernet (0x106B/0x0051, PCI0) PCI1AD_1_H 120
SM
il
1 27 26 PCI_CLK33M_SB_EXT_RR U19 PCI1CLK_H PCI1AD_2_H L22 PCI_SB_AD<2>
PPB901 PP 120
M22 PCI_SB_AD<3>
PCI1AD_3_H 120
NOSTUFF PCI PCI1AD_4_H M18 PCI_SB_AD<4> 120
1
CB912 STUFF NEAR SHASTA L20 PCI_SB_AD<5>
2PF PCI1AD_5_H 120
+/-0.25PF
PCI1AD_6_H M21 PCI_SB_AD<6>
50V 120
2 C0G
PCI1AD_7_H N16 PCI_SB_AD<7>
402-1 120
PCI1AD_8_H M20 PCI_SB_AD<8> 120
PCI1AD_9_H P22 PCI_SB_AD<9> 120
"Slot A" - AD17 M17
PCI1AD_10_H PCI_SB_AD<10> 120
PP3V3_RUN_SB 7 119 121 119 PCI_SLOTA_REQ_L AB18 PCI1REQ_0_L N18 PCI_SB_AD<11>
AA18
PCI1AD_11_H 120
121 119 PCI_SLOTA_GNT_L PCI1GNT_0_L
e
M19 PCI_SB_AD<12>
RPB900 PCI1AD_12_H 120
4.7K PCI1AD_13_H N19 PCI_SB_AD<13> 120
2 7 PCI_SLOTA_REQ_L 119 121 "Slot G" - AD27 P21
PCI1AD_14_H PCI_SB_AD<14> 120
5% 122 119 PCI_SLOTG_REQ_L AB20 PCI1REQ_1_L R22 PCI_SB_AD<15>
1/16W
SM-LF
RPB900 122 119 PCI_SLOTG_GNT_L AB19 PCI1GNT_1_L
PCI1AD_15_H 120
4.7K PCI1AD_16_H P20 PCI_SB_AD<16> 120
B 1 8 PCI_SLOTA_GNT_L
B
r
119 121
PCI1AD_17_H V21 PCI_SB_AD<17> 120
5% "Slot D" - AD20 P18 119 7 PP3V3_RUN_SB
RPB900 1/16W PCI1AD_18_H PCI_SB_AD<18> 120
PCI_SLOTD_REQ_L V17 PCI1REQ_2_L
SM-LF 119
4.7K PCI1AD_19_H T20 PCI_SB_AD<19> 120 RPB902
4 5 PCI_SLOTG_REQ_L PCI_SLOTD_GNT_L V18 PCI1GNT_2_L
119 122 119
PCI1AD_20_H R16 PCI_SB_AD<20> 120 4.7K
PCI_DEVSEL_L 3 6
5% 122 121 120 119
R17 PCI_SB_AD<21>
1/16W RPB900 PCI1AD_21_H 120
5%
SM-LF 4.7K W21
PCI1AD_22_H PCI_SB_AD<22> 120 RPB902 1/16W
3 6 PCI_SLOTG_GNT_L 119 122 SM-LF
PCI1AD_23_H Y22 PCI_SB_AD<23> 120 4.7K
PCI_FRAME_L 4 5
5% 122 121 120 119
R18 PCI_SB_AD<24>
RPB901 1/16W PCI1AD_24_H 120
P
SM-LF 5%
4.7K PCI1AD_25_H T19 PCI_SB_AD<25> 120 1/16W RPB902
3 6 PCI_SLOTD_REQ_L 119 SM-LF
PCI1AD_26_H T18 PCI_SB_AD<26> 120
4.7K
5% 122 121 120 119 PCI_IRDY_L 2 7
Y21 PCI_SB_AD<27>
1/16W RPB901 PCI1AD_27_H 120
5%
SM-LF 4.7K W20
PCI1AD_28_H PCI_SB_AD<28> 120 RPB902 1/16W
4 5 PCI_SLOTD_GNT_L 119 SM-LF
PCI1AD_29_H T16 PCI_SB_AD<29> 120
4.7K
5% 122 121 120 119 PCI_TRDY_L 1 8
AA21 PCI_SB_AD<30>
1/16W PCI1AD_30_H 120
SM-LF 5%
T17 PCI_SB_AD<31>
PCI1AD_31_H 120 1/16W
SM-LF
RPB901
=PP3V3_PWRON_SB 7 20 23 24 56
4.7K
PCI1C_BE_0_L L19 PCI_SB_CBE_L<0> 120 122 121 120 119 PCI_STOP_L 7 2
PCI1C_BE_1_L P16 PCI_SB_CBE_L<1> 120 5%
1/16W
V22 PCI_SB_CBE_L<2>
PCI1C_BE_2_L 120 SM-LF
PCI1C_BE_3_L V20 PCI_SB_CBE_L<3> 120
PCI1DEVSEL_L T22 PCI_SB_DEVSEL_L 120
T21 PCI_SB_FRAME_L
PCI1FRAME_L 120 NOSTUFF
PCI1IRDY_L R21 PCI_SB_IRDY_L 120
1
RB955
1
CB950 1
RB950
PCI1TRDY_L P19 PCI_SB_TRDY_L 4.7K 0.1uF 4.7K
PCI1STOP_L P17 PCI_SB_STOP_L
120
120
1%
1/16W 2
20%
10V
1%
1/16W
Shasta PCI Interface
ROM_CS_L AB8 CERM
125 121 ROMCS_L N17 MF-LF 402 MF-LF
PCI_SB_PAR
A 125 121
125 121
ROM_OE_L
ROM_WE_L
AA9
Y10
ROMOE_L
ROMRW_L
PCI1PAR_H
PCI1RST_L U18 SB_PCI_RESET_L
120
2 402
1
5
2 402 SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
NET_SPACING_TYPE=P3MM SPACING 4 PCI_RESET_L 20 92
2
UB950 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
3
MC74VHC1G08
SOT23-5-LF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
122 30 28 24 SYS_IO_RESET_L II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Shasta drives PCI RESET, but its output SIZE DRAWING NUMBER REV.
RB900
may not be valid during power-up, so
it is ANDed with a reset from the SMU. 1
0
2
NOSTUFF
APPLE COMPUTER INC.
D 051-6863 19
5% SCALE SHT OF
1/16W
MF-LF NONE
LAST_MODIFIED=Tue Aug 30 18:04:49 2005
402 119 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ALL RESISTOR PACKS ARE 47 OHM 1/16W 5%
D D
R PAKS ARE PIN SWAPPABLE ACROSS ALL SIGNALS (EXCEPT IDSELS)
y
PCI_SB_AD<0> RPC003 4 5 47 PCI_AD<0>
119 119 121 122 125
PCI_SB_AD<1> RPC003 1 8 47 PCI_AD<1>
119 119 121 122 125
119 PCI_SB_AD<2> RPC009 1 8 47 PCI_AD<2> 119 121 122 125
RPC001 3 6 47
r
119 PCI_SB_AD<3> PCI_AD<3> 119 121 122 125
PCI_SB_AD<4> RPC000 3 6 47 PCI_AD<4>
119 119 121 122 125
PCI_SB_AD<5> RPC003 2 7 47 PCI_AD<5>
119 119 121 122 125
PCI_SB_AD<6> RPC001 4 5 47 PCI_AD<6>
119 119 121 122 125
PCI_SB_AD<7> RPC000 2 7 47 PCI_AD<7>
119 119 121 122 125
PCI_SB_AD<8> RPC007 4 5 47 PCI_AD<8>
119 119 121 122 125
PCI_SB_AD<9> RPC002 1 8 47 PCI_AD<9>
119 119 121 122 125
RPC000
a
119 PCI_SB_AD<10> 1 8 47 PCI_AD<10> 119 121 122 125
PCI_SB_AD<11> RPC009 3 6 47 PCI_AD<11>
119 119 121 122 125
PCI_SB_AD<12> RPC000 4 5 47 PCI_AD<12>
119 119 121 122 125
PCI_SB_AD<13> RPC009 4 5 47 PCI_AD<13>
119 119 121 122 125
PCI_SB_AD<14> RPC002 2 7 47 PCI_AD<14>
119 119 121 122 125
PCI_SB_AD<15> RPC002 4 5 47 PCI_AD<15>
119 119 121 122 125
PCI_SB_AD<16> RPC002 3 6 47 PCI_AD<16>
119 119 121 122 125
n
RC000
1
47 2
119 PCI_SB_AD<17> PCI_AD<17> 119 121 122 125
i
5%
1/16W
MF-LF
C 119 PCI_SB_AD<18> RPC007 1
402
8 47 PCI_AD<18> 119 121 122 125
C
PCI_SB_AD<19> RPC006 2 7 47 PCI_AD<19>
119 119 121 122 125
PCI_SB_AD<20> RPC007 2 7 47 PCI_AD<20>
119 119 121 122 125
PCI_SB_AD<21> RPC008 1 8 47 PCI_AD<21>
119 119 121 122
PCI_SB_AD<22> RPC004 1 8 47 PCI_AD<22>
119 119 121 122
PCI_SB_AD<23> RPC006 4 5 47 PCI_AD<23>
119 119 121 122
PCI_SB_AD<24> RPC008 4 5 47 PCI_AD<24>
119 119 121 122 125
PCI_SB_AD<25> RPC006 3 6 47 PCI_AD<25>
119 119 121 122 125
m
PCI_SB_AD<26> RPC008 3 6 47 PCI_AD<26>
119 119 121 122 125
RC001
47
il
119 PCI_SB_AD<27> 1 2 PCI_AD<27> 119 121 122 125
5%
1/16W
MF-LF
402
PCI_SB_AD<28> RPC004 4 5 47 PCI_AD<28>
119 119 121 122 125
PCI_SB_AD<29> RPC008 2 7 47 PCI_AD<29>
119 119 121 122 125
PCI_SB_AD<30> RPC004 2 7 47 PCI_AD<30>
119 119 121 122 125
PCI_SB_AD<31> RPC007 3 6 47 PCI_AD<31>
119 119 121 122 125
PCI_SB_CBE_L<0> RPC003 3 6 47 PCI_CBE_L<0>
119 119 121 122
PCI_SB_CBE_L<1> RPC001 1 8 47 PCI_CBE_L<1>
119 119 121 122
RPC006 1 8 47
e
119 PCI_SB_CBE_L<2> PCI_CBE_L<2> 119 121 122
PCI_SB_CBE_L<3> RPC004 3 6 47 PCI_CBE_L<3>
119 119 121 122
PCI_SB_DEVSEL_L RPC005 3 6 47 PCI_DEVSEL_L
119 119 121 122
PCI_SB_FRAME_L RPC005 4 5 47 PCI_FRAME_L
119 119 121 122
RPC005 47
B PCI_SB_IRDY_L 2 7 PCI_IRDY_L
B
r
119 119 121 122
PCI_SB_TRDY_L RPC005 1 8 47 PCI_TRDY_L
119 119 121 122
PCI_SB_STOP_L RPC001 2 7 47 PCI_STOP_L
119 119 121 122
PCI_SB_PAR RPC009 2 7 47 PCI_PAR
119 119 121 122
PLACE CLOSE TO SHASTA
P
AD<17> IS IDSEL FOR AIRPORT
AD<27> IS IDSEL FOR USB
PCI SERIES TERMINATION
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
D 051-6863 19
APPLE COMPUTER INC.
SCALE SHT OF
NONE 120 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
PCI_CLK_AIRPORT CLOCKS PCI_CLK33M_AIRPORT 26 121
Page Notes
Power aliases required by this page:
- _PP3V3_PCI
Signal aliases required by this page:
- _PCI_CLK33M_AIRPORT (33MHz PCI clock)
D BOM options provided by this page: D
(NONE)
y
PCI Devices implemented on this page:
AD17 (Slot "A") - AirPort (0x????/0x????)
NOTE: This AirPort implementation does
Q85 WIRELESS CONNECTOR
not support PME#.
r
125 7 =PP3V3_PCI
SDFC100 NOSTUFF
STDOFF-3MMOD5MMH-1.35-TH 1 CC150 1 CC151 1 CC152
1 10UF
10%
1UF
10% 10%
1UF
2 6.3V
X5R 2 6.3V
CERM 2 6.3V
CERM
805 402 402
a
CRITICAL
JC150
20-5602-080-041-829
F-ST-SM
1 2 PCI_AD<31> 119 120 122 125
125 122 120 119 PCI_AD<30> 3 4 AIRPORT_CLKRUN_L_PD
n
5 6 TP_AP_PME_L
125 122 120 119 PCI_AD<27>
PCI_SLOTA_REQ_L
7
9
8
10
PCI_SLOTA_GNT_L 119 RC150
1
119 10K
5%
i
125 122 120 119 PCI_AD<25> 11 12 1/16W
13 14 MF-LF
125 122 120 119 PCI_AD<29> PCI_AD<24> 119 120 122 125
2 402
15 16
C 122 120 119 PCI_CBE_L<3> 17 18
=PCI_AIRPORT_RESET_L 20
PCI_AD<28> 119 120 122 125
C
125 122 120 119 PCI_AD<26> 19 20
RC151 122 120 119 PCI_AD<22> 21 22 PCI_AD<23> 119 120 122
1
22 2 23 24
125 122 121 120 119 PCI_AD<17> PCI_SLOTA_IDSEL
5% 25 26 PCI_AD<20> 119 120 122 125
1/16W
MF-LF 125 122 120 119 PCI_AD<19> 27 28 PCI_FRAME_L 119 120 122
402
122 120 119 PCI_AD<21> 29 30 PCI_AD<17> 119 120 121 122 125
122 120 119 PCI_IRDY_L 31 32
m
125 122 120 119 PCI_AD<18> 33 34 PCI_TRDY_L 119 120 122
122 120 119 PCI_DEVSEL_L 35 36
37 38 PCI_CBE_L<2> 119 120 122
il
121 26 PCI_CLK33M_AIRPORT 39 40 PCI_AD<16> 119 120 122 125
122 120 119 PCI_STOP_L 41 42
125 122 120 119 PCI_AD<12> 43 44
122 120 119 PCI_PAR 45 46
47 48 PCI_AD<14> 119 120 122 125
125 122 120 119 PCI_AD<8> 49 50 PCI_AD<13> 119 120 122 125
125 122 120 119 PCI_AD<9> 51 52
122 120 119 PCI_CBE_L<0> 53 54 PCI_AD<10> 119 120 122 125
55 56 PCI_AD<15> 119 120 122 125
125 122 120 119 PCI_AD<7> 57 58 AP_ALT_ANT NC_AP_ALT_ANT
59 60 MAKE_BASE=TRUE
e
125 122 120 119 PCI_AD<3> PCI_CBE_L<1> 119 120 122 NO_TEST=YES
125 122 120 119 PCI_AD<6> 61 62 PCI_AD<4> 119 120 122 125
63 64
125 122 120 119 PCI_AD<1> 65 66 PCI_AD<11> 119 120 122 125
125 122 120 119 PCI_AD<5> 67 68 ROM_WE_L 119 125
B B
r
125 122 120 119 PCI_AD<0> 69 70 PCI_AD<2> 119 120 122 125
71 72
143 USB_BT_P 73 74 PCI_AIRPORT_INT_L 24
143 USB_BT_N 75 76 ROM_OE_L 119 125
77 78 ROM_ONBOARD_CS_L 125
7 =PP3V3_PWRON_BT 79 80 ROM_CS_L 119 125
516S0347
P
CC160 1
1UF
10%
6.3V
CERM 2
402
SDFC101
STDOFF-3MMOD5MMH-1.35-TH
1
AIRPORT & BLUETOOTH
A SYNC_MASTER=FINO-M23
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE 121 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
CLOCKS =PCI_CLK33M_USB2 27 122
Page Notes Q63 APPLICATION OF POWER NET "=PPVIO_PCI_USB2" IS PP3V3_RUN
Power aliases required by this page:
- _PPVIO_PCI (to 3.3V or 5V)
Signal aliases required by this page: 122 7 =PPVIO_PCI_USB2
SM
XWC200 P4MM
- _PCI_CLK33M_USB2 (33MHz PCI clock) SM
PP_VIOPCIUSB2_C2
1
6 1
PPC203
D BOM options provided by this page:
PP
D
(NONE) CC201 1
CC202 1
CC203 1
y
0.1uF 0.1uF 0.1uF
20% 20% 20%
PCI Devices implemented on this page: 10V 10V 10V
CERM 2 CERM 2 CERM 2
AD27 (Slot "G") - USB2 (0x1033/0x0035) 402 402 402
NOTE: This USB2 implementation supports
H3
M4
C8
D3cold.
r
PCI_AD<0> M5
125 121 120 119 AD0
VDD_PCI
PCI_AD<1> P5
125 121 120 119 AD1
PCI_AD<2> N5
125 121 120 119 AD2
PCI_AD<3> P4
125 121 120 119 AD3
PCI_AD<4> N4
125 121 120 119 AD4
PCI_AD<5> M3
125 121 120 119 AD5
PCI_AD<6> N3
AD6 CRITICAL
a
125 121 120 119
PCI_AD<7> M1
125 121 120 119 AD7 UC200
PCI_AD<8> L2
125 121 120 119 AD8
PCI_AD<9> L1 NEC_UPD720101_USB2
125 121 120 119 AD9 FBGA-LF
PCI_AD<10> K2
125 121 120 119 AD10
PCI_AD<11> L3
125 121 120 119 AD11
PCI_AD<12> K1
125 121 120 119 AD12
PCI_AD<13> K3
125 121 120 119 AD13
n
PCI_AD<14> J2
125 121 120 119 AD14
PCI_AD<15> J1
125 121 120 119 AD15
PCI_AD<16> F2
125 121 120 119 AD16
i
PCI_AD<17> E3
125 121 120 119 AD17
PCI_AD<18> E1
125 121 120 119 AD18
C 125 121 120 119
125 121 120 119
PCI_AD<19>
PCI_AD<20>
D3
D1
AD19
AD20
C
PCI_AD<21> D2
121 120 119 AD21
PCI_AD<22> C2
121 120 119 AD22
PCI_AD<23> C1
121 120 119 AD23
PCI_AD<24> B4
125 121 120 119 AD24
PCI_AD<25> A4
125 121 120 119 AD25
PCI_AD<26> B5
125 121 120 119 AD26
PCI_AD<27> C4
125 121 120 119 (PCI_AD<27>) AD27
m
PCI_AD<28> A5
125 121 120 119 AD28
PCI_AD<29> C5
125 121 120 119 AD29
PCI_AD<30> B6
125 121 120 119 AD30
il
PCI_AD<31> A6
125 121 120 119 AD31
PCI_CBE_L<0> M2
121 120 119 CBE0
RC214 1 121 120 119 PCI_CBE_L<1> J3
CBE1
22 PCI_CBE_L<2> F1
121 120 119 CBE2
5% C3
1/16W 121 120 119 PCI_CBE_L<3> CBE3
MF-LF
402 2
PCI_PAR J4
121 120 119 PAR
PCI_FRAME_L F3
=PPVIO_PCI_USB2 121 120 119 FRAME
122 7
PCI_IRDY_L F4
121 120 119 IRDY
e
PCI_TRDY_L G1
121 120 119 TRDY
PCI_STOP_L G3
121 120 119 STOP
RC216 1 RC213 1 PCI_SLOTG_IDSEL B3
IDSEL
10K 10K G2
5% 5% 121 120 119 PCI_DEVSEL_L DEVSEL
1/16W 1/16W
PCI_SLOTG_REQ_L C6
MF-LF MF-LF 119 REQ
B RPC203 B
r
402 2 402 2
PCI_SLOTG_GNT_L D6
47 119 GNT
PCI_USB2_INT_L 4 5 NEC_PERR_L_PU H2
NTEST1 M8 TP_NEC_NTEST1
24 PERR IPD 6
NEC_SERR_L_PU H1
5% SERR OD
1/16W RPC203 NEC_INTA_L C7
SMC M7 TP_NEC_SMC
SM-LF
47 INTA OD IPD 6
2 7 NEC_INTB_L B7
INTB OD
NEC_INTC_L A7
5% INTC OD
RPC203 1/16W
122 27 =PCI_CLK33M_USB2
A8 TEB N7 TP_NEC_TEB
47 SM-LF PCLK IPD
3 6
IPD AMC P7 TP_NEC_AMC ALL NETS TO FUNCTIONAL TEST PAGE
P
NEC_VBBRST_L B8
5% VBBRST (CHIP RESET)
1/16W
SM-LF
RC250 NEC_CRUN_L_PD N6
CRUN IPD TEST L8 TP_NEC_TEST 6
47 D9
119 30 28 24 SYS_IO_RESET_L 1 2 NEC_PME_L PME OD
C9
5%
1/16W
VCCRST (PCI RESET)
RC251 MF-LF 6 TP_NEC_SMI_L L6
SMI OD NANDTEST M10 TP_NEC_NANDTEST
47 402
28 24 SYS_PME_L 1 2 SRCLK M9 TP_NEC_SRCLK 6
5% SRDTA N9 TP_NEC_SRDATA
1/16W
MF-LF NEC_LEGC_PD L7
LEGC IPD SRMOD P9 TP_NEC_SRMOD 6
402
20 =PCI_USB2_RESET_L
8
RC215 1 RPC203
4.7K 47
1%
RC250, RC251 & RPC203 REQUIRED TO
1/16W 5%
facilitate NAND-tree testing MF-LF 1/16W
402 SM-LF
2
1
P4MM
SM
1
PPC200 PP
USB 2.0 PCI Interface
P4MM
A PPC201
SM
PP
1
SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
LAST_MODIFIED=Tue Aug 30 18:04:51 2005
122 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
- =PP3V3_PCI
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)
NOTE: This page does not specify a BootROM
part number. Must use a TABLE_x_ITEM
D symbol to declare U7500 part number. D
Q63 APPLICATION IS RUN
r y
a
125 121 7 =PP3V3_PCI
CC500 1 CC501 1 CC502 1
2.2UF 0.1uF 0.1uF
20% 20% 20%
6.3V 10V 10V
CERM1 2 CERM 2 CERM 2
603 402 402
n
11 30 31
i
VPP VCC
UC500
C 122 121 120 119 PCI_AD<0> 21
1MX8-3.3V-90.0NS
A0 TSOP DQ0
25 PCI_AD<24> 119 120 121 122
C
PCI_AD<1> 20 26 PCI_AD<25>
122 121 120 119
A1SEE_TABLE DQ1 119 120 121 122
122 121 120 119 PCI_AD<2> 19 27 PCI_AD<26> 119 120 121 122
A2 DQ2
122 121 120 119 PCI_AD<3> 18 28 PCI_AD<27> 119 120 121 122
A3 DQ3
122 121 120 119 PCI_AD<4> 17 32 PCI_AD<28> 119 120 121 122
A4 DQ4
122 121 120 119 PCI_AD<5> 16 33 PCI_AD<29> 119 120 121 122
A5 DQ5
122 121 120 119 PCI_AD<6> 15 34 PCI_AD<30> 119 120 121 122
A6 DQ6
122 121 120 119 PCI_AD<7> 14 35 PCI_AD<31> 119 120 121 122
A7 DQ7
m
121 ROM_ONBOARD_CS_L 122 121 120 119 PCI_AD<8> 8
A8
PCI_AD<9> 7
122 121 120 119
A9
122 121 120 119 PCI_AD<10> 36
A10
il
Q63 APPLICATION IS RUN 122 121 120 119 PCI_AD<11> 6
A11
PCI_AD<12> 5
122 121 120 119
A12
122 121 120 119 PCI_AD<13> 4
A13
125 121 7
=PP3V3_PCI 122 121 120 119 PCI_AD<14> 3
A14
122 121 120 119 PCI_AD<15> 2
A15
122 121 120 119 PCI_AD<16> 1
A16
122 121 120 119 PCI_AD<17> 40
RC500 1 1
RC501 1
RC503 1
RC504 A17
402 122 121 120 119 PCI_AD<18> 13
10K MF-LF 10K 10K 10K A18
5% 1/16W 5% 5% 5% 122 121 120 119 PCI_AD<19> 37
1/16W 5% 1/16W 1/16W 1/16W A19
MF-LF MF-LF MF-LF MF-LF PCI_AD<20> 38
to intercept ROM chip select 402 2
RC502 2 402 2 402 2 402
122 121 120 119
A20
e
Allows ROM override module
470
121 119 ROM_CS_L 1 2 22
CE
ROM_OE_L 24
121 119
OE
121 119 ROM_WE_L 9
WE
ROM_WP_L 12
WP
B B
r
20 =PCI_ROM_RESET_L 10
PWD
P4MM
GND
SM
1
PPC500 PP 23 39
P4MM
SM
1
PPC501 PP
P4MM
SM
1
PPC502 PP
P
P4MM
SM
1
PPC503 PP
BootROM
A SYNC_MASTER=Q63
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=08/26/2005
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
LAST_MODIFIED=Tue Aug 30 18:04:52 2005 125 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE NET_PHYSICAL_TYPE DIFFERENTIAL_PAIR PLACE UATA TERMINATION RESISTORS NEAR JC901 CONNECTOR
SATA SATA SATA_RXD1_C SATA_RXD_P1_C 127 129
SATA SATA SATA_RXD1_C SATA_RXD_N1_C 127 129
RC706
33
129 127 UATA_RESET_L_R 1 2 UATA_RESET_L 127 129
SATA SATA SATA_TXD1 SATA_TXD_P1 127 129
5%
SATA SATA SATA_TXD1 SATA_TXD_N1 1/16W
127 129
MF-LF RC704
402 22
SATA SATA SATA_RXD2_C SATA_RXD_P2_C 127 129 129 127 UATA_DMACK_L_R 1 2 UATA_DMACK_L 127 129
SATA SATA SATA_RXD2_C SATA_RXD_N2_C 127 129 5%
1/16W
RC702 MF-LF
SATA SATA SATA_TXD2 SATA_TXD_P2 127 129 22 402
DIOR- :HDMARDY- :HSTROBE > 129 127 UATA_HSTROBE_R 1 2 UATA_HSTROBE 127 129
SATA SATA SATA_TXD2 SATA_TXD_N2 127 129
5%
D UATA_DD<15..8> 9 127 129
DIOW- :STOP >
1/16W
MF-LF
402
RC703
22
D
UATA_DD<7> 127 129 129 127 UATA_STOP_R 1 2 UATA_STOP 127 129
y
UATA_DD<6..0> 9 127 129 5%
1/16W
UATA_DA<2..0> 9 127 129 MF-LF
402
UATA_CS0_L 127 129
UATA_CS1_L 127 129
RC700
UATA_HSTROBE 127 129 33
r
129 127 UATA_CS0_L_R 1 2 UATA_CS0_L 127 129
UATA_STOP 127 129
5%
UATA_DMACK_L 127 129 1/16W
RC701
MF-LF
UATA_NETSPA UATA_RESET_L 127 129 402 33
129 127 UATA_CS1_L_R 1 2 UATA_CS1_L 127 129
UATA_DSTROBE 127 129
5%
UATA_DMARQ 127 129 1/16W
MF-LF
UATA_INTRQ 127 129 402
a
I171
UATA_DD_R<15..8> 127 129
I172
UATA_DD_R<7> 127 129
UATA_DD_R<6..0> 127 129
RPC704
I173 33
UATA_DA_R<2..0> UATA_DA_R<0> 2 7 UATA_DA<0>
I174 127 129 SPARE 129 127 9 127 129
I175
UATA_CS0_L_R 127 129 RPC704 5%
UATA_CS1_L_R 127 129 33 1/16W RPC704
I176 3 6 SM-LF 33
UATA_DMACK_L_R 127 129 UATA_DA_R<1> 1 8 UATA_DA<1>
I177 129 127 127 129
5%
UATA_HSTROBE_R
n
I178 127 129 1/16W 5%
UATA_STOP_R 127 129
SM-LF RPC704 1/16W
I179 33 SM-LF
UATA_RESET_L_R 127 129 UATA_DA_R<2> 4 5 UATA_DA<2>
I180 129 127 127 129
5%
i
1/16W
SM-LF
C RPC700
33
C
UATA_DD_R<0> 4 5 UATA_DD<0>
129 127 127 129
5%
RPC700 1/16W
SM-LF
33
UATA_DD_R<1> 3 6 UATA_DD<1>
129 127 9 127 129
5%
LC700
MIN_NECK_WIDTH=0.2MM 1/16W
SM-LF
RPC700
=PP1V2_PWRON_DISK_SB MIN_LINE_WIDTH=0.6MM 33
7 600-OHM-1.0A
SM
P4MM UATA_DD_R<2> 2 7 UATA_DD<2>
PP1V2_SATA_VDD XWCC00 129 127 127 129
m
SM
1
1 2 6 PP_1V2PWRONDISKSB_CC 1
PP PPCC00 5%
0805 NO_TEST=YES RPC700 1/16W
SM-LF
33
1
CC705 1
CC700 1
CC701 1
CC702 1
CC703 1
CC704 129 127 UATA_DD_R<3> 1 8 UATA_DD<3> 127 129
2.2UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
il
5%
20% 20% 20% 20% 20% 20%
2
6.3V
2
10V
2
10V
2
10V
2
10V
2
10V
1/16W RPC701
CERM1 CERM CERM CERM CERM CERM SM-LF 33
603 402 402 402 402 402 UATA_DD_R<4> 4 5 UATA_DD<4>
129 127 127 129
5%
RPC701 1/16W
AB14
AB17
T14
W15
Y18
SM-LF
33
UATA_DD_R<5> 3 6 UATA_DD<5>
129 127 127 129
SATA_VDD x 5 SATA_VDD 5%
SEE_TABLE
1/16W RPC701
U2300 SM-LF 33
UATA_DD_R<6> 2 7 UATA_DD<6>
129 127 127 129
SHASTA
V1.1 5%
RPC701 1/16W
e
Page Notes BGA-LF
(5 OF 8)
J6 129 127 UATA_DD_R<7> 1
33
8
5%
SM-LF
UATA_DD<7> 127 129
UD_IDEDD_0_H UATA_DD_R<0> 127 129
Power aliases required by this page: H7
UD_IDEDD_1_H UATA_DD_R<1> 127 129 1/16W RPC702
- _PP1V2_PWRON_DISK SM-LF
UD_IDEDD_2_H H6 UATA_DD_R<2> 127 129 33
UATA_DD_R<8> 1 8 UATA_DD<8>
129 127 127 129
B E2 UATA_DD_R<3>
B
r
Signal aliases required by this page: UD_IDEDD_3_H 127 129
5%
C1 UATA_DD_R<4>
(NONE) UD_IDEDD_4_H 127 129 RPC702 1/16W
SM-LF
UD_IDEDD_5_H C2 UATA_DD_R<5> 127 129 33
BOM options provided by this page: UATA_DD_R<9> 2 7 UATA_DD<9>
129 127 127 129
UD_IDEDD_6_H E3 UATA_DD_R<6> 127 129
(NONE) 5%
G6 UATA_DD_R<7>
UD_IDEDD_7_H 127 129 1/16W
SM-LF
RPC702
UATA
UD_IDEDD_8_H G5 UATA_DD_R<8> 127 129 33
UATA_DD_R<10> 3 6 UATA_DD<10>
Net Spacing Type: SATA D4 129 127 127 129
UD_IDEDD_9_H UATA_DD_R<9> 127 129
5%
G7 UATA_DD_R<10>
Line To Line: 0.38mm UD_IDEDD_10_H 127 129 RPC702 1/16W
F6 33 SM-LF
UD_IDEDD_11_H UATA_DD_R<11>
P
Length Tolerance: 1.27mm 127 129
4 5
C3 129 127 UATA_DD_R<11> UATA_DD<11> 127 129
Primary Max Sep: 0.25mm outer UD_IDEDD_12_H UATA_DD_R<12> 127 129
F5 5%
Primary Max Sep: 0.23mm inner DSTROBE aka: UD_IDEDD_13_H UATA_DD_R<13> 127 129 1/16W RPC703
E5 SM-LF 33
Secondary Max Sep: 2.54mm IORDY/HDMARDY* UD_IDEDD_14_H UATA_DD_R<14> 127 129
4 5
D5
129 127 UATA_DD_R<12> UATA_DD<12> 9 127 129
Secondary Length: 12.70mm UD_IDEDD_15_H UATA_DD_R<15> 127 129
HSTROBE aka: 5%
NOTE: Target differential impedance for UD_IDEDA0_H E6 UATA_DA_R<0> RPC703 1/16W
DIOR* 127 129
33 SM-LF
C4 UATA_DA_R<1> UATA_DD_R<13> 3 6 UATA_DD<13>
SATA data pairs is 100 ohms. UD_IDEDA1_H 127 129 129 127 9 127 129
STOP aka:
D6 UATA_DA_R<2>
UD_IDEDA2_H 127 129 5%
DIOW* 1/16W RPC703
B3 SM-LF 33
UD_IDECS1FX_L UATA_CS0_L_R 127 129
UATA_DD_R<14> 2 7 UATA_DD<14>
129 127 9 127 129
UATA_DSTROBE F9 B4 UATA_CS1_L_R
129 127 UD_IDECHRDY_H UD_IDECS3FX_L 127 129
5%
UATA_DMARQ D7
UD_IDEDMARQ_H UD_IDEDMACK_L E8 UATA_DMACK_L_R RPC703 1/16W
129 127 127 129 SM-LF
33
4-29-05 129 127 UATA_INTRQ C5
UD_IDEINTRQ_H
UD_IDERD_L E4 UATA_HSTROBE_R 127 129 129 127 UATA_DD_R<15> 1 8 UATA_DD<15> 127 129
UD_IDEWR_L D3 UATA_STOP_R 127 129 5%
AS OF TODAY THIS PAGE FOR M33 IS NOT UD_IDERST_L E7 UATA_RESET_L_R 127 129
1/16W
SM-LF
SYNC WITH Q63. 129 127 SATA_RXD_P1_C Y17 RXDP1 TXDP1 AA16 SATA_TXD_P1 127 129 Shasta Disk
SATA_RXD_N1_C Y16 RXDN1 SATA 0 TXDN1 AB16 SATA_TXD_N1 RC705 1
RPAK PINS WERE REMAPPED FOR 129 127 127 129
10K
A BETTER ROUTING AROUND UATA 129 127 SATA_RXD_P2_C AB15 RXDP2
SATA 1
TXDP2 Y15 SATA_TXD_P2 127 129
5%
1/16W
MF-LF
SYNC_MASTER=M33-DC
NOTICE OF PROPRIETARY PROPERTY
SYNC_DATE=06/20/2005
A
129 127 SATA_RXD_N2_C AA15
RXDN2 TXDN2 Y14 SATA_TXD_N2 127 129 402
2
CONNECTOR. SATA_GND THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AA14
AA17
T13
W16
AGREES TO THE FOLLOWING
P4MM
SM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1
PP PPCC01 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6863 19
SCALE SHT OF
NONE
LAST_MODIFIED=Tue Aug 30 18:04:53 2005
127 154
DRAWING
TITLE=KILOHANA
ABBREV=DRAWING
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SATA & USB DIFF PAIR GND VIAS
ADD THESE GROUND VIAS NEAR EACH LAYER JUMP ELECTRICAL_CONSTRAINT_SET NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR NO_TEST
FOR THE SATA DIFF PAIRS. ONE GND VIA PER
SATA CONNECTOR CC904
SIGNAL VIA, AND PLACE GND VIA APPROXIMATELY
129 127 9
129 127
UATA_DD<15..8>
UATA_DD<7>
UATA_DD
UATA_DD7
UATA_NETPH
UATA_NETPH
UATA_NETSPA
UATA_NETSPA
0.152MM AWAY FROM SIGNAL VIA.
0.01UF 129 127 9 UATA_DD<6..0> UATA_DD UATA_NETPH UATA_NETSPA
129 SATA_TXD_P1_C 1 2 SATA_TXD_P1 127 129 129 127 9 UATA_DA<2..0> UATA_HOST UATA_NETPH UATA_NETSPA
129 127 UATA_CS0_L UATA_HOST UATA_NETPH UATA_NETSPA
CRITICAL CC905 10%
16V GV901 GV902 UATA_CS1_L UATA_HOST UATA_NETPH UATA_NETSPA
0.01UF CERM HOLE-VIA-P5RP25 HOLE-VIA-P5RP25 129 127
JC900 129 SATA_TXD_N1_C 1 2
402
SATA_TXD_N1
1 1 129 127 UATA_HSTROBE UATA_HOST UATA_NETPH UATA_NETSPA
EP00-081-91 127 129
129 127 UATA_STOP UATA_HOST UATA_NETPH UATA_NETSPA
M-ST-SM
10% CC907 GV904 129 127 UATA_DMACK_L UATA_HOST_R UATA_NETPH UATA_NETSPA
D
1
2 129 SATA_RXD_N1
16V
CERM
402
0.01UF
1 2 SATA_RXD_N1_C 127 129
GV903
HOLE-VIA-P5RP25
HOLE-VIA-P5RP25
1
129 127 UATA_RESET_L UATA_RESET_L UATA_NETPH UATA_NETSPA D
3
1 129 UATA_DSTROBE_R UATA_DEV_R_C UATA_NETPH UATA_NETSPA
y
10% 129 UATA_DMARQ_R UATA_DEV_R UATA_NETPH UATA_NETSPA
4
CC908 16V
CERM
GV905 GV906 UATA_INTRQ_R UATA_DEV_R UATA_NETPH UATA_NETSPA
5 0.01UF 402 HOLE-VIA-P5RP25 129
HOLE-VIA-P5RP25 1
6 129 SATA_RXD_P1 1 2 SATA_RXD_P1_C 127 129 1
7 UATA FROM RPAKS TO JC901
10% 127 UATA_DD_R<15..8> UATA_NETPH UATA_NETSPA
16V GV907 GV908 I392
r
CERM UATA_DD_R<7> UATA_NETPH UATA_NETSPA
518S0251 402 HOLE-VIA-P5RP25 HOLE-VIA-P5RP25 127 I393
1 1 127 UATA_DD_R<6..0> UATA_NETPH UATA_NETSPA I394
127 UATA_DA_R<2..0> UATA_NETPH UATA_NETSPA I395
127 UATA_CS0_L_R UATA_NETPH UATA_NETSPA
GV909 GV910 UATA_CS1_L_R UATA_NETPH UATA_NETSPA
I396
HOLE-VIA-P5RP25 HOLE-VIA-P5RP25 127 I397
SATA PORT1 IS NOT USED IN M23/M33:NO TEST 1 1 127 UATA_HSTROBE_R UATA_NETPH UATA_NETSPA I398
UATA_NETPH UATA_NETSPA
a
127 UATA_STOP_R I399
SATA_TXD_P2 NC_SATA_TXD_P2 GV911 GV912 UATA_DMACK_L_R
UATA_NETPH UATA_NETSPA
127
MAKE_BASE=TRUE
6
HOLE-VIA-P5RP25 HOLE-VIA-P5RP25 127 I400
1 1 UATA_NETPH UATA_NETSPA
127 UATA_RESET_L_R I401
127 SATA_TXD_N2 NC_SATA_TXD_N2 6 UATA_NETPH UATA_NETSPA
MAKE_BASE=TRUE GV913 GV914 129 127 UATA_DSTROBE I402
HOLE-VIA-P5RP25 HOLE-VIA-P5RP25 UATA_NETPH UATA_NETSPA
1 1 129 127 UATA_DMARQ I403
SATA_RXD_N2_C NC_SATA_RXD_N2_C
n
127 6 UATA_NETPH UATA_NETSPA
MAKE_BASE=TRUE 129 127 UATA_INTRQ
GV915 GV916 I404
HOLE-VIA-P5RP25 HOLE-VIA-P5RP25
1 1
127 SAT
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