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012 k62 - MLB - 051-8442 - 10.1.0

The document contains technical specifications and a table of contents for a hardware design, detailing resistance, capacitance, and oscillator values. It includes various sections related to system architecture, power management, and component connections. The last modification date is noted as February 8, 2011.

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0% found this document useful (0 votes)

39 views101 pages

012 k62 - MLB - 051-8442 - 10.1.0

Uploaded by

iago.lorenzo

We take content rights seriously. If you suspect this is your content, claim it here.

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Download as PDF, TXT or read online on Scribd

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8 7 6 5 4 3 2 1

CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION

K62 MLB
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2011-02-08

LAST_MODIFIED=Tue Feb 8 15:20:30 2011

(.csa) Date (.csa) Date

D Page
TABLE_TABLEOFCONTENTS_HEAD
Contents Sync Page
TABLE_TABLEOFCONTENTS_HEAD
Contents Sync D
1 05/21/2009 52 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
1 Table of Contents K60
TABLE_TABLEOFCONTENTS_ITEM
49 SMBUS CONNECTIONS K62_MARK
2 01/09/2011 53 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
2 System Block Diagram K62_SIJI
TABLE_TABLEOFCONTENTS_ITEM
50 CPU/PCH/GPU POWER SENSE K62_MARK
3 01/09/2011 54 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
3 Power Block Diagram K62_JERRY
TABLE_TABLEOFCONTENTS_ITEM
51 HDD OOB SENSE K62_MARK
4 N/A 55 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
4 BOM Configuration K62_AARON
TABLE_TABLEOFCONTENTS_ITEM
52 TEMP SENSORS K62_MARK
5 07/01/2009 56 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
5 DEBUG LEDS K62_AARON
TABLE_TABLEOFCONTENTS_ITEM
53 HD AND OD FAN K62_JERRY
6 12/30/2010 57 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
6 Power Conn / Alias K62_AARON
TABLE_TABLEOFCONTENTS_ITEM
54 CPU FAN K62_JERRY
7 11/30/2009 61 11/30/2009

TABLE_TABLEOFCONTENTS_ITEM
7 Holes K62_AARON
TABLE_TABLEOFCONTENTS_ITEM
55 SPI ROM K62_AARON
8 01/09/2011 62 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
8 UNUSED SIGNAL ALIAS K62_SIJI
TABLE_TABLEOFCONTENTS_ITEM
56 AUDIO: CODEC/REGULATOR K62_DAVID
9 09/11/2010 63 01/09/2011
9 Signal Aliases K62_SIJI 57 AUDIO: FILTER/BUFFER K62_DAVID

m
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

10 01/09/2011 64 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
10 CPU DMI/PEG/FDI/RSVD K62_ROSITA
TABLE_TABLEOFCONTENTS_ITEM
58 AUDIO: SPEAKER AMP_1 K62_DAVID
11 01/09/2011 65 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
11 CPU CLOCK/MISC/JTAG K62_ROSITA
TABLE_TABLEOFCONTENTS_ITEM
59 AUDIO: SPEAKER AMP K62_DAVID
12 01/09/2011 66 01/09/2011
12 CPU DDR3 INTERFACES 60 Audio: MLB to I/O Conn.

co
K62_ROSITA K62_DAVID
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

13 01/09/2011 67 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
13 CPU POWER K62_ROSITA
TABLE_TABLEOFCONTENTS_ITEM
61 AUDIO: Detects/Grounding K62_DAVID
14 01/09/2011 68 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
14 CPU GROUNDS K62_ROSITA
TABLE_TABLEOFCONTENTS_ITEM
62 AUDIO: Mikey K62_DAVID
15 01/09/2011 69 01/09/2011
15 STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU K62_SIJI 63 POWER SEQUENCING ENABLES K62_SIJI

s.
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

16 N/A 70 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
16 CPU NON-GFX DECOUPLING K62_AARON
TABLE_TABLEOFCONTENTS_ITEM
64 POWER SEQUENCING PGOOD K62_SIJI
17 11/30/2009 71 N/A
17 GFX DECOUPLING & PCH PWR ALIAS 65 VREG: PPVCORE_S0_CPU
C
K62_AARON K62_AARON
C

ic
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

18 01/09/2011 72 N/A

TABLE_TABLEOFCONTENTS_ITEM
18 PCH SATA/PCIE/CLK/LPC/SPI K62_SIJI
TABLE_TABLEOFCONTENTS_ITEM
66 VREG: CPU CORE - PHASES 1-3 K62_AARON
19 01/09/2011 73 N/A

TABLE_TABLEOFCONTENTS_ITEM
19 PCH DMI/FDI/GRAPHICS K62_SIJI
TABLE_TABLEOFCONTENTS_ITEM
67 VREG:AXG PHASE/CORE - CAPS K62_AARON
20 01/09/2011 74 12/08/2009

at
TABLE_TABLEOFCONTENTS_ITEM
20 PCH PCI/FLASHCACHE/USB K62_SIJI
TABLE_TABLEOFCONTENTS_ITEM
68 1V05 REGULATOR K62_AARON
21 01/09/2011 75 12/08/2009

TABLE_TABLEOFCONTENTS_ITEM
21 PCH MISC K62_SIJI
TABLE_TABLEOFCONTENTS_ITEM
69 CPU VCCSA REGULATOR K62_AARON
22 07/01/2009 76 12/08/2009
22 PCH POWER K60_SIJI 70 CPU 3P/4P BOM OPTIONS K62_AARON

em
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

23 07/01/2009 77 12/08/2009

TABLE_TABLEOFCONTENTS_ITEM
23 PCH GROUNDS K62_AARON
TABLE_TABLEOFCONTENTS_ITEM
71 5V_S3 / 3V3_S5 VREGS K62_AARON
24 07/01/2009 78 11/30/2009

TABLE_TABLEOFCONTENTS_ITEM
24 PCH DECOUPLING K62_AARON
TABLE_TABLEOFCONTENTS_ITEM
72 1.5V / 1.8V VREGS K62_AARON
25 01/09/2011 79 N/A

TABLE_TABLEOFCONTENTS_ITEM
25 CPU & PCH XDP K62_SIJI
TABLE_TABLEOFCONTENTS_ITEM
73 3.42 G3HOT SUPPLY K62_AARON
26 01/09/2011 80 04/07/2010
26 CLOCK (CK505) K62_ROSITA 74 S3+S0 FETS K62_AARON

ch
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

28 01/09/2011 81 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
27 CHIPSET SUPPORT K62_SIJI
TABLE_TABLEOFCONTENTS_ITEM
75 12V_S0 & 12V_S5 switch K62_JERRY
29 01/09/2011 84 N/A

TABLE_TABLEOFCONTENTS_ITEM
28 DDR3 VREF MARGINING K62_ROSITA
TABLE_TABLEOFCONTENTS_ITEM
76 MXM PCIe, DP & Power K62_AARON
30 01/09/2011 85 N/A
29 MEMORY CAPS K62_ROSITA 77 MXM I/O K62_AARON

kS
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

31 01/09/2011 86 N/A

TABLE_TABLEOFCONTENTS_ITEM
30 DDR3 SO-DIMM 0 & 2 K62_ROSITA
TABLE_TABLEOFCONTENTS_ITEM
78 MXM PCIE CAPS K62
32 01/09/2011 87 N/A

TABLE_TABLEOFCONTENTS_ITEM
31 DDR3 SO-DIMM 1 & 3 K62_ROSITA
TABLE_TABLEOFCONTENTS_ITEM
79 DP ALIAS K62_AARON
33 01/09/2011 88 N/A

TABLE_TABLEOFCONTENTS_ITEM
32 DDR3 SUPPORT AND BITSWAPS K62_ROSITA
TABLE_TABLEOFCONTENTS_ITEM
80 GREEN CLOCK K62_AARON
34 07/16/2009 89 (MASTER)
33 PCI-E Wireless Connector K62_AARON 81 T29 POWER K62_AARON

oo
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

35 11/14/2010 90 N/A

TABLE_TABLEOFCONTENTS_ITEM
34 USB HUB 1 K62_SIJI
TABLE_TABLEOFCONTENTS_ITEM
82 Display: Int DP Connector K62_AARON
36 11/14/2010 91 N/A
B TABLE_TABLEOFCONTENTS_ITEM
35
38
USB HUB 2 K62_SIJI
01/09/2011
TABLE_TABLEOFCONTENTS_ITEM
83
92
2V9/3V3/12V POWER SWITCH K62_AARON
N/A
B
36 CAESAR IV SUPPORT K62_MARK 84 Internal DP MUXing K62_AARON
TABLE_TABLEOFCONTENTS_ITEM

39
eb 01/09/2011 TABLE_TABLEOFCONTENTS_ITEM

93 (MASTER)

TABLE_TABLEOFCONTENTS_ITEM
37 ETHERNET PHY (CAESAR IV) K62_MARK
TABLE_TABLEOFCONTENTS_ITEM
85 DisplayPort/T29 A MUXing (MASTER)
40 01/09/2011 94 (MASTER)

TABLE_TABLEOFCONTENTS_ITEM
38 Ethernet Connector K62_MARK
TABLE_TABLEOFCONTENTS_ITEM
86 DisplayPort/T29 A Connector (MASTER)
41 01/09/2011 95 (MASTER)

TABLE_TABLEOFCONTENTS_ITEM
39 FireWire LLC/PHY (FW643) K62_ROSITA
TABLE_TABLEOFCONTENTS_ITEM
87 DisplayPort/T29 B MUXing (MASTER)
42 01/09/2011 96 (MASTER)
40 88
ot
FireWire: 1394B MISC K62_ROSITA DisplayPort/T29 B Connector (MASTER)
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

43 01/09/2011 97 (MASTER)

TABLE_TABLEOFCONTENTS_ITEM
41 FIREWIRE CONNECTOR K62_ROSITA
TABLE_TABLEOFCONTENTS_ITEM
89 T29 Host (1 of 2) (MASTER)
45 01/09/2011 98 (MASTER)
42 SATA Connectors K62_JERRY 90 T29 Host (2 of 2) (MASTER)
N

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

46 01/09/2011 100 06/08/2010

TABLE_TABLEOFCONTENTS_ITEM
43 EXTERNAL USB CONNECTORS K62_JERRY
TABLE_TABLEOFCONTENTS_ITEM
91 K60/K62 RULE DEFINITIONS K62_AARON
47 01/09/2011 101 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
44 Internal USB Connections K62_JERRY
TABLE_TABLEOFCONTENTS_ITEM
92 Memory Constraints K62_ROSITA
48 01/09/2011 102 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
45 SD READER CONNECTOR K62_MARK
TABLE_TABLEOFCONTENTS_ITEM
93 PCIE/DMI/FDI/SATA CONSTRAINTS K62_ROSITA
49 01/09/2011 103 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
46 SMC K62_JERRY
TABLE_TABLEOFCONTENTS_ITEM
94 IBEX PEAK CONSTRAINTS K62_SIJI
50 01/09/2011 104 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
47 SMC Support K62_JERRY
TABLE_TABLEOFCONTENTS_ITEM
95 USB/ENET/SD/FW/AUD CONSTRAINTS K62_MARK
51 11/30/2009 105 06/11/2010

TABLE_TABLEOFCONTENTS_ITEM
48 LPC+SPI Debug Connector K62_AARON
TABLE_TABLEOFCONTENTS_ITEM
96 GRAPHICS CONSTRAINTS K62_AARON
106 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
97 SMC Constraints K62_JERRY
107 01/09/2011

TABLE_TABLEOFCONTENTS_ITEM
98 POWER CONSTRAINTS K62_JERRY
108 06/11/2010

TABLE_TABLEOFCONTENTS_ITEM
99 T29 CONSTRAINTS K62_AARON
109 01/09/2011

A 100 PM RESETS ENABLES PGOOD CONST

TABLE_TABLEOFCONTENTS_ITEM

101
110
K60/K62 ICT/FCT
K62_JERRY

K62_AARON
N/A
DRAWING TITLE
A
TABLE_TABLEOFCONTENTS_ITEM

SCH,K62,MLB
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

INTERNAL DISP X4 DP X4 DP PG 84
DDR3 1333 CHB
J3200, J3200
J9002 PG 90
X4 DP X4 DP SO-DIMMS POWER SUPPLY
LGA1155 - SANDY BRIDGE PG 32
T29 LANES TEMP, CURRENT SENSE
T29 LANES
DP LANES TO INT MUX
T29 ROUTER J2500
XDP CONN
DISPLAY PORT CONN PG 25
TEMP SENSORS
J9600 PG 96 X4 DMI

D MIDBUS PROBE
MXM - GPU DIE
CPU HEATSINK
D
GPU HEATSINK
AMBIENT INTAKE
PG 13
CPU DIE-PECI
HARD DRIVE (OOB)
LCD TEMP
XDP
FDI INTERFACE DMI INTERFACE U2510 LEFT SKIN TEMP
GPIOs INTERFACE XDP CONN
PG 25 RIGHT SKIN TEMP
OPTICAL DRIVE

PG 19 PG 19 PG 19 PG 55

J4700

25MHZ
ALS
U8800 Misc PG 47
TO ENET 25MHZ GREEN CLK 25MHZ CLK

m
PG 88 PG 19 U6100 J5600, J5601, J5700
SYNTH
FAN CONN AND CONTROL
SPI PG 56,57
Boot ROM
PG 61
PG 18 SPI J5100

co
LPC+SPI CONN

SATA-A0
J4510
SATA CONN SATA 3.0 6GHZ. Port80,serial
HDD
PG 51
PG 45 PG 18
INTEL U4900

SATA-A1
J4520

s.
B,0 BSB ADC Fan
SATA CONN
SSD
SATA 3.0 6GHZ.
SATA COUGAR POINT SMC Ser
6 SATA 2.O PORTS Prt
PG 45 LPC
C PG 49
C

ic
J4530

SATA-A2
SATA CONN
ODD
SATA 2.0 3GHZ.
U1800
PG 45

at
PG 18
PG 18

ANALOG VIDEO OUTPUT

RGB OUT
PWR
(PORT A)

em
DIGITAL VIDEO OUTPUT
CTRL
HDMI/DVI/DP
(PORT B)

0 1 2 3 4 5 6 7 8 9 10 11 12 13
PG 20
J4700
DIGITAL VIDEO OUTPUT USB CAMERA
PG 47
HDMI/DVI/DP
(PORT C)

DIGITAL VIDEO OUTPUT

ch
HDMI/DVI/DP
J4630
(PORT D)
U3600 EXTD

(UP TO 14 DEVICES)
PG 46
PG 19
J4610
USB HUB2 EXTB

USB 2.0
PG 46
X4 PCIE GEN2 LANES 5GBIT/S

kS
PG 36
J4700
J3900 T3900
BLUETOOTH
PG 47
U3800
UP TO 8 LANES3
PCI-E GEN2

J4620
GB E-NET U3500 EXTC PG 46
E-NET E-NET X1 PCIE GEN1 LANE 2.5GBIT/S
CONTROLLER
CONNECTOR MAGNETICS J4600
EXTA

oo
AND PHY PG 46
USB HUB1 J4780
PG 39 PG 39 PG 38 IR
B PG 35
PG 47
J47XX
SD CONNECTOR
B
X1 PCIE GEN1 LANE 2.5GBIT/S SMB PG 47
DIMM’S, MIKEY, BLC
X1 PCIE GEN1 LANE 2.5GBIT/S
eb
MIKEY
J4800
PG 18
PG 18

SD CARD PCI HDA

(SUPPORTED UPTO 4 REQ/GNT)
PG 20 PG 18
ot
PG 48
N

U4100
U6201
Audio
FW643 Codec
PG 41

HEADPHONES
INTERNAL/EXTERNAL
MICROPHONES SPEAKER AMPS
LINE INPUT
A U6400, U6500
SYNC_MASTER=K62_SIJI SYNC_DATE=01/09/2011 A
PAGE TITLE

System Block Diagram

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

J4300 J3400 Audio REVISION
R

FireWire Mini PCI-E Conns 10.1.0

J6600,J6601,J6602,J6603
NOTICE OF PROPRIETARY PROPERTY: BRANCH
Conn AirPort THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
PG 43 PG 34 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
K75F AC/DC POWER SUPPLY (SPEC:310W)
TEMP SENSOR I2C CLK,DATA
12V_G3H EMC1403
INA219
SPEC:22.5A(270W)
12V LED POWER

m
PP12V_S5_LED 7.5A
(PS_ON) SPEC:7.5A (90W)

co
PP12V_S0:PEAK 26.5A(318W)
LCD PANEL 1.6A
PP12V_S0_FWR 1.2A
PP12V_S0_HDD 1.2A
AUDIO 1.7A

s.
PM_SLP_S3 FANS 0.75A
MXM 7.13A (95W TDP)
C PP12V_G3H: PP3V42_G3H_REG SMC PP3V3_S5_AVREF_SMC SMC VREF C

ic
SW LT3470A LDO SN0903048
PAGE 79 PAGE 50 PPVCORE/AXG CORE 112A

at
.65-1.5V @ 112A/55A VAXG 15A
PM_SMC_G2_EN
PM_EN_USB_PWR SWreg ISL6364
PP12V_S5:PEAK 9.8A(118W)

em
PP5V_USB_PORTx USB EXT PORT 4.7A PAGE 71-73
PP5V_S3_REG TPS2560 PAGE 46
ISL62383 5V@10.3A USB_IR
PAGE 77 USB_CAMERA PP1V05_S0 CPU VCCIO 8.5A (CPU)
1V05 VCCIO 5A (PCH)

ch
1.05V @ 25A
P5VS0_EN PP5V_S0 AUDIO
PCH SWReg ISL9563A 1V05 T29 3A
MXM 2.5A PAGE 76
FET 7A/2.7A HDD 1.8A
SSD 0.8A

kS
PAGE 80 ODD_PWR_EN_L
PP3V3_S5_REG
ISL62383 3.3V@6.2A ODD 1.5A
PCH PPVCCSA 8.8A
PAGE 77 BOOT ROM LDO 0.925V@8.8A
VCCSA
CPU PLL

oo
PP1V8_S0_REG
SWReg ISL8013A 1A PAGE 76
B PAGE 78 B
P3V3S3_EN
PP12V_T29
eb SMSC HUB X2, BT
PP3V3_S3 PP12V_T29 1.1A@12V (1ST PORT)
PM_SLP_S3_L & AP_PWR_EN 12V @ 1.2A
FET 2.9A/1.2A
PP3V3_S3_MINI AIRPORT FET 0.5A@3.3V (2ND PORT#1)
PAGE 80
FET 2.75A/1.1A/0.19A PAGE 91
ot
PAGE 34
ENET_PWR_EN

PP3V3_S3_ENET ETHERNET
N

FET 0.25A/0.2A/0.06A
P3V3S0_EN
FIREWIRE PAGE 38
PP3V3_S0 LCD PANEL
PCH FW
FET 2.7A/1.76A AUDIO PP1V0_FWPHY
MXM 1A MAX BJT 1.0V @ 0.08A
PAGE 80 PAGE 42
DP_RDRV 0.7/0.02A
PP3V3_S0_SD SDHC(0.25AMP)
PP1V5_S3_REG LAZARUS ( 0.1AMP)
TPS51116, 1.5V 11A/6.7A
PAGE 48
PAGE 78 MAIN MEMORY
A SYNC_MASTER=K62_JERRY SYNC_DATE=01/09/2011 A
PAGE TITLE
PM_SLP_S3 Power Block Diagram
DRAWING NUMBER SIZE
CPU MEM
PP1V5_S0 AUDIO Apple Inc. 051-8442 D
FET 6.2A/3A REVISION
R
PAGE 78 10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

PP0V75_S0 THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
0.75V @ 0.6A MEM_VTT
PAGE 75
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 3 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BOM Variants COMMON TABLE_5_HEAD

TABLE_BOMGROUP_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
BOM NUMBER BOM NAME BOM OPTIONS TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
337S4088 1 IC,COUGAR POINT,SLJ4F,BD82Z68,PRQ,B3 U1800 CRITICAL

D 085-1226 PCBA,MLB,DEV,K62 DEVELOPMENT,DEV_GROUP

TABLE_BOMGROUP_ITEM
353S3055 2 IC,PI3VEDP212,X2 DP MUX,QFN U9390,U9590 CRITICAL
TABLE_5_ITEM

D
639-1769 PCBA,MLB,K62,2.8G,4C,PRQ,P2_ODD K62,2P8GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P2,YES_DBG TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
338S0753 1 IC,FW643,1394B_PCIE,PHY/LINK U4100 CRITICAL
639-1770 PCBA,MLB,K62,3.1G,4C,PRQ,P2_ODD K62,3P1GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P2,YES_DBG TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
825-7122 1 MLB LABEL,48.0X4.8 X14 CRITICAL
639-1771 PCBA,MLB,K62,3.4G,4C,PRQ,P2_ODD K62,3P4GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P2,YES_DBG TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
343S0534 1 IC,BCM57765,ENET&SD,8X8 U3900 CRITICAL
639-2186 PCBA,MLB,K62,2.8G,4C,PRQ,P2_ODD,NO_DBG K62,2P8GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P2,NO_DBG TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
RAW: 335S0807 341T0184 1 FLASH,EFI BOOTROM,K60/K62 U6100 CRITICAL
639-2187 PCBA,MLB,K62,3.1G,4C,PRQ,P2_ODD,NO_DBG K62,3P1GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P2,NO_DBG TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
RAW: 335S0539 341T0328 1 SFLASH ENET 2MBIT,CIV U3990 CRITICAL
639-2188 PCBA,MLB,K62,3.4G,4C,PRQ,P2_ODD,NO_DBG K62,3P4GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P2,NO_DBG TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
338S0945 1 T29 ROUTER, IC, ASSP U9700 CRITICAL T29
639-2124 PCBA,MLB,K62,2.8G,4C,PRQ,P1_ODD K62,2P8GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P1,YES_DBG TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
RAW: 335S0550 341T0329 1 IC,T29 SERIAL EEPROM U9790 CRITICAL T29
639-2121 PCBA,MLB,K62,3.1G,4C,PRQ,P1_ODD K62,3P1GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P1,YES_DBG TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
RAW: 337S3997 341T0327 2 IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25 U9330,U9530 CRITICAL T29
639-2123 PCBA,MLB,K62,3.4G,4C,PRQ,P1_ODD K62,3P4GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P1,YES_DBG TABLE_5_ITEM

TABLE_BOMGROUP_ITEM
RAW: 338S0878 341T0186 1 IC,SMC,K62 U4900 CRITICAL

m
639-2129 PCBA,MLB,K62,2.8G,4C,PRQ,P1_ODD,NO_DBG K62,2P8GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P1,NO_DBG
TABLE_BOMGROUP_ITEM

639-2131 PCBA,MLB,K62,3.1G,4C,PRQ,P1_ODD,NO_DBG K62,3P1GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P1,NO_DBG

TABLE_BOMGROUP_ITEM

639-2130 PCBA,MLB,K62,3.4G,4C,PRQ,P1_ODD,NO_DBG K62,3P4GHZ_SNB_CPU,BASIC1,BASIC2,CPUVCORE-4PH,ODD_SATA:P1,NO_DBG

co
BOM GROUPS

s.
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM
CPUS TABLE_5_HEAD

BASIC1 COMMON,ALTERNATE,MXM,FCIM,CPU_1V5_SENSE,CPU_VCCSA_SENSE,1V05_PCH_SENSE PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

C C

ic
TABLE_BOMGROUP_ITEM TABLE_5_ITEM

BASIC2 HUB_USX2061,AP,BT,IR,T29,VAXG,PRODUCTION 337S4042 1 SNB,SR00D,PRQ,D2,2.8,95W,4+1,6M,LGA CPU CRITICAL 2P8GHZ_SNB_CPU

TABLE_BOMGROUP_ITEM TABLE_5_ITEM

DEV_GROUP VREFMRGN_A,VREFMRGN_B,DIMM_1V5_SENSE 337S4040 1 SNB,SR00Q,PRQ,D2,3.1,95W,4+1,6M,LGA CPU CRITICAL 3P1GHZ_SNB_CPU

TABLE_BOMGROUP_ITEM TABLE_5_ITEM

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YES_DBG XDP,XDP_CONN,XDP_CPU_BPM,MOJOMUX:YES,LPCPLUS:YES 337S4041 1 SNB,SR00B,PRQ,D2,3.4,95W,4+1,8M,LGA CPU CRITICAL 3P4GHZ_SNB_CPU
TABLE_BOMGROUP_ITEM

NO_DBG MOJOMUX:NO,LPCPLUS:NO

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K62 PARTS TABLE_5_HEAD

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PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

CPU SOCKET & ILM SUB-BOMS TABLE_5_HEAD

051-8442 1 SCH,MLB,K62 SCH1 K62
TABLE_5_ITEM

TABLE_5_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 820-2828 1 PCBF,MLB,K62 MLB1 K62
TABLE_5_ITEM

511S0071 1 SOCKET,LGA1155,CPU-LF U1000 CRITICAL TYCO_SOCKET

kS
TABLE_5_ITEM

604-1474 1 ASSY,PURCHASED,ILM,TYCO ILM CRITICAL TYCO_SOCKET

TABLE_5_ITEM

511S0073 1 SOCKET,LGA1155,CPU-LF U1000 CRITICAL MOLEX_SOCKET

TABLE_5_ITEM

604-1161 1 ASSY,PURCHASED,ILM,MOLEX ILM CRITICAL MOLEX_SOCKET

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B TABLE_BOMGROUP_HEAD
K62 ALTERNATE PARTS B
BOM NUMBER BOM NAME BOM OPTIONS TABLE_ALT_HEAD

TABLE_BOMGROUP_ITEM
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
085-2451 SUB ASSY,CPU SOCKET,K62,TYCO TYCO_SOCKET
eb TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

085-2450 SUB ASSY,CPU SOCKET,K62,MOLEX MOLEX_SOCKET 128S0298 128S0293 ALL 330UF

TABLE_ALT_ITEM

371S0679 371S0652 ALL PIN DIODE

TABLE_ALT_ITEM

TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 377S0107 377S0066 ALL USB DIODE
ot
TABLE_ALT_ITEM

TABLE_5_ITEM

085-2451 1 TYCO CPU SOCKET AND ILM SKT_ILM CRITICAL 376S0972 376S0612 ALL ROHM TRA-BJT

TABLE_ALT_HEAD
N

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_ALT_ITEM

085-2450 085-2451 SKT_ILM MOLEX ALTERNATE

BOARD STACK-UP
TOP SIGNAL
2 GROUND
A 3 SIGNAL SYNC_MASTER=K62_AARON SYNC_DATE=N/A A
PAGE TITLE
4 POWER BOM Configuration
5 POWER DRAWING NUMBER
051-8442
SIZE
D
Apple Inc.
6 SIGNAL R
REVISION
10.1.0
7 GROUND NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

BOTTOM SIGNAL THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
PAGE
4 OF 110
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 4 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

S5 Led ALL_SYS_PWRGD Led MXM PWR GOOD Led VIDEO ON Led

=PP3V3_S0_LED
D =PP3V3_S3_LED
6 5
6 5 =PP3V3_S0_LED
D
6 5

1
R502
1
R503
1K
R504
1

5% 1K
1K 1/16W 5%
5% MF-LF 1/16W
1/16W MF-LF
MF-LF 2 402 2 402
6 5 =PP3V3_S5_LED 2 402 GPU_PRESENT_R
CORE_VOLTAGES_ON_R LCD_SHOULD_ON_R
1
R501
1K
A
A

LED503
5%
1/16W
LED502
GREEN-3.6MCD
GREEN-3.6MCD
2.0X1.25MM-SM
MF-LF K
2.0X1.25MM-SM SILKSCREEN:3 A
2 402 K
SILKSCREEN:2
ITS_PLUGGED_IN
CORE_VOLTAGES_ON
GPU_PRESENT_DRAIN
LED504
GREEN-3.6MCD
A
6 K 2.0X1.25MM-SM
SILKSCREEN:4
LED501 3
D
GREEN-3.6MCD
2.0X1.25MM-SM D Q502

m
K
SILKSCREEN:1 Q502 2
2N7002DW-X-G VIDEO_ON_L
2N7002DW-X-G 100 25 21 IN MXM_GOOD G S SOT-363 IN 82

100 64 32 IN ALL_SYS_PWRGD_R 5 G S SOT-363

1
4

co
s.
C C

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at
PROTO DEBUG LEDS ARE SHOWN BELOW

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ch
6 5 =PP3V3_S5_LED
DEVELOPMENT 6 5 =PP3V3_S5_LED 6 5 =PP3V3_S0_LED
6 5 =PP3V3_S0_LED DEVELOPMENT DEVELOPMENT
1
R510 DEVELOPMENT 1 1

kS
3.3K 1
R540 R500 R549
5% 3.3K 3.3K
1/16W 3.3K 5% 5%
MF-LF 5% 1/16W 1/16W
2 402 1/16W
MF-LF
MF-LF MF-LF
PM_LED_S3 2 402 2 402
2 402 PM_LED_S4 PM_LED_AXG
PM_LED_PCHCORE
A DEVELOPMENT DEVELOPMENT

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A A DEVELOPMENT
SILK_PART=SLP_S3 LED510 A DEVELOPMENT
GREEN-3.6MCD SILK_PART=SLP_S4 LED500 SILK_PART=VAXG_PGOOD LED542
2.0X1.25MM-SM
SILK_PART=PCHCORE_PGOOD LED540 GREEN-3.6MCD GREEN-3.6MCD

B K
SILKSCREEN:5
PM_LED1_S3
K
GREEN-3.6MCD
2.0X1.25MM-SM
SILKSCREEN:6
K 2.0X1.25MM-SM
SILKSCREEN:7
K 2.0X1.25MM-SM
SILKSCREEN:11 B
PM_LED1_S4 PM_LED1_AXG
PM_LED1_PCHCORE
6
eb 3
DEVELOPMENT 6 3
D DEVELOPMENT
DEVELOPMENT DEVELOPMENT D
Q500 D D
2N7002DW-X-G Q520
100 63 47 46 36 32 26 19 PM_SLP_S3_L 2 G S SOT-363
Q540 Q500 2N7002DW-X-G
IN 2N7002DW-X-G 2N7002DW-X-G PM_PGOOD_PVAXG 5 G S
100 65 IN SOT-363
100 64 PGOOD_PCH_S0 2 G S SOT-363 100 63 47 46 32 19 PM_SLP_S4_L 5 G S SOT-363
IN IN
1
ot
4
1 4
N

6 5 =PP3V3_S3_LED
DEVELOPMENT
1
R505
1K
6 5 =PP3V3_S5_LED 6 5 =PP3V3_S5_LED 5%
DEVELOPMENT DEVELOPMENT 1/16W
1 6 5 =PP3V3_S0_LED 1 MF-LF
R560 DEVELOPMENT
1
R530 2 402
3.3K R550 3.3K ITS_ALIVE
5% 5%
1/16W 3.3K 1/16W A
MF-LF 5% MF-LF DEVELOPMENT
2 402 1/16W
MF-LF 2 402 LED505
PM_LED_S5 2 402
PM_LED_DDRREG GREEN-3.6MCD
DEVELOPMENT PM_LED_PVCORE K 2.0X1.25MM-SM
A A DEVELOPMENT
A SILKSCREEN:8
SILK_PART=SLP_S5 LED560 DEVELOPMENT LED530 SILK_PART=DDR_PGOOD
GREEN-3.6MCD
SILK_PART=VCORE_PGOOD LED550 GREEN-3.6MCD

A K 2.0X1.25MM-SM
SILKSCREEN:12
K
GREEN-3.6MCD
2.0X1.25MM-SM
K 2.0X1.25MM-SM
SILKSCREEN:10 SYNC_MASTER=K62_AARON SYNC_DATE=07/01/2009 A
PM_LED1_S5 SILKSCREEN:9 PM_LED1_DDRREG PAGE TITLE

3
PM_LED1_PVCORE
6
DEBUG LEDS
DEVELOPMENT DRAWING NUMBER SIZE
3
D
Q530 DEVELOPMENT
D DEVELOPMENT
Q520 Apple Inc. 051-8442 D
D
2N7002DW-X-G 2N7002DW-X-G REVISION
PM_SLP_S5_L 5 G Q540 PM_PGOOD_DDR1V5_S3_REG 2 G R
100 63 47 46 19 IN S SOT-363
5
2N7002DW-X-G
100 72 63 IN S SOT-363
10.1.0
100 65 64 25 IN PM_PGOOD_PVCORE_CPU G S SOT-363
NOTICE OF PROPRIETARY PROPERTY: BRANCH
4 1
1 C501 4 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
0.1UF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
20%
10V
2 CERM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
5 OF 110
402 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 5 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
98 PP0V75_S0 PPVTT_S0_DDR_LDO 72
MAKE_BASE=TRUE
VOLTAGE=0.75V
MIN_LINE_WIDTH=0.4 mm
=PP0V75_S0_MEM_VTT_S0FET 32 "S5" RAILS
POWER SUPPLY TO MLB PP12V_G3H_ACDC 6
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
ALWAYS ON WHEN UNIT HAS AC POWER AND IN S5

"S0" RAILS PP3V3_S5 PP3V3_S5_REG

518-0352 1 C614
1UF
10%
98 PPVTT_S0_DDR
MAKE_BASE=TRUE
VOLTAGE=0.75V
MIN_LINE_WIDTH=0.4 mm
PPVTT_S0_DDR_FET
=PP0V75_S0_MEM_VTT_B
32

31 ONLY ON IN RUN
98
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
=PP3V3_S5_PCH
=PP3V3_S5_PCH_GPIO
71

18 19 21 24

20
100 84 IN BL_PWM CRITICAL 2 25V
X5R MIN_NECK_WIDTH=0.2 mm =PP0V75_S0_MEM_VTT_A 30 NET_SPACING_TYPE=POWER
402 NET_SPACING_TYPE=POWER MAX_NECK_LENGTH=3 MM =PP3V3_S5_ROM 48 55
MAX_NECK_LENGTH=3 MM
1 C613
J600 =PP3V3_S5_PCH_VCCSUS3_3_USB 22 24
76833-0100 98 PPVCORE_S0_CPU PPVCORE_S0_CPU_REG 66 67 98 PP1V8_S0 PP1V8_S0_REG 72 =PP3V3_S5_PWRCTL 11 63 64
0.001UF M-RT-TH MAKE_BASE=TRUE MAKE_BASE=TRUE
10% VOLTAGE=1.1V =PPVCORE_S0_CPU 13 16 50 65 VOLTAGE=1.8V =PP3V3R1V8_S0_PCH_VCCDFTERM 22 24 =PP3V3_S5_S3FET 74
50V 1 8
2 X7R MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.5MM

D 402 2
3
9
10
PP12V_S0_PS 6
MIN_NECK_WIDTH=0.3MM
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V8_S0_CPU_PLL
24 80

13 16
=PP3V3_S5_S0FET
=PP3V3_S5_PCH_STRAPS
74

15
D
98 PPVAXG_S0 PPVAXG_S0_REG 67 =PP1V8_S0_PCH 19 =PP3V3_S5_XDP 25
4 11 MAKE_BASE=TRUE
R601 VOLTAGE=1.05V =PPVAXG_S0_CPU 13 17 50 65 =PP1V8_S0_PWRCTL 64 =PP3V3_S5_LPCPLUS 48
5 12 BL_EN 82 100 MIN_LINE_WIDTH=0.6MM
0 IN =PP3V3_S5_PCH_VCCDSW
6 13 MIN_NECK_WIDTH=0.3MM 22 24
49 BI =SMB_ACDC_SDA 1 2 SMB_ACDC_SDA_RC NET_SPACING_TYPE=POWER
1 C611 1 C612 MAX_NECK_LENGTH=3 MM 101 98 PP5V_S0 PP5V_S0_FET 74 =PP3V3_S5_USB_HUB 34
1/16W I2C_GND 7 14 SMB_ACDC_SCL_RC MAKE_BASE=TRUE
402 10UF 0.001UF 98 PP1V05_S0 PP1V05_S0_REG 68 VOLTAGE=5V =PP5V_S0_AUDIO 56 =PP3V3_S5_CPU_VCCSA 69
5% 10% 10% MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm
1 16V 50V
R609 2 X5R-CERM
1210
2 X7R
402
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5MM
=PP1V05_S0_PWR 50 MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=POWER
=PP5V_S0_SATA 42 =PP3V3_S5_PCH_VCCSPI 22 24

0 MIN_NECK_WIDTH=0.25MM =PPVCCIO_S0_XDP 25 MAX_NECK_LENGTH=3 MM =PP5V_S0_MXM 76 =PP3V3_S5_VRD 71

5% NET_SPACING_TYPE=POWER
1 C604 1/16W
MF-LF
MAX_NECK_LENGTH=3 MM =PPVCCIO_S0_CPU 10 11 13 16 65 =PP5V_S0_VRD 65 67 =PP3V3_S5_LED 5
47PF =PPVCCIO_S0_SMC =PP5V_S0_ISENSE =PP3V3_S5_MEMRESET
5% 2 402 46 47 50 32

2 50V
CERM
=PP1V05_S0_PCH_PWR 50 =PP5V_S0_PCH 24 =PP3V3_S5_RSTBUF 27
402 =PPVCCSA_S0_INPUT_PWR =PP5V_S0_P1V05_VREG =PP3V3_S5_SMCUSBMUX
50 69 68 43

PS_ON =PP1V05_S0_CK505 26 =PP5V_S0_LPCPLUS 48 =PP3V3_S5_P3V3R2V9_A 83

=PP5V_S0_P1V8_REG 72 =PP3V3_S5_P3V3R2V9_B 83
R611 98 PP1V05_S0_PCH PP1V05_S0_PCH_SNS 50
=PP3V3R1V5_S5_PCH_VCCSUSHDA

m
MAKE_BASE=TRUE 24
0 VOLTAGE=1.05V =PP1V05_S0_PCH_VCC_DMI 22 24
3
1 2 =SMB_ACDC_SCL IN 49 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm =PP1V05_S0_PCH_VCCADPLL 17
1/16W NET_SPACING_TYPE=POWER
D 1 C610 402 MAX_NECK_LENGTH=3 MM =PP1V05_S0_PCH_VCCIO_DMI 22 24
Q610 0.001UF 5%
=PP1V05_S0_PCH_VCCIO_SATA
2N7002 C605 18 22 24

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10% 1 98 PP5V_S5 PP5V_S5_LDO 71
PM_EN_P12V_S0_FET 1 G S SOT23-HF1 50V =PP1V05_S0_PCH_VCCIO_PCIE
100 63 IN 2 X7R 47PF 18 19 22 24 MAKE_BASE=TRUE
402 5% VOLTAGE=5V =PP5V_S5_PCH 24
50V =PP1V05_S0_PCH_VCC_CORE 22 24 MIN_LINE_WIDTH=0.4 MM
PLACE C610 CLOSE TO CONNECTOR 2 2 CERM MIN_NECK_WIDTH=0.2 mm
PLACE C613 CLOSE TO CONNECTOR 402
=PP1V05_S0_PCH_VCCIO_USB 22 24 98 PP12V_S0 PP12V_S0_PS 6 NET_SPACING_TYPE=POWER
PLACE C614 CLOSE TO CONNECTOR =PP1V05_S0_PCH
MAKE_BASE=TRUE
=PP12V_S0_AUDIO_SPKRAMP
MAX_NECK_LENGTH=3 MM
PLACE C612 CLOSE TO CONNECTOR 18 24 80 VOLTAGE=12V 58 59
MIN_LINE_WIDTH=1mm
=PP1V05_S0_PCH_VCCDIFFCLK =PP12V_S0_VRD

s.
22 24 MIN_NECK_WIDTH=0.5mm 65
NET_SPACING_TYPE=POWER 98 PP12V_S5 PP12V_S5_FET 75 98
=PP1V05_S0_PCH_VCCSSC 22 24 MAX_NECK_LENGTH=3 MM =PP12V_S0_MXM_PWR 50 MAKE_BASE=TRUE
VOLTAGE=12V =PP12V_S5_DDR_VREG 72
=PP1V05_S0_PCH_V_PROC_IO 22 24 =PP12V_S0_LCD 82 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm =PP12V_S5_P5VS3_VREG 71

C =PP1V05_S0_PCH_VCCASW 22 24 =PP12V_S0_P1V05_VREG 68 NET_SPACING_TYPE=POWER

=PP12V_S5_PWRCTL C

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MAX_NECK_LENGTH=3 MM 33 64 74
=PP1V05_S0_P1V05T29FET 81 =PP12V_S0_PWRCTL 63 64 81
=PP12V_S5_T29_A 83
=PP12V_S0_SENSE 51
98 PP1V05_S0_INPUT_VCCSA PPVCCSA_S0_INPUT_SNS 50 =PP12V_S5_T29_B 83
MAKE_BASE=TRUE =PP12V_S0_FW 41
VOLTAGE=1.05V =PPVCCIO_S0_CPU_VCCSA 69
"G3H" RAILS

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MIN_LINE_WIDTH=0.5MM =PP12V_S0_CPU_VCCSA 69
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=POWER =PP12V_S0_SATA 42 ALWAYS ON WHEN UNIT HAS AC POWER AND IN G3HOT PER SMC
MAX_NECK_LENGTH=3 MM
=PP12V_S0_FAN 53 54 G3H: ALIASES
MLB TO BLC 98 PPVCCSA_S0_CPU PPVCCSA_S0_FET 69

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MAKE_BASE=TRUE
NOSTUFF VOLTAGE=0.925V =PPVCCSA_S0_CPU 13 50 98 PP3V42_G3H PP3V42_G3H_REG 73
MIN_LINE_WIDTH=0.6MM MAKE_BASE=TRUE
1 C626 MIN_NECK_WIDTH=0.3MM =PPVCCSA_S0_PWRCTL 64 VOLTAGE=3.42V =PP3V3_G3H_RTC_D 27
NET_SPACING_TYPE=POWER MIN_LINE_WIDTH=0.6MM
47PF MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2MM =PP3V3_G3H_SMC 46 47
5% NET_SPACING_TYPE=POWER
50V
2 CERM 98 PP1V5_S0 PP1V5_S0_FET 74 MAX_NECK_LENGTH=3 MM =PP3V3_G3H_SMCUSBMUX 43
MAKE_BASE=TRUE
402 VOLTAGE=1.5V =PP1V5_S0_AUD_DIG 56 =PP3V3_G3H_LPCPLUS 48
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM =PP1V5_S0_CK505 26 98 PP12V_S0_MXM PP12V_S0_MXM_SNS 50
NET_SPACING_TYPE=POWER MAKE_BASE=TRUE

ch
MAX_NECK_LENGTH=3 MM =PP1V5_S0_MINI 33 VOLTAGE=12V
MIN_LINE_WIDTH=0.6MM =PP12V_S0_MXM 76
=PP1V5_S0_PWR 50 MIN_NECK_WIDTH=0.2MM
R631 =PP1V5_S0_DP
NET_SPACING_TYPE=POWER
0 84 MAX_NECK_LENGTH=3 MM
97 82 49 BI SMB_BLC_TCON_SDA R630 1 2 SMB_BLC_TCON_SDA_R
0 98 PP1V5_S0_CPU_MEM PP1V5_S0_CPU_MEM_SNS 50
97 82 49 IN SMB_BLC_TCON_SCL 1 2 1/16W SMB_BLC_TCON_SCL_R MAKE_BASE=TRUE 98 PP12V_G3H PP12V_G3H_ACDC 6
402 =PP1V5_S0_CPU_MEM
VOLTAGE=1.5V MAKE_BASE=TRUE

kS
1/16W 5% 11 13 16 28 29
402 MIN_LINE_WIDTH=0.4MM VOLTAGE=12V =PP12V_G3H_S5_FET 75
5% NOSTUFF MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6 mm
NET_SPACING_TYPE=POWER MIN_NECK_WIDTH=0.2 MM =PP12V_G3H_3V42 73
1 C616 MAX_NECK_LENGTH=3 MM
"S3" RAILS NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
47PF PP3V3_S0 PP3V3_S0_FET
5% 98 74 ON IN RUN AND SLEEP
50V MAKE_BASE=TRUE
2 CERM VOLTAGE=3.3V =PP3V3_S0_PCH 18 21 24
402 MIN_LINE_WIDTH=0.4MM
T29 RAILS

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MIN_NECK_WIDTH=0.2MM =PP3V3_S0_FAN 53 54
NET_SPACING_TYPE=POWER
=PP3V3_S0_SMBUS MAX_NECK_LENGTH=3 MM =PP3V3_S0_PCH_VCCADAC 17
49 6 PP1V5_S3 PP1V5_S3_REG
98 72
FET DIODE IS S TO D (FACES BLC WHICH CRITICAL =PPSPD_S0_MEM_A 30 47 MAKE_BASE=TRUE
B NOSTUFF
3V3 RISES BEFORE MLB 3V3).
2 J602 =PPSPD_S0_MEM_B 31
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
=PP1V5_S3_MEM_PWR
=PP1V5_S3_S0FET
50
B
Q600 53780-8608 =PP3V3_S0_AUDIO 56 58 59 60 61 62 NET_SPACING_TYPE=POWER
74

1 C607 G 2N7002DW-X-G F-RT-SM =PP3V3R1V5_S0_PCH_VCCSUSHDA

MAX_NECK_LENGTH=3 MM
47PF SOT-363 10
eb 24

5% 1 S D 6
=PP3V3_S0_SMBUS 6 49
50V
2 CERM =PP3V3_S0_SMC_LS 47 51 98 PP3V3_S0_T29 PP3V3_T29_FET 81
402 1 98 PP1V5_S3_MEM PP1V5_S3_MEM_SNS 50 MAKE_BASE=TRUE
NOSTUFF 2
=PP3V3_S0_SMBUS_SMC_0 49 MAKE_BASE=TRUE VOLTAGE=3.3V =PP3V3_T29_RTR 80 81 89 90
VOLTAGE=1.5V =PP1V5_S3_MEMRESET 32 MIN_LINE_WIDTH=0.6MM
=PP3V3_S0_SMBUS_SMC_B MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2MM
NOSTUFF R617 3 49
MIN_NECK_WIDTH=0.2 mm =PP1V5_S3_MEM_A 28 29 30 NET_SPACING_TYPE=POWER
0 =PP3V3_S0_SMBUS_SMC_MGMT
ot
R618 4 49 NET_SPACING_TYPE=POWER MAX_NECK_LENGTH=3 MM
49 BI =SMB_BLC_PCH_SDA 1 2 SMB_BLC_PCH_SDA_R MAX_NECK_LENGTH=3 MM =PP1V5_S3_MEM_B 28 29 31
0 5
=PP3V3_S0_MXM 21 64 76 77
49 IN =SMB_BLC_PCH_SCL 1 2 1/16W SMB_BLC_PCH_SCL_R
402
6
=PP3V3_S0_ODD 42 101 98 PP3V3_S3 PP3V3_S3_FET 74
1/16W 5% MAKE_BASE=TRUE 98 PP1V05_S0_T29 PP1V05_T29_FET 81
402
BLC SDA/SCL 7
=PP3V3_S0_SATALED 18 42 VOLTAGE=3.3V =PP3V3_S3_BT 44 MAKE_BASE=TRUE
5% MIN_LINE_WIDTH=0.4MM VOLTAGE=1.05V =PP1V05_T29_RTR 90
N

ISOLATION CIRCUIT 8
=PP3V3_S0_SENSE 50 52 MIN_NECK_WIDTH=0.2MM =PP3V3_S3_SMBUS_SMC_A 49 MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=POWER MIN_NECK_WIDTH=0.2MM =PP1V05_T29 81
NOSTUFF =PP3V3_S0_PWRCTL 63 64 74 81 MAX_NECK_LENGTH=3 MM =PP3V3_S3_MINI 33 NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
1 C606 5
Q600 9
=PP3V3_S0_PCH_VCC3_3_GPIO 22 24 =PP3V3_S3_PWRCTL 64 74 83
47PF G 2N7002DW-X-G =PP3V3_S0_FWPHY 39 40 41 =PP3V3_S3_MEMRESET 32
5%
50V SOT-363
2 CERM 518S0543 =PP3V3_S0_DP 82 =PP3V3_S3_USB_HUB 34 35
402 4 S D 3
=PP3V3_S0_PCH_VCC3_3_PCI 22 24 =PP3V3_S3_ENET_PHY 36
ISOLATED_GND
R619
0
1
R620
=PP3V3_S0_CK505 26 =PP3V3_S3_SDCARD 44 45 GND RAILS
BLC_GPIO 1 2 BLC_GPIO_R =PP3V3_S0_PCH_GPIO 20 45 =PP3V3_S3_VREFMRGN 28
94 21 15 IN 0 =PP3V3_S0_PCH_STRAPS =PP3V3_S3_VRD
1/16W 5% 15 72
402 1/16W
5% MF-LF =PP3V3_S0_PCH_VCC3_3_SATA 22 24 =PP3V3_S3_LED 5 GND
2 402 =PP3V3_S0_RSTBUF 11 27 =PP3V3_SW_DPAPWR 79
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
=PP3V3_S0_PCH_PM 27 =PP3V3_SW_DPBPWR 79 NET_SPACING_TYPE=GND
L602 =PP3V3_S0_SMBUS_SMC_BSA =PP3V3_S3_SYSCLK
MAKE_BASE=TRUE
FERR-1000-OHM 49 80 MAX_NECK_LENGTH=4.1 MM
=PP3V3_S0_SDCARD 45 =PP3V3_S3_P3V3R2V9_REG_A 83
100 82 VSYNC_DP_CONN 1 2 VSYNC_DP_CONN_R
IN =PP3V3_S0_P1V05_VREG =PP3V3_S3_P3V3R2V9_REG_B
A 0402
=PP3V3_S0_PCH_VCC3V3
68

22 24 =PP3V3_S3_PCH
83

21 SYNC_MASTER=K62_AARON SYNC_DATE=12/30/2010 A
=PP3V3_S0_VRD 65 68
PAGE TITLE
=PP3V3_S0_LED 5 101 98 PP5V_S3
MAKE_BASE=TRUE
PP5V_S3_REG 71 Power Conn / Alias
=PP3V3_S0_P3V3T29FET 81 VOLTAGE=5V =PP5V_S3_USB 43 DRAWING NUMBER SIZE
=PP3V3_S0_DPSDRVA 85
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM =PP5V_S3_S0FET 74
Apple Inc. 051-8442 D
=PP3V3_S0_DPSDRVB NET_SPACING_TYPE=POWER
87 MAX_NECK_LENGTH=3 MM =PP5V_S3_CAMERA 44 REVISION
R
=PP3V3_S0_INTDPMUX 84 =PP5V_S3_IR 44 10.1.0
=PP3V3_S0_T29PWRCTL 81 =PP5V_S3_MEMRESET 32 NOTICE OF PROPRIETARY PROPERTY: BRANCH
=PP3V3_S0_T29I2C 49 =PP5V_S3_DDR_VREG 72 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
=PP3V3_S0_ENET_PHY 36 37 =PP5V_S3_VREFMRGN 28 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
=PP5V_S3_P3V3R2V9_REG_A 83
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 110
=PP5V_S3_P3V3R2V9_REG_B 83 SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 6 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CPU Heatsink DIMM CONNECTOR NUTS

4mm Plated Holes (998-0850) Nuts (805-9582)
OMIT OMIT OMIT OMIT
ZH0700 ZH0701 ZH0702 ZH0703 CRITICAL CRITICAL CRITICAL CRITICAL
4P75R4 4P75R4 4P75R4 4P75R4 NUT0750 NUT0751 NUT0752 NUT0753
1 1 1 1 NUT-4.25OD1.4H-1.40-3.25-TH NUT-4.25OD1.4H-1.40-3.25-TH NUT-4.25OD1.4H-1.40-3.25-TH NUT-4.25OD1.4H-1.40-3.25-TH

D 1 1 1 1 D

PCH HEATSINK MTG HOLES (NON-PLATED HOLE ON PCB ONLY)

m
co
Rear Cover
STANDOFFS (WAS 860-1255 BUT NOW REPLACED WITH 860-1430)

s.
OMIT_TABLE
OMIT_TABLE CRITICAL OMIT_TABLE OMIT_TABLE OMIT_TABLE CRITICAL
OMIT_TABLE
CRITICAL SDF0714 CRITICAL CRITICAL SDF0718 CRITICAL
SDF0713 STDOFF-6.8OD15.0H-1.56-TH SDF0715 STDOFF-6.8OD15.0H-1.56-TH
SDF0717 SDF0719
C C

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STDOFF-6.8OD15.0H-1.56-TH 1 STDOFF-6.8OD15.0H-1.56-TH STDOFF-6.8OD15.0H-1.56-TH 1 STDOFF-6.8OD15.0H-1.56-TH
1 1 1 1

at
em
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_ITEM

860-1430 6 STANDOFF,MLB,K60/K62 SDF0713,SDF0714,SDF0715,SDF0717,SDF0718,SDF0719 COMMON

ch
kS
oo
Backer Plate
B B
Nuts (835-0269)
eb
CRITICAL CRITICAL CRITICAL CRITICAL
NUT0700 ZH0720 ZH0721 ZH0722
NUT-6.5OD1.4H-1.56-3.8-TH 5R3 5R3 5R3
1 1 1 1
ot
N

For EMC
EMC Spring (870-1577); Near DIMMs EMC POGO Pins (870-1698); Near DIMMs
NOSTUFF
CRITICAL SC0705 SC0706
2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98
A SC0702
SM SM SYNC_MASTER=K62_AARON SYNC_DATE=11/30/2009 A
1 EMI-SPRING 1 1 PAGE TITLE
CLIP-SM-K2
Holes
DRAWING NUMBER SIZE
CRITICAL CRITICAL
NOSTUFF NOSTUFF Apple Inc. 051-8442 D
REVISION
R
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
7 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 7 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
UNUSED CPU SIGNALS NC ON UNUSED PCIE ALIASES NC ON UNUSED DISPLAY ALIASES NC ON UNUSED FDI ALIASES
10 TP_CPU_RSVD<16..1> NC_CPU_RSVD<16..1>
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_CRT_IG_DDC_CLK NC_CRT_IG_DDC_CLK 10 TP_CPU_FDI_TX_N<7..0> NC_CPU_FDI_TXN<7..0>
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
10 TP_CPU_RSVD<46..19> NC_CPU_RSVD<46..19>
MAKE_BASE=TRUE NO_TEST=TRUE 10 TP_CPU_FDI_TX_P<7..0> NC_CPU_FDI_TXP<7..0>
19 TP_CRT_IG_DDC_DATA NC_CRT_IG_DDC_DATA MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_PCH_FDI_RX_N<7..0> NC_PCH_FDI_RXN<7..0>
MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_CRT_IG_RED NC_CRT_IG_RED 19 TP_PCH_FDI_RX_P<7..0> NC_PCH_FDI_RXP<7..0>
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_CRT_IG_GREEN NC_CRT_IG_GREEN
MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE5P
D 18 TP_PCIE_CLK100M_PE5N
MAKE_BASE=TRUE NO_TEST=TRUE
NC_PCIE_CLK100M_PE5N
19 TP_CRT_IG_BLUE NC_CRT_IG_BLUE
MAKE_BASE=TRUE NO_TEST=TRUE D
MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_CRT_IG_HSYNC NC_CRT_IG_HSYNC
MAKE_BASE=TRUE NO_TEST=TRUE
21 TP_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE6P
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_CRT_IG_VSYNC NC_CRT_IG_VSYNC
21 TP_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6N MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE

21 TP_PCIE_CLK100M_PE7P NC_PCIE_CLK100M_PE7P 19 TP_DP_IG_B_MLN<3..0> NC_DP_IG_B_MLN<3..0>

MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
21 TP_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7N 19 TP_DP_IG_B_MLP<3..0> NC_DP_IG_B_MLP<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_DP_IG_B_AUX_N NC_DP_IG_B_AUXN
10 TP_PE_RX_N<3..0> NC_PE_RXN<3..0> MAKE_BASE=TRUE NO_TEST=TRUE

10 TP_PE_RX_P<3..0>
MAKE_BASE=TRUE
NC_PE_RXP<3..0>
NO_TEST=TRUE 19 TP_DP_IG_B_AUX_P NC_DP_IG_B_AUXP
MAKE_BASE=TRUE NO_TEST=TRUE
NC ON UNUSED SATA ALIASES
MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_DP_IG_B_HPD NC_DP_IG_B_HPD 18 TP_SATA_D_D2RN NC_SATA_D_D2RN
NC ON UNUSED PCI ALIASES 10 TP_PE_TX_N<3..0> NC_PE_TXN<3..0> MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE

m
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_DP_IG_B_DDC_CLK NC_DP_IG_B_CTRL_CLK 18 TP_SATA_D_D2RP NC_SATA_D_D2RP
10 TP_PE_TX_P<3..0> NC_PE_TXP<3..0> MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_PCI_AD<31..0> NC_PCI_AD<31..0> MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_DP_IG_B_DDC_DATA NC_DP_IG_B_CTRL_DATA
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_SATA_D_R2D_CN NC_SATA_D_R2D_CN
20 TP_PCI_C_BE_L<3..0> NC_PCI_C_BE_L<3..0> MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE TP_SATA_D_R2D_CP NC_SATA_D_R2D_CP

co
18 TP_PCIE_D2R_PERN4 NC_PCIE_D2R_PERN4 18
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_PCI_PAR NC_PCI_PAR 19 TP_DP_IG_C_MLN<3..0> NC_DP_IG_C_MLN<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCIE_D2R_PERP4 NC_PCIE_D2R_PERP4 MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_SATA_E_D2RN NC_SATA_E_D2RN
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_DP_IG_C_MLP<3..0> NC_DP_IG_C_MLP<3..0>
20 TP_PCI_RESET_L NC_PCI_RESET_L MAKE_BASE=TRUE NO_TEST=TRUE TP_SATA_E_D2RP NC_SATA_E_D2RP
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCIE_R2D_PETN4 NC_PCIE_R2D_PETN4 18
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_DP_IG_C_AUX_N NC_DP_IG_C_AUXN

s.
MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_PCIE_R2D_PETP4 NC_PCIE_R2D_PETP4 TP_SATA_E_R2D_CN NC_SATA_E_R2D_CN
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_DP_IG_C_AUX_P NC_DP_IG_C_AUXP 18
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_SATA_E_R2D_CP NC_SATA_E_R2D_CP
TP_DP_IG_C_HPD NC_DP_IG_C_HPD MAKE_BASE=TRUE NO_TEST=TRUE
C 19
C

ic
MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_CLK 18 TP_SATA_F_D2RN NC_SATA_F_D2RN
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_DP_IG_C_CTRL_DATA NC_DP_IG_C_CTRL_DATA 18 TP_SATA_F_D2RP NC_SATA_F_D2RP
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE

at
18 TP_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE4P 18 TP_SATA_F_R2D_CN NC_SATA_F_R2D_CN
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4N 19 TP_DP_IG_D_MLN<3..0> NC_DP_IG_D_MLN<3..0> 18 TP_SATA_F_R2D_CP NC_SATA_F_R2D_CP
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
TP_DP_IG_D_MLP<3..0> NC_DP_IG_D_MLP<3..0>

em
19
18 TP_LPC_DREQ0_L NC_LPC_DREQ0_L MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_DP_IG_D_AUXN NC_DP_IG_D_AUXN
MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_DP_IG_D_AUXP NC_DP_IG_D_AUXP
MAKE_BASE=TRUE NO_TEST=TRUE
NC ON UNUSED MEM ALIASES 19 TP_DP_IG_D_HPD NC_DP_IG_D_HPD
MAKE_BASE=TRUE NO_TEST=TRUE
TP_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_CLK

ch
12 TP_MEM_A_DQ_CB<7..0> NC_MEM_A_DQ_CB<7..0>
NC ON UNUSED USB ALIASES 19

19 TP_DP_IG_D_CTRL_DATA
MAKE_BASE=TRUE NO_TEST=TRUE
NC_DP_IG_D_CTRL_DATA
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_USB_1N NC_USB_1N
MAKE_BASE=TRUE NO_TEST=TRUE
TP_MEM_A_DQS_N<8> NC_MEM_A_DQSN<8> TP_USB_1P NC_USB_1P

kS
12 20
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
12 TP_MEM_A_DQS_P<8> NC_MEM_A_DQSP<8> 20 TP_USB_2N NC_USB_2N
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_USB_2P NC_USB_2P
MAKE_BASE=TRUE NO_TEST=TRUE

12 TP_MEM_B_DQ_CB<7..0> NC_MEM_B_DQ_CB<7..0> 20 TP_USB_3N NC_USB_3N

MAKE_BASE=TRUE NO_TEST=TRUE

oo
MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_USB_3P NC_USB_3P
MAKE_BASE=TRUE NO_TEST=TRUE
TP_USB_4N NC_USB_4N
B 12 TP_MEM_B_DQS_N<8> NC_MEM_B_DQSN<8>
MAKE_BASE=TRUE NO_TEST=TRUE
20

TP_USB_4P
MAKE_BASE=TRUE
NC_USB_4P
NO_TEST=TRUE
19 TP_SDVO_TVCLKINN NC_SDVO_TVCLKINN
MAKE_BASE=TRUE NO_TEST=TRUE
B
12 TP_MEM_B_DQS_P<8> NC_MEM_B_DQSP<8> 20
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
TP_USB_5N NC_USB_5N
eb 19 TP_SDVO_TVCLKINP NC_SDVO_TVCLKINP
20 MAKE_BASE=TRUE NO_TEST=TRUE
NC ON UNUSED MISC ALIASES 20 TP_USB_5P
MAKE_BASE=TRUE
NC_USB_5P
NO_TEST=TRUE
19 TP_SDVO_STALLN NC_SDVO_STALLN
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_HDA_SDIN1 NC_HDA_SDIN1
MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_USB_6N NC_USB_6N 19 TP_SDVO_STALLP NC_SDVO_STALLP
MAKE_BASE=TRUE NO_TEST=TRUE
ot
18 TP_HDA_SDIN2 NC_HDA_SDIN2 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE TP_USB_6P NC_USB_6P
20
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_SDVO_INTN NC_SDVO_INTN
MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_HDA_SDIN3 NC_HDA_SDIN3
MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_USB_7N NC_USB_7N 19 TP_SDVO_INTP NC_SDVO_INTP
N

MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE

20 TP_USB_7P NC_USB_7P
MAKE_BASE=TRUE NO_TEST=TRUE
21 TP_PCH_PWM0 NC_PCH_PWM0
MAKE_BASE=TRUE NO_TEST=TRUE

21 TP_PCH_PWM1 NC_PCH_PWM1
MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_PCH_L_BKLTCTL NC_PCH_L_BKLTCTL
21 TP_PCH_PWM2 NC_PCH_PWM2 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_USB_10N NC_USB_10N 18 TP_PCH_L_BKLTEN NC_PCH_L_BKLTEN
21 TP_PCH_PWM3 NC_PCH_PWM3 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 20 TP_USB_10P NC_USB_10P
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCH_L_VDD_EN NC_PCH_L_VDD_EN
21 TP_PCH_SST NC_PCH_SST MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_USB_11N NC_USB_11N
MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_USB_11P NC_USB_11P 18 TP_PCH_CLKOUT_DPN NC_PCH_CLKOUT_DPN
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE

A 20 TP_USB_12N NC_USB_12N 18 TP_PCH_CLKOUT_DPP NC_PCH_CLKOUT_DPP

MAKE_BASE=TRUE NO_TEST=TRUE SYNC_MASTER=K62_SIJI SYNC_DATE=01/09/2011 A
MAKE_BASE=TRUE NO_TEST=TRUE PAGE TITLE

18 TP_PCH_CL_CLK1 NC_PCH_CL_CLK1
MAKE_BASE=TRUE NO_TEST=TRUE
20 TP_USB_12P NC_USB_12P
MAKE_BASE=TRUE NO_TEST=TRUE UNUSED SIGNAL ALIAS
DRAWING NUMBER SIZE
18 TP_PCH_CL_DATA1 NC_PCH_CL_DATA1
MAKE_BASE=TRUE NO_TEST=TRUE 20 TP_USB_13N NC_USB_13N Apple Inc. 051-8442 D
MAKE_BASE=TRUE NO_TEST=TRUE REVISION
18 TP_PCH_CL_RST1 NC_PCH_CL_RST1 20 TP_USB_13P NC_USB_13P R
10.1.0
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
8 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 8 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

m
PEG Slot Support

co
THIS SIGNAL NAME IS CONNECTED TO MXM
18 IN PEG_CLK100M_P 93 GPU_CLK100M_PCIE_P CLK_100M_MXM_P OUT 76
MAKE_BASE=TRUE
18 IN PEG_CLK100M_N 93 GPU_CLK100M_PCIE_N CLK_100M_MXM_N OUT 76
MAKE_BASE=TRUE
=PEG_R2D_C_P<0..15> PEG_R2D_C_P<0..15>

s.
10 IN OUT 78 93
MAKE_BASE=TRUE
10 IN =PEG_R2D_C_N<0..15> PEG_R2D_C_N<0..15> OUT 78 93
MAKE_BASE=TRUE
=PEG_D2R_P<0..15> PEG_D2R_P<0..15>
C 10 OUT IN 78 93
C

ic
MAKE_BASE=TRUE
10 OUT =PEG_D2R_N<0..15> PEG_D2R_N<0..15> IN 78 93
MAKE_BASE=TRUE

at
21 IN PEG_CLKREQ_L MXM_CLKREQ_L OUT 76 100
MAKE_BASE=TRUE

MXM_RESET_L PEG_RESET_L

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76 27 100
MAKE_BASE=TRUE

ch
kS
oo
B eb B
ot
N

R929
22
100 94 19 IN PM_CLK32K_SUSCLK_R 1 2 PM_CLK32K_SUSCLK OUT 46 94 100

PLACEMENT_NOTE=PLACE CLOSE TO U1800 5%

1/16W
MF-LF
402

A SYNC_MASTER=K62_SIJI SYNC_DATE=09/11/2010 A
PAGE TITLE

Signal Aliases
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

OMIT
=PPVCCIO_S0_CPU
93 19 IN DMI_S2N_N<0> W4 DMI_RX_0* OMIT PEG_COMPI B4
PLACEMENT_NOTE=Place within 12.7MM of CPU 6 11 13 16 65
U1000
93 19 IN DMI_S2N_N<1> V4 DMI_RX_1* U1000 PEG_ICOMPO B5 R1010 SANDY_BRIDGE
24.9 2 LGA1155-SKT
93 19 IN DMI_S2N_N<2> Y4 DMI_RX_2* SANDY_BRIDGE PEG_RCOMPO C4 93 CPU_PEG_COMP
MIN_LINE_WIDTH=0.3MM
1
93 19 DMI_S2N_N<3> AA5 DMI_RX_3* LGA1155-SKT MIN_NECK_WIDTH=0.2MM 1% (5 OF 10)
IN
(1 OF 10) NET_SPACING_TYPE=CPU_RCOMP 1/16W
MF-LF 8 TP_CPU_RSVD<1> C38 RSVD_C38 RSVD_P35 P35 TP_CPU_RSVD<20> 8
93 19 IN DMI_S2N_P<0> W5 DMI_RX_0 PEG_RX_0* B12 =PEG_D2R_N<0> IN 9 402
8 TP_CPU_RSVD<2> C39 RSVD_C39 RSVD_P37 P37 TP_CPU_RSVD<21> 8
93 19 IN DMI_S2N_P<1> V3 DMI_RX_1 PEG_RX_1* D11 =PEG_D2R_N<1> IN 9
8 TP_CPU_RSVD<3> D38 RSVD_D38 RSVD_P39 P39 TP_CPU_RSVD<22> 8
93 19 DMI_S2N_P<2> Y3 DMI_RX_2 PEG_RX_2* C9 =PEG_D2R_N<2> 9

D 93 19
IN
IN DMI_S2N_P<3> AA4 DMI_RX_3 PEG_RX_3* E9
B7
=PEG_D2R_N<3>
IN
IN 9
8

8
TP_CPU_RSVD<4>
TP_CPU_RSVD<5>
H7
H8
RSVD_H7
RSVD_H8
RSVD_R34
RSVD_R36
R34
R36
TP_CPU_RSVD<23>
TP_CPU_RSVD<24>
8

8
D
PEG_RX_4* =PEG_D2R_N<4> IN 9
DMI_N2S_N<0> V6 DMI_TX_0* TP_CPU_RSVD<6> J9 RSVD_J9 RSVD_R38 R38 TP_CPU_RSVD<25>

DMI
93 19 OUT 8 8
PEG_RX_5* C5 =PEG_D2R_N<5> IN 9
93 19 OUT DMI_N2S_N<1> W8 DMI_TX_1* 8 TP_CPU_RSVD<7> J31 RSVD_J31 RSVD_R40 R40 TP_CPU_RSVD<26> 8
PEG_RX_6* A6 =PEG_D2R_N<6> IN 9
93 19 DMI_N2S_N<2> Y7 DMI_TX_2* 8 TP_CPU_RSVD<8> J33 RSVD_J33 RSVD_AB6 AB6 TP_CPU_RSVD<27> 8
OUT E1 =PEG_D2R_N<7>
AA8 PEG_RX_7* IN 9
J34 AB7
93 19 OUT DMI_N2S_N<3> DMI_TX_3* 8 TP_CPU_RSVD<9> RSVD_J34 RSVD_AB7 TP_CPU_RSVD<28> 8
PEG_RX_8* F3 =PEG_D2R_N<8> IN 9
8 TP_CPU_RSVD<10> K9 RSVD_K9 RSVD_AD34 AD34 TP_CPU_RSVD<29> 8
93 19 OUT DMI_N2S_P<0> V7 DMI_TX_0 PEG_RX_9* G1 =PEG_D2R_N<9> IN 9
8 TP_CPU_RSVD<11> K31 RSVD_K31 RSVD_AD35 AD35 TP_CPU_RSVD<30> 8
93 19 DMI_N2S_P<1> W7 DMI_TX_1 PEG_RX_10* H4 =PEG_D2R_N<10> 9
OUT IN TP_CPU_RSVD<12> K34 AD37 TP_CPU_RSVD<31>
8 RSVD_K34 RSVD_AD37 8

RESERVED
93 19 OUT DMI_N2S_P<2> Y6 DMI_TX_2 PEG_RX_11* J2 =PEG_D2R_N<11> IN 9
8 TP_CPU_RSVD<13> L9 RSVD_L9 RSVD_AE6 AE6 TP_CPU_RSVD<32> 8
93 19 OUT DMI_N2S_P<3> AA7 DMI_TX_3 PEG_RX_12* K4 =PEG_D2R_N<12> IN 9
8 TP_CPU_RSVD<14> L31 RSVD_L31 RSVD_AF4 AF4 TP_CPU_RSVD<33> 8
PEG_RX_13* L2 =PEG_D2R_N<13> IN 9
8 TP_CPU_RSVD<15> L33 RSVD_L33 RSVD_AG4 AG4 TP_CPU_RSVD<34> 8
8 TP_CPU_FDI_TX_N<0> AC7 FDI_TX_0* PEG_RX_14* M4 =PEG_D2R_N<14> IN 9
8 TP_CPU_RSVD<16> L34 RSVD_L34 RSVD_AJ11 AJ11 TP_CPU_RSVD<35> 8
8 TP_CPU_FDI_TX_N<1> AC3 FDI_TX_1* PEG_RX_15* N2 =PEG_D2R_N<15> 9
IN SNS_CPU_THERMD_N M34 AJ29 TP_CPU_RSVD<36>
AD1 97 52 OUT RSVD_M34 ThermDC RSVD_AJ29 8
8 TP_CPU_FDI_TX_N<2> FDI_TX_2*
PEG_RX_0 B11 =PEG_D2R_P<0> IN 9 97 52 OUT SNS_CPU_THERMD_P N33 RSVD_N33 ThermDA RSVD_AJ30 AJ30 TP_CPU_RSVD<37> 8
TP_CPU_FDI_TX_N<3> AD3 FDI_TX_3*

FLEXIBLE DISPLAY INTERFACE

8
D12 =PEG_D2R_P<1> TP_CPU_RSVD<19> N34 AJ31 TP_CPU_RSVD<38>

m
AD6 PEG_RX_1 IN 9 8 RSVD_N34 RSVD_AJ31 8
8 TP_CPU_FDI_TX_N<4> FDI_TX_4*
PEG_RX_2 C10 =PEG_D2R_P<2> 9 RSVD_AN20 AN20 TP_CPU_RSVD<39> 8
TP_CPU_FDI_TX_N<5> AE8 IN
8 FDI_TX_5* E10 H36 AP20
PEG_RX_3 =PEG_D2R_P<3> IN 9 93 25 15 IN CPU_CFG<0> CFG_0 RSVD_AP20 TP_CPU_RSVD<40> 8
8 TP_CPU_FDI_TX_N<6> AF2 FDI_TX_6*
PEG_RX_4 B8 =PEG_D2R_P<4> IN 9 93 25 15 IN CPU_CFG<1> J36 CFG_1 RSVD_AT11 AT11 TP_CPU_RSVD<41> 8
8 TP_CPU_FDI_TX_N<7> AG1 FDI_TX_7*

co
PEG_RX_5 C6 =PEG_D2R_P<5> IN 9 93 25 15 IN CPU_CFG<2> J37 CFG_2 RSVD_AT14 AT14 TP_CPU_RSVD<42> 8

8 TP_CPU_FDI_TX_P<0> AC8 FDI_TX_0 PEG_RX_6 A5 =PEG_D2R_P<6> IN 9 93 25 15 IN CPU_CFG<3> K36 CFG_3 RSVD_AU10 AU10 TP_CPU_RSVD<43> 8

(Unused)
8 TP_CPU_FDI_TX_P<1> AC2 FDI_TX_1 PEG_RX_7 E2 =PEG_D2R_P<7> IN 9 93 25 IN CPU_CFG<4> L36 CFG_4 RSVD_AV34 AV34 TP_CPU_RSVD<44> 8

8 TP_CPU_FDI_TX_P<2> AD2 FDI_TX_2 PEG_RX_8 F4 =PEG_D2R_P<8> IN 9 93 25 15 IN CPU_CFG<5> N35 CFG_5 RSVD_AW34 AW34 TP_CPU_RSVD<45> 8

PCI EXPRESS -- GRAPHICS

8 TP_CPU_FDI_TX_P<3> AD4 FDI_TX_3 PEG_RX_9 G2 =PEG_D2R_P<9> IN 9 93 25 15 IN CPU_CFG<6> L37 CFG_6 RSVD_AY10 AY10 TP_CPU_RSVD<46> 8

s.
8 TP_CPU_FDI_TX_P<4> AD7 FDI_TX_4 PEG_RX_10 H3 =PEG_D2R_P<10> IN 9 93 25 IN CPU_CFG<7> M36 CFG_7
AE7 J1 J38 RSVD_NCTF_AV1 AV1 TP_CPU_RSVD_NCTF<1>
8 TP_CPU_FDI_TX_P<5> FDI_TX_5 PEG_RX_11 =PEG_D2R_P<11> IN 9 93 25 IN CPU_CFG<8> CFG_8
AF3 K3 L35 RSVD_NCTF_AW2 AW2 TP_CPU_RSVD_NCTF<2>
8 TP_CPU_FDI_TX_P<6> FDI_TX_6 PEG_RX_12 =PEG_D2R_P<12> IN 9 93 25 IN CPU_CFG<9> CFG_9
RSVD_NCTF_AY3 AY3
C TP_CPU_FDI_TX_P<7> AG2 L1 =PEG_D2R_P<13> CPU_CFG<10> M38
TP_CPU_RSVD_NCTF<3>
C

ic
8 FDI_TX_7 PEG_RX_13 IN 9 93 25 IN CFG_10
M3 N36 RSVD_NCTF_B39 B39 TP_CPU_RSVD_NCTF<4>
PEG_RX_14 =PEG_D2R_P<14> IN 9 93 25 IN CPU_CFG<11> CFG_11
15 CPU_FDI_FSYNC<0> AC5 FDI_FSYNC_0
PEG_RX_15 N1 =PEG_D2R_P<15> IN 9 93 25 IN CPU_CFG<12> N38 CFG_12 NCTF_A38 A38 TP_CPU_NCTF<1>
15 CPU_FDI_FSYNC<1> AE5 FDI_FSYNC_1
93 25 IN CPU_CFG<13> N39 CFG_13 NCTF_C2 C2 TP_CPU_NCTF<2>

at
PEG_TX_0* C14 =PEG_R2D_C_N<0> 9
CPU_FDI_INT AG3 FDI_INT OUT CPU_CFG<14> N37 D1 TP_CPU_NCTF<3>
15
E13 93 25 IN CFG_14 NCTF_D1
PEG_TX_1* =PEG_R2D_C_N<1> OUT 9
93 25 CPU_CFG<15> N40 CFG_15 NCTF_AU40 AU40 TP_CPU_NCTF<4>
CPU_FDI_LSYNC<0> AC4 FDI_LSYNC_0 G13 =PEG_R2D_C_N<2> IN
15 PEG_TX_2* OUT 9
G37 AW38
93 25 15 IN CPU_CFG<16> CFG_16 NCTF_AW38 TP_CPU_NCTF<5>
15 CPU_FDI_LSYNC<1> AE4 FDI_LSYNC_1 PEG_TX_3* F11 =PEG_R2D_C_N<3> OUT 9
CPU_CFG<17> G36 CFG_17

em
93 25 IN
PLACEMENT_NOTE=Place within 12.7MM of CPU PEG_TX_4* J13 =PEG_R2D_C_N<4> OUT 9 INTEL SUGGESTS TO KEEP THESE TPS
CPU_FDI_COMPIO AE2 FDI_COMPIO
MIN_LINE_WIDTH=0.3MM PEG_TX_5* D7 =PEG_R2D_C_N<5> 9
AE1 FDI_ICOMPO OUT
1 MIN_NECK_WIDTH=0.2MM
C3
R1011 NET_SPACING_TYPE=CPU_RCOMP PEG_TX_6*
E5
=PEG_R2D_C_N<6> OUT 9

0 TP_PE_RX_N<0> P4 PEG_TX_7* =PEG_R2D_C_N<7> OUT 9

5% 8 PE_RX_0* F7
1/16W PEG_TX_8* =PEG_R2D_C_N<8> OUT 9
MF-LF 8 TP_PE_RX_N<1> R1 PE_RX_1*
402 2 PEG_TX_9* G9 =PEG_R2D_C_N<9> OUT 9
(Available for Workstation only)

8 TP_PE_RX_N<2> T3 PE_RX_2* G6 FOR SANDYBRIDGE PROCESSOR

ch
PEG_TX_10* =PEG_R2D_C_N<10> OUT 9
8 TP_PE_RX_N<3> U1 PE_RX_3*
PEG_TX_11* K8 =PEG_R2D_C_N<11> OUT 9

TP_PE_RX_P<0> P3 J6 =PEG_R2D_C_N<12>
CFG [6:5] :PCIE CONFIGURATION SELECT 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
8 PE_RX_0 PEG_TX_12* OUT 9
CFG [2] :PCIE LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
PCI EXPRESS

8 TP_PE_RX_P<1> R2 PE_RX_1 PEG_TX_13* M7 =PEG_R2D_C_N<13> 9

OUT
8 TP_PE_RX_P<2> T4 PE_RX_2 PEG_TX_14* L5 =PEG_R2D_C_N<14> 9
OUT

kS
8 TP_PE_RX_P<3> U2 PE_RX_3 PEG_TX_15* N6 =PEG_R2D_C_N<15> OUT 9

8 TP_PE_TX_N<0> P7 PE_TX_0* PEG_TX_0 C13 =PEG_R2D_C_P<0> 9

OUT
8 TP_PE_TX_N<1> T8 PE_TX_1* PEG_TX_1 E14 =PEG_R2D_C_P<1> 9
OUT
8 TP_PE_TX_N<2> R5 PE_TX_2* PEG_TX_2 G14 =PEG_R2D_C_P<2> OUT 9

8 TP_PE_TX_N<3> U6 PE_TX_3* PEG_TX_3 F12 =PEG_R2D_C_P<3> OUT 9

oo
PEG_TX_4 J14 =PEG_R2D_C_P<4> OUT 9
8 TP_PE_TX_P<0> P8 PE_TX_0
PEG_TX_5 D8 =PEG_R2D_C_P<5> OUT 9
8 TP_PE_TX_P<1> T7 PE_TX_1
B 8 TP_PE_TX_P<2> R6
U5
PE_TX_2
PEG_TX_6
PEG_TX_7
D3
E6
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
OUT
OUT
9

9
B
8 TP_PE_TX_P<3> PE_TX_3
PEG_TX_8 F8 =PEG_R2D_C_P<8> 9
OUT
PEG_TX_9 G10
eb
=PEG_R2D_C_P<9> OUT 9

PEG_TX_10 G5 =PEG_R2D_C_P<10> 9
OUT
PEG_TX_11 K7 =PEG_R2D_C_P<11> OUT 9

PEG_TX_12 J5 =PEG_R2D_C_P<12> OUT 9

PEG_TX_13 M8 =PEG_R2D_C_P<13> OUT 9

ot
PEG_TX_14 L6 =PEG_R2D_C_P<14> OUT 9

PEG_TX_15 N5 =PEG_R2D_C_P<15> OUT 9

A A
PAGE TITLE

CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

65 16 13 11 10 6 =PPVCCIO_S0_CPU

D D
1
NOSTUFF 1 1 NOSTUFF NOSTUFF1
R1100 R1101 R1104 R1102
1K 51 51 1K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 402 402 402
2 2 2 2

OMIT
U1000
SANDY_BRIDGE
LGA1155-SKT
(2 OF 10)

CLOCKS
BASED ON INTEL MOBILE SOLUTION AJ33 SKTOCC* BCLK_ITP C40 ITPCPU_CLK100M_P IN 18 93
100 63 OUT CPU_SKTOCC_L
BCLK_ITP* D40 ITPCPU_CLK100M_N IN 18 93

=PPVCCIO_S0_CPU 100 19 OUT CPU_PROC_SEL K32 PROC_SEL

BCLK_0 W2 DMI_CLK100M_CPU_P

m
65 16 13 11 10 6
IN 18 93

BCLK_0* W1 DMI_CLK100M_CPU_N IN 18 93
PLACEMENT_NOTE=PLACE WITHIN 2 INCHES OF CPU
100 CPU_CATERR_L E37 CATERR*
R11241 PRDY* K38

THERMAL
XDP_CPU_PRDY_L OUT 25
75

co
5% 100 46 21 BI CPU_PECI J35 PECI PREQ* K40 XDP_CPU_PREQ_L IN 25
1/16W
MF-LF
402 2
CPU_PROCHOT_L H34 PROCHOT* TCK M40 XDP_CPU_TCK
R1125 100 65 47 BI IN 25 93

2
43 1
TMS L38 XDP_CPU_TMS IN 25 93
100 27 IN CPU_RESET_L
100 47 OUT CPU_THRMTRIP_L G35 THERMTRIP* TRST* J39 XDP_CPU_TRST_L IN 25 93
5%

s.
1/16W NOSTUFF
MF-LF
R11261 TDI L40 XDP_CPU_TDI

JTAG & BPM

402

PWR MGMT
IN 25 93

0 100 PLT_RESET_LS1V05_L F36 RESET* TDO L39 XDP_CPU_TDO OUT 25 93

C 5%
C

ic
1/16W
MF-LF E38 PM_SYNC
402 2 100 19 IN PM_SYNC DBR* E39 XDP_DBRESET_L OUT 25 100

100 25 21 IN CPU_PWRGD J40 UNCOREPWRGOOD

BPM[0]* H40 XDP_BPM_L<0> BI 25 93

at
BPM[1]* H38 XDP_BPM_L<1> BI 25 93

100 PM_MEM_PWRGD_R AJ19 SM_DRAMPWROK BPM[2]* G38 XDP_BPM_L<2>

DDR3 MISC
29 28 16 13 6 =PP1V5_S0_CPU_MEM BI 25 93

BPM[3]* G40 XDP_BPM_L<3> 25 93

CPU_MEM_RESET_L AW18 SM_DRAMRST* BI
100 32 OUT
BPM[4]* G39 XDP_BPM_L<4>

em
R11201 CPU_DDR_VREF AJ22 SM_VREF BPM[5]* F38 XDP_BPM_L<5>
BI 25 93

200 92 28 IN BI 25 93
1% BPM[6]* E40 XDP_BPM_L<6> 25 93
1/16W BI
FROM PCH MF-LF AH1 FC_AH1 F40
402 2 R1121 TP_CPU_DIMM_VREF_B BPM[7]* XDP_BPM_L<7> BI 25 93

121 TP_CPU_DIMM_VREF_A AH4 FC_AH4

100 19 IN PM_MEM_PWRGD 2 1
1%
PM_MEM_PWRGD MUST ASSERT MIN. 100ns AFTER =PP1V5_S0_CPU_MEM IS STABLE 1/16W

ch
MF-LF
402

64 63 6 =PP3V3_S5_PWRCTL
NOSTUFF NOSTUFF
1
C1110 1 C1111 R1111

kS
1
27 11 6 =PP3V3_S0_RSTBUF 1
R1183 0.1UF
10%
0.1UF
10%
1K
5%
4.7K 16V 2 2 16V
1/16W
5% 6 X5R X5R MF-LF
1 1/16W 402 402 2 402
R1190 MF-LF
2 402
D Q1180
27 11 6 =PP3V3_S0_RSTBUF 12K
OPEN-DRAIN BUFFER 5% DMB53D0UV

oo
1/16W SOT-563
MF-LF 2 G
PM_MEM_PWRGD_L
2 402
100

B 5 U1190 B
74LVC1G07 3 S
SC70
Q1180
100 74 64 IN PM_PGOOD_P1V5_S0_FET 2 4 100 PGOOD_P1V5_S0_DLY 5
eb 1
DMB53D0UV
NC SOT-563
4
1 3 C1180 1
NC_U1190_P1 0.015UF
NO_TEST=TRUE 10%
16V
ot
CAN ADJUST R1190 AND C1180 X7R 2
C1190 1 402
0.1UF
20%
10V
CERM 2
402
N

A A
PAGE TITLE

CPU CLOCK/MISC/JTAG
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

OMIT OMIT
U1000 U1000
SANDY_BRIDGE SANDY_BRIDGE
LGA1155-SKT LGA1155-SKT
92 32 MEM_A_DQ<0> AJ3 SA_DQ_0 (3 OF 10) SA_CK_0 AY25 MEM_A_CLK_P<0> 32 92 92 32 MEM_B_DQ<0> AG7 SB_DQ_0 (4 OF 10) SB_CK_0 AL21 MEM_B_CLK_P<0> 32 92
BI OUT BI OUT
92 32 MEM_A_DQ<1> AJ4 SA_DQ_1 SA_CK_0* AW25 MEM_A_CLK_N<0> 32 92 92 32 MEM_B_DQ<1> AG8 SB_DQ_1 SB_CK_0* AL22 MEM_B_CLK_N<0> 32 92
BI OUT BI OUT
92 32 BI MEM_A_DQ<2> AL3 SA_DQ_2 92 32 BI MEM_B_DQ<2> AJ9 SB_DQ_2
AL4 SA_CKE_0 AV19 MEM_A_CKE<0> OUT 30 92
AJ8 SB_CKE_0 AU16 MEM_B_CKE<0> OUT 31 92
92 32 BI MEM_A_DQ<3> SA_DQ_3 92 32 BI MEM_B_DQ<3> SB_DQ_3

D 92 32

92 32
BI
BI
MEM_A_DQ<4>
MEM_A_DQ<5>
AJ2
AJ1
SA_DQ_4
SA_DQ_5
SA_CK_1 AU24
SA_CK_1* AU25
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
OUT
OUT
32 92

32 92
92 32

92 32
BI
BI
MEM_B_DQ<4>
MEM_B_DQ<5>
AG5
AG6
SB_DQ_4
SB_DQ_5
SB_CK_1 AL20
SB_CK_1* AK20
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
OUT
32 92

32 92
D
92 32 BI MEM_A_DQ<6> AL2 SA_DQ_6 92 32 BI MEM_B_DQ<6> AJ6 SB_DQ_6
AL1 SA_CKE_1 AT19 MEM_A_CKE<1> OUT 30 92
AJ7 SB_CKE_1 AY15 MEM_B_CKE<1> OUT 31 92
92 32 BI MEM_A_DQ<7> SA_DQ_7 92 32 BI MEM_B_DQ<7> SB_DQ_7

DDR SYSTEM MEMORY A

92 32 MEM_A_DQ<8> AN1 SA_DQ_8 SA_CK_2 AW27 MEM_A_CLK_P<2> 32 92 92 32 MEM_B_DQ<8> AL7 SB_DQ_8 SB_CK_2 AL23 MEM_B_CLK_P<2> 32 92
BI OUT BI OUT

DDR SYSTEM MEMORY B

92 32 BI MEM_A_DQ<9> AN4 SA_DQ_9 SA_CK_2* AY27 MEM_A_CLK_N<2> OUT 32 92 92 32 BI MEM_B_DQ<9> AM7 SB_DQ_9 SB_CK_2* AM22 MEM_B_CLK_N<2> OUT 32 92

92 32 BI MEM_A_DQ<10> AR3 SA_DQ_10 92 32 BI MEM_B_DQ<10> AM10 SB_DQ_10

AR4 SA_CKE_2 AU18 MEM_A_CKE<2> OUT 30 92
AL10 SB_CKE_2 AW15 MEM_B_CKE<2> OUT 31 92
92 32 BI MEM_A_DQ<11> SA_DQ_11 92 32 BI MEM_B_DQ<11> SB_DQ_11
92 32 BI MEM_A_DQ<12> AN2 SA_DQ_12 SA_CK_3 AV26 MEM_A_CLK_P<3> OUT 32 92 92 32 BI MEM_B_DQ<12> AL6 SB_DQ_12 SB_CK_3 AP21 MEM_B_CLK_P<3> OUT 32 92

92 32 BI MEM_A_DQ<13> AN3 SA_DQ_13 SA_CK_3* AW26 MEM_A_CLK_N<3> OUT 32 92 92 32 BI MEM_B_DQ<13> AM6 SB_DQ_13 SB_CK_3* AN21 MEM_B_CLK_N<3> OUT 32 92

92 32 BI MEM_A_DQ<14> AR2 SA_DQ_14 92 32 BI MEM_B_DQ<14> AL9 SB_DQ_14

AR1 SA_CKE_3 AV18 MEM_A_CKE<3> OUT 30 92
AM9 SB_CKE_3 AV15 MEM_B_CKE<3> OUT 31 92
92 32 BI MEM_A_DQ<15> SA_DQ_15 92 32 BI MEM_B_DQ<15> SB_DQ_15
92 32 BI MEM_A_DQ<16> AV2 SA_DQ_16 SA_CS_0* AU29 MEM_A_CS_L<0> OUT 30 92 92 32 BI MEM_B_DQ<16> AP7 SB_DQ_16 SB_CS_0* AN25 MEM_B_CS_L<0> OUT 31 92

92 32 BI MEM_A_DQ<17> AW3 SA_DQ_17 SA_CS_1* AV32 MEM_A_CS_L<1> OUT 30 92 92 32 BI MEM_B_DQ<17> AR7 SB_DQ_17 SB_CS_1* AN26 MEM_B_CS_L<1> OUT 31 92

92 32 BI MEM_A_DQ<18> AV5 SA_DQ_18 SA_CS_2* AW30 MEM_A_CS_L<2> OUT 30 92 92 32 BI MEM_B_DQ<18> AP10 SB_DQ_18 SB_CS_2* AL25 MEM_B_CS_L<2> OUT 31 92

MEM_A_DQ<19> AW5 AU33 MEM_A_CS_L<3> MEM_B_DQ<19> AR10 AT26 MEM_B_CS_L<3>

m
92 32 BI SA_DQ_19 SA_CS_3* OUT 30 92 92 32 BI SB_DQ_19 SB_CS_3* OUT 31 92

92 32 MEM_A_DQ<20> AU2 SA_DQ_20 92 32 MEM_B_DQ<20> AP6 SB_DQ_20

BI BI
92 32 BI MEM_A_DQ<21> AU3 SA_DQ_21 SA_ODT_0 AV31 MEM_A_ODT<0> OUT 30 92 92 32 BI MEM_B_DQ<21> AR6 SB_DQ_21 SB_ODT_0 AL26 MEM_B_ODT<0> OUT 31 92

92 32 BI MEM_A_DQ<22> AU5 SA_DQ_22 SA_ODT_1 AU32 MEM_A_ODT<1> OUT 30 92 92 32 BI MEM_B_DQ<22> AP9 SB_DQ_22 SB_ODT_1 AP26 MEM_B_ODT<1> OUT 31 92

co
92 32 BI MEM_A_DQ<23> AY5 SA_DQ_23 SA_ODT_2 AU30 MEM_A_ODT<2> OUT 30 92 92 32 BI MEM_B_DQ<23> AR9 SB_DQ_23 SB_ODT_2 AM26 MEM_B_ODT<2> OUT 31 92

92 32 BI MEM_A_DQ<24> AY7 SA_DQ_24 SA_ODT_3 AW33 MEM_A_ODT<3> OUT 30 92 92 32 BI MEM_B_DQ<24> AM12 SB_DQ_24 SB_ODT_3 AK26 MEM_B_ODT<3> OUT 31 92

92 32 BI MEM_A_DQ<25> AU7 SA_DQ_25 92 32 BI MEM_B_DQ<25> AM13 SB_DQ_25

92 32 BI MEM_A_DQ<26> AV9 SA_DQ_26 SA_DQS_0* AK2 MEM_A_DQS_N<0> BI 32 92 92 32 BI MEM_B_DQ<26> AR13 SB_DQ_26 SB_DQS_0* AH6 MEM_B_DQS_N<0> BI 32 92

92 32 BI MEM_A_DQ<27> AU9 SA_DQ_27 SA_DQS_1* AP2 MEM_A_DQS_N<1> BI 32 92 92 32 BI MEM_B_DQ<27> AP13 SB_DQ_27 SB_DQS_1* AL8 MEM_B_DQS_N<1> BI 32 92

s.
92 32 BI MEM_A_DQ<28> AV7 SA_DQ_28 SA_DQS_2* AV4 MEM_A_DQS_N<2> BI 32 92 92 32 BI MEM_B_DQ<28> AL12 SB_DQ_28 SB_DQS_2* AP8 MEM_B_DQS_N<2> BI 32 92

92 32 MEM_A_DQ<29> AW7 SA_DQ_29 SA_DQS_3* AW8 MEM_A_DQS_N<3> 32 92 92 32 MEM_B_DQ<29> AL13 SB_DQ_29 SB_DQS_3* AN12 MEM_B_DQS_N<3> 32 92
BI BI BI BI
92 32 BI MEM_A_DQ<30> AW9 SA_DQ_30 SA_DQS_4* AV36 MEM_A_DQS_N<4> BI 32 92 92 32 BI MEM_B_DQ<30> AR12 SB_DQ_30 SB_DQS_4* AN28 MEM_B_DQS_N<4> BI 32 92

C MEM_A_DQ<31> AY9 AP39 MEM_A_DQS_N<5> MEM_B_DQ<31> AP12 AR33 MEM_B_DQS_N<5> C

ic
92 32 BI SA_DQ_31 SA_DQS_5* BI 32 92 92 32 BI SB_DQ_31 SB_DQS_5* BI 32 92

92 32 BI MEM_A_DQ<32> AU35 SA_DQ_32 SA_DQS_6* AK39 MEM_A_DQS_N<6> BI 32 92 92 32 BI MEM_B_DQ<32> AR28 SB_DQ_32 SB_DQS_6* AM33 MEM_B_DQS_N<6> BI 32 92

92 32 BI MEM_A_DQ<33> AW37 SA_DQ_33 SA_DQS_7* AF39 MEM_A_DQS_N<7> BI 32 92 92 32 BI MEM_B_DQ<33> AR29 SB_DQ_33 SB_DQS_7* AG34 MEM_B_DQS_N<7> BI 32 92

92 32 BI MEM_A_DQ<34> AU39 SA_DQ_34 SA_DQS_8* AV12 TP_MEM_A_DQS_N<8> 8 92 32 BI MEM_B_DQ<34> AL28 SB_DQ_34 SB_DQS_8* AN15 TP_MEM_B_DQS_N<8> 8

at
92 32 BI MEM_A_DQ<35> AU36 SA_DQ_35 92 32 BI MEM_B_DQ<35> AL29 SB_DQ_35
SA_DQS_0 AK3 MEM_A_DQS_P<0> 32 92 SB_DQS_0 AH7 MEM_B_DQS_P<0> 32 92
MEM_A_DQ<36> AW35 BI MEM_B_DQ<36> AP28 BI
92 32 BI SA_DQ_36 AP3 92 32 BI SB_DQ_36 AM8
SA_DQS_1 MEM_A_DQS_P<1> BI 32 92 SB_DQS_1 MEM_B_DQS_P<1> BI 32 92
92 32 MEM_A_DQ<37> AY36 SA_DQ_37 92 32 MEM_B_DQ<37> AP29 SB_DQ_37
BI AW4 MEM_A_DQS_P<2> BI AR8 MEM_B_DQS_P<2>
AU38 SA_DQS_2 BI 32 92
AM28 SB_DQS_2 BI 32 92
MEM_A_DQ<38> SA_DQ_38 MEM_B_DQ<38> SB_DQ_38

em
92 32 BI 92 32 BI
SA_DQS_3 AV8 MEM_A_DQS_P<3> BI 32 92 SB_DQS_3 AN13 MEM_B_DQS_P<3> BI 32 92
92 32 MEM_A_DQ<39> AU37 SA_DQ_39 92 32 MEM_B_DQ<39> AM29 SB_DQ_39
BI AV37 MEM_A_DQS_P<4> BI AN29 MEM_B_DQS_P<4>
AR40 SA_DQS_4 BI 32 92
AP32 SB_DQS_4 BI 32 92
92 32 BI MEM_A_DQ<40> SA_DQ_40 92 32 BI MEM_B_DQ<40> SB_DQ_40
SA_DQS_5 AP38 MEM_A_DQS_P<5> 32 92 SB_DQS_5 AP33 MEM_B_DQS_P<5> 32 92
MEM_A_DQ<41> AR37 BI MEM_B_DQ<41> AP31 BI
92 32 BI SA_DQ_41 AK38 92 32 BI SB_DQ_41 AL33
SA_DQS_6 MEM_A_DQS_P<6> BI 32 92 SB_DQS_6 MEM_B_DQS_P<6> BI 32 92
92 32 BI MEM_A_DQ<42> AN38 SA_DQ_42 92 32 BI MEM_B_DQ<42> AP35 SB_DQ_42
SA_DQS_7 AF38 MEM_A_DQS_P<7> 32 92 SB_DQS_7 AG35 MEM_B_DQS_P<7> 32 92
MEM_A_DQ<43> AN37 BI MEM_B_DQ<43> AP34 BI
92 32 BI SA_DQ_43 AV13 92 32 BI SB_DQ_43 AN16
SA_DQS_8 TP_MEM_A_DQS_P<8> 8 SB_DQS_8 TP_MEM_B_DQS_P<8> 8
92 32 MEM_A_DQ<44> AR39 SA_DQ_44 92 32 MEM_B_DQ<44> AR32 SB_DQ_44
BI BI

ch
92 32 MEM_A_DQ<45> AR38 SA_DQ_45 SA_MA_0 AV27 MEM_A_A<0> 30 92 92 32 MEM_B_DQ<45> AR31 SB_DQ_45 SB_MA_0 AK24 MEM_B_A<0> 31 92
BI OUT BI OUT
92 32 MEM_A_DQ<46> AN39 SA_DQ_46 SA_MA_1 AY24 MEM_A_A<1> 30 92 92 32 MEM_B_DQ<46> AR35 SB_DQ_46 SB_MA_1 AM20 MEM_B_A<1> 31 92
BI OUT BI OUT
92 32 BI MEM_A_DQ<47> AN40 SA_DQ_47 SA_MA_2 AW24 MEM_A_A<2> OUT 30 92 92 32 BI MEM_B_DQ<47> AR34 SB_DQ_47 SB_MA_2 AM19 MEM_B_A<2> OUT 31 92

92 32 BI MEM_A_DQ<48> AL40 SA_DQ_48 SA_MA_3 AW23 MEM_A_A<3> OUT 30 92 92 32 BI MEM_B_DQ<48> AM32 SB_DQ_48 SB_MA_3 AK18 MEM_B_A<3> OUT 31 92

MEM_A_DQ<49> AL37 SA_DQ_49 SA_MA_4 AV23 MEM_A_A<4> MEM_B_DQ<49> AM31 SB_DQ_49 SB_MA_4 AP19 MEM_B_A<4>

kS
92 32 BI OUT 30 92 92 32 BI OUT 31 92

92 32 BI MEM_A_DQ<50> AJ38 SA_DQ_50 SA_MA_5 AT24 MEM_A_A<5> OUT 30 92 92 32 BI MEM_B_DQ<50> AL35 SB_DQ_50 SB_MA_5 AP18 MEM_B_A<5> OUT 31 92

92 32 MEM_A_DQ<51> AJ37 SA_DQ_51 SA_MA_6 AT23 MEM_A_A<6> 30 92 92 32 MEM_B_DQ<51> AL32 SB_DQ_51 SB_MA_6 AM18 MEM_B_A<6> 31 92
BI OUT BI OUT
92 32 MEM_A_DQ<52> AL39 SA_DQ_52 SA_MA_7 AU22 MEM_A_A<7> 30 92 92 32 MEM_B_DQ<52> AM34 SB_DQ_52 SB_MA_7 AL18 MEM_B_A<7> 31 92
BI OUT BI OUT
92 32 BI MEM_A_DQ<53> AL38 SA_DQ_53 SA_MA_8 AV22 MEM_A_A<8> OUT 30 92 92 32 BI MEM_B_DQ<53> AL31 SB_DQ_53 SB_MA_8 AN18 MEM_B_A<8> OUT 31 92

92 32 BI MEM_A_DQ<54> AJ39 SA_DQ_54 SA_MA_9 AT22 MEM_A_A<9> OUT 30 92 92 32 BI MEM_B_DQ<54> AM35 SB_DQ_54 SB_MA_9 AY17 MEM_B_A<9> OUT 31 92

oo
92 32 BI MEM_A_DQ<55> AJ40 SA_DQ_55 SA_MA_10 AV28 MEM_A_A<10> OUT 30 92 92 32 BI MEM_B_DQ<55> AL34 SB_DQ_55 SB_MA_10 AN23 MEM_B_A<10> OUT 31 92

92 32 BI MEM_A_DQ<56> AG40 SA_DQ_56 SA_MA_11 AU21 MEM_A_A<11> OUT 30 92 92 32 BI MEM_B_DQ<56> AH35 SB_DQ_56 SB_MA_11 AU17 MEM_B_A<11> OUT 31 92

B 92 32

92 32
BI
BI
MEM_A_DQ<57>
MEM_A_DQ<58>
AG37
AE38
SA_DQ_57
SA_DQ_58
SA_MA_12
SA_MA_13
AT21
AW32
MEM_A_A<12>
MEM_A_A<13>
OUT
OUT
30 92

30 92
92 32

92 32
BI
BI
MEM_B_DQ<57>
MEM_B_DQ<58>
AH34
AE34
SB_DQ_57
SB_DQ_58
SB_MA_12
SB_MA_13
AT18
AR26
MEM_B_A<12>
MEM_B_A<13>
OUT
OUT
31 92

31 92
B
92 32 MEM_A_DQ<59> AE37 SA_DQ_59 SA_MA_14 AU20 MEM_A_A<14> 30 92 92 32 MEM_B_DQ<59> AE35 SB_DQ_59 SB_MA_14 AY16 MEM_B_A<14> 31 92
BI OUT BI OUT
92 32 BI MEM_A_DQ<60> AG39 SA_DQ_60 SA_MA_15 AT20
eb
MEM_A_A<15> OUT 30 92 92 32 BI MEM_B_DQ<60> AJ35 SB_DQ_60 SB_MA_15 AV16 MEM_B_A<15> OUT 31 92

92 32 MEM_A_DQ<61> AG38 SA_DQ_61 92 32 MEM_B_DQ<61> AJ34 SB_DQ_61

BI AU12 TP_MEM_A_DQ_CB<0> BI AL16 TP_MEM_B_DQ_CB<0>
AE39 SA_ECC_CB_0 8
AF33 SB_ECC_CB_0 8
92 32 BI MEM_A_DQ<62> SA_DQ_62 92 32 BI MEM_B_DQ<62> SB_DQ_62
SA_ECC_CB_1 AU14 TP_MEM_A_DQ_CB<1> 8 SB_ECC_CB_1 AM16 TP_MEM_B_DQ_CB<1> 8
92 32 BI MEM_A_DQ<63> AE40 SA_DQ_63 92 32 BI MEM_B_DQ<63> AF35 SB_DQ_63
SA_ECC_CB_2 AW13 TP_MEM_A_DQ_CB<2> 8 SB_ECC_CB_2 AP16 TP_MEM_B_DQ_CB<2> 8

MEM_A_BA<0> AY29 SA_BS_0 AY13 TP_MEM_A_DQ_CB<3> MEM_B_BA<0> AP23 SB_BS_0 AR16 TP_MEM_B_DQ_CB<3>
ot
92 30 OUT SA_ECC_CB_3 8 92 31 OUT SB_ECC_CB_3 8

92 30 OUT MEM_A_BA<1> AW28 SA_BS_1 SA_ECC_CB_4 AU13 TP_MEM_A_DQ_CB<4> 8 92 31 OUT MEM_B_BA<1> AM24 SB_BS_1 SB_ECC_CB_4 AL15 TP_MEM_B_DQ_CB<4> 8

92 30 OUT MEM_A_BA<2> AV20 SA_BS_2 SA_ECC_CB_5 AU11 TP_MEM_A_DQ_CB<5> 8 92 31 OUT MEM_B_BA<2> AW17 SB_BS_2 SB_ECC_CB_5 AM15 TP_MEM_B_DQ_CB<5> 8

SA_ECC_CB_6 AY12 TP_MEM_A_DQ_CB<6> 8 SB_ECC_CB_6 AR15 TP_MEM_B_DQ_CB<6> 8

92 30 MEM_A_CAS_L AV30 SA_CAS* 92 31 MEM_B_CAS_L AK25 SB_CAS*
OUT OUT
N

SA_ECC_CB_7 AW12 TP_MEM_A_DQ_CB<7> 8 SB_ECC_CB_7 AP15 TP_MEM_B_DQ_CB<7> 8

92 30 OUT MEM_A_RAS_L AU28 SA_RAS* 92 31 OUT MEM_B_RAS_L AP24 SB_RAS*
92 30 OUT MEM_A_WE_L AW29 SA_WE* 92 31 OUT MEM_B_WE_L AR25 SB_WE*

A SYNC_DATE=01/09/2011 A
PAGE TITLE

CPU DDR3 INTERFACES

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

OMIT
U1000
65 50 16 13 6 =PPVCORE_S0_CPU SANDY_BRIDGE
65 50 16 13 6 =PPVCORE_S0_CPU LGA1155-SKT =PPVCCIO_S0_CPU 6 10 11 13 16 65

D
A12
A13
VCC_001 (6 OF 10) VCCIO_01 A11
A7
(NOT controlled by VCCIO_SEL)
OMIT D
OMIT
A14
VCC_002
VCC_003
VCCIO_02
VCCIO_03 AA3
Fixed at 1.05V U1000
U1000 A15 VCC_004 VCCIO_04 AB8
SANDY_BRIDGE
LGA1155-SKT
SANDY_BRIDGE 65 50 17 6 =PPVAXG_S0_CPU
A16 VCC_005 VCCIO_05 AF8 AB33 ( 7 OF 10 )
LGA1155-SKT VCCAXG_01
A18 VCC_006 VCCIO_06 AG33 AB34
F16 VCC_071 (10 OF 10) VCC_131 K22 VCCAXG_02
A24 VCC_007 VCCIO_07 AJ16 AB35
F18 VCC_072 VCC_132 K24 VCCAXG_03
A25 VCC_008 VCCIO_08 AJ17 AB36
F19 VCC_073 VCC_133 K25 VCCAXG_04
A27 VCC_009 VCCIO_09 AJ26 AB37
F21 VCC_074 VCC_134 K27 VCCAXG_05
A28 VCC_010 VCCIO_10 AJ28 AB38
F22 VCC_075 VCC_135 K28 VCCAXG_06
B15 VCC_011 VCCIO_11 AJ32 AB39
F24 VCC_076 VCC_136 K30 VCCAXG_07
B16 VCC_012 VCCIO_12 AK15 AB40
F25 VCC_077 VCC_137 L13 VCCAXG_08
B18 VCC_013 VCCIO_13 AK17 AC33
F27 VCC_078 VCC_138 L14 VCCAXG_09
B24 VCC_014 VCCIO_14 AK19 AC34
F28 VCC_079 VCC_139 L15 VCCAXG_10
B25 VCC_015 VCCIO_15 AK21 AC35 =PP1V5_S0_CPU_MEM 6 11 16 28 29
F30 VCC_080 VCC_140 L16 VCCAXG_11
B27 AK23

m
VCC_016 VCCIO_16
POWER
F31 L18 AC36 VCCAXG_12
VCC_081 VCC_141 B28 AK27
F32 L19 VCC_017 VCCIO_17 AC37 VCCAXG_13
VCC_082 VCC_142 B30 AK29
F33 CPU CORE SUPPLY L21 VCC_018 VCCIO_18 AC38 VCCAXG_14
VCC_083 VCC_143 B31 AK30
F34 L22 VCC_019 VCCIO_19 AC39 VCCAXG_15 VDDQ0 AJ13

IO POWER
VCC_084 VCC_144

co
B33 VCC_020 VCCIO_20 B9 AC40 AJ14
G15 L24 VCCAXG_16 VDDQ1

POWER
VCC_085 VCC_145 B34 D6
G16 L25 VCC_021 VCCIO_22 T33 VCCAXG_17 VDDQ2 AJ20
VCC_086 VCC_146 C15 D10
G18 L27 VCC_022 VCCIO_21 T34 VCCAXG_18 VDDQ3 AJ23
VCC_087 VCC_147 C16 E3
G19 L28 VCC_023 VCCIO_23 T35 VCCAXG_19 VDDQ4 AJ24
VCC_088 VCC_148 C18 E4
G21 L30 VCC_024 VCCIO_24 T36 VCCAXG_20 VDDQ5 AR20

s.
VCC_089 VCC_149 C19 G3
G22 M14 VCC_025 VCCIO_25 T37 AR21
VCC_090 VCC_150 VCCAXG_21 VDDQ6
C21 VCC_026 VCCIO_26 G4
G24 VCC_091 VCC_151 M15 T38 VCCAXG_22 VDDQ7 AR22

DDR3-1.5V RAILS
C22 VCC_027 VCCIO_27 J3 T39 AR23
G25 M16
C

GRAPHICS
VCCAXG_23 VDDQ8
C VCC_092 VCC_152 C24 J4

ic
VCC_028 VCCIO_28 T40 AR24

POWER
G27 VCC_093 VCC_153 M18 VCCAXG_24 VDDQ9
C25 VCC_029 VCCIO_29 J7 U33 AU19
G28 VCC_094 VCC_154 M19 VCCAXG_25 VDDQ10
C27 VCC_030 VCCIO_30 J8 U34 AU23

CPU CORE SUPPLY

G30 VCC_095 VCC_155 M21 VCCAXG_26 VDDQ11
C28 VCC_031 VCCIO_31 L3 U35 AU27

at
G31 VCC_096 VCC_156 M22 VCCAXG_27 VDDQ12
C30 VCC_032 VCCIO_32 L4 U36 AU31
G32 VCC_097 VCC_157 M24 VCCAXG_28 VDDQ13
C31 L7
CPU CORE SUPPLY

G33 M25 VCC_033 VCCIO_33 U37 VCCAXG_29 VDDQ14 AV21

VCC_098 VCC_158 C33 M13
H13 M27 VCC_034 VCCIO_34 U38 VCCAXG_30 VDDQ15 AV24
VCC_099 VCC_159 C34 N3

em
H14 M28 VCC_035 VCCIO_35 U39 VCCAXG_31 VDDQ16 AV25
VCC_100 VCC_160 C36 N4
VCC_036 VCCIO_36 PLACEMENT NOTE: U40 AV29
H15 VCC_101 VCC_161 M30 VCCAXG_32 VDDQ17
D13 VCC_037 VCCIO_37 N7 W33 AV33
H16 VCC_102 VCCAXG_33 VDDQ18
=PPVCCSA_S0_CPU D14 VCC_038 VCCIO_38 R3 PLACE R1300 AND
H18 6 50 W34 VCCAXG_34 VDDQ19 AW31
VCC_103 D15 R4 R1302 NEAR CPU
H19 VCC_039 VCCIO_39 W35 AY23
VCC_104 VCCAXG_35 VDDQ20
D16 VCC_040 VCCIO_40 R7 PLACEMENT_NOTE=Place close to CPU W36 AY26
H21 VCC_105 VCCSA0 H10 PLACEMENT_NOTE=Place close to CPU VCCAXG_36 VDDQ21
D18 VCC_041 VCCIO_41 U3 W37 AY28

ch
H22 VCC_106 VCCSA1 H11 =PPVCCIO_S0_CPU 6 10 11 13 16 65 VCCAXG_37 VDDQ22
D19 VCC_042 VCCIO_42 U4 W38
H24 VCC_107 VCCSA2 H12 VCCAXG_38
D21 VCC_043 VCCIO_43 U7 Y33
H25 VCC_108 VCCSA3 J10 1 1 VCCAXG_39
D22 VCC_044 VCCIO_44 V8 R1300 R1302 Y34
H27 K10 75 110 VCCAXG_40 =PP1V8_S0_CPU_PLL
VCCSA

VCC_109 VCCSA4 D24 W3

6 16

H28 K11 VCC_045 VCCIO_45 1% 1% Y35 VCCAXG_41

VCC_110 VCCSA5 D25 1/16W 1/16W

kS
VCC_046 MF-LF MF-LF Y36 VCCPLL0 AK11

1.8V
H30 VCC_111 VCCSA6 L11 402 402 VCCAXG_42
D27 VCC_047 2 2
H31 L12 Y37 VCCAXG_43 VCCPLL1 AK12
VCC_112 VCCSA7 D28
H32 M10 VCC_048 Y38 VCCAXG_44
VCC_113 VCCSA8 D30
J12 M11 VCC_049
VCC_114 VCCSA9 D31 VCCIO_SEL P33 TP_CPU_VCCIO_SEL
J15 M12 VCC_050
VCC_115 VCCSA10 D33 VCC_051 VCCSA_VID P34 TP_CPU_VCCSA_VID

oo
J16

CPU VIDS
VCC_116 D34 R1310
J18 VCC_052
VCC_117 D35 44.2 2
J19 VCC_053 VIDALERT* A37 98 CPU_VIDALERT_L_R 1% 1 1/16W CPU_VIDALERT_L IN 65 98
VCC_118 402
B J21 VCC_119
D36
E15
VCC_054
VCC_055 VIDSCLK C37 98 CPU_VIDSCLK_R
MF-LF

R1311
B
J22 VCC_120 E16 VCC_056 5% 1
0 2 1/16W CPU_VIDSCLK
J24 A4
VCC_121 VSS_NCTF0 E18
eb
VCC_057 VIDSOUT B37 98 CPU_VIDSOUT_R 402
OUT 65 98

J25 B3 MF-LF
VCC_122 VSS_NCTF1
NCTF

E19 VCC_058
J27 VCC_123 VSS_NCTF2 AV39 R1312
E21 VCC_059 0
J28 VCC_124 VSS_NCTF3 AY37 5% 1 2 1/16W CPU_VIDSOUT 65 98
E22 BI
J30 VCC_060 MF-LF 402
VCC_125 E24
K15 VCC_061
ot
VCC_126
SENSE LINES

E25 VCC_062 VCCSA_SENSE T2 CPU_VCCSA_SENSE OUT 69 98

K16 VCC_127 E27 VCC_063
K18 VCC_128 E28 VCC_064 VCC_SENSE A36 CPU_VCC_SENSE_P 65 98
K19 OUT
VCC_129 E30 VCC_065 VSS_SENSE B36 CPU_VCC_SENSE_N
N

OUT 65 98
K21 VCC_130 E31 VCC_066
E33 VCC_067 VCCIO_SENSE AB4 CPU_VCCIO_SENSE_P 68 98
OUT
E34 VCC_068 VSSIO_SENSE AB3 CPU_VCCIO_SENSE_N OUT 68 98
E35 VCC_069
F15 VCC_070 VCCAXG_SENSE L32 CPU_VAXG_SENSE_P 65 98
OUT
VSSAXG_SENSE M32 CPU_VAXG_SENSE_N OUT 65 98

A SYNC_MASTER=K62_ROSITA SYNC_DATE=01/09/2011 A
PAGE TITLE

CPU POWER
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

D
AA35
AA36
VSS_008
VSS_009
VSS_098
VSS_099
AM4
AM40
AW11
AW14
VSS_189 VSS_279 H33
H35
D
AA37 AM5 VSS_190 VSS_280
VSS_010 VSS_100 AW16 H37
AA38 AN10 VSS_191 VSS_281
VSS_011 VSS_101 AW36 H39
AA6 AN11 VSS_192 VSS_282
VSS_012 VSS_102 AW6 H5
AB5 AN14 VSS_193 VSS_283
VSS_013 VSS_103 AY11 H6
AC1 AN17 VSS_194 VSS_284
VSS_014 VSS_104 AY14 H9
AC6 AN19 VSS_195 VSS_285
VSS_015 VSS_105 AY18 J11
AD33 AN22 VSS_196 VSS_286
VSS_016 VSS_106 AY35 J17
AD36 AN24 VSS_197 VSS_287
VSS_017 VSS_107 AY4 J20
AD38 AN27 VSS_198 VSS_288
VSS_018 VSS_108

VSS
AY6 VSS_199 VSS_289 J23
AD39 VSS_019 VSS_109 AN30
AY8 VSS_200 VSS_290 J26
AD40 VSS_020 VSS_110 AN31

VSS
B10 VSS_201 VSS_291 J29
AD5 VSS_021 VSS_111 AN32
B13 VSS_202 VSS_292 J32
AD8 VSS_022 VSS_112 AN33
B14 VSS_203 VSS_293 K1
AE3 AN34

m
VSS_023 VSS_113 B17 K12
AE33 AN35 VSS_204 VSS_294
VSS_024 VSS_114 B23 K13
AE36 AN36 VSS_205 VSS_295
VSS_025 VSS_115 B26 K14
AF1 AN5 VSS_206 VSS_296
VSS_026 VSS_116 B29 K17
VSS_207 VSS_297

co
AF34 VSS_027 VSS_117 AN6
B32 VSS_208 VSS_298 K2
AF36 VSS_028 VSS_118 AN7
B35 VSS_209 VSS_299 K20
AF37 VSS_029 VSS_119 AN8
B38 VSS_210 VSS_300 K23
AF40 VSS_030 VSS_120 AN9
B6 VSS_211 VSS_301 K26
AF5 VSS_031 VSS_121 AP1
C11 K29

s.
AF6 AP11 VSS_212 VSS_302
VSS_032 VSS_122 C12 K33
AF7 AP14 VSS_213 VSS_303
VSS_033 VSS_123 C17 K35
AG36 AP17 VSS_214 VSS_304
VSS_034 VSS_124 C20 K37
C AH2 AP22 VSS_215 VSS_305
C

ic
VSS_035 VSS_125 C23 K39
AH3 AP25 VSS_216 VSS_306
VSS_036 VSS_126 C26 K5
AH33 AP27 VSS_217 VSS_307
VSS_037 VSS_127 C29 K6
AH36 AP30 VSS_218 VSS_308
VSS_038 VSS_128

at
C32 VSS_219 VSS_309 L10
AH37 VSS_039 VSS_129 AP36
C35 VSS_220 VSS_310 L17
AH38 VSS_040 VSS_130 AP37
C7 VSS_221 VSS_311 L20
AH39 VSS_041 VSS_131 AP4
C8 VSS_222 VSS_312 L23
AH40 VSS_042 VSS_132 AP40

em
D17 VSS_223 VSS_313 L26
AH5 VSS_043 VSS_133 AP5
D2 VSS_224 VSS_314 L29
AH8 VSS_044 VSS_134 AR11
D20 VSS_225 VSS_315 L8
AJ12 VSS_045 VSS_135 AR14
D23 VSS_226 VSS_316 M1
AJ15 VSS_046 VSS_136 AR17
D26 VSS_227 VSS_317 M17
AJ18 VSS_047 VSS_137 AR18
D29 VSS_228 VSS_318 M2
AJ21 VSS_048 VSS_138 AR19
D32 M20

ch
AJ25 AR27 VSS_229 VSS_319
VSS_049 VSS_139 D37 M23
AJ27 AR30 VSS_230 VSS_320
VSS_050 VSS_140 D39 M26
AJ36 AR36 VSS_231 VSS_321
VSS_051 VSS_141 D4 M29
AJ5 AR5 VSS_232 VSS_322
VSS_052 VSS_142 D5 M33
AK1 AT1 VSS_233 VSS_323
VSS_053 VSS_143

kS
D9 VSS_234 VSS_324 M35
AK10 VSS_054 VSS_144 AT10
E11 VSS_235 VSS_325 M37
AK13 VSS_055 VSS_145 AT12
E12 VSS_236 VSS_326 M39
AK14 VSS_056 VSS_146 AT13
E17 VSS_237 VSS_327 M5
AK16 VSS_057 VSS_147 AT15
E20 VSS_238 VSS_328 M6
AK22 VSS_058 VSS_148 AT16
E23 M9

oo
AK28 AT17 VSS_239 VSS_329
VSS_059 VSS_149 E26 N8
AK31 AT2 VSS_240 VSS_330
VSS_060 VSS_150 E29 P1
VSS_241 VSS_331
B AK32
AK33
VSS_061
VSS_062
VSS_151
VSS_152
AT25
AT27
E32
E36
VSS_242 VSS_332 P2
P36
B
AK34 AT28 VSS_243 VSS_333
VSS_063 VSS_153 E7 P38
AK35 VSS_064 VSS_154 AT29
eb VSS_244 VSS_334
E8 VSS_245 VSS_335 P40
AK36 VSS_065 VSS_155 AT3
F1 VSS_246 VSS_336 P5
AK37 VSS_066 VSS_156 AT30
F10 VSS_247 VSS_337 P6
AK4 VSS_067 VSS_157 AT31
F13 VSS_248 VSS_338 R33
AK40 VSS_068 VSS_158 AT32
F14 R35
ot
AK5 AT33 VSS_249 VSS_339
VSS_069 VSS_159 F17 R37
AK6 AT34 VSS_250 VSS_340
VSS_070 VSS_160 F2 R39
AK7 AT35 VSS_251 VSS_341
VSS_071 VSS_161 F20 R8
AK8 AT36 VSS_252 VSS_342
VSS_072 VSS_162
N

F23 VSS_253 VSS_343 T1

AK9 VSS_073 VSS_163 AT37
F26 VSS_254 VSS_344 T5
AL11 VSS_074 VSS_164 AT38
F29 VSS_255 VSS_345 T6
AL14 VSS_075 VSS_165 AT39
F35 VSS_256 VSS_346 U8
AL17 VSS_076 VSS_166 AT4
F37 VSS_257 VSS_347 V1
AL19 VSS_077 VSS_167 AT40
F39 VSS_258 VSS_348 V2
AL24 VSS_078 VSS_168 AT5
F5 VSS_259 VSS_349 V33
AL27 VSS_079 VSS_169 AT6
F6 VSS_260 VSS_350 V34
AL30 VSS_080 VSS_170 AT7
F9 VSS_261 VSS_351 V35
AL36 VSS_081 VSS_171 AT8
G11 VSS_262 VSS_352 V36
AL5 VSS_082 VSS_172 AT9
G12 VSS_263 VSS_353 V37
AM1 VSS_083 VSS_173 AU1
G17 VSS_264 VSS_354 V38
AM11 VSS_084 VSS_174 AU15
G20 VSS_265 VSS_355 V39
AM14 VSS_085 VSS_175 AU26
G23 VSS_266 VSS_356 V40
AM17 VSS_086 VSS_176 AU34
G26 V5
A AM2
AM21
VSS_087
VSS_088
VSS_177
VSS_178
AU4
AU6
G29
VSS_267
VSS_268
VSS_357
VSS_358 W6 A
G34 VSS_269 VSS_359 Y5 PAGE TITLE
AM23 AU8
AM25
VSS_089
VSS_090
VSS_179
VSS_180 AV10
G7 VSS_270 VSS_360 Y8 CPU GROUNDS
DRAWING NUMBER SIZE
1156
Apple Inc. 051-8442 D
1157 REVISION
SKT_MNT_HOLE R
1158 10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
14 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 14 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

15 6 =PP3V3_S0_PCH_STRAPS
15 6 =PP3V3_S0_PCH_STRAPS 15 6 =PP3V3_S0_PCH_STRAPS

NOSTUFF NOSTUFF NOSTUFF

R15221 NOSTUFF R15261 R15271 R15281
1 1 1 1 1 NOSTUFF
1 NOSTUFF
1 1 10K R15231 R15241 R15251 10K 10K 10K
R1519 R1591 R1508 R1507 R1503 R1504 R1506 R1509
D 10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
10K
5%
5%
1/16W
MF-LF
10K
5%
1/16W
10K
5%
1/16W
10K
5%
1/16W
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
D
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 402 MF-LF MF-LF MF-LF 402 402 402
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
2 402 402 402
2 2 2
402 402 402 402 402 402 402 402
2 2 2
2 2 2 2 2 2 2 2

MINI_CLKREQ_L 15 33 100

PCH_GPIO0_BMBUSY_L 21 25 JTAG_T29_TDO 21 89 99

PCH_GPIO19_SATA1GP 18 25 JTAG_T29_TDI 21 89 99

JTAG_T29_TCK 21 25 89 99 PCH_GPIO36_SATA2GP 21 25

DP_AUXCH_ISOL 18 25 85 87 94
T29_SW_RESET_L 21 81 94
FW_PME_L 21 39 100
PCH_GPIO7_TACH3 21
BLC_GPIO 6 21 94
NOSTUFF NOSTUFF PCH_GPIO49_SATA5GP 21 25
FW_PWR_EN 21 100
R15341 R15551
95 37 18 ENET_MEDIA_SENSE Multiplux with Mini FW_MINI_CLKREQ_L 15 18 94 10K 10K
5% 5%
100 37 21 ENET_LOW_PWR 1/16W 1/16W
MF-LF MF-LF

m
402 402
2 2

1 1
R1510 R1511
R15481

co
10K 10K
5% 5% 10K
1/16W 1/16W 5%
MF-LF
402
2
MF-LF
402
2
1/16W
MF-LF
R1595
402
2 FW_MINI_CLKREQ_L 1
0 2 MINI_CLKREQ_L
94 18 15 15 33 100

5%
1/16W

s.
MF-LF
NOSTUFF 402
R1596
0
C 1 2 FW_CLKREQ_L 39 100
C

ic
5%
1/16W
MF-LF 15 6 =PP3V3_S5_PCH_STRAPS
15 6 =PP3V3_S0_PCH_STRAPS 402 15 6 =PP3V3_S5_PCH_STRAPS

at
NOSTUFF 1 NOSTUFF 1 NOSTUFF
NOSTUFF NOSTUFF R1520 R1538 R15351 R15391 R15151
R15761 R15751 R15741 R15731 R15721 R15701 R15431 4.7K 4.7K 10K 10K 10K
10K 10K 10K 10K 10K 10K 4.7K 5% 5% 5% 5% 5%

em
5% 5% 5% 5% 5% 5% 5% 1/16W 1/16W 1/16W 1/16W 1/16W
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF MF-LF
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF 402 402 402 402 402
402 402 402 402 402 402 402
2 2 2 2 2
2 2 2 2 2 2 2
NOSTUFF
R15711 R15301 R15901 R15561
10K 10K 10K 10K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 402 402 402 PM_BATLOW_L 19 46 100

ch
PCH_SPKR 18
2 2 2 2
PCH_GPIO30_SUSWARN_L 19
PM_CLKRUN_L 19 46 48 100
ENET_CLKREQ_L 18 36 94

PCH_GPIO15 21 25
SDCARD_RESET 21 44 100 101
T29_CLKREQ_L 21 81 94 PCH_GPIO29_SLP_LAN_L 19
ENET_SW_RESET_L 21 36 94
PCH_GPIO24

kS
21
PCH_GPIO70_TACH6 21 PCH_GPIO8 21
SMC_WAKE_SCI_L 18 21 46 100
PCH_GPIO71_TACH7 21 NOSTUFF
JTAG_T29_TMS 18 89 99
HDA_SDOUT 18 56 94 R15171
New SP_DESCRIPTOR_OVERRIDE_L strap 10K
5%
1/16W
MF-LF
402
2

oo
93 25 10 CPU_CFG<2>
93 25 10 CPU_CFG<16> 93 25 10 CPU_CFG<6> NOSTUFF
1
R1592
B 93 25 10

93 25 10
CPU_CFG<3>
CPU_CFG<1>
93 25 10 CPU_CFG<5>
10K
5%
B
1/16W
93 25 10 CPU_CFG<0> MF-LF
eb 402
2

NOSTUFF1 NOSTUFF 1
NOSTUFF1 NOSTUFF 1 NOSTUFF 1 NOSTUFF 1 R1500 1
R1585 R1586 R1587 R1588 R1521 R1541 1K 19 PCH_FDI_FSYNC<0>
1K 1K 1K 1K 1K 1K 5%
5% 5% 5% 5% 5% 5% 1/16W 19 PCH_FDI_FSYNC<1>
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W MF-LF
PCH_FDI_INT
ot
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF 402 19
2
402 402 402 402 402 402
2 2 2 2 2 2 PCH_FDI_LSYNC<1>
19

19 PCH_FDI_LSYNC<0>
N

NOSTUFF 1 NOSTUFF 1
These can be Placed close to J2500 and Only for debug access NOSTUFF NOSTUFF NOSTUFF R1568 R1569
R1565 1 R1566 1 R15671 1K 1K
1K 1K 1K 5% 5%
5% 5% 5% 1/16W 1/16W
1/16W 1/16W 1/16W MF-LF MF-LF
MF-LF MF-LF MF-LF 402 402
402 402 402
2 2
2 2 2

REMOVE THESE PULL DOWN RESISTORS AFTER PROTO

10 CPU_FDI_FSYNC<0>
100 42 21 ODD_PWR_EN_L
10 CPU_FDI_FSYNC<1>
10 CPU_FDI_INT
20 PCH_PCI_GNT3_L
CPU_FDI_LSYNC<1>
A 20

20
PCH_PCI_GNT2_L
PCH_PCI_GNT1_L
10

10 CPU_FDI_LSYNC<0> SYNC_MASTER=K62_SIJI SYNC_DATE=01/09/2011 A

PAGE TITLE
20 PCH_PCI_GNT0_L
PCH_INIT3V3_L
NOSTUFF 1 NOSTUFF 1 STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
21 NOSTUFF NOSTUFF 1 NOSTUFF 1 R1563 R1564
R1560 1 R1561 R1562 1K 1K
DRAWING NUMBER SIZE

NOSTUFF NOSTUFF
1K
5% 5%
1K 1K
5%
5%
1/16W
5%
1/16W Apple Inc. 051-8442 D
NOSTUFF1 NOSTUFF1 NOSTUFF 1 1 1 REVISION
1 R1553 R1554 R1512 1/16W 1/16W 1/16W MF-LF MF-LF
R1550 R1551 R1552 10K 10K 10K
MF-LF
402
MF-LF
402
MF-LF
402
402
2 402
2 R
10.1.0
1K 10K 10K 5% 5% 5%
2 2 2
5% 5% 5% 1/16W 1/16W 1/16W NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/16W 1/16W 1/16W MF-LF MF-LF MF-LF
MF-LF MF-LF MF-LF 402
2 402
2 402
2 THE INFORMATION CONTAINED HEREIN IS THE
402
2
402
2
402
2 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
REMOVE THESE PULL DOWN RESISTORS AFTER PROTO I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
15 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 15 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CPU VCORE DECOUPLING

14x 22UF,0805 INTEL RECOMMENDATION 18X 22UF 0805 (14 Inside cavity and 4 North of processor) 10x 10UF and 10x 1UF CAPACITORS
PLACEMENT_NOTE (C1600-C1613):
65 50 16 13 6
=PPVCORE_S0_CPU Place inside socket cavity
16 13 6
65 50
=PPVCORE_S0_CPU Place inside socket cavity

1 C1620 1 C1621 1 C1622 1 C1623 1 C1624 1 C1625 1 C1626 1 C1627 1 C1628 1 C1629 D
D 1 C1600
22UF
1 C1601
22UF
1 C1602
22UF
1 C1603
22UF
1 C1604
22UF
1 C1605
22UF
1 C1606
22UF
1 C1607
22UF
1 C1608
22UF
1 C1609
22UF
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
10UF
20%
10V
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V 603 603 603 603 603 603 603 603 603 603
CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R
805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3

1 C1630 1 C1631 1 C1632 1 C1633 1 C1634 1 C1635 1 C1636 1 C1637 1 C1638 1 C1639
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
1
C1610 1
C1611 1
C1612 1
C1613 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
16V
2 X5R
22UF 22UF 22UF 22UF 402 402 402 402 402 402 402 402 402 402
20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
805-3 805-3 805-3 805-3

m
BULK CAPS ON CPU VREG PAGE 72

co
s.
CPU VCCIO DECOUPLING
C 8X 22UF 0805, 6X 10UF 0805 INTEL RECOMMENDATION 9X22UF 0805,16X 0805 placeholders C

ic
PLACEMENT_NOTE (C1650-C1657):
13 11 10 6 =PPVCCIO_S0_CPU

at
65 Place under socket cavity on secondary side.

1 C1650 1 C1651 1 C1652 1 C1653 1 C1654 1 C1655 1 C1656 1 C1657

22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF

em
20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
805 805 805 805 805 805 805 805

PLACEMENT_NOTE (C1660-C1665):

Place at edge of socket. BULK CAPS ON CPU VREG PAGE 72

ch
1
C1660 1
C1661 1
C1662 1
C1663 1
C1664 1
C1665
10uF 10uF 10uF 10uF 10uF 10uF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603

kS
oo
B 1
C1670
330UF-0.0045OHM B
20%
2 2V
POLY
CASE-D2-SM
eb
ot

Memory (CPU VCCDDR) DECOUPLING

6x 22uF 0805, 5x 1uF 0402. INTEL RECOMMENDATION 9X 22uF 0805

28 13 11 6
29
=PP1V5_S0_CPU_MEM Note: VCCSA decoupling is on regulator page
1 1 1 1 1 1 1 1 1 1 1
C1676 C1677 C1678 C1679 C1680 C1681 C1682 C1683 C1684 C1685 C1686
22uF 22uF 22uF 22uF 22uF 22uF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 10V 10V 10V 10V 10V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805 805 805 402 402 402 402 402

PLL (CPU VCCSFR) DECOUPLING

A 2x 47uF, 1x 22uF 0805, 1x 10uF 0603, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402. INTEL RECOMMENDATION 10x 10uF 0805
SYNC_MASTER=K62_AARON SYNC_DATE=N/A A
13 6 =PP1V8_S0_CPU_PLL PAGE TITLE

CPU NON-GFX DECOUPLING

DRAWING NUMBER SIZE
1 C1693 1 C1694 1 C1692 1 C1691 1 C1695 1 C1690 1 C1696 1 C1697
Apple Inc. 051-8442 D
1UF 1UF 2.2UF 4.7UF 10UF 22uF 47UF 47UF REVISION
10% 10% 10% 10% 20% 20% 20% 20%
R
2
10V
X5R 2
10V
X5R 2
6.3V
X5R 2
6.3V
X5R-CERM 2
6.3V
X5R 2
6.3V
CERM-X5R 2
6.3V
X5R 2
6.3V
X5R 10.1.0
402 402 402 603 603 805 0805 0805
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
BULK CAPS ON VTT REG PAGE 78 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
16 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 16 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
VAXG DECOUPLING
INTEL RECOMMENDATION 6X22UF 0805,3X 4.7UF
PLACEMENT_NOTE (C1704-C1709):

Place inside socket cavity

65 50 13 6 =PPVAXG_S0_CPU
VAXG VAXG VAXG VAXG VAXG VAXG
1
C1704 1
C1705 1
C1706 1
C1707 1
C1708 1
C1709
22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
805-3 805-3 805-3 805-3 805-3 805-3

m
co
OMIT VAXG VAXG
1
C1710 1
C1711 1
C1712
4.7UF 4.7UF 4.7UF
10% 10% 10%
6.3V 6.3V 6.3V
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
603 603 603

s.
C C

ic
BULK CAPS ON CPU VREG PAGE 73

at
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_ITEM

138S0586 1 CAP,4.7UF,10%,6.3V,0603 C1710 VAXG

TABLE_5_ITEM

em
113S0022 1 RES,0 OHM,5%,0603 C1710 NO_VAXG

ch
R1750
0
6 =PP3V3_S0_PCH_VCCADAC 1 2
PP3V3_S0_PCH_VCCA_DAC_F

kS
22 98
5% MAKE_BASE=TRUE
1/16W MIN_LINE_WIDTH=0.4 MM
MF-LF MIN_NECK_WIDTH=0.2 MM
402 VOLTAGE=3.3V

R1760

oo
0
6 =PP1V05_S0_PCH_VCCADPLL 1 2 PP1V05_S0_PCH_VCCADPLLA_F 22 98
MAKE_BASE=TRUE
5% MIN_LINE_WIDTH=0.4MM
1/16W MIN_NECK_WIDTH=0.2MM
B MF-LF
402
eb VOLTAGE=1.05V
B
R1765
0
1 2 PP1V05_S0_PCH_VCCADPLLB_F 22 98
MAKE_BASE=TRUE
5% MIN_LINE_WIDTH=0.4MM
1/16W MIN_NECK_WIDTH=0.2MM
MF-LF VOLTAGE=1.05V
402
ot
N

A SYNC_MASTER=K62_AARON SYNC_DATE=11/30/2009 A
PAGE TITLE

GFX DECOUPLING & PCH PWR ALIAS

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

1
94 LPC_R_AD<0> R1860 1 2 33 LPC_AD<0> PLACE THIS RESISTOR NEAR THE PCH PIN
R1890
R1830 1
BI 46 48 94
5% 1/16W MF-LF 402
BR39 OMIT BK15 90.9
PCH_CLK32K_RTCX1 RTCX1 FWH0/LAD0 37.4
94 27 IN
PCH_CLK32K_RTCX2 BN39 RTCX2
U1800 FWH1/LAD1
94
BJ17
LPC_R_AD<1> R1861 1
5% 1/16W
2 33 LPC_AD<1>
MF-LF 402
BI 46 48 94
1
1%
MF-LF 1%
1/16W
94 27 OUT
COUGAR-POINT R1820 1/16W
OMIT
FWH2/LAD2 BJ20 LPC_R_AD<2> R1862 1 2 33 LPC_AD<2>
BI 46 48 94
10K
MF-LF
PCIE_ENET_D2R_N J20 PERN1 SMBALERT*/GPIO11 BN49 PCH_GPIO11_SMBALERT_L
402
2
WLCSP
SYM 1 OF 10 FWH3/LAD3 BG20
5% 1/16W MF-LF 402
5%
402
2
95 37 IN
PCIE_ENET_D2R_P L20 PERP1
U1800 18

94 LPC_R_AD<3> R1863 1 2 33 LPC_AD<3>

BI 46 48 94
1/16W
MF-LF
95 37 IN
COUGAR-POINT SMBCLK BT47 SMBUS_PCH_CLK 49 97
RTC_RESET_L BT41 RTCRST* 5% 1/16W MF-LF 402
PCIE_ENET_R2D_C_N F25 PETN1 OUT
100 27 18
FWH4/LFRAME* BG17 2
402 95 37 OUT WLCSP SMBDATA BR49 SMBUS_PCH_DATA
94 LPC_FRAME_R_L R1864 1 2 33 LPC_FRAME_L
OUT 46 48 94
95 37 PCIE_ENET_R2D_C_P F23 PETP1 BI 49 97

100 18 PCH_SRTCRST_L BN37 SRTCRST* 5% 1/16W MF-LF 402 OUT SYM 2 OF 10

LDRQ0* BK17 TP_LPC_DREQ0_L

RTC
LPC
8

D 18 PCH_INTRUDER_L BM38 INTRUDER* LDRQ1*/GPIO23 BA20 T29_PWR_EN 81 100

93 33

93 33
IN
IN
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
P20
R20
PERN2
PERP2
SML0ALERT*/GPIO60 BU49 SML_PCH_0_ALERT_L 18
D
BN41 SML0CLK BT51 SML_PCH_0_CLK 49 97
100 18 PCH_INTVRMEN_L INTVRMEN SERIRQ AV52 LPC_SERIRQ 46 48 93 33 PCIE_MINI_R2D_C_N C22 PETN2 OUT
BI OUT
A22 SML0DATA BM50 SML_PCH_0_DATA BI 49 97
93 33 OUT PCIE_MINI_R2D_C_P PETP2

94 18 HDA_BIT_CLK_R BU22 HDA_BCLK SATA0RXN AC56 SATA_HDD_D2R_N 42 93 93 39 PCIE_FW_D2R_N H17 PERN3 SML1ALERT*/PCHHOT*/GPIO74 BR46 SML_PCH_1_ALERT_L 18
IN IN
SATA0RXP AB55 SATA_HDD_D2R_P PCIE_FW_D2R_P J17 PERP3

SMBUS
IN 42 93 93 39 IN
BP23 AE46 E21 SML1CLK/GPIO58 BJ46 SML_PCH_1_CLK OUT 49 97
94 18 HDA_SYNC_R HDA_SYNC SATA0TXN SATA_HDD_R2D_C_N 42 93 93 39 PCIE_FW_R2D_C_N PETN3
AE44
OUT OUT
B21 SML1DATA/GPIO75 BK46 SML_PCH_1_DATA BI 49 97
SATA0TXP SATA_HDD_R2D_C_P OUT 42 93 93 39 OUT PCIE_FW_R2D_C_P PETP3
15 PCH_SPKR BE56 SPKR
SATA1RXN AA53 SATA_SSD_D2R_N 42 93 8 TP_PCIE_D2R_PERN4 P17 PERN4
IN IN
SATA1RXP AA56 SATA_SSD_D2R_P TP_PCIE_D2R_PERP4 M17 PERP4

IHDA
94 18 HDA_RST_R_L BC22 HDA_RST* IN 42 93 8 IN
SATA1TXN AG49 SATA_SSD_R2D_C_N 42 93 8 TP_PCIE_R2D_PETN4 F18 PETN4
OUT OUT
SATA1TXP AG47 SATA_SSD_R2D_C_P 42 93 8 TP_PCIE_R2D_PETP4 E17 PETP4
HDA_SDIN0 BD22 OUT OUT
94 56 IN HDA_SDIN0
8 TP_HDA_SDIN1 BF22 HDA_SDIN1 SATA2RXN AL50 SATA_ODD_D2R_N 42 93 99 89 PCIE_T29_D2R_N<0> N15 PERN5
IN IN
TP_HDA_SDIN2 BK22 HDA_SDIN2 SATA2RXP AL49 SATA_ODD_D2R_P PCIE_T29_D2R_P<0> M15 PERP5

PEG
8 42 93 99 89
IN IN
CLKOUT_PEG_A_N AG8 PEG_CLK100M_N

m
OUT 9
8 TP_HDA_SDIN3 BJ22 HDA_SDIN3 SATA2TXN AL56 SATA_ODD_R2D_C_N 42 93 99 89 PCIE_T29_R2D_C_N<0> B17 PETN5
AL53
OUT OUT
C16 CLKOUT_PEG_A_P AG9 PEG_CLK100M_P OUT 9
SATA2TXP SATA_ODD_R2D_C_P OUT 42 93 99 89 OUT PCIE_T29_R2D_C_P<0> PETP5
94 18 HDA_SDOUT_R BT23 HDA_SDO
SATA3RXN AN46 TP_SATA_D_D2RN 8 99 89 PCIE_T29_D2R_N<1> J15 PERN6
IN
CLKOUT_DMI_N P31 DMI_CLK100M_CPU_N 11 93

co
AN44 TP_SATA_D_D2RP PCIE_T29_D2R_P<1> L15 OUT
BC25 SATA3RXP 8 99 89 PERP6
99 89 15 JTAG_T29_TMS HDA_DOCK_EN*/GPIO33 AN56
IN
A16 CLKOUT_DMI_P R31 DMI_CLK100M_CPU_P OUT 11 93
BA25 SATA3TXN TP_SATA_D_R2D_CN 8 99 89 OUT PCIE_T29_R2D_C_N<1> PETN6

SATA
95 37 15 ENET_MEDIA_SENSE HDA_DOCK_RST*/GPIO13 AM55 B15
SATA3TXP TP_SATA_D_R2D_CP 8 99 89 OUT PCIE_T29_R2D_C_P<1> PETP6
AN49 J12 CLKOUT_DP_N N56 TP_PCH_CLKOUT_DPN OUT 8
BA43 SATA4RXN TP_SATA_E_D2RN 8 99 89 PCIE_T29_D2R_N<2> PERN7
CLKOUT_DP_P M55
XDP_PCH_TCK IN TP_PCH_CLKOUT_DPP
94 25 JTAG_TCK AN50 H12 OUT 8
TP_SATA_E_D2RP PCIE_T29_D2R_P<2>

PCI-E*
s.
SATA4RXP 8 99 89 IN PERP7
94 25 XDP_PCH_TMS BC50 JTAG_TMS JTAG SATA4TXN AT50 TP_SATA_E_R2D_CN 8 99 89 PCIE_T29_R2D_C_N<2> F15 PETN7
OUT

FROM CLK BUFFER

SATA4TXP AT49 TP_SATA_E_R2D_CP PCIE_T29_R2D_C_P<2> F13 PETP7 CLKIN_DMI_N P33 PCH_CLK100M_DMI_N
94 25 XDP_PCH_TDI BC52 JTAG_TDI
8 99 89 OUT IN 26 93

CLKIN_DMI_P R33
C AT46 TP_SATA_F_D2RN PCIE_T29_D2R_N<3> H10 PCH_CLK100M_DMI_P IN 26 93
C

ic
BF47 SATA5RXN 8 99 89 IN PERN8
94 25 XDP_PCH_TDO JTAG_TDO AT44 J10
SATA5RXP TP_SATA_F_D2RP 8 99 89 IN PCIE_T29_D2R_P<3> PERP8
SATA5TXN AV50 TP_SATA_F_R2D_CN 8 99 89 PCIE_T29_R2D_C_N<3> B13 PETN8 CLKIN_DOT_96N BD38 PCH_CLK96M_DOT_N 26 93
OUT IN
SATA5TXP AV49 TP_SATA_F_R2D_CP 8 99 89 PCIE_T29_R2D_C_P<3> D13 PETP8 CLKIN_DOT_96P BF38 PCH_CLK96M_DOT_P 26 93
OUT IN

at
55 48 SPI_CLK_R R1822 1 2 22 94 SPI_CLK_1_R AR54 SPI_CLK TOTAL_ETCH_LENGTH=5 MM
94 OUT
SATAICOMPO AJ53 94 PCH_SATAICOMP 93 37 PCIE_CLK100M_ENET_N AE6 CLKOUT_PCIE0N
5% 1/16W MF-LF 402
AT57 PLACE R1830 AT BALL AJ53 OUT
CLKIN_SATA_N AF55 PCH_CLK100M_SATA_N IN 26 93
SATAICOMPI AJ55 AC6
TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS
94 48 SPI_CS0_R_L SPI_CS0* 93 37 PCIE_CLK100M_ENET_P CLKOUT_PCIE0P
OUT OUT
CLKIN_SATA_P AG56 PCH_CLK100M_SATA_P
SPI

IN 26 93

em
TP_SPI_CS1_L AR56 SPI_CS1* 93 33 PCIE_CLK100M_MINI_N AA5 CLKOUT_PCIE1N
SATALED* BF57 PCH_SATALED_L OUT
18 42 W5
PCIE_CLK100M_MINI_P CLKOUT_PCIE1P
SPI_MOSI_R R1823
93 33 OUT
55 48 1 2 22 SPI_MOSI_1_R AU53 SPI_MOSI REFCLK14IN AN8 PCH_CLK14P3M_REFCLK 26 94
SATA0GP/GPIO21 BC54
94 OUT DP_AUXCH_ISOL IN
5% 1/16W MF-LF 402 15 25 85 87 94 AB12
AT55 =PP1V05_S0_PCH 6 24 80 93 39 OUT PCIE_CLK100M_FW_N CLKOUT_PCIE2N
94 55 48 IN SPI_MISO SPI_MISO SATA1GP/GPIO19 AY52 PCH_GPIO19_SATA1GP 15 25 AB14
93 39 PCIE_CLK100M_FW_P CLKOUT_PCIE2P
CLKIN_PCILOOPBACK BD15
OUT PCH_CLK33M_PCIIN IN 27 94
1
R1831 94 15 FW_MINI_CLKREQ_L AV43 PCIECLKRQ2*/GPIO20
DOES THIS NEED LENGTH MATCH???

L_BKLTCTL AG12 TP_PCH_L_BKLTCTL 49.9 IN

ch
1%
L_BKLTEN AG18 TP_PCH_L_BKLTEN 8 1/16W 99 89 OUT PCIE_CLK100M_T29_N AB9 CLKOUT_PCIE3N XTAL25_IN AJ3 PCH_CLK25M_XTALIN IN 27 80 94
MF-LF
L_VDD_EN AG17 TP_PCH_L_VDD_EN 8 402
2 99 89 OUT PCIE_CLK100M_T29_P AB8 CLKOUT_PCIE3P XTAL25_OUT AJ5 PCH_CLK25M_XTALOUT OUT 27 94

SATA3COMPI AE54 8 OUT TP_PCIE_CLK100M_PE4N Y9 CLKOUT_PCIE4N

TOTAL_ETCH_LENGTH=5 MM TOTAL_ETCH_LENGTH=5 MM
SATA3RCOMP0 AE52 94 PCH_SATA3COMP 8 OUT TP_PCIE_CLK100M_PE4P Y8 CLKOUT_PCIE4P XCLK_RCOMP AL2 94 PCH_XCLK_RCOMP
PLACE R1831 AT BALL AE52 PLACE R1890 AT BALL AL2

kS
SATA3RBIAS AC52 94 PCH_SATA3RBIAS AF3
8 OUT TP_PCIE_CLK100M_PE5N CLKOUT_PCIE5N
TP_PCIE_CLK100M_PE5P AG2 CLKOUT_PCIE5P CLKOUTFLEX0/GPIO64 AT9 DP_GPU_T29_SEL

CLOCK
8 OUT 61 84 94

FLEX
98 27 22 19 PP3V3_G3H_RTC R18321 94 36 15 ENET_CLKREQ_L BL54 PCIECLKRQ5*/GPIO44
CLKOUTFLEX1/GPIO65 BA5
=PP3V3_S0_SATALED 750 IN TP_PCH_GPIO65_CLKOUTFLEX1
42 6
1% AE12
1/16W TP_DMI_MIDBUS_CLK100M_PEGB1N CLKOUT_PEG_B_N

oo
MF-LF AE11
1 1
402
2
TP_DMI_MIDBUS_CLK100M_PEGB1P CLKOUT_PEG_B_P CLKOUTFLEX2/GPIO66 AW5 TP_PCH_GPIO66_CLKOUTFLEX2
R1802 R1803 PLACE R1832 AT BALL AC52
20K 20K
CLKOUTFLEX3/GPIO67 BA2
B 5%
1/16W
MF-LF
5%
1/16W
MF-LF
R18501
TP_PCH_GPIO67_CLKOUTFLEX3
B
402 402 10K
2 2
5% CLKOUT_ITPXDP_N R52 ITPXDP_CLK100M_N 18 25 93
1/16W
MF-LF
eb CLKOUT_ITPXDP_P N52 ITPXDP_CLK100M_P 18 25 93
402
1 1 2
R1800 R1801 CLKIN_GND0_N W53 PCH_CLKIN_GNDN0
390K 1M
5% 5% CLKIN_GND0_P V52 PCH_CLKIN_GNDP0
1/16W 1/16W
MF-LF MF-LF RTC_RESET_L 18 27 100
402 402 CLKIN_GND1_N R27 PCH_CLKIN_GNDN1
2 2 PCH_SRTCRST_L
ot
18 100
CLKIN_GND1_P P27 PCH_CLKIN_GNDP1
PCH_INTRUDER_L 18

PCH_INTVRMEN_L 18 100 CL_CLK1 BA50 TP_PCH_CL_CLK1 8

NOSTUFF
PCH_SATALED_L 18 42
R1840 CL_DATA1 BF50 TP_PCH_CL_DATA1 8
N

C1802 1 1
C1803 0
1UF 1UF 93 25 18 ITPXDP_CLK100M_N 1 2 ITPCPU_CLK100M_N 11 93
CL_RST1* BF49 TP_PCH_CL_RST1 8
10% 10%
10V 10V 5%
X5R 2 2 X5R 1/16W NOSTUFF
MF-LF
402 402
R1841
R18721
402 1
0 R1873
R18701
1
93 25 18 ITPXDP_CLK100M_P 1 2 ITPCPU_CLK100M_P 11 93 R1871 10K 10K
5% 10K 10K 5% 5%
1/16W 5% 5% 1/16W 1/16W
MF-LF 1/16W 1/16W MF-LF MF-LF
MF-LF MF-LF 402
402
402 402
2 2 402
2 2

PLACE THESE 33 OHM RESISTORS CLOSE TO PCH (MIN 500MIL)

24 21 19 6 =PP3V3_S5_PCH
R1810
33
94 18 HDA_BIT_CLK_R 1 2 HDA_BIT_CLK OUT 56 94

A PLACE R1880 CLOSE TO R1813

5%
1/16W
MF-LF
402 R1811 SYNC_MASTER=K62_SIJI SYNC_DATE=01/09/2011 A
33 1 1 1 PAGE TITLE
R1853 R1854 R1855
R1880
0
94 18 HDA_SYNC_R 1

5%
2 HDA_SYNC OUT 56 94
10K
5%
10K
5%
10K
5%
PCH SATA/PCIE/CLK/LPC/SPI
94 18 HDA_SDOUT_R 1 2 SPI_DESCRIPTOR_OVERRIDE_L OUT 46 100 1/16W 1/16W 1/16W 1/16W DRAWING NUMBER SIZE
MF-LF
5% R1812 402 NOSTUFF
MF-LF MF-LF MF-LF
051-8442 D
1/16W 33 2 402 2 402 2 402 Apple Inc.
MF-LF
402
94 18 HDA_RST_R_L 1 2 HDA_RST_L OUT 56 94
SMC_WAKE_SCI_L
R1895 REVISION
100 46 21 15 R

NOSTUFF
5%
1/16W
1
0
2 PCH_GPIO11_SMBALERT_L
10.1.0
MF-LF
402 R1813 5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/16W
33 MF-LF THE INFORMATION CONTAINED HEREIN IS THE
94 18 HDA_SDOUT_R 1 2 HDA_SDOUT OUT 15 56 94 402 18 SML_PCH_0_ALERT_L PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5%
1/16W
MF-LF
18 SML_PCH_1_ALERT_L I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
18 OF 110
402 SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 18 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

=PP3V3_S5_PCH 6 18 19 21 24

=PP1V05_S0_PCH_VCCIO_PCIE 6 18 22 24

1
R1905 1
10K R1900
5% 49.9
1/16W 1%
MF-LF 1/16W
402 MF-LF
2
2
402 OMIT OMIT
D33 C42 J57 SDVO_TVCLKINN U9
93 10 IN DMI_N2S_N<0>
A36
DMI0RXN U1800 FDI_RXN0
F45
TP_PCH_FDI_RX_N<0> 8 TP_PCH_RESERVE_0
U43
RESERVED_0 U1800 TP_SDVO_TVCLKINN 8

93 10 IN DMI_N2S_N<1> DMI1RXN COUGAR-POINT FDI_RXN1 TP_PCH_FDI_RX_N<1> 8 TP_PCH_RESERVE_1 RESERVED_1 COUGAR-POINT SDVO_TVCLKINP U8 TP_SDVO_TVCLKINP 8
WLCSP
D 93 10

93 10
IN
IN
DMI_N2S_N<2>
DMI_N2S_N<3>
B37
E37
DMI2RXN
DMI3RXN
SYM 3 OF 10
FDI_RXN2
FDI_RXN3
H41
C46
TP_PCH_FDI_RX_N<2>
TP_PCH_FDI_RX_N<3>
8

8
TP_PCH_RESERVE_2
TP_PCH_RESERVE_3
M49
M50
RESERVED_2
RESERVED_3
WLCSP
SYM 4 OF 10 SDVO_STALLN U5 TP_SDVO_STALLN 8 D
B45 R50 SDVO_STALLP W3 TP_SDVO_STALLP 8
B33 FDI_RXN4 TP_PCH_FDI_RX_N<4> 8 TP_PCH_RESERVE_4 RESERVED_4
93 10 IN DMI_N2S_P<0> DMI0RXP B47 Y41
B35 FDI_RXN5 TP_PCH_FDI_RX_N<5> 8 TP_PCH_RESERVE_5 RESERVED_5 SDVO_INTN T3 TP_SDVO_INTN 8
93 10 DMI_N2S_P<1> DMI1RXP J43 H50 SDVO_INTP U2
IN TP_PCH_FDI_RX_N<6> TP_PCH_RESERVE_6 TP_SDVO_INTP
C36 FDI_RXN6 8 RESERVED_6 8
93 10 IN DMI_N2S_P<2> DMI2RXP M43 U44
F38 FDI_RXN7 TP_PCH_FDI_RX_N<7> 8 TP_PCH_RESERVE_7 RESERVED_7
93 10 IN DMI_N2S_P<3> DMI3RXP U46
B43 TP_PCH_RESERVE_8 RESERVED_8 SDVO_CTRLCLK AL15 TP_DP_IG_B_DDC_CLK 8
FDI_RXP0 TP_PCH_FDI_RX_P<0> 8
U50
J36 F43 TP_PCH_RESERVE_9 RESERVED_9 SDVO_CTRLDATA AL17 TP_DP_IG_B_DDC_DATA 8
93 10 OUT DMI_S2N_N<0> DMI0TXN FDI_RXP1 TP_PCH_FDI_RX_P<1> 8 R44
P38 J41 TP_PCH_RESERVE_10 RESERVED_10
93 10 OUT DMI_S2N_N<1> DMI1TXN FDI_RXP2 TP_PCH_FDI_RX_P<2> 8 U49 DDPB_AUXN R9 TP_DP_IG_B_AUX_N 8
H38 D47 TP_PCH_RESERVE_11 RESERVED_11
93 10 OUT DMI_S2N_N<2> DMI2TXN FDI_RXP3 TP_PCH_FDI_RX_P<3> 8 AB44 DDPB_AUXP R8 TP_DP_IG_B_AUX_P 8
M41 A46 TP_PCH_RESERVE_12 RESERVED_12
93 10 OUT DMI_S2N_N<3> DMI3TXN FDI_RXP4 TP_PCH_FDI_RX_P<4> 8
AB49 DDPB_HPD T1 TP_DP_IG_B_HPD 8
TP_PCH_RESERVE_13 RESERVED_13

DMI
FDI
C49

DIGITAL DISPLAY INTERFACE

H36 FDI_RXP5 TP_PCH_FDI_RX_P<5> 8 E52 R12
93 10 OUT DMI_S2N_P<0> DMI0TXP H43 TP_PCH_RESERVE_14 RESERVED_14 DDPB_0N TP_DP_IG_B_MLN<0> 8
R38 FDI_RXP6 TP_PCH_FDI_RX_P<6> 8 H52 R14 EXTERNAL DP
93 10 OUT DMI_S2N_P<1> DMI1TXP P43 TP_PCH_RESERVE_15 RESERVED_15 DDPB_0P TP_DP_IG_B_MLP<0> 8
J38 FDI_RXP7 TP_PCH_FDI_RX_P<7> 8 F53 M12
93 10 OUT DMI_S2N_P<2> DMI2TXP TP_PCH_RESERVE_16 RESERVED_16 DDPB_1N TP_DP_IG_B_MLN<1> 8

DMI_S2N_P<3> P41 TP_PCH_RESERVE_17 J55 M11 TP_DP_IG_B_MLP<1>

m
93 10 OUT DMI3TXP RESERVED_17 DDPB_1P 8
FDI_INT H46 PCH_FDI_INT OUT 15
L56 K8
TP_PCH_RESERVE_18 RESERVED_18 DDPB_2N TP_DP_IG_B_MLN<2> 8
A32 H8
PCH_DMI2RBIAS
94 DMI2RBIAS FDI_FSYNC0 B51 PCH_FDI_FSYNC<0> OUT 15 TP_PCH_RESERVE_19 K46 RESERVED_19 DDPB_2P TP_DP_IG_B_MLP<2> 8
PLACE R1920 AT BALL A32
FDI_FSYNC1 C52 PCH_FDI_FSYNC<1> OUT 15 TP_PCH_RESERVE_20 Y50 RESERVED_20 DDPB_3N M3 TP_DP_IG_B_MLN<3> 8

co
1 TP_PCH_RESERVE_21 AB50 RESERVED_21 DDPB_3P L5 TP_DP_IG_B_MLP<3>
R1920 94 PCH_DMI_COMP E31 DMI_ZCOMP FDI_LSYNC0 E49 PCH_FDI_LSYNC<0> OUT 15 L53
8

750 SHORT THESE TWO PINS VERY NEAR THE PINS B31 TP_PCH_RESERVE_22 RESERVED_22
1% PLACE THE RESISTOR VERY CLOSE TO COMMON POINT DMI_IRCOMP FDI_LSYNC1 D51 PCH_FDI_LSYNC<1> 15 Y44
1/16W PLACE R1900 AT BALL E31 OUT TP_PCH_RESERVE_23 RESERVED_23 DDPC_CTRLCLK AL12 TP_DP_IG_C_CTRL_CLK 8
MF-LF TOTAL_ETCH_LENGTH=5 MM G56
2 402 TP_PCH_RESERVE_24 RESERVED_24 DDPC_CTRLDATA AL14 TP_DP_IG_C_CTRL_DATA 8

SYSTEM POWER
100 46 27 25 PM_SYSRST_L BE52 SYS_RESET* WAKE* BC44 PCIE_WAKE_L 19 33 36 79 100 TP_PCH_RESERVE_25 AB46 RESERVED_25
IN IN
DDPC_AUXN U12 TP_DP_IG_C_AUX_N

s.
MANAGEMENT
K49 8
BJ53 TP_PCH_RESERVE_26 RESERVED_26
100 64 32 IN PM_SYS_PWRGD SYS_PWROK CLKRUN*/GPIO32 BC56 PM_CLKRUN_L BI 15 46 48 100 K50 DDPC_AUXP U14 TP_DP_IG_C_AUX_P 8
TP_PCH_RESERVE_27 RESERVED_27
BJ38 M48 DDPC_HPD N2 TP_DP_IG_C_HPD 8
100 64 21 IN PM_PCH_PWRGD PWROK TP_PCH_RESERVE_28 RESERVED_28
C J3 TP_DP_IG_C_MLN<0> C

ic
BG46 DDPC_0N
SUS_STAT*/GPIO61 BN54
8
100 11 OUT PM_MEM_PWRGD DRAMPWROK LPC_PWRDWN_L OUT 46 48 100 L2
DDPC_0P TP_DP_IG_C_MLP<0> 8
BT37 INTERNAL DP
100 19 IN PM_DSW_PWRGD DPWROK SUSCLK/GPIO62 BA47 PM_CLK32K_SUSCLK_R OUT 9 94 100 DDPC_1N G4 TP_DP_IG_C_MLN<1> 8

DDPC_1P G2 TP_DP_IG_C_MLP<1> 8
BC46 SLP_S5*/GPIO63 BH50

at
100 64 IN PM_ASW_PWRGD APWROK PM_SLP_S5_L OUT 5 46 47 63 100 F5
DDPC_2N TP_DP_IG_C_MLN<2> 8

100 27 19 PM_RSMRST_PCH_L BK38 RSMRST* SLP_S4* BN52 PM_SLP_S4_L 5 32 46 47 63 100 DDPC_2P F3 TP_DP_IG_C_MLP<2> 8
IN OUT
DDPC_3N E2 TP_DP_IG_C_MLN<3> 8
15 PCH_GPIO30_SUSWARN_L BU46 SUSWARN*/SUSPWRDNACK/GPIO30 SLP_S3* BM53 PM_SLP_S3_L 5 26 32 36 46 47 63 100
OUT
DDPC_3P E4 TP_DP_IG_C_MLP<3>

em
8

100 46 25 PM_PWRBTN_L BT43 PWRBTN* SLP_A* BC41 TP_PM_SLP_A_L

IN
KEEPING TP, IF NEED TO USE IT LATER
BG43 DDPD_CTRLCLK AL9 TP_DP_IG_D_CTRL_CLK 8
19 PCH_GPIO31_ACPRESENT GPIO31 TP23 J25 TP_PCH_TP23
IN
DDPD_CTRLDATA AL8 TP_DP_IG_D_CTRL_DATA 8

100 46 15 PM_BATLOW_L AV46 BATLOW*/GPIO72 PMSYNCH F55 PM_SYNC 11 100 8 TP_CRT_IG_BLUE AM1 CRT_BLUE
DDPD_AUXN R6
IN OUT TP_DP_IG_D_AUXN
AN2 8
BJ48 8 TP_CRT_IG_GREEN CRT_GREEN
PCH_RI_L RI* SLP_LAN*/GPIO29 BH49 PCH_GPIO29_SLP_LAN_L 15 AN6 DDPD_AUXP N6 TP_DP_IG_D_AUXP 8
8 TP_CRT_IG_RED CRT_RED
DDPD_HPD M1

ch
TP_DP_IG_D_HPD 8

CRT
1 DF_TVS R47 PCH_DF_TVS 19 100 AW3 B5
R1909 8 TP_CRT_IG_DDC_CLK CRT_DDC_CLK DDPD_0N TP_DP_IG_D_MLN<0> 8
10K 8 TP_CRT_IG_DDC_DATA AW1 CRT_DDC_DATA DDPD_0P D5 TP_DP_IG_D_MLP<0> 8
5%
1/16W
DDPD_1N D7 TP_DP_IG_D_MLN<1> 8
MF-LF
DSWVRMEN BR42 PCH_DSWVRMEN 19 100 AR4 C6
402 TP_CRT_IG_HSYNC CRT_HSYNC DDPD_1P TP_DP_IG_D_MLP<1>

kS
2 8 8
BD43 AR2 C9
SLP_SUS* TP_PCH_SLP_SUS_L 8 TP_CRT_IG_VSYNC CRT_VSYNC DDPD_2N TP_DP_IG_D_MLN<2> 8

DDPD_2P B7 TP_DP_IG_D_MLP<2> 8
SUSACK* BP45 TP_PCH_SUSACK_L AT3 B11
PCH_DAC_IREF DAC_IREF DDPD_3N TP_DP_IG_D_MLN<3> 8
AM6 CRT_IRTN DDPD_3P E11 TP_DP_IG_D_MLP<3> 8
1
R1951

oo
1K
5%
1/16W
MF-LF
B eb 2 402
PLACE CLOSE TO U1800 PIN
B

PP3V3_G3H_RTC 18 22 27 98

1
R1915 R1990
0
ot
390K 100 27 19 PM_RSMRST_PCH_L 2 1 PM_DSW_PWRGD 19 100
5%
1/16W 5%
MF-LF 1/16W =PP1V8_S0_PCH 6
402 MF-LF
2 402
N

=PP3V3_S5_PCH 6 18 19 21 24
1
R1981
=PP3V3_S5_PCH 6 18 19 21 24
1
2.2K
PCH_DSWVRMEN 19 100 R1925 5%
1/16W
1K MF-LF
1% 402
1/16W 2
1
R1961 MF-LF
402
10K 2
5% R1980
1/16W 4.7K
MF-LF 100 19 PCH_DF_TVS 2 1 CPU_PROC_SEL 11 100
402
2 5%
NOSTUFF 1/16W
MF-LF
R1960 402

2
0 1
PCIE_WAKE_L 19 33 36 79 100
100 47 46 SMC_ADAPTER_EN PCH_GPIO31_ACPRESENT 19

5%
A 1/16W
MF-LF
402
A
PAGE TITLE

PCH DMI/FDI/GRAPHICS
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

OMIT
BF15 USBP0N BF36
8 TP_PCI_AD<0>
BF17
AD0 U1800 USB_HUB1_UP_N BI 34 95

8 TP_PCI_AD<1> AD1 COUGAR-POINT USBP0P BD36 USB_HUB1_UP_P BI 34 95

USB HUB 1
8 TP_PCI_AD<2> BT7 AD2 WLCSP
BT13 SYM 5 OF 10 USBP1N BC33 TP_USB_1N BI 8
8 TP_PCI_AD<3> AD3
BG12 USBP1P BA33 TP_USB_1P BI 8
Unused
8 TP_PCI_AD<4> AD4
8 TP_PCI_AD<5> BN11 AD5 USBP2N BM33 TP_USB_2N 8
BI
8 TP_PCI_AD<6> BJ12 AD6 USBP2P BM35 TP_USB_2P 8
Unused
BI

D 8

8
TP_PCI_AD<7>
TP_PCI_AD<8>
BU9
BR12
AD7
AD8
USBP3N BT33 TP_USB_3N BI 8 D
BJ3 USBP3P BU32 TP_USB_3P BI 8
Unused
8 TP_PCI_AD<9> AD9
8 TP_PCI_AD<10> BR9 AD10 USBP4N BR32 TP_USB_4N 8
BI Unused
8 TP_PCI_AD<11> BJ10 AD11 USBP4P BT31 TP_USB_4P 8
BI
8 TP_PCI_AD<12> BM8 AD12
BF3 USBP5N BN29 TP_USB_5N BI 8
8 TP_PCI_AD<13> AD13 Unused
BN2 USBP5P BM30 TP_USB_5P BI 8
8 TP_PCI_AD<14> AD14
8 TP_PCI_AD<15> BE4 AD15 USBP6N BK33 TP_USB_6N 8
BI
BE6 Unused
8 TP_PCI_AD<16> AD16 USBP6P BJ33 TP_USB_6P BI 8

8 TP_PCI_AD<17> BG15 AD17

BC6 USBP7N BF31 TP_USB_7N BI 8
8 TP_PCI_AD<18> AD18 Unused
BT11 USBP7P BD31 TP_USB_7P BI 8
8 TP_PCI_AD<19> AD19
8 TP_PCI_AD<20> BA14 AD20 USBP8N BN27 USB_HUB2_UP_N 35 95
BI
BL2 USB HUB 2
8 TP_PCI_AD<21> AD21 USBP8P BR29 USB_HUB2_UP_P BI 35 95

TP_PCI_AD<22> BC4

m
8 AD22
BL4 USBP9N BR26 USB_CAMERA_N BI 44 95
8 TP_PCI_AD<23> AD23
BC2 USBP9P BT27 USB_CAMERA_P BI 44 95
USB CAMERA
8 TP_PCI_AD<24> AD24
8 TP_PCI_AD<25> BM13 AD25 USBP10N BK25 TP_USB_10N 8
BI
Unused

co
8 TP_PCI_AD<26> BA9 AD26 USBP10P BJ25 TP_USB_10P 8
BI
8 TP_PCI_AD<27> BF9 AD27 =PP3V3_S5_PCH_GPIO 6
BA8 USBP11N BJ31 TP_USB_11N BI 8
8 TP_PCI_AD<28> AD28 Unused
USBP11P BK31 TP_USB_11P

USB
BI 8
TP_PCI_AD<29> BF8 AD29 1 1
8
R2061 1 1PRODUCTION R2068
8 TP_PCI_AD<30> AV17 AD30 USBP12N BF27 TP_USB_12N 8 10K R2063 R2065 10K
BI

s.
BK12 Unused 5% 10K 10K 5%
8 TP_PCI_AD<31> AD31 USBP12P BD27 TP_USB_12P BI 8 1/16W 5% 5% 1/16W
MF-LF 1/16W 1/16W MF-LF
402 MF-LF MF-LF
8 TP_PCI_C_BE_L<0> BN4 C/BE0* USBP13N BJ27 TP_USB_13N 8
2
402 402
2 402
BI 2 2
BP7 Unused
USBP13P BK27 R20601
C 8 TP_PCI_C_BE_L<1> C/BE1* TP_USB_13P BI 8 R2062 1 1
C

ic
TP_PCI_C_BE_L<2> BG2 R2066
8 C/BE2* 10K
5%
10K
5%
R2064 1 10K
45 20 6 =PP3V3_S0_PCH_GPIO 8 TP_PCI_C_BE_L<3> BP13 C/BE3* USBRBIAS* BP25 94 PCH_USB_RBIAS 1/16W 1/16W 10K 5%
TIE TRACES TOGETHER CLOSE TO PINS MF-LF MF-LF 5% 1/16W
BK10 USBRBIAS BM25 402 402 1/16W MF-LF
R2010 10K 1 2 PCI_INTA_L PIRQA* PLACE THE RESISTOR CLOSE TO COMMON POINT
2 2
MF-LF 402

at
2
5% 1/16W MF-LF 402 BJ5 402
R2011 10K 1 2 PCI_INTB_L PIRQB* 2
5% 1/16W MF-LF 402 BM15 BM43
R2012 10K PCI_INTC_L AP_PWR_EN

PCI
1 2 PIRQC* OC0*/GPIO59 25 33 100
5% 1/16W MF-LF 402 BP5 BD41
R2013 10K 1 2 PCI_INTD_L PIRQD* OC1*/GPIO40 USB_HUB_SOFT_RESET_L 25 34 100
5% 1/16W MF-LF 402 BG41
OC2*/GPIO41 T29_DP_PORTA_PWR_EN 25 83 94 100

em
R2015 10K 1 2 94 PCI_REQ0_L BG5 REQ0*
5% 1/16W MF-LF 402 OC3*/GPIO42 BK43 ENET_PWR_EN
R2016 10K 1 2 94 PCI_REQ1_L BT5 REQ1*/GPIO50
25 36 100

5% 1/16W MF-LF 402 OC4*/GPIO43 BP43 T29_DP_PORTB_PWR_EN 25 83 94

94 20 PCI_REQ2_L BK8 REQ2*/GPIO52
OC5*/GPIO9 BJ41 SDCONN_STATE_CHANGE 25 45 100
R2018 10K 1 2 PCI_REQ3_L AV11 REQ3*/GPIO54
5% 1/16W MF-LF 402 OC6*/GPIO10 BT45 PCH_GPIO10_OC6_L 25

15 PCH_PCI_GNT0_L BA15 GNT0* OC7*/GPIO14 BM45 PCH_GPIO14_OC7_L 25

15 PCH_PCI_GNT1_L AV8 GNT1*/GPIO51

ch
15 PCH_PCI_GNT2_L BU12 GNT2*/GPIO53
15 PCH_PCI_GNT3_L BE2 GNT3*/GPIO55 1
R2070
R2030 10K 1 2 100 51 USE_HDD_OOB_L BN9 PIRQE*/GPIO2 22.6
5% 1/16W MF-LF 402 AV9 1%
100 61 AUD_IP_PERIPHERAL_DET PIRQF*/GPIO3 1/16W

kS
BT15 MF-LF
R2031 10K 1 2 94 87 85 T29_MCU_INT_L PIRQG*/GPIO4 402
2
5% 1/16W MF-LF 402 BR4
100 62 AUD_I2C_INT_L PIRQH*/GPIO5

8 TP_PCI_RESET_L AV14 PCIRST*

PLACE R2070 AT BALL BM25
R2020 10K 1 2 PCI_SERR_L BR6 SERR*
5% 1/16W MF-LF 402 BM3
R2021 10K

oo
1 2 PCI_PERR_L PERR*
5% 1/16W MF-LF 402
R2022 10K 1 2 PCI_IRDY_L BF11 IRDY*
5% 1/16W MF-LF 402 BH8
B R2023 10K 1 2
8 TP_PCI_PAR
PCI_DEVSEL_L BH9
PAR
DEVSEL*
B
5% 1/16W MF-LF 402 BC11
R2024 10K 1 2 PCI_FRAME_L FRAME*
5% 1/16W MF-LF 402
eb
R2027 10K 1 2 PCI_PLOCK_L BA17 PLOCK*
5% 1/16W MF-LF 402
R2025 10K 1 2 PCI_STOP_L BC12 STOP*
5% 1/16W MF-LF 402 BC8
R2026 10K 1 2 PCI_TRDY_L TRDY*
5% 1/16W MF-LF 402
TP_PCI_PME_L AV15
ot
PME*

100 27 PLT_RESET_L BK48 PLTRST*

OUT
PCH SATA PORT 1 OPTION SELECT IS ODD OR SSD
94 27 LPC_CLK33M_SMC_R AT11 CLKOUT_PCI0
OUT
AN14
N

LPC_CLK33M_LPCPLUS_R
20 PCI_REQ2_L R2017 10K ODD_SATA:P2
1 2 =PP3V3_S0_PCH_GPIO 6 20 45
94 27 OUT CLKOUT_PCI1
94 5% 1/16W MF-LF 402 TP_PCI_CLK33M_OUT2 AT12 CLKOUT_PCI2
TP_PCI_CLK33M_OUT3 AT17
R2098 10K ODD_SATA:P1
1 2
CLKOUT_PCI3
5% 1/16W MF-LF 402 94 27 PCH_CLK33M_PCIOUT AT14 CLKOUT_PCI4
OUT

A SYNC_MASTER=K62_SIJI SYNC_DATE=01/09/2011 A
PAGE TITLE

PCH PCI/FLASHCACHE/USB
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

24 21 18 6 =PP3V3_S0_PCH

OMIT
AW55 =PP3V3_S0_PCH 6 18 21 24
25 15 PCH_GPIO0_BMBUSY_L BMBUSY*/GPIO0 U1800 CLKOUT_PCIE6N AB3 TP_PCIE_CLK100M_PE6N 8

D R2190
1 100 39 15 FW_PME_L BR19 TACH1/GPIO1 COUGAR-POINT
WLCSP
CLKOUT_PCIE6P AA2 TP_PCIE_CLK100M_PE6P 8
D
47K BLC_GPIO BA22 TACH2/GPIO6 SYM 6 OF 10 CLKOUT_PCIE7N AE2 TP_PCIE_CLK100M_PE7N R2150 1
5%
R2134 94 15 6 OUT 8
10K
1/16W
1
0
2 BR16 CLKOUT_PCIE7P AF1 TP_PCIE_CLK100M_PE7P 8 5%
1
MF-LF 100 47 46 SMC_RUNTIME_SCI_L 15 PCH_GPIO7_TACH3 TACH3/GPIO7 1/16W R2155
402 1/16W MF-LF MF-LF
2 5% 402 10K
402 15 PCH_GPIO8 BP51 GPIO8 MISC A20GATE BB57 PCH_A20GATE
NOSTUFF
2
5%
1/16W

100 37 15 ENET_LOW_PWR BK50 LAN_PHY_PWR_CTRL/GPIO12 R2170 MF-LF

402
0 2

BM55 PECI H48 PCH_PECI 1 2 CPU_PECI 11 46 100

25 15 PCH_GPIO15 GPIO15 1/16W MF-LF
5% Place this near the T point
402

CPU
94 25 21 AUD_IPHS_SWITCH_EN_PCH AU56 SATA4GP/GPIO16 RCIN* BG56 PCH_RCIN_L
BT17
R2140
48 LPCPLUS_GPIO TACH0/GPIO17 0
IN
PROCPWRGD D53 100 PCH_PROCPWRGD 1 2 CPU_PWRGD OUT 11 25 100
1/16W MF-LF
100 42 15 ODD_PWR_EN_L BA53 SCLOCK/GPIO22 5%
402
BP53 THRMTRIP* E56 PM_THRMTRIP_L IN 47 100
15 IN PCH_GPIO24 GPIO24/MEM_LED

m
100 46 18 15 SMC_WAKE_SCI_L BJ43 GPIO27
TP1 P22 TP_PCH_TP1
100 32 25 ISOLATE_CPU_MEM_L BJ55 GPIO28
OUT
TP2 L31 TP_PCH_TP2

GPIO
94 81 15 T29_SW_RESET_L BL56 STP_PCI*/GPIO34

co
TP3 L33 TP_PCH_TP3
100 25 5 MXM_GOOD BJ57 GPIO35
TP4 M38 TP_PCH_TP4
25 15 PCH_GPIO36_SATA2GP BB55 SATA2GP/GPIO36
TP5 L36 TP_PCH_TP5
99 89 25 15 JTAG_T29_TCK BG53 SATA3GP/GPIO37
TP6 Y18 TP_PCH_TP6

s.
99 89 15 JTAG_T29_TDO BE54 SLOAD/GPIO38
TP7 Y17 TP_PCH_TP7
99 89 15 JTAG_T29_TDI BF55 SDATAOUT0/GPIO39
TP8 AB18
C TP_PCH_TP8
C

ic
94 21 PCH_PEG_CLKREQ_L AV44 PCIECLKRQ6*/GPIO45
TP9 AB17 TP_PCH_TP9
94 81 15 T29_CLKREQ_L BP55 PCIECLKRQ7*/GPIO46
TP10 BM46 TP_PCH_TP10
AW53

at
100 15 FW_PWR_EN SDATAOUT1/GPIO48
TP11 BA27 TP_PCH_TP11
25 15 PCH_GPIO49_SATA5GP BA56 SATA5GP/GPIO49
TP12 BC49 TP_PCH_TP12
94 48 SPIROM_USE_MLB BT53 GPIO57
TP13 AE49 TP_PCH_TP13

em
101 100 44 15 SDCARD_RESET BU16 TACH4/GPIO68
TP14 AE41 TP_PCH_TP14
94 36 15 ENET_SW_RESET_L BM18 TACH5/GPIO69
TP15 AE43 TP_PCH_TP15
15 PCH_GPIO70_TACH6 BN17 TACH6/GPIO70 6 =PP3V3_S3_PCH
TP16 AE50 TP_PCH_TP16
15 PCH_GPIO71_TACH7 BP15 TACH7/GPIO71
TP17 BA36 TP_PCH_TP17

ch
5 MC74VHC1G08
AUD_IPHS_SWITCH_EN_PCH 1 SOT23-5-HF
TP18 AY36

RSVD
94 25 21
BN21 TP_PCH_TP18
TP_PCH_PWM0 AUD_IPHS_SWITCH_EN
8
BT21
PWM0
U2100 4 62 100

8 TP_PCH_PWM1 PWM1 TP19 Y14 TP_PCH_TP19 100 64 19 PM_PCH_PWRGD 2

8 TP_PCH_PWM2 BM20 PWM2
BN19 TP20 Y12 TP_PCH_TP20 3
TP_PCH_PWM3 PWM3

kS
8

TP21 H31 TP_PCH_TP21

8 TP_PCH_SST BC43 SST
C2110 1
TP22 J27 TP_PCH_TP22 0.1UF
20%
10V
2
TP24 L22
CERM
TP_PCH_TP24 402

TP25 J31

oo
TP_PCH_TP25
A4 VSS_NCTF_0
A6 TP26 L27 TP_PCH_TP26
VSS_NCTF_1
B B2
BM1
VSS_NCTF_2 TP27 L25 TP_PCH_TP27 B
VSS_NCTF_3
BM57 TP28 J22 TP_PCH_TP28
eb VSS_NCTF_4

NCTF
BP1 VSS_NCTF_5 TP29 C29 TP_PCH_TP29
BP57 VSS_NCTF_6
BT2 TP30 F28 TP_PCH_TP30
VSS_NCTF_7
BU4 VSS_NCTF_8 TP31 C26 TP_PCH_TP31
BU52
ot
VSS_NCTF_9
BU54 TP32 B25 TP_PCH_TP32
VSS_NCTF_10
BU6 VSS_NCTF_11 TP33 E29 TP_PCH_TP33
D1 VSS_NCTF_12
F1 TP34 E27 TP_PCH_TP34
N

VSS_NCTF_13
A54 TP35 B27 TP_PCH_TP35
TS_VSS1
A52 TS_VSS2 TP36 D25 TP_PCH_TP36
F57 TS_VSS3
D57 NC_1 AY20 TP_PCH_NC
TS_VSS4

=PP3V3_S0_MXM 6 64 76 77
AU2 VSSADAC INIT3_3V* BN56 PCH_INIT3V3_L 15
24 19 18 6 =PP3V3_S5_PCH
THIS SIGNAL IS INTEDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
This has internal pull up and should not pulled low.
1
R2161
10K Q2100
5%
G 1

1/16W SSM3K15FV
MF-LF
2 402 SOD-VESM-HF

PCH_PEG_CLKREQ_L PEG_CLKREQ_L
D

A 94 21 9
A
3

SYNC_MASTER=K62_SIJI SYNC_DATE=01/09/2011
2

PAGE TITLE

NOSTUFF
PCH MISC
R2160 DRAWING NUMBER SIZE

1
0
2 Apple Inc. 051-8442 D
1/16W MF-LF REVISION
5% R
402 10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE

MXM CLKREQ ISOLATION I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
21 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 21 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT

U1800 OMIT
COUGAR-POINT
WLCSP U1800
SYM 10 OF 10 COUGAR-POINT
TP_1V05_S0_PCH_VCCA_CLK AL5 VCCACLK WLCSP
VCCIO_2 AY25 =PP1V05_S0_PCH_VCCIO_USB 6 24
AV41 AY27 SMY 7 OF 10
TP_PPVOUT_PCH_DCPSUSBYP DCPSUSBYP VCCIO_3
PP3V3_S0_PCH_VCCA_DAC_F

CRT
PCH output, for decoupling only VCCIO_0 AV24 98 17

98 PPVOUT_G3_PCH_DCPRTC
BR54 DCPRTC Max and Idle = 1 MA AT1 VCCADAC VCCCORE_0 AC24 =PP1V05_S0_PCH_VCC_CORE 6 24
PLACE C2210 AT BR54 VCCIO_1 AV26

CLOCK AND MISCELLANEOUS

MIN_NECK_WIDTH=0.2 mm AC26
MIN_LINE_WIDTH=0.2 mm VCCCORE_1 1.44 A Max, 474mA Idle
D 1
C2210
0.1UF
VOLTAGE=3.3V
BT56

R54
DCPRTC_NCTF
VCCSUS3_3_0 U31 =PP3V3_S5_PCH_VCCSUS3_3_USB 6 24
98 24 22 PP1V8R1V5_S0_PCH_VCCVRM_F
159mA Max, 114mA Idle R56
VCCCORE_2 AC28
AC30
D
PP1V8R1V5_S0_PCH_VCCVRM_F

DMI
20%
98 24 22 VCCVRM_2 AV30 97mA Max, 15mA Idle (VCCVRM 4 total) VCCVRM_1 VCCCORE_3
10V VCCSUS3_3_1 AC32
2 CERM AB1 AV32 (VCCSUS3_3 - 11 TOTAL) E41 VCCCORE_4
PP1V05_S0_PCH_VCCADPLLA_F VCCADPLLA VCCSUS3_3_2 =PP1V05_S0_PCH_VCC_DMI VCCDMI_0

USB

VCC CORE
98 17 24 6
402
40mA Max, 5mA Idle VCCCORE_5 AE24
VCCSUS3_3_3 AY31 57 mA Max, 30mA Idle B41 VCCDMI_1
98 17 PP1V05_S0_PCH_VCCADPLLB_F AC2 VCCADPLLB VCCCORE_6 AE28
40mA Max, 10mA Idle VCCSUS3_3_4 AY33
VCCCORE_7 AE30

VCCIO_DMI/CLK
VCCSUS3_3_5 BJ36
24 6 =PP1V05_S0_PCH_VCCIO_DMI Y30 VCCIO_26 VCCCORE_8 AE32
VCCSUS3_3_6 BK36
Y32 VCCIO_27 VCCCORE_9 AE34
VCCSUS3_3_7 BM36
AA34 VCCIO_16 VCCCORE_10 AE36
VCCSUS3_3_8 AT40
Y34 VCCIO_28 VCCCORE_11 AG32
VCCSUS3_3_9 AU38
AA36 VCCIO_17 VCCCORE_12 AG34
VCCSUS3_3_10 BT35
Y36 VCCIO_9 VCCCORE_13 AJ32
PCH output, for decoupling only V33 VCCIO_23 VCCCORE_14 AJ34
PLACE CAP AT BALL BA46 BA46
98 PPVOUT_S0_PCH_DCPSST DCPSST V5REF_SUS BT25 =PP5V_S5_PCH_V5REFSUS 24
V36 VCCIO_10 VCCCORE_15 AJ36
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V Max and Idle = 1mA V31 AL32
AA32 VCCIO_22 VCCCORE_16
TP_DCPSUS_0

m
DCPSUS_0

PCI/GPIO/LPC
1
C2222 F30 VCCIO_19 VCCCORE_17 AL34
TP_DCPSUS_1 AT41 DCPSUS_1
0.1UF
20% A39 V5REF BF1 =PP5V_S0_PCH_V5REF 24 VCCCORE_18 AN32
10V
98 PPVOUT_S5_PCH_DCPSUS DCPSUS_2 Max and Idle = 1mA AN34
2 MIN_LINE_WIDTH=0.2 mm VCCCORE_19
CERM
MIN_NECK_WIDTH=0.2 mm VCC3_3_7 A12 =PP3V3_S0_PCH_VCC3_3_PCI 6 24

CPU PCI/GPIO/LPC
402
VOLTAGE=1.05V 24 6 =PP3V3_S0_PCH_VCC3V3 AF57 VCC3_3_0 VCCCORE_20 AR32

co
VCC3_3_8 AU20 409 mA Max, 42mA Idle B53 AR34
1
C2230 PLACE C2230 AT BALL A39 (VCC3_3[1-9] total) PP1V05_S0_PCH_VCCAPLL_EXP_F VCCAPLLEXP VCCCORE_21
VCC3_3_9 AV20
98 24
0.1UF 24 6 =PP3V3_S0_PCH_VCC3_3_GPIO
AL38 VCC3_3_4

HVCMOS
FDI
20% PP1V8R1V5_S0_PCH_VCCVRM_F AJ1 =PP3V3_S0_PCH_VCC3_3_SATA
10V NOSTUFF AN38 98 24 22 VCCVRM_0 6 24
2 VCC3_3_5
CERM
402 Need to check layout decoupling AU22 VCC3_3_1 BC17
VCC3_3_6
VCC3_3_2 BD17

s.
VCCIO_8 AJ38 =PP1V05_S0_PCH_VCCIO_SATA 6 18 24 VCC3_3_3 BD20
24 6 =PP1V05_S0_PCH_VCCASW AU32 VCCASW_0
VCCIO_12 AE40
1.61A Max, 433mA Idle AV36 VCCASW_1
VCCIO_15 AG40
AU34
C AG38 VCCASW_2
C

SATA

ic
VCCIO_14 AG24
D55 AG41 VCCASW_3 VCCAFDIPLL C54 TP_1V05_S0_PCH_FDIPLL
24 6 =PP1V05_S0_PCH_V_PROC_IO V_PROC_IO VCCIO_4 AG26
Max and Idle = 1mA B56 BA38 VCCASW_4
V_PROC_IO_NCTF VCCIO_13 AG28 VCCAPLLDMI2 A19 PP1V05_S0_PCH_VCCAPLLDMI2_F 24 98
AN40 VCCASW_5

VCCASW
VCCIO_6 AJ24 VCCCLKDMI AJ20 PP1V05_S0_PCH_VCCCLKDMI_F

at
VCCASW_6
BU42 RTC VCCIO_7 AN41
AJ26 20mA Max, 10mA Idle
24 98

98 27 19 18 PP3V3_G3H_RTC VCCRTC AL40 VCCASW_7

PLACE C2231 AT BALL BU42 VCCIO_5 AJ28
PLACE C2232 AT BALL BU42 VCCASW_8 Y20 =PP1V05_S0_PCH_VCCIO_PCIE

VCCIO_PCIE
T55 AL24 VCCIO_30 6 18 19 24
24 6 =PP3V3R1V8_S0_PCH_VCCDFTERM VCCDFTERM_0 VCCASW_9 Y22 3.456A Max, 426mA Idle
200 mA Max, 2mA Idle VCCIO_31 (VCCIO[1-31] total)

em
T57 VCCDFTERM_1 AL28 VCCASW_10
1
C2231 1
C2232 VCCIO_24 Y24
VCCAPLLSATA U56 PP1V05_S0_PCH_VCCAPLL_SATA_F 24 98
AN22 VCCASW_11
1UF
10%
0.1UF
20%
24 6 =PP1V05_S0_PCH_VCCDIFFCLK AE15 VCCDIFFCLKN_0 AN24 VCCIO_25 Y26
6.3V 10V 55mA Max, 5mA Idle AE17 VCCASW_12 Y28
2 CERM 2 CERM VCCDIFFCLKN_1 AN26 VCCIO_11
402 402 AG15 VCCASW_13 V22
VCCDIFFCLKN_2 VCCIO_29
VCCVRM_3 R2 PP1V8R1V5_S0_PCH_VCCVRM_F 22 24 98
AN28 VCCASW_14 V25
AV40 AR24 VCCIO_20
24 6 =PP3V3_S5_PCH_VCCDSW VCCDSW3_3 VCCASW_15 V27
3mA Max, 1mA Idle AR26 VCCIO_21

ch
AN52 VCCASW_16 F20
24 6 =PP3V3_S5_PCH_VCCSPI VCCSPI VCCIO_18
20mA Max, 1mA Idle VCCSUSHDA AV28 PP3V3R1V5_PCH_VCCSUSHDA 24 98
AR28 VCCASW_17
HDA

AC20 10 mA Max, 1mA Idle AR30

24 6 =PP1V05_S0_PCH_VCCSSC VCCSSC_0 VCCASW_18
105mA Max, 90mA Idle AE20 AR36
VCCSSC_1 VCCASW_19
AR38 VCCASW_20

kS
AU30 VCCASW_21
AU36 VCCASW_22

oo
B eb B
ot
N

A A
PAGE TITLE

PCH POWER
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

OMIT
OMIT
AE56 AN12
BG38 J46
BR36 U1800 AN15
BH52
U1800 J48
C12 COUGAR-POINT AN17
BH6
COUGAR-POINT J5
AY22 WLCSP AN18 WLCSP
SYM 8 OF 10 BJ1 SYM 9 OF 10 J53
A26 AN20

D A29
A42
AN30
AN36
BJ15
BK20
K52
K6 D
BK41 K9
A49 AN4
BK52 L12
A9 AN43
BK6 L17
AA20 AN47
BM10 L38
AA22 AN54
BM12 L41
AA24 AN9
BM16 L43
AA26 AR20
BM22 M20
AA28 AR22
BM23 M22
AA30 AR52
BM26 M25
AA38 AR6
BM28 M27
AB11 AT15
BM32 M31
AB15 AT18
BM40 M33
AB40 AT43
BM42 M36
AB41 AT47
BM48 M46

m
AB43 AT52
BM5 M52
AB47 AT6
BN31 M57
AB52 AT8
BN47 M6
AB57 AU24

co
BN6 M8
AB6 AU26
BP3 M9
AC22 AU28
BP33 N4
AC34 AU5
BP35 N54
AC36 AV12
BR22 R11
AC38 AV18

s.
BR52 R15
AC4 AV22
BU19 R17
AC54 AV34
BU26 R22
AE14 AV38
C BU29 R4
C

ic
AE18 AV47
BU36 R41
AE22 AV6
BU39 R43
AE26 AW57
C19 R46
AE38 AY38

at
C32 R49
AE4 AY6
C39 T52
AE47 B23
C4 T6
AE8 BA11
VSS VSS D15 U11

em
AE9 BA12 VSS VSS
D23 U15
AF52 BA31
D3 U17
AF6 BA41
D35 U20
AG11 BA44
D43 U22
AG14 BA49
D45 U25
AG20 BB1
E19 U27
AG22 BB3

ch
E39 U33
AG30 BB52
E54 U36
AG36 BB6
E6 U38
AG43 BC14
E9 U41
AG44 BC15
F10 U47

kS
AG46 BC20
F12 U53
AG5 BC27
F16 V20
AG50 BC31
F22 V38
AG53 BC36
F26 V6
AH52 BC38
F32 W1
AH6 BC47

oo
F33 W55
AJ22 BC9
F35 W57
AJ30 BD25
B AJ57
AK52
BD33
BF12
F36
F40
Y11
Y15 B
F42 Y38
AK6 BF20
eb F46 Y40
AL11 BF25
F48 Y43
AL18 BF33
F50 Y46
AL20 BF41
F8 Y47
AL22 BF43
G54 Y49
AL26 BF46
ot
H15 Y52
AL30 BF52
H20 Y6
AL36 BF6
H22 AL43
AL41 BG22
H25 AL44
AL46 BG25
N

H27 R36
AL47 BG27
H33 P36
AM3 BG31
H6 R25
AM52 BG33
J1 P25
AM57 BG36
J33
AN11

A SYNC_MASTER=K62_AARON SYNC_DATE=07/01/2009 A
PAGE TITLE

PCH GROUNDS
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

REVISION
R
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
23 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 23 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH VCCSUS3_3 BYPASS
22 18 6 =PP1V05_S0_PCH_VCCIO_SATA
22 6 =PP3V3R1V8_S0_PCH_VCCDFTERM
R2400 (PCH SUSPEND USB 3.3V PWR)
80 6 =PP1V8R1V5_S0_PCH_VCCVRM
0 22 6 =PP3V3_S5_PCH_VCCSUS3_3_USB 1
1
C2444 1
C2452 1
C2453
1 2 98 22 PP1V8R1V5_S0_PCH_VCCVRM_F C2440 1UF 1UF 1UF
MIN_LINE_WIDTH=0.5MM 0.1UF
5% MIN_NECK_WIDTH=0.25MM
1 1 1
1 C2412 20%
10%
6.3V
10%
6.3V
10%
6.3V
1/16W VOLTAGE=1.8V
1 C2484 C2455 C2413 2.2UF 10V 2 CERM 2 CERM 2 CERM
MF-LF MAKE_BASE=TRUE 1 C2436 1 C2443 C2445 0.1UF 2.2UF 0.1UF 2 CERM 402 402 402
402 1 C2447 1UF 1UF 10UF 10% 10% 10%
10%
6.3V PLACEMENT_NOTE: 402
2
0.1UF 10% 10% 20%
2
16V
2
16V
2
16V X5R
PLACE C2440 AT BALL T55
10% 6.3V 6.3V 6.3V X5R X5R X5R 402
16V 2 CERM 2 CERM CERM 2 402 603 402
2 X5R 402 402 805-1 PLACEMENT_NOTEs:
402
PLACEMENT_NOTEs: PLACE C2452 AT BALL AG38
PLACE C2453 AT BALL AJ38
PLACE C2484 AT BALL U31 PCH VCCSUSHDA BYPASS PLACE C2444 AT BALL BA38
PLACEMENT_NOTEs: PLACE C2455 AT BALL AV30
D PLACE C2447 AT BALL
PLACE C2436 AT BALL
PLACE C2443 AT BALL
R56
R54
AJ1
PLACE C2413 AT BALL
PLACE C2415 AT BALL
BT35
AT40
(PCH HD Audio 3.3V/1.5V PWR)
D
PLACE C2445 AT BALL R2 98 24 22 PP3V3R1V5_PCH_VCCSUSHDA

80 18 6 =PP1V05_S0_PCH
NOSTUFF
L2401
1
C2441 22 6 =PP1V05_S0_PCH_VCCSSC
0.1UF
1.0UH-0.5A PLACEMENT_NOTE: 20%
2
10V 1 C2475 C2480 1
1 2 PP1V05_S0_PCH_VCCAPLL_EXP_F 22 98 22 6 =PP1V05_S0_PCH_V_PROC_IO PLACE C2441 AT BALL AV28 CERM
MIN_LINE_WIDTH=0.5MM
402 1UF 10UF
1210 MIN_NECK_WIDTH=0.25MM
10% 20%
6.3V 6.3V
VOLTAGE=1.05V 2 CERM CERM 2
MAKE_BASE=TRUE 402 805-1
NOSTUFF
NOSTUFF C2416 1 1 C2417 1 C2430
1
C2489 4.7UF 0.1UF 0.1UF
C2400 1
1UF 20% 10% 10%
10UF 10%
PLACE C2489 AT BALL B53 6.3V 16V 16V
10% 6.3V X5R 2 2 X5R 2 X5R PLACEMENT_NOTEs:
16V 2 CERM 402 402 402
X5R-CERM 2 402
0805 PLACE C2475 AT BALL AE20
22 6 =PP3V3_S5_PCH_VCCSPI PLACE C2480 AT BALL AC20
PLACEMENT_NOTEs (all 3):
1 C2442

m
PLACE C2416 AT BALL D55
PLACE C2417 AT BALL D55 1UF
PLACE C2430 AT BALL B56 10%
6.3V
PLACEMENT_NOTE: 2 CERM
PCH VCCIO BYPASS 402 22 6 =PP1V05_S0_PCH_VCCDIFFCLK
NOSTUFF PLACE C2442 AT BALL AN52
(PCH DMI 1.05V PWR)
L2404

co
1 C2434 1 C2435 C2437 1
1.0UH-0.5A
1UF 1UF 10UF
1 2 22 6 =PP1V05_S0_PCH_VCC_DMI 10% 10% 20%
6.3V 6.3V 6.3V
2 CERM 2 CERM CERM 2
1210
PP1V05_S0_PCH_VCCAPLLDMI2_F 402 402 805-1
22 98
MIN_LINE_WIDTH=0.5MM PLACEMENT_NOTE: 1
C2419 1
C2487

s.
NOSTUFF MIN_NECK_WIDTH=0.25MM 1UF 1UF
NOSTUFF VOLTAGE=1.05V PLACE C2419 AT BALL B41 PLACEMENT_NOTEs:
1
C2488 MAKE_BASE=TRUE PLACE C2487 AT BALL E41 10%
6.3V
10%
6.3V
C2406 1
1UF 2 CERM 2 CERM 22 6 =PP3V3_S5_PCH_VCCDSW
10UF 10% 402 402 PLACE C2434 AT BALL AE15
6.3V PLACE C2435 AT BALL AE17
C
10%
16V 2 CERM
C2499 1 PLACE C2437 AT BALL AE15
C

ic
X5R-CERM 2 402
0805 PLACE C2488 AT BALL A19 0.1UF
PCH VCC3_3 BYPASS 20%
10V
CERM 2
(PCH PCI 3.3V PWR) PLACEMENT_NOTE: 402

at
PLACE C2499 AT BALL AV40 PCH VCCIO BYPASS
NOSTUFF
PCH VCCSATAPLL Filter (PCH USB 1.05V PWR)
L2405 (PCH SATA PLL PWR)
10UH-0.45A 22 6 =PP1V05_S0_PCH_VCCIO_USB

em
1 2 PP1V05_S0_PCH_VCCAPLL_SATA_F 22 98
MIN_LINE_WIDTH=0.5MM
1210 MIN_NECK_WIDTH=0.25MM 22 19 18 6 =PP1V05_S0_PCH_VCCIO_PCIE 1
C2446 1
C2449 1
C2450
VOLTAGE=1.05V
NOSTUFF MAKE_BASE=TRUE 22 6 =PP3V3_S0_PCH_VCC3V3 1UF 1UF 1UF
NOSTUFF 10% 10% 10%
6.3V 6.3V 6.3V
C2408 1
1
2 CERM 2 CERM 2 CERM
10UF C2409 402 402 402
10% 1UF 1
C2423
16V
2
10% 1
C2429 1
C2414 1
C2407 1
C2463 C2401 1 C2410 1 C2415 1
X5R-CERM
2
16V 0.1UF PLACEMENT_NOTEs:
1UF 1UF 1UF 1UF 10UF 10UF 10UF

ch
0805 X5R 10%
402 PLACEMENT_NOTE: PLACEMENT_NOTEs: 16V 10% 10% 10% 10% 20% 20% 20%
2 X5R 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
PLACE C2409 AT BALL U56 402 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 CERM 2 CERM 2 PLACE C2446 AT BALL AY25
PLACE C2423 AT BALL AF57 402 402 402 402 805 805-1 805-1 PLACE C2449 AT BALL AY27
PLACE C2450 AT BALL AV26

L2406
10UH-0.45A R2415

kS
1 2 1
PP1V05_S0_PCH_VCCCLKDMI_L 1 2 PP1V05_S0_PCH_VCCCLKDMI_F 22 98 PCH VCCCORE BYPASS
1210-HF
MIN_LINE_WIDTH=0.5MM MIN_LINE_WIDTH=0.5MM (PCH 1.05V CORE PWR)
MIN_NECK_WIDTH=0.25MM 5% MIN_NECK_WIDTH=0.25MM PLACEMENT_NOTEs: 22 6 =PP1V05_S0_PCH_VCC_CORE
VOLTAGE=1.05V 1/16W VOLTAGE=1.05V
MF-LF MAKE_BASE=TRUE
402 C2448 1
22 6 =PP3V3_S0_PCH_VCC3_3_GPIO PLACE C2410 AT BALL Y20 1 1 1 1 1
10UF 1 PLACE C2415 AT BALL F20 C2481 C2482 C2483 C2460 C2461
10%
C2411 PLACE C2429 AT BALL Y24 1UF 1UF 1UF 10UF 10UF
16V 1UF PLACE C2414 AT BALL Y26
1
C2486 1
C2485 10% 10% 10% 20% 20%

oo
X5R-CERM 2
10%
PLACE C2407 AT BALL Y28 6.3V 6.3V 6.3V 6.3V 6.3V
0805 16V PLACE C2411 AT BALL AJ20 0.1UF 0.1UF PLACE C2401 AT BALL V22 2 CERM 2 CERM 2 CERM CERM 2 CERM 2
2 X5R 10% 10%
PLACE C2463 AT BALL V25 402 402 402 805-1 805-1
402 25V 25V
2 2
B X5R
402
X5R
402 B
PLACEMENT_NOTE:

21 18 6 =PP3V3_S0_PCH
eb PLACE C2485 AT BALL AL38
PLACE C2486 AT BALL AU22
PLACEMENT_NOTEs:
PLACE C2482 AT BALL AC24
6 =PP5V_S0_PCH PCH V5REF Filter & Follower 22 6 =PP1V05_S0_PCH_VCCASW PLACE C2461 AT BALL AR32
PLACE C2481 AT BALL AC32
1 mA (PCH Reference for 5V Tolerance on PCI) PLACE C2460 AT BALL AJ34
1 PLACE C2483 AT BALL AL34
R2405 2 5 D2400 22 6 =PP3V3_S0_PCH_VCC3_3_PCI
100 NC
ot
5% BAT54DW-X-G
NC

1/16W
1
C2426 1
C2456 1
C2496 1
C2498 C2418 1 C2420 1 C2428 1
SOT-363 1
MF-LF 6 C2421 1
C2422 1UF 1UF 1UF 1UF 10UF 10UF 10UF
402
1 0.1UF 1UF 10% 10% 10% 10% 20% 20% 20%
10% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V =PP1V05_S0_PCH_VCCIO_DMI
PLACEMENT_NOTEs: 16V 6.3V 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 CERM 2 CERM 2 22 6
PP5V_S0_PCH_V5REF 98 2 X5R 2 CERM 402 402 402 402 805-1 805-1 805-1
MIN_LINE_WIDTH=0.3MM
N

402 402
MIN_NECK_WIDTH=0.25MM <1 MA PLACE C2421 AT BALL A12 1 1 1
VOLTAGE=5V PLACE C2422 AT BALL AU20 1
C2470 1
C2469 C2473 C2472 C2471
C2439 1 MAKE_BASE=TRUE
1UF 1UF 10UF 10UF 10UF
1UF =PP5V_S0_PCH_V5REF 10% 10% 20% 20% 20%
10% 22 6.3V 6.3V 6.3V 6.3V 6.3V
10V 2 CERM 2 CERM CERM 2 CERM 2 CERM 2
X5R 2 402 402 805-1 805-1 805-1
402
PLACEMENT_NOTE: PLACEMENT_NOTEs:
PLACE C2439 AT BALL BF1
PLACE C2420 AT BALL AU32
PLACE C2428 AT BALL AJ24
PLACE C2426 AT BALL AU30
PLACE C2456 AT BALL AG28 PLACEMENT_NOTEs:
PLACE C2496 AT BALL AR36
PLACE C2418 AT BALL AN32 PLACE C2469 AT BALL V36
PLACE C2498 AT BALL AR24 PLACE C2471 AT BALL AA34
PLACE C2470 AT BALL Y32
PLACE C2472 AT BALL V31
21 19 18 6 =PP3V3_S5_PCH PLACE C2473 AT BALL F30
6 =PP5V_S5_PCH PCH V5REF_SUS Filter & Follower
NOSTUFF
1 mA S0-S5 (PCH Reference for 5V Tolerance on USB) R2406
2 4 0
R2404 2 D2400 6
=PP3V3R1V5_S0_PCH_VCCSUSHDA 1 2 PP3V3R1V5_PCH_VCCSUSHDA 22 24 98
10
A 5%
NC BAT54DW-X-G 5%
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4MM
A
NC

1/16W SOT-363 1/16W

MF-LF
MIN_NECK_WIDTH=0.2MM SYNC_MASTER=K62_AARON SYNC_DATE=07/01/2009
MF-LF 3
402 402 PAGE TITLE
=PP3V3_S0_PCH_VCC3_3_SATA
1

PP5V_S5_PCH_V5REFSUS 98
22 6
PCH DECOUPLING
MIN_LINE_WIDTH=0.3MM 1 DRAWING NUMBER SIZE
MIN_NECK_WIDTH=0.25MM <1 MA S0-S5 C2424 1
C2425 1
C2427
C2438 1
VOLTAGE=5V 0.1UF 1UF 1UF Apple Inc. 051-8442 D
R2407 PLACEMENT_NOTEs: 10% 10% 10%
REVISION
0.1UF 0 16V 6.3V 6.3V
=PP5V_S5_PCH_V5REFSUS =PP3V3R1V5_S5_PCH_VCCSUSHDA 2 2 2 R
20%
10V
2
22 6 1 2
PLACE C2424 AT BALL BC17
X5R
402
CERM
402
CERM
402 10.1.0
CERM 5%
402 1/16W
PLACE C2425 AT BALL BD20
PLACE C2427 AT BALL BD17
NOTICE OF PROPRIETARY PROPERTY: BRANCH
PLACEMENT_NOTE: MF-LF
402 THE INFORMATION CONTAINED HEREIN IS THE
PLACE C2438 AT BALL BT25 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
24 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 24 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PROCESSOR MINI XDP DESIGN NOTE:

ODT AVAILABLE ON JTAG

=PPVCCIO_S0_XDP 6 25
25 6 =PPVCCIO_S0_XDP
PLACEMENT NOTE:
PLACEMENT_NOTE=Place close to CPU
CRITICAL PLACE TDO TERM NEAR PLACEMENT_NOTE=Place close to CPU
SNB XDP CONN
XDP_CONN XDP XDP XDP
R25101 R25111 R25121
J2500 51 51 51
DF40C-60DS-0.4V 5% 5% 5%
F-ST-SM-HF 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF

D 1
3
2
4
402

PLACEMENT_NOTE=Place close to J2500

2 402
2 402
2 D
11 BI XDP_CPU_PREQ_L OBSFN_A0 OBSFN_C0 CPU_CFG<16> IN 10 15 93

11 XDP_CPU_PRDY_L OBSFN_A1 5 6 OBSFN_C1 CPU_CFG<17> 10 93 93 25 11 XDP_CPU_TDO

IN IN
PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs 7 8 93 25 11 XDP_CPU_TDI
XDP_CPU_BPM 93 11 XDP_BPM_L<0> OBSDATA_A0 9 10 OBSDATA_C0 CPU_CFG<0> 10 15 25 93 93 25 11 XDP_CPU_TMS
IN IN
RP2500 93 11 IN XDP_BPM_L<1> OBSDATA_A1 11 12 OBSDATA_C1 CPU_CFG<1> IN 10 15 93 93 25 11 XDP_CPU_TCK
93 11 XDP_BPM_L<4> 1 8 13 14 93 25 11 XDP_CPU_TRST_L
IN
93 11 XDP_BPM_L<5> 2
0
7
93 11 XDP_BPM_L<2> OBSDATA_A2 15 16 OBSDATA_C2 CPU_CFG<2> 10 15 93 PLACEMENT_NOTE=Place close to CPU PLACEMENT_NOTE=Place close to CPU
IN IN IN
5%
93 11 XDP_BPM_L<6> 3
1/16W
6
93 11 XDP_BPM_L<3> OBSDATA_A3 17 18 OBSDATA_C3 CPU_CFG<3> 10 15 93
IN IN IN
SM-LF
19 20 XDP1 XDP
93 11 IN XDP_BPM_L<7> 4 5
R2513 R25141
93 10 CPU_CFG<10> OBSFN_B0 21 22 OBSFN_D0 CPU_CFG<8> 10 93 51 51
IN IN
5% 5%
XDP_CPU_CFG 93 10 CPU_CFG<11> OBSFN_B1 23 24 OBSFN_D1 CPU_CFG<9> 10 93 1/16W 1/16W
IN IN
MF-LF MF-LF
RP2501 25 26 402
2 402
2
27 28 PLACEMENT NOTE:
93 10 IN CPU_CFG<12> 1 8 93 XDP_OBSDATA_B<0> OBSDATA_B0 OBSDATA_D0 CPU_CFG<4> IN 10 93
2 7 29 30 XDP PLACE TCK/TDI/TMS/TRST*
93 10 IN CPU_CFG<13> 0 93 XDP_OBSDATA_B<1> OBSDATA_B1 OBSDATA_D1 CPU_CFG<5> IN 10 15 93
R2515 PLACEMENT_NOTE=Place close to R1841 TERM NEAR CPU

m
5%
93 10 CPU_CFG<14> 3
1/16W
6 31 32 0
IN 5% 1 2 1/16W ITPXDP_CLK100M_P
SM-LF IN 18 93
93 10 CPU_CFG<15> 4 5 93 XDP_OBSDATA_B<2> OBSDATA_B2 33 34 OBSDATA_D2 CPU_CFG<6> 10 15 93
IN IN MF-LF
93 XDP_OBSDATA_B<3> OBSDATA_B3 35 36 OBSDATA_D3 CPU_CFG<7> 10 93 402
IN
37 38 XDP

co
XDP 39 40 R2516 PLACEMENT_NOTE=Place close to R1840
PLACEMENT_NOTE=Place close to CPU
R2500 XDP_CPU_PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 93 XDP_CPU_CLK100M_P
41 42 0
1K XDP_CPU_PWRBTN_L HOOK1 ITPCLK#/HOOK5 93 XDP_CPU_CLK100M_N 5% 1 2 1/16W ITPXDP_CLK100M_N 18 93
CPU_PWRGD 5% 1 2 1/16W
IN
100 21 11 IN
VCC_OBS_AB 43 44 VCC_OBS_CD MF-LF
MF-LF 402
402 XDP 93 XDP_CPU_CFG<0> HOOK2 45 46 RESET#/HOOK6 XDPCPU_PLTRST_L 27 94
IN
PLACEMENT_NOTE=Place close to SMC R2502 47 48 <- 1K SERIES R ON PCH SUPPORT P. 28
XDP_VR_READY XDP_DBRESET_L

s.
HOOK3 DBR#/HOOK7 OUT 11 25 100
0 49 50
100 46 25 19 OUT PM_PWRBTN_L 5% 1 2 1/16W NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28
MF-LF 49 25 =SMBUS_XDP_SDA SDA 51 52 TDO XDP_CPU_TDO 11 25 93
402
BI IN
53 54
C XDP 49 25 IN =SMBUS_XDP_SCL SCL TRSTn XDP_CPU_TRST_L OUT 11 25 93
C

ic
PLACEMENT_NOTE=Place close to CPU
R2501 TCK1 55 56 TDI XDP_CPU_TDI
1K NC OUT 11 25 93

93 25 15 10 CPU_CFG<0> 5% 1 2 1/16W 93 25 11 XDP_CPU_TCK TCK0 57 58 TMS XDP_CPU_TMS 11 25 93

OUT OUT OUT =PP3V3_S5_XDP 6 25
MF-LF 59 60 XDP_PRESENT#
402 XDP

at
R2504 XDP XDP PLACEMENT NOTE:
PLACEMENT_NOTE=Place close to PCH
0 C2500 1 1
C2501 PLACE TDO TERM NEAR PLACEMENT_NOTE=Place close to PCH
100 65 64 5 OUT PM_PGOOD_PVCORE_CPU 5% 1 2 1/16W
0.1uF 518S0774 0.1uF PCH XDP CONN
XDP1 XDP XDP
R25511 R25521
MF-LF 10% 10%
402 16V
2 2
16V R2550
X5R X5R
200 200 200

em
402 402
5% 5% 5%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
402 402 402
2 2 2
PLACEMENT_NOTE=Place close to J2550

XDP 94 25 18 XDP_PCH_TDO
PLACEMENT_NOTE=Place close to SW2800
R2506 To Reset Button 94 25 18 XDP_PCH_TDI

ch
XDP_DBRESET_L 1
0 2 PM_SYSRST_L
94 25 18 XDP_PCH_TMS
100 25 11 IN OUT 19 27 46 100
94 25 18 XDP_PCH_TCK
5%
1/16W PLACEMENT_NOTE=Place close to PCH PLACEMENT_NOTE=Place close to PCH

PCH MINI XDP MF-LF

402
PLACEMENT_NOTE=Place close to PCH PLACEMENT_NOTE=Place close to PCH

XDP XDP XDP XDP

R25531 R25541 R25551 R25561

kS
25 6 =PP3V3_S5_XDP
100 100 100 51
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
CRITICAL MF-LF MF-LF MF-LF MF-LF
XDP 402
2 402
2 402
2 402
2
PLACEMENT_NOTE=Place close to PCH
R2582 XDP_CONN
OC0#/GPIO59
100 33 20 IN AP_PWR_EN 5% 1
0
2 1/16W J2550
DF40C-60DS-0.4V

oo
MF-LF 402
XDP F-ST-SM-HF XDP
PLACEMENT_NOTE=Place close to PCH
OC1#/GPIO40 R2580 1 2 R2578 PLACEMENT_NOTE=Place close to PCH
GPIO15
B 100 34 20 IN USB_HUB_SOFT_RESET_L 5% 1
MF-LF
0
2 1/16W
402
TP_XDP_PCH_OBSFN_A<0> OBSFN_A0 3
5
4
6
OBSFN_C0 XDP_PCH_GPIO15 5% 1
MF-LF
0
2 1/16W
402
PCH_GPIO15 IN 15 21
This is to derive 1.05V SUS RAIL
B
TP_XDP_PCH_OBSFN_A<1> OBSFN_A1 OBSFN_C1 PCH_GPIO0_BMBUSY_L IN 15 21 XDP PLACEMENT NOTE:
XDP 7 8 R2576 PLACEMENT_NOTE=Place close to PCH
PLACEMENT_NOTE=Place close to PCH
OC2#/GPIO41 R2583
eb 0
MGPIO7/GPIO28 PLACE TCK/TDI/TMS/TRST*
TERM NEAR PCH
0 XDP_PCH_AP_PWR_EN OBSDATA_A0 9 10 OBSDATA_C0 XDP_PCH_ISOLATE_CPU_MEM_L 5% 1 2 1/16W ISOLATE_CPU_MEM_L 21 32 100
T29_DP_PORTA_PWR_EN 5% 1 2 1/16W MF-LF 402 IN
100 94 83 20 IN MF-LF 402 XDP_PCH_USB_HUB_SOFT_RST_L OBSDATA_A1 11 12 OBSDATA_C1 XDP_PCH_MXM_GOOD XDP
XDP 13 14 R2577 PLACEMENT_NOTE=Place close to PCH
GPIO35
PLACEMENT_NOTE=Place close to PCH R2587 15 16
0
OC3#/GPIO42 XDP_PCH_T29_DP_PORTA_PWR_EN OBSDATA_A2 OBSDATA_C2 XDP_PCH_DP_AUXCH_ISOL 5% 1 2 1/16W MXM_GOOD IN 5 21 100
0 17 18
MF-LF 402
ENET_PWR_EN 5% 1 2 1/16W XDP_PCH_ENET_PWR_EN PCH_GPIO19_SATA1GP
ot
100 36 20 IN OBSDATA_A3 OBSDATA_C3 IN 15 18 XDP
MF-LF 402
19 20 R2575 PLACEMENT_NOTE=Place close to PCH
SATA0GP/GPIO21
XDP 21 22
0
PLACEMENT_NOTE=Place close to PCH
R2586 TP_XDP_PCH_OBSFN_B<0> OBSFN_B0 OBSFN_D0 TP_XDP_PCH_OBSFN_D<0> 5% 1 2 1/16W DP_AUXCH_ISOL IN 15 18 85 87 94
OC4#/GPIO43 MF-LF 402
0 TP_XDP_PCH_OBSFN_B<1> OBSFN_B1 23 24 OBSFN_D1 TP_XDP_PCH_OBSFN_D<1>
94 83 20 IN T29_DP_PORTB_PWR_EN 5% 1 2 1/16W
N

MF-LF 402 25 26
SATA2GP/GPIO36
XDP_PCH_T29_DP_PORTB_PWR_EN OBSDATA_B0 27 28 OBSDATA_D0 PCH_GPIO36_SATA2GP 15 21
IN
XDP 29 30
XDP_PCH_SDCONN_CHANGE OBSDATA_B1 OBSDATA_D1 XDP_PCH_JTAG_T29_TCK XDP
PLACEMENT_NOTE=Place close to PCH
OC5#/GPIO9 R2581 31 32 R2573 PLACEMENT_NOTE=Place close to PCH
0 SATA3GP/GPIO37
100 45 20 IN SDCONN_STATE_CHANGE 5% 1 2 1/16W 0
MF-LF 402 20 PCH_GPIO10_OC6_L OBSDATA_B2 33 34 OBSDATA_D2 XDP_PCH_AUD_IPHS_SWITCH_EN 5% 1 2 1/16W JTAG_T29_TCK 15 21 89 99
IN MF-LF 402 IN
XDP 20 PCH_GPIO14_OC7_L OBSDATA_B3 35 36 OBSDATA_D3 PCH_GPIO49_SATA5GP 15 21 XDP
IN IN
PLACEMENT_NOTE=Place close to J2550
R2584 37 38 R2579 PLACEMENT_NOTE=Place close to PCH
SATA4GP/GPIO16
1K 39 40
0
25 6 IN =PP3V3_S5_XDP 5% 1 2 1/16W XDP_PCH_S5_PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 TP_XDP_PCH_HOOK4 5% 1 2 1/16W AUD_IPHS_SWITCH_EN_PCH IN 21 94
MF-LF 402 MF-LF 402
XDP_PCH_PWRBTN_L HOOK1 41 42 ITPCLK#/HOOK5 TP_XDP_PCH_HOOK5
XDP 43 44
PLACEMENT_NOTE=Place close to SMC
R2585 VCC_OBS_AB VCC_OBS_CD
0 TP_XDPPCH_HOOK2 HOOK2 45 46 RESET#/HOOK6 XDPPCH_PLTRST_L 27 100 <- 1K SERIES R ON PCH SUPPORT P. 28
PM_PWRBTN_L 5% 1 2 1/16W IN
100 46 25 19 OUT MF-LF 402 TP_XDPPCH_HOOK3 HOOK3 47 48 DBR#/HOOK7 XDP_DBRESET_L 11 25 100
OUT
49 50 NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28
49 25 =SMBUS_XDP_SDA SDA 51 52 TDO XDP_PCH_TDO 18 25 94
BI IN
=SMBUS_XDP_SCL 53 54 TP_XDP_PCH_TRST_L
A 49 25 IN SCL
TCK1 NC
55 56
TRSTn
TDI XDP_PCH_TDI OUT 18 25 94 SYNC_MASTER=K62_SIJI SYNC_DATE=01/09/2011 A
94 25 18 XDP_PCH_TCK TCK0 57 58 TMS XDP_PCH_TMS 18 25 94
PAGE TITLE
OUT OUT
59 60 XDP_PRESENT# CPU & PCH XDP
XDP XDP DRAWING NUMBER SIZE
C2580 1
518S0774
1 C2581 Apple Inc. 051-8442 D
0.1uF 0.1uF REVISION
10% 10% R
16V
X5R 2 2
16V
X5R
10.1.0
402 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
25 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 25 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BUF_CLK BUF_CLK
BUF_CLK
L2600 L2650
FERR-120-OHM-1.5A FERR-120-OHM-1.5A R2650
1 2 1 2 1
2.2 2
6 =PP1V05_S0_CK505 98 PP1V05_S0_CK505_F 6 =PP1V5_S0_CK505 98 PP1V5_S0_CK505_F 98 PP1V5_S0_CK505_R
MIN_LINE_WIDTH=0.5mm MIN_LINE_WIDTH=0.5mm
0402 MIN_NECK_WIDTH=0.2mm BUF_CLK BUF_CLK BUF_CLK BUF_CLK BUF_CLK 0402 MIN_NECK_WIDTH=0.2mm 5% BUF_CLK
VOLTAGE=1.05V VOLTAGE=1.5V 1/16W BUF_CLK BUF_CLK
C2600 1 1 C2602 1 C2603 1 C2604 1 C2605 MF-LF
402
C2650 1 1 C2651 1 C2652
D
10UF
20%
6.3V
X5R 2 2
0.1UF
10%
16V
X5R 2
0.1UF
10%
16V
X5R 2
0.1UF
10%
16V
X5R 2
0.1UF
10%
16V
X5R
10UF
20%
6.3V
X5R 2
2
0.1UF
10%
16V
2
0.1UF
10%
16V
D
603 402 402 402 402 603 X5R X5R
402 402
PLACE IT CLOSE TO L2650
PLACE IT CLOSE TO L2600
BUF_CLK PLACE IT CLOSE TO POWER PINS PLACE IT CLOSE TO POWER PINS

L2610
FERR-120-OHM-1.5A
6 =PP3V3_S0_CK505 1 2 98 PP3V3_S0_CK505_F
MIN_LINE_WIDTH=0.5mm
0402 MIN_NECK_WIDTH=0.2mm BUF_CLK BUF_CLK BUF_CLK
VOLTAGE=3.3V
C2610 1 1 C2615 1 C2616
10UF 0.1UF 0.1UF
20% 10% 10%
6.3V 16V 16V
X5R 2 2 X5R 2 X5R
603 402 402
PLACE IT CLOSE TO L2610

PLACE IT CLOSE TO POWER PINS

m
co
s.
CRITICAL
Y2620

22
9

4
14.31818
C CK505_XTAL_OUT_R 1 2
C

ic
94

VDD_CPU_IO

VDD_SRC_IO

VDD_SATA_IO

VDD_27

VDD_96_IO

VDD_REF
BUF_CLK BUF_CLK

VDD_CORE
5X3.2-SM
C2620 1
BUF_CLK 1
C2621 1 NOSTUFF
R2616
18pF 18pF 10M

at
5% 5%
50V 50V 5%
CERM 2 2 CERM 1/16W PLACE R2699 NEAR PIN 26
402 402 MF-LF
2 402 CRITICAL BUF_CLK

BUF_CLK U2600 R2699

SLG2AP108 33

em
R2615 94 CK505_XTAL_IN 24 X1 QFN REF 26 PCH_CLK14P3M_REFCLK_R 5% 1 2 402 PCH_CLK14P3M_REFCLK OUT 18 26 94
0 1/16W MF-LF
5% 1 2 1/16W 94 CK505_XTAL_OUT 23 X2 OMIT
CPU* 18 TP_CLK133M_PCH_N 93
R2605 OR R2606 CAN BE CHANGED TO "BUF_CLK" OPTION LATER MF-LF 402
WHEN FCIM IS FULLY VALIDATED -> 49 IN =SMBUS_CK505_SCL 3 SCL CPU 19 TP_CLK133M_PCH_P 93 PCH BCLK 133MHZ
NOSTUFF
R2605 49 BI =SMBUS_CK505_SDA 2 SDA SRC_2* 11 PCH_CLK100M_DMI_N OUT 18 26 93

0 SRC_2 10 PCH_CLK100M_DMI_P OUT 18 26 93

100 63 47 46 36 32 19 5 IN PM_SLP_S3_L 5% 1 2 1/16W CK505_CKPWRGD_PD_L 1 CKPWRGD/PD* PCH DMI/PCIe 100MHz

ch
MF-LF 402 SATA* 15 PCH_CLK100M_SATA_N OUT 18 26 93
100 CK505_27MHZ_EN 32 27MHZ_EN
NOSTUFF SATA 14 PCH_CLK100M_SATA_P OUT 18 26 93
R2606 PCH SATA 100MHZ
0 27MHZ 29 CK505_CLK27M
64 IN PM_PGOOD_CK505 5% 1 2 1/16W BUF_CLK BUF_CLK
MF-LF 402
R26201 1
R2600 27MHZ_SS 30 TP_CK505_CLK27M_SS

kS
10K 10K
5% 5% DOT_96* 7 PCH_CLK96M_DOT_N 18 26 93

VSS_SATA

VSS_CORE
OUT
STUFF THIS TO POWER DOWN CK505 -> 1/16W 1/16W

VSS_REF
VSS_CPU

VSS_SRC
MF-LF MF-LF DOT_96 6 PCH_CLK96M_DOT_P

VSS_27

VSS_96
OUT 18 26 93
402 2 2 402 PCH USB Clock 96MHz
THRM
PAD BUF_CLK

oo
1
R2690

33
10K
5%
B eb 1/16W
MF-LF
2 402
B
ot
N

UNUSED clock terminations for FCIM MODE

94 26 18 PCH_CLK14P3M_REFCLK

93 26 18 PCH_CLK100M_DMI_N

93 26 18 PCH_CLK100M_DMI_P

93 26 18 PCH_CLK100M_SATA_N

93 26 18 PCH_CLK100M_SATA_P

93 26 18 PCH_CLK96M_DOT_N

A 93 26 18 PCH_CLK96M_DOT_P
SYNC_MASTER=K62_ROSITA SYNC_DATE=01/09/2011 A
PAGE TITLE

CLOCK (CK505)
FCIM FCIM FCIM FCIM FCIM FCIM FCIM DRAWING NUMBER SIZE
1
R2657 1
R2651 1R2652 1R2653 1R2654 1
R2655 1
R2656 Apple Inc. 051-8442 D
10K 10K 10K 10K 10K 10K 10K REVISION
5% 5% 5% 5% 5% 5% 5% R
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
10.1.0
2 402 2 402 2 402 2 402 2 402 2 402 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
26 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 26 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

RTC Power Sources Platform Reset Connections

D2800
BAT54DW-X-G
SOT-363
=PP3V3_G3H_RTC_D PP3V3_G3H_RTC RTC_RESET_L
6
1 6 MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
18 19 22 98 100 18
Unbuffered R2881
Coin-Cell Holder R2800 VOLTAGE=3.3V
PLT_RESET_L 1
33
2 DEBUG_RESET_L
OMIT 100 20 IN OUT 48 100
1K MAKE_BASE=TRUE
98 PPVBATT_G3_RTC 2 1 98 PPVBATT_G3_RTC_R 4 3 1 C2899 5%
1/16W
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm 5%
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm NOSTUFF MF-LF
VOLTAGE=3.3V 1/16W VOLTAGE=3.3V NONE 402
NONE
MF-LF
NC
5 NC NC 2 NC 2 NONE

D 1
J2800
402
603
PLACE THIS ON THE BOTTOM SIDE
R2882
33
D
BB10201-C1403-7H 1 2 ENET_RESET_L OUT 36 100
2 SM 5%
1/16W
511-0054 MF-LF
NOTE: R2800 and D2800 form the double- 402

fault protection for RTC battery. R2892

33
1 2 FW_RESET_L OUT 39 100

5%
1/16W
MF-LF

PCH RTC Crystal 402

T29
R2855
33
1 2 T29_RESET_L OUT 81 100

5%
1/16W
PLACE C2810 CLOSE TO Y2810 MF-LF
402
C2810
R2810

m
12pF XDP
0 1 2 R2899
94 18 PCH_CLK32K_RTCX2 1 2 94 PCH_CLK32K_RTCX2_R
IN 1K
5% 1 2 XDPPCH_PLTRST_L OUT 25 100
1/16W 5%
1 MF-LF CRITICAL 50V 5%
R2811 CERM

3
402 1/16W

co
402

4
10M Y2810 NC MF-LF
5% 402

2
1/16W 32.768K NC
MF-LF SM-2
C2811 XDP

1
R2870 402 2
12pF R2898
0 1 2
1K
94 18 PCH_CLK32K_RTCX1 1 2 94 PCH_CLK32K_RTCX1_R 1 2 XDPCPU_PLTRST_L 25 94
OUT OUT

s.
5% PLACE Y2810 CLOSE TO U1800 5%
5%
1/16W
50V 27 11 6 =PP3V3_S0_RSTBUF 1/16W
MF-LF MF-LF MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED
402 CERM
402
Buffered 402

PLACE C2811 CLOSE TO Y2810

C C

ic
PCH 25MHZ CRYSTAL 1
5 MC74VHC1G08
SOT23-5-HF
4 94 PLT_RST_BUF_L 1
R2890
33
2 PEG_RESET_L
PLACE C2815 CLOSE TO Y2815 U2880 OUT 9 100
NOSTUFF C2815 DEVELOPMENT 2 5%
R2815

at
22pF 1
1/16W
0 1 2 3 R2880 MF-LF
94 18 PCH_CLK25M_XTALOUT 1 2 94 PCH_CLK25M_XTALOUT_R 402
IN
C2880 1 100K
DEVELOPMENT 1 5%
5% 0.1UF 5%
R2883

25.0000M
1/16W
R2816 1/16W

8X4.5MM-SM3
50V 20% 33

Y2815
MF-LF MF-LF
CERM 10V SMC_LRESET_L
1M 402 1 2

em
2
2
2 402
CERM OUT 46 100
402
5% DEVELOPMENT 402
1/16W CRITICAL 5%
MF-LF 1/16W
NOSTUFF 402 2
C2816 MF-LF

1
402
R2872 22pF
0 1 2 R2888
94 80 18 PCH_CLK25M_XTALIN 1 2 94 PCH_CLK25M_XTALIN_R
OUT 33
5% PLACE Y2815 CLOSE TO U1800 DEVELOPMENT 5% 1 2 MINI_RESET_L OUT 33 100
1/16W
MF-LF 50V 5%

ch
402 CERM 1/16W
402 =PP3V3_S0_RSTBUF MF-LF
27 11 6
PLACE C2816 CLOSE TO Y2815 402

OPEN-DRAIN BUFFER R2884

33
1 2 SDCARD_PLT_RST_L OUT 44 100
5 U2890 5%
74LVC1G07 1/16W

kS
SC70 MF-LF
402
6 =PP3V3_S0_PCH_PM 2 4 CPU_RESET_L 11 100
OUT
NC VTT VOLTAGE DIVIDER AND PU ON CPU PAGE
1
R2897 1 3
4.7K 1
5% C2890

oo
1/16W NC_U2890_P1
MF-LF 0.1UF NO_TEST=TRUE
20%
2 402 10V
CERM 2

B 402
B
Reset Button
eb
PM_SYSRST_L OUT 19 25 46 100

DEVELOPMENT
SW2800 6 =PP3V3_S5_RSTBUF
NTC020-CC1J-B260T
ot
1 SM 2
C2870 1
0.1UF
20%
10V
2
N

CERM
402

3 4

5 MC74VHC1G08
100 71 64 PM_PGOOD_P3V3_S5_REG 1 SOT23-5-HF
4 PM_RSMRST_PCH_L
SILK_PART=SYS RESET 2
U2870 19 100

R2825
PLACEMENT_NOTE=Place close to U1800 33 R2850
94 20 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC OUT 46 94 0
100 46 PM_RSMRST_L 1 2
5%

A 1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to U1800
R2826
33
5%
1/16W
MF-LF
402
SYNC_MASTER=K62_SIJI SYNC_DATE=01/09/2011 A
94 20 LPC_CLK33M_LPCPLUS_R 1 2 LPC_CLK33M_LPCPLUS 48 94
PAGE TITLE
IN OUT
5%
1/16W
NOSTUFF
CHIPSET SUPPORT
MF-LF DRAWING NUMBER SIZE
R2827 402 SMC PROVIDES RSMRST_L DE-ASSERTION DELAY UPON ENTRY TO S5
94 20 PCH_CLK33M_PCIOUT
PLACEMENT_NOTE=Place close to U1800
1
33
2 PCH_CLK33M_PCIIN 18 94 SMC PROVIDES RSMRST_L ASSERTION TIMING REQUIREMENTS UPON EXPECTED EXIT FROM S5 Apple Inc. 051-8442 D
IN OUT
REVISION
5% SMC MAY FORCE A RSMRST_L ASSERTION WITHOUT AN S5 POWER TRANSITION IN SOME ERROR CASES R
1/16W
MF-LF PGOOD PROVIDES RSMRST_L ASSERTION TIMING REQUIREMENTS UPON AN UN-EXPECTED EXIT FROM S5 (POWER LOSS)
10.1.0
402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
28 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 27 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

30 29 28 6
=PP1V5_S3_MEM_A

=PP3V3_S3_VREFMRGN PLACEMENT NOTE:

28 6

VREFMRGN_A PLACE R2970, R2971 and C2950 close to DIMM PIN

R2909
=PP5V_S3_VREFMRGN 1
10 2 98 PP5V_S3_VREFMRGN_A
28 6
30 29 28 6 =PP1V5_S3_MEM_A
1% VREFMRGN_A
VREFMRGN_A 1/16W
1 C2900 MF-LF
1 C2901
D VREFMRGN_A 0.1UF
10% 353S2369
402 0.1UF
10%
2 16V
1
R2970 D
R2900 2 16V
X5R
1 VREFMRGN_A VREFMRGN_A X5R
402
1K
=I2C_VREFMRGN_A_SCL 0 VDD R2902 1%
49 IN 1 2 402
U2900 12.1K2 U2901 VREFMRGN_A VREFMRGN_A
1/16W
MF-LF
5% 1 1 5 LM321 2 402
1/16W ISL90727WIE627ZTK SOT23-5 R2904 R2958
MF-LF SC-70 1%
4 1
2.2 2 VREFMARGIN_DIMMA_DQ 1
0 2 PP0V75_S3_MEM_VREFDQ_A
402 1/16W 92
97 I2C_VREFMRGN_DIMMA_SCL 3 SCL VREFMRGN_A RH 6 MF-LF OUT 28 30 98

402 5% 5%
VREFMRGN_A 3 353S1961 1/16W 1/16W 1 NOSTUFF
R2901 97 I2C_VREFMRGN_DIMMA_SDA 4 SDA RW 5 92 VREFMARGIN_DIMMA_DACOUT 2
VREFMRGN_A
1
MF-LF
VREFMRGN_A
MF-LF R2971 1 C2950
=I2C_VREFMRGN_A_SDA 1
0 2 GND
VREFMRGN_A
R2905 402
1 C2902
402
1K 0.1UF
49 BI 1K 1UF
1% 10%

2
1 1/16W
5%
1/16W
R2903 1%
1/16W 10%
6.3V
MF-LF 2 16V
X5R
MF-LF I2C ADDR = 0X5C (WRITE) 12.1K MF-LF 2 CERM 2 402 402
402 1% 2 402 402
I2C ADDR = 0X5D (READ) 1/16W 92 VREFMARGIN_DIMMA_OPFB
MF-LF
2 402

m
co
31 29 28 6
=PP1V5_S3_MEM_B
PLACEMENT NOTE:
=PP3V3_S3_VREFMRGN

s.
28 6
PLACE R2975, R2976 and C2951 close to DIMM PIN
VREFMRGN_B
R2919
=PP5V_S3_VREFMRGN 1
10 2 98 PP5V_S3_VREFMRGN_B
C 28 6
=PP1V5_S3_MEM_B C

ic
31 29 28 6
1% VREFMRGN_B
VREFMRGN_B 1/16W 1 C2911 VREFMARGIN_DIMMB_DQ OUT 28 92
MF-LF
1 C2910 402 0.1UF
0.1UF 1
VREFMRGN_B 10% 353S2370 10%
2 16V
R2975
R2910 1K

at
16V
2 X5R 1 VREFMRGN_B VREFMRGN_B X5R R2956 change to NOSTUFF if use VREFMARGIN_DIMMB_DQ
0 402 1%
49 IN
=I2C_VREFMRGN_B_SCL 1 2 402 VDD R2912 U2911 to drive both VREFCA_A and VREFCA_B 1/16W
MF-LF
U2910 12.1K2 1 5 LM321 VREFMRGN_B VREFMRGN_B
5%
ISL90728WIE627ZTK
1
R2914 R2956 2 402
1/16W SOT23-5
MF-LF SC-70 1%
4
2.2 0 PP0V75_S3_MEM_VREFDQ_B

em
402 1/16W 1 2 1 2
97 I2C_VREFMRGN_DIMMB_SCL 3 SCL VREFMRGN_B RH 6 MF-LF OUT 28 31 98

402 5% 5%
VREFMRGN_B 3 353S1961 1/16W 1/16W 1 NOSTUFF
R2911 97 I2C_VREFMRGN_DIMMB_SDA 4 SDA RW 5 92 VREFMARGIN_DIMMB_DACOUT 2 1
VREFMRGN_B MF-LF
VREFMRGN_B MF-LF R2976 1 C2951
=I2C_VREFMRGN_B_SDA 1
0 2
GND
VREFMRGN_B
R2915 402
1 C2912
402
1%
1K 0.1UF
49 BI 1K 1UF 10%
2

1 1/16W
5%
1/16W
R2913 1%
1/16W 10%
6.3V
MF-LF
16V
2 X5R
MF-LF I2C ADDR = 0X7C (WRITE) 12.1K MF-LF 2 CERM 2 402 402
402 1% 2 402 402
1/16W VREFMARGIN_DIMMB_OPFB PLACE IT CLOSE TO DIMM CONNECTOR PIN

ch
I2C ADDR = 0X7D (READ) 92
MF-LF
2 402

kS
DIMM VREFDQ

oo
B B
DIMM VREFCA
eb
30 29 28 6 =PP1V5_S3_MEM_A

1
R2988 PLACEMENT NOTE:
1K
ot
1% PLACE R2988, R2989 and C2921 close to DIMM PIN
1/16W
MF-LF
NOSTUFF 2 402
R2995
0
VREFMARGIN_DIMMB_DQ PP0V75_S3_MEM_VREFCA_A
1 2
CPU VREF
N

92 28 IN OUT 30 98

5%
1/16W NOSTUFF
1
MF-LF
402 R2989 1 C2921
1K 0.1UF
1% 10% NOSTUFF
1/16W
MF-LF 16V
2 X5R PLACEMENT NOTE: R2960
2 402 402 PP0V75_S3_MEM_VREFDQ_A 1
0 2 PP0V75_S3_MEM_VREFDQ_B
98 30 28 28 31 98
PLACE R2968, R2969 and C2961 near CPU
5%
1/16W
MF-LF
29 16 13 11 6 =PP1V5_S0_CPU_MEM 402

31 29 28 6 =PP1V5_S3_MEM_B EMPTY ONE SET OF OP-AMP & POT WHEN R2960 IS STUFF
1
R2968
100
1%
1
R2978 PLACEMENT NOTE: 1/16W
MF-LF
1K 2 402
A NOSTUFF
1%
1/16W
MF-LF
PLACE R2978, R2979 and C2991 close to DIMM PIN

CPU_DDR_VREF SYNC_MASTER=K62_ROSITA SYNC_DATE=01/09/2011 A

R2996 2 402 OUT 11 92
PAGE TITLE
0
92 28 IN VREFMARGIN_DIMMB_DQ 1 2 PP0V75_S3_MEM_VREFCA_B OUT 31 98 1
R2969
DDR3 VREF MARGINING
5%
1/16W NOSTUFF 100
1 C2961 DRAWING NUMBER SIZE
1 0.1UF 051-8442 D
MF-LF
402 R2979 1 C2991 1%
1/16W 10%
16V Apple Inc.
1K 0.1UF MF-LF 2 X5R REVISION
1% 10% 2 402 402 R
10.1.0
1/16W 16V
MF-LF 2 X5R
2 402 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
29 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 28 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

DIMM A (CLOSER TO CPU) CAPS TO STITCH 1V5_CPU_MEM TO GND NEAR DIMM DIMM B (FURTHER FROM CPU)

29 28 16 13 11 6 =PP1V5_S0_CPU_MEM

D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D
C3015 C3016 C3017 C3018 C3019 C3010 C3025 C3026 C3027 C3028 C3029 C3020 C3021 C3022 C3023 C3014 C3030 C3031 C3032 C3033 C3034 C3035 C3036 C3037 C3038 C3039
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

m
EXTRA DECOUPLING CAPS FOR 1V5_CPU_MEM RAIL

co
29 28 16 13 11 6 =PP1V5_S0_CPU_MEM

1 C3040 1 C3041 1 C3042 1 C3043 1 C3044 1 C3045 1 C3046 1 C3047 1 C3048 1 C3049 1 C3090 1 C3091 1 C3092 1 C3093 1 C3094 1 C3095 1 C3096
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF

s.
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

C C

ic
at
29 28 16 13 11 6 =PP1V5_S0_CPU_MEM

1 C30A0 1 C30A1 1 C30A2 1 C30A3 1 C30A4 1 C30A5 1 C30A6 1 C30A7 1 C30A8 1 C30A9 1 C30AA 1 C30AB 1 C30AC 1 C30AD 1 C30AE 1 C30AF 1 C30AG

em
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

ch
kS
DECOUPLING CAPS FOR 1V5_S3_MEM AT CHANNEL A DIMM CONNECTOR

30 28 6 =PP1V5_S3_MEM_A

oo
B 1
C3050
10UF
1
C3051
10UF
1 C3052
1UF
1 C3053
1UF
1 C3054
1UF
1 C3055
1UF
1 C3056
1UF
1 C3057
1UF
1 C3058
1UF
1 C3059
1UF
1 C3060
1UF
1 C3061
1UF
1 C3062
1UF
1 C3063
1UF
1 C3064
1UF
1 C3065
1UF
1 C3066
1UF
1 C3067
1UF
1 C3068
1UF
1 C3069
1UF
B
20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 CERM 2 CERM 2 CERM
eb
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
603 603 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
ot
DECOUPLING CAPS FOR 1V5_S3_MEM AT CHANNEL B DIMM CONNECTOR
N

31 28 6 =PP1V5_S3_MEM_B

1
C3070 1
C3071 1 C3072 1 C3073 1 C3074 1 C3075 1 C3076 1 C3077 1 C3078 1 C3079 1 C3080 1 C3081 1 C3082 1 C3083 1 C3084 1 C3085 1 C3086 1 C3087 1 C3088 1 C3089
10UF 10UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2
6.3V
X5R 2
6.3V
X5R 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
603 603 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

A SYNC_MASTER=K62_ROSITA SYNC_DATE=01/09/2011 A
PAGE TITLE

MEMORY CAPS
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

30 32 32 30 =MEM_A_DQ<0> 5B
DQ0
J3100 DQ5
6B =MEM_A_DQ<5>
30 32

30 32
DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD) DIMM2 SPD ADDR=0XA2(WR)/0XA3(RD)
7A F-RT-TH 8A 7B F-RT-TH 8B
32 30 =MEM_A_DQ<1> DQ1 VSS_2 32 30 =MEM_A_DQ<1> DQ1 VSS_2 30 MEM_DIMM0_SA<1> 47 30 6 =PPSPD_S0_MEM_A
9A (1 OF 2) 10A =MEM_A_DQS_N<0> 9B (2 OF 2) 10B =MEM_A_DQS_N<0>

DDR3-SODIMM-DUAL
VSS_3 DQS0* 30 32 VSS_3 DQS0* 30 32

DDR3-SODIMM-DUAL
11A 12A 11B 12B 30 MEM_DIMM0_SA<0>
DM0 DQS0 =MEM_A_DQS_P<0> 30 32 DM0 DQS0 =MEM_A_DQS_P<0> 30 32
1
13A 14A 13B 14B R3142
VSS_4 VSS_5 VSS_4 VSS_5 1 1 10K
32 30 =MEM_A_DQ<2> 15A
DQ2 DQ6
16A =MEM_A_DQ<6> 30 32 32 30 =MEM_A_DQ<2> 15B
DQ2 DQ6
16B =MEM_A_DQ<6> 30 32
R3140 R3141 5%
17A 18A 17B 18B 10K 10K 1/16W
32 30 =MEM_A_DQ<3> DQ3 DQ7 =MEM_A_DQ<7> 30 32 32 30 =MEM_A_DQ<3> DQ3 DQ7 =MEM_A_DQ<7> 30 32 5% 5% MF-LF
19A 20A 19B 20B 1/16W 1/16W 402
2
VSS_6 VSS_7 VSS_6 VSS_7 MF-LF MF-LF
21A 22A 21B 22B 402 402
=MEM_A_DQ<8> =MEM_A_DQ<12> =MEM_A_DQ<8> =MEM_A_DQ<12> 2 2
32 30 DQ8 DQ12 30 32 32 30 DQ8 DQ12 30 32
MEM_DIMM2_SA<0>
=MEM_A_DQ<9> 23A 24A =MEM_A_DQ<13> =MEM_A_DQ<9> 23B 24B =MEM_A_DQ<13>
30
32 30 DQ9 DQ13 30 32 32 30 DQ9 DQ13 30 32

D 25A
27A
VSS_8 VSS_9
26A
28A
25B
27B
VSS_8 VSS_9
26B
28B
30 MEM_DIMM2_SA<1> D
32 30 =MEM_A_DQS_N<1> DQS1* DM1 32 30 =MEM_A_DQS_N<1> DQS1* DM1
=MEM_A_DQS_P<1> 29A 30A MEM_RESET_L =MEM_A_DQS_P<1> 29B 30B MEM_RESET_L
32 30 DQS1 RESET* 30 31 32 92 100 32 30 DQS1 RESET* 30 31 32 92 100
31A 32A 31B 32B 1
VSS_10 VSS_11 VSS_10 VSS_11 R3143
=MEM_A_DQ<10> 33A 34A =MEM_A_DQ<14> =MEM_A_DQ<10> 33B 34B =MEM_A_DQ<14> 10K
32 30 DQ10 DQ14 30 32 32 30 DQ10 DQ14 30 32
35A 36A 35B 36B 5%
32 30 =MEM_A_DQ<11> DQ11 DQ15 =MEM_A_DQ<15> 30 32 32 30 =MEM_A_DQ<11> DQ11 DQ15 =MEM_A_DQ<15> 30 32 1/16W
37A 38A 37B 38B MF-LF
VSS_12 VSS_13 VSS_12 VSS_13 2
402

=MEM_A_DQ<16> 39A 40A =MEM_A_DQ<20> =MEM_A_DQ<16> 39B 40B =MEM_A_DQ<20>

32 30 DQ16 DQ20 30 32 32 30 DQ16 DQ20 30 32

=MEM_A_DQ<17> 41A 42A =MEM_A_DQ<21> =MEM_A_DQ<17> 41B 42B =MEM_A_DQ<21>

32 30 DQ17 DQ21 30 32 32 30 DQ17 DQ21 30 32
=PPSPD_S0_MEM_A
43A 44A 43B 44B 47 30 6
VSS_14 VSS_15 VSS_14 VSS_15
=MEM_A_DQS_N<2> 45A 46A =MEM_A_DQS_N<2> 45B 46B
32 30 DQS2* DM2 32 30 DQS2* DM2
=MEM_A_DQS_P<2> 47A 48A =MEM_A_DQS_P<2> 47B 48B 1
C3140
32 30 DQS2 VSS_16 32 30 DQS2 VSS_16
49A 50A =MEM_A_DQ<22> 49B 50B =MEM_A_DQ<22> 2.2UF
VSS_17 DQ22 30 32 VSS_17 DQ22 30 32
20%
=MEM_A_DQ<18> 51A 52A =MEM_A_DQ<23> =MEM_A_DQ<18> 51B 52B =MEM_A_DQ<23> 6.3V
32 30 DQ18 DQ23 30 32 32 30 DQ18 DQ23 30 32 2 CERM
=MEM_A_DQ<19> 53A 54A =MEM_A_DQ<19> 53B 54B 402-LF
32 30 DQ19 VSS_18 32 30 DQ19 VSS_18

m
55A 56A =MEM_A_DQ<28> 55B 56B =MEM_A_DQ<28>
VSS_19 DQ28 30 32 VSS_19 DQ28 30 32

=MEM_A_DQ<24> 57A 58A =MEM_A_DQ<29> =MEM_A_DQ<24> 57B 58B =MEM_A_DQ<29>

32 30 DQ24 DQ29 30 32 32 30 DQ24 DQ29 30 32

=MEM_A_DQ<25> 59A 60A =MEM_A_DQ<25> 59B 60B

32 30 DQ25 VSS_20 32 30 DQ25 VSS_20
61A 62A =MEM_A_DQS_N<3> 61B 62B =MEM_A_DQS_N<3>
VSS_21 DQS3* 30 32 VSS_21 DQS3* 30 32

co
63A 64A =MEM_A_DQS_P<3> 63B 64B =MEM_A_DQS_P<3>
DM3 DQS3 30 32 DM3 DQS3 30 32
PP0V75_S3_MEM_VREFCA_A
65A 66A 65B 66B 98 30 28
VSS_22 VSS_23 VSS_22 VSS_23
=MEM_A_DQ<26> 67A 68A =MEM_A_DQ<30> =MEM_A_DQ<26> 67B 68B =MEM_A_DQ<30>
32 30 DQ26 DQ30 30 32 32 30 DQ26 DQ30 30 32

=MEM_A_DQ<27> 69A 70A =MEM_A_DQ<31> =MEM_A_DQ<27> 69B 70B =MEM_A_DQ<31>

32 30 DQ27 DQ31 30 32 32 30 DQ27 DQ31 30 32
71A 72A 71B 72B

s.
VSS_24 VSS_25 VSS_24 VSS_25
KEY KEY
1
C3135 1
C3136
MEM_A_CKE<2> 73A 74A MEM_A_CKE<3> MEM_A_CKE<0> 73B 74B MEM_A_CKE<1> 2.2UF 0.1UF
92 12 CKE0 CKE1 12 92 92 12 CKE0 CKE1 12 92
20% 20%
=PP1V5_S3_MEM_A 75A 76A =PP1V5_S3_MEM_A =PP1V5_S3_MEM_A 75B 76B =PP1V5_S3_MEM_A 6.3V 10V
30 29 28 6 VDD_0 VDD_1 6 28 29 30 30 29 28 6 VDD_0 VDD_1 6 28 29 30 2 2

C 77A 78A MEM_A_A<15> 77B 78B MEM_A_A<15>

CERM
402-LF
CERM
402
C

ic
NC_0 A15 12 30 92 NC_0 A15 12 30 92

MEM_A_BA<2> 79A 80A MEM_A_A<14> MEM_A_BA<2> 79B 80B MEM_A_A<14>

92 30 12 BA2 A14 12 30 92 92 30 12 BA2 A14 12 30 92
81A 82A 81B 82B
VDD_2 VDD_3 VDD_2 VDD_3
MEM_A_A<12> 83A 84A MEM_A_A<11> MEM_A_A<12> 83B 84B MEM_A_A<11>
92 30 12 A12/BC* A11 12 30 92 92 30 12 A12/BC* A11 12 30 92

at
MEM_A_A<9> 85A 86A MEM_A_A<7> MEM_A_A<9> 85B 86B MEM_A_A<7> PP0V75_S3_MEM_VREFDQ_A
92 30 12 A9 A7 12 30 92 92 30 12 A9 A7 12 30 92 98 30 28
87A 88A 87B 88B
DIMM 2

DIMM 0
VDD_4 VDD_5 VDD_4 VDD_5
MEM_A_A<8> 89A 90A MEM_A_A<6> MEM_A_A<8> 89B 90B MEM_A_A<6>
92 30 12 A8 A6 12 30 92 92 30 12 A8 A6 12 30 92

MEM_A_A<5> 91A 92A MEM_A_A<4> MEM_A_A<5> 91B 92B MEM_A_A<4>

em
92 30 12 A5 A4 12 30 92 92 30 12 A5 A4 12 30 92
1
C3130 1
C3131
93A 94A 93B 94B
VDD_6 VDD_7 VDD_6 VDD_7 2.2UF 0.1UF
MEM_A_A<3> 95A 96A MEM_A_A<2> MEM_A_A<3> 95B 96B MEM_A_A<2> 20% 20%
92 30 12 A3 A2 12 30 92 92 30 12 A3 A2 12 30 92 6.3V 10V
97A 98A 97B 98B 2 CERM 2 CERM
92 30 12 MEM_A_A<1> A1 A0 MEM_A_A<0> 12 30 92 92 30 12 MEM_A_A<1> A1 A0 MEM_A_A<0> 12 30 92 402-LF 402
99A 100A 99B 100B
VDD_8 VDD_9 VDD_8 VDD_9
=MEM_A_CLK_P<2> 101A 102A =MEM_A_CLK_P<3> =MEM_A_CLK_P<0> 101B 102B =MEM_A_CLK_P<1>
32 CK0 CK1 32 32 CK0 CK1 32

=MEM_A_CLK_N<2> 103A 104A =MEM_A_CLK_N<3> =MEM_A_CLK_N<0> 103B 104B =MEM_A_CLK_N<1>

32 CK0* CK1* 32 32 CK0* CK1* 32

ch
105A 106A 105B 106B
VDD_10 VDD_11 VDD_10 VDD_11 =PP0V75_S0_MEM_VTT_A
MEM_A_A<10> 107A 108A MEM_A_BA<1> MEM_A_A<10> 107B 108B MEM_A_BA<1>
30 6
92 30 12 A10_AP BA1 12 30 92 92 30 12 A10_AP BA1 12 30 92

MEM_A_BA<0> 109A 110A MEM_A_RAS_L MEM_A_BA<0> 109B 110B MEM_A_RAS_L

92 30 12 BA0 RAS* 12 30 92 92 30 12 BA0 RAS* 12 30 92
111A 112A 111B 112B
VDD_12 VDD_13 VDD_12 VDD_13
MEM_A_WE_L 113A 114A MEM_A_CS_L<2> MEM_A_WE_L 113B 114B MEM_A_CS_L<0> 1
C3150 1
C3151

kS
92 30 12 WE* S0* 12 92 92 30 12 WE* S0* 12 92

MEM_A_CAS_L 115A 116A MEM_A_ODT<2> MEM_A_CAS_L 115B 116B MEM_A_ODT<0> 2.2UF 2.2UF
92 30 12 CAS* ODT0 12 92 92 30 12 CAS* ODT0 12 92
20% 20%
117A 118A 117B 118B 6.3V 6.3V
VDD_14 VDD_15 VDD_14 VDD_15 2 CERM 2 CERM
MEM_A_A<13> 119A 120A MEM_A_ODT<3> MEM_A_A<13> 119B 120B MEM_A_ODT<1> 402-LF 402-LF
92 30 12 A13 ODT1 12 92 92 30 12 A13 ODT1 12 92

MEM_A_CS_L<3> 121A 122A MEM_A_CS_L<1> 121B 122B

92 12 S1* NC_1 92 12 S1* NC_1
123A 124A 123B 124B
VDD_16 VDD_17 VDD_16 VDD_17

oo
125A 126A PP0V75_S3_MEM_VREFCA_A 125B 126B PP0V75_S3_MEM_VREFCA_A
TEST VREFCA 28 30 98 TEST VREFCA 28 30 98
127A 128A 127B 128B STACKED SO-DIMM CONN.
VSS_26 VSS_27 VSS_26 VSS_27
129A 130A 129B 130B
B 32 30

32 30
=MEM_A_DQ<32>
=MEM_A_DQ<33> 131A
DQ32
DQ33
DQ36
DQ37
132A
=MEM_A_DQ<36>
=MEM_A_DQ<37>
30 32

30 32
32 30

32 30
=MEM_A_DQ<32>
=MEM_A_DQ<33> 131B
DQ32
DQ33
DQ36
DQ37
132B
=MEM_A_DQ<36>
=MEM_A_DQ<37>
30 32

30 32
DIMM2 B
133A 134A 133B 134B (Section A)
VSS_28 VSS_29 VSS_28 VSS_29
32 30 =MEM_A_DQS_N<4> 135A
DQS4* DM4
136A
eb 32 30 =MEM_A_DQS_N<4> 135B
DQS4* DM4
136B DIMM0
=MEM_A_DQS_P<4> 137A 138A =MEM_A_DQS_P<4> 137B 138B (Section B)
32 30 DQS4 VSS_30 32 30 DQS4 VSS_30
139A 140A =MEM_A_DQ<38> 139B 140B =MEM_A_DQ<38>
VSS_31 DQ38 30 32 VSS_31 DQ38 30 32

=MEM_A_DQ<34> 141A 142A =MEM_A_DQ<39> =MEM_A_DQ<34> 141B 142B =MEM_A_DQ<39>

32 30 DQ34 DQ39 30 32 32 30 DQ34 DQ39 30 32

=MEM_A_DQ<35> 143A 144A =MEM_A_DQ<35> 143B 144B

32 30 DQ35 VSS_32 32 30 DQ35 VSS_32
ot
145A 146A 145B 146B CPU - MEM Ch. A
VSS_33 DQ44 =MEM_A_DQ<44> 30 32 VSS_33 DQ44 =MEM_A_DQ<44> 30 32

=MEM_A_DQ<40> 147A 148A =MEM_A_DQ<45> =MEM_A_DQ<40> 147B 148B =MEM_A_DQ<45>

32 30 DQ40 DQ45 30 32 32 30 DQ40 DQ45 30 32

=MEM_A_DQ<41> 149A 150A =MEM_A_DQ<41> 149B 150B

32 30 DQ41 VSS_34 32 30 DQ41 VSS_34
151A 152A =MEM_A_DQS_N<5> 151B 152B =MEM_A_DQS_N<5>
VSS_35 DQS5* 30 32 VSS_35 DQS5* 30 32
Page Notes
N

153A 154A =MEM_A_DQS_P<5> 153B 154B =MEM_A_DQS_P<5>

DM5 DQS5 30 32 DM5 DQS5 30 32
155A 156A 155B 156B
VSS_36 VSS_37 VSS_36 VSS_37
157A 158A 157B 158B Power aliases required by this page:
32 30 =MEM_A_DQ<42> DQ42 DQ46 =MEM_A_DQ<46> 30 32 32 30 =MEM_A_DQ<42> DQ42 DQ46 =MEM_A_DQ<46> 30 32
159A 160A 159B 160B - =PP1V5_S0_MEM_A
32 30 =MEM_A_DQ<43> DQ43 DQ47 =MEM_A_DQ<47> 30 32 32 30 =MEM_A_DQ<43> DQ43 DQ47 =MEM_A_DQ<47> 30 32
161A 162A 161B 162B - =PP1V5_S3_MEM_A
VSS_38 VSS_39 VSS_38 VSS_39
163A 164A 163B 164B - =PP0V75_S0_MEM_VTT_A
32 30 =MEM_A_DQ<48> DQ48 DQ52 =MEM_A_DQ<52> 30 32 32 30 =MEM_A_DQ<48> DQ48 DQ52 =MEM_A_DQ<52> 30 32
165A 166A 165B 166B - =PPSPD_S0_MEM_A (2.5 - 3.3V)
32 30 =MEM_A_DQ<49> DQ49 DQ53 =MEM_A_DQ<53> 30 32 32 30 =MEM_A_DQ<49> DQ49 DQ53 =MEM_A_DQ<53> 30 32
167A 168A 167B 168B Signal aliases required by this page:
VSS_40 VSS_41 VSS_40 VSS_41
=MEM_A_DQS_N<6> 169A 170A =MEM_A_DQS_N<6> 169B 170B - =I2C_SODIMMA_SCL - ALL DQ, DQS, DM SIGNALS;
32 30 DQS6* DM6 32 30 DQS6* DM6 TO FACILITATE BITSWAPS WITH ALIASES
=MEM_A_DQS_P<6> 171A 172A =MEM_A_DQS_P<6> 171B 172B - =I2C_SODIMMA_SDA
32 30 DQS6 VSS_42 32 30 DQS6 VSS_42
173A 174A =MEM_A_DQ<54> 173B 174B =MEM_A_DQ<54>
VSS_43 DQ54 30 32 VSS_43 DQ54 30 32
175A 176A 175B 176B BOM options provided by this page:
32 30 =MEM_A_DQ<50> DQ50 DQ55 =MEM_A_DQ<55> 30 32 32 30 =MEM_A_DQ<50> DQ50 DQ55 =MEM_A_DQ<55> 30 32
177A 178A 177B 178B (NONE)
32 30 =MEM_A_DQ<51> DQ51 VSS_44 32 30 =MEM_A_DQ<51> DQ51 VSS_44
179A 180A =MEM_A_DQ<60> 179B 180B =MEM_A_DQ<60>
VSS_45 DQ60 30 32 VSS_45 DQ60 30 32

A 32 30 =MEM_A_DQ<56>
=MEM_A_DQ<57>
181A
183A
DQ56 DQ61
182A
184A
=MEM_A_DQ<61> 30 32 32 30 =MEM_A_DQ<56>
=MEM_A_DQ<57>
181B
183B
DQ56 DQ61
182B
184B
=MEM_A_DQ<61> 30 32
SYNC_MASTER=K62_ROSITA SYNC_DATE=01/09/2011 A
32 30 DQ57 VSS_46 32 30 DQ57 VSS_46 PAGE TITLE
185A 186A 185B 186B
187A
VSS_47
DM7
DQS7*
DQS7
188A
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
30 32

30 32
187B
VSS_47
DM7
DQS7*
DQS7
188B
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
30 32

30 32
DDR3 SO-DIMM 0 & 2
189A 190A 189B 190B DRAWING NUMBER SIZE
VSS_48 VSS_49 VSS_48 VSS_49 051-8442 D
32 30 =MEM_A_DQ<58> 191A
DQ58 DQ62
192A =MEM_A_DQ<62> 30 32 32 30 =MEM_A_DQ<58> 191B
DQ58 DQ62
192B =MEM_A_DQ<62> 30 32 Apple Inc. REVISION
=MEM_A_DQ<59> 193A 194A =MEM_A_DQ<63> =MEM_A_DQ<59> 193B 194B =MEM_A_DQ<63>
32 30 DQ59 DQ63 30 32 32 30 DQ59 DQ63 30 32 R
195A 196A 195B 196B 10.1.0
VSS_50 VSS_51 VSS_50 VSS_51 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MEM_DIMM2_SA<0> 197A 198A MEM_EVENT_L MEM_DIMM0_SA<0> 197B 198B MEM_EVENT_L
30 SA0 EVENT* 30 31 47 30 SA0 EVENT* 30 31 47
199A 200A 199B 200B THE INFORMATION CONTAINED HEREIN IS THE
47 30 6 =PPSPD_S0_MEM_A VDDSPD SDA =I2C_SODIMMA_SDA 30 49 47 30 6 =PPSPD_S0_MEM_A VDDSPD SDA =I2C_SODIMMA_SDA 30 49 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
201A 202A 201B 202B THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MEM_DIMM2_SA<1> SA1 SCL =I2C_SODIMMA_SCL MEM_DIMM0_SA<1> SA1 SCL =I2C_SODIMMA_SCL
30

=PP0V75_S0_MEM_VTT_A 203A 204A =PP0V75_S0_MEM_VTT_A

30 49 30

=PP0V75_S0_MEM_VTT_A 203B 204B =PP0V75_S0_MEM_VTT_A

30 49
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
31 OF 110
30 6 VTT_0 VTT_1 6 30 30 6 VTT_0 VTT_1 6 30
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
409
MTG PIN MTG PIN
410 IV ALL RIGHTS RESERVED 30 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP0V75_S3_MEM_VREFDQ_B 1A 2A PP0V75_S3_MEM_VREFDQ_B 1B 2B
98 31 28 VREFDQ
CRITICALVSS_0
98 31 28 VREFDQ
CRITICALVSS_0
3A 4A =MEM_B_DQ<4> 3B 4B =MEM_B_DQ<4>
VSS_1 DQ4 VSS_1 DQ4
32 31 =MEM_B_DQ<0> 5A
DQ0 J3200 DQ5
6A =MEM_B_DQ<5>
31 32

31 32 32 31 =MEM_B_DQ<0> 5B
DQ0
J3200 DQ5
6B =MEM_B_DQ<5>
31 32

31 32
DIMM1 SPD ADDR=0XA4(WR)/0XA5(RD) DIMM3 SPD ADDR=0XA6(WR)/0XA7(RD)
7A F-RT-TH 8A 7B F-RT-TH 8B
32 31 =MEM_B_DQ<1> DQ1 VSS_2 32 31 =MEM_B_DQ<1> DQ1 VSS_2 31 6 =PPSPD_S0_MEM_B 31 6 =PPSPD_S0_MEM_B
9A (1 OF 2) 10A =MEM_B_DQS_N<0> 9B (2 OF 2) 10B =MEM_B_DQS_N<0>

DDR3-SODIMM-DUAL
VSS_3 DQS0* 31 32 VSS_3 DQS0* 31 32

DDR3-SODIMM-DUAL
11A 12A =MEM_B_DQS_P<0> 11B 12B =MEM_B_DQS_P<0>
DM0 DQS0 31 32 DM0 DQS0 31 32
1 1 1
13A 14A 13B 14B R3240 R3242 R3243
VSS_4 VSS_5 VSS_4 VSS_5 10K 10K 10K
=MEM_B_DQ<2> 15A 16A =MEM_B_DQ<6> =MEM_B_DQ<2> 15B 16B =MEM_B_DQ<6>
32 31 DQ2 DQ6 31 32 32 31 DQ2 DQ6 31 32 5% 5% 5%
17A 18A 17B 18B 1/16W 1/16W 1/16W
32 31 =MEM_B_DQ<3> DQ3 DQ7 =MEM_B_DQ<7> 31 32 32 31 =MEM_B_DQ<3> DQ3 DQ7 =MEM_B_DQ<7> 31 32 MF-LF MF-LF MF-LF
19A 20A 19B 20B 402 402 402
2 2 2
VSS_6 VSS_7 VSS_6 VSS_7
=MEM_B_DQ<8> 21A 22A =MEM_B_DQ<12> =MEM_B_DQ<8> 21B 22B =MEM_B_DQ<12>
32 31 DQ8 DQ12 31 32 32 31 DQ8 DQ12 31 32
MEM_DIMM3_SA<1>
=MEM_B_DQ<9> 23A 24A =MEM_B_DQ<13> =MEM_B_DQ<9> 23B 24B =MEM_B_DQ<13> MEM_DIMM1_SA<1>
31
32 31 DQ9 DQ13 31 32 32 31 DQ9 DQ13 31 32 31

D 25A
27A
VSS_8 VSS_9
26A
28A
25B
27B
VSS_8 VSS_9
26B
28B
31 MEM_DIMM1_SA<0> 31 MEM_DIMM3_SA<0> D
32 31 =MEM_B_DQS_N<1> DQS1* DM1 32 31 =MEM_B_DQS_N<1> DQS1* DM1
=MEM_B_DQS_P<1> 29A 30A MEM_RESET_L =MEM_B_DQS_P<1> 29B 30B MEM_RESET_L
32 31 DQS1 RESET* 30 31 32 92 100 32 31 DQS1 RESET* 30 31 32 92 100
1
31A
VSS_10 VSS_11
32A 31B
VSS_10 VSS_11
32B R3241
33A 34A 33B 34B 10K
32 31 =MEM_B_DQ<10> DQ10 DQ14 =MEM_B_DQ<14> 31 32 32 31 =MEM_B_DQ<10> DQ10 DQ14 =MEM_B_DQ<14> 31 32 5%
35A 36A 35B 36B 1/16W
32 31 =MEM_B_DQ<11> DQ11 DQ15 =MEM_B_DQ<15> 31 32 32 31 =MEM_B_DQ<11> DQ11 DQ15 =MEM_B_DQ<15> 31 32 MF-LF
37A 38A 37B 38B 402
2
VSS_12 VSS_13 VSS_12 VSS_13
=MEM_B_DQ<16> 39A 40A =MEM_B_DQ<20> =MEM_B_DQ<16> 39B 40B =MEM_B_DQ<20>
32 31 DQ16 DQ20 31 32 32 31 DQ16 DQ20 31 32

=MEM_B_DQ<17> 41A 42A =MEM_B_DQ<21> =MEM_B_DQ<17> 41B 42B =MEM_B_DQ<21>

32 31 DQ17 DQ21 31 32 32 31 DQ17 DQ21 31 32
43A 44A 43B 44B
VSS_14 VSS_15 VSS_14 VSS_15 =PPSPD_S0_MEM_B
=MEM_B_DQS_N<2> 45A 46A =MEM_B_DQS_N<2> 45B 46B 31 6
32 31 DQS2* DM2 32 31 DQS2* DM2
=MEM_B_DQS_P<2> 47A 48A =MEM_B_DQS_P<2> 47B 48B
32 31 DQS2 VSS_16 32 31 DQS2 VSS_16
49A 50A =MEM_B_DQ<22> 49B 50B =MEM_B_DQ<22>
VSS_17 DQ22 31 32 VSS_17 DQ22 31 32

=MEM_B_DQ<18> 51A 52A =MEM_B_DQ<23> =MEM_B_DQ<18> 51B 52B =MEM_B_DQ<23>

1
C3240
32 31 DQ18 DQ23 31 32 32 31 DQ18 DQ23 31 32
2.2UF
=MEM_B_DQ<19> 53A 54A =MEM_B_DQ<19> 53B 54B 20%
32 31 DQ19 VSS_18 32 31 DQ19 VSS_18 6.3V

m
55A 56A 55B 56B 2 CERM
VSS_19 DQ28 =MEM_B_DQ<28> 31 32 VSS_19 DQ28 =MEM_B_DQ<28> 31 32
402-LF
=MEM_B_DQ<24> 57A 58A =MEM_B_DQ<29> =MEM_B_DQ<24> 57B 58B =MEM_B_DQ<29>
32 31 DQ24 DQ29 31 32 32 31 DQ24 DQ29 31 32

=MEM_B_DQ<25> 59A 60A =MEM_B_DQ<25> 59B 60B

32 31 DQ25 VSS_20 32 31 DQ25 VSS_20
61A 62A =MEM_B_DQS_N<3> 61B 62B =MEM_B_DQS_N<3>
VSS_21 DQS3* 31 32 VSS_21 DQS3* 31 32

co
63A 64A =MEM_B_DQS_P<3> 63B 64B =MEM_B_DQS_P<3>
DM3 DQS3 31 32 DM3 DQS3 31 32
65A 66A 65B 66B
VSS_22 VSS_23 VSS_22 VSS_23 PP0V75_S3_MEM_VREFCA_B
=MEM_B_DQ<26> 67A 68A =MEM_B_DQ<30> =MEM_B_DQ<26> 67B 68B =MEM_B_DQ<30>
98 31 28
32 31 DQ26 DQ30 31 32 32 31 DQ26 DQ30 31 32

=MEM_B_DQ<27> 69A 70A =MEM_B_DQ<31> =MEM_B_DQ<27> 69B 70B =MEM_B_DQ<31>

32 31 DQ27 DQ31 31 32 32 31 DQ27 DQ31 31 32
71A 72A 71B 72B

s.
VSS_24 VSS_25 VSS_24 VSS_25
73A KEY 74A 73B KEY 74B
92 12 MEM_B_CKE<2> CKE0 CKE1 MEM_B_CKE<3> 12 92 92 12 MEM_B_CKE<0> CKE0 CKE1 MEM_B_CKE<1> 12 92
1
C3235 1
C3236
=PP1V5_S3_MEM_B 75A 76A =PP1V5_S3_MEM_B =PP1V5_S3_MEM_B 75B 76B =PP1V5_S3_MEM_B 2.2UF 0.1UF
31 29 28 6 VDD_0 VDD_1 6 28 29 31 31 29 28 6 VDD_0 VDD_1 6 28 29 31

C 77A 78A MEM_B_A<15> 77B 78B MEM_B_A<15>

20%
6.3V
20%
10V
C

ic
NC_0 A15 12 31 92 NC_0 A15 12 31 92 2 CERM 2 CERM
MEM_B_BA<2> 79A 80A MEM_B_A<14> MEM_B_BA<2> 79B 80B MEM_B_A<14> 402-LF 402
92 31 12 BA2 A14 12 31 92 92 31 12 BA2 A14 12 31 92
81A 82A 81B 82B
VDD_2 VDD_3 VDD_2 VDD_3
MEM_B_A<12> 83A 84A MEM_B_A<11> MEM_B_A<12> 83B 84B MEM_B_A<11>
92 31 12 A12/BC* A11 12 31 92 92 31 12 A12/BC* A11 12 31 92

at
MEM_B_A<9> 85A 86A MEM_B_A<7> MEM_B_A<9> 85B 86B MEM_B_A<7>
92 31 12 A9 A7 12 31 92 92 31 12 A9 A7 12 31 92
87A 88A 87B 88B
DIMM 3

DIMM 1
VDD_4 VDD_5 VDD_4 VDD_5 98 31 28 PP0V75_S3_MEM_VREFDQ_B
MEM_B_A<8> 89A 90A MEM_B_A<6> MEM_B_A<8> 89B 90B MEM_B_A<6>
92 31 12 A8 A6 12 31 92 92 31 12 A8 A6 12 31 92

MEM_B_A<5> 91A 92A MEM_B_A<4> MEM_B_A<5> 91B 92B MEM_B_A<4>

em
92 31 12 A5 A4 12 31 92 92 31 12 A5 A4 12 31 92
93A 94A 93B 94B
VDD_6 VDD_7 VDD_6 VDD_7
MEM_B_A<3> 95A 96A MEM_B_A<2> MEM_B_A<3> 95B 96B MEM_B_A<2>
1
C3230 1
C3231
92 31 12 A3 A2 12 31 92 92 31 12 A3 A2 12 31 92
2.2UF 0.1UF
MEM_B_A<1> 97A 98A MEM_B_A<0> MEM_B_A<1> 97B 98B MEM_B_A<0> 20% 20%
92 31 12 A1 A0 12 31 92 92 31 12 A1 A0 12 31 92
2
6.3V
2
10V
99A 100A 99B 100B CERM CERM
VDD_8 VDD_9 VDD_8 VDD_9 402-LF 402
=MEM_B_CLK_P<2> 101A 102A =MEM_B_CLK_P<3> =MEM_B_CLK_P<0> 101B 102B =MEM_B_CLK_P<1>
32 CK0 CK1 32 32 CK0 CK1 32

=MEM_B_CLK_N<2> 103A 104A =MEM_B_CLK_N<3> =MEM_B_CLK_N<0> 103B 104B =MEM_B_CLK_N<1>

32 CK0* CK1* 32 32 CK0* CK1* 32

ch
105A 106A 105B 106B
VDD_10 VDD_11 VDD_10 VDD_11
MEM_B_A<10> 107A 108A MEM_B_BA<1> MEM_B_A<10> 107B 108B MEM_B_BA<1>
92 31 12 A10_AP BA1 12 31 92 92 31 12 A10_AP BA1 12 31 92
31 6 =PP0V75_S0_MEM_VTT_B
MEM_B_BA<0> 109A 110A MEM_B_RAS_L MEM_B_BA<0> 109B 110B MEM_B_RAS_L
92 31 12 BA0 RAS* 12 31 92 92 31 12 BA0 RAS* 12 31 92
111A 112A 111B 112B
VDD_12 VDD_13 VDD_12 VDD_13
MEM_B_WE_L 113A 114A MEM_B_CS_L<2> MEM_B_WE_L 113B 114B MEM_B_CS_L<0>

kS
92 31 12 WE* S0* 12 92 92 31 12 WE* S0* 12 92

MEM_B_CAS_L 115A 116A MEM_B_ODT<2> MEM_B_CAS_L 115B 116B MEM_B_ODT<0> 1

C3250 1
C3251
92 31 12 CAS* ODT0 12 92 92 31 12 CAS* ODT0 12 92
117A 118A 117B 118B 2.2UF 2.2UF
VDD_14 VDD_15 VDD_14 VDD_15 20% 20%
MEM_B_A<13> 119A 120A MEM_B_ODT<3> MEM_B_A<13> 119B 120B MEM_B_ODT<1> 6.3V 6.3V
92 31 12 A13 ODT1 12 92 92 31 12 A13 ODT1 12 92 2 CERM 2 CERM
MEM_B_CS_L<3> 121A 122A MEM_B_CS_L<1> 121B 122B 402-LF 402-LF
92 12 S1* NC_1 92 12 S1* NC_1
123A 124A 123B 124B
VDD_16 VDD_17 VDD_16 VDD_17

oo
125A 126A PP0V75_S3_MEM_VREFCA_B 125B 126B PP0V75_S3_MEM_VREFCA_B
TEST VREFCA 28 31 98 TEST VREFCA 28 31 98
127A 128A 127B 128B STACKED SO-DIMM CONN.
VSS_26 VSS_27 VSS_26 VSS_27
129A 130A 129B 130B
B 32 31

32 31
=MEM_B_DQ<32>
=MEM_B_DQ<33> 131A
DQ32
DQ33
DQ36
DQ37
132A
=MEM_B_DQ<36>
=MEM_B_DQ<37>
31 32

31 32
32 31

32 31
=MEM_B_DQ<32>
=MEM_B_DQ<33> 131B
DQ32
DQ33
DQ36
DQ37
132B
=MEM_B_DQ<36>
=MEM_B_DQ<37>
31 32

31 32
DIMM3 B
133A 134A 133B 134B (Section A)
VSS_28 VSS_29 VSS_28 VSS_29
32 31 =MEM_B_DQS_N<4> 135A
DQS4* DM4
136A
eb 32 31 =MEM_B_DQS_N<4> 135B
DQS4* DM4
136B DIMM1
=MEM_B_DQS_P<4> 137A 138A =MEM_B_DQS_P<4> 137B 138B (Section B)
32 31 DQS4 VSS_30 32 31 DQS4 VSS_30
139A 140A =MEM_B_DQ<38> 139B 140B =MEM_B_DQ<38>
VSS_31 DQ38 31 32 VSS_31 DQ38 31 32

=MEM_B_DQ<34> 141A 142A =MEM_B_DQ<39> =MEM_B_DQ<34> 141B 142B =MEM_B_DQ<39>

32 31 DQ34 DQ39 31 32 32 31 DQ34 DQ39 31 32

=MEM_B_DQ<35> 143A 144A =MEM_B_DQ<35> 143B 144B

32 31 DQ35 VSS_32 32 31 DQ35 VSS_32
ot
145A 146A 145B 146B CPU - MEM Ch. B
VSS_33 DQ44 =MEM_B_DQ<44> 31 32 VSS_33 DQ44 =MEM_B_DQ<44> 31 32

=MEM_B_DQ<40> 147A 148A =MEM_B_DQ<45> =MEM_B_DQ<40> 147B 148B =MEM_B_DQ<45>

32 31 DQ40 DQ45 31 32 32 31 DQ40 DQ45 31 32

=MEM_B_DQ<41> 149A 150A =MEM_B_DQ<41> 149B 150B

32 31 DQ41 VSS_34 32 31 DQ41 VSS_34
151A 152A =MEM_B_DQS_N<5> 151B 152B =MEM_B_DQS_N<5>
VSS_35 DQS5* 31 32 VSS_35 DQS5* 31 32
Page Notes
N

153A 154A =MEM_B_DQS_P<5> 153B 154B =MEM_B_DQS_P<5>

DM5 DQS5 31 32 DM5 DQS5 31 32
155A 156A 155B 156B
VSS_36 VSS_37 VSS_36 VSS_37
157A 158A 157B 158B Power aliases required by this page:
32 31 =MEM_B_DQ<42> DQ42 DQ46 =MEM_B_DQ<46> 31 32 32 31 =MEM_B_DQ<42> DQ42 DQ46 =MEM_B_DQ<46> 31 32
159A 160A 159B 160B - =PP1V5_S0_MEM_B
32 31 =MEM_B_DQ<43> DQ43 DQ47 =MEM_B_DQ<47> 31 32 32 31 =MEM_B_DQ<43> DQ43 DQ47 =MEM_B_DQ<47> 31 32
161A 162A 161B 162B - =PP1V5_S3_MEM_B
VSS_38 VSS_39 VSS_38 VSS_39
163A 164A 163B 164B - =PP0V75_S0_MEM_VTT_B
32 31 =MEM_B_DQ<48> DQ48 DQ52 =MEM_B_DQ<52> 31 32 32 31 =MEM_B_DQ<48> DQ48 DQ52 =MEM_B_DQ<52> 31 32
165A 166A 165B 166B - =PPSPD_S0_MEM_B (2.5 - 3.3V)
32 31 =MEM_B_DQ<49> DQ49 DQ53 =MEM_B_DQ<53> 31 32 32 31 =MEM_B_DQ<49> DQ49 DQ53 =MEM_B_DQ<53> 31 32
167A 168A 167B 168B Signal aliases required by this page:
VSS_40 VSS_41 VSS_40 VSS_41
=MEM_B_DQS_N<6> 169A 170A =MEM_B_DQS_N<6> 169B 170B - =I2C_SODIMMB_SCL - ALL DQ, DQS, DM SIGNALS;
32 31 DQS6* DM6 32 31 DQS6* DM6 TO FACILITATE BITSWAPS WITH ALIASES
=MEM_B_DQS_P<6> 171A 172A =MEM_B_DQS_P<6> 171B 172B - =I2C_SODIMMB_SDA
32 31 DQS6 VSS_42 32 31 DQS6 VSS_42
173A 174A =MEM_B_DQ<54> 173B 174B =MEM_B_DQ<54>
VSS_43 DQ54 31 32 VSS_43 DQ54 31 32
175A 176A 175B 176B BOM options provided by this page:
32 31 =MEM_B_DQ<50> DQ50 DQ55 =MEM_B_DQ<55> 31 32 32 31 =MEM_B_DQ<50> DQ50 DQ55 =MEM_B_DQ<55> 31 32
177A 178A 177B 178B (NONE)
32 31 =MEM_B_DQ<51> DQ51 VSS_44 32 31 =MEM_B_DQ<51> DQ51 VSS_44
179A 180A =MEM_B_DQ<60> 179B 180B =MEM_B_DQ<60>
VSS_45 DQ60 31 32 VSS_45 DQ60 31 32

A 32 31 =MEM_B_DQ<56>
=MEM_B_DQ<57>
181A
183A
DQ56 DQ61
182A
184A
=MEM_B_DQ<61> 31 32 32 31 =MEM_B_DQ<56>
=MEM_B_DQ<57>
181B
183B
DQ56 DQ61
182B
184B
=MEM_B_DQ<61> 31 32
SYNC_MASTER=K62_ROSITA SYNC_DATE=01/09/2011 A
32 31 DQ57 VSS_46 32 31 DQ57 VSS_46 PAGE TITLE
185A 186A 185B 186B
187A
VSS_47
DM7
DQS7*
DQS7
188A
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
31 32

31 32
187B
VSS_47
DM7
DQS7*
DQS7
188B
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
31 32

31 32
DDR3 SO-DIMM 1 & 3
189A 190A 189B 190B DRAWING NUMBER SIZE
VSS_48 VSS_49 VSS_48 VSS_49 051-8442 D
32 31 =MEM_B_DQ<58> 191A
DQ58 DQ62
192A =MEM_B_DQ<62> 31 32 32 31 =MEM_B_DQ<58> 191B
DQ58 DQ62
192B =MEM_B_DQ<62> 31 32 Apple Inc. REVISION
=MEM_B_DQ<59> 193A 194A =MEM_B_DQ<63> =MEM_B_DQ<59> 193B 194B =MEM_B_DQ<63>
32 31 DQ59 DQ63 31 32 32 31 DQ59 DQ63 31 32 R
195A 196A 195B 196B 10.1.0
VSS_50 VSS_51 VSS_50 VSS_51 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MEM_DIMM3_SA<0> 197A 198A MEM_EVENT_L MEM_DIMM1_SA<0> 197B 198B MEM_EVENT_L
31 SA0 EVENT* 30 31 47 31 SA0 EVENT* 30 31 47
199A 200A 199B 200B THE INFORMATION CONTAINED HEREIN IS THE
31 6 =PPSPD_S0_MEM_B VDDSPD SDA =I2C_SODIMMB_SDA 31 49 31 6 =PPSPD_S0_MEM_B VDDSPD SDA =I2C_SODIMMB_SDA 31 49 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
201A 202A 201B 202B THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MEM_DIMM3_SA<1> SA1 SCL =I2C_SODIMMB_SCL MEM_DIMM1_SA<1> SA1 SCL =I2C_SODIMMB_SCL
31

=PP0V75_S0_MEM_VTT_B 203A 204A =PP0V75_S0_MEM_VTT_B

31 49 31

=PP0V75_S0_MEM_VTT_B 203B 204B =PP0V75_S0_MEM_VTT_B

31 49
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
32 OF 110
31 6 VTT_0 VTT_1 6 31 31 6 VTT_0 VTT_1 6 31
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
409
MTG PIN MTG PIN
410 IV ALL RIGHTS RESERVED 31 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CPU CHANNEL A DQS 0 -> DIMM A DQS 7 CPU CHANNEL B DQS 0 -> DIMM B DQS 7
DDR3 RESET SUPPORT S5
CPU_RESET_L
0
ISOLATE_L
3.3V
MEM_RESET_L
0
SNB? CANNOT CONTROL THIS SIGNAL DIRECTLY SINCE IT MUST BE HIGH IN SLEEP AND CPU MEM RAILS ARE NOT POWERED IN SLEEP.
92 12 MEM_A_DQS_N<0> =MEM_A_DQS_N<7> 30 92 12 MEM_B_DQS_N<0> =MEM_B_DQS_N<7> 31
S0 0 3.3V 0
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
92 12 MEM_A_DQS_P<0> =MEM_A_DQS_P<7> 30 92 12 MEM_B_DQS_P<0> =MEM_B_DQS_P<7> 31
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE S0 1.5V 3.3V 1.5V
92 12 MEM_A_DQ<7> =MEM_A_DQ<57> MEM_B_DQ<7> =MEM_B_DQ<61> 32 6 =PP3V3_S3_MEMRESET 32 6 =PP5V_S3_MEMRESET 6 =PP1V5_S3_MEMRESET
30 92 12 31
MAKE_BASE=TRUE MAKE_BASE=TRUE S3 0 0 1.5V
92 12 MEM_A_DQ<6> =MEM_A_DQ<56> 30 92 12 MEM_B_DQ<6> =MEM_B_DQ<60> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
R33501
1
92 12 MEM_A_DQ<5> =MEM_A_DQ<58> 30 92 12 MEM_B_DQ<5> =MEM_B_DQ<62> 31 R3351 R33521 NOSTUFF 1
S0 1.5V 3.3V 1.5V
MAKE_BASE=TRUE MAKE_BASE=TRUE R3353
92 12 MEM_A_DQ<4>
MAKE_BASE=TRUE
=MEM_A_DQ<59> 30 92 12 MEM_B_DQ<4>
MAKE_BASE=TRUE
=MEM_B_DQ<63> 31
20K
5%
20K
5%
20K
5%
R3355 C3353 1
20K S5 0 3.3V 0
92 12 MEM_A_DQ<3> =MEM_A_DQ<60> 30 92 12 MEM_B_DQ<3> =MEM_B_DQ<56> 31
1/16W 1/16W 1/16W
CPU_MEM_RESET_L 1
0 2
0.0022UF 5%
MAKE_BASE=TRUE MAKE_BASE=TRUE MF-LF MF-LF MF-LF 100 32 11 10% 1/16W

D 92 12

92 12
MEM_A_DQ<2>
MEM_A_DQ<1>
MAKE_BASE=TRUE
=MEM_A_DQ<61>
=MEM_A_DQ<62>
30

30
92 12

92 12
MEM_B_DQ<2>
MEM_B_DQ<1>
MAKE_BASE=TRUE
=MEM_B_DQ<57>
=MEM_B_DQ<58>
31

31
402
2 2 402

ISOLATE_CPU_MEM
402
2 5%
1/16W
MF-LF
50V
CERM 2
402 2
MF-LF
402 D
MAKE_BASE=TRUE MAKE_BASE=TRUE 402
92 12 MEM_A_DQ<0> =MEM_A_DQ<63> 30 92 12 MEM_B_DQ<0> =MEM_B_DQ<59> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
6
CPU CHANNEL A DQS 1 -> DIMM A DQS 6 CPU CHANNEL B DQS 1 -> DIMM B DQS 6 3 2 3 MEM_RESET_L 30 31 92 100
MEM_A_DQS_N<1> =MEM_A_DQS_N<6> MEM_B_DQS_N<1> =MEM_B_DQS_N<6> D S D
92 12

MEM_A_DQS_P<1>
MAKE_BASE=TRUE NO_TEST=TRUE
=MEM_A_DQS_P<6>
30 92 12

MEM_B_DQS_P<1>
MAKE_BASE=TRUE NO_TEST=TRUE
=MEM_B_DQS_P<6>
31
Q3306 D
Q3306
Q3304
92 12
MAKE_BASE=TRUE NO_TEST=TRUE
30 92 12
MAKE_BASE=TRUE NO_TEST=TRUE
31
2
2N7002DW-X-G 2N7002 G
32 ISOLATE_CPU_MEM_L_R1 G S SOT-363 2N7002DW-X-G SOT23-HF1
5 G S SOT-363 S R CLK D Q QB
92 12 MEM_A_DQ<15> =MEM_A_DQ<49> 30 92 12 MEM_B_DQ<15> =MEM_B_DQ<51> 31
1 L H X X H L
MAKE_BASE=TRUE MAKE_BASE=TRUE 1
92 12 MEM_A_DQ<14> =MEM_A_DQ<52> 30 92 12 MEM_B_DQ<14> =MEM_B_DQ<54> 31
4 ISOLATE_CPU_MEM_5V_L H L X X L H
MAKE_BASE=TRUE MAKE_BASE=TRUE
92 12 MEM_A_DQ<13> =MEM_A_DQ<51> 30 92 12 MEM_B_DQ<13> =MEM_B_DQ<53> 31 L L X X H H
MAKE_BASE=TRUE MAKE_BASE=TRUE
92 12 MEM_A_DQ<12> =MEM_A_DQ<50> 30 92 12 MEM_B_DQ<12> =MEM_B_DQ<52> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE H H POSEDGE L L H
92 12 MEM_A_DQ<11> =MEM_A_DQ<48> 30 92 12 MEM_B_DQ<11> =MEM_B_DQ<48> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
92 12 MEM_A_DQ<10> =MEM_A_DQ<53> 30 92 12 MEM_B_DQ<10> =MEM_B_DQ<49> 31 H H POSEDGE H H L
MAKE_BASE=TRUE MAKE_BASE=TRUE
MEM_A_DQ<9> =MEM_A_DQ<55> MEM_B_DQ<9> =MEM_B_DQ<50> =PP3V3_S5_MEMRESET
92 12
MAKE_BASE=TRUE
30 92 12
MAKE_BASE=TRUE
31 32 6
R3385
92 12 MEM_A_DQ<8> =MEM_A_DQ<54> 30 92 12 MEM_B_DQ<8> =MEM_B_DQ<55> 31 0
ISOLATE_CPU_MEM_L

m
MAKE_BASE=TRUE MAKE_BASE=TRUE 100 25 21 1 2
MEM_RESET_HW
CPU CHANNEL A DQS 2 -> DIMM A DQS 5 CPU CHANNEL B DQS 2 -> DIMM B DQS 5 C3300 1 5%

14
MEM_RESET_HW 1/16W
92 12 MEM_A_DQS_N<2> =MEM_A_DQS_N<5> 30 92 12 MEM_B_DQS_N<2> =MEM_B_DQS_N<5> 31
0.1UF MF-LF
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 20% 402 =PP3V3_S5_MEMRESET
MEM_A_DQS_P<2> =MEM_A_DQS_P<5> MEM_B_DQS_P<2> =MEM_B_DQS_P<5> 10V VCC 32 6
CERM 2
92 12
MAKE_BASE=TRUE NO_TEST=TRUE
30 92 12
MAKE_BASE=TRUE NO_TEST=TRUE
31
U3300

co
402
MEM_A_DQ<23> =MEM_A_DQ<40> MEM_B_DQ<23> =MEM_B_DQ<45>
74LVC74ABQ MEM_RESET_HW
1
MEM_RESET_HW
1
92 12
MAKE_BASE=TRUE
30 92 12
MAKE_BASE=TRUE
31
DHVQFN R3381 R3382
92 12 MEM_A_DQ<22> =MEM_A_DQ<45> 30 92 12 MEM_B_DQ<22> =MEM_B_DQ<40> 31
4 1SD* 1Q 5 PM_SLP_S4_D_L 32 100 10K 10K
MAKE_BASE=TRUE MAKE_BASE=TRUE 2 1D NOSTUFF 5% 5%
92 12 MEM_A_DQ<21> =MEM_A_DQ<46> 30 92 12 MEM_B_DQ<21> =MEM_B_DQ<42> 31 100 63 47 46 19 5 PM_SLP_S4_L 1Q* 6 TP_PM_SLP_S4_D
R3383 1/16W 1/16W
MAKE_BASE=TRUE MAKE_BASE=TRUE 3 1CP MF-LF MF-LF
92 12 MEM_A_DQ<20> =MEM_A_DQ<47> 30 92 12 MEM_B_DQ<20> =MEM_B_DQ<47> 31 100 64 19 PM_SYS_PWRGD
ISOLATE_CPU_MEMHW_L 1
0 2 ISOLATE_CPU_MEM_L_R1 2 402
2 402

s.
MAKE_BASE=TRUE MAKE_BASE=TRUE 1 1RD* 32
92 12 MEM_A_DQ<19> =MEM_A_DQ<41> 30 92 12 MEM_B_DQ<19> =MEM_B_DQ<44> 31 32 6 =PP3V3_S3_MEMRESET
MAKE_BASE=TRUE MAKE_BASE=TRUE 5%
92 12 MEM_A_DQ<18> =MEM_A_DQ<44> 30 92 12 MEM_B_DQ<18> =MEM_B_DQ<41> 31 10 2SD* 1/16W CPU_MEM_RESET3V3_L
MAKE_BASE=TRUE MAKE_BASE=TRUE 100 32 PM_SLP_S4_D_L 2Q 9 MF-LF 32
92 12 MEM_A_DQ<17> =MEM_A_DQ<43> 30 92 12 MEM_B_DQ<17> =MEM_B_DQ<46> 31 12 2D 402 CPU_MEM_RESET3V3
2Q* 8
C MEM_A_DQ<16>
MAKE_BASE=TRUE
=MEM_A_DQ<42> MEM_B_DQ<16>
MAKE_BASE=TRUE
=MEM_B_DQ<43>
32 6 =PP3V3_S3_MEMRESET TP_ISOLATE_CPU
C

ic
92 12 30 92 12 31 11 2CP
MAKE_BASE=TRUE MAKE_BASE=TRUE 32 CPU_MEM_RESET3V3_L 3 MEM_RESET_HW
CPU CHANNEL A DQS 3 -> DIMM A DQS 4 CPU CHANNEL B DQS 3 -> DIMM B DQS 4 PM_SLP_S3_L 13 2RD* MEM_RESET_HW
MEM_A_DQS_N<3> =MEM_A_DQS_N<4> MEM_B_DQS_N<3> =MEM_B_DQS_N<4>
100 63 47 46 36 32 26 19 5
THRM R3380 3
MEM_RESET_HW
D Q3350
92 12
MAKE_BASE=TRUE NO_TEST=TRUE
30 92 12
MAKE_BASE=TRUE NO_TEST=TRUE
31
GND PAD 10K 2N7002
Q3360

at
MEM_A_DQS_P<3> =MEM_A_DQS_P<4> MEM_B_DQS_P<3> =MEM_B_DQS_P<4> CPU_MEM_RESET_L 1 2 CPU_MEM_RESET_R_L 1 SOT23-HF1
92 12 30 92 12 31 100 32 11 1 G S

15
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 2N3904
5%
1/16W SOT23-HF
92 12 MEM_A_DQ<31> =MEM_A_DQ<37> 30 92 12 MEM_B_DQ<31> =MEM_B_DQ<32> 31 MF-LF 2 2
MAKE_BASE=TRUE MAKE_BASE=TRUE 402
92 12 MEM_A_DQ<30> =MEM_A_DQ<33> 30 92 12 MEM_B_DQ<30> =MEM_B_DQ<39> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE

em
92 12 MEM_A_DQ<29> =MEM_A_DQ<35> 30 92 12 MEM_B_DQ<29> =MEM_B_DQ<37> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
92 12 MEM_A_DQ<28> =MEM_A_DQ<34> 30 92 12 MEM_B_DQ<28> =MEM_B_DQ<38> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
92 12 MEM_A_DQ<27> =MEM_A_DQ<36> 30 92 12 MEM_B_DQ<27> =MEM_B_DQ<35> 31 =PP3V3_S5_MEMRESET
MAKE_BASE=TRUE MAKE_BASE=TRUE NOSTUFF 32 6
92 12 MEM_A_DQ<26> =MEM_A_DQ<32> 30 92 12 MEM_B_DQ<26> =MEM_B_DQ<34> 31
R3390
MAKE_BASE=TRUE MAKE_BASE=TRUE NOSTUFF
92 12 MEM_A_DQ<25> =MEM_A_DQ<38> 30 92 12 MEM_B_DQ<25> =MEM_B_DQ<36> 31
ALL_SYS_PWRGD_R
0 1
MEM_A_DQ<24>
MAKE_BASE=TRUE
=MEM_A_DQ<39> MEM_B_DQ<24>
MAKE_BASE=TRUE
=MEM_B_DQ<33>
100 64 5 1 2 C3390
92 12 30 92 12 31
MAKE_BASE=TRUE MAKE_BASE=TRUE 5% 0.1UF
=PP5V_S3_MEMRESET

ch
1/16W 20% 32 6
10V
CPU CHANNEL A DQS 4 -> DIMM A DQS 3 CPU CHANNEL B DQS 4 -> DIMM B DQS 3 MF-LF
402 CERM 2
MEM_A_DQS_N<4> =MEM_A_DQS_N<3> MEM_B_DQS_N<4> =MEM_B_DQS_N<3> 402 1 1
92 12
MAKE_BASE=TRUE NO_TEST=TRUE
30 92 12
MAKE_BASE=TRUE NO_TEST=TRUE
31
NOSTUFF R3387 R3384
92 12 MEM_A_DQS_P<4> =MEM_A_DQS_P<3> 30 92 12 MEM_B_DQS_P<4> =MEM_B_DQS_P<3> 31
R3391 NOSTUFF 20K 20K
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 5 NOSTUFF 5% 5%
PM_EN_DDRVTT_S0_REG 1
0 2 DDRSYS_EN 1 MC74VHC1G08 R3393 1/16W 1/16W
100 72 63 SOT23-5-HF MF-LF MF-LF
MEM_A_DQ<39> =MEM_A_DQ<28> MEM_B_DQ<39> =MEM_B_DQ<28> 0

kS
402
92 12
MAKE_BASE=TRUE
30 92 12
MAKE_BASE=TRUE
31
5% 4 SLP_S3_CTL_L 1 2 2 2 402
92 12 MEM_A_DQ<38> =MEM_A_DQ<29> 30 92 12 MEM_B_DQ<38> =MEM_B_DQ<24> 31 1/16W
2
U3390 PM_SLP_S3_5V 32 100
MAKE_BASE=TRUE MAKE_BASE=TRUE MF-LF 5% PM_SLP_S3_5V_L 32 100
92 12 MEM_A_DQ<37> =MEM_A_DQ<27> 30 92 12 MEM_B_DQ<37> =MEM_B_DQ<31> 31 402 1/16W
MAKE_BASE=TRUE MAKE_BASE=TRUE MF-LF 6
92 12 MEM_A_DQ<36> =MEM_A_DQ<31> 30 92 12 MEM_B_DQ<36> =MEM_B_DQ<30> 31
3 402 3
MAKE_BASE=TRUE MAKE_BASE=TRUE D
MEM_A_DQ<35> =MEM_A_DQ<25> MEM_B_DQ<35> =MEM_B_DQ<29> D
92 12

MEM_A_DQ<34>
MAKE_BASE=TRUE
=MEM_A_DQ<24>
30 92 12

MEM_B_DQ<34>
MAKE_BASE=TRUE
=MEM_B_DQ<25>
31
R3394 Q3370 Q3370
92 12 30 92 12 31 0 2N7002DW-X-G

oo
MAKE_BASE=TRUE MAKE_BASE=TRUE PM_SLP_S3_L 1 2 100 PM_SLP_S3_5V_R2 2 G S SOT-363
2N7002DW-X-G
92 12 MEM_A_DQ<33> =MEM_A_DQ<26> 30 92 12 MEM_B_DQ<33> =MEM_B_DQ<27> 31
100 63 47 46 36 32 26 19 5 5 G S SOT-363
MAKE_BASE=TRUE MAKE_BASE=TRUE 5%
92 12 MEM_A_DQ<32> =MEM_A_DQ<30> 30 92 12 MEM_B_DQ<32> =MEM_B_DQ<26> 31 1/16W 1
MAKE_BASE=TRUE MAKE_BASE=TRUE 4
B CPU CHANNEL A DQS 5 -> DIMM A DQS 2 CPU CHANNEL B DQS 5 -> DIMM B DQS 2
NOSTUFF
MF-LF
402 B
92 12 MEM_A_DQS_N<5> =MEM_A_DQS_N<2> 30 92 12 MEM_B_DQS_N<5> =MEM_B_DQS_N<2> 31
R3386
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
MEM_A_DQS_P<5> =MEM_A_DQS_P<2> MEM_B_DQS_P<5> =MEM_B_DQS_P<2> 0
92 12
MAKE_BASE=TRUE NO_TEST=TRUE
30 92 12
MAKE_BASE=TRUE
eb
NO_TEST=TRUE
31
1 2
5%
92 12 MEM_A_DQ<47> =MEM_A_DQ<17> 30 92 12 MEM_B_DQ<47> =MEM_B_DQ<18> 31 1/16W
MAKE_BASE=TRUE MAKE_BASE=TRUE MF-LF
92 12 MEM_A_DQ<46> =MEM_A_DQ<16> 30 92 12 MEM_B_DQ<46> =MEM_B_DQ<20> 31 402
MAKE_BASE=TRUE MAKE_BASE=TRUE
92 12 MEM_A_DQ<45> =MEM_A_DQ<22> 30 92 12 MEM_B_DQ<45> =MEM_B_DQ<23> 31

MEM_A_DQ<44>
MAKE_BASE=TRUE
=MEM_A_DQ<23> MEM_B_DQ<44>
MAKE_BASE=TRUE
=MEM_B_DQ<22> Q3375
ot
92 12 30 92 12 31

92 12 MEM_A_DQ<43>
MAKE_BASE=TRUE
=MEM_A_DQ<21> 30 92 12 MEM_B_DQ<43>
MAKE_BASE=TRUE
=MEM_B_DQ<19> 31
FDMC8296
POWER33 3
MAKE_BASE=TRUE MAKE_BASE=TRUE
92 12 MEM_A_DQ<42> =MEM_A_DQ<20> 30 92 12 MEM_B_DQ<42> =MEM_B_DQ<21> 31
2
MAKE_BASE=TRUE MAKE_BASE=TRUE
92 12 MEM_A_DQ<41> =MEM_A_DQ<18> 30 92 12 MEM_B_DQ<41> =MEM_B_DQ<17> 31
5 1
MAKE_BASE=TRUE MAKE_BASE=TRUE 6 =PP0V75_S0_MEM_VTT_S0FET PPVTT_S0_DDR_FET 6
N

92 12 MEM_A_DQ<40> =MEM_A_DQ<19> 30 92 12 MEM_B_DQ<40> =MEM_B_DQ<16> 31 D S

MAKE_BASE=TRUE MAKE_BASE=TRUE
CPU CHANNEL A DQS 6 -> DIMM A DQS 1 CPU CHANNEL B DQS 6 -> DIMM B DQS 1 R33401 1
100K G R3388
92 12 MEM_A_DQS_N<6> =MEM_A_DQS_N<1> 30 92 12 MEM_B_DQS_N<6> =MEM_B_DQS_N<1> 31 5% 10
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 1/16W
4 5%
92 12 MEM_A_DQS_P<6> =MEM_A_DQS_P<1> 30 92 12 MEM_B_DQS_P<6> =MEM_B_DQS_P<1> 31 MF-LF 1/16W
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 402
2 MF-LF

100 32 PM_SLP_S3_5V_L 2 402

92 12 MEM_A_DQ<55> =MEM_A_DQ<12> 30 92 12 MEM_B_DQ<55> =MEM_B_DQ<8> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE VTT_R
92 12 MEM_A_DQ<54> =MEM_A_DQ<13> 30 92 12 MEM_B_DQ<54> =MEM_B_DQ<14> 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
92 12 MEM_A_DQ<53> =MEM_A_DQ<10> 30 92 12 MEM_B_DQ<53> =MEM_B_DQ<10> 31

92 12 MEM_A_DQ<52>
MAKE_BASE=TRUE
=MEM_A_DQ<15> 30 92 12 MEM_B_DQ<52>
MAKE_BASE=TRUE
=MEM_B_DQ<11> 31
MEMORY CLOCK ALIASING 3

MAKE_BASE=TRUE MAKE_BASE=TRUE MEM_A_CLK_P<0> =MEM_A_CLK_P<0> D

92 12 MEM_A_DQ<51>
MAKE_BASE=TRUE
=MEM_A_DQ<8> 30 92 12 MEM_B_DQ<51>
MAKE_BASE=TRUE
=MEM_B_DQ<9> 31
92 12

MEM_A_CLK_N<0>
MAKE_BASE=TRUE NO_TEST=TRUE
=MEM_A_CLK_N<0>
30
Q3380
92 12 MEM_A_DQ<50> =MEM_A_DQ<9> 30 92 12 MEM_B_DQ<50> =MEM_B_DQ<15> 31
92 12
MAKE_BASE=TRUE NO_TEST=TRUE
30
2N7002
MAKE_BASE=TRUE MAKE_BASE=TRUE 92 12 MEM_A_CLK_P<1> =MEM_A_CLK_P<1> 30 100 32 PM_SLP_S3_5V 1 G S SOT23-HF1
92 12 MEM_A_DQ<49> =MEM_A_DQ<11> 30 92 12 MEM_B_DQ<49> =MEM_B_DQ<12> 31 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE 92 12 MEM_A_CLK_N<1> =MEM_A_CLK_N<1> 30
92 12 MEM_A_DQ<48> =MEM_A_DQ<14> 30 92 12 MEM_B_DQ<48> =MEM_B_DQ<13> 31 MAKE_BASE=TRUE NO_TEST=TRUE 2
MAKE_BASE=TRUE MAKE_BASE=TRUE 92 12 MEM_A_CLK_P<2> =MEM_A_CLK_P<2> 30
MAKE_BASE=TRUE NO_TEST=TRUE
CPU CHANNEL A DQS 7 -> DIMM A DQS 0 CPU CHANNEL B DQS 7 -> DIMM B DQS 0 MEM_A_CLK_N<2> =MEM_A_CLK_N<2>
A 92 12 MEM_A_DQS_N<7>
MAKE_BASE=TRUE
=MEM_A_DQS_N<0>
NO_TEST=TRUE
30 92 12 MEM_B_DQS_N<7>
MAKE_BASE=TRUE
=MEM_B_DQS_N<0>
NO_TEST=TRUE
31
92 12

92 12 MEM_A_CLK_P<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
=MEM_A_CLK_P<3>
NO_TEST=TRUE
30

30 SYNC_MASTER=K62_ROSITA SYNC_DATE=01/09/2011 A
92 12 MEM_A_DQS_P<7> =MEM_A_DQS_P<0> 30 92 12 MEM_B_DQS_P<7> =MEM_B_DQS_P<0> 31 92 12 MEM_A_CLK_N<3> =MEM_A_CLK_N<3> 30
PAGE TITLE
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
DDR3 SUPPORT AND BITSWAPS
92 12 MEM_A_DQ<63> =MEM_A_DQ<5> 30 92 12 MEM_B_DQ<63> =MEM_B_DQ<2> 31 92 12 MEM_B_CLK_P<0> =MEM_B_CLK_P<0> 31 DRAWING NUMBER SIZE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
92 12 MEM_A_DQ<62>
MAKE_BASE=TRUE
=MEM_A_DQ<4> 30 92 12 MEM_B_DQ<62>
MAKE_BASE=TRUE
=MEM_B_DQ<1> 31 92 12 MEM_B_CLK_N<0>
MAKE_BASE=TRUE
=MEM_B_CLK_N<0>
NO_TEST=TRUE
31
Apple Inc. 051-8442 D
92 12 MEM_A_DQ<61> =MEM_A_DQ<3> 30 92 12 MEM_B_DQ<61> =MEM_B_DQ<3> 31 92 12 MEM_B_CLK_P<1> =MEM_B_CLK_P<1> 31 REVISION
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE R
92 12 MEM_A_DQ<60>
MAKE_BASE=TRUE
=MEM_A_DQ<2> 30 92 12 MEM_B_DQ<60>
MAKE_BASE=TRUE
=MEM_B_DQ<7> 31 92 12 MEM_B_CLK_N<1>
MAKE_BASE=TRUE
=MEM_B_CLK_N<1>
NO_TEST=TRUE
31 10.1.0
92 12 MEM_A_DQ<59> =MEM_A_DQ<1> 30 92 12 MEM_B_DQ<59> =MEM_B_DQ<4> 31 92 12 MEM_B_CLK_P<2> =MEM_B_CLK_P<2> 31 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
92 12 MEM_A_DQ<58> =MEM_A_DQ<0> 30 92 12 MEM_B_DQ<58> =MEM_B_DQ<5> 31 92 12 MEM_B_CLK_N<2> =MEM_B_CLK_N<2> 31 THE INFORMATION CONTAINED HEREIN IS THE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
92 12 MEM_A_DQ<57> =MEM_A_DQ<7> 30 92 12 MEM_B_DQ<57> =MEM_B_DQ<6> 31 92 12 MEM_B_CLK_P<3> =MEM_B_CLK_P<3> 31 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
92 12 MEM_A_DQ<56>
MAKE_BASE=TRUE
=MEM_A_DQ<6> 30 92 12 MEM_B_DQ<56>
MAKE_BASE=TRUE
=MEM_B_DQ<0> 31 92 12 MEM_B_CLK_N<3>
MAKE_BASE=TRUE
=MEM_B_CLK_N<3>
NO_TEST=TRUE
31
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
33 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 32 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

NOSTUFF =PP3V3_S3_MINI_CONN 33

=PP3V3_S3_MINI_CONN 33
R3401
0
1 2 CRITICAL
AP WAKE# ISOLATION
D 1
R3470
5%
1/16W
MF-LF J3400 D
Q3470 10K 402 AS0B226-S40N-7F
5% F-RT-SM

G 1
SSM3K15FV 1/16W 54
MF-LF
SOD-VESM-HF 2 402

AP_WAKE_L

S
100 79 36 19 OUT PCIE_WAKE_L 1 2

2
RSVD_MINI_WLAN_ACTIVE 3 4 =PP1V5_S0_MINI 6
RSVD_MINI_BT_ACTIVE 5 6

33 OUT AP_MINI_CLKREQ_L 7 8 NC NOSTUFF NOSTUFF

9 10 NC C3400 1 C3401 1
93 18 IN PCIE_CLK100M_MINI_N 11 12 NC 0.1uF 10uF
20% 20%
PCIE_CLK100M_MINI_P 13 14 NC 10V 6.3V 2
93 18 IN CERM 2 X5R
15 16 NC 402 603
RESERVED NC 17 KEY 18
93 18 OUT PCIE_MINI_D2R_N 19 20
RESERVED NC NC

m
93 18 OUT PCIE_MINI_D2R_P 21 22 AP_MINI_RESET_L IN 33 100
23 24
NOSTUFF
PLACEMENT_NOTE=PLACE CLOSE TO U1800. 25 26
R3490 0
C3431 27 28 1 2 =SMB_MINI_SCL 49

co
0.1uF 29 30 SMB_MINI_SCL R3491 5%
0 NOSTUFF 1/16W
93 18 IN PCIE_MINI_R2D_C_N 1 2 93 PCIE_MINI_R2D_N 31 32 SMB_MINI_SDA 1 2 MF-LF =SMB_MINI_SDA 49
402
10%
93 PCIE_MINI_R2D_P 33 34 5%
1/16W
16V
X5R
35 36 TP_USB_MININ MF-LF
402
402 37 38 TP_USB_MINIP

s.
PLACEMENT_NOTE=PLACE CLOSE TO U1800. 39 40 NO AVAILALBLE USB ON THIS PLATFORM
C3430 41 42 NC TARGET CARDS DO NOT USE IT
0.1uF 43 44 NC
C PCIE_MINI_R2D_C_P 1 2
C

ic
93 18 IN
NC 45 46 NC
10% NC 47 48
16V
X5R NC 49 50
402

at
NC 51 52

em
516S0457

ch
=PP3V3_S3_MINI_CONN 33
=PP3V3_S3_MINI 6 33

=PP12V_S5_PWRCTL

kS
C3408 1 74 64 6

0.1UF CRITICAL 1 C3461

10%
16V 2 Q3403 0.1UF
1

1 X5R 10%
R3412 VDD
402 IRFH3702TRPBF 2 16V
X5R
100K PQFN 402
1%
1/16W Q3406 PP3V3_S3_MINI_CONN 98

oo
MF-LF
2 402
SLG4AP016V VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
TDFN

S
MIN_NECK_WIDTH=0.2MM

1
100 33 PM_PGOOD_MINI 2 SENSE
+ =PP3V3_S3_MINI
B 0.7V - 33 6
=PP3V3_S3_MINI_CONN 33
B

G
DLY RESET HAS 100MS DELAY ONCE ENABLE IS HIGH
eb

P3V3_S0_MINI_EN_G 4
100 33 OUT AP_MINI_RESET_L 4 RESET*
MR* 3 MINI_RESET_L IN 27 100 =PP3V3_S3_MINI
33 6

AP_PWR_EN_FET

1
EN 6 IN 33

OUT 8 MINI_CLKREQ_L VCC

OUT 15 100
AP_MINI_CLKREQ_L 7 IN 1
R3410
ot
(OD)
33 IN
THRM 10K U3404
PAD GND 5% SLG5AP001
1/16W TDFN
9

MF-LF 5D ON 2
2 402
CRITICAL
N

7G S6
100 33 PM_PGOOD_MINI 8 PG NC 3

THRM
PAD GND

4
33 AP_PWR_EN_FET
=PP3V3_S3_MINI 6 33

AP PWR EN ISOLATION
1
R3471
AP 10K
Q3471 5%
G 1

SSM3K15FV 1/16W
A SOD-VESM-HF
MF-LF
2 402 SYNC_MASTER=K62_AARON SYNC_DATE=07/16/2009 A
PAGE TITLE

PCI-E Wireless Connector

100 25 20 AP_PWR_EN
3

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

=PP3V3_S3_USB_HUB
6 =PP3V3_S5_USB_HUB 6 34 35

D D
USB HUB-1 1
R3740
20K
5%
1
R3741
10K
5%

L3558 1/16W
MF-LF
1/16W
MF-LF
FERR-120-OHM-1.5A 2 402
2 402
NOSTUFF
=PP3V3_S3_USB_HUB 1 2 98 USB_HUB1_VDDPLL3V3
35 34 6
0402
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
C3741 1
100PF
5%
1 C3536 1 C3537 1 C3538 1 C3539 50V
CERM 2 USB_PON_RESET
0.01UF 100PF 10UF 0.1UF 402 USB_PON_RESET_L
10% 5% 20% 10%
16V 50V 6.3V 16V
2 CERM 2 CERM 2 X5R 2 X7R-CERM Q3740 R3755
1 C3518 402 402 603 402 2N7002DW-X-G
6 3
0
10UF SOT-363 D D 1 2 USB_HUB_RESET_L 34
20% 35
2 6.3V Q3740 5%
X5R 2N7002DW-X-G 1/16W

m
603 PM_PGOOD_P3V3_S3_FET 2 G S 5 G S SOT-363 MF-LF
100 74
402
L3559 NOSTUFF 1 4
FERR-120-OHM-1.5A 1 C3740
1 2
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM 98 USB_HUB1_VDDA3V3 =PP3V3_S3_USB_HUB 6 34 35 0.47UF

co
10%
0402 6.3V
2 CERM-X5R
1 C3523 1 C3525 1 C3526 1 C3529 402
1 C3542 1 C3543 1 C3544 1 C3545 1 C3546 1 C3547 0.1UF
10%
0.1UF
10%
0.01UF
10% 10%
0.01UF
0.01UF 100PF 10UF 0.1UF 0.1UF 0.1UF 16V 16V 16V 16V
10% 5% 20% 10% 10% 10% 2 X7R-CERM 2 X7R-CERM 2 CERM 2 CERM
16V 50V 6.3V 16V 16V 16V 402 402 402 402
2 CERM 2 CERM 2 X5R 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM
R3745

s.
402 402 603 402 402 402
0
100 25 20 USB_HUB_SOFT_RESET_L 1 2
5%
1/16W
C MF-LF
C

ic
402

35 34 6
=PP3V3_S3_USB_HUB

10
15
23
29
36

at
5
NOSTUFF NOSTUFF
CRITICAL R35971 R35991 VDD33
Y3500 10K 100K
5% 5%
24.000M-60PPM-16PF 1/16W 1/16W

em
1 2 MF-LF MF-LF

USB_HUB1_TEST
402 2 402 2 OMIT
5X3.2X1.4-SM
1 C3519 R3591
1 C3520 U3500
5%
18PF 1M 5%
18PF USB2514-AEZG
1 2
50V 50V
2 CERM
402
5%
2 CERM
402
11 TEST QFN USBDM_DN1/PRT_DIS_M1 1 USB_SDCARD_N 44 95
1/16W
MF-LF USBDP_DN1/PRT_DIS_P1 2 USB_SDCARD_P
USB_HUB_RESET_L 44 95

ch
402 35 34 IN
26 RESET*
USBDM_DN2/PRT_DIS_M2 3 USB_IR_N 44 95
94 USB_HUB1_XTAL1 33 XTALIN/CLKIN
USBDP_DN2/PRT_DIS_P2 4 USB_IR_P 44 95
94 USB_HUB1_XTAL2 32 XTALOUT
USBDM_DN3/PRT_DIS_M3 6 USB_EXTA_N
USB_HUB1_LOCAL_PWR 28 43 95
SUSP_IND/LOCAL_PWR/NON_REM0 7
USBDP_DN3/PRT_DIS_P3 USB_EXTA_P

kS
43 95
22 SDA/SMBDATA/NON_REM1
USB_HUB1_SMBDATA 8 USB_EXTC_N
USBDM_DN4/PRT_DIS_M4 43 95
USB_HUB1_SMBCLK 24 SCL/SMBCLK/CFG_SEL0 USBDP_DN4/PRT_DIS_P4 9 USB_EXTC_P 43 95
=PP3V3_S3_USB_HUB
35 34 6
=PP3V3_S3_USB_HUB USB_HUB1_CFG_SEL1 25 12
6 34 35
HS_IND/CFG_SEL1 PRTPWR1/BC_EN1* TP_USB_HUB1_PRTPWR1
PRTPWR2/BC_EN2* 16 TP_USB_HUB1_PRTPWR2
14 CRFILT

oo
18 1
1 1 NOSTUFF
1
R3598 PRTPWR3/BC_EN3* TP_USB_HUB1_PRTPWR3 1
R3580 R3581 1
R3550
R3504 R35921 R3594 34 PLLFILT 20 10K
10K 10K PRTPWR4/BC_EN4* TP_USB_HUB1_PRTPWR4 10K 10K
8

10K 10K 5%
NOSTUFF 5% 5% 5%
B 5%
1/16W
MF-LF
VCC
5%
1/16W
5%
1/16W
1/16W
MF-LF
2 402
OCS1* 13 TP_USB_HUB1_OCS1_L
1/16W
MF-LF
1/16W
MF-LF
2 402
1/16W
MF-LF B
2 402 U3514 MF-LF
402 2
MF-LF
2 402 OCS2* 17 TP_USB_HUB1_OCS2_L 2 402
2 402
M24C02 19 USB_EXTA_OC_L
7 WC*
eb OSC3* 43
WP_HUB1 MLP8 SDA 5 OSC4* 21 USB_EXTC_OC_L 43
1 C3534
0.1UF 6 SCL CRITICAL 1 RBIAS 35 USB_HUB1_RBIAS
10%
R3501 94

16V
2 X5R
10K 27 USB_HUB1_VBUS_DET
5% VBUS_DET
402 1 E0 NOSTUFF 1/16W CKPLUS_WAIVE=NDIFPR_BADTERM MIN_NECK_WIDTH=0.25MM
ot
1 MF-LF 30 MIN_LINE_WIDTH=0.5MM
2 E1 R3566 1
R3565 1
R3567 402 2 USBDM_UP USB_HUB1_UP_N IN 20 95

3 E2 10K 10K 10K USBDP_UP 31 USB_HUB1_UP_P 20 95

5% IN
1/16W 5% 5%
VSS THRM_PAD 1/16W 1/16W THRM_PAD
MF-LF MF-LF MF-LF
2 402
4

2 402 2 402
N

37
R3500
1
12K 2
1%
1/16W
BOM TABLE TABLE_5_HEAD

MF
402 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM

SEL1 SEL0 DESCRIPTION 338S0721 2 SMSC USX2061-AEZG U3500,U3600 CRITICAL HUB_USX2061

TABLE_5_ITEM

DEFAULT K23F ==> 0 0 Internal Default with Self powered Operation 338S0824 2 SMSC USB2514B U3500,U3600 CRITICAL HUB_USB2514B

0 1 SMBUS Slave Config 98 USB_HUB1_VDD1V8

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
1 0 Internal Default with Bus powered Operation
98 USB_HUB1_VDD1V8PLL
1 1 EEPROM Supported MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM 1 C3524 1 C3527 1 C3528 1 C3530
0.1UF 1UF 0.1UF 1UF
A 10%
16V
2 X7R-CERM
10%
16V
2 X5R
10%
16V
2 X7R-CERM
10%
16V
2 X5R SYNC_MASTER=K62_SIJI SYNC_DATE=11/14/2010 A
402 402 402 402 PAGE TITLE
NON_REM1 NON_REM0 DESCRIPTION
0 0 All ports are Non removable USB HUB 1
0 1 Port1 is non removable DRAWING NUMBER SIZE

DEFAULT K23F ==> 1 0 Port 1 and 2 are non removable Apple Inc. 051-8442 D
1 1 Port1,2 and 3 are non Removable REVISION
R
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
35 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 34 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D
USB HUB-2 D
L3658
FERR-120-OHM-1.5A
35 34 6 =PP3V3_S3_USB_HUB 1 2 98 USB_HUB2_VDDPLL3V3
0402 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
1 C3636 1 C3637 1 C3638 1 C3639
0.01UF 100PF 10UF 0.1UF
10% 5% 20% 10%
2 16V
CERM 2 50V
CERM
6.3V
2 X5R 16V
2 X7R-CERM
402 402 603 402
1 C3618
10UF
20%
6.3V
2 X5R
603
L3629
FERR-120-OHM-1.5A
1 2
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM 98 USB_HUB2_VDDA3V3 =PP3V3_S3_USB_HUB 6 34 35

m
0402
1 C3623 1 C3625 1 C3626 1 C3629
1 C3642 1 C3643 1 C3644 1 C3645 1 C3646 1 C3647 0.1UF
10%
0.1UF
10%
0.01UF
10% 10%
0.01UF
0.01UF 100PF 10UF 0.1UF 0.1UF 0.1UF
2 16V 16V 2 16V 16V

co
10% 5% 20% 10% 10% 10% X7R-CERM 2 X7R-CERM CERM 2 CERM
16V 50V 6.3V 16V 16V 16V 402 402 402 402
2 CERM 2 CERM 2 X5R 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM
402 402 603 402 402 402

s.
35 34 6
=PP3V3_S3_USB_HUB

C C

10
15
23
29
36
ic 5
1 NOSTUFF
CRITICAL NOSTUFF
R36971 R36991 VDD33 =PP3V3_S3_USB_HUB
Y3600 10K 100K 35 34 6
5% 5%
24.000M-60PPM-16PF

at
1/16W 1/16W
1 2 MF-LF MF-LF
402 2 402 2 OMIT
5X3.2X1.4-SM R36601 R36611
1 C3619 R3691 1 C3620 U3600 10K 10K
18PF 1M 18PF USB2514-AEZG 5% 5%

em
1/16W 1/16W
5% 1 2 5% MF-LF MF-LF
50V 50V
2 CERM
402
5%
2 CERM
402
USB_HUB2_TEST 11 TEST QFN USBDM_DN1/PRT_DIS_M1 1 USB_BT_N 44 95
402 2 402 2
1/16W
MF-LF USBDP_DN1/PRT_DIS_P1 2 USB_BT_P 44 95
402 34 IN USB_HUB_RESET_L 26 RESET*
USBDM_DN2/PRT_DIS_M2 3 USB_HUB2UNUSED_N 95
94 USB_HUB2_XTAL1 33 XTALIN/CLKIN
USBDP_DN2/PRT_DIS_P2 4 USB_HUB2UNUSED_P 95
94 USB_HUB2_XTAL2 32 XTALOUT
6

ch
28 USBDM_DN3/PRT_DIS_M3 USB_EXTB_N 43 95
USB_HUB2_LOCAL_PWR SUSP_IND/LOCAL_PWR/NON_REM0
USBDP_DN3/PRT_DIS_P3 7 USB_EXTB_P 43 95
USB_HUB2_SMBDATA 22 SDA/SMBDATA/NON_REM1
USBDM_DN4/PRT_DIS_M4 8 USB_EXTD_N 43 95
USB_HUB2_SMBCLK 24 SCL/SMBCLK/CFG_SEL0 USBDP_DN4/PRT_DIS_P4 9 USB_EXTD_P 43 95

=PP3V3_S3_USB_HUB

kS
35 34 6 USB_HUB2_CFG_SEL1 25 HS_IND/CFG_SEL1 PRTPWR1/BC_EN1* 12 TP_USB_HUB2_PRTPWR1
PRTPWR2/BC_EN2* 16 TP_USB_HUB2_PRTPWR2 =PP3V3_S3_USB_HUB 6 34 35
14 CRFILT
NOSTUFF 1 PRTPWR3/BC_EN3* 18 TP_USB_HUB2_PRTPWR3 1
1
R3604 R3692 1 1
R3694 R3698 34 PLLFILT PRTPWR4/BC_EN4* 20 TP_USB_HUB2_PRTPWR4 R3680 1 R3681 R36821
10K 10K 10K 10K 10K 10K 10K
8

5%
NOSTUFF 5% 5%
5% 5%
5%
5%
1/16W VCC 1/16W 1/16W
1/16W OCS1* 13 TP_USB_HUB2_OCS1 1/16W
1/16W
1/16W
MF-LF MF-LF

oo
MF-LF MF-LF MF-LF MF-LF MF-LF
2 402 17
2 402 U3614 402 2
2 402 OCS2*
19
TP_USB_HUB2_OCS2 402 2 402 2 402 2
USB_EXTB_OC_L
7 WC*
M24C02 OSC3* 43

SDA 5
B 1
WP_HUB2
C3634
MLP8 OSC4* 21

35
USB_EXTD_OC_L 43
B
0.1UF 1 RBIAS USB_HUB2_RBIAS 94

10%
6 SCL CRITICAL R3601
16V
2 X5R
eb 10K VBUS_DET 27 USB_HUB2_VBUS_DET
5%
402 1 E0 1/16W CKPLUS_WAIVE=NDIFPR_BADTERM
NOSTUFF MF-LF USBDM_UP 30 USB_HUB2_UP_N 20 95
2 E1 402 2 IN
1
3 E2 R3665 1R3666 1R3667 USBDP_UP 31 USB_HUB2_UP_P IN 20 95
10K 10K 10K THRM_PAD
VSS THRM_PAD 5% 5% 5%
1/16W 1/16W 1/16W
ot
4

MF-LF MF-LF MF-LF

37
2 402 2 402 2 402

R3600
12K
N

1 2
1%
1/16W
MF
402

98 USB_HUB2_VDD1V8
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM

98 USB_HUB2_VDD1V8PLL
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
1 C3624 1 C3627 1 C3628 1 C3630
0.1UF 1UF 0.1UF 1UF
10% 10% 10% 10%
16V 16V 16V 16V
2 X7R-CERM 2 X5R 2 X7R-CERM 2 X5R
402 402 402 402

A SYNC_MASTER=K62_SIJI SYNC_DATE=11/14/2010 A
PAGE TITLE

USB HUB 2
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

CAESAR IV 1.2V INT.VR CMPTS CAESAR IV POWER ENABLE CIRCUIT CAESAR IV ACTIVITY LED
3V3_ENET_PHY_FET = S0 || (S3 POWER && ENET_PWR_EN)
PLACEMENT_NOTE=PLACE L3800 CLOSE TO U3900 =PP3V3_S3_ENET_PHY_FET
80 37 36
L3800
4.7UH-0.8A
=PP3V3_S3_ENET_PHY_FET 36 37 80

D
1
PCAA031B-SM
2 ENET_SR_LX
MIN_LINE_WIDTH=1.0MM
37 98 NOSTUFF
R3856 DEVELOPMENT
1
D
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V =PP3V3_S3_ENET_PHY 1
0
2 PP3V3_S3_ENET_PHY_FET R3815
6
MAKE_BASE=TRUE
98 330
SWITCH_NODE=TRUE 5% MIN_LINE_WIDTH=1.0 MM 5%
DIDT=TRUE NOSTUFF 1/8W MIN_NECK_WIDTH=0.2 MM 1/16W
1 MF-LF VOLTAGE=3.3V MF-LF
R3853 Q3850 805 NET_SPACING_TYPE=SWITCHNODE 2 402
10K FDC606P_G ENET_ACT
5%
ENET_SR_VFB SOT-6

6
37 98 1/16W A
MIN_LINE_WIDTH=1.0MM MF-LF DEVELOPMENT
MIN_NECK_WIDTH=0.2MM

2 5
VOLTAGE=1.2V 2 402 LED3800

D
4
GREEN-3.6MCD
2.0X1.25MM-SM

1
K
=PP1V2_S3_ENET_PHY 37
1 SILKSCREEN:ENET ACT
R3855

G
10K 1
C3853
5%

3
1/16W 0.1UF
PP1V2_S3_ENET_INTREG MF-LF 10%
MAKE_BASE=TRUE
98
2 402 2
16V
X7R-CERM C3852
MIN_LINE_WIDTH=1.0MM
MIN_NECK_WIDTH=0.2MM R3852 402 0.1UF 37 IN ENET_TRAFFICLED_L ENET_LED_ACT_L
C3825

m
MAKE_BASE=TRUE
1 1 C3827 1 C3828 1 C3829 1 C3830 1 C3831 1 C3826 VOLTAGE=1.2V 1
100K
2 ENET_PWR_ENABLE_L 1 2
10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10% 10% 10% 10% 5%
6.3V 16V 16V 16V 16V 16V 16V 1/16W 10%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R MF-LF X5R
603-2 402 402 402 402 402 402 402 16V
402

co
ENET_PWR_EN_L

PLACEMENT_NOTE=PLACE CLOSE TO L3800

PLACEMENT_NOTE=PLACE CLOSE TO L3800
3
D

s.
R3802 Q3852
100
47 46 0 5
2N7002DW-X-G
CAESAR IV WAKE# ISOLATION 19 5
32 26
63
PM_SLP_S3_L 1
5%
2 PM_SLP_S3_R3802_L G S SOT-363
6

C 1/16W 4
C

ic
MF-LF D
402
R3801 Q3852
=PP3V3_S3_ENET_PHY_FET 36 0 2N7002DW-X-G
37 80
100 25 20 IN ENET_PWR_EN 1 2 ENET_PWR_EN_R 2 G S SOT-363
FROM PCH GPIO ->
5%

at
1/16W 1
1
R3870 MF-LF
402
Q3870 10K
5%
G 1

SSM3K15FV 1/16W
MF-LF
CAESAR IV 25MHZ XTAL

em
SOD-VESM-HF 2 402

NOSTUFF
D

100 79 33 19 OUT PCIE_WAKE_L ENET_WAKE_L =ENET_WAKE_L IN 37

MAKE_BASE=TRUE NOSTUFF C3850
3

R3850 27pF
200 1 2
95 37 IN ENET_CLK25M_XTALO 1 2 95 ENET_CLK25M_XTALO_R
NOSTUFF 1% NOSTUFF 5%
CAESAR IV SW RESET GATING 1/16W

ch
R38511 MF-LF CRITICAL 50V
CERM

3
402 402
10M

2 4
5% Y3850 NOSTUFF
=PP3V3_S0_ENET_PHY NOSTUFF 1/16W 25.0000M
37 6 MF-LF SM-3.2X2.5MM C3851

1
R3854 402 2 197S0177 27pF
0 1 2
ENET_CLK25M_XTALI ENET_CLK25M_XTALI_R

kS
95 37 OUT 1 2
5 MC74VHC1G08 5%
100 27 IN ENET_RESET_L 1 SOT23-5-HF 1/16W 5%
MF-LF 50V
4 ENET_RESET_LOGIC_L CERM
U3880 OUT 36 94 402
402
94 21 15 IN ENET_SW_RESET_L 2
PLACEMENT_NOTE=PLACE CLOSE TO U3900
3 R3857

oo
0
99 80 ENET_CLK25M_XTALI_OSC 1 2
C3880 1 IN
5%
0.1UF
B 20%
10V
CERM 2
1/16W
MF-LF
402
B
402
eb
CAESAR IV RESET CONNECTION CAESAR IV STRAPS (NONE)
ot

R3829
N

0 ENET_RESET_LOGIC_R_L
94 36 IN ENET_RESET_LOGIC_L 1 2 OUT 37

5%
1/16W
MF-LF
402

CAESAR IV CLKREQ ISOLATION

A =PP3V3_S3_ENET_PHY_FET 36 37 80
SYNC_MASTER=K62_MARK SYNC_DATE=01/09/2011 A
PAGE TITLE

CAESAR IV SUPPORT
1
R3872 DRAWING NUMBER SIZE

Q3872 10K
Apple Inc. 051-8442 D
5%
G 1

SSM3K15FV 1/16W REVISION

MF-LF R
SOD-VESM-HF 2 402
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
ENET_CLKREQ_FET_L
D

94 18 15 OUT ENET_CLKREQ_L IN 37 94 THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
3

THE POSESSOR AGREES TO THE FOLLOWING: PAGE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
38 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 36 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
=PP1V2_S3_ENET_PHY 36
281mA (1000base-T max power, Caesar IV) R3901
0 396mA (1000base-T, Caesar II)
80 37 36 =PP3V3_S3_ENET_PHY_FET 1 2 98 ENET_3V3_S3_SR_IN
SWITCH_NODE=TRUE
5%
1/16W
DIDT=TRUE
NET_SPACING_TYPE=SWITCHNODE
1 C3980 1 C3981
MF-LF
402
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
0.1UF 0.1UF
VOLTAGE=3.3V 10% 10%
16V 16V ENET_SR_LX
CRITICAL 2 X5R 2 X5R 36 98
1 C3979 402 402 VDD for Card Reader I/O Internal 1.2V Switching Regulator pins.
4.7UF L3900 =PP3V3R1V8_ENET_LR_OUT CRITICAL
20% FERR-600-OHM-0.5A R3900
37 ENET_SR_VFB 36 98
6.3V L3920
2 CERM 0
1 2 98 PP3V3_S3_ENET_PHY_XTALVDDH ENET_XTALVDDH FERR-600-OHM-0.5A
D
603
SM
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V C3900 1
1

5%
1/16W
2 98
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
98 PP1V2_S3_ENET_PHY_AVDDL 1 2
D
MF-LF MIN_LINE_WIDTH=0.4 mm
0.1UF MIN_NECK_WIDTH=0.2 mm SM
402
10% VOLTAGE=1.2V
16V
2 1 1
X7R-CERM
402
C3921 C3920
CRITICAL 0.1UF 4.7UF
10% 10%
L3905 16V
2 2
6.3V
CRITICAL
FERR-600-OHM-0.5A X7R-CERM X5R-CERM
402 603
L3925
1 2 98 PP3V3_S3_ENET_PHY_BIASVDDH FERR-600-OHM-0.5A
MIN_LINE_WIDTH=0.4 mm
SM MIN_NECK_WIDTH=0.2 mm 1 2
VOLTAGE=3.3V 1 C3905 98 PP1V2_S3_ENET_PHY_PCIEPLL
MIN_LINE_WIDTH=0.4 mm
0.1UF MIN_NECK_WIDTH=0.2 mm SM
10% VOLTAGE=1.2V
16V
2 X7R-CERM
402
C3926 1 1
C3925
CRITICAL 0.1UF 4.7UF
10% 10%
L3910 16V
2 2
6.3V
CRITICAL
FERR-600-OHM-0.5A X7R-CERM X5R-CERM
402 603
L3930
1 2 98 PP3V3_S3_ENET_PHY_AVDDH FERR-600-OHM-0.5A

m
MIN_LINE_WIDTH=0.4 mm
SM MIN_NECK_WIDTH=0.2 mm 1 2
1
C3910 1
C3911 98 PP1V2_S3_ENET_PHY_GPHYPLL
VOLTAGE=3.3V R3910 1 MIN_LINE_WIDTH=0.4 mm
SM
4.7K 0.1UF 0.1UF MIN_NECK_WIDTH=0.2 mm
10% 10% VOLTAGE=1.2V
5% 16V 16V
1/16W 2 X7R-CERM 2 X7R-CERM C3931 1 1 C3930

co
MF-LF 402 402
402
2
0.1UF 4.7UF
10% 10%
16V 6.3V
X7R-CERM 2 2 X5R-CERM
402 603

s.
R3940 1
1
R3941 1
C3917 1
C3918 C3915 1 1
C3916
4.7K 4.7K 0.1UF 0.1UF 4.7UF 0.1UF

42
48

BIASVDDH 37

XTALVDDH 17

20
56
62

SR_VDD 14

SR_VDDP 15

SR_LX 16

SR_VFB 13
39
45
51

29
32

GPHY_PLLVDDL 36
35
61
1 1
10% 10% 10% 10% C3936 C3935

7
5% 5%
16V 16V 6.3V 16V
36 6 =PP3V3_S0_ENET_PHY 1/16W 1/16W 2 2 2 2 0.1UF 10UF
C MF-LF MF-LF
X7R-CERM
402
X7R-CERM
402
X5R-CERM
603
X7R-CERM
402 10% 10%
C

ic
PCIE_PLLVDDL
402
2 2
402 AVDDH VDDO AVDDL VDDC 16V 6.3V
X7R-CERM 2 2 X5R LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
402 805
1
the card reader on-chip I/O.
R3942 Connect only to U3900 pin 20.
C3950 1K

at
0.1uF 5% Current =PP3V3R1V8_ENET_LR_OUT 37
1 2
1/16W
Limiting OMIT
95 18 OUT PCIE_ENET_D2R_N MF-LF
402 Resistor
10%
2
U3900
16V C3951 ENET_VMAIN_PRSNT 58 VMAIN_PRSNT (IPD-ENET) BCM57765 TRD0_P 40 ENETCONN_MDI_P<0> BI 38 95 PP3V3R1V8_ENET_LR_OUT_REG
X5R 98
0.1uF

em
402 QFN-8X8 TRD0_N 41 ENETCONN_MDI_N<0> 38 95 DEVELOPMENT DEVELOPMENT MIN_LINE_WIDTH=0.3 mm
PCIE_ENET_D2R_P 1 2 BI MIN_NECK_WIDTH=0.2 mm
95 18 OUT 95 PCIE_ENET_D2R_C_N 27 PCIE_TXD_N TRD1_P 44 ENETCONN_MDI_P<1> 38 95
VOLTAGE=1.8V
BI
10% 95 PCIE_ENET_D2R_C_P 28 PCIE_TXD_P TRD1_N 43 ENETCONN_MDI_N<1> 38 95 NOSTUFF
BI
16V
X5R 46 ENETCONN_MDI_P<2>
1 C3970 1 C3971 1
C3972 1 NOSTUFF
C3955 402 95 PCIE_ENET_R2D_P 33 PCIE_RXD_P TRD2_P BI 38 95
4.7UF 0.1UF 0.1UF R3959 1 C3959
0.1uF TRD2_N 47 ENETCONN_MDI_N<2> 38 95
10% 10% 10% 150
95 PCIE_ENET_R2D_N 34 PCIE_RXD_N BI 6.3V 16V 16V 5% 10PF
2 2 2
95 18 IN PCIE_ENET_R2D_C_P 1 2
TRD3_P 50 ENETCONN_MDI_P<3> BI 38 95
X5R-CERM X7R-CERM X7R-CERM 1/16W 5%
603 402 402 MF-LF 50V
31 PCIE_REFCLK_P 49 2 CERM

ch
10%
93 18 IN PCIE_CLK100M_ENET_P TRD3_N ENETCONN_MDI_N<3> BI 38 95 DEVELOPMENT 2 402
402
16V C3956 93 18 IN PCIE_CLK100M_ENET_N 30 PCIE_REFCLK_N
X5R
0.1uF
402
GPIO_0 5

(IPD)
95 18 IN PCIE_ENET_R2D_C_N 1 2
36 IN ENET_RESET_LOGIC_R_L 11 PERST* (IPD)
NC
GPIO_1/CR_BUS_PWR 8 MUST DO: REMOVE C/R3959 AFTER PROTO 2
10% ENET_CLKREQ_FET_L 12 CLKREQ* RE*/GPIO_2 9 ENET_MEDIA_SENSE
R3943 16V
94 36 OUT (OD) OUT 15 18 95

kS
0 X5R
=ENET_WAKE_L 1 2 402 ENET_WAKE_R_L 3 WAKE* NOTE: "IPx" == Programmable pull-up/down DEVELOPMENT
36 IN (OD)
SD_DETECT/WE*
(IPx-ENET)
o1 95 ENET_SD_DETECT_L R3960 0 1 2 SDCONN_DETECT_L IN 45
(See note) 5%
SD_DETECT can only be used active low due to errata.
5% 1/16W MF-LF 402
1/16W
4 LOW_PWR R3961 DEVELOPMENT
MF-LF 100 21 15 IN ENET_LOW_PWR (IPD) (IPU-ENET) CR_CMD/CLE 26 95 ENET_SD_CMD 33 1 2 SDCONN_CMD IN 45 95
WAKE# 402 PLACEMENT_NOTE=PLACE NEAR U3900 5% 1/16W MF-LF 402
DEVELOPMENT
6 SMB_CLK CR_CLK/RY_BY* 21 95 ENET_SD_CLK R3979 33 1 2 SDCONN_CLK OUT 45 95
Must isolate from PCIe WAKE# if PHY ENET_SMB_CLK PLACEMENT_NOTE=PLACE NEAR U3900 5% 1/16W MF-LF 402

oo
ENET_SMB_DATA 10 SMD_DATA 25 ENET_CR_DATA<0> R3971 33 DEVELOPMENT
1 2 SDCONN_DATA<0>
is powered-down in S3/S5. Standard (IPD-ENETM) CR_DATA0 95
BI 45 95
DEVELOPMENT5% 1/16W MF-LF 402
N-channel FET isolation suggested. CR_DATA1 24 95 ENET_CR_DATA<1> R3972 33 1 2 SDCONN_DATA<1> BI 45 95
37 ENET_SCLK 66 SCLK DEVELOPMENT5% 1/16W MF-LF 402
B If PHY is always powered then alias
37
BI
ENET_MISO 64 SI/LINKLED*
CR_DATA2 23 95 ENET_CR_DATA<2> R3973
R3974
33 1 2
DEVELOPMENT5% 1/16W MF-LF 402
SDCONN_DATA<2> BI 45 95
B

(IPU)
IN 22 ENET_CR_DATA<3> 33 1 2 SDCONN_DATA<3>
=ENET_WAKE_L to PCIE_WAKE_L. 65 CR_DATA3 95
BI 45 95
ENET_MOSI

(IPU-ENET)
37 BI SO DEVELOPMENT5% 1/16W MF-LF 402
CR_DATA4 52 95 ENET_CR_DATA<4> R3975 33 1 2 SDCONN_DATA<4> BI 45 95
ENET_CS_L 63
37 BI
eb CS*
CR_DATA5 53 95 ENET_CR_DATA<5> R3976 33 DEVELOPMENT
1 2
5% 1/16W MF-LF 402
SDCONN_DATA<5> BI 45 95
DEVELOPMENT5% 1/16W MF-LF 402
TP_ENET_SPD100LED_L 2 SPD100LED*/SERIAL_DO (OD) CR_DATA6 54 95 ENET_CR_DATA<6> R3977 33 1 2 SDCONN_DATA<6> BI 45 95
DEVELOPMENT5% 1/16W MF-LF 402
36 OUT ENET_TRAFFICLED_L 67 TRAFFICLED*/SERIAL_DI (OD) CR_DATA7 55 95 ENET_CR_DATA<7> R3978 33 1 2 SDCONN_DATA<7> BI 45 95
5% 1/16W MF-LF 402
(IPU-ENET)
CE*/MS_INS* 59 NC_ENET_CE_L_MS_INS_L NO_TEST=TRUE
95 36 ENET_CLK25M_XTALI 18 XTALI No MS (Memory Stick) Insert feature needed.
IN (IPU-ENET) 60 ENET_CR_PWREN
ot
19 XTALO CR_LED/ALE OUT 45 Control signal to light LED or control SD bus power.
95 36 OUT ENET_CLK25M_XTALO (IPU-ENET)
CR_WP*/XD_WP* 57 SDCONN_WP IN 45
95 ENET_RDAC 38 RDAC (NO IPU OR IPD-ENET) XD_DETECT 68 ENET_SR_DISABLE R3980 1K 1 2 NOSTUFF =PP3V3_S3_ENET_PHY_FET 36 37 80
THRM_PAD 5% 1/16W MF-LF 402
(See note)
PHY Non-Volatile Memory

69
R3981
N

1
ENET 1.2V SR IS ENABLED IF FLOATING. 1K 1 2
R3965 5% 1/16W MF-LF 402
ENET supports both active-levels for WP.
ROM contains MAC address, PCIe config 1.24K PLACEMENT_NOTE=PLACE R3971 NEAR U3900
1% PLACEMENT_NOTE=PLACE R3972 NEAR U3900
1/16W
ENET_CR Signals PLACEMENT_NOTE=PLACE R3973 NEAR U3900
info as well as code for Bonjour proxy. MF-LF PLACEMENT_NOTE=PLACE R3974 NEAR U3900
Avoids need for EFI to program at startup. 2 402 PLACEMENT_NOTE=PLACE R3975 NEAR U3900
BCM requests SD CR[0:7], CMD, CLK termination. PLACEMENT_NOTE=PLACE R3976 NEAR U3900
(Required ROM size 1 Mbit) PLACEMENT_NOTE=PLACE R3977 NEAR U3900
PLACEMENT_NOTE=PLACE R3978 NEAR U3900
ENET_SR_DISABLE PLACEMENT_NOTE=PLACE R3961 NEAR U3900
80 37 36 =PP3V3_S3_ENET_PHY_FET PLACEMENT_NOTE=PLACE R3979 NEAR U3900

If ENET switching regulator is

used, this pin can float (alias to
R3993 1 R3992 1 TP_). If not used, must be pulled
6

4.7K 4.7K 1
C3990
5% 5% VCC 0.1UF to 3.3V ENET via 1K resistor (not
1/16W 1/16W 10%
MF-LF MF-LF 16V provided on this page).
402
2 402
2 U3990 2 X7R-CERM

R3904 AT45DB021D 402

SOIC-8S1
0
37 ENET_SCLK 1 2 ENET_SCLK_R 2 SCK SI 1 ENET_MOSI 37
IN IN
A 37 ENET_CS_L
5% 402
1/16W
MF-LF 4 CS*
OMIT_TABLE
SYNC_MASTER=K62_MARK SYNC_DATE=01/09/2011 A
IN PAGE TITLE
SO 8 ENET_MISO OUT
ENET_SWP_L 5 WP*
NOSTUFF
37
ETHERNET PHY (CAESAR IV)
DRAWING NUMBER SIZE
ENET_SRESET_L 3 RESET* 1
R3990
1
R3997
GND 4.7K 4.7K Apple Inc. 051-8442 D
5% 5% REVISION
7

NOTE: Pull-down on SO plus internal pull-ups on 1/16W 1/16W R

MF-LF MF-LF 10.1.0
other 3 SPI pins configures ENET for the 2 402 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
Atmel AT45DB011D (1Mbit) ROM. If a different THE INFORMATION CONTAINED HEREIN IS THE
ROM is used then the straps must change. PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
NOTE: ENETM requires SI pull-down instead of SO. I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 39 OF 110
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 37 OF 101

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

THIS PAGE IS DIFFERENT BETWEEN K60 AND K62.

m
co
CRITICAL

T4000

s.
LFE9249APF
SOI
1 TCT1 MCT1 24 ENETCONN_MCT0

2 TD1+ 1CT:1CT MX1+ 23

C 95 37 BI ENETCONN_MDI_P<0> ENETCONN_MDI_T_P<0> BI 38 95
C

ic
NOTE PAIR AND PIN POLARITY SWAPS CRITICAL
95 37 BI ENETCONN_MDI_N<0> 3 TD1- MX1- 22 ENETCONN_MDI_T_N<0> BI 38 95
J4000
RJ45-K60K62

at
4 TCT2 MCT2 21 ENETCONN_MCT1 F-ANG-TH
ENET_MDI
95 37 BI ENETCONN_MDI_N<1> 5 TD2+ 1CT:1CT MX2+ 20 ENETCONN_MDI_T_N<1> BI 38 95 95 38 BI ENETCONN_MDI_T_P<1> 1
TRAN_P0
CKPLUS_WAIVE=NDIFPR_BADTERM CKPLUS_WAIVE=NDIFPR_BADTERM
95 38 BI ENETCONN_MDI_T_N<1> 2
TRAN_N0
ENETCONN_MDI_P<1> 6 TD2- MX2- 19 ENETCONN_MDI_T_P<1> BI ENETCONN_MDI_T_N<0> 3

em
95 37 BI 38 95 CKPLUS_WAIVE=NDIFPR_BADTERM 95 38 BI TRAN_P1
95 38 ENETCONN_MDI_T_P<2> 4
BI TRAN_P2
7 TCT3 MCT3 18 ENETCONN_MCT2 95 38 BI ENETCONN_MDI_T_N<2> 5
TRAN_N2
CKPLUS_WAIVE=PDIFPR_BADTERM 95 38 BI ENETCONN_MDI_T_P<0> 6
TRAN_N1
95 37 BI ENETCONN_MDI_P<2> 8 TD3+ 1CT:1CT MX3+ 17 ENETCONN_MDI_T_P<2> BI 38 95
95 38 ENETCONN_MDI_T_P<3> 7
BI TRAN_P3
95 38 BI ENETCONN_MDI_T_N<3> 8
TRAN_N3
95 37 BI ENETCONN_MDI_N<2> 9 TD3- MX3- 16 ENETCONN_MDI_T_N<2> BI 38 95

ch
9
10 TCT4 MCT4 15 ENETCONN_MCT3 SHIELD
10 PINS
95 37 BI ENETCONN_MDI_N<3> 11 TD4+ 1CT:1CT MX4+ 14 ENETCONN_MDI_T_N<3> BI 38 95
CKPLUS_WAIVE=NDIFPR_BADTERM CKPLUS_WAIVE=NDIFPR_BADTERM 514-0733
ENETCONN_MDI_P<3> 12 TD4- MX4- 13 ENETCONN_MDI_T_P<3> BI

kS
95 37 BI 38 95

157S0071

oo
B eb B

1 1 1 1
ENETCONN_TCT R4000 R4001 R4002 R4003
75 75 75 75
5% 5% 5% 5%
1 C4001 1 C4002 1 C4003 1 C4004
ot
1/16W 1/16W 1/16W 1/16W
0.1UF 0.1UF 0.1UF 0.1UF MF-LF MF-LF MF-LF MF-LF
20% 20% 20% 20% 2 402 2 402 2 402 2 402
10V
2 CERM 2 10V 10V
2 CERM 2 10V
CERM CERM
402 402 402 402
ENETCONN_MCT_BS
N

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
NOSTUFF
PLACE ONE CAP PER TCT PIN 1 C4000
NOTE: Check with PHY and Magnetics MFR to determine what to do with center taps. 1000PF
10%
2KV
2 CERM
1206

NOTE: BOB SMITH TERMINATION FOR EMC.

A SYNC_MASTER=K62_MARK SYNC_DATE=01/09/2011 A
PAGE TITLE

Ethernet Connector
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

=PP3V3_S0_FWPHY 6 39 40 41
7 mA I/O
138 mA

1 1 1 1 1
C4120 C4121 C4122 C4123 C4124
1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
402 402 402 402 402

L4130
120-OHM-0.3A-EMI
D 114 mA FireWire PHY
98 PP3V3_FW_FWPHY_VDDA 1 2
D
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM 0402-LF
VOLTAGE=3.3V
C4130 1
C4131 1
C4132 1

1UF 1UF 1UF

10% 10% 10%
6.3V 6.3V 6.3V
CERM 2 CERM 2 CERM 2
402 402 402
K18 has 0.475-ohm upstream of L4110

L4110 L4135
40 =PP1V0_S0_FWPHY 120-OHM-0.3A-EMI 120-OHM-0.3A-EMI
1 2 98 PP1V0_FW_FWPHY_AVDD
25 mA PCIe SerDes 17 mA PCIe SerDes 1 2
135 mA 98 PP3V3_FW_FWPHY_VP25
MIN_LINE_WIDTH=0.4 MM MIN_LINE_WIDTH=0.4 MM
0402-LF MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 0402-LF
VOLTAGE=1.0V VOLTAGE=3.3V
1 C4110 1 C4111 C4135 1 C4136 1

1UF 1UF 1UF 1UF

10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM CERM 2 CERM 2
402 402 402 402

m
110 mA Digital Core 0 mA VReg PWR

co
1
C4100 1
C4101 1
C4102 1
C4103 1
C4104 1
C4105 1
C4106 C4141 1 1
C4140
1UF 1UF 1UF 1UF 1UF 1UF 1UF 0.1UF 1UF
10% 10% 10% 10% 10% 10% 10% 20% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 10V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 2 CERM

s.
402 402 402 402 402 402 402 402 402

C C

ic
PLACEMENT_NOTE=Place C4170 close to U1800
PLACEMENT_NOTE=Place C4171 close to U1800

C4170

B12
C13

E10

H12

M12

N11

C12

G12

L11

A12

L10

K12
APN: 338S0753 -> 1 2 16V PCIE_FW_R2D_C_N

J1
L3

L9
IN 18 93
0.1UF10%

at
X5R 402
VDD10 VDD33 VDDH VP VP25 VREG_PWR C4171 1 2 16V PCIE_FW_R2D_C_P IN 18 93
OMIT 0.1UF10% X5R 402
NC
B13 ATBUSB PCIE_RXD0N N8 93 PCIE_FW_R2D_N
CRITICAL
NC
A13 ATBUSH PCIE_RXD0P N7 93 PCIE_FW_R2D_P
U4100

em
A11 ATBUSN PCIE_TXD0N N5 93 PCIE_FW_D2R_C_N C4175 1 2 16V PCIE_FW_D2R_N
NC 0.1UF10%
OUT 18 93

FW643 N6 PCIE_FW_D2R_C_P X5R 402

PCIE_TXD0P 93
40 IN FW_PHY_DS0 F12 DS0 (IPD) NT-19 C4176 1 2 16V
BGA
PCIE_FW_D2R_P OUT 18 93
40 IN FW_PHY_DS1 E12 DS1 (IPD) NT-20 0.1UF10% X5R 402
REFCLKN N9 PCIE_CLK100M_FW_N IN 18 93
40 IN FW_PHY_DS2 E13 DS2 (IPD) NT-21 PCI EXPRESS PHY PLACEMENT_NOTE=PLACE C4175 CLOSE TO U4100
REFCLKP N10 PCIE_CLK100M_FW_P IN 18 93 PLACEMENT_NOTE=PLACE C4176 CLOSE TO U4100
40 BI FW_P0_TPA_N B8 TPA0N

ch
40 BI FW_P0_TPA_P A8 TPA0P
NT-4 (IPU) TCK M4 TP_FW643_TCK
95 40 BI FW_P1_TPA_N B5 TPA1N
NT-3 (IPU) TDI N2 TP_FW643_TDI
95 40 BI FW_P1_TPA_P A5 TPA1P TEST CONTROLLER =PP3V3_S0_FWPHY 6 39 40 41
(IPU) TDO M1 TP_FW643_TDO
95 40 BI FW_P2_TPA_N B3 TPA2N
NT-1 (IPU) TMS M3 TP_FW643_TMS
95 40 BI FW_P2_TPA_P A3 TPA2P 1394 PHY NOSTUFF

kS
R4165 1
FW_P0_TPB_N B9 N1 FW643_TRST_L 1
40 BI TPB0N NT-2 (IPU) TRST* R4166
40 BI FW_P0_TPB_P A9 TPB0P 10K 10K
5% 5%
95 40 BI FW_P1_TPB_N B6 TPB1N 1/16W 1/16W
MF-LF MF-LF
FW_P1_TPB_P A6 TPB1P NT-10 (IPD) 402 2
2 402
95 40 BI
WAKE* C2 FW_PME_L OUT 15 21 100
95 40 BI FW_P2_TPB_N B4 TPB2N NT-12 (IPD)
98 41 PPVP_FW_PHY_CPS FIXME!!! - TYPO IN SYMBOL REGCTL REGCLT D13 FW643_REGCTL

oo
95 40 BI FW_P2_TPB_P A4 TPB2P
PLACEMENT_NOTE=Place close to U4100.B10 POWER MANAGEMENT VAUX_DETECT E1 FW643_VAUX_DETECT
R4160 1 40 BI FW_P0_TPBIAS B7 TPBIAS0 FIXME!!! - TYPO IN SYMBOL VAUX_ENABLE VAUX_DISABLE D2 TP_FW643_VAUX_ENABLE

B 200K
1%
1/16W
40

40
BI
BI
FW_P1_TPBIAS
FW_P2_TPBIAS
C3

A2
TPBIAS1
TPBIAS2
NT-13 (OD) CLKREQN L2 FW_CLKREQ_L OUT 15 100
1
R4164
10K
B
MF-LF 5%
402 1/16W
2 FW643_R0
eb B11 R0 MF-LF
FW643_TPCPS B10 TPCPS 2 402
NT-16 (IPD) SCIFCLK G2 TP_FW643_SCIFCLK
SCIF NT-14 (IPD) SCIFDAIN G1 TP_FW643_SCIFDAIN
C4150 TP_FW643_NAND_TREE K1 NAND_TREE NT-OUT
R4150 NT-17 SCIFDOUT H1 TP_FW643_SCIFDOUT
22PF FW643_REXT L8 REXT
1 2
412 NOTE: NT-xx notes show NT-15 (IPD) SCIFMC F2 TP_FW643_SCIFMC
FW_CLK24P576M_XO FW_CLK24P576M_XO_R F13
ot
95 1 2 95 XO
NAND tree order.
5%
1% 95 FW_CLK24P576M_XI G13 XI NT-9
50V
CRITICAL 1/16W
1 MF-LF
CERM
402
Y4150 402 TP_FW643_SE M13 SE (IPD)
24.576M
HC49-USMD
R4161 1 1
R4170 TP_FW643_SM N13 SM (IPD)
SERIAL EEPROM NT-7 SCL N12 FW643_SCL
N

2 2.94K 191 CONTROLLER NT-6 SDA M11 TP_FW643_SDA

C4151 1% 1% TP_FW643_MODE_A J2 MODE_A (IPD) NT-18
22PF 1/16W 1/16W
MF-LF MF-LF TP_FW643_CE L13 CE (IPD)
1 2
402 402
2 2 TP_FW643_FW620_L D12 FW620* (IPU) MISCELLANEOUS
5% TP_FW643_JASI_EN D1
50V K18 has a different crystal JASI_EN (IPD) NT-11
CERM TP_FW643_AVREG A10 AVREG CHIP RESET NT-5 PERST* N4 FW_RESET_L 27 100
402 IN
TP_FW643_VBUF H13 VBUF
FW643_PU_RST_L K13 1
FW_RESET* (IPU) NT-8 R4163
10K
40 FW643_OCR10_CTL J12 OCR_CTL_V10 5%
R4162 1 1
C4162 J13 OCR_CTL_V12 (Reserved)
1/16W
MF-LF
External power-on reset (IPU 100K): 470K NC 402
5%
0.33UF 2
Per LSI, R4162 and C4162 can be NOSTUFF -> 1/16W 10% VSS VREG_VSS
6.3V
MF-LF 2
B2

D7
D9

D10

F7
F8

F10

G4
G6

G10

H8
H10

J10

K10

L12
CERM-X5R
402 402
2

A SYNC_MASTER=K62_ROSITA SYNC_DATE=01/09/2011 A
PAGE TITLE

FireWire LLC/PHY (FW643)

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

D D
Termination
Place close to FireWire PHY
FW643 1.0V GENERATION
39 FW_P0_TPBIAS
VOLTAGE=1.86V
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.08MM

CRITICAL
Q4200 1 C4250 R42501 1
R4251
BCP6916DG 0.33UF 56.2 56.2
10% 1% 1%
SOT223-4 6.3V
2 CERM-X5R 1/16W 1/16W
402 MF-LF MF-LF
2 PP1V0_S0_FW_VDD =PP1V0_S0_FWPHY 39 402 2 2 402
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3MM
MAKE_BASE=TRUE
=PP3V3_S0_FWPHY 1 C4210 1 C4211 1 C4212 1 C4213

m
41 40 39 6 3 4 MIN_LINE_WIDTH=0.6MM
0.1UF 0.1UF 10UF 10UF MIN_NECK_WIDTH=0.1MM
20% 20% 20% 20% VOLTAGE=1.0V
1 2 10V 10V
2 CERM 2 6.3V 2 6.3V
CERM CERM CERM
1 C4200 1 C4201 402 402 805-1 805-1
2.2UF 2.2UF

co
20% 20% 39 FW_P0_TPA_P FW_PORT0_TPA_P 41 95
6.3V 6.3V NOTE: MULTIPLE VIAS TO DGND MAKE_BASE=TRUE
2 CERM 2 CERM NOTE: Q4200 COLLECTOR CONNECT TO CAPS WITH 0.4 SQ-IN HEAT SINK 39 FW_P0_TPA_N FW_PORT0_TPA_N 41 95
402-LF 402-LF MAKE_BASE=TRUE
39 FW_P0_TPB_P FW_PORT0_TPB_P 41 95
MAKE_BASE=TRUE
39 FW_P0_TPB_N FW_PORT0_TPB_N 41 95
MAKE_BASE=TRUE

s.
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY 1
R42521 R4253
C 56.2 C

ic
56.2 1%
1% 1/16W
1/16W MF-LF
R4200 MF-LF
402 2 2 402
75

at
39 FW643_OCR10_CTL 1 2 FW_OCR10_CTL_R
NET_SPACING_TYPE=SWITCHNODE NET_SPACING_TYPE=SWITCHNODE
MIN_LINE_WIDTH=0.25MM 5% MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM 1/16W MIN_NECK_WIDTH=0.2MM
DIDT=TRUE MF-LF DIDT=TRUE FW_P0_TPA_C
402

em
1
R4254
C4254 1 1%
4.99K
220PF 1/16W
5% MF-LF
25V
CERM 2 2 402
402

ch
kS
1394 PHY DATA/STROBE OPTIONS
41 40 39 6 =PP3V3_S0_FWPHY 2ND & 3RD TPA/TPB PAIR UNUSED

oo
39 FW_P1_TPBIAS NC_FW_PORT1_TPBIAS
MAKE_BASE=TRUE
NOSTUFF NO_TEST=TRUE
B 1
R4255 1R4256 1R4257 95 39 FW_P1_TPA_P NC_FW_PORT1_TPA_P
B
10K 10K 10K MAKE_BASE=TRUE
5% 5% 5% NO_TEST=TRUE
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
eb 95 39 FW_P1_TPA_N NC_FW_PORT1_TPA_N
2 402 2 402 2 402 MAKE_BASE=TRUE
NO_TEST=TRUE

39 FW_PHY_DS0 95 39 FW_P1_TPB_P NC_FW_PORT1_TPB_P

MAKE_BASE=TRUE
NO_TEST=TRUE
39 FW_PHY_DS1
FW_P1_TPB_N NC_FW_PORT1_TPB_N
ot
THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT 95 39
MAKE_BASE=TRUE
39 FW_PHY_DS2 IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE, FW643 NO_TEST=TRUE
HAS INTERNAL 100K PULL-DOWNS, ONLY PULL-UPS NECESSARY.
39 FW_P2_TPBIAS NC_FW_PORT2_TPBIAS
MAKE_BASE=TRUE
N

1
R4258 NO_TEST=TRUE
10K FW_P2_TPA_P NC_FW_PORT2_TPA_P
5% 95 39
1/16W MAKE_BASE=TRUE
MF-LF NO_TEST=TRUE
2 402 95 39 FW_P2_TPA_N NC_FW_PORT2_TPA_N
MAKE_BASE=TRUE
NO_TEST=TRUE

95 39 FW_P2_TPB_P NC_FW_PORT2_TPB_P
MAKE_BASE=TRUE
NO_TEST=TRUE
95 39 FW_P2_TPB_N NC_FW_PORT2_TPB_N
MAKE_BASE=TRUE
NO_TEST=TRUE

NOTE: AGERE’S RECOMMENDATION FOR UNUSED PORTS

A SYNC_MASTER=K62_ROSITA SYNC_DATE=01/09/2011 A
PAGE TITLE

FireWire: 1394B MISC

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

INRUSH RESETABLE PTC

CRITICAL PLACEMENT_NOTE=PLACE CLOSE TO F4300
POUR COPPER TO SINK HEAT
CRITICAL
F4301 XW4300
1 2 PPVP_FW_PHY_CPS
0.3AMP-60V OUT 39 98

12 VOLTS Q4350 1 2 SM
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
FDC610PZ VOLTAGE=12V

14 WATTS MAX PER PORT SSOT6 SMD030F-SM

POUR COPPER TO SINK HEAT

6
R4300 CRITICAL CRITICAL
CRITICAL CRITICAL
L4300

5
0.33 2 Q4300 F4300
=PP12V_S0_FW PP12V_S0_VG_OK P12V_FW_R D4300 D

4
1
98 98
FERR-250-OHM
D 41 6

1 2
MIN_LINE_WIDTH=1.7MM
5%
MIN_LINE_WIDTH=1.7MM FDC610PZ SM 3AMP-32V
MIN_NECK_WIDTH=0.5MM MIN_NECK_WIDTH=0.5MM
VOLTAGE=12V 1W VOLTAGE=12V SSOT6 98 P12V_FW_CL 1 2 98 P12V_FW_D 1 2 98 FW_PORT0_VP_F 1 2 98 FW_PORT0_VP
MF MIN_LINE_WIDTH=1.7MM MIN_LINE_WIDTH=1.7MM MIN_LINE_WIDTH=1.7MM MIN_LINE_WIDTH=1.7MM
2512 MIN_NECK_WIDTH=0.5MM MIN_NECK_WIDTH=0.5MM MIN_NECK_WIDTH=0.5MM SM MIN_NECK_WIDTH=0.5MM

6
VOLTAGE=12V CRS08-1.5A-30V VOLTAGE=12V 603 VOLTAGE=12V VOLTAGE=12V

2 5
1 FAST NON-RESETABLE FUSE

4
R4351 NOSTUFF
1K C4351 1 THIS FUSE WILL NOT BLOW
1 C4300
0.01UF

1
5%
1/16W
0.001UF 3
NOSTUFF IT IS HERE FOR SAFETY ONLY 10%
MF-LF
20% 50V SHOULD BE DONE AS A POWER STRIP(SUBPLANE)
50V
2 402 CERM 2
402
Q4301 5.1V 3 D4305 2 X7R
603-1

3
MMBT2907AXG D4301 1 MMBD914XG
60V-600MA SOT23
FWPWR_ON_L SOT23 MMBZ5231BXG 1
SOT23

3
1
R4355
1K R4352
5% 51.1K2
1/16W
MF-LF
1 41 FW_CURRENT_LIMIT
402 1%
2 1
R4301 PORT 0

m
1/16W
FWPWR_EN_L

MF-LF 10K FW_TURN_ON_V

402
5%
1/16W 1
1394B
MF-LF
2 402
R4302 1R4303
15K 20K

co
5% 5% CRITICAL
FW_CURRENT_LIMIT_Q 1/10W
MF-LF
1/16W
MF-LF
J4300
2 603 2 402
FWB-PL-K60-K62
3 3 F-ANG-TH
D Q4302 1 FW_FET_LINEAR_LIMIT_OUT FW_PORT0_TPB_N 1 TPB- TPB(R)
Q4351 MMBT2222A7F IN 41
95 41 40 BI
NO_TEST=TRUE 9
2N7002 SOT23 FW_FET_LINEAR_LIMIT_IN

s.
OUT 41
1 G S SOT23-HF1 2 PLACE CLOSE TO COMPARATOR 95 41 40 BI FW_PORT0_TPB_P 2 TPB+ VP

1 NO_TEST=TRUE 8
2 1 C4302 R4307 7
20K
C 0.01UF NC SC/NC
C

ic
20% 5% 6
16V 1/16W
2 CERM MF-LF 95 41 40 BI FW_PORT0_TPA_N 3 TPA- VG
402 2 402 NO_TEST=TRUE FW_PORT0_TPA_R 5
FW_PORT0_TPA_P 4 TPA+ TPA(R)

at
95 41 40 BI
NO_TEST=TRUE
10
SHIELD
NOSTUFF 11 PINS
D4302

em
R4304 BAS40XG C4332 1
514-0769
100K 2 1 3 0.001UF
1 FW_FET_LINEAR_LIMIT_FB 10%
50V
5% AREF needs to be isolated from all CERM 2
1/16W SOT23 402
MF-LF 41 6 =PP12V_S0_FW local grounds per 1394b spec
402
When a billingual device is connected to a
beta-only device, there is no DC path
C4304

ch
1 between them (to avoid ground offset issue)
8 0.1UF
10%
16V R43351 1 C4335
V+ 2 X7R-CERM BREF should be hard-connected to logic 1M 0.1UF
10%
U4300 402
ground for speed signaling and connection 1%
1/16W 2 50V
LM393 X7R
MF-LF 603-1
5.1V 6 SOI-HF 402 2

kS
7 NC
R4305
D4303
SOT23
5

FW_CURRENT_LIMIT 100K 2 3 1 2
41 IN 1 FW_CURRENT_LIMIT_R FW_CURRENT_LIMIT_RD 1 FW_FET_LINEAR_LIMIT_OUT OUT 41
5% 41 FW_FET_LINEAR_LIMIT_IN 3
1/16W IN
MF-LF MMBZ5231BXG

oo
402 GND
4

B PLACE CLOSE TO COMPARATOR

C4305 1
1
R4306 B
200K
2.2UF 5%
10%
16V 2
eb 1/16W
MF-LF
X5R 2 402
603
ot
N

ACTIVE "LATE VG" + ESD PROTECTION

40 39 6
=PP3V3_S0_FWPHY

C4350 1
0.1UF
10%
16V
PLACEMENT_NOTE=PLACE U4350 CLOSE TO J4300 X7R-CERM 2
402
1

VCC
U4350
TPD4S1394
TP_FW_LATEVG_VCLMP 3 VCLMP LLP 8
CRITICAL D1+ FW_PORT0_TPB_P BI 40 41 95

FWPWR_EN D1- 7 FW_PORT0_TPB_N BI 40 41 95

A NOSTUFF
4 FWPWR_EN
D2+ 6 FW_PORT0_TPA_P BI 40 41 95
SYNC_MASTER=K62_ROSITA SYNC_DATE=01/09/2011 A
PAGE TITLE
1 D2- 5 FW_PORT0_TPA_N
R4350
100K
GND BI 40 41 95
FIREWIRE CONNECTOR
2

5% DRAWING NUMBER SIZE

1/16W
MF-LF
Apple Inc. 051-8442 D
2 402 REVISION
R
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
43 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 41 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D SILKSCREEN:HDD PWR HDD Power D

SILKSCREEN:SATA0
SATA PORT A0 FOR HDD J4511
50293-00771-H01 =PP12V_S0_SATA 6 42
12V 2A/0.8A
M-ST-SM
J4510 1
EP00-081-91
M-ST-SM 2 =PP5V_S0_SATA 6 42 5V 1.2A/0.34A
1 3
C4510 1 2 SATA_HDD_R2D_C_P 4
2 93 SATA_HDD_R2D_P 0.01UF 10% CERM
16V 402
3 93 SATA_HDD_R2D_N IN 18 93 5 L4511
4 C4511 1 2 SATA_HDD_R2D_C_N IN 18 93
6 FERR-220-OHM
5
0.01UF 10% CERM
16V 402 7 97 HDD_OOB_TEMP_FB 1 2 HDD_OOB_TEMP_FILT
93 SATA_HDD_D2R_C_N 51 97 101

6 CRITICAL 0402
93 SATA_HDD_D2R_C_P C4515 1 2 SATA_HDD_D2R_N
7
0.01UF 10% CERM
16V 402
518S0813 C4518 1 1 C4517

m
OUT 18 93
CRITICAL OUT 18 93
10UF 10UF
10% 20%
C4516 SATA_HDD_D2R_P 25V 2 10V
518S0251 0.01UF
1 2
10% CERM
X5R 2
1206-1
X5R
603
16V 402

co
BOMOPTION OPTIONS FOR SATA PORT A1 AND A2
SATA PORT A1 FOR SSD/ODD SATA PORT A2 FOR ODD
A1 A2 ODD_SATA:P1 ODD_SATA:P2

s.
SSD ODD X SILKSCREEN:SATA2
C ODD X SILKSCREEN:SATA1 ODD_SATA:P2
=PP3V3_S0_ODD C

ic
J4520 6

J4530 1735574 R45201

1735574 M-ST-TH
USE OF PORT A2 FOR SSD IS NOT INTENDED VIA BOMOPTION THOUGH MLB SUPPORTS IT. M-ST-TH
C4530 1 2 SATA_SSD_R2D_C_P 14 33K

at
14 5% ODD_SATA:P2
0.01UF 10% CERM 1/16W
16V 402 IN 18 93
MF-LF C4520 1 2 SATA_ODD_R2D_C_P
5V (SSD) 1.4A/0.8A/0.03A S1
C4531 1 2 SATA_SSD_R2D_C_N IN 18 93
GND
S1 402 2 0.01UF 10% CERM
16V 402 IN 18 93

GND 0.01UF 10% CERM

S2 C4521 1 2 SATA_ODD_R2D_C_N IN 18 93
5V (ODD) 1.5A/1A/0.14A S2 93 SATA_SSD_R2D_P
16V 402
A+ 93 SATA_ODD_R2D_P
10% CERM
A+ 0.01UF

em
S3 93 SATA_ODD_R2D_N 16V 402
S3 93 SATA_SSD_R2D_N A- ODD_SATA:P2
A- S4 ODD_SATA:P2
S4 C4532 1 2 SATA_SSD_D2R_N GND C4522 1 2 SATA_ODD_D2R_N
GND 0.01UF 10% CERM S5 SATA_ODD_D2R_C_N 10% CERM
S5 SATA_SSD_D2R_C_N 16V 402 OUT 18 93 B- 93 0.01UF 16V 402 18 93
B- 93 OUT
OUT 18 93 S6 93 SATA_ODD_D2R_C_P
S6 B+ OUT 18 93
B+ 93 SATA_SSD_D2R_C_P
C4533 1 2 SATA_SSD_D2R_P S7
C4523 1 2 SATA_ODD_D2R_P
S7 GND 0.01UF 10% CERM
16V 402
0.01UF 10% CERM
GND 16V 402 KEY ODD_SATA:P2
KEY P1
P1 DP NC

ch
DP NC P2 ODD_SATA:P2
P2 ODD_SATA:P1 +5V
+5V
P3 R4531 +5V P3 R4521
+5V P4 0 SMC_ODD_DETECT
P4 SATA1_SMC_ODD_DETECT 2
0 1 SMC_ODD_DETECT MD SATA2_SMC_ODD_DETECT 2 1 42 46 101
MD 42 46 101
P5 5%
P5 5% GND 1/16W
GND 1/16W ODD_SATA:P1 P6 MF-LF ODD_SATA:P2
P6 GND

kS
MF-LF 402
GND 402 R4532 R4522
PP5V_S0_SATA_PORTA1 0 15 PP5V_S0_SATA_PORTA2 0 PP5V_S0_SATA_FET
15
98 2 1 PP5V_S0_SATA_FET 42 CRITICAL
98 2 1 42 98
98
NET_PHYSICAL_TYPE=POWER NET_PHYSICAL_TYPE=POWER 5%
CRITICAL VOLTAGE=5V 5%
1/8W 518-0361 ODD_SATA:P2 ODD_SATA:P2 VOLTAGE=5V 1/8W
518-0361 ODD_SATA:P1 MF-LF
805 1 C4527 1 C4525 MF-LF
805
1 C4537 1 C4535 ODD_SATA:P2 10UF 1UF NOSTUFF

oo
10UF 1UF 20% 10%
20%
10V
10%
10V
R4533 10V
2 X5R
10V
2 X5R R4523
2 X5R 2 X5R 0 603 402 0 =PP5V_S0_SATA
603 402 2 1 =PP5V_S0_SATA 2 1 6 42

B 5%
1/8W
6 42
5%
1/8W
MF-LF
B
MF-LF 805
805
eb
SATA Activity LED
=PP3V3_S0_SATALED
ot
18 6
CRITICAL NOSTUFF
DEVELOPMENT R4550
Q4500
R4599 1
42 6
=PP5V_S0_SATA FDMC8298 1
0 2 PP5V_S0_SATA_FET 42 98
330 MLP3.3X3.3
5% VOLTAGE=5V
N

5%
1/10W 1/8W NET_PHYSICAL_TYPE=POWER
MF-LF MF-LF

1 2 3
603
2
805
SATALED_R_L

S
D
DEVELOPMENT R45031

5
A
DS4599 100K
GREEN-3.6MCD 5%

G
2.0X1.25MM-SM 1/16W
MF-LF
K 402 2
PCH_SATALED_L SILK_PART=SATA ACTIVE

4
18 SATALED_L
MAKE_BASE=TRUE
42 6
=PP12V_S0_SATA
C4500

1
1 CRITICAL
0.1UF ODD_PWR_GATE VCC
10%
16V
2 X5R
U4501
402 SLG5AP001
5D TDFN On= 2-5V
ON 2

A R4501
0
7 G S6 SYNC_MASTER=K62_JERRY SYNC_DATE=01/09/2011 A
ODD_PWR_EN_L 1 2 ODD_PWR_EN_L_R 8 PG PAGE TITLE
100 21 15 3
NC NC 3 NC
5%
1/16W
MF-LF
D
Q4502
353S2499
THRM
SATA Connectors
PAD GND DRAWING NUMBER SIZE
402 2N7002
051-8442 D

4
1 G S SOT23-HF1
Apple Inc. REVISION
R
2
10.1.0
ODD_PWR_EN_LD NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
45 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 42 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

USB/SMC DEBUG MUX ADDED AT EVT & SWITCH TO S5 RAIL

NOSTUFF
R4653
0
6 =PP3V3_G3H_SMCUSBMUX 1 2
5%
R4654 1/16W
MF-LF
=PP3V3_S5_SMCUSBMUX 1 0 402
155S0329

m
6 2
5% MOJOMUX:YES
L4630 1/16W
MF-LF
FERR-220-OHM-2.5A 402
Current Limit at 2.1Amp (@ S3 & S0) 98 PP5V_USB_PORT3 1 2 98 PP5V_USB_PORT3_F
PORT 3

co
VOLTAGE=5V 0603 VOLTAGE=5V
CRITICAL MIN_LINE_WIDTH=0.6MM PP3V3_SMCUSBMUX MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM CRITICAL
98
155S0329 MIN_NECK_WIDTH=0.2MM
U4600 L4660
TPS2561DR C4650 1

SON
FERR-220-OHM-2.5A 0.1UF
MOJOMUX:YES J4630
=PP5V_S3_USB PP5V_USB_PORT2 20%
CRITICAL USB-K60K62

9
2 IN_0 CRITICAL
OUT1 9 1 2 10V
98

s.
43 6
CERM 2 F-ANG-TH
3 IN_1 OUT2 8
VOLTAGE=5V 0603 402 VCC L4631
120-OHM-90MA
5
MIN_LINE_WIDTH=0.6MM CRITICAL
MIN_NECK_WIDTH=0.2MM DLP0NS
10 FAULT1* SMC_RX_L 5 M+ MOJOMUX:YES Y+ 1
ILIM 7 ILIM_IN1
SYM_VER-1
34 USB_EXTC_OC_L
48 47 46
1
C 35 USB_EXTD_OC_L
6 FAULT2*
C4630 C4660 48 47 46 SMC_TX_L 4 M-
U4650Y- 2 95 USB_D_MUXED_N 4 3 VBUS
C

ic
C4603 1 1 C4661 1 1 USB_PORT3_N
R46001 0.1UF 0.01uF 0.1UF 0.01uF PI3USB102ZLE
95 2
DATA-
4 EN1 23.2K 20% 20% 20% 20% 7 D+ TQFN 95 USB_PORT3_P 3
1% 10V 16V 10V 16V 95 35 USB_EXTD_P DATA+
CRITICAL 5 EN2 95 USB_D_MUXED_P 1 2
C4601 1 1 THRM 1/16W CERM 2 2 CERM CERM 2 2 CERM 95 35 USB_EXTD_N
6 D- 4
GND
C4602 MF-LF 402 402 402 402

at
0.1UF GND PAD 402 2
20%
330UF
20% 2 5 3 4 6

11
10V
CERM 2 2 6.3V (PUT CAP ON CONNECTOR SIDE) 8 OE* SEL 10

NC
IO
NC
IO
POLY-TANT
402 CASE-D3L-SM
Place R4600 very close to ILIM pin
98 PP5V_USB_PORT2_F
GND 6 VBUS
514-0768

3
1 GND
MIN_LINE_WIDTH=0.6MM
155S0329 MIN_NECK_WIDTH=0.2MM
94 63 PM_EN_USB_PWR VOLTAGE=5V R4651
CRITICAL
1
0 2 D4630
L4600 5% RCLAMP0502N
CRITICAL FERR-220-OHM-2.5A
1/16W SLP1210N6
U4620 98 PP5V_USB_PORT0 155S0329 1 2 98 PP5V_USB_PORT0_F MF-LF
402 R4652 CRITICAL
VOLTAGE=5V MOJOMUX:NO 1 0

ch
VOLTAGE=5V 0603
TPS2561DR MIN_LINE_WIDTH=0.6MM 2
SON
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM L4620 C46331 1 C4600 MIN_NECK_WIDTH=0.2MM
5%
2 IN_0 FERR-220-OHM-2.5A 0.1UF 0.01uF 1/16W
43 6 =PP5V_S3_USB OUT1 9 20% 20% MF-LF
10V 16V
3 IN_1 OUT2 8 98 PP5V_USB_PORT1 1 2 CERM 2 2 CERM 402
VOLTAGE=5V 402 402 MOJOMUX:NO
MIN_LINE_WIDTH=0.6MM 0603
USB_EXTA_OC_L 10 FAULT1* ILIM 7 ILIM_IN2 MIN_NECK_WIDTH=0.2MM CRITICAL
PORT 2

kS
34
USB_DEBUGPRT_EN_L
35 USB_EXTB_OC_L
CRITICAL
6 FAULT2*
R46201 C4623 1 1 C4624 47 46

0.1UF 0.01uF SEL=1: CHOOSE USB

C4621 1 1
C4622 4 EN1 23.2K 20% 20% 98 PP5V_USB_PORT1_F SEL=0: CHOOSE SMC
1% 10V 16V
0.1UF CERM 2 2
20%
330UF 5 EN2
THRM
1/16W
MF-LF 402
CERM
402 VOLTAGE=5V J4620
10V 20% MIN_LINE_WIDTH=0.6MM CRITICAL
2 6.3V GND PAD 402 2 USB-K60K62
CERM 2 POLY-TANT MIN_NECK_WIDTH=0.2MM
402 L4621 F-ANG-TH

oo
CASE-D3L-SM
1

(PUT CAP ON CONNECTOR SIDE) 120-OHM-90MA 5

Place R4620 very close to ILIM pin DLP0NS
SYM_VER-1

B J4610
USB-MG6-K60-K62 95 34 USB_EXTC_N
4 3
95 USB_PORT2_N
1
2
VBUS
DATA-
B
CRITICAL F-ANG-TH 95 34 USB_EXTC_P 3
USB_PORT2_P
L4611 95
5
PORT 1 1 2 DATA+
eb 120-OHM-90MA 4
DLP0NS GND
SYM_VER-1
1
4 3 VBUS 2 5 3 4 6
95 USB_PORT1_N 2

NC
IO
NC
IO
95 35 USB_EXTB_N DATA-
95 35 USB_EXTB_P
1 2
95 USB_PORT1_P 3
4
DATA+
6 VBUS 514-0768
ot
GND 1 GND
2 5 3 4 6

NC
IO
NC
IO
6 VBUS D4620
514-0770
N

RCLAMP0502N
1 GND SLP1210N6
CRITICAL

D4610
RCLAMP0502N
SLP1210N6
CRITICAL
CRITICAL
J4600
USB-MG6-K60-K62
USB PORT POWER: L4601 F-ANG-TH
5
120-OHM-90MA
EACH PORT IS HARDWARE Capable of : DLP0NS
STATE
S0, S3
MAX
2.7A
MIN ( WITHIN THE TOLERANCE)
2.1A -- PER PORT
95 34 USB_EXTA_N
4
SYM_VER-1

3
95 USB_PORT0_N
1
2
VBUS
DATA-
PORT 0
WHEN CURRENT HITS LIMIT, TPS2561 BECOME CONSTANT CURRENT MODE 95 34 USB_EXTA_P 95 USB_PORT0_P 3
AND STAY AT THE LIMIT LEVEL UNTIL THERMAL SHUTDOWN WHEN JUNCTION REACH 130C 1 2
DATA+
4
A SOFTWARE WILL ALOW 500MA/PORT, PLUS 2700MA EXTRA POWER TO BE
distributed to approved devices on a 1st-come, 1st-served basis.
2 5 3 4
GND
SYNC_MASTER=K62_JERRY SYNC_DATE=01/09/2011 A
6 PAGE TITLE
NC
IO
NC
IO

6 VBUS
514-0770 EXTERNAL USB CONNECTORS
1 GND DRAWING NUMBER SIZE
EXAMPLE: Port 1 - iPad fast charging = 2100mA
Port 2 - Wired Keyboard = 1100mA Apple Inc. 051-8442 D
REVISION
Port 3 - iPhone fast charging = 1000mA R

PORT 4 - USB 2.0 500MA = 500MA

D4600 10.1.0
RCLAMP0502N NOTICE OF PROPRIETARY PROPERTY: BRANCH
TOTAL: 4700MA SLP1210N6
THE INFORMATION CONTAINED HEREIN IS THE
CRITICAL PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
46 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 43 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

m
IR RECEIVER CONNECTOR CAMERA/ALS & BLUETOOTH (K37A) CONNECTOR
IR

co
IR CRITICAL CRITICAL
L4700
CRITICAL
L4702
J4780
53261-8604 =PP5V_S3_CAMERA
220-OHM-1.4A
120-OHM-90MA M-RT-SM 6
1 2 98 PP5V_S3_CAMERA_FLT
DLP0NS NET_PHYSICAL_TYPE=POWER 0603
SYM_VER-1 5 VOLTAGE=5V CRITICAL

s.
C4701 1 MIN_LINE_WIDTH=0.6MM
4 3 C4700 1 MIN_NECK_WIDTH=0.2MM
95 34 USB_IR_N 101 95 USB_IR_L_N
95 USB_IR_L_P
1 10UF
20%
10V
0.1UF
20%
10V
J4700
95 34 USB_IR_P 101 2
X5R 2 CERM 2 50224-01311-001
C 1 2
3 805 402 M-RT-SM C

ic
101 98 PP5V_S3_IR_FLT 14
4 120-OHM-90MA
VOLTAGE=5V DLP0NS
L4703 MIN_LINE_WIDTH=0.6MM
IR MIN_NECK_WIDTH=0.2MM
SYM_VER-1

220-OHM-1.4A L4701 4 3 CRITICAL 1

=PP5V_S3_IR C4781 6

at
1 2
6
1 2 95 20 USB_CAMERA_N 101 95 USB_CAMERA_L_N
1UF USB_CAMERA_P 95 USB_CAMERA_L_P 3
NET_PHYSICAL_TYPE=POWER 0603 10% 95 20 101
CRITICAL 16V 1 2
2 X5R 4
IR
603
518S0667 49 =SMB_ALS_SCL 5

em
BT 120-OHM-90MA
DLP0NS 49 =SMB_ALS_SDA 6
SYM_VER-1
CRITICAL
L4720 4 3
7
USB_BT_L_N 8
95 35 USB_BT_N 101 95

101 95 USB_BT_L_P 9
95 35 USB_BT_P
1 2 10
101 97 52 SNS_SKIN_LEFT_P 11

ch
101 97 52 SNS_SKIN_LEFT_N 12
CRITICAL 13
BT
L4721 220-OHM-1.4A

SD Card Reader Board ( Lazarus ) 6 =PP3V3_S3_BT

NET_PHYSICAL_TYPE=POWER
1
0603
2 98

VOLTAGE=3.3V
PP3V3_S3_BT_FLT
MIN_LINE_WIDTH=0.5MM
15

kS
BT BT
MIN_NECK_WIDTH=0.2MM 1 C4720
10UF
1 C4721
0.1UF
518S0785
CRITICAL 20% 20%
6.3V 10V
CRITICAL 2 CERM 2 CERM

L4750 J4750
SM06B-SRKS-G-TB-HF
805-1 402

120-OHM-90MA

oo
DLP0NS F-RT-SM
SYM_VER-1 7
4 3
USB_SDCARD_N Skin Temp sense at upper Left Screen corner
B 95 34

95 34 USB_SDCARD_P
95

95
USB_SDCARD_L_N
USB_SDCARD_L_P
1
2
B
1 2
3
eb 4
CRITICAL
L4751 5
FERR-250-OHM 6
=PP3V3_S3_SDCARD
45 6
1 2 PP3V3_S3_SDCARD_FLT 98

NET_PHYSICAL_TYPE=POWER SM
VOLTAGE=3.3V 8
MIN_NECK_WIDTH=0.2MM
ot
MIN_LINE_WIDTH=0.6MM

100 SDCARD_RESET_L 518S0751

R4750 C4750 1
N

10K 1UF
1 2 10%
6.3V
CERM 2
1% 6
1/16W 402
MF-LF
402
D
Q4710
2N7002DW-X-G
101 100 21 15
SDCARD_RESET 2 G S
SOT-363

1
R4751 1
10K
1%
1/16W
SDCARD_PLT_RST_R_L
MF-LF
2 402 3
D Q4710
2N7002DW-X-G
SOT-363
100 27 SDCARD_PLT_RST_L 5 G S

A 4
SYNC_MASTER=K62_JERRY SYNC_DATE=01/09/2011 A
PAGE TITLE

Internal USB Connections

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

D D
SD CARD 3.3V OVERCURRENT PROTECTION CHIP WITH ACTIVE LOAD DISCHARGE
TPS2065-1 (1.0A LIMIT) HAS ACTIVE LOAD DISCHARGE SO R4800 IS NOSTUFF.

DEVELOPMENT
CRITICAL

U4800 =PP3V3_S0_SW_SD_PWR 45
TPS2065-1
2 IN0 DGN OUT0 6
6 =PP3V3_S0_SDCARD 3 IN1 OUT1 7
PP3V3_S0_SW_SD_PWR 98
OUT2 8 MAKE_BASE=TRUE
353S0004 MIN_LINE_WIDTH=0.4 mm
37 ENET_CR_PWREN 4 EN NOSTUFF MIN_NECK_WIDTH=0.2 mm
OC* 5 DEVELOPMENT DEVELOPMENT
1
VOLTAGE=3.3V
R4800

m
DEVELOPMENT DEVELOPMENT DEVELOPMENT THRM
1 C4802 1 C4803 47K
GND PAD 10UF 0.1UF 5% =PP3V3_S0_PCH_GPIO
1 C4805 1 C4800 1 C4801 20%
2 6.3V
10%
2 16V
1/16W 6 20

9
22UF 10UF 0.1UF X5R X7R-CERM MF-LF DEVELOPMENT
20% 20% 10% 603 402 2 402
6.3V
2 6.3V 2 16V R48011

co
2 CERM-X5R X5R X7R-CERM
805-3 603 402 10K
5%
1/16W
MF-LF
DEVELOPMENT 402 2

SD SPEC REQUIRES 47 UF R4802

CAPACITANCE ON 3.3V INPUT. 0

s.
SDCONN_OC_L_R 1 2 TP_SDCONN_OC_L
22 + 10 + 10 + 2.2 (FLEX)
5%
1/16W
MF-LF

C 402
C

ic
at
em
SDCONN DETECT DEBOUNCE, INVERSION, AND DETECT-CHANGED PCH GPIO CIRCUIT SD CARD CONNECTOR
DEVELOPMENT
CRITICAL

ch
998-3513
J4800
44 6 =PP3V3_S3_SDCARD SDCONN_DETECT_L OUT 37 -> TO ENET CHIP 50671-02641
F-RT-SM
28
DEVELOPMENT
1

kS
R4810 1
10K 3 45 SDCONN_DETECT 2
5% NOSTUFF
1/16W 3
MF-LF
D Q4810 (CARD INSERTED = OPEN)
402 2 2N7002 DEVELOPMENT 37 OUT SDCONN_WP 4 CAESAR-IV CARD DETECT IS PROGRAMMABLE, BUT A SILICON BUG
SOT23-HF1
1 G S 95 37 SDCONN_DATA<7> 5 MAKES THE ACTIVE-HIGH CASE UNUSABLE.
BI
6

oo
SDCONN_DATA<6>
2 C4812 1 95 37 BI
7
0.1UF
DEVELOPMENT 20%
10V GENERATE A 1 PULSE ON 95 37 SDCONN_DATA<1> 8

B R4811
33K
CERM
402
2
CARD INSERT OR REMOVAL
DEVELOPMENT
BI
9 B
1 2 SDCONN_DETECT_SHORT_DLY DEVELOPMENT L4800 95 37 BI SDCONN_DATA<0> 10
6
74LVC1G86GF FERR-10-OHM-500MA 11
5%
1/16W 1
SOT891
eb R4814
MF-LF Vih = 2.0V 0 95 37 SDCONN_CLK 1 2 SDCONN_CLK_L 12
SDCONN_DETECT 402 4 SDCONN_DETECT_PULSE 1 2 SDCONN_STATE_CHANGE OUT IN
45 IN
Vil = 0.8V 2
U4810 20 25 100
SM 13
R4812 NC
DEVELOPMENT
5%
1/16W
-> TO PCH GPIO 14
-> FROM SD CONN 33K 5 MF-LF
15
1 2 SDCONN_DETECT_LONG_DLY 3
X 402 45 =PP3V3_S0_SW_SD_PWR
SDCONN_CMD 16
ot
5% NC 95 37 OUT
1/16W
MF-LF
402
C4810 1 C4811 1 17
1UF 0.1UF 95 37 SDCONN_DATA<3> 18
DEVELOPMENT 10% 20% BI
10V 10V DEVELOPMENT 19
X5R 2 CERM 2
N

402-1 402
95 37 SDCONN_DATA<5> 20
BI
DEVELOPMENT 21

95 37 SDCONN_DATA<2> 22
BI
23

95 37 SDCONN_DATA<4> 24
BI
25
26

A SYNC_MASTER=K62_MARK SYNC_DATE=01/09/2011 A
PAGE TITLE

SD READER CONNECTOR
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

D D
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
338S0878 98 47 46 PP3V3_G3H_AVREF_SMC Peak/Ave/Standby = 2mA/1mA/5uA

SMC_EXCARD_PWR_EN B12 P10

U4900 P60 L13 SMC_PM_G2_EN
47 46 6 =PP3V3_G3H_SMC Peak/Ave/Sleep/Standby = 40mA/25mA/20mA/50uA
47 OUT H8S2117 OUT 75 100

47 OUT SMC_RSTGATE_L C13 P11 LFBGA P61 L14 NC 1

C4904 1
C4905 1
C4906
ALL_SYS_PWRGD_SMC
C4902 1 1
C4903
100 64 IN A15 P12 (1 OF 4) P62 L15 NC 22UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20%
RSMRST_PWRGD B14 P13 P63 K12 20% 20% 10V 10V 10V
100 64 IN OMIT NC 6.3V
2 2
10V 2 CERM 2 CERM 2 CERM
B15 K13 SMC_ADAPTER_EN CERM CERM
NC P14 P64 OUT 19 47 100 805 402 402 402 402
PM_RSMRST_L C14 P15 P65 K14
100 27 OUT NC PLACEMENT_NOTE=Place C4907 close to U4900 pin 13
47 OUT CPUIMVP_VR_ON D12 P16 P66 J12 SMC_PROCHOT_3_3_L IN 47 100

m
100 25 19 OUT PM_PWRBTN_L C15 P17 P67 J13 SMC_BIL_BUTTON_L IN 47
R4999 Peak/Ave/Standby= 2mA/1mA/5uA SMC_VCL
4.7
K62 NEW:NOT USE NC D13 P20 P70 N12 SMC_VCORE_ISENSE IN 50 97 (IMON) 1 2 98 46 PP3V3_G3H_SMC_AVCC
MIN_LINE_WIDTH=0.25 MM C4907 1

N14

J15

M14
NC D14 P21 P71 R13 SMC_VCORE_VSENSE IN 50 97
(IMON) 5% MIN_NECK_WIDTH=0.20 MM
0.47UF

A1
P1

F1
1/16W VOLTAGE=3.4V

co
D15 P22 P72 P13 SMC_CPU_1V5_ISENSE 50 97 MF-LF 10%
NC IN 402 6.3V
E12 P23 P73 R14 SMC_CPU_1V5_VSENSE C4920 1 CERM-X5R 2
NC IN 50 97
0.1UF AVCC VCC VCL AVREF
402

NC E14 P24 P74 P14 SMC_VCCSA_ISENSE IN 50 97 20%

K62 NEW:NOT USE 1 1
10V R4909 R4901
NC E15 P25 P75 R15 SMC_VCCSA_VSENSE IN 50 97 CERM
402
2
U4900 10K 10K
K62 NEW:NOT USE NC E13 P26 P76 N13 SMC_VAXG_ISENSE IN 50 97 (IMON) H8S2117 5% 5%

s.
PLACEMENT_NOTE=Place R4999 close to U4900 pin 76 LFBGA 1/16W 1/16W
NC F14 P27 P77 P15 SMC_VAXG_VSENSE IN 50 97 (IMON) PLACEMENT_NOTE=Place C4920 close to U4900 pin 76 MF-LF MF-LF
402 2
(3 OF 4) 2 402
94 48 18 BI LPC_AD<0> D9 P30 P80 C7 SMC_WAKE_SCI_L OUT 15 18 PROTO-3, Change back to WAKE_SCI_L OMIT
21 100 MD1 E2 SMC_MD1 IN 48

C 94 48 18 BI LPC_AD<1> C9 P31 P81 A7 NC K1 C

ic
MD2
94 48 18 BI LPC_AD<2> A9 P32 P82 B7 PM_CLKRUN_L OUT 15 19 48 100 100 48 47 IN SMC_RESET_L E3 RES* SMC_KBC_MDE
94 48 18 BI LPC_AD<3> B9 P33 P83 D6 LPC_PWRDWN_L IN 19 48 100
97 47 SMC_XTAL A2 XTAL
94 48 18 IN LPC_FRAME_L D8 P34 P84 C6 SMC_TX_L OUT 43 46 47 48 SMC_NMI
97 47 SMC_EXTAL B2 EXTAL NMI F4 IN 48

at
100 27 IN SMC_LRESET_L C8 P35 P85 A6 SMC_RX_L IN 43 46 47 48

94 27 IN LPC_CLK33M_SMC A8 P36 P86 B6 (OC) SMB_MGMT_CLK BI 49

48 18 BI LPC_SERIRQ D7 P37
P90 K4 SMC_ONOFF_L IN 47 100 SMC_TRST_L
ETRST* L1 IN 48
A5 P40 P91 J2 SMC_BC_ACOK

em
NC IN 47

B5 P41 P92 J1 AVSS R12 NOSTUFF

K62 P1 NOT USED, WAS OOB_TEMP NC NC 1
49 BI SMB_MGMT_DATA D5 P42 (OC) P93 J3 PM_SLP_S3_L IN 5 19 26 32 36 47 63 100 VSS R4902 1
R4998
1
R4903
10K 10K 0
47 OUT SMS_ONOFF_L C3 P43 P94 J4 PM_SLP_S4_L IN 5 19 32 47 K60 New Change 5%
5% 5%
63 100 1/16W

D2
P4
F12
B13
A4
NC B1 P44 P95 H2 PM_SLP_S5_L IN 5 19 47 63
100
K60 New Change XW4900 MF-LF
1/16W
MF-LF
1/16W
MF-LF
SM
2 402
C2 P45 P96 H1 PM_CLK32K_SUSCLK 2 402 2 402
NC IN 9 94 100
2 1
47 OUT SMC_GFX_THROTTLE_L D3 P46 P97 G2 (OC) SMB_0_S0_DATA BI 49

ch
NC C1 P47

48 47 46 43 OUT SMC_TX_L G1 P50

48 47 46 43 IN SMC_RX_L G4 P51
PP3V3_G3H_AVREF_SMC GND_SMC_AVSS 46 47 50 97
49 BI SMB_0_S0_CLK F2 P52 (OC) 98 47 46

kS
47 46 6 =PP3V3_G3H_SMC
98 46 PP3V3_G3H_SMC_AVCC

AVCC1 N15

AVREF1 M15
VCC3 P2
SMC_PA0 R3 PA0
U4900 PE0 M3 SMC_PE0
K62 NEW:NOT USE,PULLED UP 47 IN
H8S2117 IN 47 K62 NEW:NOT USE,PULLED UP

oo
100 18 OUT SPI_DESCRIPTOR_OVERRIDE_L (OC) P3 PA1 LFBGA PE1* M2 SMC_TCK IN 47 48
100 27 25 19 OUT PM_SYSRST_L (OC) R2 PA2 (2 OF 4) PE2* M1 SMC_TDI IN 47 48

B 47 43

47
OUT
IN
USB_DEBUGPRT_EN_L
MEM_EVENT_A_L
(OC)
(OC)
N3
R1
PA3
PA4 OMIT
PE3*
PE4*
L4
L2
SMC_TDO
SMC_TMS
OUT 47 48
IN 47 48
E4 U4900 B
N4
H8S2117 PJ0 C5 NC
47 IN MEM_EVENT_B_L (OC) N2 PA5 PF0 M7 G3_POWERON_L IN 47 LFBGA
PJ1 B8
47 BI SYS_ONEWIRE (OC) M4 PA6
eb M9 (4 OF 4) NC
PF1 P6 SMC_SYS_LED OUT 47
M12 PJ2 C10 NC
100 19 15 OUT PM_BATLOW_L (OC) N1 PA7 NC OMIT
PF2 R6 SMC_LID 47
M13 PJ3 C12 NC
NC B10 PB0 PF3 N6 NC L12 PJ4 A14 NC
SMC_RUNTIME_SCI_L A10 PB1 PF4 M6 PJ5 F15
PROTO-3:back to K75F 100 47 21 OUT NC A3 NC
SMC_ODD_DETECT D10 R5 BDV_BKL_PWM PJ6 J14
ot
101 42 IN PB2 PF5 OUT 84 100 K62 PROTO-2:NEW NC
K62 NEW:NOT USE,PULLED UP 47 IN
(See below) SMC_PB3 A11 PB3 PF6 P5 NC PJ7 K15 NC
97 51 IN SMC_HDD_OOB_TEMP B11 PB4 PF7 N5 NC PI0 N8 NC
NC C11 PB5
PG0 P9 NC PI1 N7 NC
N

K62 NEW:NOT USE,PULLED UP IN

SMC_PB6 A12 PB6
PG1 R9 SMC_SMS_INT IN 47 PI2 M5 NC
47 IN SMC_GFX_OVERTEMP_L D11 PB7
PG2 N9 (OC) SMB_BSA_DATA BI 49 PI3 L3 NC
53 OUT SMC_FAN_0_CTL G14 PC0 PG3 P8 (OC) SMB_BSA_CLK BI 49 PI4 K3 NC
53 OUT
SMC_FAN_1_CTL G15 PC1 PG4 R8 (OC) SMB_A_S3_DATA BI 49 PI5 H3 NC
G13 PC2 PG5 M8 (OC) SMB_A_S3_CLK PI6 H4

P12 AVSS1
NC BI 49
NC

VSS
54 OUT SMC_FAN_3_CTL G12 PC3 PG6 P7 (OC) SMB_B_S0_DATA BI 49 PI7 G3 NC
53 IN SMC_FAN_0_TACH H14 PC4 PG7 R7 (OC) SMB_B_S0_CLK BI 49

SMC_FAN_1_TACH

R4
F13
A13
B4
D1
53 IN H15 PC5
PH0 E1 SMC_PROCHOT OUT 47 100
NC H13 PC6 R4910
PH1 F3 SMC_THRMTRIP OUT 47
54 IN SMC_FAN_3_TACH H12 PC7 1 2 0 CPU_PECI 11 21 100
PH2 K2 NC MF-LF 5% 402 1/16W 97 50 47 46 GND_SMC_AVSS
(IMON) 97 50 IN SMC_1V05_ISENSE M11 PD0 PECI PH3 C4 100 CPU_PECI_R R4911
(IMON) 97 50 IN SMC_1V05_VSENSE P11 PD1 PEVref PH4 D4 PVCCIO_S0_SMC_R 1 2 0 =PPVCCIO_S0_SMC 6 47
MF-LF 5% 402 1/16W
97 50 IN SMC_PCH_1V05_ISENSE R11 PD2 PEVSTP PH5 B3 100 PM_PECI_PWRGD_R
SMC_PCH_1V05_VSENSE N11 R4912 0
A 97 50

97 50
IN
IN SMC_GPU_ISENSE P10
PD3
PD4 1 C4910 MF-LF 5%
1 2
402 1/16W
PM_PECI_PWRGD 64 100
SYNC_MASTER=K62_JERRY SYNC_DATE=01/09/2011 A
97 50 SMC_GPU_VSENSE R10 PD5 0.1UF PAGE TITLE
IN
97 50 IN
SMC_DIMM_ISENSE N10 PD6 2
20%
10V
CERM
402
SMC
97 50 IN SMC_DIMM_VSENSE M10 PD7 DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

REVISION
SMC PB3: SMC_IG_THROTTLE_L for MG systems. R
Otherwise, TP/NC okay (was ISENSE_CAL_EN) 10.1.0
SMC PG1: SMS Interrupt can be active high or low, rename net accordingly.
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
If SMS interrupt is not used, pull up to SMC rail. PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
49 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 46 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

=PP3V3_G3H_SMC D
D SMC Reset "Button", Supervisor & AVREF Supply MISC. SIGNAL ALIASES
47 46 6

100 47 46 SMC_ONOFF_L R5020 10K 1 2

SMC_GFX_OVERTEMP_L MXM_ALERT_L 5% 1/16W MF-LF 402
47 46 77 48 46 43 SMC_TX_L R5021 10K 1 2
47 46 6
=PP3V3_G3H_SMC MAKE_BASE=TRUE
SMC_RX_L R5022 100K 1 2
5% 1/16W MF-LF 402
48 46 43
SMC_GFX_THROTTLE_L MXM_PWR_LEVEL 5% 1/16W MF-LF 402
46 77 46 SYS_ONEWIRE R5023 2.0K 1 2
MAKE_BASE=TRUE 5% 1/16W MF-LF 402
CPUIMVP_VR_ON SMC_DELAYED_PWRGD 48 46 SMC_TMS R5024 10K 1 2
46 64 100 5% 1/16W MF-LF 402
1 MAKE_BASE=TRUE 48 46 SMC_TDO R5025 10K 1 2

3
C5010 1 R5010 SMC_TDI R5026 10K 1 2
5% 1/16W MF-LF 402
1K 48 46
0.47UF V+ VIN 5% 1/16W MF-LF 402
10% 5%
48 46 SMC_TCK R5027 10K 1 2
6.3V U5010 1/16W
5% 1/16W MF-LF 402
SILK_PART=SMC RESET CERM-X5R 2
VREF-3.3V-VDET-3.0V
MF-LF
46 SMC_BIL_BUTTON_L R5028 10K 1 2
402 2 402 5% 1/16W MF-LF 402
46 SMC_BC_ACOK R5029 10K 1 2
DEVELOPMENT
NC 6
DFN
5 SMC_RESET_L 5% 1/16W MF-LF 402
MR1* (IPU)SN0903048 RESET* 46 48 100 R5030 10K
S5000 NC 7
MR2* (IPU)
OUT 100 46 19 SMC_ADAPTER_EN
USB_DEBUGPRT_EN_L R5031 10K
1

1
2

2
5% 1/16W MF-LF 402
46 43
5% 1/16W MF-LF 402
1 SM 2 100 SMC_MANUAL_RST_L 4 8 PP3V3_G3H_AVREF_SMC G3_POWERON_L R5034 10K 1 2
DELAY REFOUT 46 98 46

m
MIN_LINE_WIDTH=0.4 mm 5% 1/16W MF-LF 402
THRM MIN_NECK_WIDTH=0.1 mm
GND PAD VOLTAGE=3.3V UNUSED PORT 7 ANALOG SENSORS 46 SMC_SMS_INT R5032 10K 1 2
C5011 1

9
5% 1/16W MF-LF 402
0.01UF C5012 1 1
C5013 46 SMC_LID R5033 10K 1 2
10% 5% 1/16W MF-LF 402
0.01UF

co
3 4 16V
2
10uF
CERM 20% 10%
6.3V 16V
402
X5R 2 2 CERM 46 SMC_PA0 R5037 100K 1 2
603 402 5% 1/16W MF-LF 402
GND_SMC_AVSS 46 50 97 46 SMC_PB6 R5038 100K 1 2
MIN_LINE_WIDTH=0.4 mm
NTC020-CC1J-B260T MIN_NECK_WIDTH=0.1 mm 46 SMC_PE0 R5036 100K 1 2
5% 1/16W MF-LF 402
VOLTAGE=0V 5% 1/16W MF-LF 402

s.
MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.
51 47 6
=PP3V3_S0_SMC_LS
NOTE: Internal pull-ups are to VIN, not V+.
R5035
C 47 46 SMC_GFX_OVERTEMP_L 10K 1 2
C

ic
5% 1/16W MF-LF 402
R5044 10K
UNUSED TP/NC ALIASES 100 46 21 SMC_RUNTIME_SCI_L 1 2
5% 1/16W MF-LF 402

at
46 SMC_EXCARD_PWR_EN TP_SMC_EXCARD_PWR_EN
POWER BUTTON 46 SMS_ONOFF_L
MAKE_BASE=TRUE
TP_SMS_ONOFF_L
J5010 SILK_PART=PWR BTN MAKE_BASE=TRUE
PM_SLP_S3_L R5041 100K

em
1 2
53261-8602 46 SMC_RSTGATE_L TP_SMC_RSTGATE_L 100 63 46 36 32 26 19 5
5% 1/16W MF-LF 402
R5042 100K
SMC Crystal Circuit M-RT-SM
3 518S0665
MAKE_BASE=TRUE
100 63 46 19 5

100 63 46 32 19 5
PM_SLP_S5_L
PM_SLP_S4_L R5043 100K
1

1
2

2
5% 1/16W MF-LF 402

CRITICAL 5% 1/16W MF-LF 402

C5020 100 POWER_BUTTON_L 1
46 SMC_SYS_LED TP_SMC_SYS_LED
15PF MAKE_BASE=TRUE

97 46 SMC_XTAL 1 2 2 46 SMC_PB3 TP_SMC_PB3

MAKE_BASE=TRUE
5%

ch
CRITICAL 50V 4
1 CERM
Y5020 402
20.00MHZ
5X3.2-SM
2 C5021
DEVELOPMENT
S5010 SMC PROCHOT 3.3V LEVEL SHIFTING
15PF R5012
1 2
NTC020-CC1J-B260T
SMC_EXTAL SM 1K SMC_ONOFF_L =PP3V3_S0_SMC_LS

kS
97 46 1 2 1 2 46 47 100
OUT 51 47 6
5% 5%
50V 1/16W
CERM MF-LF
402 402
1 C5014 R5077 1 R5078 1
0.1UF 3.3K 470
20% 5%
10V 5%
3 4 2 CERM R5094 1/16W 1/16W
MF-LF MF-LF
3.3K

oo
402
100 65 11
CPU_PROCHOT_L 1 2 402 2 402
2 TO SMC
BI
Can be driven by VREG or CPU 5% SMC_PROCHOT_3_3_L OUT 46 100
SMC & MXM THERMTRIP LEVEL SHIFTING 1/16W

B SILK_PART=SYS POWER
MF-LF
402 CPU_PROCHOT_BUF B
3 CPRCHOT_R
6 3
MEM_EVENT
eb D
51 47 6
=PP3V3_S0_SMC_LS R5095 To PCH FROM SMC 2
Q5077 5 Q5077
0 Q5095 MMDT3904-X-G MMDT3904-X-G
1 MXM_THRMTRIP_L 1 2 PM_THRMTRIP_L 100 46 IN SMC_PROCHOT 5 G S SOT-363-LF SOT-363-LF
R5097 MXM_THRMTRIP
1
OUT 21 100 2N7002DW-X-G
SOT-363 1 4
30 6 =PPSPD_S0_MEM_A 10K R5096 5%
6 3 1/16W 4
5% 3.3K
1/16W MF-LF
D 5% D 402
ot
MF-LF
R50401 FROM MXM 402 2
1/16W
MF-LF
10K MXM_OVERT_L 2
2 402
5
Q5096 6
5% 77 G S G S
1/16W IN
Q5096 2N7002DW-X-G D
MF-LF 2N7002DW-X-G SOT-363 Q5095
402 2 1 4 2N7002DW-X-G
SOT-363
N

SOT-363
2 G S
FROM DIMMS
FROM SMC
31 30 MEM_EVENT_L
IN
46
SMC_THRMTRIP 1
IN
TO SMC
46 MEM_EVENT_A_L
MAKE_BASE=TRUE
46 6
=PPVCCIO_S0_SMC
TO/FROM SMC
1
R5087
46 MEM_EVENT_B_LI581 51 47 6 =PP3V3_S0_SMC_LS 5%
51
1/16W
1 MF-LF
R5086 R5088 2 402
3.3K
C_THRMTRP1 1
0 2
5%
100 11 IN
CPU_THRMTRIP_L 1/16W
MF-LF 5%
1/16W
2 402 MF-LF
C_THRMTRP 402
R5085
A FROM CPU
1
3.3K
2 C_THRMTRP_L 6 3 SYNC_MASTER=K62_JERRY SYNC_DATE=01/09/2011 A
PAGE TITLE
5%
1/16W
MF-LF
402
2
Q5086
MMDT3904-X-G
5
Q5086 SMC Support
SOT-363-LF MMDT3904-X-G DRAWING NUMBER SIZE
1 4 SOT-363-LF
Apple Inc. 051-8442 D
REVISION
R
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
50 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 47 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D LPC+SPI Connector D
FRANK CONNECTOR
CRITICAL
LPCPLUS:YES
J5100
55909-0374
M-ST-SM
6 =PP3V3_G3H_LPCPLUS 31 32

6 =PP5V_S0_LPCPLUS
1 2 LPC_CLK33M_LPCPLUS IN 27 94

94 46 18 BI LPC_AD<0> 3 4 LPC_AD<2> BI 18 46 94

94 46 18 BI LPC_AD<1> 5 6 LPC_AD<3> BI 18 46 94
7 8

94 48 IN SPI_ALT_MOSI 9 10 SPIROM_USE_MLB OUT 21 48 94

94 48 OUT SPI_ALT_MISO 11 12 SPI_ALT_CLK IN 48 94

m
94 46 18 IN LPC_FRAME_L 13 14 SPI_ALT_CS_L IN 48 94

100 46 19 15 OUT PM_CLKRUN_L 15 16 LPC_SERIRQ BI 18 46

47 46 OUT SMC_TMS 17 18 LPC_PWRDWN_L IN 19 46 100

100 27 DEBUG_RESET_L 19 20 SMC_TDI 46 47

co
IN OUT
47 46 OUT SMC_TDO 21 22 SMC_TCK OUT 46 47

46 IN SMC_TRST_L 23 24 SMC_RESET_L OUT 46 47 100

46 OUT SMC_MD1 25 26 SMC_NMI OUT 46

47 46 43 IN SMC_TX_L 27 28 SMC_RX_L OUT 43 46 47

29 30 LPCPLUS_GPIO

s.
OUT 21

33 34

C C

ic
516S0573

at
em
Alternate SPI ROM Support

ch
48 6 =PP3V3_S5_LPCPLUS
55 6 =PP3V3_S5_ROM LPCPLUS:YES
48 6 =PP3V3_S5_LPCPLUS
1 C5144
R5144 1 0.1UF
20%
20K LPCPLUS:YES 10V
2 CERM R5140 1

kS
5% 402 100K
1/16W 5%
MF-LF 1/16W
402 2 U5100 MF-LF
402 2
NC7SB3157P6XG
1 B1 SC70 SEL 6
94 55 OUT SPI_MLB_CS_L SPIROM_USE_MLB 21 48 94
MAKE_BASE=TRUE
1

oo
2 GND VCC 5 LPCPLUS:YES
R5145
B 94 48 OUT SPI_ALT_CS_L 3
0
4 94 SPI_CS0_L 1
0 2 SPI_CS0_R_L IN 18 94
B
B0 A
5% PLACEMENT_NOTE=Place near U1800
Pull-up on debug card VER 1 1/16W
eb MF-LF
CRITICAL 402

LPCPLUS:NO
R5146
0
ot
1 2
5% PLACEMENT_NOTE=PLACE NEXT TO U5100
1/16W
MF-LF
402
N

SPI Bus Series Resistance Option

LPCPLUS:YES
R5156
33
94 48 OUT SPI_ALT_CLK 1 2 SPI_CLK_R IN 18 55 94

PLACEMENT_NOTE=Place next to R6150 5%

1/16W
LPCPLUS:YES
MF-LF
402 R5157
33
94 48 OUT SPI_ALT_MOSI 1 2 SPI_MOSI_R IN 18 55 94

LPCPLUS:YES 5%
1/16W
PLACEMENT_NOTE=Place next to R6152
MF-LF
R5158 402
33
94 48 IN SPI_ALT_MISO 1 2 SPI_MISO OUT 18 55 94

PLACEMENT_NOTE=Place next to R6105 5%

A 1/16W
MF-LF
402 SYNC_MASTER=K62_AARON SYNC_DATE=11/30/2009 A
PAGE TITLE

LPC+SPI Debug Connector

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

PCH R5208 1 1
R5209 MEMORY A DIMMS R5202 1 1
R5203 SMC R52701 1
R5271 ALS
U1800
2.2K
5%
2.2K
5% J3100-A/B
PCH 8.2K
5%
8.2K
5% U4900
4.7K
5% 5%
4.7K
(WRITE: 0X52 READ: 0X53)
1/16W 1/16W U1800 1/16W 1/16W 1/16W 1/16W
(MASTER) MF-LF MF-LF (DIMM0: WRITE: 0XA0 READ: 0XA1) MF-LF MF-LF (MASTER) MF-LF MF-LF
402
2 2
402 (MASTER) 402
2 2
402 402 2 2 402
(DIMM2: WRITE: 0XA2 READ: 0XA3)

D 97 18 SMBUS_PCH_CLK
MAKE_BASE=TRUE
=I2C_SODIMMA_SCL 30
97 18 SML_PCH_0_CLK
MAKE_BASE=TRUE
46 SMB_A_S3_CLK 97 SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
=SMB_ALS_SCL 44
D
97 18 SMBUS_PCH_DATA =I2C_SODIMMA_SDA 30 46 SMB_A_S3_DATA 97 SMBUS_SMC_A_S3_SDA =SMB_ALS_SDA 44
MAKE_BASE=TRUE 97 18 SML_PCH_0_DATA MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEMORY B DIMMS
J3200-A/B
(DIMM1: WRITE: 0XA4 READ: 0XA5)
(DIMM3: WRITE: 0XA6 READ: 0XA7)
SMC "MANAGEMENT" SMBUS (BUS 1)
USES INTERNAL SMC CONTROLLER CHANNEL 1 ONLY
=I2C_SODIMMB_SCL 31
THIS PAGE DIFFERENT BETWEEN K60 AND K62. 6 =PP3V3_S0_SMBUS_SMC_MGMT
=I2C_SODIMMB_SDA 31

XDP (PCH)
J2550 R5290 1 1
R5291 PANEL TEMP SENSOR
SMC 2.2K 2.2K TMP421 ON TCON BOARD VIA J9002
MIKEY U4900 5%
1/16W
5%
1/16W
(SLAVE)

m
49 25 =SMBUS_XDP_SCL
U6806
(WRITE: 0X72 READ: 0X73)
SMC SLAVE SMBUS "2" CONNECTIONS (MASTER) MF-LF
402 2
MF-LF
2 402
(WRITE: 0X9E READ: 0X9F)

=SMBUS_XDP_SDA USES INTERNAL SMC CONTROLLER CHANNEL 2 ONLY (NO CONNECTIONS, JUST PULLUP)
49 25 46 SMB_MGMT_CLK 97 SMBUS_SMC_MGMT_SCL SMB_DP_TCON_SLA_SCL 82
MAKE_BASE=TRUE
=I2C_AUDIO_SCL 62 6 =PP3V3_S0_SMBUS_SMC_BSA
46 SMB_MGMT_DATA 97 SMBUS_SMC_MGMT_SDA SMB_DP_TCON_SLA_SDA 82

co
MAKE_BASE=TRUE
=I2C_AUDIO_SDA 62

1 1
DISPLAY TCON
SMC R5280 R5281 PARADE ON TCON BOARD VIA J9002
100K 100K
U4900 5% 5% (SLAVE)
XDP (CPU) CK505 1/16W 1/16W
(TBD WRITE: 0X1A READ: 0X1B)

s.
(SLAVE) MF-LF MF-LF
J2500 U2600 402 2 2 402 (TO READ VENDOR ID
(WRITE: 0XD2 READ: 0XD3) AND PANEL ID)
46 SMB_BSA_CLK 97 SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE TCON ALSO HAS

C =SMBUS_XDP_SCL =SMBUS_CK505_SCL SMB_BSA_DATA SMBUS_SMC_BSA_SDA MASTER BUS TO LUT ROM

ic
49 25 26 46 97
MAKE_BASE=TRUE AND EDID ROM.
49 25 =SMBUS_XDP_SDA =SMBUS_CK505_SDA 26

at
MEM VREF MARGIN A
U2900
SMC "B" SMBUS CONNECTIONS
BUS B CAN USE EITHER INTERNAL SMC CHANNEL 0 OR 1, K60/62 CHOOSES 0
(WRITE: 0X5C READ: 0X5D)

em
SPTX BLC MICRO 6 =PP3V3_S0_SMBUS_SMC_B
VIA J602 =I2C_VREFMRGN_A_SCL 28

(WRITE: 0X6E READ: 0X6F)

=I2C_VREFMRGN_A_SDA 28
AC/DC PS TEMPS DISPLAY TCON TO SPTX OR O2M BLC
SMC R5260 1 1
R5261 EMC1403-[1,2] : ACDC THRU J600
(WRITE: 0X98 OR 0X9A, READ: 0X99 OR 0X9B)
=SMB_BLC_PCH_SCL 2.0K 2.0K
6 U4900 5% 5%
1/16W 1/16W 3 SENSE POINTS - PRIMARY, SECONDARY, AMB
(MASTER) =PP3V3_S0_SMBUS

ch
=SMB_BLC_PCH_SDA MF-LF MF-LF 49 6
6
MEM VREF MARGIN B 402 2
2 402
1
U2910 46 SMB_B_S0_CLK 97 SMBUS_SMC_B_S0_SCL =SMB_ACDC_SCL 6 R5210 1 R5211 BLC MICRO
MAKE_BASE=TRUE
NEED TO ADD PCH_SDA
(WRITE: 0X7C READ: 0X7D)
46 SMB_B_S0_DATA 97 SMBUS_SMC_B_S0_SDA =SMB_ACDC_SDA 6
DISPLAY TCON 2.2K
5% 5%
2.2K VIA J602
(SLAVE)
1/16W 1/16W
ISOLATION CIRCUITRY MAKE_BASE=TRUE VIA J9002 MF-LF MF-LF (WRITE: 0X6E READ: 0X6F)
=I2C_VREFMRGN_B_SCL 28

kS
402 2
(MASTER) 2 402
=I2C_VREFMRGN_B_SDA 28
AC/DC PS POWER 97
82
INA219: ACDC THRU J600 =SMB_DP_TCON_SDA SMB_BLC_TCON_SDA OUT 6
MAKE_BASE=TRUE 97
(WRITE: 0X80, READ: 0X81) =SMB_DP_TCON_SCL SMB_BLC_TCON_SCL BI 6
MAKE_BASE=TRUE 82

DP SDRV "A" OUTPUT VOLTAGE, CURRENT, POWER

oo
NOTE: DISPLAY TCON HAS 4.7K PU.
U9310, PS8301 NOTE: SPTX BLC HAS 4.7K PU.
NOTE: O2MICRO BLC HAS NO PU.
(WRITE: 0X94, READ: 0X95)

B B
=I2C_DPSDRVA_SCL 85
T29 I2C CONNECTIONS
=I2C_DPSDRVA_SDA SMC "0" SMBUS CONNECTIONS
85
eb
USES INTERNAL SMC CONTROLLER CHANNEL 0 ONLY 6 =PP3V3_S0_T29I2C I2C BUS PULL-UP RAIL MUST REFLECT
WHEN USB POWER (VBUS) IS VALID.
6 =PP3V3_S0_SMBUS_SMC_0
T29 T29
DP SDRV "B" Also reserve 0x56 and 0x32 per spec
T29 PORT A MCU
U9510, PS8301 T29 IC R5230 1 1
R5231
MXM TEMP 4.7K 4.7K
ot
1 1 U9330
(WRITE: 0XB4, READ: 0XB5) SMC R5250 R5251 U9700 5% 5%
2.2K 2.2K GPU ON CARD - J8400 1/16W 1/16W (WRITE: 0X26 READ: 0X27)
U4900 5% 5% (MASTER) MF-LF MF-LF
1/16W 1/16W 402 402
=I2C_DPSDRVB_SCL 87
NV INSIDE (WRITE: 0X9E READ: 0X9F) 2 2
(MASTER) MF-LF MF-LF
EMC1402 ON AMD MXM CARD (WRITE: 0X98 READ: 0X99)
402 2 2 402 99 89 I2C_T29_SCL =I2C_T29AMCU_SCL 85
N

=I2C_DPSDRVB_SDA 87 MAKE_BASE=TRUE
46 SMB_0_S0_CLK 97 SMBUS_SMC_0_S0_SCL =SMB_MXM_THRM_SCL 77
MAKE_BASE=TRUE 99 89 I2C_T29_SDA =I2C_T29AMCU_SDA 85
MAKE_BASE=TRUE
46 SMB_0_S0_DATA 97 SMBUS_SMC_0_S0_SDA =SMB_MXM_THRM_SDA 77
MAKE_BASE=TRUE

EMC1414: U5520
DEV: CPU D,CPU HTSK
(WRITE: 0X78 READ: 0X79)
T29 PORT B MCU
U9530
PCH "SML 1" CONNECTIONS EMC1428: U5500
PROD: AMB,L-SKIN,R-SKIN,ODD,
(WRITE: 0X24 READ: 0X25)
LCD,CPU PROX,MXM TEMPS
49 6 =PP3V3_S0_SMBUS (WRITE: 0x92 READ:0x93) =I2C_T29BMCU_SCL 87

=SMB_SNS1_SCL 52
=I2C_T29BMCU_SDA 87
NOSTUFF NOSTUFF
=SMB_SNS1_SDA 52

PCH (FOR TEMP) R5204 1 1

R5205
A U1800
8.2K
5%
1/16W
5%
8.2K
1/16W
SYNC_MASTER=K62_MARK SYNC_DATE=01/09/2011 A
(SLAVE) MF-LF MF-LF
PAGE TITLE

(WRITE: 0X86 READ: 0X89)

402 2 2 402 R5206
0
PCIE MINI-CARD SMBUS CONNECTIONS
97 18 SML_PCH_1_CLK 1 2 DRAWING NUMBER SIZE
MAKE_BASE=TRUE
5%
X18 WI-FI MODULE 051-8442 D
97 18 SML_PCH_1_DATA
MAKE_BASE=TRUE
1/16W
MF-LF R5207 TMP106: J3400
Apple Inc. REVISION
402 0 R
1 2 (WRITE: 0X90 READ: 0X91) 10.1.0
5%
=SMB_MINI_SCL
NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/16W 33
MF-LF THE INFORMATION CONTAINED HEREIN IS THE
402 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
=SMB_MINI_SDA 33 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
52 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
THE PCH address is user programmable by SPI ROM IV ALL RIGHTS RESERVED 49 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VDD 1.5V CPU VCC (VCORE) GPU MXM
SENSE RESISTOR CURRENT (IC5R) AND VOLTAGE (VC5R) SENSE IMON CURRENT (IC0C) AND VOLTAGE (VC0C) SENSE SENSE RESISTOR CURRENT (IG0R) AND VOLTAGE (VG0R) SENSE
OMIT_TABLE IMAX = 8.25A
R5300 R5330
PP1V5_S0_CPU_MEM_SNS 4.53K CRITICAL IMAX = 8.25A
0.002 6
=PPVCORE_S0_CPU SMC_VCORE_VSENSE
1% CPU_1V5_SENSE 65 16 13 6 1 2
OUT 46 97
R5361 PP12V_S0_MXM_SNS
1/4W
MF-LF R5301 1% 0.002 6

1206 4.53K2
1/16W
MF-LF
1
C5330 1%
1/4W
6 =PP1V5_S0_PWR 1 2 1 SMC_CPU_1V5_VSENSE OUT 46 97 402 0.22UF
20% MF-LF R5360
3 4 1% OMIT_TABLE 6.3V 1206 18.2K2 SMC_GPU_VSENSE
1/16W
PLACEMENT_NOTE=PLACE C5330 NEAR SMC
PLACEMENT_NOTE=PLACE R5330 NEAR CPU
2 X5R PLACE C CLOSE TO SMC 6 =PP12V_S0_MXM_PWR 1 2 1 OUT 46 97

52 50 6 =PP3V3_S0_SENSE MF-LF
402
1 C5301 OMIT_TABLE
402
GND_SMC_AVSS 46 3 4 1%
0.22UF 47 50 97 1/16W 1
CPU_1V5_SENSE
PLACEMENT_NOTE=PLACE C5301 NEAR SMC
20%
6.3V
R5331 MF-LF
402
R5362 1 C5362
C5300 PLACEMENT_NOTE=PLACE R5301 NEAR CPU 2 X5R 9.31K2 =PP3V3_S0_SENSE 6.04K 0.22UF
1 SNS_PS_VCORE_ISNS 52 50 6

D 0.22UF 402
GND_SMC_AVSS 1%
1%
1/16W
MF-LF
20%
6.3V
2 X5R D

3
1 2
V+
46 47 50 97
1/16W
MF-LF
C5331 1 C5360 2 402 402
402 0.01UF 0.22UF GND_SMC_AVSS 46 47 50 97
20% CPU_1V5_SENSE 1 2 20%
6.3V U5300 50 6 =PP5V_S0_ISENSE 6.3V PLACEMENT_NOTE=PLACE R5360 NEAR CPU
X5R R5302 2 X5R

3
PLACEMENT_NOTE=PLACE C5362 NEAR SMC
402 INA210 4.53K2 20% 402
97 SNS_CPU_1V5_N 5 IN- OUT 6
SC70 97 SMC_CPU_1V5_ISENSE_R 1 SMC_CPU_1V5_ISENSE OUT 46 97 16V V+
CERM
CPU_1V5_SENSE 1% OMIT_TABLE 402 U5360 R5363
SNS_CPU_1V5_P 4 IN+ REF 1
1/16W
MF-LF
1 C5302 R5333 INA210 4.53K
97
402 0.22UF 10K U5330 97 SNS_I_MXM_N 5 IN- SC70 OUT SMC_GPU_R
6 1 2 SMC_GPU_ISENSE OUT 46 97
20%
6.3V 98 65 IN VR_CPU_IMON 1 2 98 97 VR_ISNS_VCORE_P 1 5 OPA348 R5332
GND PLACEMENT_NOTE=PLACE C5302 NEAR SMC 2 X5R
1% SC70-5 5.1K 2 CRITICAL 1%
353S2073
PLACEMENT_NOTE=PLACE R5302 NEAR SMC 402 1/16W 4 1 SMC_VCORE_ISENSE 97 SNS_I_MXM_P 4 IN+ REF 1
1/16W
MF-LF
1 C5363

2
IMON MAX = 0.9V MF-LF OUT 46 97
402 0.22UF
GAIN = 200V/V GND_SMC_AVSS 46 47 50 97 402 5% 20%
VR_ISNS_VCORE_N 3 CRITICAL 1/16W 1 6.3V
2 MF-LF C5332 GND 2 X5R
IMAX = 2.79V 402 0.22UF 402

2
1 10%
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD

THE NO_1V05_PCH_SENSE,
NO_CPU_VCCSA_SENSE, AND
R5334 PLACEMENT_NOTE=PLACE C5332 NEAR SMC 2 6.3V
CERM-X5R
NO_CPU_1V5_SENSE 10K PLACEMENT_NOTE=PLACE R5332 NEAR SMC
402 GND_SMC_AVSS
TABLE_5_ITEM

BOMOPTIONS SHOULD IDEALLY 1% 46 47 50 97

1/16W

m
104S0018 1 RES,2 MILLIOHM,1206 R5300 CPU_1V5_SENSE NEVER BE USED AS TOTAL CPU POWER MF-LF GND_SMC_AVSS
SENSING REQUIRES ALL 46 47 50 97
TABLE_5_ITEM

3 SENSORS. 2 402
101S0414 1 RES,0 OHM,1206,20 MILLIOHM MAX R5300 NO_CPU_1V5_SENSE
TABLE_5_HEAD

TABLE_5_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

132S0080 2 CAP,0.22UF,402 C5301,C5302 CPU_1V5_SENSE

co
TABLE_5_ITEM

TABLE_5_ITEM

114S0312 1 RES,MTL FILM,1/16W,9.31K,0402 R5331 CPUVCORE-3PH

116S0004 2 RES,0 OHM,402 C5301,C5302 NO_CPU_1V5_SENSE
TABLE_5_ITEM

CPU VCCSA
114S0345 1 RES,MTL FILM,1/16W,21K,0402 R5331 CPUVCORE-4PH
DIMM VDD 1.5V (LIKELY DEVELOPMENT ONLY)
SENSE RESISTOR CURRENT (IM0R) AND VOLTAGE (VM0R) SENSE
SENSE RESISTOR CURRENT (ICSR) AND VOLTAGE (VCSR) SENSE

s.
OMIT_TABLE
R5310 IMAX = 8.25A CPU VAXG R5370
IMAX = 8.25A

0.002 IMON CURRENT (IC0G) AND VOLTAGE (VC0G) SENSE 0.002 PP1V5_S3_MEM_SNS
C PPVCCSA_S0_INPUT_SNS 6 1%
6
DIMM_1V5_SENSE C

ic
1% CPU_VCCSA_SENSE VAXG 1/4W
1/4W
MF-LF R5311 R5340 MF-LF R5371
1206 13 6 =PPVCCSA_S0_CPU 4.53K2 4.53K =PP1V5_S3_MEM_PWR 1
1206
2 1
4.53K2 SMC_DIMM_VSENSE
69 6 =PPVCCSA_S0_INPUT_PWR 1 2 1 SMC_VCCSA_VSENSE OUT 46 97 65 17 13 6 =PPVAXG_S0_CPU 1 2 SMC_VAXG_VSENSE OUT 46 97
6 OUT 46 97

3 4 1% OMIT_TABLE 3 4 1% OMIT_TABLE

at
OMIT_TABLE 1%
1/16W
1/16W
MF-LF 1 C5311 1/16W 1
C5340 =PP3V3_S0_SENSE MF-LF 1 C5371
52 50 6 =PP3V3_S0_SENSE 402
MF-LF
402 0.22UF 52 50 6 402
0.22UF
CPU_VCCSA_SENSE 0.22UF 20% DIMM_1V5_SENSE PLACEMENT_NOTE=PLACE R5371 NEAR CPU 20%
20% 6.3V
6.3V
2
C5310 PLACEMENT_NOTE=PLACE C5311 NEAR SMC
PLACEMENT_NOTE=PLACE R5311 NEAR CPU
6.3V
2 X5R
PLACEMENT_NOTE=PLACE C5340 NEAR SMC
PLACEMENT_NOTE=PLACE R5340 NEAR CPU
X5R
402 GND_SMC_AVSS C5370 PLACEMENT_NOTE=PLACE C5372 NEAR SMC
2 X5R
402
402 46 47 50 97
0.22UF

em
0.22UF GND_SMC_AVSS 46 VAXG GND_SMC_AVSS

3
46 47 50 97
R5341
3

1 2 47 50 97 1 2
V+ 21K V+
20% CPU_VCCSA_SENSE
1 2 SNS_PS_VAXG_ISNS 20% DIMM_1V5_SENSE
6.3V
X5R U5310 R5312 1% VAXG 6.3V
X5R U5370 R5372
402 INA210 4.53K2
1/16W
MF-LF
C5341 402 INA210 4.53K2 SMC_DIMM_ISENSE
97 SNS_VCCSA_N 5 IN- SC70
OUT 6 97 SMC_VCCSA_ISENSE_R 1 SMC_VCCSA_ISENSE 46 97 402 0.01UF 97 SNS_DIMM_1V5_N 5 IN- OUT97 6 SMC_DIMM_1V5_R 1
SC70 OUT 46 97
OUT
1% OMIT_TABLE 50 6 =PP5V_S0_ISENSE 1 2 DIMM_1V5_SENSE 1% OMIT_TABLE
CPU_VCCSA_SENSE
1/16W 1 C5312 1/16W 1 C5372

ch
97 SNS_VCCSA_P 4 IN+ REF 1 MF-LF 20% 97 SNS_DIMM_1V5_P 4 IN+ REF 1 MF-LF
402 0.22UF 16V 402 0.22UF
20% CERM 20%
6.3V 6.3V
GND PLACEMENT_NOTE=PLACE C5312 NEAR SMC
2 X5R VAXG 402 GND 2 X5R
PLACEMENT_NOTE=PLACE R5312 NEAR SMC VAXG 402
402 R5343 353S2073 GND_SMC_AVSS 46

2
353S2073 U5340
2

47 50 97
GAIN = 200V/V GND_SMC_AVSS 10K OPA348
VAXG GAIN = 200V/V
46 47 50 97 98 65 IN VR_AXG_IMON 1 2 VR_ISNS_VAXG_P 1 5
R5342
SC70-5

kS
IMON MAX = 0.9V
1%
1/16W 4 1
5.1K 2 SMC_VAXG_ISENSE OUT 46 97
MF-LF TABLE_5_HEAD

TABLE_5_HEAD

402 5% OMIT_TABLE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION 98 97 VR_ISNS_VAXG_N 3 CRITICAL 1/16W 1 C5342 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
2 MF-LF
0.22UF
TABLE_5_ITEM

TABLE_5_ITEM

VAXG IMAX = 2.79V 402

104S0018 1 RES,2 MILLIOHM,1206 R5310 CPU_VCCSA_SENSE 1 10% 132S0080 2 CAP,0.22UF,402 C5371,C5372 DIMM_1V5_SENSE
R5344 PLACEMENT_NOTE=PLACE C5342 NEAR SMC 2 6.3V
CERM-X5R
TABLE_5_ITEM

10K
TABLE_5_ITEM

116S0004 2 RES,0 OHM,402 C5371,C5372 PRODUCTION

oo
101S0414 1 RES,0 OHM,1206,20 MILLIOHM MAX R5310 NO_CPU_VCCSA_SENSE PLACEMENT_NOTE=PLACE R5342 NEAR SMC 402
1%
TABLE_5_ITEM
1/16W
132S0080 2 CAP,0.22UF,402 C5311,C5312 CPU_VCCSA_SENSE MF-LF GND_SMC_AVSS 46 47 50 97
2 402
B 116S0004 2 RES,0 OHM,402 C5311,C5312 NO_CPU_VCCSA_SENSE
TABLE_5_ITEM

B
PCH 1.05V
eb TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

SENSE RESISTOR CURRENT (IN1R) AND VOLTAGE (VN1R) SENSE 132S0080 2 CAP,0.22UF,402 C5340,C5342 VAXG
TABLE_5_ITEM

TABLE_5_ITEM

OMIT_TABLE 116S0004 2 RES,0 OHM,402 C5340,C5342 NO_VAXG

R5320 IMAX = 8.25A
ot
NOTE: TOTAL CPU POWER = VC0C*IC0C
0.002 PP1V05_S0_PCH_SNS 6
+ VC5R*IC5R
1% 1V05_PCH_SENSE + VCSR*ICSR
+ VC0G*IC0G
1/4W
MF-LF
1206
R5321
4.53K2
1.05V FOR CPU VCCIO, CPU VCCSA & PCH 1.05V where
+ VV1R*IC1R
6 =PP1V05_S0_PCH_PWR 1 2 1 SMC_PCH_1V05_VSENSE OUT 46 97 IMON CURRENT (IV1R) AND VOLTAGE (VV1R) SENSE IC1R = IV1R - IN1R - ICSR
N

3 4 1% OMIT_TABLE
1/16W R5350
52 50 6 =PP3V3_S0_SENSE MF-LF
402
1 C5321 =PP1V05_S0_PWR
4.53K
SMC_1V05_VSENSE
1V05_PCH_SENSE 0.22UF 6 1 2
OUT 46 97
PLACEMENT_NOTE=PLACE C5321 NEAR SMC
20%
6.3V 1%
C5320 PLACEMENT_NOTE=PLACE R5321 NEAR CPU 2 X5R
402
1/16W
MF-LF
1
C5350
0.22UF GND_SMC_AVSS 46 402 0.22UF
20%
3

47 50 97
1 2 6.3V
PLACEMENT_NOTE=PLACE C5350 NEAR SMC 2 X5R
V+ PLACEMENT_NOTE=PLACE R5350 NEAR CPU
402
20% 1V05_PCH_SENSE GND_SMC_AVSS 46 47 50 97
6.3V
X5R U5320 R5322
402 INA210 4.53K2
97 SNS_1V05_PCH_N 5 IN- SC70 OUT 6 SNS_1V05_PCH_R 1 SMC_PCH_1V05_ISENSE OUT 46 97

1V05_PCH_SENSE 1% OMIT_TABLE C5351

97 SNS_1V05_PCH_P 4 IN+ REF 1
1/16W
MF-LF
1 C5322 0.01UF
402 0.22UF =PP5V_S0_ISENSE 1 2
20% 50 6
6.3V
GND 2 X5R
20%
PLACEMENT_NOTE=PLACE C5322 NEAR SMC 402 16V
353S2073
2

PLACEMENT_NOTE=PLACE R5322 NEAR SMC CERM

A GAIN = 200V/V GND_SMC_AVSS 46 47 50 97

R5353
402
SYNC_MASTER=K62_MARK SYNC_DATE=01/09/2011 A
1K U5350 PAGE TITLE

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_HEAD
98 68 IN P1V05_IMON
IMON MAX = 2.7V
1
5%
2 VR_ISNS_P_1V05 1 5 OPA348
SC70-5 R5352
5.1K 2
CPU/PCH/GPU POWER SENSE
1/16W 4 1 SMC_1V05_ISENSE OUT 46 97 DRAWING NUMBER SIZE
TABLE_5_ITEM

MF-LF
104S0018 1 RES,2 MILLIOHM,1206 R5320 1V05_PCH_SENSE 402
VR_ISNS_N_1V05 3
5%
1/16W Apple Inc. 051-8442 D
CRITICAL 1 C5352 REVISION
TABLE_5_ITEM

2 MF-LF
101S0414 1 RES,0 OHM,1206,20 MILLIOHM MAX R5320 NO_1V05_PCH_SENSE IMAX = 2.7V 402 0.22UF R
10.1.0
10%
2 6.3V
TABLE_5_ITEM

132S0080 2 CAP,0.22UF,402 C5321,C5322 1V05_PCH_SENSE PLACEMENT_NOTE=PLACE C5352 NEAR SMC

PLACEMENT_NOTE=PLACE R5352 NEAR SMC
CERM-X5R NOTICE OF PROPRIETARY PROPERTY: BRANCH
402
TABLE_5_ITEM

THE INFORMATION CONTAINED HEREIN IS THE

116S0004 2 RES,0 OHM,402 C5321,C5322 NO_1V05_PCH_SENSE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
GND_SMC_AVSS 46 47 50 97 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
53 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 50 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

m
co
s.
HDD OOB TEMPERATURE SENSING
C C

ic
6 =PP12V_S0_SENSE

1 1
C5400
R5400

at
110K 0.1UF
20%
1% 16V
1/16W 2 CERM
MF-LF
402
Trip point 1.0V. 603
2 =PP3V3_S0_SMC_LS
51 47 6 =PP3V3_S0_SMC_LS 100 51 HDD_OOB_1V00_REF 6 47 51

em
Pull up 1.5V. 1
R5401 1
1
R5405
FROM DRIVE: C5401 1K
1 10K
LOW: 0.0V TO 0.3V R5402
180K
1%
1/16W
0.1UF
20%
8
U5400 5%
1/16W
HIGH: 1.2V TO 2.0V MF-LF 2 16V
LM393 MF-LF
5% CERM 2 2 402
1/16W
402
2 603 SOI-HF
MF-LF V+
402 1 SMC_HDD_OOB_TEMP OUT
2
R5403 46 97

ch
3.3K 3 GND
101 97 42 IN HDD_OOB_TEMP_FILT 1 2 97 HDD_OOB_TEMP_R
CRITICAL
1.5V 5% 4
R5404 1 1/16W
MF-LF
150K 402
5%
1/16W NOSTUFF

kS
MF-LF 1
402
2
R5406
0
5%
1/16W
MF-LF

R5407 8
U5400 2 402

USE_HDD_OOB_L 1
10K
2 USE_HDD_OOB_L_R 6 LM393
SOI-HF

oo
100 20 IN
5% V+
1/16W 7
MF-LF USE_HDD_OOB_PD
B 402
100 51
HDD_OOB_1V00_REF
eb 5 GND

4
CRITICAL B
DRIVE ACTIVE = VALID SIGNAL PROTOCOL BETWEEN 0-2.0V.
DRIVE ASLEEP = HDD DRIVES HDD_OOB_TEMP LOW
DRIVE ABSENT = OOB IS PULLED HIGH UNLESS PCH DETERMINES SSD PRESENT AND DRIVES USE_HDD_OOB_L LOW WHICH THEN PULLS HDD_OOB_TEMP LOW.

NOTE: WILL BE CONNECTED TO SATA PWR CONNECTOR PIN 11

ot
THIS PIN IS ORIGINALLY INTENDED FOR HDD LED OUTPUT,
AND ALSO FOR HDD STAGGERED PIN UP (FLOATING) OR IMMEDIATE SPIN-UP (GROUND).
BOTH FUNCTIONS NOT USED.
N

A SYNC_MASTER=K62_MARK SYNC_DATE=01/09/2011 A
PAGE TITLE

HDD OOB SENSE

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

SILK_PART=AMB TEMP MXM HTSK TEMP SENSOR SILK_PART=MXM HSK

AMBIENT TEMP SENSOR MXM
SNS T1: PRODUCTION TEMP SENSOR IC L5500
J5500
53780-8603 FERR-220-OHM
L5540
MXM
J5530
53398-8602
FERR-220-OHM M-RT-SM M-ST-SM
4 SNS_T1_5_P 1 2 3
52 50 6 =PP3V3_S0_SENSE 97 52 SNS_T1_1_P 1 2 97 52

MXM 0402
0402
1
R5500 1R5501 1R5502 1 C5501 101 97 SNS_AMB_P 1 1 C5514 MXM 97 SNS_MXM_P 1
C5500 1 6.81K 10K 20K 0.0022UF L5501 101 97 SNS_AMB_N 2 0.0022UF L5541 97 SNS_MXM_N 2

16
1% 5% 10% 10%
CRITICAL 1UF 1/16W
5%
1/16W 1/16W 2 50V FERR-220-OHM 3 2 CERM
50V FERR-220-OHM
10% CERM
10V MF-LF MF-LF MF-LF
VDD X5R 2
2 402 2 402
2 402 97 52 SNS_T1_1_N 402 1 2 97 52 SNS_T1_5_N 402 1 2 4

D U5500
EMC1428-7
402-1
0402 5 0402
CRITICAL D
CRITICAL 518S0678
QFN 518S0677 Place Hsk sensor conn top side next MXM or CPU
97 52 SNS_T1_1_P 1 DP1 ALERT* 7 SNS_T1_ALERT_L
AMB (TA0p) 2
97 52 SNS_T1_1_N DN1 SILK_PART=ODD TEMP
SYS_SHND* 6 SNS_T1_ADDR
SNS_T1_2_P 3 ODD TEMP SENSOR J5510 CPU PROXIMITY TEMP SENSOR
ODD (TO0p)
97 52 DP2/DN3
SMDATA 11 =SMB_SNS1_SDA BI 49 52
L5510 53780-8602
97 52 SNS_T1_2_N 4 DN2/DP3 FERR-220-OHM
M-RT-SM SNS_T1_6_P
SMCLK 12
97 52
10 =SMB_SNS1_SCL IN 49 52 SNS_T1_2_P 1 2 3
97 52 SNS_T1_4_P DP4/DN5 97 52
LEFT SKIN (TS2p) 9 0402 NOSTUFF
97 52 SNS_T1_4_N DN4/DP5 TRIP/SET 5 SNS_T1_TRIPSET 1 C5511 3
Set trip point to 125 C. 0.0022UF
101 97 SNS_ODD_P 1
Q5500
1 C5504
CPU PROX (TC0p)
97 52 SNS_T1_6_P 15 DP6/DN7 NC 13 NC 10% L5511 101 97 SNS_ODD_N 2
MMBT3904G 1 0.0022UF
10%
97 52 SNS_T1_6_N 14 DN6/DP7 2
50V
CERM
FERR-220-OHM SOT23 50V
2 CERM
402
97 52 SNS_T1_2_N 1 2 4 2 402

2 2 GND THRM_PAD 0402 97 52 SNS_T1_6_N

OMIT OMIT CRITICAL

17
XW5504 SM
XW5505 518S0698 Place Q5500 (CPU Proximity Sensor) at the solder side

m
SM
at edge near backer plate of CPU to replace HeatSink Temp Sensor
OMIT 2 2 OMIT 1 1
XW5502 SM
SM XW5503
2 2

co
OMIT OMIT 1 1
PLACEMENT_NOTE=PLACE U5500 UNDER MXM HTSK TO GET MXM PROX TEMP
MLB Prox 0 (Tm0p)
CPU HTSK TEMP SENSOR
SM
XW5500 SM XW5501 RIGHT SKIN TEMP SENSOR SILK_PART=SKIN RIGHT TEMP SILK_PART=CPU HSK
1 1 L5520 J5520 L5522 J5521
FERR-220-OHM 53261-8602 FERR-220-OHM 53398-8602
97 52 SNS_T1_7_N M-RT-SM M-ST-SM
52 SNS_T1_3_P
1 2 3 SNS_T1_7_P

s.
CPU HTSK (TC0h) SNS_T1_7_P 97 97 52
2 1 3
97 52
0402 0402
97 52 SNS_T1_5_N 1 C5512 SNS_SKIN_RIGHT_P 1 1 C5522 97 SNS_CPU_H_P 1
MXM HTSK (TG0h) 0.0022UF
SNS_T1_5_P L5521 0.0022UF
C 97 52 10% 101 97 SNS_SKIN_RIGHT_N 2
10% L5523 97 SNS_CPU_H_N 2
C

ic
2 50V
CERM FERR-220-OHM 50V
2 CERM FERR-220-OHM
97 52 SNS_T1_3_N 402
RIGHT SKIN (TS0p) SNS_T1_3_N 1 2 4 402
97 52 SNS_T1_3_P
97 52
97 52 SNS_T1_7_N 2 1 4
0402 0402
CRITICAL CRITICAL

at
518S0665 518S0678

EMC1428-7: 6.8K PULL UP: I2C ADDRESS: WRITE: 0x92, READ: 0x93

em
LEFT SKIN TEMP SENSOR L5530
FERR-1000-OHM
97 52 SNS_T1_4_P 1 2 CONNECTOR COMBINED WITH CAMERA/BT
0402
1 C5513 SNS_SKIN_LEFT_P 44 97 101
0.0022UF

ch
10% L5531 SNS_SKIN_LEFT_N 44 97 101
2 50V
CERM
FERR-1000-OHM
402
97 52 SNS_T1_4_N 1 2
0402

kS
THIS PAGE DIFFERENT BETWEEN K60 AND K62.

oo
B eb B

SNS T2: DEVELOPMENT TEMP SENSOR IC

DEVELOPMENT =PP3V3_S0_SENSE
N

6 50 52
97 10 SNS_CPU_THERMD_P
CPU THERMAL DIODE
(TC0D) 1 C5521 DEVELOPMENT DEVELOPMENT DEVELOPMENT
ONLY DP/N1 compatible with CPU thermal diode 0.0022UF
10%
C5520 1 1
R5520 1
R5521
50V 1UF 33.2K 10K
2 CERM 10%
1% 5%
402 6.3V
97 10 SNS_CPU_THERMD_N DEVELOPMENT 1 X5R 2 1/16W
MF-LF
1/16W
MF-LF
402-1
VDD 2 402
2 402

DEVELOPMENT
U5520
EMC1414-A
SILK_PART=LCD TEMP 2 DP1
MSOP
7
J5550 DEVELOPMENT THERM*/ADDR SNS_T2_ADDR
53261-8602 L5550 3 DN1 ALERT* 8 SNS_T2_ALERT_L
M-RT-SM FERR-220-OHM
3 4 DP2/DN3 9
1 2 97 SNS_T2_DP2 DEVELOPMENT SMDATA =SMB_SNS1_SDA BI 49 52
0402
1 97 SNS_LCD_H_P 1 C5550 5 DN2/DP3 SMCLK 10 =SMB_SNS1_SCL 49 52
0.0022UF IN
L5551
A 2 97 SNS_LCD_H_N FERR-220-OHM
2 402
10%
50V
CERM
GND
6 SYNC_MASTER=K62_MARK SYNC_DATE=01/09/2011 A
1 2 97 SNS_T2_DN2 PAGE TITLE
4
0402
DEVELOPMENT
MLB Prox 1 (Tm1p) TEMP SENSORS
CRITICAL DRAWING NUMBER SIZE
518S0665
Apple Inc. 051-8442 D
REVISION
EMC1414-A-AIZL: 33K PULL UP: I2C ADDRESS: WRITE: 0x78, READ: 0x79 R
LCD TEMP
(TL2p)
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
55 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 52 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D FAN 0 CRITICAL
L5610
220-OHM-1.4A D
54 53 6 =PP12V_S0_FAN 1 2 PP12V_S0_FAN0_L
MIN_LINE_WIDTH=0.5MM
0603 MIN_NECK_WIDTH=0.25MM
VOLTAGE=12V

R56021 R5603 1 1 C5606 1 C5607

1.5K 1.5K 4.7UF
20%
0.01UF
20%
5%
1/4W 5%
1/8W 2 16V
CERM 2 16V
CERM
MF-LF 5 1206-1 402
1206 2 MF-LF
805 2
54 53 6 =PP3V3_S0_FAN R5605 CRITICAL
3.9K2
F0_VOLTAGE8R5 1 F0_GATESLOWDN
4 Q5600
R56061 5%
1/8W NTHS5443T1H
10K
5%
1/16W 3
MF-LF
805
C5601 1
1206A-03-HF ODD FAN
MF-LF
402 2 D Q5602 0.47UF
10%
2N7002 CRITICAL

1
2
3

6
7
8
16V
J5600

m
SMC_FAN_0_CTL X7R 2
1 SOT23-HF1 805
46 G S CRITICAL 53780-8604
M-RT-SM
MIN_NECK_WIDTH=0.25MM
2 L5620 MIN_LINE_WIDTH=0.5MM 5
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
220-OHM-1.4A

co
FAN_0_PWR 1 2 101 FAN_0_PWR_L 1 MOTOR CONTROL
CRITICAL 0603 101 FAN_TACH0_L 2 TACH
3 3
D5600
1
C5602 GND
100UF 4 12V DC
54 53 6 =PP3V3_S0_FAN MMBD914XG 20%

s.
1 2 16V
ELEC
SOT23 6.3X5.5-SM1-HF 6
R5600
1
10K 101 FAN_0_GND
518S0730

C 5% MIN_LINE_WIDTH=0.5MM
C

ic
1/16W CRITICAL MIN_NECK_WIDTH=0.25MM
MF-LF
2 402
L5600 R5620
1
R5699 FERR-220-OHM 0
47K 5%
46 SMC_FAN_0_TACH 1 2 FAN_TACH0 1 2 1/10W

at
0402 MF-LF
5%
1/16W NOTE: ADDED TO PROTECT SMC 2 603
MF-LF
402 PLACEMENT_NOTE=PLACE R5620 CLOSE TO J5600 Pin3

em
CRITICAL

FAN 1 220-OHM-1.4A
L5630
=PP12V_S0_FAN PP12V_S0_FAN1_L

ch
54 53 6
1 2
MIN_LINE_WIDTH=0.5MM
0603 MIN_NECK_WIDTH=0.25MM
VOLTAGE=12V
C5608 1 1 C5628 1 C5609
R56101 2.2UF
10%
2.2UF
10%
0.01UF
20%
1.5K 2 16V 2 16V
R56071 16V 2

kS
5% X5R X5R CERM
1/4W 1.5K 603 603 402
MF-LF
=PP3V3_S0_FAN 1206 2 5%
54 53 6 1/8W
MF-LF 5
1 805 2
R5611 R5609 CRITICAL
10K
5% F1_VOLTAGE8R5
3.9K
1 2 F1_GATESLOWDN Q5603 HD FAN

oo
1/16W 4
MF-LF 5%
402 2 3 1/8W NTHS5443T1H
MF-LF 1206A-03-HF
Q5605 805 CRITICAL
B D
2N7002 C5603 1 CRITICAL
J5601
53780-8604
B
SMC_FAN_1_CTL 1 G S SOT23-HF1 0.47UF M-RT-SM

1
2
3

6
7
8
46
10% MIN_NECK_WIDTH=0.25MM
L5640 5
eb 16V 2
X7R
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM 220-OHM-1.4A
MIN_LINE_WIDTH=0.5MM
2 805
FAN_1_PWR 1 2 101 FAN_1_PWR_L 1 MOTOR CONTROL
CRITICAL
0603 101 FAN_TACH1_L 2 TACH
3 D5601 1
C5605 3 GND
MMBD914XG 100UF 4
ot
12V DC
20%
54 53 6 =PP3V3_S0_FAN 1 SOT23 2 16V
TANT
D-HF 6

R5601
1
101 FAN_1_GND
518S0730
N

10K MIN_LINE_WIDTH=0.5MM
5% MIN_NECK_WIDTH=0.25MM
1/16W
MF-LF
2 402 C5605 IS POLY-TANT BECAUSE IT MUST BE PLACED ON THE BOTTOM CRITICAL
L5601
R5630
1
0
R5698 FERR-220-OHM 5%
1/10W
SMC_FAN_1_TACH 1
47K 2 1 2 MF-LF
46 FAN_TACH1
2 603
5% 0402
1/16W PLACEMENT_NOTE=PLACE R5630 CLOSE TO J5601 Pin3
MF-LF
402

A SYNC_MASTER=K62_JERRY SYNC_DATE=01/09/2011 A
PAGE TITLE

HD AND OD FAN
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

D D

SMC’S FAN3 OUTPUT CONTROL FAN 2

m
CRITICAL
L5710
220-OHM-1.4A
53 6
=PP12V_S0_FAN 1 2 101 98 PP12V_S0_FAN2_L

co
0603 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
1 C5708 1 C5709 VOLTAGE=12V
4.7UF
20%
0.01UF
20%
1 16V 2 16V
=PP3V3_S0_FAN R5704 R5701 1 2 CERM
1206-1
CERM
402
1.5K 1.5K

s.
54 53 6
5% 5%
1/4W 1/8W
MF-LF MF-LF
2 1206 805 2
5

C C
R5703
CPU FAN

ic
1
R5705 3.9K 2
10K F2_VOLTAGE8R5 1 F2_GATESLOWDN CRITICAL
5% 4
1/16W 5%
MF-LF 1/8W Q5700

at
2 402 MF-LF
805 NTHS5443T1H
C5701 1 1206A-03-HF J5700
0.47UF CRITICAL
53780-8604
M-RT-SM

1
2
3

6
7
8
3 10%
Q5702 16V 2 L5720 5

em
D X7R
2N7002 805 220-OHM-1.4A
SOT23-HF1 FAN_2_PWR FAN_2_PWR_L
46
SMC_FAN_3_CTL 1 G S MIN_NECK_WIDTH=0.25MM
1
0603
2 101

MIN_NECK_WIDTH=0.25MM
1 MOTOR CONTROL
MIN_LINE_WIDTH=0.5MM MIN_LINE_WIDTH=0.5MM 2 TACH
3
2
D5700
1
C5702 3 GND
MMBD914XG 100UF 4 12V DC
SOT23 20%
1 2 16V

ch
ELEC
6.3X5.5-SM1-HF 6
CRITICAL
101 FAN_2_GND 518S0730
CRITICAL

54 53 6
=PP3V3_S0_FAN
MIN_LINE_WIDTH=0.5MM

kS
1 MIN_NECK_WIDTH=0.25MM
R5700 1
10K
5% CRITICAL
0
R5720
1/16W
MF-LF
L5701 5%
R5797 2 402
FERR-220-OHM 1/10W
SMC_FAN_3_TACH 47K FAN_TACH2 101 FAN_TACH2_L MF-LF
46 1 2 1 2 2 603

oo
5% 0402
1/16W PLACEMENT_NOTE=PLACE R5720 CLOSE TO J5700 Pin3
MF-LF
402
B eb B
ot
N

FAN 3 SMC CONTROL (UNUSED)

A SYNC_MASTER=K62_JERRY SYNC_DATE=01/09/2011 A
PAGE TITLE
CPU FAN
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

D D

m
co
s.
C C

ic
48 6 =PP3V3_S5_ROM

at
R6100 1 1
CRITICAL

8
R6101 C6100 1
3.3K 3.3K
5% 5% 1UF
10%
VDD

em
1/16W 1/16W 6.3V
MF-LF MF-LF 2
402 2 2 402
CERM
402 U6100
R6150 64MBIT R6152
33 SOIC 33
94 48 18 IN SPI_CLK_R 1 2 94 SPI_CLK 6 SCK SI 5 94 SPI_MOSI 1 2 SPI_MOSI_R IN 18 48 94

5% 5%
PLACEMENT_NOTE=PLACE CLOSE TO U6100
1/16W
SST25VF064C 1/16W
PLACEMENT_NOTE=PLACE CLOSE TO U6100
MF-LF R6105 MF-LF
94 48 IN SPI_MLB_CS_L 402 1 CE* SO 2 94 SPI_MISO_R 1
33
2
402
SPI_MISO OUT 18 48 94

ch
SPI_WP_L 3 WP* OMIT
5%
SPI_HOLD_L 7 HOLD* 1/16W
MF-LF
VSS 402

4
kS
oo
B eb B
ot
N

A SYNC_MASTER=K62_AARON SYNC_DATE=11/30/2009 A
PAGE TITLE

SPI ROM
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

C6201 1 1 C6200
4.7UF 0.47UF
20% 10% PP4V5_AUDIO_ANALOG 56 58 59 61 98
4V 10V IN
X5R-1 2 2 X5R
CRITICAL
402 402 C6205 1 1 C6204C6206 C6207
C6208 1
1UF 0.47UF
0.47UF
1 1
10UF
10UF 10% 10%
20%
16V 2
C6202 1 1 10V
C6203 402-1
X5R 2
10V
2 X5R 10%
10V
20%
6.3V
0.47UF X5R 2 2 CERM-X5R

D 56 GND_AUDIO_HPAMP
POLY-TANT
CASE-B2-SM 10%
10V
10UF
20%
402
402 0402-1 D

25
X5R 2 2 16V

9
98 61 59 58 56 PP4V5_AUDIO_ANALOG POLY-TANT GND_AUDIO_HPAMP 56
IN
C6209 1 1 C6210 VD VA_REF VA_HP VA
402 CASE-B2-SM
GND_AUDIO_CODEC
1 2.2UF 2.2UF 56 57 58 59 60 61 62
1
R6200 20%
6.3V
20%
6.3V VBIAS_DAC 29 VBIAS_DAC TWEETERS R6205
2.67K CERM 2 2 CERM AUD_HP_PORT_L 0
1% 402-LF 402-LF HPOUT_L 38 MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM OUT 59 5%
1/16W CS4206_FP 44 VHP_FILT+ CRITICAL 1/16W
MF-LF HPOUT_R 40 MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM AUD_HP_PORT_R MF-LF
2 402
CS4206_FN 41 VHP_FILT- U6201 OUT 58
2 402
CS4206B HPREF 39 MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM AUD_HP_PORT_REF
QFN
NC TP_AUD_DMIC_SDA1 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 AUD_LO1_L_P OUT 57 62

NC TP_AUD_GPIO_1 12 GPIO1/DMIC_SDA2
/SPDIF_OUT2
LINEOUT_L1- 34 AUD_LO1_L_N OUT 57 62

HP AMP 57 OUT AUD_GPIO_2 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_R_P OUT 57 62 HP AMP/LINE OUT

SPEAKERS 58 OUT AUD_GPIO_3 15 GPIO3 LINEOUT_R1- 37 AUD_LO1_R_N OUT 57 62

61 IN AUD_SENSE_A 13 SENSE_A LINEOUT_L2+ 31 AUD_LO2_L_P OUT 59 62

CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_L_N OUT 59 62 WOOFERS

CS4206_FLYC AUD_LO2_R_P

m
LINEOUT_R2+ 32 OUT 58 62
45 FLYP
LINEOUT_R2- 33 AUD_LO2_R_N
C6211 1 1 C6212 43 FLYC OUT 58 62

2.2UF 2.2UF 42 FLYN

20% 20%
6.3V 2 2 6.3V MICBIAS 16 AUD_CODEC_MICBIAS 61
TABLE_ALT_HEAD

co
CERM CERM OUT
402-LF 402-LF MIN_LINE_WIDTH=0.20MM PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
MIN_NECK_WIDTH=0.15MM PART NUMBER
3 VL_HD
CS4206_FLYN MIN_LINE_WIDTH=0.20MM TABLE_ALT_ITEM

VCOM 28 CS4206_VCOM MIN_NECK_WIDTH=0.15MM 353S2592 353S3199 U6201 CS4206A

1 VL_IF

s.
PLACE TP FOR ALL HDA SIGNALS NEAR CODEC
LINEIN_L+ 21 AUD_LI_P_L IN 57
94 18 IN HDA_BIT_CLK 6 BITCLK
LINEIN_C- 22 AUD_LI_COM IN 57

HDA_SYNC AUD_LI_P_R
C 94 18 IN LINEIN_R+ 23 IN 57
C

ic
R6201 10 SYNC
22
94 18 OUT HDA_SDIN0 1 2 94 AUD_SDI_R 8 SDI MICIN_L+ 18 AUD_MIC_INP_L IN 62

5% 5 SDO MICIN_L- 17 AUD_MIC_INN_L IN 62

at
1/16W
MF-LF MICIN_R+ 19 AUD_MIC_INR_P IN 61 62
402 11 RESET*
94 18 15 IN HDA_SDOUT MICIN_R- 20 AUD_MIC_INR_N IN 61 62

94 18 IN HDA_RST_L
AUD_SPDIF_IN_CODEC 47 SPDIF_IN

em
100 84 IN
94 AUD_SPDIF_CHIP 48 SPDIF_OUT
VREF+_ADC 27 CS4206_VREF_ADC
MIN_LINE_WIDTH=0.20MM
NC
R6202 MIN_NECK_WIDTH=0.15MM
22 TP_CS4206_DMIC_SCL NC
94 60 OUT AUD_SPDIF_OUT 1 2 DMIC_SCL 4
5% R62031
1/16W 100K
MF-LF 1%
402 1/16W DGND THRM_PAD AGND
MF-LF

ch
402 2

26
CRITICAL CRITICAL
1 1
C6213 C6214 DIFF FSINPUT= 2.45VRMS
1UF 10UF
10%
20V 2
20%
2 16V
SE FSINPUT= 1.22VRMS
TANT POLY-TANT DAC1 FSOUTPUT= 1.34VRMS

kS
CASE-P3-HF CASE-B2-SM
56 GND_AUDIO_HPAMP DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS

62 61 60 59 58 57 56 GND_AUDIO_CODEC APN 152S1314

CRITICAL

oo
T6250 61 57 PP5V_AUDIO_ISO
MIN_LINE_WIDTH=0.4MM
1.8UH-1.6A-243MOHM
ISOLATED 5 V POWER SUPPLY FOR HP AMP LPD3015-SM D6252 MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
B APPLE P/N 353S2456 56 6 IN =PP5V_S0_AUDIO 1 3 AUD_XFRMR_SEC 1
DO222-SM
2
B
4.5V POWER SUPPLY FOR CODEC MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
eb CRITICAL CRITICAL L1 L2
STPS1L30MF
C6250 1 Q6250 NOSTUFF C6256 1
1
R6255 CRITICAL
MIN_LINE_WIDTH=0.40MM 10UF DMMT3906W-7-F 5 1.0K
20% 1 1UF C6258 1 1 C6259 1
MIN_NECK_WIDTH=0.20MM
VOLTAGE=4.5V 10V
X5R 2
SOT-363 R6258 10% 1%
1/10W
56 SC4503_SW 2 4
10UF
R6257
XW6212 603
1 1K 25V
X5R 2 MF-LF 150UF-.025-OHM 20%
4.99K
1% 20%
PP5V_AUDIO_HPAMP 56 98 1/16W
402 2 603 6.3V 2 10V
2 X5R
1%
1/10W
OUT TANT
ot
MF-LF MF-LF
1

SC4503_SW_SNBR CASE-B2-SM 603

SM
6 2 402 MIN_LINE_WIDTH=0.4MM 2 603
MIN_NECK_WIDTH=0.2MM APN 128S0271
2
SC4503_FB_DDROP
D6250
N

SOD-523
1
R6256 BAT54XV2T1
MIN_LINE_WIDTH=0.40MM
C6257 1 49.9K 1 62 60 57 56 GND_AUDIO_ISO
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.20MM 0.1UF 1% MIN_NECK_WIDTH=0.2MM
VOLTAGE=4.5V 10% 1/16W VOLTAGE=0V
16V
L6210 X7R-CERM 2 MF-LF
MIN_LINE_WIDTH=0.40MM
FERR-220-OHM VR6201
TPS71745
MIN_NECK_WIDTH=0.20MM
VOLTAGE=4.5V
402 2 402
R6260
=PP5V_S0_AUDIO 1 2 4V5_REG_IN 6 IN 1 PP4V5_AUDIO_ANALOG
56 6 IN 98 SON
OUT OUT 56 58 59 61 98 R62541 1
10 2 GND_AUDIO_ISO 56 57 60 62
0402 CRITICAL 20
1% 1%
R6220 100 4V5_REG_EN 4 EN NR/FB 3 4V5_NR SOT-363 1/10W 1/10W
2 MF-LF MF-LF
0 DMMT3906W-7-F 603 2 603
56 6 IN =PP5V_S0_AUDIO 1 2
GND NC 5 MIN_LINE_WIDTH=0.4MM APN 353S3080 Q6250 D6251
5%
2
MIN_NECK_WIDTH=0.2MM CRITICAL R6253 SOD-523
1/16W NOSTUFF SC4503_SW 56 43.2K2
MF-LF
402 1 C6221 1 C6222 C6223 1 1 C6224 MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
SC4503_FB_RDIV
3
SC4503_FB_PNP 1
4
SC4503_FB_FILT 2 1 SC4503_SW_D
0.1UF 1UF 1%
1UF 1UF 10%
16V
10%
10V R6250 1 1/16W BAT54XV2T1
10% 10% 1
R6251 MF-LF
5

SW 1

10V 10V X7R-CERM 2 2 X5R

40.2K 402
A 2 X5R
402-1
2 X5R
402-1
402 402-1

GND_AUDIO_CODEC 56 57 58 59 60 61 62
1%
1/16W
MF-LF
IN
U6250 1%
3.40K
1/16W
NOSTUFF NOSTUFF SYNC_MASTER=K62_DAVID SYNC_DATE=01/09/2011 A
NOSTUFF MIN_LINE_WIDTH=0.5MM 402 2
SC4503 MF-LF C6254 1 1 C6261 1
R6259 C6255 1 PAGE TITLE

R6212
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V TSOT-23
4 SHDN*/SS
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM 2 402 0.01UF
10%
16V
0.001UF
10%
50V 1%
100K 0.001UF
10%
50V
AUDIO: CODEC/REGULATOR
1
0 2
SC4503_SHDN_L FB 3 SC4503_FB CERM 2 2 X7R 1/16W X7R 2 DRAWING NUMBER SIZE
MF-LF
5%
SYM VER 2
CRITICAL NOSTUFF
402 402
2 402
402
Apple Inc. 051-8442 D
1
1/16W
MF-LF C6252 1 1 C6251 C6253 1 R6252 R
REVISION
402
0.1UF 0.1UF GND 1UF 1%
12.4K 10.1.0
10% 10% 10% NOTICE OF PROPRIETARY PROPERTY:
R6210
2

16V 16V 10V 1/16W BRANCH

0 XW6211 X7R-CERM 2 2 X7R-CERM X5R 2 MF-LF
1 2 GND_AUDIO_HPAMP 56
402 402 402-1 2 402 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
MIN_LINE_WIDTH=0.2MM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1

5% SM MIN_NECK_WIDTH=0.1MM
1/10W
MF-LF
VOLTAGE=0V I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
62 OF 110
603 SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 56 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SIGNAL_MODEL=EMPTY
C6362
220PF
1 2

5%
25V
CERM
402

R6362
7.87K2
1
R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL
1%
1/16W
MF-LF MAX97220_OUTR OUT 57 60 61 56 PP5V_AUDIO_ISO
402

D CRITICAL
C6361 R6361
SIGNAL_MODEL=EMPTY D
33UF
AUD_LO1_R_N 1 2 62 AUD_LO1_R_C_N 1
10K 2 MAX97220_INR_N C6350 1 1 C6351 C6352 1 1 C6353
62 56 IN OUT 57 62
0.1UF 10UF 1UF 1UF
1% 10% 20% 10% 10%
1/16W 16V 10V 10V 10V
20% X7R-CERM 2 2 X5R X5R 2 2 X5R
6.3V MF-LF
402 402 603 402-1 402-1
TANT
CASE-A
62 60 57 56 GND_AUDIO_ISO GND_AUDIO_ISO 56 57 60 62
CRITICAL
C6363 R6363

13
33UF

9
10K
62 56 IN AUD_LO1_R_P 1 2 62 AUD_LO1_R_C_P 1 2 MAX97220_INR_P OUT 57 62

PVDD
SVDD
SVDD2
1%
20% 1/16W R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL
6.3V MF-LF
TANT 402
CASE-A
SIGNAL_MODEL=EMPTY 62 57 IN MAX97220_INR_N 14 INL- OUTL 12 MAX97220_OUTR OUT 57 60
SIGNAL_MODEL=EMPTY 15 INL+ CRITICAL MIN_LINE_WIDTH=0.4MM
R63641 62 57 MAX97220_INR_P MIN_NECK_WIDTH=0.2MM
7.87K
1 C6364 IN
U6350 BIAS 11 MAX97220_BIAS

m
220PF MIN_LINE_WIDTH=0.4MM
1% MAX97220AETE MIN_NECK_WIDTH=0.2MM
1/16W 5%
25V 62 57 IN MAX97220_INL_P 7 INR+ TQFN OUTR 10 MAX97220_OUTL OUT 57 60
MF-LF 2 CERM MIN_LINE_WIDTH=0.4MM MIN_LINE_WIDTH=0.4MM
402 2 402 L6350 62 57 IN MAX97220_INL_N 8 INR- MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
R6365 FERR-220-OHM C1P
2
MAX97220_C1P
0

co
GND_AUDIO_ISO 1 2 MAX97220_SGND AUD_GPIO_2 1 2 MAX97220_SHDN_L 16 SHDN* C1N 4

17 THM_PAD
62 60 57 56 56 IN
5% 0402 1 C6355 1 C6356

PGND

SGND

PVSS
1/16W
MF-LF 1UF 1UF
402 SIGNAL_MODEL=EMPTY 10% 10%
1 SIGNAL_MODEL=EMPTY 1 2 10V
X5R 2 10V
X5R
R6374 1 C6374 R6350 402-1 402-1

5
7.87K 100K

s.
1% 220PF 5%
1/16W 5% 1/16W MAX97220_C1N
MF-LF 2 25V
CERM MF-LF MIN_LINE_WIDTH=0.4MM
402 2 402 402 2 MIN_NECK_WIDTH=0.2MM

C C

ic
CRITICAL
C6373 R6373
33UF MAX97220_PVSS
AUD_LO1_L_P 1 2 AUD_LO1_L_C_P 1
10K 2 MAX97220_INL_P
62 56 IN 62
OUT 57 62 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

at
1% VOLTAGE=0V
20% 1/16W
6.3V
TANT
MF-LF
402
1 C6354
CASE-A 1UF
10%
10V
2 X5R
CRITICAL

em
402-1
C6371 R6371
33UF
10K
62 56 IN AUD_LO1_L_N 1 2 62 AUD_LO1_L_C_N 1 2 MAX97220_INL_N OUT 57 62

1%
20% 1/16W 62 60 57 56 GND_AUDIO_ISO
6.3V MF-LF
TANT 402
CASE-A SIGNAL_MODEL=EMPTY
MAX97220_OUTL OUT 57 60

ch
R6372
1
7.87K2
1%
1/16W
MF-LF
402

kS
C6372
220PF
1 2

5%
25V
CERM
402 CODEC Nom SE RIN = 20K OHMS

oo
SIGNAL_MODEL=EMPTY
FC = 3.62 HZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
B NET RIN = 18K OHMS B
MIN_NECK_WIDTH=.2MM
eb
MIN_LINE_WIDTH=.3MM
CRITICAL
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM R6300 C6300
AUD_LI_LF 22UF
7.87K2
60 IN AUD_LI_L 1 2 1 AUD_LI_P_L OUT 56

1%
1/16W 20%
ot
MF-LF 6.3V
402 TANT
CASE-P
NOSTUFF
R63011 1 C6301
21.5K 820PF
N

1% 10%
1/16W 50V
MF-LF 2 CERM
402 2 402

MIN_NECK_WIDTH=0.2MM CRITICAL MIN_NECK_WIDTH=.2MM

MIN_LINE_WIDTH=0.3MM C6302 MIN_LINE_WIDTH=.3MM
22UF
60 IN AUD_LI_GND 2 1 AUD_LI_COM OUT 56

20%
6.3V
1 TANT
R6303 CASE-P
10
1%
1/16W NOSTUFF
MF-LF
2 402
R63051 1 C6304
21.5K 820PF
1% 10%
1/16W
GND_AUDIO_CODEC 2 50V
A 62 61 60 59 58 56 IN MF-LF
402 2
CERM
402
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
SYNC_MASTER=K62_DAVID SYNC_DATE=01/09/2011 A
PAGE TITLE

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM R6306
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
CRITICAL
C6303 AUDIO: FILTER/BUFFER
7.87K2 AUD_LI_RF 22UF DRAWING NUMBER SIZE
60 IN AUD_LI_R 1 2 1 AUD_LI_P_R OUT 56
Apple Inc. 051-8442 D
1% REVISION
1/16W 20% R
MF-LF
402
6.3V
TANT
10.1.0
CASE-P NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
63 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 57 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RIGHT CH SPEAKER AMP
APPLE P/N 353S3069
59 6 IN =PP12V_S0_AUDIO_SPKRAMP

CRITICAL
C6400 1 C6401 C6402 1 C6403 C6404 1 C6405 R6402 = HIGH = 400 KHZ
1
=PP3V3_S0_AUDIO
1 1 1
C6406 SPEAKER AMP GAIN = +9 DB
10UF 0.1UF 62 61 60 59 56 6
0.1UF 1UF 0.1UF 1UF 220UF
10%
25V 2
10%
2 25V
NOSTUFF NOSTUFF 10%
25V 2
10%
2 25V
10%
25V 2
10%
2 25V
20%
2 16V
SPEAKER AMP RIN = 210K NOMINAL W/ +9 DB GAIN
X5R X5R X5R X5R X5R X5R
805 402 R64021 R64041 1
R6406 402 603-1 402 603-1
ELEC
SM-CASE-C1-HF
FC_HPF, TWEETERS = ~924 HZ (820 PF)
5%
0
5%
0
5%
0 FC_HPF, WOOFERS = ~23 HZ (0.033 UF)
1/16W 1/16W 1/16W

D MF-LF
402 2
MF-LF
402 2
MF-LF
2 402
D
AUD_RAMP_GAIN0

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS AUD_RAMP_GAIN1 C6413 SIGNAL_MODEL=EMPTY

0.22UF CRITICAL
L6400 C6408 1 1 1 2 L6404
FERR-1000-OHM 820PF R6405 R6407 AUD_RAMP_BSPL
MIN_LINE_WIDTH=0.20MM 220-OHM-25%-2.5A
1 2 1 2
0 0 MIN_NECK_WIDTH=0.15MM 20%
AUD_HP_R_N AUD_RAMP_RINC_P AUD_RAMP_RIN_P

26
27

14
15
62 58 IN 62 62 5% 5% 25V 1 2
AUD_RAMP_OUTPL AUD_SPKR_RWFR_OUT_P

AVCC 4
1/16W 1/16W X5R OUT 60 62
0402 MF-LF MF-LF MIN_LINE_WIDTH=0.6MM
10% 402 2 603 0603
50V 2 402 MIN_NECK_WIDTH=0.25MM

PVCCL

PVCCR
CERM SIGNAL_MODEL=EMPTY
402
CRITICAL
L6401 C6409 L6405
FERR-1000-OHM 820PF
U6400 220-OHM-25%-2.5A
62 58 AUD_HP_R_P 1 2 62 AUD_RAMP_RINC_N 1 2 62 AUD_RAMP_RIN_N
IN
0402
TPA3117D2 C6414 AUD_RAMP_OUTNL
MIN_LINE_WIDTH=0.6MM
1 2 AUD_SPKR_RWFR_OUT_N OUT 60 62
10% 9 RINP QFN BSPL 25 0.22UF MIN_NECK_WIDTH=0.25MM 0603
50V

m
CERM 8 CRITICAL 24 1 2
402 RINN OUTPL AUD_RAMP_BSNL
22 MIN_LINE_WIDTH=0.20MM
1 OUTNL MIN_NECK_WIDTH=0.15MM 20%
LINN
L6402 C6410 32 LINP
BSNL 21 25V
X5R
FERR-1000-OHM 0.033UF 603

co
MIN_LINE_WIDTH=0.40MM 2 16
1 2 AUD_RAMP_LINC_N 1 2 AUD_RAMP_LIN_N PP5V_RAMP_VREG
62 56 IN AUD_LO2_R_N 62 62 MIN_NECK_WIDTH=0.20MM
3
GAIN0 BSPR
17
C6415 SIGNAL_MODEL=EMPTY
0402
R6408 GAIN1 OUTPR 0.22UF CRITICAL
10%
16V 10 OUTNR 19 AUD_RAMP_BSPR 1 2 L6406 OUTPUT POLARITY FLIP TO
X5R 1 2 AUD_RAMP_REG_OUT 6 REG_OUT 20 MIN_LINE_WIDTH=0.20MM 220-OHM-25%-2.5A MAKE LAYOUT MORE LOGICAL
402 BSNR MIN_NECK_WIDTH=0.15MM
1% 20%
L6403 C6411 1/16W AUD_RAMP_PLIMIT 7 25V AUD_RAMP_OUTPR 1 2 AUD_SPKR_RTWT_OUT_N

s.
PLIMIT X5R OUT 60 62
FERR-1000-OHM MF-LF 12 MIN_LINE_WIDTH=0.6MM
0.033UF 402 603 MIN_NECK_WIDTH=0.25MM 0603
11 PBTL
62 56 AUD_LO2_R_P 1 2 62 AUD_RAMP_LINC_P 1 2 62 AUD_RAMP_LIN_P 13
IN
0402 31 28 SIGNAL_MODEL=EMPTY
C 10%
AUD_RAMP_FSEL FSEL NC
C

ic
16V 29 CRITICAL
X5R
402
30 SD* 10 L6407
220-OHM-25%-2.5A

PGND
AGND

THRM
R6409

PAD
AUD_RAMP_OUTNR 1 2 AUD_SPKR_RTWT_OUT_P
C6416 OUT 60 62

at
0

AUD_RAMP_PBTL
MIN_LINE_WIDTH=0.6MM
59 AUD_SPKRAMP_MUTE_L 1 2 0.22UF MIN_NECK_WIDTH=0.25MM 0603
OUT
AUD_RAMP_BSNR 1 2

18
23

33
5% CRITICAL CRITICAL
1/16W MIN_LINE_WIDTH=0.20MM
R6400 MF-LF
402
MIN_NECK_WIDTH=0.15MM
20% SIGNAL_MODEL=EMPTY C6420 1 C6422 1 SIGNAL_MODEL=EMPTY
0 25V 1000PF 1000PF

em
58 56 AUD_GPIO_3 1 2 X5R 5% 5%
IN 603 25V 25V
5% NP0-C0G 2 NP0-C0G 2
1/16W 402 402
MF-LF
402 NOSTUFF 1
NOSTUFF
1 C6417 R6410 1 C6418 1R6403
2.2UF 10K 1UF 0
R64011 1 C6412 20% 1% 10% 5%
CRITICAL CRITICAL
100K
5% 100PF 2 10V
X5R-CERM 1/16W
MF-LF
10V
2 X5R 1/16W
MF-LF
SIGNAL_MODEL=EMPTY 1 C6419 1 C6421 SIGNAL_MODEL=EMPTY
5% 402 402 1000PF 1000PF

ch
1/16W 50V 402 2 2 402 5% 5%
MF-LF 2 CERM 25V 25V
402 2 402 2 NP0-C0G 2 NP0-C0G
402 402

kS
CRITICAL
SE-TO-DIFF CONVERTER
C6453 SIGNAL_MODEL=EMPTY
3.3UF R6453 R6454
21K 21K
56 AUD_HP_PORT_R 2 1 AUD_R_SE_DIFF_IN 1 2 AUD_R_SE_DIFF_IN_R 1 2 AUD_SE_DIFF_SHDN_L 59

oo
1% 1%
10% 1/16W 1/16W
16V MF-LF MF-LF
TANT 402 402
SMA-HF1
R6460
B 1
0 2 AUD_GPIO_3 IN 56 58
B
5%
eb B4
1/16W
MF-LF
402
V- 1
C3 C4
AUD_HP_R_P R6461
U6450 C1 OUT 58 62 100K
5%
UCSP 1/16W
C2
V+ MAX4253 MF-LF
ot
B1
CRITICAL 2 402
SIGNAL_MODEL=EMPTY
R6455
2.21K
1 2
N

1%
1/16W SIGNAL_MODEL=EMPTY
MF-LF
402 R6457
2.21K
AUD_R_SE_DIFF_P_INV 1 2

1%
SIGNAL_MODEL=EMPTY 1/16W
MF-LF
R6458 402
2.21K
1 2

1%
1/16W SIGNAL_MODEL=EMPTY
MF-LF
402 R6456
2.21K
AUD_R_SE_DIFF_N_INV 1 2

1%
1/16W
MF-LF
402

98 61 59 56 PP4V5_AUDIO_ANALOG

A R6450 1 CRITICAL
SYNC_MASTER=K62_DAVID SYNC_DATE=01/09/2011 A
21K B1 PAGE TITLE
1%
1/16W
MF-LF
59 AUD_SE_DIFF_VBIAS
MIN_LINE_WIDTH=0.20MM
A2
V+
MAX4253
UCSP
A1
AUD_HP_R_N
AUDIO: SPEAKER AMP_1
402 DRAWING NUMBER SIZE
C6450 1 1
C6451 2
MIN_NECK_WIDTH=0.15MM
U6450 OUT 58 62

051-8442 D
4.7UF 0.47UF A3 A4
Apple Inc.
20% 10% V- REVISION
6.3V 2 2
10V B4 R
X5R
402
X5R
402 CRITICAL 10.1.0
R6451 1 1
NOTICE OF PROPRIETARY PROPERTY:
21K C6452 BRANCH
1% 3.3UF THE INFORMATION CONTAINED HEREIN IS THE
1/16W 10% PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
MF-LF 2 16V THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 TANT
2 SMA-HF1 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
64 OF 110
62 61 60 59 57 56 GND_AUDIO_CODEC SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 58 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LEFT CH SPEAKER AMP
APPLE P/N 353S3069
58 6 IN =PP12V_S0_AUDIO_SPKRAMP

CRITICAL
C6500 1 C6501 C6502 1 C6503 C6504 1 C6505 R6502 = LOW = 300 KHZ
1
=PP3V3_S0_AUDIO
1 1 1
C6506 SPEAKER AMP GAIN = +9 DB
10UF 0.1UF 62 61 60 58 56 6
0.1UF 1UF 0.1UF 1UF 220UF
10%
25V 2
10%
2 25V
NOSTUFF NOSTUFF 10%
25V 2
10%
2 25V
10%
25V 2
10%
2 25V
20%
2 16V
SPEAKER AMP RIN = 210K NOMINAL W/ +9 DB GAIN
X5R X5R X5R X5R X5R X5R
805 402 R65041 1
R6506 402 603-1 402 603-1
ELEC
SM-CASE-C1-HF
FC_HPF, TWEETERS = ~924 HZ (820 PF)
5%
0
5%
0 FC_HPF, WOOFERS = ~23 HZ (0.033 UF)
1/16W 1/16W

D MF-LF
402 2
MF-LF
2 402
D
AUD_LAMP_GAIN0

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS AUD_LAMP_GAIN1 C6513 SIGNAL_MODEL=EMPTY

0.22UF CRITICAL
L6500 C6508 1 1 1 2 L6504
FERR-1000-OHM 820PF R6505 R6507 AUD_LAMP_BSPL
MIN_LINE_WIDTH=0.20MM 220-OHM-25%-2.5A
1 2 1 2
0 0 MIN_NECK_WIDTH=0.15MM 20%
AUD_HP_L_N AUD_LAMP_RINC_P AUD_LAMP_RIN_P

26
27

14
15
62 59 IN 62 62 5% 5% 25V 1 2
AUD_LAMP_OUTPL AUD_SPKR_LWFR_OUT_P

AVCC 4
1/16W 1/16W X5R OUT 60 62
0402 MF-LF MF-LF MIN_LINE_WIDTH=0.6MM
10% 402 2 603 0603
50V 2 402 MIN_NECK_WIDTH=0.25MM

PVCCL

PVCCR
CERM
402 SIGNAL_MODEL=EMPTY
CRITICAL
L6501 C6509 L6505
FERR-1000-OHM 820PF
U6500 220-OHM-25%-2.5A
62 59 AUD_HP_L_P 1 2 62 AUD_LAMP_RINC_N 1 2 62 AUD_LAMP_RIN_N
IN
0402
TPA3117D2 C6514 AUD_LAMP_OUTNL
MIN_LINE_WIDTH=0.6MM
1 2 AUD_SPKR_LWFR_OUT_N OUT 60 62
10% 9 RINP QFN BSPL 25 0.22UF MIN_NECK_WIDTH=0.25MM 0603
50V

m
CERM 8 CRITICAL 24 1 2
402 RINN OUTPL AUD_LAMP_BSNL
22 MIN_LINE_WIDTH=0.20MM
1 OUTNL MIN_NECK_WIDTH=0.15MM 20%
LINN
L6502 C6510 32 LINP
BSNL 21 25V
X5R
FERR-1000-OHM 0.033UF 603

co
MIN_LINE_WIDTH=0.40MM 2 16
1 2 AUD_LAMP_LINC_N 1 2 AUD_LAMP_LIN_N PP5V_LAMP_VREG
62 56 IN AUD_LO2_L_N 62 62 MIN_NECK_WIDTH=0.20MM
3
GAIN0 BSPR
17
C6515 SIGNAL_MODEL=EMPTY
0402
R6508 GAIN1 OUTPR 0.22UF CRITICAL
10%
16V 10 OUTNR 19 AUD_LAMP_BSPR 1 2 L6506 OUTPUT POLARITY FLIP TO
X5R 1 2 AUD_LAMP_REG_OUT 6 REG_OUT 20 MIN_LINE_WIDTH=0.20MM 220-OHM-25%-2.5A MAKE LAYOUT MORE LOGICAL
402 BSNR MIN_NECK_WIDTH=0.15MM
1% 20%
L6503 C6511 1/16W AUD_LAMP_PLIMIT 7 25V AUD_LAMP_OUTPR 1 2 AUD_SPKR_LTWT_OUT_N

s.
PLIMIT X5R OUT 60 62
FERR-1000-OHM MF-LF 12 MIN_LINE_WIDTH=0.6MM
0.033UF 402 603 MIN_NECK_WIDTH=0.25MM 0603
11 PBTL
62 56 AUD_LO2_L_P 1 2 62 AUD_LAMP_LINC_P 1 2 62 AUD_LAMP_LIN_P 13
IN
0402 31 28 SIGNAL_MODEL=EMPTY
C 10%
AUD_LAMP_FSEL FSEL NC
C

ic
16V 29 CRITICAL
X5R
402
30 SD* 10 L6507
220-OHM-25%-2.5A

PGND
AGND

THRM
R6509

PAD
AUD_LAMP_OUTNR 1 2 AUD_SPKR_LTWT_OUT_P
C6516 OUT 60 62

at
0

AUD_LAMP_PBTL
MIN_LINE_WIDTH=0.6MM
58 AUD_SPKRAMP_MUTE_L 1 2 0.22UF MIN_NECK_WIDTH=0.25MM 0603
IN
AUD_LAMP_BSNR 1 2

18
23

33
5% CRITICAL CRITICAL
1/16W MIN_LINE_WIDTH=0.20MM
MF-LF
402
MIN_NECK_WIDTH=0.15MM
20% SIGNAL_MODEL=EMPTY C6520 1 C6522 1 SIGNAL_MODEL=EMPTY
25V 1000PF 1000PF

em
X5R 5% 5%
603 25V 25V
NP0-C0G 2 NP0-C0G 2
402 402

NOSTUFF 1
R65021 1 C6517 R6510 1 C6518 1R6503
0 2.2UF 10K 1UF 0 CRITICAL CRITICAL
5% 20% 1% 10% 5%
1/16W
MF-LF
2 10V
X5R-CERM 1/16W
MF-LF
10V
2 X5R 1/16W
MF-LF
SIGNAL_MODEL=EMPTY 1 C6519 1 C6521 SIGNAL_MODEL=EMPTY
402 402 1000PF 1000PF

ch
402 2 402 2 2 402 5% 5%
25V 25V
2 NP0-C0G 2 NP0-C0G
402 402

kS
CRITICAL
SE-TO-DIFF CONVERTER
SIGNAL_MODEL=EMPTY
C6553
3.3UF R6553 R6554
21K 21K
56 AUD_HP_PORT_L 2 1 AUD_L_SE_DIFF_IN 1 2 AUD_L_SE_DIFF_IN_R 1 2

oo
1% 1%
10% 1/16W 1/16W
16V MF-LF MF-LF
TANT 402 402
SMA-HF1

B eb AUD_SE_DIFF_SHDN_L IN 58
B
B4

C3 V- C4
AUD_HP_L_P
U6550 C1 OUT 59 62

UCSP
C2
V+ MAX4253
ot
B1
SIGNAL_MODEL=EMPTY CRITICAL
R6555
2.21K
1 2
N

1%
1/16W SIGNAL_MODEL=EMPTY
MF-LF
402 R6557
2.21K
AUD_L_SE_DIFF_P_INV 1 2

1%
SIGNAL_MODEL=EMPTY 1/16W
MF-LF
R6558 402
2.21K
1 2

1%
1/16W SIGNAL_MODEL=EMPTY
MF-LF
402 R6556
2.21K
AUD_L_SE_DIFF_N_INV 1 2

1%
1/16W
MF-LF
402

98 61 58 56 PP4V5_AUDIO_ANALOG

A CRITICAL
SYNC_MASTER=K62_DAVID SYNC_DATE=01/09/2011 A
B1 PAGE TITLE
A2
V+
MAX4253
UCSP
A1
AUD_HP_L_N
AUDIO: SPEAKER AMP
DRAWING NUMBER SIZE
C6550 1 1
C6551 U6550 OUT 59 62

051-8442 D
4.7UF 0.47UF 58 AUD_SE_DIFF_VBIAS A3 A4
Apple Inc.
20% 10% V- REVISION
6.3V 2 2
10V B4 R
X5R
402
X5R
402 10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
65 OF 110
62 61 60 58 57 56 GND_AUDIO_CODEC SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 59 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SPEAKER CABLE CONNECTORS
APPLE P/N 518S0748
INTERNAL MIC CON APPLE P/N 518S0656
APPLE P/N 518S0677
PROPERTIES FOR ALL SPKR NETS
PROPERTIES FOR ALL SPKR NETS CRITICAL CRITICAL
CRITICAL
J6602 J6603
J6601 78048-0573
78048-0473 M-RT-SM
L6600 53780-8603 M-RT-SM
M-RT-SM
FERR-1000-OHM 4 1
62 59 IN AUD_SPKR_LWFR_OUT_P 1
62 58 IN AUD_SPKR_RWFR_OUT_P WOOFER (BL) 2
AUD_MIC1_IN_N 1 2 WOOFER (BR) 62 59 AUD_SPKR_LWFR_OUT_N

D
62 61 OUT
0402
62 AUD_MIC_IN1_CONN_N
1
62 58

62 58
IN
IN
AUD_SPKR_RWFR_OUT_N
AUD_SPKR_RTWT_OUT_P
2
3 NO_TEST
IN
NC NC_J6702_3 3 D
2
TWEETER (FR) 4
62 59 IN AUD_SPKR_LTWT_OUT_P 4
L6602 GND_AUDIO_MIC1_CONN 62 58 IN AUD_SPKR_RTWT_OUT_N TWEETER (FL) AUD_SPKR_LTWT_OUT_N 5
MIN_LINE_WIDTH=0.3MM 62 59 IN
FERR-1000-OHM MIN_NECK_WIDTH=0.2MM 3
VOLTAGE=0V
62 61 OUT AUD_MIC1_IN_P 1 2 62 AUD_MIC_IN1_CONN_P
5
0402

SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
CRITICAL 2 2
CRITICAL
DZ6600 DZ6601 1
R6600
6.8V-100PF 6.8V-100PF 0
402 402 5%
1/16W
MF-LF
1 1 2 402

m
co
s.
C C

ic
R6601

at
22
100 94 84 OUT AUD_SPDIF_IN 1 2
L6604 5%
1/16W
FERR-1000-OHM MF-LF
402

em
61 59 58 56 6 IN =PP3V3_S0_AUDIO 1 2
62
0402
L6605 REMOTE I/O CONNECTOR
FERR-1000-OHM APPLE P/N 518S0723
61 OUT AUD_LI_TIP_DET 1 2

MIN_LINE_WIDTH=0.3MM
CRITICAL L6610 0402

MIN_NECK_WIDTH=0.2MM
10-OHM-1A

ch
CRITICAL
AUD_LI_GND 1 2
57 OUT
MIN_LINE_WIDTH=0.3MM 0402 L6607
J6600
MIN_NECK_WIDTH=0.2MM FERR-1000-OHM 20143-020E-20F
F-RT-SM
57 OUT AUD_LI_R 1 2 21
0402

kS
MIN_LINE_WIDTH=0.3MM L6608 1
MIN_NECK_WIDTH=0.2MM FERR-1000-OHM
101 AUD_SPDIFIN_JACK 2
57 OUT AUD_LI_L 1 2
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V 101 98 PP3V3_AUDIO_SPDIF_JACK 3
0402 L6609 101 AUD_LI_DET_JACK 4
FERR-1000-OHM MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD_LI_GND_JACK 5
GND_AUDIO_CODEC 1 2

oo
62 61 59 58 57 56 OUT
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD_LI_R_JACK 6
MIN_LINE_WIDTH=0.15MM L6606 0402
AUD_LI_GND_JACK 7
MIN_NECK_WIDTH=0.1MM FERR-1000-OHM MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

B 62 OUT HS_MIC_HI 1
0402
2 MIN_LINE_WIDTH=0.4MM
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
101 AUD_LI_L_JACK

AUD_GND_DET_JACK
8
9
B
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 HS_MIC_HI_JACK 10
MIN_LINE_WIDTH=0.4MM
eb
MIN_NECK_WIDTH=0.2MM 101 AUD_HP_GND_JACK 11
R6617 MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD_HP_L_JACK 12
GND_AUDIO_ISO 1
0 2 AUD_HP_GND_JACK 13
62 57 56 OUT
CRITICAL 5% MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD_HP_R_JACK 14
1/10W
L6616 MF-LF MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD_HP_TYPEDET_JACK 15
ot
FERR-120-OHM-1.5A 603
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD_IP_PERPH_JACK 16
57 IN MAX97220_OUTL 1 2 MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM 101 AUD_HP_TIPDET_JACK 17
0402 L6618 CRITICAL PP3V3_AUDIO_SPDIF_JACK 18
FERR-120-OHM-1.5A 19
N

57 IN MAX97220_OUTR 1 2 20
MIN_LINE_WIDTH=0.2MM L6614 0402
MIN_NECK_WIDTH=0.1MM FERR-1000-OHM 23
61 OUT AUD_HP_TYPE 1 2 24
0402 L6615
MIN_LINE_WIDTH=0.2MM FERR-1000-OHM 22
MIN_NECK_WIDTH=0.1MM
62 61 OUT AUD_IP_PERPH_DET 1 2

MIN_LINE_WIDTH=0.2MM L6612 0402

MIN_NECK_WIDTH=0.1MM FERR-1000-OHM
61 OUT AUD_HP_TIP_DET 1 2
0402

AUD_SPDIF_OUT CRITICAL CRITICAL 2

CRITICAL 2
CRITICAL 1 C6611 1 C6613 1 C6615
94 56 IN 2 2 DZ6607 DZ6609 0.01UF 0.01UF 0.01UF
C6600 1 1 C6601 DZ6603 DZ6605 6.8V-100PF 6.8V-100PF
10%
2 16V
10%
2 16V
10%
2 16V
A 1UF
10%
10V 2
0.47UF
10%
2 10V
6.8V-100PF
402
6.8V-100PF
402
402 402
CRITICAL
CERM
402
CRITICAL
CERM
402
CERM
402
SYNC_MASTER=K62_DAVID SYNC_DATE=01/09/2011 A
X5R
402-1
X5R
402
C6604 1 CRITICAL 1 C6608 1 1
DZ6610
2
DZ6612
2 C6614 1 PAGE TITLE
1
0.01UF
10%
1
DZ6606
ESDALC5-1BM2
2
0.01UF
10%
16V
6.8V-100PF 6.8V-100PF
0.01UF
10%
16V
Audio: MLB to I/O Conn.
16V CERM 2 402 402 CERM 2 DRAWING NUMBER SIZE
CERM 2 SOD882
402
402
1 1
402
Apple Inc. 051-8442 D
1 REVISION
R
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
66 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 60 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Internal Microphone Impedance Matching

R6743
2.2K 2
AUD_INTMICBIAS 1 AUD_CODEC_MICBIAS IN 56

5%
1/16W
CRITICAL MF-LF
402
SIGNAL_MODEL=EMPTY 1
R6793 C6751 1
3.40K 4.7UF
1% 20%
1/16W 6.3V 2

D MF-LF
2 402
TANT
603-HF
GND_AUDIO_CODEC 56 57 58 59 60 61 62
D
C6795
0.1UF
62 60 IN AUD_MIC1_IN_P 1 2 AUD_MIC_INR_P OUT 56 62

1 10%
C6750 1 R6791 16V
X5R
0.0082UF 100K 402
10% 5%
25V 2
X7R
1/16W
MF-LF C6796
402 2 402 0.1UF
62 60 IN AUD_MIC1_IN_N 1 2 AUD_MIC_INR_N OUT 56 62

10%
16V
1 X5R
R6792 402
3.40K
SIGNAL_MODEL=EMPTY 1%
1/16W
MF-LF
2 402
XW6702

m
SM
AUD_MIC1_IN_G 1 2 GND_AUDIO_CODEC 56 57 58 59 60 61 62

IPHS HS Detect Debounce CKT

co
61 IN JACK_DET_V_FILT 62 61 60 59 58 56 6 =PP3V3_S0_AUDIO

1
R6797 R67981 R67681

s.
100K
10K 100K 5%
5% 5% 1/16W
L6700 1/16W 1/16W MF-LF
FERR-220-OHM MF-LF MF-LF 402 2 R6799
C 2 402 402 2
0 C

ic
98 61 59 58 56 PP4V5_AUDIO_ANALOG 1 2 AUD_IP_PERPH_DET_DB 1 2 AUD_IP_PERIPHERAL_DET 20 100
OUT
0402 5%
1/16W
NOSTUFF 6 MF-LF
JACK_DET_V_FILT 402
L6701 OUT 61

at
MIN_LINE_WIDTH=0.4MM D
FERR-220-OHM MIN_NECK_WIDTH=0.2MM
1 2
R6796 Q6701
62 61 60 59 58 56 6 =PP3V3_S0_AUDIO AUD_IP_PERPH_DET_INV 0 AUD_IP_PERPH_DET_R G
0402
1 2 2 NTZD3154NT1H
5% SOT-563-HF

em
1/16W
1 C6700 3 MF-LF
402
S
0.1UF
10% D 1
16V
2 X5R
402
R6700 Q6701 NOSTUFF
17.4K2
62 60 IN AUD_IP_PERPH_DET 1 AUD_IP_PER_DEB 5 G NTZD3154NT1H 1 C6797
62 61 60 59 58 57 56 GND_AUDIO_CODEC 1%
SOT-563-HF 0.1UF
1/16W 10%
C6740 2 16V

ch
MF-LF 1 S X5R
402
0.1UF 402
10% 4
2 16V
X5R
R6710 402

GND_AUDIO_CODEC 1
0 2 JACK_L_RTN_0
62 61 60 59 58 57 56

kS
5%
1/16W
MF-LF
402

Digital Out Headphone Out LI Insert Detect

oo
(DETECT B) (DETECT D) (DETECT C)
B 61 56 IN AUD_SENSE_A
61 56
eb IN AUD_SENSE_A 61 56 IN AUD_SENSE_A
B
57 56 IN PP5V_AUDIO_ISO CRITICAL 98 61 59 58 56 IN PP4V5_AUDIO_ANALOG
1 61 IN JACK_DET_V_FILT 1
1
R6794 R6744
R6790 20K 5.11K
10K
0.1%
1/16W R67951 1%
1/16W R67301 1
R6701
5% MF 100K MF-LF 10K 10K
ot
1/16W 2 402 5% 2 402 5% 1%
MF-LF 1/16W 1/16W 1/16W
2 402 AUD_Q6702_D3 NC MF-LF
402 2 AUD_Q6701_D6 NC MF-LF
402 2
MF-LF
2 402

6 3
N

D D
Q6700 Q6702 60 IN AUD_LI_TIP_DET
60 AUD_HP_TYPE 2 G NTZD3154NT1H AUD_HP_TYPE_INV 5 G NTZD3154NT1H
IN
SOT-563-HF SOT-563-HF

S S
AUD_LI_TIP_DET_INV
1 4

61 IN JACK_DET_V_FILT
6

AUD_HP_TIP_DET_INV D
1
R6762 Q6703
10K 2 G NTZD3154NT1H
A 5%
1/16W
MF-LF 3 6
S
SOT-563-HF
SYNC_MASTER=K62_DAVID SYNC_DATE=01/09/2011 A
2 402 3 PAGE TITLE
D D
Q6700 Q6702 DP Audio Enable 1 D AUDIO: Detects/Grounding
AUD_HP_TIP_DET 5 G NTZD3154NT1H 2 G NTZD3154NT1H DP_GPU_T29_SEL Q6703 DRAWING NUMBER SIZE
60 IN
SOT-563-HF SOT-563-HF 94 84 18 IN
5 G NTZD3154NT1H
Apple Inc. 051-8442 D
SOT-563-HF
REVISION
S S R
S 10.1.0
4 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
4
R6711 R6712 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
0 0 62 61 60 59 58 57 56 GND_AUDIO_CODEC THE POSESSOR AGREES TO THE FOLLOWING: PAGE
GND_AUDIO_CODEC 1 2 JACK_L_RTN_1 GND_AUDIO_CODEC 1 2 JACK_L_RTN_2
62 61 60 59 58 57 56

5%
62 61 60 59 58 57 56

5%
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
67 OF 110
1/16W 1/16W SHEET
MF-LF MF-LF III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
402 402 IV ALL RIGHTS RESERVED 61 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_SPACING_RULE_HEAD TABLE_PHYSICAL_RULE_HEAD

CODEC OUTPUT SIGNAL PATHS SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM

AUDIO * 0.1 MM ? AUDIODIFF * Y 0.1 MM 0.1 MM 10 MM 0.1 MM 0.1 MM

FUNCTION VOLUME/MUTE CONVERTER PIN COMPLEX SHDN DET ASSIGNMENT TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM

HP/LINE OUT 0X03 (3) 0X03 (3) 0X0A (10,D) GPIO_2 0X0A (D) SPKROUT * 0.2 MM ? SPKROUTDIFF * Y 0.6 MM 0.25 MM 10 MM 0.2 MM 0.2 MM

PRIMARY SPKRS (WFR) 0X04 (4) 0X04 (4) 0X0B (11) GPIO_3 N/A
SECONDARY SPKRS (TWT) 0X02 (2) 0X02 (2) 0X09 (09) GPIO_3 N/A TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_TYPE
SPDIF OUT N/A 0X08 (8) 0x10 (16) N/A 0X0D (B) NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_PHYSICAL_ASSIGNMENT_ITEM

AUDIODIFF * AUDIODIFF
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_HP_L_P 59
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I213
SPKROUTDIFF * SPKROUTDIFF I214 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_HP_L_N 59
CODEC INPUT SIGNAL PATHS AUD_HP_R_P 58

D FUNCTION
CONVERTER PIN COMPLEX ENABLE/CONTROL DET ASSIGNMENT
I215

I216
AUDIO_DIFFPAIR

AUDIO_DIFFPAIR
AUDIODIFF

AUDIODIFF
AUDIO

AUDIO AUD_HP_R_N 58 D
LINE IN I217 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_L_P 56 57
0X05 (5) 0X12 (12,C) N/A 0X12 (C)
SPDIF IN I218 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_L_N 56 57
0X07 (7) 0x0F (15) N/A N/A
INTERNAL MIC I211 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_R_P 56 57
0X06 (6) 0X0E (14,LEFT & RIGHT) N/A N/A
EXTERNAL MIC I212 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_R_N 56 57
0X06 (6) 0X0D (13,V22,B,LEFT) COUGAR POINT GPIO 16 COUGAR POINT GPIO 5 (RCVR INT)
COUGAR POINT GPIO 3 (PERIPH DET) I210 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_L_P 56 59

AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_L_N 56 59

I209

I208 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_R_P 56 58

AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO2_R_N 56 58

I206
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LINC_P 58
I207
I204 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LINC_N 58

I205 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_RINC_P 58

AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_RINC_N 58

I203
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LIN_P 58
I220

I219 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_RAMP_LIN_N 58

m
MIKEY RECEIVER
WRITE: 0X72 READ: 0X73
CKT
APN 353S2640
I222

I221

I224
AUDIO_DIFFPAIR

AUDIO_DIFFPAIR

AUDIO_DIFFPAIR
AUDIODIFF

AUDIODIFF

AUDIODIFF
AUDIO

AUDIO

AUDIO
AUD_RAMP_RIN_P

AUD_RAMP_RIN_N

AUD_LAMP_LINC_P

AUD_LAMP_LINC_N
58

co
I223 AUDIO_DIFFPAIR AUDIODIFF AUDIO

AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RINC_P 59

I226
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RINC_N 59
I225
I227 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_LIN_P 59
MIN_LINE_WIDTH=0.20MM
L6800 MIN_NECK_WIDTH=0.15MM
VOLTAGE=3.3V
I229 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_LIN_N 59
FERR-1000-OHM

s.
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RIN_P 59
98 62 PP3V3_S0_HS_F I228
61 60 59 58 56 6 IN =PP3V3_S0_AUDIO 1 2
I230 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LAMP_RIN_N 59
0402 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_L_C_P 57
I232

C I233 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_L_C_N 57

ic
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_R_C_P 57
I235
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_LO1_R_C_N 57
I234
R6802 I236 AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INL_P 57
0

at
49 IN =I2C_AUDIO_SCL 1 2
I238 AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INL_N 57

5% I237 AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INR_P 57

1/16W
MF-LF I239 AUDIO_DIFFPAIR AUDIODIFF AUDIO MAX97220_INR_N 57
402
AUD_SPKR_RWFR_OUT_P
R6803 1 C6800 I240 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT 58 60

em
1
0 R6806 1UF I241 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_RWFR_OUT_N 58 60

49 BI =I2C_AUDIO_SDA 1 2 10K 10%

2 10V
1 C6801 I242 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_RTWT_OUT_P 58 60

A2
5% X5R 0.1UF
5% 1/16W 402 CRITICAL I243 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_RTWT_OUT_N 58 60
1/16W MF-LF 10%
MF-LF
2 402 2 16V
X5R AVDD I244 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LWFR_OUT_P 59 60
402 402 MIN_LINE_WIDTH=0.15MM
R6804 U6806
CD3282A1
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM MIN_LINE_WIDTH=0.15MM I246 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LWFR_OUT_N 59 60

MIN_NECK_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM I245 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LTWT_OUT_P 59 60

0 WCSP
AUD_I2C_INT_L HS_MIC_BIAS

ch
100 20 OUT 1 2 SPKROUT_DIFFPAIR SPKROUTDIFF SPKROUT AUD_SPKR_LTWT_OUT_N 59 60
HS_SCL C3 SCL MICBIAS C1 I247
5% I252 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_MIC1_IN_P 60 61
1/16W
MF-LF HS_SDA B3 SDA DETECT B1 HS_SW_DET AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_MIC1_IN_N 60 61
I253
402
62 HS_RST D3 D1 I254 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_MIC_INR_P 56 61
R6805 HS_INT_L INT* BYPASS HS_RX_BP
AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_MIC_INR_N 56 61
I255
0

kS
100 21 IN AUD_IPHS_SWITCH_EN 1 2 A3 ENABLE I256 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_MIC_IN1_CONN_P 60
CRITICAL
5%
HS_HDET A1
1 C6802 1 I257 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_MIC_IN1_CONN_N 60
1/16W
MF-LF
HDET 0.01UF C6803
402 10% 4.7UF

C2 DGND

D2 AGND
1
B2 CS 2 25V
X7R
20%
R6816 R6807 402 2 6.3V
TANT
AUD_IP_PERPH_DET 0 100K 603-HF

oo
61 60 2 1 5%
IN
1/16W
5% MF-LF
1/16W
MF-LF 2 402

B 402
B
62 61 60 59 58 57 56 GND_AUDIO_CODEC
eb
1 1
R6808 R6809
1K 2.2K
ot
5% 5%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402
N

98 62 PP3V3_S0_HS_F

C6810 1 1 C6811 8
1UF
10%
0.1UF
10% MIN_LINE_WIDTH=0.15MM R6810
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM C6804 MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
10V 16V VCC MIN_NECK_WIDTH=0.1MM 0.1UF
HS_MIC_HI X5R 2 2 X5R
HS_MIC_HI_SW 1
2.2K 2 AUD_MIC_INF 1 2 AUD_MIC_INP_L
60 IN
MIN_LINE_WIDTH=0.15MM 402 402 U6807 OUT 56

MIN_NECK_WIDTH=0.1MM 5%
NX3L2G66GD 1/16W 10%
1 1Y 1Z 2 1 16V
7 1E
R6812 MF-LF
402 1 C6806 X5R
402
100K 0.0082UF
SOT996-2 5% 10%
5 2Y 2Z 6 1/16W
HS_MIC_LO MF-LF 2 25V
X7R C6805 MIN_LINE_WIDTH=0.15MM
R6814 VOLTAGE=0V
MIN_LINE_WIDTH=0.15MM AUD_SW_SEL 3 2E 2 402 MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM 402
0.1UF
MIN_NECK_WIDTH=0.1MM
0 MIN_NECK_WIDTH=0.1MM
60 57 56 GND_AUDIO_ISO 2 1
GND HS_MIC_LO_SW 1 2 AUD_MIC_INN_L OUT 56

5%
10%
1/16W
MF-LF R6815 4 16V
X5R
402
HS_RST 0 1 402
A 2 1
R6811
PLACE R6814 NEAR J6600
62

5%
1/16W 5%
0 FLP = 8.82 KHZ
FHP = 80 HZ SYNC_MASTER=K62_DAVID
PAGE TITLE
SYNC_DATE=01/09/2011 A
MF-LF 1/16W
402 MF-LF
2 402 AUDIO: Mikey
DRAWING NUMBER SIZE

62 61 60 59 58 57 56 GND_AUDIO_CODEC Apple Inc. 051-8442 D

SLP_S4 ENABLES
64 63 11 6 =PP3V3_S5_PWRCTL
C6910
R6971 0.1UF
0 2 1
100 47 46 19 5 PM_SLP_S5_L 1 2
5% 20%
1/16W 10V

D MEMVTT_EN SEQUENCE
MF-LF
402
NOSTUFF
CERM
402 D
R6972 14 74LVC08
=PP3V3_S0_PWRCTL PM_SLP_S4_L 1
0 2 100 PM_SLP_S4_1_L_R 1 TSSOP-HF R6911
100 63 47 46 32 19 5
81 74 64 6
3
33 PM_EN_P3V3_S3_FET
5%
U6900 100 S4_ENABLES 1 2 74 100
1/16W
MF-LF 2 08 5% Enable FET
402 1/16W
MF-LF
1 1 7 402
R6951 R6952
10K 10K R6912
5%
1/16W
5%
1/16W 1
33 2 PM_EN_P5V_S3_REG 71 100
MF-LF MF-LF
2 402 2 402 5% ENABLE REGULATOR
1/16W
PM_EN_DDRVTT_S0_REG MF-LF
32 63 72 100
64 63 11 6 =PP3V3_S5_PWRCTL 402
NOSTUFF
1 C6951 1
NOSTUFF
C6953
100PF 1
5% 3
0.1UF R6915

m
50V Q6911 10%
2 CERM 10K
VTT_REG_PGOOD_L 5
2 16V 1
402 MMDT3904-X-G
SOT-363-LF
X5R
402 R6916 5%
1/16W
NOSTUFF NOSTUFF
100K MF-LF 1
C6920 1
C6921
4 5% 2 402 0.47UF 0.47UF
1/16W 10% 10%
MF-LF

co
2 402
CPU_SKTOCC 94 2
6.3V
2
6.3V

R6950 6 CERM-X5R
402
CERM-X5R
402

1
10K 2 2
Q6911
64 63 PM_PGOOD_P1V05_S0_REG 100 CPUVTT_REG_PGOOD_R MMDT3904-X-G 3
100 68
5% SOT-363-LF
D
1/16W
MF-LF
NOSTUFF 1 Q6910
402 1 C6952 2N7002

s.
0.47UF 100 11 CPU_SKTOCC_L 1 G S SOT23-HF1
10%
2 6.3V
CERM-X5R 2
402
R6970
C NOSTUFF
0 C

ic
1
R6917 PLACE TOP SIDE
100 83 71 63 PM_PGOOD_P5V_S3_REG 1 2 PM_EN_USB_PWR 43 94

10K 5% NOSTUFF
5% REWORK TO POWER UP WITH NO CPU 1/16W
1
1/16W MF-LF
402
C6924
MF-LF

at
0.47UF
2 402 10%
6.3V
2 CERM-X5R
402

=PP3V3_S5_PWRCTL
64 63 11 6

em
14 74LVC08 NOSTUFF
PM_SLP_S4_L TSSOP-HF
100 63 47 46 32 19 5 4
PM_EN_DDR1V5_S3_REG
R6931
6 72 100 33
U6900 100 74 64 63 PM_PGOOD_P3V3_S0_FET 1 2 PM_EN_P1V5_S0_FET 63 74 100
5 08 5%
1/16W
7 MF-LF

ch
402
100 83 71 63 PM_PGOOD_P5V_S3_REG

64 63 11 6 =PP3V3_S5_PWRCTL
SLP_S3 ENABLES

kS
NOSTUFF OTHER RAILS ENABLED BY P3V3_S0 AND P5V_S0:
R6946 PP1V8_S0 VREG (CPU PLL)
33

2
R6955 1 2 PM_EN_P3V3_S0_FET 63 74 100
5% OUT

10K
=PP3V3_S5_PWRCTL 5%
64 63 11 6 1/16W Enable FET
MF-LF 1/16W

oo
402 MF-LF
402

1
14 74LVC08
P3V3_S5_PWRCTL_U6900_R 10 TSSOP-HF R6947
B 9
U6900
8 1
33 2 PM_EN_P5V_S0_FET OUT 74 100 B
100 64 PGOOD_P12V_S0 08 5% Enable FET
14 74LVC08 1/16W
100 47 46 36 32 26 19 5 PM_SLP_S3_L 13 TSSOP-HF
eb 7 NOSTUFF NOSTUFF MF-LF
402
2 R6944 2 R6941
11 PM_EN_P12V_S0_FET 5% 5%

10K
U6900 6 100

33
1/16W 1/16W
100 72 5 PM_PGOOD_DDR1V5_S3_REG 12 08 MF-LF MF-LF
402 402
1 1
7
PM_SLP_S3_BUF_L
ot
100

OPTION TO DELAY 1V8 Enable FET

=PP12V_S0_PWRCTL R6932 PM_EN_P1V5_S0_FET 63 74 100
6 64 81
PM_PGOOD_P3V3_S0_FET 1
33 2
100 74 64 63
PM_EN_DDRVTT_S0_REG
N

5% 32 63 72 100
1/16W
MF-LF Enable regulator OPTIONAL SEQUENCE TO DELAY 3V,1V5
402
1 NOSTUFF
R6934
82K R6990 NOSTUFF
NOSTUFF NOSTUFF NOSTUFF NOSTUFF R6930
5% 33 1 1 1 1
33 PM_EN_P3V3_S0_FET
1/16W
100 74 64 63 PM_PGOOD_P5V_S0_FET 1 2
PM_EN_P1V8_S0_REG 72 100
C6947 1
C6941 C6945 C6946 100 74 64 63 PM_PGOOD_P5V_S0_FET 1 2 63 74 100
MF-LF
0.47UF C6944 0.47UF 0.47UF 0.47UF
2 402 5%
1/16W 10% 0.47UF 10% 10% 10%
5%
1/16W
6.3V 6.3V 6.3V 6.3V
MF-LF 2 CERM-X5R
10%
6.3V
2 CERM-X5R
2 CERM-X5R
2 CERM-X5R
MF-LF
402 2 402
402 CERM-X5R 402 402 402
PM_PGOOD_P5V_S0_FET NOSTUFF
63 64 74 100
1 C6994
402
R6933
1
33 2 PM_EN_P1V5_S0_FET
0.47UF 100 74 64 63 PM_PGOOD_P5V_S0_FET 63 74 100
10%
1 6.3V 5%
R6935 2 CERM-X5R 1/16W
MF-LF
33K 402
402
5%
1/16W
MF-LF
2 402
A NOSTUFF SYNC_MASTER=K62_SIJI SYNC_DATE=01/09/2011 A
R6942 Enable regulator CPUVTT VREG/ NOTE: PM_PGOOD_P1V05_S0_REG ENABLES VCCSA REGULATOR CIRCUIT ON PAGE 70 PAGE TITLE
33
1 2 PM_EN_P1V05_S0_REG 68 100
PCH CORE
100 68 64 63
PM_PGOOD_P1V05_S0_REG
MAKE_BASE=TRUE
=PM_EN_VCCSA_S0_CPU POWER SEQUENCING ENABLES
5% DRAWING NUMBER SIZE
1/16W NOSTUFF
MF-LF
402
1 C6942
Apple Inc. 051-8442 D
1UF REVISION
10%
R

R6936 2
6.3V
CERM
10.1.0
33 402
NOTICE OF PROPRIETARY PROPERTY: BRANCH
100 74 64 63 PM_PGOOD_P3V3_S0_FET 1 2
Enable regulator THE INFORMATION CONTAINED HEREIN IS THE
5% VCCSA REGULATOR PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
OPTION TO DELAY 1V05 1/16W 100 64 PM_PGOOD_PVCCSA_S0_REG PM_EN_PVCORE_CPU 65 100 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MF-LF
402
MAKE_BASE=TRUE TO ENABLE OF CPU VCORE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
69 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 63 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PGOOD COMPARATORS FOR PP1V8_S0 AND PP12V_S0
=PP3V3_S0_PWRCTL
81 74 64 63 6
81 64 63 6 =PP12V_S0_PWRCTL
=PP3V3_S5_PWRCTL =PP3V3_S5_PWRCTL
1 64 63 11 6 6 11 63 64
R7020
1
64.9K
1%
R7017
1/16W 10K 1 NOSTUFF
MF-LF 5% R7067 1
2 402 1/16W
MF-LF 10K
R7050
1
R7007 1 R7018 2 402
5%
1/16W
1K
5%
10K PGOOD_P1V8_S0 100 MF-LF 1/16W

1
49.9K 5% 402
2 MF-LF

R7021 1% 1/16W 402

2 =PP3V3_S0_PWRCTL
10K
1/16W MF-LF
2 402
R7066 81 74 64 63 6

D
D 1%
1/16W
CRITICAL
MF-LF
402
2
PGOOD_1V8_S0_G2
3

Q7011 100 71 27 PM_PGOOD_P3V3_S5_REG 1

0 2 RSMRST_PWRGD OUT 46 100

2
MF-LF
402 8 U7080 5
MMDT3904-X-G 5% To SMC (2) 1
1V60_COMP_REF 6 LM393 6
SOT-363-LF
1/16W
MF-LF
NOSTUFF R7061
V+ SOI-HF 4
402 1 C7059 10K
7 PGOOD_1V8_S0_G1 2
Q7011 0.1UF 5%
R7002 MMDT3904-X-G 10%
1/16W
MF-LF
2.0K 2 5 GND SOT-363-LF
2 16V 2 402
6 =PP1V8_S0_PWRCTL 1 1V80_COMP_REF 1
X5R
402
1% 4
1/16W
MF-LF R7063
402 (1.67V/1.22V; 132mV Hysteresis)
PVCCSA_EN_L 1
33 2 PM_EN_PVCCSA_S0_REG_L 100
FROM THIS SMC GENERATES PM_RSMRST_L
WHICH GOES INTO RSMRST_L OF PCH 5%
DELAY IS ABOUT 200MS 1/16W
MF-LF
3 402

R7060 D
Q7010 NOSTUFF
0 2N7002
63 =PM_EN_VCCSA_S0_CPU 1 2 VTTS3PG_1
1 G S SOT23-HF1
1 C7061
=PP3V3_S3_PWRCTL 0.1UF

m
83 74 6 5%
74 64 33 6 =PP12V_S5_PWRCTL 1/16W NOSTUFF 10%
MF-LF 16V
2 2 X5R
402 1 C7066 402
1 0.1UF
R7080 1 10%
33.2K R7086 2 16V

co
1% 10K X5R
1 402
1/16W
MF-LF 74 64 33 6 =PP12V_S5_PWRCTL R7084 5%
1/16W =PP3V3_S0_PWRCTL
2 402 10K MF-LF 81 74 64 63 6
5% 2 402
1/16W
1
C7080 R70831 MF-LF PGOOD_P12V_S0 63 100
VCCSA ENABLE SIGNAL
2 402 1
1 0.1UF 49.9K 3 1
R7091 R7092

s.
R7081 20%
1%
1/16W 10K
100K 2
16V
CERM MF-LF PGOOD_12V_S0_G2 D
Q7080 10K 5%
1% 603 CRITICAL 402
2 5% 1/16W
1/16W
6
2N7002DW-X-G 1/16W MF-LF
MF-LF
U7080 SOT-363 MF-LF 2 402
C 2 402 8
D
5 G S
2 402 PM_PGOOD_PVCCSA_S0_REG
C

ic
100 9V_COMP_REF 2 LM393 Q7080 63 64 100

V+ SOI-HF 2N7002DW-X-G 4
PVCCSA_L
R7082 1 PGOOD_12V_S0_G1 2 G S
SOT-363
R7093 3

10K Q7090
2.0K 2 GND 1 2 PVCCSA_R_L 5

at
81 64 63 6 =PP12V_S0_PWRCTL 1 100 12V_COMP_REF 3 1
MMDT3904-X-G
5% SOT-363-LF
1% 4 1/16W
1/16W MF-LF 4
MF-LF 402
402
(9V/9.58V; 580mV Hysteresis) R7090 6

em
1K 2
Q7090
6 =PPVCCSA_S0_PWRCTL 1 2 VCCSAPG_1
MMDT3904-X-G
5% SOT-363-LF
1/16W NOSTUFF
MF-LF 1
402 1 C7091
0.1UF
10%
16V
2 X5R
402

ch
S0 RAILS PGOOD
VCCSA POWERGOOD

kS
=PP3V3_S0_PWRCTL 6 63 64 74 81
81 74 64 63 6 =PP3V3_S0_PWRCTL

1 C7050
0.1UF
1
C7022
0.1UF
NOSTUFF

oo
20%
10V

4
14 74LVC08
TSSOP-HF
2 CERM
2
20%
10V R7052
100 72 PM_PGOOD_P1V8_S0_REG 402 CERM
402 1
33 2
100 64 5 PGOOD_PCH_S0
B 81 74 64 63 6 =PP3V3_S0_PWRCTL
100 PGOOD_CPU_S0 5
U7000
08
6

R7032
5%
1/16W
B
MF-LF
7 1
33 2
402
PM_MXM_EN
eb 77 100

14 74LVC08 74LVC08 5% NOSTUFF

PM_PGOOD_PVCCSA_S0_REG 1 TSSOP-HF
PM_PGOOD_PVCORE_CPU 1
14
TSSOP-HF 1/16W SMC
100 64 63
3
100 65 25 5
3
MF-LF
402 R7053
U7000 U7050100 PGOOD_SYSPWROK
1
33 2 ALL_SYS_PWRGD_SMC
PM_PGOOD_P1V5_S0_FET 2 08 2 46 64 100
100 74 64 11
100 94 64 PGOOD_PCH_S0_R 08
5%
ot
7 1/16W NOSTUFF
7 MF-LF
402 R7022
33 R7094
1 2 SMC_DELAYED_PWRGD 47 64 100
33
5% 100 68 64 63 PM_PGOOD_P1V05_S0_REG 1 2
81 74 64 63 6 =PP3V3_S0_PWRCTL 1/16W
N

MF-LF 5%
402 1/16W
NOSTUFF MF-LF
=PP3V3_S0_PWRCTL PM_ASW_PWRGD
81 74 64 63 6
R7099 402 19 64 100

R7029 ALL_SYS_PWRGD 1
33 2 PM_PECI_PWRGD
0 14 74LVC08 100 94 46 100
14 74LVC08 PGOOD_SYSPWROK_R 13 TSSOP-HF
81 74 64 63 6 =PP3V3_S0_PWRCTL
100 94 PGOOD_CPU_UNCORE 10 TSSOP-HF R7035 1 2 100
11
5%
1/16W
8 100 33 ALL_SYS_PWRGD_SMC
5%
U7050 R7023 MF-LF NOSTUFF
PGOOD_PCH_S0 1 2 1/16W 402
9
U7050 64 5 46 64 100
MF-LF 100 77 PM_MXM_PGOOD 12 08 33 1 C7056
08 5% 402 1 2 ALL_SYS_PWRGD_R 5 32 100
1/16W
7
OUT 0.47UF
MF-LF 5% 10%
7
14 74LVC08 402 1/16W
R7028 2 6.3V
CERM-X5R
MF-LF
100 74 63 PM_PGOOD_P5V_S0_FET 13 TSSOP-HF 402 33 402
1 2 PM_SYS_PWRGD 19 32 100
11 PGOOD_5V_1V05_3V3 =PP3V3_S0_MXM =PM_MXM_PGOOD_PULLUP
U7000 100 94 77 76 21 6 77
5%
12 08 PULL-UP ON MXM PAGE 1/16W
MF-LF
402
7

NOSTUFF
R7024 R7054 R7078
A 1
0 2 100 94 64 PGOOD_PCH_S0_R 1
0 2 100 PM_PCH_PWRGD_R
1
33 2 PM_PCH_PWRGD 19 21 100 SYNC_MASTER=K62_SIJI SYNC_DATE=01/09/2011 A
5% PAGE TITLE

=PP3V3_S0_PWRCTL
5%
1/16W
MF-LF
5%
1/16W
MF-LF NOSTUFF
1/16W
MF-LF
402
NOSTUFF POWER SEQUENCING PGOOD
74 64 63 6 =PP3V3_S0_PWRCTL
6 63 64 74 81
402
1
402
1 C7023
1 C7055 DRAWING NUMBER SIZE
81
74LVC08 OPTION FOR SMC TO OUPUT R7031OPTION FOR PCH PWROK
TO BE DRIVEN BY SAME
AND SYSPWROK
SIGNAL 0.47UF
0.47UF 051-8442 D
TSSOP-HF 74LVC08 DELAYED PWRGD (BY 99MS) R7030 100K
5% 10%
10%
2 6.3V
Apple Inc. REVISION
14 14 0 1/16W 2 6.3V CERM-X5R R
100 68 64 63 PM_PGOOD_P1V05_S0_REG 10 100 94 PGOOD_3V3_1V05 4 TSSOP-HF 100 64 47 SMC_DELAYED_PWRGD 1 2 MF-LF
CERM-X5R
402
402
10.1.0
8 6 PM_PGOOD_CK505 5% 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
U7000 U7050 26

100 74 63 PM_PGOOD_P3V3_S0_FET 9 08 100 74 64 11

PM_PGOOD_P1V5_S0_FET 5 08
1/16W
MF-LF R7079 THE INFORMATION CONTAINED HEREIN IS THE
402
1
33 2
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
7 7
PM_ASW_PWRGD 19 64 100 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5%
1/16W
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
70 OF 110
MF-LF SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
ALL_SYS_PWRGD CIRCUIT 402
IV ALL RIGHTS RESERVED 64 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

50 17 13 6 =PPVAXG_S0_CPU
SM R7160
1K
CPU CORE/AXG REG 1.1V/75A O/P= PPVCORE_S0_CPU_REG
1 98 2 VR_AXG_VSNS_XW_P
VOLTAGE=1.1V
1 2
R7162 =PP3V3_S0_VRD
OMIT NET_PHYSICAL_TYPE=SNS_DIFF 5% 10 98 VR_AXG_VSEN 6 65 68

XW7120 R7161 1/16W

MF-LF
1 2
R7127
1
0 2 VR_AXG_VSNS_R_P
402 5%
1/16W
SIGNAL_MODEL=EMPTY
67 6
=PP5V_S0_VRD 2
2.2 1 98 65 PP5V_S0_CPU_VCORE_VCC
MF-LF
402 NOSTUFF 5% MAX_NECK_LENGTH=3MM
5%
98 13 IN CPU_VAXG_SENSE_P 1/16W
MF-LF
1 C7155 1/8W
MF-LF
MIN_NECK_WIDTH=0.3MM
MIN_LINE_WIDTH=0.6MM
1
R7195
402 1.25 mOhm loadline 0.0022UF 805
VOLTAGE=5V 10K
98 13 IN CPU_VAXG_SENSE_N 10%
50V 5%

D R7163
0
R7164
10 VR_AXG_RGND
2 CERM
402
1/16W
MF-LF
2 402
D
1 2 VR_AXG_VSNS_R_N 1 2 98

5% 5%
1 C7157 CPU VCORE
XW7130
1/16W
MF-LF
R7165
1/16W
MF-LF
1 C7156
SM 402
1K
402
10%
0.0022UF 0.0022UF
10% 1 C7114 VOUT = VCORE
1 2 1 2 50V
98 VR_AXG_VSNS_XW_N
VOLTAGE=0V
50V
2 CERM 2 CERM R7157 1 10UF CPUVCORE-3PH PEAK = 75A
NET_PHYSICAL_TYPE=SNS_DIFF 5% 402 402 10%
1K 25V 1
OMIT 1/16W
MF-LF 5% 2 X5R R7106 AVG = 55A
402 65
AGND_CPU =PP3V3_S0_VRD 1/16W
MF-LF
805
1
NOSTUFF 0
68 65 6
402 2
AGND_CPU R7101 5%
1/16W VR_AXG_PWM
0 MF-LF OUT 67 98
C7116 R7128 5%
1/16W 1NOSTUFF 1
NOSTUFF
2 402
0.0022UF
1 2 98 VR_SEN_R2 1
249 2
MF-LF
2 402
R7102 R7104
0
1
R7107
0 5% 0

2
1
R7189 C7113

RT7103
1% 1 5% 1/16W 5%
10% 1/16W 1/16W MF-LF 1/16W
50V MF-LF 1K 0.1UF MF-LF 2 402 MF-LF

6.8K
0603
CERM 402 5% 10% 2 402 2 402
402 1/16W
MF-LF
16V
2 X5R R7108

m
OMIT OMIT 2 402 402 NOSTUFF NOSTUFF 1
110 2
R7129 R7130 98 VR_SEN_R1 NOSTUFF 1
R7103 1R7105
0 806 1 0 1%
R7131 R7100

1
1 2 98 VR_SEN_R3 1 2
5% 0 1/16W
10 0 5% MF-LF
1% 1/16W 1/16W 402
5% 1 2 5% MF-LF

co
1/16W 1/16W MF-LF
NOSTUFF LOCAL 5V

35
MF-LF 1/16W 2 402 DIFFERENTIAL_PAIR=VR_AXG_ISNS
MF-LF 5% MF-LF 2 402 1 C7101
402 402 1/16W
MF-LF
1 C7115 98 VR_AXG_TM 2 402 1 C7100 0.1UF
1 C7102 VR_AXG_ISNS_P IN 67 98

402 0.01UF VCC 10% 220PF

220PF 10%
VR_AXG_ISNS_N
20%
16V
98 VR_AXG_PWM_R 5% 2 16V
X5R 2 50V
C7117
2 CERM
402
U7100 25V
2 CERM 402 X7R-CERM
402
IN 67 98

R7132 ISL6364 402 DIFFERENTIAL_PAIR=VR_AXG_ISNS

s.
3900PF
9.09K2 98 VR_AXG_COMP_RC 1 2 QFN
1 AGND_CPU 65 23 TMS PWMS 26 AGND_CPU
65
1%
1/16W 10% 20 ISENS+ 24 98 VR_AXG_ISNS_R_P R7109
1.02K2
C MF-LF 50V VSENS
ISENS- 25 VR_AXG_ISNS_R_N 1 C

ic
402 X7R OMIT 98
C7118 0402 R71411 2 1.21K 98 VR_AXG_HFREQ_COMP 16 HFCOMPS/DVCS
1 0
1% 1/16W 402 MF-LF
39PF 1% 1/16W MF-LF 402 PWM1 38 98 VR_CPU_PWM1_R R7110 2 VR_CPU_PWM1 OUT 66 98
19 1/16W 5% MF-LF 402
1 2 98 VR_AXG_FB FBS ISEN1+ 46 VR_CPU_ISNS1_P IN 66 98
DIFFERENTIAL_PAIR=VR_CPU_ISNS1

at
ISEN1- 45 98 VR_CPU_ISNS1_R_N
5%
50V
21 RGNDS 1 C7103 1 C7104 VR_CPU_ISNS1_N
C7119 R7133 CERM
18 PWM2 36 98 VR_CPU_PWM2_R 220PF 0.1UF DIFFERENTIAL_PAIR=VR_CPU_ISNS1
IN 66 98

4700PF 402 98 VR_AXG_COMP COMPS 10% 10%

VR_CPU_PSICOMP2 1 2 98 VR_CPU_PSICOMP1 301 ISEN2+ 42 50V
2 X7R-CERM 2 16V
X5R
98 1 2
13 402
PM_PGOOD_PVCORE_CPU VR_RDY ISEN2- 41 VR_CPU_ISNS2_R_N

em
100 64 25 5 OUT 98 402
10%
1% AGND_CPU
1/16W 65
100V
CERM
MF-LF
402
98 65 PP5V_S0_CPU_VCORE_VCC R7140 1 2 953K
MF-LF 402
VR_AXG_TCOMP 30 BTS_DES_TCOMPS
98 PWM3 39 98 VR_CPU_PWM3_R R71111 2 1.02K
R7134
402 C7120 R7156 1 2 953K
1/16W
1%
98 VR_CPU_SUTH 29 BT_FDVID_TCOMP ISEN3+ 48 0
1% 1/16W MF-LF 402
VR_CPU_PWM2
390PF 1%1/16W MF-LF 402
R7142 1 216.5K OMIT 98 VR_CPU_N_PSI 28 NPSI_DE_IMAX R7112 2 1 OUT 66 98
249 ISEN3- 47 98 VR_CPU_ISNS3_R_N 1/16W 5% MF-LF 402
1 2 1/16W 1% MF-LF402 VR_CPU_ISNS2_P
1 2 98 VR_CPU_FB_RC R7143 1 215.0K OMIT 98 VR_CPU_FDVID 27 ADDR_IMAXS_TMAX DIFFERENTIAL_PAIR=VR_CPU_ISNS2
IN 66 98

1% 1% 1/16W MF-LF 402 PWM4 37 98 VR_CPU_PWM4_R

1/16W 10%
50V
98 13 IN
CPU_VIDSCLK 12 SVCLK
ISEN4+ 44
1 C7105 1 C7106 VR_CPU_ISNS2_N
MF-LF CPU_VIDALERT_L 11 SVALERT* 0.1UF IN 66 98

ch
402 CERM 98 13 OUT 220PF DIFFERENTIAL_PAIR=VR_CPU_ISNS2
402 CPU_VIDSOUT 10 SVDATA ISEN4- 43 98 VR_CPU_ISNS4_R_N 10% 10%
16V
98 13 BI 50V 2 X5R
2 X7R-CERM
402 402
OMIT 4 VSEN FSS_DRPS 22 VR_AXG_SW_FREQ
98
AGND_CPU
R7135 R7136 3 R71131
65
2 1.02K
1.33K2
1 98 VR_CPU_FB_R 1
1.02K2 RGND VR_RDYS 17 PM_PGOOD_PVAXG 1% 1/16W MF-LF 402
1 0

kS
98 VR_CPU_FB 7 FB R7114 2 VR_CPU_PWM3 OUT 66 98
1% 1%
98 VR_CPU_PSICOMP 6 IMONS 14 VR_AXG_IMON 1/16W 5% MF-LF 402
1/16W
R7121 1/16W PSICOMP VR_CPU_ISNS3_P IN 66 98
MF-LF MF-LF DIFFERENTIAL_PAIR=VR_CPU_ISNS3
402 10 402 OMIT FS_DRP 34 VR_CPU_SW_FREQ
5% 1/16W
1 2
MF-LF 402
R7144
1/16W
1 2 2.55K
MF-LF 402
98 VR_CPU_HFREQ_COMP 5 HFCOMP
98
1 C7107 1 C7108
1%
RAMP_ADJ 2 98 VR_CPU_RAMP_ADJ 220PF 0.1UF VR_CPU_ISNS3_N
98 VR_CPU_COMP 8 COMP 10% 10%
16V DIFFERENTIAL_PAIR=VR_CPU_ISNS3
IN 66 98

EN_VTT 40 2 50V 2 X5R

oo
32 SICI
PM_EN_PVCORE_CPU IN 63 100 X7R-CERM 402
C7122 98 VR_CPU_IAUTO 402
82PF AGND_CPU 65
98 50 VR_CPU_IMON 9 IMON EN_PWR 1 98 VR_EN_PWR_OVP R71151 2 1.02K
B 1 2

OMIT
100
11 CPU_PROCHOT_L
OUT
R7199 1 2 0 VR_HOT_L 15 VR_HOT*
RSET 33 CPUVCORE-4PH
0
1% 1/16W MF-LF 402
B
5%
50V
47 5% 1/16W MF-LF 402 98 VR_CPU_TM 31 R7184 2 1 VR_CPU_PWM4 OUT 67 98
TM
CERM C7123 THRM 1/16W 5% MF-LF 402 VR_CPU_ISNS4_P
R7145 402
eb DIFFERENTIAL_PAIR=VR_CPU_ISNS4
IN 67 98

4.99K2 820PF PAD CPUVCORE-4PH CPUVCORE-4PH

1 98 VR_CPU_FB2 1 2
R7149 1 R7150 1 R7151 1
OMIT 1 C7187 1 C7188

49
1 220PF 0.1UF VR_CPU_ISNS4_N
1%
1/16W 10%
1 C7124 R7152 1 30.1K 26.1K 255K R7158 R7120 1 1 R7155 10% 10%
16V DIFFERENTIAL_PAIR=VR_CPU_ISNS4
IN 67 98

MF-LF 50V 0.01UF 0 NOSTUFF 1% 1% 1% 255K 105K 50V

2 X7R-CERM 2 X5R
402 CERM 20% 5% 1/16W 1/16W 1/16W 1% 98 VR_RSET 124K 402
402 16V 1/16W MF-LF MF-LF MF-LF 1/16W 1% 1% 402
2 CERM R7146 1 R7147 1 R7148 1 1
R7118
ot
MF-LF 402 2 402 2 402 2 MF-LF OMIT 1/16W 1/16W AGND_CPU 65
402 402 2 110 90.9 54.9 2 402 R7119 1 MF-LF
402 2
MF-LF
2 402
1.18M R71851 2 1.02K
5% 1% 1% 1% 1% 1/16W MF-LF 402
98 65 PP5V_S0_CPU_VCORE_VCC 1/16W 1/16W 1/16W 12.4K 1/16W
MF-LF MF-LF MF-LF 1% MF CPUVCORE-4PH
402 2 402 2 402 2 1/16W 2 402
MF-LF
N

402 2 NOSTUFF
2

AGND_CPU
RT7104

65
PP5V_S0_CPU_VCORE_VCC R7181 1
R7159 1 =PPVCCIO_S0_CPU 65 98
10K
6.8K

16 13 11 10 6
0603

1K NOSTUFF
5% 1 C7132 R7179 1 AGND_CPU 65
65 AGND_CPU 1
R7122 5%
1/16W
1/16W 0.1UF 100K MF-LF
MF-LF 10% 1 C7126 100K 5% 402 2
402 2 5%
2 16V
X5R 0.1UF 1/16W 1/16W
MF-LF
MF-LF AGND_CPU
1

402 10%
2 402
65
16V 402 2
2 X5R PP12V_S0_CPU_FLTRD 65 66 67 98
402
65 AGND_CPU 1 C7112 PP5V_S0_CPU_VCORE_VCC 65 98
MAX_NECK_LENGTH=3MM 1 0.1UF NOSTUFF
65 AGND_CPU
1
OMIT MIN_NECK_WIDTH=0.3MM
MIN_LINE_WIDTH=0.6MM
R7123 10% R7180 1
R7153 2.74K

VR_EN_PWR_OVP_R
50 16 13 6 =PPVCORE_S0_CPU 845
VOLTAGE=0V 1%
16V
2 X5R 100K
SM R7166 1%
1/16W
MF-LF
402 5%
1/16W
1K C7127
VR_CPU_IMON_R

1/16W 1 MF-LF
2 402
1 98 2 VR_CPU_VSNS_XW_P 1 2
R7167 MF-LF 402 2

XW7101
27.0NF

2
OMIT
VOLTAGE=1.1V
NET_PHYSICAL_TYPE=SNS_DIFF 5% 10 98 VR_CPU_VSEN 2 402 10%
1/16W 1 2 10V
2 X5R
R7168 50 98

SM
OUT
XW7123 MF-LF
A

OMIT
1
0 402 5% SIGNAL_MODEL=EMPTY 1
OMIT 402 R7124 A
1 2 VR_CPU_VSNS_R_P 1/16W
R7154 6.65K OMIT SYNC_MASTER=K62_AARON SYNC_DATE=N/A

1
MF-LF
NOSTUFF 9.76K 1% 1 PAGE TITLE
5% 402 98
1/16W R7125
98 13 IN CPU_VCC_SENSE_P 1/16W
MF-LF
1 C7158
0.0022UF
98
1%
1/16W
MF-LF
MF-LF
2 402 5%
1K VREG: PPVCORE_S0_CPU
402 1.25 mOhm loadline C7111

VR_AXG_IMON_R
1
98 13 IN CPU_VCC_SENSE_N 10% 2 402
AGND_CPU
1/16W DRAWING NUMBER SIZE
2 50V
CERM 65
MF-LF 0.1UF 051-8442 D
R7169 R7170 402 152-0118 2 402 10% Apple Inc.
0 10 AGND_CPU CRITICAL 2 16V REVISION
2 VR_CPU_VSNS_R_N 98 VR_CPU_RGND 65 X5R
1 1 2
L7100 1
OMIT 402 R
10.1.0
5% 5%
1 C7160
0.24UH+/-20%-0.00042OHM-40A R7126 NOTICE OF PROPRIETARY PROPERTY: BRANCH
XW7133
1/16W
MF-LF
R7171
1/16W
MF-LF
1 C7159 0.0022UF =PP12V_S0_VRD 1 2 PP12V_S0_CPU_FLTRD 1%
13.7K
THE INFORMATION CONTAINED HEREIN IS THE
SM 402 402 0.0022UF 10%
6
NET_PHYSICAL_TYPE=POWER
65 66 67 98
98 1/16W PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
1 2 1
1K 2
10% 50V SDP1108M-TH VOLTAGE=12V MF-LF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
98 VR_CPU_VSNS_XW_N 50V 2 CERM
2 CERM 2 402
VOLTAGE=0V
NET_PHYSICAL_TYPE=SNS_DIFF 5% 402 402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 71 OF 110
OMIT 1/16W
MF-LF
CPU CORE INPUT FILTER II NOT TO REPRODUCE OR COPY IT
SHEET
AGND_CPU 65 AGND_CPU III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
402 65
IV ALL RIGHTS RESERVED 65 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
98 67 65
PP12V_S0_CPU_FLTRD
NET_SPACING_TYPE=POWER
CRITICAL CRITICAL CRITICAL CRITICAL
1 1 THESE TWO CAPS ARE FOR EMC
C7272 C7270 1
C7271 Q7201
CRITICAL
CRITICAL CRITICAL
220UF 220UF 220UF NOSTUFF
376S0772 IRF6710
1
C7205 1 1 C7215 1 1
20% 20% 20% 1 R7205 R7201 S1 220UF C7206 C7207 C7281 1 C7210 1 C7211
10UF
2 16V
ALUM-POLY
8X7-TH
2 16V
ALUM-POLY
8X7-TH
2 16V
ALUM-POLY
8X7-TH
R7202
5%
1/10W
MF-LF
10
5%
1/10W
0
1
1 10
5%
1/10W
MF-LF
PHASE 1 D
1
2
5
20%
2 16V
ALUM-POLY
8X7-TH
10UF
10%
2 16V
X5R-CERM
0805
10%
2 16V
X5R-CERM
0805
1UF
10%
2 16V
X5R
603
1UF
10%
2 16V
X5R
603
2 50V
X7R
0.001UF
10%

402
2 25V
X5R
1UF
10%

402
603 2 MF-LF
603 2 2 603 4 G 6
98 VR_CPU_DRV1_VCC 98 VR_CPU_DRV1_PVCC CRITICAL R7208
NET_PHYSICAL_TYPE=POWER 3 S CRITICAL 0.0005
NO_TEST=TRUE 1 C7201
NET_PHYSICAL_TYPE=POWER L7201 1%
PPVCORE_S0_CPU_REG
D 98 VR_CPU_DRV1_UVCC
NET_PHYSICAL_TYPE=POWER
NO_TEST=TRUE
1UF
10%
2 16V
98 VR_CPU_BOOT1_RC
NET_PHYSICAL_TYPE=VR_CTL_PHY SWITCH_NODE=TRUE
0.24UH+/-20%-0.00042OHM-40A
1 2 PPVCORE_S0_CPU_REG1
1W
MF
0612
6 66 67 D
NO_TEST=TRUE X5R NET_SPACING_TYPE=VR_CONTROL 1 2
603
R72041 DIDT=TRUE 3 4

9
SDP1108M-TH

7
NOSTUFF
NO_TEST=TRUE
VCC UVCC LVCC
5%
0 1 C7203 R72061
U7201 1/10W 0.22UF 2.2
MF-LF 10% 5%
ISL6622 603 2 16V 1/8W
2 X7R MF-LF
DFN 98 VR_CPU_DRV1_BOOT 603 805 2
VR_CPU_DRV1_GDSEL 3 GDSEL
98
BOOT 2 NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL
NO_TEST=TRUE
NOSTUFF VR_CPU_PH1_SNUB 98
C7202 1 1 C7200 1
R7207 UGATE 1 98 VR_CPU_DRV1_UGATE 1 2 6 7
CRITICAL DIDT=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY
1UF 1UF 0 NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY NET_SPACING_TYPE=VR_CONTROL D CRITICAL DIDT=TRUE
10% 10% 5% PHASE 10 98 VR_CPU_PHASE1 1 C7208 NET_SPACING_TYPE=SWITCHNODE
16V 2
X5R 2 16V
X5R 1/10W
MF-LF NET_PHYSICAL_TYPE=POWER DIDT=TRUE NET_SPACING_TYPE=SWITCHNODE Q7202 0.001UF
603 603 603 4 PWM LGATE 6 98 VR_CPU_DRV1_LGATE 5 G IRF6795 10%
2 DIDT=TRUE DIRECTFET-MX 50V
2 CERM
NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY NET_SPACING_TYPE=VR_CONTROL S
THRML 402
GND PAD NOSTUFF
376S0771 3 4 VR_CPU_ISNS1_P

11
OUT 65 98

m
VR_CPU_PWM1
98 65 IN VR_CPU_ISNS1_N OUT 65 98

co
CRITICAL THESE TWO CAPS ARE FOR EMC
CRITICAL CRITICAL CRITICAL
376S0772 Q7221
IRF6710
1
C7225 1 C7226 1 C7229 1 C7282 1 C7227 1 C7230 1 C7231
1
PHASE 2 S1 220UF 10UF 10UF 1UF 1UF 0.001UF 1UF

s.
NOSTUFF R7221
R72221 R72251 10
1 20%
2 16V
10%
16V
10%
16V
10% 10% 10% 10%
2 16V 2 16V 2 50V 2 25V
D
10 5% 2 ALUM-POLY 2 X5R-CERM 2 X5R-CERM X5R X5R X7R X5R
5% 0 1/10W 8X7-TH 0805 0805 603 603 402 402
1/10W 5% MF-LF 5
1/10W
C MF-LF MF-LF 2 603 4 G 6
C

ic
603 2 603 2
VR_CPU_DRV2_VCC CRITICAL
98
NET_PHYSICAL_TYPE=POWER VR_CPU_DRV2_PVCC 3 S
CRITICAL
R7228
NO_TEST=TRUE 98 0.0005
98 VR_CPU_DRV2_UVCC NET_PHYSICAL_TYPE=POWER
98 VR_CPU_BOOT2_RC L7221 1%
1W PPVCORE_S0_CPU_REG
0.24UH+/-20%-0.00042OHM-40A

at
NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY MF 6 66 67
NET_PHYSICAL_TYPE=POWER NET_SPACING_TYPE=VR_CONTROL SWITCH_NODE=TRUE 98 PPVCORE_S0_CPU_REG2
0612
NOSTUFF
1 C7221 1 2 1 2
C7222 1 1 C7220 1UF R72241 DIDT=TRUE 3 4
7

SDP1108M-TH
9

1UF 10% NO_TEST=TRUE 1 C7223

10% 1UF VCC PVCC
16V
2 X5R 0 NOSTUFF
10% 152-0118
16V 2 16V 603 5% 0.22UF R72261

em
X5R
603
2 X5R
603
U7221 1/10W
MF-LF
10%
2 16V 2.2
ISL6612 603 2 X7R 5%
603 1/8W
QFN1 MF-LF
NO_TEST=TRUE 805 2
4 PWM BOOT 2 98 VR_CPU_DRV2_BOOT
98 65 IN
VR_CPU_PWM2 CRITICAL NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL VR_CPU_PH2_SNUB 98
UGATE 1 98 VR_CPU_DRV2_UGATE 1 2 6 7
NET_PHYSICAL_TYPE=VR_CTL_PHY
NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL D CRITICAL DIDT=TRUE
PHASE 10 98 VR_CPU_PHASE2 1 C7228 NET_SPACING_TYPE=SWITCHNODE

ch
98 VR_CPU_DRV2_GDSEL 3 NC Q7222
NET_PHYSICAL_TYPE=POWER DIDT=TRUE NET_SPACING_TYPE=SWITCHNODE 0.001UF
NOSTUFF 8 NC LGATE 6 98 VR_CPU_DRV2_LGATE 5 G IRF6795 10%
1 DIRECTFET-MX 50V
2 CERM
R7227 THRML
NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL S 402
0 GND PAD NOSTUFF
5% 3 4 VR_CPU_ISNS2_P
5

376S0771
11

1/10W OUT 65 98
MF-LF

kS
2 603
VR_CPU_ISNS2_N OUT 65 98

oo
CRITICAL CRITICAL THESE TWO CAPS ARE FOR EMC
CRITICAL CRITICAL
B 1
Q7241
IRF6710
1
C7245
220UF
1 C7246
10UF
1 C7249
10UF
1 C7283
1UF
1 C7247
1UF
1 C7250
0.001UF
1 C7251
1UF
B
R72421
10
NOSTUFF
R7245 1
R7241
10 PHASE 3 376S0772 S1
1
20%
2 16V
ALUM-POLY
10%
2 16V
10%
16V
2 X5R-CERM
10%
16V
2 X5R
10%
2 16V
10%
50V
2 X7R 2 X5R
10%
25V
5% 0 5%
1/10W
eb D
2 8X7-TH
X5R-CERM
0805 0805 603
X5R
603 402 402
1/10W 5% MF-LF
MF-LF 1/10W 5
603 2 MF-LF 2 603
603 2 4 G 6
98 VR_CPU_DRV3_VCC CRITICAL R7248
NO_TEST=TRUE NET_PHYSICAL_TYPE=POWER 98 VR_CPU_DRV3_PVCC 3 S CRITICAL 0.0005
98 VR_CPU_DRV3_UVCC NET_PHYSICAL_TYPE=POWER 98 VR_CPU_BOOT3_RC L7241 1%
1W PPVCORE_S0_CPU_REG
ot
NET_PHYSICAL_TYPE=POWER NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY 0.24UH+/-20%-0.00042OHM-40A MF 6 66 67
1 C7241 NET_SPACING_TYPE=VR_CONTROL SWITCH_NODE=TRUE 98 PPVCORE_S0_CPU_REG3
0612
1 2 1 2
NOSTUFF 1UF R72441 DIDT=TRUE
C7242 1 1 C7240 3 4
7

SDP1108M-TH
9

10% NO_TEST=TRUE 1 C7243

1UF 1UF VCC
16V
2 X5R 0 NOSTUFF 152-0118
PVCC 0.22UF
R72461
N

10% 10% 603 5% 10%

16V 2
X5R 2 X5R
16V U7241 1/10W
MF-LF 2 16V
X7R 2.2
603 603 ISL6612 603 2 603 5%
376S0771 1/8W
QFN1 MF-LF
98 VR_CPU_DRV3_BOOT NO_TEST=TRUE 805 2
4 PWM BOOT 2
NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL 1 2 6 7
VR_CPU_PWM3 CRITICAL VR_CPU_PH3_SNUB 98
98 65 IN UGATE 1 98 VR_CPU_DRV3_UGATE NO_TEST=TRUE D CRITICAL
NET_PHYSICAL_TYPE=VR_CTL_PHY
PHASE 10
NET_PHYSICAL_TYPE=VR_CTL_PHY
98 VR_CPU_PHASE3
DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL Q7242 DIDT=TRUE
1 C7248 NET_SPACING_TYPE=SWITCHNODE
98 VR_CPU_DRV3_GDSEL 3 NC 5 G IRF6795
NOSTUFF NET_PHYSICAL_TYPE=POWER DIDT=TRUE NET_SPACING_TYPE=SWITCHNODE DIRECTFET-MX 0.001UF
1 8 NC LGATE 6 S 10%
R7247 98 VR_CPU_DRV3_LGATE 2 50V
CERM VR_CPU_ISNS3_P
0 THRML 3 4 402 OUT 65 98
5% GND PAD NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL NOSTUFF
1/10W NO_TEST=TRUE
VR_CPU_ISNS3_N
5

MF-LF 65 98
OUT
2 603

A A
OUTPUT BULK DECOUPLING: 128S0209
PPVCORE_S0_CPU_REG
SYNC_MASTER=K62_AARON
PAGE TITLE
SYNC_DATE=N/A

6 66 67 VREG: CPU CORE - PHASES 1-3

DRAWING NUMBER SIZE
75A MAX 051-8442 D
Apple Inc.
1
C7260 1
C7261 1
C7262 1
C7263 1
C7264 1
C7265 R
REVISION
330UF-0.0045OHM
20% 20%
330UF-0.0045OHM 330UF-0.0045OHM
20%
330UF-0.0045OHM
20%
330UF-0.0045OHM
20%
330UF-0.0045OHM
20%
10.1.0
2 2V
POLY
2 2V
POLY
2 2V
POLY
2 2V
POLY
2 2V
POLY
2 2V
POLY
NOTICE OF PROPRIETARY PROPERTY: BRANCH
CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
72 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 66 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PP12V_S0_CPU_FLTRD THESE TWO CAPS ARE FOR EMC

D 98 67 66 65
CPUVCORE-4PH CPUVCORE-4PH CPUVCORE-4PH CPUVCORE-4PH
D
CRITICAL CRITICAL CRITICAL CRITICAL CPUVCORE-4PH CPUVCORE-4PH CPUVCORE-4PHCPUVCORE-4PH

CPUVCORE-4PH
CPUVCORE-4PH Q7301 1
C7304 1 C7305 1 C7306 1 C7307 1 C7319 1 C7308 1 C7309
1 IRF6710 220UF 10UF 10UF 1UF 1UF 1UF 1UF
R73111
5%
1/10W
10
NOSTUFF
R73121
5%
0
R7313
5%
10
1/10W
MF-LF
PHASE 4 376S0772 S1
D
1
2
20%
2 16V
ALUM-POLY
8X7-TH
10%
16V
2 X5R-CERM
0805
10%
16V
2 X5R-CERM
0805
2
10%
16V
X5R
603
10%
2 16V
X5R
603
10%
2 16V
X5R
603
10%
2 16V
X5R
603
MF-LF 1/10W 5
603 2 MF-LF 2 603 CPUVCORE-4PH
603 2 4 G 6
98 VR_CPU_DRV4_VCC CPUVCORE-4PH CRITICAL R7301
NET_PHYSICAL_TYPE=POWER 98 VR_CPU_DRV4_PVCC 3 S CRITICAL 0.0005
NO_TEST=TRUE
98 VR_CPU_DRV4_UVCC NET_PHYSICAL_TYPE=POWER 98 VR_CPU_BOOT4_RC L7301 1%
1W PPVCORE_S0_CPU_REG
NET_PHYSICAL_TYPE=POWER NO_TEST=TRUE CPUVCORE-4PH NET_PHYSICAL_TYPE=VR_CTL_PHY 0.24UH+/-20%-0.00042OHM-40A MF 6 66
1 C7311 NET_SPACING_TYPE=VR_CTL SWITCH_NODE=TRUE 98 PPVCORE_S0_CPU_REG4
0612
CPUVCORE-4PH 1 2 1 2
NOSTUFF 1UF R73031 DIDT=TRUE CPUVCORE-4PH
C7312 1 1 C7310 3 4

7
CPUVCORE-4PH SDP1108M-TH

9
10% NO_TEST=TRUE 1 C7303
1UF 1UF VCC
16V
2 X5R 0 CPUVCORE-4PH NOSTUFF 152-0118
PVCC 0.22UF
10% 10% 603 5% 10% R73021
16V
X5R 2 2 X5R
16V U7301 1/10W
MF-LF 2 16V 2.2

m
603 603 603 2 X7R 5%
ISL6612 603
376S0771 1/8W
QFN1 MF-LF
98 VR_CPU_DRV4_BOOT NO_TEST=TRUE 805 2
4 PWM BOOT 2 NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL 1 2 6 7
VR_CPU_PWM4 CRITICAL
NO_TEST=TRUE CRITICAL
VR_CPU_PH4_SNUB 98
98 65
UGATE 1 98 VR_CPU_DRV4_UGATE

co
IN D NET_PHYSICAL_TYPE=VR_CTL_PHY
PHASE 10
NET_PHYSICAL_TYPE=VR_CTL_PHY
98 VR_CPU_PHASE4
DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL Q7302 DIDT=TRUE
1 C7302 NET_SPACING_TYPE=SWITCHNODE
98 VR_CPU_DRV4_GDSEL 3 NC 5 G IRF6795
NOSTUFF NET_PHYSICAL_TYPE=POWER DIDT=TRUE NET_SPACING_TYPE=SWITCHNODE DIRECTFET-MX 0.001UF
1 8 NC LGATE 6 S 10%
R7310 98 VR_CPU_DRV4_LGATE NO_TEST=TRUE
CPUVCORE-4PH 2 50V
CERM VR_CPU_ISNS4_P
0 GND
THRML 3 4 402 OUT 65 98

s.
5% PAD NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL NOSTUFF
1/10W
VR_CPU_ISNS4_N

11
MF-LF 65 98
OUT
2 603

C C

ic
at
em
AXG PHASE (MAX 15A)

ch
=PP5V_S0_VRD 98 67 66 65
PP12V_S0_CPU_FLTRD THESE TWO CAPS ARE FOR EMC
65 6

CRITICAL CPUVCORE-4PH
CRITICAL
1 C7325 1 1 C7329
R7321 C7326

kS
10UF 10UF 1UF
1 376S0906 10% 10% 10%
0 2 16V 16V 2 16V
5% CRITICAL X5R-CERM 2 X5R-CERM X5R
1/10W 98 VR_AXG_BOOT1_RC 0805 0805 603
MF-LF NET_PHYSICAL_TYPE=VR_CTL_PHY
2 603 1 C7323 Q7324
98 VR_AXG_DRV1_PVCC R73241 DIDT=TRUE 0.22UF CSD58864Q5D CRITICAL R7328
NET_PHYSICAL_TYPE=POWER 10% SON5X6 VIN 1 CRITICAL
1 NET_SPACING_TYPE=VR_CONTROL 3 TG 0.0005

oo
MIN_NECK_WIDTH=0.3MM
MIN_LINE_WIDTH=0.6MM
1 C73211/10W
5% NO_TEST=TRUE 2 16V
X7R L7321 1%
VOLTAGE=12V 10%
1UF MF-LF 603 VSW 6 0.68UH-7.6MOHM-12A 1W
MF PPVAXG_S0_REG 6
16V 603 2 PPVCORE_S0_AXG_REGOUT 0612
NO_TEST=TRUE 2 PPVCORE_S0_AXG_REG1
B 2 X5R
603
4 TGR 7 98 1 1 2
B
7

8 NET_SPACING_TYPE=SWITCHNODE PIC0504H-SM 3 4
1
C7330 1
C7331
1 C7332 1 C7333
VCC R73261 152S1268 330UF-0.0045OHM 330UF-0.0045OHM 10UF 10UF
U7322 VR_AXG_DRV1_BOOT NO_TEST=TRUE
eb 5 BG 2.2 20% 20%
20% 20%
2 10V 2 10V
98
5%
NOSTUFF 1/8W 2 2V 2 2V X5R X5R
ISL6620 NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE
NET_SPACING_TYPE=VR_CONTROL MF-LF
POLY POLY 603 603
QFN PGND 805 2
CASE-D2-SM CASE-D2-SM
98 65 VR_AXG_PWM 4 PWM BOOT 2 R7325

9
IN
2
1 1 VR_AXG_PH1_SNUB 98
9 EN UGATE 1 98 VR_AXG_DRV1_UGATE NO_TEST=TRUE VR_AXG_DRV1_UGATE_R
ot
CRITICAL NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE 5% NET_PHYSICAL_TYPE=VR_CTL_PHY NO_TEST=TRUE NET_PHYSICAL_TYPE=VR_CTL_PHY
1/10W DIDT=TRUE
PHASE 10 98 VR_AXG_PHASE1 VR_CONTROL MF-LF
DIDT=TRUE VR_CTL 1 C7328NET_SPACING_TYPE=SWITCHNODE
3 NC
NET_PHYSICAL_TYPE=POWER DIDT=TRUE 603 NET_SPACING_TYPE=SWITCHNODE NO_TEST=TRUE 0.001UF
8 NC LGATE 6 98 VR_AXG_DRV1_LGATE 10%
NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL NO_TEST=TRUE 50V
2 CERM
N

THRML 402
GND PAD
NOSTUFF
VR_AXG_ISNS_P
5

OUT 65 98

VR_AXG_ISNS_N OUT 65 98

A SYNC_MASTER=K62_AARON SYNC_DATE=N/A A
PAGE TITLE

VREG:AXG PHASE/CORE - CAPS

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

65 6 =PP3V3_S0_VRD
1V05 REGULATOR for CPU & PCH VCCIO O/P= PP1V05_S0_REG
1
R7411
10K
5%
1/16W
MF-LF
2 402
98 50 OUT P1V05_IMON R7467 6 =PP12V_S0_P1V05_VREG
DIDT=TRUE NET_SPACING_TYPE=POWER
2.2
1 2
100 64 63 OUT PM_PGOOD_P1V05_S0_REG
5% THESE TWO CAPS ARE FOR EMC
D
1/10W
MF-LF
603
R7460
R7480 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
D
2.2 1 1 1 1 1 1 1 1
=PP5V_S0_P1V05_VREG 1
2.2
2 5V_S0_P1V05REG_VIN
98 PP12V_S0_P1V05_VREG_VIN 1 2
C7427 C7426 C7420 C7421 C7422 C7423 C7424 C7425
6 VOLTAGE=12V 10UF 10UF 1UF 1UF 1UF
VOLTAGE=5V 0.6 mm 5% 100UF 220UF 220UF
5% 0.6 mm 0.2 MM 1/10W 20% 20% 20% 10% 10% 10% 10% 10%
1/10W MF-LF 16V 16V 16V 16V 16V
0.2 MM 1 2 16V 2 16V 2 16V 2 X5R-CERM 2 X5R-CERM 2 X5R 2 X5R 2 X5R
MF-LF C7430 603 376S0772 POLY ALUM-POLY ALUM-POLY
603 6.3X6-TH 8X7-TH 8X7-TH 0805 0805 603 603 603
1UF
6 =PP3V3_S0_P1V05_VREG
NOSTUFF 98 5V_S0_P1V05REG_VDD 10% Q7420
C7465 1 C7461 1 VOLTAGE=5V
1 C7462 2 16V
X5R
IRF6710
0.6 mm S1
NOSTUFF 1UF 1UF 1UF 402 1
1 1 1 NOSTUFF 1 10% 10% 0.2 MM 10% D
R7490 R7491 R7492 R7484 16V 16V 16V GND_P1V05S0_AGND 68 2
X5R 2 X5R 2 2 X5R

22
20.0K 20.0K 20.0K 20.0K 1
1% 1% 1% 1% R7461 402 402 402 5
1/16W 1/16W 1/16W 1/16W 1K VDD PVCC 4 G 6
MF-LF MF-LF MF-LF MF-LF 5% (PP1V05S0_UGATE)
2 402 2 402 2 402 402 2 1/16W MIN_LINE_WIDTH=0.5 MM

P1V05_REG_VID0
MF-LF
2 402
U7401 MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE 3 S

1 RBIAS QFN DIDT=TRUE

P1V05S0_RBIAS VIN 14

ISL9563A
NET_SPACING_TYPE=SWITCHNODE
R7474 C7464
P1V05S0_SOFT 2 SOFT 0 0.22UF
P1V05_REG_VID1 18 P1V05S0_UGATE 1 2
R7420

m
UGATE
98 1 2 P1V05S0_BOOT_R
0.25 MM CRITICAL 0.0005
5%
28 IMON BOOT
98 17 P1V05S0_BOOT 1/10W
0.2 MM
DIDT=TRUE
16V
X7R
L7420 1%
1W
NET_SPACING_TYPE=VR_CTL 0.2 MM
0.25 MM
MF-LF
603
NET_SPACING_TYPE=VR_CTL 603 0.36UH-45A-0.76MOHM MF
31 10% 0612
P1V05_REG_VID2 PGOOD PHASE 19 DIDT=TRUE
1
98 P1V05S0_PHASE (P1V05S0_PHASE) 98 2 P1V05S0_PHASE_L 1 2 PP1V05_S0_REG 6 68

co
24 VID0 MIN_LINE_WIDTH=0.5 MM NET_SPACING_TYPE=SWITCHNODE MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM MSQ1211R36LF-TH MIN_NECK_WIDTH=0.2 MM 3 4
25
1 NOSTUFF VID1 DIDT=TRUE
1 NOSTUFF 1 SWITCH_NODE=TRUE
DIDT=TRUE
R7493 R7494 R7495 26 VID2 CRITICAL NET_PHYSICAL_TYPE=POWER 1 NOSTUFF
C7463
20.0K 20.0K 20.0K 0.0022UF
1% 1% 1% P1V05_REG_VID3 27 VID3
1/16W 1/16W 1/16W 1 2 6 7 10%
23 50V
MF-LF MF-LF MF-LF 1 NC NC 2 CERM

s.
2 402 2 402 2 402 R7483 29 D 376S0771 402
IN PM_EN_P1V05_S0_REG VR_ON DIDT=TRUE
20.0K
1% P1V05S0_FDE 30 AF_EN LGATE
98 21 P1V05S0_LGATE Q7421 98 P1V05S0_SNUBBER
MIN_LINE_WIDTH=0.4MM
1/16W
32 (P1V05S0_LGATE) 5 G IRF6795 MIN_NECK_WIDTH=0.4MM
MF-LF FDE DIRECTFET-MX NET_SPACING_TYPE=VR_CTL

C 402 2
P1V05S0_VSEN 8 MIN_LINE_WIDTH=0.5 MM S 1NOSTUFF
98 P1V05S0_ISP_R
C

ic
98 VSEN MIN_NECK_WIDTH=0.2 MM R7462
GATE_NODE=TRUE
98 P1V05S0_RTN 9 RTN DIDT=TRUE
3 4 0.499
NET_SPACING_TYPE=SWITCHNODE 1%
1/10W
98 P1V05S0_VW 4 VW MF
2 603 (P1V05S0_V0)

at
1
VO
98 12 P1V05S0_VO R7464
1K
1%
98 P1V05S0_COMP 5 COMP OCSET 3 98 P1V05S0_OCSET 1/16W

em
MF-LF
2 402
98 P1V05S0_FB 6 FB ISP
98 13 P1V05S0_ISP
ISN
98 11 P1V05S0_ISN
P1V05_S0_VDIFF 7 VDIFF
1NOSTUFF
98
1
ICOMP
98 10 P1V05S0_ICOMP R7469 1 C7473 R7470
9.31K 0.01UF 10K
68 6 PP1V05_S0_REG PGND VSS THRM_PAD 1% 10% 1%
1/16W 50V 1/16W
MF-LF 2 X7R MF-LF

33
1

ch
R7463 (P1V05S0_VO) 2 402 402 2 402
100 1
1% C7476 1 R7472
1/16W 0.1UF 150K 1
MF-LF 10% 1% R7473 1 1
R7466 2 402 16V 1/16W C7477 C7478
X7R-CERM 2 MF-LF 10K 0.1UF 0.1UF
20 (P1V05S0_VSEN) 402 2 402 1% 10% 10%
CPU_VCCIO_SENSE_P 1 2 1/16W

kS
98 13
MF-LF 2 25V
X5R 2 25V
X5R
1%
1/16W 1 C7470 (P1V05S0_ISP) 2 402 402 402
MF-LF
402 0.001UF (P1V05S0_ISN)
10%
R7468 2 50V
20 X7R
CPU_VCCIO_SENSE_N 1 2 402 1
98 13
(P1V05S0_RTN) XW7461 R7475

oo
1% SM 45.3K
1/16W
MF-LF 1 2
1%
1/16W
OUTPUT BULK DECOUPLING
402
1
68 GND_P1V05S0_AGND MF-LF
R7471 VOLTAGE=0V OMIT 2 402 68 6 PP1V05_S0_REG
B 100
1%
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM (P1V05S0_ICOMP) B
1/16W 1 1 1 1 1 1
MF-LF C7443 C7444 C7445 C7446 C7428 C7429
2 402
eb 330UF-0.0045OHM 330UF-0.0045OHM 330UF-0.0045OHM 330UF-0.0045OHM 22UF 22UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V
2 2V 2 2V 2 2V 2 2V 2 CERM-X5R 2 CERM-X5R
POLY POLY POLY POLY
CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM 805 805

(P1V05S0_VW)
ot

C7479 1
0.001UF
C7480 10%
50V
33PF X7R 2
N

1
1 2 402 R7476
6.65K
5% 1%
1/16W
50V 1.05V DEFAULT, OTHER VALUES TBD
CERM C7481 MF-LF
R7477 402 0.001UF 2 402
150K 1 2
1 2 P1V05S0_COMP_C
(P1V05S0_COMP)
1%
1/16W 10% VID<3:0> Voltage
MF-LF 50V
402 CERM
402 (P1V05S0_FB) 0000 +1.100V
C7482 0011 +1.050V
R7478 0.001UF
1
200 2 1 2
P1V05S0_VDIF_C
1%
1/16W 10%
MF-LF R7479 50V
402 2.21K2 CERM
1 402
(P1V05S0_VDIFF)
1%
A 1/16W
MF-LF
402
SYNC_MASTER=K62_AARON SYNC_DATE=12/08/2009 A
PAGE TITLE

1V05 REGULATOR
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

CPU VCCSA 0.925V (8.8A MAX)

D D
=PPVCCIO_S0_CPU_VCCSA 6

NOTE: THIS RAIL IS COMING FROM PPVCCSA_S0_INPUT_SNS AFTER SENSE RES

CRITICAL

U7505
R7531 ISL21070
100 SOT23-3 C7551
6 =PP3V3_S5_CPU_VCCSA 1 2 VCCSA_REF 1 VIN VOUT 2 10PF
5% 1 2
1/16W
MF-LF
402 5%
GND 50V
CERM
402

3
1 C7515 1 C7516

m
1UF 1UF
10% 10%
R7550 C7550
2 10V
X5R 2 10V
X5R 560PF
402 402 1
49.9K
2 VCCSA_FIL 1 2 5
1%

co
1/16W 10%
MF-LF 50V D
402 CERM
402 R7505
0
Q7500
1 2 98 VCCSA_GATE 4 G IRFH3702TRPBF
NET_PHYSICAL_TYPE=VR_CTL_PHY S PQFN
5% DIDT=TRUE
1/16W NET_SPACING_TYPE=VR_CTL
MF-LF 376S0910

s.
402
1

C C

ic
4 NOSTUFF
98 VCCSA_CNTRL_INPUT1 3 R7506 PPVCCSA_S0_FET 6

1K
VCCSA_OUT 1 2 CRITICAL CRITICAL

at
1 NET_PHYSICAL_TYPE=POWER OMIT_TABLE OMIT_TABLE
5% 1 C7507 1 C7508
LM358-SOI-HF NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE 1/16W
DIDT=TRUE
NET_SPACING_TYPE=POWER 1
C7509 1
C7510
2 8 U7501 NET_SPACING_TYPE=VR_CTL MF-LF
402 220UF-25MOHM 220UF-25MOHM
10UF
10%
10UF
10%
20% 20% 6.3V
2 X5R 2 6.3V
2 6V X5R
2 6V POLY-TANT 805 805
POLY-TANT

em
=PP12V_S0_CPU_VCCSA 6 CASE-D2E-SM CASE-D2E-SM

1 Place C7507 inside cavity

R7504 Place C7508 inside cavity
2.2
5%
1/10W
MF-LF
2 603

ch
98 VCCSA_PWR_RC

1 C7502 TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

1UF
10% TABLE_5_ITEM

kS
2 25V
X5R
128S0330 2 POLYTANT,6V,220UF,25MOHM C7509,C7510
603-1

R7507 R7535

oo
5.49K 22
98 VCCSA_CNTRL_INPUT2 1 2 VCCSA_CNTRL_INPUT2_R 1 2
1% 5%
1/16W 1/16W
B MF-LF
402
MF-LF
402 B
NOSTUFF
C7512
eb 10PF
1 1 2
R7533
10K 5%
1% 50V
1/16W CERM
MF-LF 402
2 402
ot

R7552 C7552
560PF
1
1K 98
2 VCCSA_CRL 1 2
N

5%
1/16W 10%
MF-LF 50V
402 CERM
402

R7503
0
98 13 CPU_VCCSA_SENSE 1 2
5%
1/16W
MF-LF
402 1 C7501
100PF
5%
50V
50 6
=PPVCCSA_S0_INPUT_PWR 2 CERM
402

4 CRITICAL
1 C7504 1 C7505
A 5
1
C7506
330UF-0.009OHM
20%
4.7UF
20%
0.1UF
20%
SYNC_MASTER=K62_AARON SYNC_DATE=12/08/2009 A
PAGE TITLE
2 2V 2 6.3V 10V
2 CERM
7
LM358-SOI-HF
POLY
CASE-D2-HF
X5R-CERM1
402 402 CPU VCCSA REGULATOR
6 8 U7501 DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

REVISION
R
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOTE: THIS POWER RAIL IS BEFORE THE SENSE RES R5310 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
75 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 69 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CPU VCORE 3 PHASE/4 PHASE BOM OPTIONS

D D

TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_ITEM

116S0066 1 RES,1K,5%,0402 R7125 CPUVCORE-4PH

TABLE_5_ITEM

114S0303 1 RES,7.5K,5%,0402 R7125 CPUVCORE-3PH

TABLE_5_ITEM

114S0327 1 RES,13.7K,1%,0402 R7126 CPUVCORE-4PH

TABLE_5_ITEM

114S0316 1 RES,10.2K,1%,0402 R7126 CPUVCORE-3PH

TABLE_5_ITEM

m
114S0323 1 RES,12.4K,1%,0402 R7119 CPUVCORE-4PH
TABLE_5_ITEM

114S0316 1 RES,10.2K,1%,0402 R7119 CPUVCORE-3PH

TABLE_5_ITEM

114S0355 1 RES,26.1K,1%,0402 R7150 CPUVCORE-4PH

co
TABLE_5_ITEM

114S0338 1 RES,17.8K,1%,0402 R7150 CPUVCORE-3PH

TABLE_5_ITEM

114S0211 1 RES,845,1%,0402 R7153 CPUVCORE-4PH

TABLE_5_ITEM

116S0004 1 RES,0,1%,0402 R7153 CPUVCORE-3PH

s.
TABLE_5_ITEM

114S0314 1 RES,9.76K,1%,0402 R7154 CPUVCORE-4PH

TABLE_5_ITEM

114S0316 1 RES,10.2K,1%,0402 R7154 CPUVCORE-3PH

C TABLE_5_ITEM

ic
114S0225 1 RES,1.21K,1%,0402 R7141 CPUVCORE-4PH
TABLE_5_ITEM

114S0217 1 RES,976,1%,0402 R7141 CPUVCORE-3PH

TABLE_5_ITEM

114S0335 1 RES,16.5K,1%,0402 R7142 CPUVCORE-4PH

at
TABLE_5_ITEM

114S0349 1 RES,23.2K,1%,0402 R7142 CPUVCORE-3PH

TABLE_5_ITEM

114S0331 1 RES,15K,1%,0402 R7143 CPUVCORE-3PH

em
TABLE_5_ITEM

114S0257 1 RES,2.55K,1%,0402 R7144 CPUVCORE-4PH

TABLE_5_ITEM

114S0252 1 RES,2.32K,1%,0402 R7144 CPUVCORE-3PH

TABLE_5_ITEM

114S0209 1 RES,806,1%,0402 R7130 CPUVCORE-4PH

TABLE_5_ITEM

114S0188 1 RES,487,1%,0402 R7130 CPUVCORE-3PH

TABLE_5_ITEM

ch
116S0004 1 RES,0R,1%,0402 R7129 CPUVCORE-4PH
TABLE_5_ITEM

114S0189 1 RES,499,1%,0402 R7129 CPUVCORE-3PH

TABLE_5_ITEM

114S0219 1 RES,1.02K,1%,0402 R7136 CPUVCORE-4PH

TABLE_5_ITEM

114S0131 1 RES,130,1%,0402 R7136 CPUVCORE-3PH

kS
TABLE_5_ITEM

132S8221 1 CAP,820PF,10%,0402 C7123 CPUVCORE-4PH

TABLE_5_ITEM

132S1534 1 CAP,0.0012UF,10%,0402 C7123 CPUVCORE-3PH

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B eb B
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N

A SYNC_MASTER=K62_AARON SYNC_DATE=12/08/2009 A
PAGE TITLE

CPU 3P/4P BOM OPTIONS

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

D D
3V3 S5 REGULATOR C7719 1 C7766 1 C7767 1 C7768 1 C7758 1 C7765 1

71 6
=PP12V_S5_P5VS3_VREG
NET_SPACING_TYPE=POWER
100UF
20%
16V
POLY
6.3X6-TH
2
100UF
20%
16V
POLY
6.3X6-TH
2
100UF
20%
16V
POLY
6.3X6-TH
2
100UF
20%
16V
POLY
6.3X6-TH
2
10UF
10%
16V
X5R-CERM
0805
2
10UF
10%
16V
X5R-CERM
0805
2 5V S3 REGULATOR
EMC CAPS
PLACE CLOSE TO FET
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
=PP3V3_S5_VRD 6
Power Rating ?
C7718 1 C7712 1 C7710 1 1 C7711 1 C7722
100UF 10UF 10UF 1
10% 10%
1UF 1UF R7726

m
20% 10% 10%
16V 2 16V
X5R-CERM 2 16V
X5R-CERM 2 2 16V 2 16V
=PP12V_S5_P5VS3_VREG 6 71 20K
POLY X5R X5R 5%
6.3X6-TH 0805 0805
603 603 1/16W
MF-LF
NOSTUFF 2 402

co
1
R7725 PP5V_S5_LDO 6
20K EMC: C7754,C7755
3V3 OUTPUT 5% PLACE AT Q7330

2
1/16W
MF-LF
2 402

R7776
CRITICAL
RJK0384DPA
Q7710 D1
1 C7754 1 C7755 5V OUTPUT

s.
L7710 1UF 1UF
PP3V3_S5_REG 2
0.002
1
WPAK G1 1 (P3V3S5_UGATE) 10% 10%
6 2.2UH-14A 376S0801 MIN_NECK_WIDTH=0.2MM
NET_PHYSICAL_TYPE=POWER
2 16V 2 16V
1 1 X5R X5R
1%
1206
1/4W
MF-LF 1 2 NET_PHYSICAL_TYPE=POWER 7 S1/D2 MIN_LINE_WIDTH=0.6MM C7742 R7740 1 603 603
GATE_NODE=TRUE R7741
C 4.7UF 2.2
C

ic
MMD06CZ-SM DIDT=TRUE NET_SPACING_TYPE=VR_CONTROL 20% 5% 1 EMC: C7763,C7764
1 6.3V
98 PP3V3_S5_REG_R C7730 2 CERM 1/8W
MF-LF
5%
1/8W DIDT=TRUE
PLACE AT L7750.2
PP5V_S3_REG
NET_PHYSICAL_TYPE=POWER C7790 1000PF G2 6 (P3V3S5_LGATE) 603
0.01UF R7790 5% 2 805 MF-LF
5
6

15.8K 2 25V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM 2 805
16V 1 2 CERM 1 2 NP0-C0G P5V_S5_LDO_R PM_PGOOD_P5V_S3_REG OUT 63 83 100
C7763 1 C7764 1

at
402 GATE_NODE=TRUE
10% 402 1% NOSTUFF
S2 NET_SPACING_TYPE=VR_CONTROL D CRITICAL 0.001UF 0.001UF
P5V_S5_VCC1 10% 10%
1/16W
Q7750

3
MF-LF 1 C7741 50V
2
50V 2
1 NET_SPACING_TYPE=VR_CTL 4 G X7R X7R
R7791 402
NOSTUFF C7740 1 1UF 1 C7743 MIN_LINE_WIDTH=0.6MM
FDMS0346 402 402
15.8K 1 10% MIN_NECK_WIDTH=0.2 MM POWER56
R7730 1UF 1UF

em
1%
16V
2 X5R
10% 10% NET_SPACING_TYPE=VR_CONTROL 376S0875

P5VS3_REG_BOOT_R
0.499

NET_SPACING_TYPE=VR_CONTROL
1/16W 16V 603 16V

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2 MM
MF-LF 1% X5R 2 2 X5R S R7775
2 402 1/10W 603 603
MF CRITICAL 0.002
2 1
2 603 1 2 3 L7750 1% 1/4W

VCC1 5

4
C7756 2.2UH+/-20%-0.0069OHM-16A 1206 MF-LF
R7750 0.1UF

VCC2
VIN_5V_S5_REG_RC 2
0 1 2 1 1 2
P3V3S5_REG_SNUB 18 LDO5 VIN 17 PP5V_S3_REG_R

ch
PIC1005H-SM
98
C7714 R7710 5% DIDT=TRUE
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE 10%
1
X7R
2 98 P3V3S5_REG_BOOT_R 1
0
2
U7700 FCCM 3 TP_P5VS3_REG_FCCM
1/10W
MF-LF
10%
25V
X5R NOSTUFF
DIDT=TRUE NET_PHYSICAL_TYPE=POWER NET_PHYSICAL_TYPE=POWER
603
50V 603-1 MIN_NECK_WIDTH=0.2MM
5%
ISL62383 402 C7757 1
MIN_LINE_WIDTH=0.6MM PM_PGOOD_P3V3_S5_REG 7 PGOOD1
0.1UF DIDT=TRUE 1/10W 100 64 27 QFN PGOOD2 1 MIN_NECK_WIDTH=0.2 MM 0.001UF C7770
NET_SPACING_TYPE=VR_CONTROL MF-LF
603
CRITICAL MIN_LINE_WIDTH=0.6MM 10%
50V
R7770 27.0NF
(P3V3S5_PHASE) 98 P3V3S5_REG_UGATE 14 UGATE1 UGATE2 22 98 P5VS3_REG_UGATE NET_SPACING_TYPE=VR_CONTROL CERM 2 9.76K 1 2 OUTPUT BULK DECOUPLING:

kS
DIDT=TRUE 2 1
DIDT=TRUE 402
NET_SPACING_TYPE=VR_CONTROL98 P3V3S5_REG_BOOT 15 BOOT1 BOOT2 21 98 P5VS3_REG_BOOT 1% 1/16W
MIN_NECK_WIDTH=0.2MM DIDT=TRUE 402 MF-LF 10%
DIDT=TRUE MIN_NECK_WIDTH=0.2 MM 10V
MIN_LINE_WIDTH=0.6MM 5V_SNUBBER CRITICAL CRITICAL
98 P3V3S5_REG_PHASE 13 PHASE1 PHASE2 23 98 P5VS3_REG_PHASE MIN_LINE_WIDTH=0.6MM X5R
402
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
DIDT=TRUE DIDT=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.4MM C7761 1 1
C7762
98 P3V3S5_REG_LGATE 16 LGATE1 LGATE2 20 98 P5VS3_REG_LGATE MIN_NECK_WIDTH=0.2 MM
5
MIN_NECK_WIDTH=0.2 MM
1 1
330UF 330UF
NET_SPACING_TYPE=SWITCHNODE
NET_PHYSICAL_TYPE=POWER DIDT=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6MM NET_SPACING_TYPE=SWITCHNODE
1 C7760 C7769 20%
6.3V 2
20%
2 6.3V

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P3V3S5_REG_ISEN 10 ISEN2 26 P5VS3_REG_ISEN NET_SPACING_TYPE=VR_CONTROL R7752 10UF 10UF POLY-TANT POLY-TANT
OUTPUT BULK DECOUPLING: PLACEMENT_NOTE=PLACE NEXT TO C7716 98 ISEN1 98
D 0.499 R7771 1
6.3V 20% 6.3V
CASE-D3L-SM CASE-D3L-SM
2 1 P5VS3_REG_OCSET 2 20%
CERM 805-1 2 CERM 805-1
98 P3V3S5_REG_OCSET 11 OCSET1 OCSET2 25 98
1% 1/10W 9.76K
128S0237
B 1 C7717 1
CRITICAL
XW7716
SM
98 P3V3S5_REG_VOUT1 9 VOUT1 VOUT2 27 98 P5VS3_REG_VOUT2 CRITICAL
4 G MF 603
2 NOSTUFF
1%
1/16W
MF-LF
B
C7715 C7721 1 Q7751 402 2
P3V3S5_REG_FB_R

10UF 10UF OMIT 98 P3V3S5_REG_FB

10% 330UF 1 8 FB1 FB2 28 98 P5VS3_REG_FB
10% 16V
2
20% R7724
eb FDMS0355S S
16V
X5R-CERM 2 X5R-CERM
0805
6.3V 2
POLY-TANT R77201 976 1 6 FSET1 FSET2 2 98 P5VS3_REG_FSET2
POWER56
0805 CASE-D3L-SM 45.3K
1%
1%
1/16W
R7722 1 2 3 2
MF-LF 68K 12 EN1 24
<Ra> 1/16W
MF-LF 402 2 5% EN2 376S0917
402 2 1/16W
MF-LF THRM SM XW7751
2 402 PAD PGND OMIT
ot
1

19
C7720 1 100 PM_EN_P3V3_S5_REG
R7721 1 1000PF
1 C7723 1
C7716 <Rb> 10.0K 5%
1
0.1UF 0.1UF 0.5%
25V
NP0-C0G 2 R7723
20% 20%
1/16W 402 33K
N

MF
2
16V
2
16V
402
5% 98 P3V3S5_REG_FSET1
CERM CERM 2 1/16W
603 603 MF-LF
2 402 1 C7701 1
R7701
0.01UF 16.5K
EMC CAPS Vout = 0.6V * (1 + Ra / Rb) 10% 1%
16V

P5VS5_REG_FB_R
PLACE CLOSE 2 CERM 1/16W
TO L 402 MF-LF R77591 R77551
2 402 976 75K RA
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2

100 63
PM_EN_P5V_S3_REG RB
C7759 1 1
1 NOSTUFF R7756
1 C7747 R7747 1000PF 10K
0.01UF 16.5K 1 C7777 5% 1%
25V
10% 1% 0.001UF NP0-C0G 2 1/16W
2 16V
CERM
1/16W
MF-LF 10% 402 MF-LF
402 50V 2 402
2 402 2 CERM

A 402
SYNC_MASTER=K62_AARON SYNC_DATE=12/08/2009 A
PAGE TITLE

5V_S3 / 3V3_S5 VREGS

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

1.5 V DDR SUPPLY PPDDR_S3_REG

NET_PHYSICAL_TYPE=POWER VOUT = 1.5V
PEAK = 11A
=PP12V_S5_DDR_VREG AVG = 6.7A
D 6
NET_PHYSICAL_TYPE=POWER DIDT=TRUE
EMC CAPS
PLACE CLOSE TO FET D
NET_SPACING_TYPE=POWER
=PP5V_S3_DDR_VREG R7801 CRITICAL CRITICAL
6
1 C7833 1 C7834 EMC CAPS
NET_PHYSICAL_TYPE=POWER 1
4.7
2 98 PP5V_S3_DDR_REG_V5FILT C7830 1 C7831 1 1
C7832 1UF 1UF PLACE CLOSE TO L7830
MIN_LINE_WIDTH=0.6 mm NET_PHYSICAL_TYPE=POWER 270UF 270UF 10UF 10% 10%
5% MIN_NECK_WIDTH=0.2 mm 20% 20% 10%
16V 2 16V
X5R 2 16V
X5R
1/16W VOLTAGE=5V 16V 2 16V 2 2 X5R-CERM 603 603
MF-LF ELEC ELEC 1 C7838 1 C7839
402 8X9-TH1 8X9-TH1 0805
6 =PP3V3_S3_VRD 0.001UF
10%
0.001UF
10%
50V 50V
1
C7815 2 2 X7R
R7810 1
R7841
X7R
R7820 1
C7800 1 C7801 1
10UF 402 402
3.57K 4.7

23
20%
10K 4.7UF 1UF 6.3V 1% (DDRREG_DRVH) 1 2 DDR_REG_UGATE_R
20% 10% 2
5% 6.3V 10V
X5R 1/16W MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm CRITICAL
1/16W CERM 2 X5R 2 V5IN V5FILT VLDOIN 603 MF-LF MIN_NECK_WIDTH=0.2 mm C7840 5%
1/10W
MIN_NECK_WIDTH=0.2 mm
MF-LF 402
402
2
603 402 2 DIDT=TRUE 0.1UF MF-LF
603
DIDT=TRUE
VR_CTL Q7830
6 COMP VDDQSNS 8 98 DDR_REG_BOOT_R 1 2 CSD58864Q5D
DIDT=TRUE SON5X6 VIN 1 CRITICAL
CRITICAL 3 TG
PM_EN_DDRVTT_S0_REG MODE 4 98 DDR_REG_VDDQSNS
20%
25V L7830
100 63 32 IN 10 S3 VTT Enable
R7840 CERM
VSW 6 1.5UH-15%-22A-3.3MOHM

m
603
100 63 IN PM_EN_DDR1V5_S3_REG 11 S5 VDDQ/VTTREF Enable 0 NET_SPACING_TYPE=SWITCHNODE 4 TGR 7 1 2
VBST 22 98 DDR_REG_BOOT 1 2 MIN_LINE_WIDTH=0.6 mm 98 DDR_REG_PHASE_R PP1V5_S3_REG 6
100 63 5 OUT PM_PGOOD_DDR1V5_S3_REG 13 PGOOD VDDQ PGOOD U7800 DIDT=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm 8 SDP1182M-TH NET_PHYSICAL_TYPE=POWER
MIN_NECK_WIDTH=0.2 mm 5% NET_SPACING_TYPE=VR_CONTROL MIN_LINE_WIDTH=0.6 mm
NET_SPACING_TYPE=VR_CONTROL 1/10W MIN_NECK_WIDTH=0.2 mm
TPS51116 DRVH 21 98 DDR_REG_UGATE MF-LF DIDT=TRUE NOSTUFF 1 OUTPUT BULK DECOUPLING:
TP_PPVTT_S3_DDR_BUF 10mA max load QFN NET_SPACING_TYPE=VR_CONTROL 603

co
5 VTTREF 5 BG NET_SPACING_TYPE=VR_CTL C7841
1000PF CRITICAL 1
(NOT USED) Vout = VDDQSNS/2 SYM (2 OF 2) LL 20 98 DDR_REG_PHASE (DDRREG_LL) 5% 1 CRITICAL C7837
24 VTT MIN_LINE_WIDTH=0.6 mm DIDT=TRUE PGND 25V
NP0-C0G 2
C7835 1
C7836 10UF
OMIT Vout = VTTREF MIN_NECK_WIDTH=0.2 mm 330UF 330UF 20%

9
402 1V5_SNUBBER 20% 6.3V
XW7803 DRVL 19 98 DDR_REG_LGATE (DDRREG_DRVL) 98
2 2.5V
20% 2 X5R
SM NET_SPACING_TYPE=VR_CONTROL MIN_LINE_WIDTH=0.6 mm DIDT=TRUE
POLY-TANT 2 2.5V 603
PPVTT_S0_DDR_LDO DDR_REG_VTTSNS 2 VTTSNS
MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.4MM CASE-D2E-SM3 POLY-TANT
CASE-D2E-SM3

s.
6 1 2 98 MIN_NECK_WIDTH=0.4MM
NO_TEST=TRUE CS 16 98 DDR_REG_CS DIDT=TRUE
FEEDBACK THROUGH SHORT NET_SPACING_TYPE=SWITCHNODE
SHOULD NOT NEED TP NC 7 NC0
12 NC1 VDDQSET 9 98 DDR_REG_FB 1NOSTUFF
NC R7831
C 0.499 C

ic
2
CRITICAL CRITICAL VTTGND THRM_PAD GND PGND CS_GND 1% OMIT
OMIT 1/10W
C7804 1
1 C7803 XW7831 XW7830

17
PLACEMENT_NOTE=PLACE NEXT TO Q7831 MF SM
22UF 22UF SM
2 603
20%
6.3V 20% 98 DDR_REG_CSGND (DDRREG_CSGND) 1 2 1

at
2 6.3V
CERM-X5R 2 MIN_LINE_WIDTH=0.2 mm
CERM-X5R PLACEMENT_NOTE=PLACE NEXT TO L7830
805-3 805-3 MIN_NECK_WIDTH=0.2 mm

98 DDR_REG_PGND (DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm NOSTUFF

em
MIN_LINE_WIDTH=0.2 mm 1
1
2
2MIN_NECK_WIDTH=0.2 mm
C7820 1 R7832 <Ra>
C7805 XW7800 15.0K
0.033UF XW7801 100PF 1%
SM 5%
10% OMIT SM 50V 1/16W
16V OMIT CERM 2 MF-LF
X5R 2
2 402
1 402
402 1
(DDRREG_FB)

1
R7833 <Rb>
STATE S3 S5 VDDQ VTTREF VTT Vout = 0.75V * (1 + Ra / Rb)

ch
AGND_DDR_REG 15.0K
S0 HI HI ON ON ON MIN_LINE_WIDTH=0.6 mm
1%
1/16W
S3 LO HI ON ON OFF MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
MF-LF
2 402
S5 LO LO OFF OFF OFF

kS
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B eb B
1.8 V SUPPLY
1A Average current
ot

6
=PP5V_S0_P1V8_REG Vo=0.8*(1+ Ra/Rb)
Vo=0.8*(1+ 59/47)=1.804V
N

1 C7854 1 C7855 1 R7853 1 R7854

22UF 22UF
20% 20% 100K 100K
2 6.3V 2 6.3V
1
2

X5R-CERM-1 X5R-CERM-1 5% 5%
603 603 1/16W 1/16W
MF-LF MF-LF VDD
2 402 2 402 VIN
CRITICAL
U7850 L7850
ISL8013A 1.5UH-4A
QFN LX0 13
100 63
PM_EN_P1V8_S0_REG 5 EN CRITICAL LX1 14
98 P1V8_REG_PHASE 1 2
PP1V8_S0_REG
MMD04BZ-SM 6
LX2 15 NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
100 64 PM_PGOOD_P1V8_S0_REG 7 PG SWITCHNODE NET_PHYSICAL_TYPE=POWER
8 1
98 P1V8_REG_SYNC 4 SYNCH
VFB
98 P1V8_REG_VFB 1 <Ra> R7850
59.0K
A NOSTUFF
CONTINUOUS MODE
NC
16
6 C7850 5%
47PF
50V 2 1/16W 1%
MF-LF 402
SYNC_MASTER=K62_AARON SYNC_DATE=11/30/2009 A
1 R7860 402 CERM 2
1 C7852 1 C7853 PAGE TITLE

100K
SGND PGND THRM_PAD 22UF
20%
6.3V
22UF
20%
6.3V
1.5V / 1.8V VREGS
5% 1 2 X5R-CERM-1 2 X5R-CERM-1 DRAWING NUMBER SIZE
R7851
9
10

11
12

1/16W
MF-LF <Rb> 47.0K
603 603
Apple Inc. 051-8442 D
2 402 REVISION
1/16W 1% R
MF-LF 402 10.1.0
2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
78 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 72 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

m
6
=PP12V_G3H_3V42
NET_SPACING_TYPE=POWER 98 P3V42G3H_BOOST

co
C7900 1

3
C7910 1 VIN BOOST
0.22UF
10UF 20% CRITICAL
1 10% 6.3V 2
R7910 25V 2 U7900 X5R L7900
6.98K X5R
LT3470A 402
PP3V42_G3H_REG

s.
1% 805 33UH
1/16W DFN 6

MF-LF 100 3V42G3H_SHDN_L 8 SHDN* SW 4 98 P3V42G3H_SW 1 2

402 2
BIAS 2 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
CDPH4D19FHF-SM Vout = 3.425
C 7 NC CRITICAL SWITCH_NODE=TRUE DIDT=TRUE
250mA max output C

ic
NC NET_SPACING_TYPE=SWITCHNODE
FB 1
THRM
(Switcher limit)
GND PAD 1
C7901 1 <Ra> R7900

at
22pF 348K
1%
353S2171 5%
50V 1/16W 1 C7902
CERM 2 MF-LF
402 2 22UF
402 20%
2 6.3V
X5R-CERM-1
P3V42G3H_FB

em
98
1 603
R7911 1 C7911
2.1K 1000PF
1%
1/16W 5% <Rb> R79011
MF-LF 2 25V
NP0-C0G 200K
402 2 402 1%
1/16W
MF-LF
402 2

ch
Vout = 1.25V * (1 + Ra / Rb)

kS
oo
B eb B
ot
N

A SYNC_MASTER=K62_AARON SYNC_DATE=N/A A
PAGE TITLE

3.42 G3HOT SUPPLY

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

5V S0 FET (6.6A PK/3.1A AVG) 3.3V S0 FET (2.9APK / 2.0A AVG) 3.3V S3 FET (3.4A PK / 1.6A AVG)
74 64 33 6 =PP12V_S5_PWRCTL
74 64 33 6 =PP12V_S5_PWRCTL
1 C8000 =PP12V_S5_PWRCTL
0.1UF 1 C8053 74 64 33 6
10%
CRITICAL 16V
2 X5R 0.1UF 1 C8050
CRITICAL 10%
Q8000 402
Q8053 2 16V
X5R
0.1UF
10%
IRFH3702TRPBF 402 CRITICAL 16V
2 X5R
IRFH3702TRPBF
PQFN
PP5V_S0_FET PQFN
Q8050 402
6
IRFH3702TRPBF
D 6 =PP5V_S3_S0FET PP3V3_S0_FET 6
PQFN
D

S
=PP3V3_S5_S0FET PP3V3_S3_FET

1
6 6

S
5

1
6 =PP3V3_S5_S3FET

S
5

1
G
81 74 64 63 6 =PP3V3_S0_PWRCTL

G
81 74 64 63 6 =PP3V3_S0_PWRCTL
83 64 6 =PP3V3_S3_PWRCTL
NOSTUFF

G
4
1
1
R8000 VCC

P5V_S0_EN_G

1
10K 1
R8050

4
P3V3_S0_EN_G
1
5%
U8000 VCC R8051

1
1/16W 10K

P3V3_S3_EN_G
MF-LF 5% 10K VCC
2 402
SLG5AP001 1/16W
MF-LF
U8053 5%
1/16W
5D TDFN
ON 2 2 402 SLG5AP001
TDFN
MF-LF
402
U8050
7G CRITICAL
5D ON 2 2 SLG5AP001
S6 5D TDFN
7G CRITICAL ON 2
8 PG S6
64 63PM_PGOOD_P5V_S0_FET NC 3 7G
100
8 PG CRITICAL S6
100 64 63 PM_PGOOD_P3V3_S0_FET NC 3
THRM

m
PAD GND 100 34 PM_PGOOD_P3V3_S3_FET 8 PG NC 3
THRM

4
PAD GND
THRM

4
PAD GND

4
co
100 63 IN PM_EN_P5V_S0_FET
100 63 IN PM_EN_P3V3_S0_FET
100 63 IN PM_EN_P3V3_S3_FET

s.
1.5V S0 FET (4.8A PK / 4.8A AVG)
C CRITICAL C

ic
Q8025
IRFH3702TRPBF
PQFN

at
6 =PP1V5_S3_S0FET PP1V5_S0_FET 6
D

S
5

em
G

1 C8025
0.1UF
4

10%
2 16V
X5R
74 64 33 6 =PP12V_S5_PWRCTL 402
P1V5_S0_EN_G

81 74 64 63 6 =PP3V3_S0_PWRCTL

ch
1

1
R8020 VCC
10K
5%
1/16W
U8025
MF-LF SLG5AP001
2 402

kS
5D TDFN
ON 2
7G CRITICAL S6

100 64 11 PM_PGOOD_P1V5_S0_FET 8 PG NC 3

THRM

oo
PAD GND
9

B eb B
100 63 IN PM_EN_P1V5_S0_FET
ot
N

A SYNC_MASTER=K62_AARON SYNC_DATE=04/07/2010 A
PAGE TITLE

S3+S0 FETS
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

D D
THE NMOS PMOS SHARING FOOTPRINT WILL NOT WORK DUE TO THE REVERSE POLARITY OF BODY DIODE.

PROTO-3:
Q8110 P-CH MOSFET 376S0933 4.6-MOHM 20A (WHEN USED W/Q8112)
IRFH9310PBF
=PP12V_G3H_S5_FET ADD C8111 2.2UF PQFN R8132
6 CRITICAL 0.005
1%
1W
10Amp-7Amp
NOSTUFF
R8103 98 PP12V_S5_RSN
MF
2512 PP12V_S5_FET

5
1 2 6 98
100 PP12V_SLG1

D
1 2
98 NET_PHYSICAL_TYPE=POWER 3 4
VOLTAGE=12V
5% 1 C8100 MIN_LINE_WIDTH=1mm

m
G
1/10W MIN_NECK_WIDTH=0.5mm
MF-LF 1UF NOSTUFF NOSTUFF

4
603 10% R8104 C8110 1
2 16V
X5R 0 R81101 C8111 1
0.47UF
1 2
603 353S3098 2.2UF 10%
NOSTUFF 10K

1
5% 10% 16V 2
5%

co
VCC 1/16W 16V X7R
1/16W X7R-CERM 2 805
MF-LF

NC
MF-LF

NC
U8100 402 402 2 805

(2.4-5.5V) SLG5AP026
SMC_PM_G2_EN 2 TDFN 5 S5_D_ON1 REMOVE R8132 BEFORE DVT
100 46 ON D1 R8111
High=3.3V S5_S_ON1 NOSTUFF 10K S5_MSFT_G1

s.
NOSTUFF 3 NC D2 6 1 2 100
R8105
R81001 7 S5_GT_ON 1
0 2
5%
100K CRITICAL
G
5% MF-LF
1/16W
MF-LF R8101
5% 1/16W 402 402 0
C 1/16W PG 8 PGOOD_P12V_S5_G3H 1 2 TP_PGOOD_P12VS5_G3H
C

ic
MF-LF
402 2 THRM NOSTUFF 5%
GND PAD R8106 1/16W
S5_DG_1 MF-LF

9
100

1
0 2
402
NOSTUFF

at
5%
1/16W
MF-LF 1
402 R8112
10K
5% 402
MF-LF
1/16W

em
2
100 SMC_PM_G2_EN_L
3
D
R8113 Q8112
0 100 SMC_PM_G2_EN_R 2N7002

ch
1 2 1 G S SOT23-HF1
5%
1/16W 2
MF-LF
402

kS
oo
B eb B
ot
N

A SYNC_MASTER=K62_JERRY SYNC_DATE=01/09/2011 A
PAGE TITLE

12V_S0 & 12V_S5 switch

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

Page Notes
Power aliases required by this page:
- =PP3V3_S0_MXM
- =PP5V_S0_MXM
- =PPV_S0_MXM_PWRSRC

Signal aliases required by this page:

(NONE)

D BOM options provided by this page: D

- MXM

MXM
77 76 64 21 6 =PP3V3_S0_MXM CRITICAL
MXM
MXM
R84001 J8400 =PP3V3_S0_MXM 6 21 64 76 77

100K B35P101-0121 J8400 MXM MXM

5%
1/16W F-RT-SM B35P101-0121 1 C8415 1 C8416
MF-LF F-RT-SM
402 2
(2 OF 4)
(4 OF 4) 0.001UF 22UF
APPLE P/N: 516S0699 10% 20%
2 50V
X7R 2 6.3V
CERM-X5R
100 9 MXM_CLKREQ_L 154 CLK_REQ* DP_A_AUX* 277 MXM_DP_A_AUX_N 79 6 =PP5V_S0_MXM 1 278 402 805-3
DP_A_AUX 279 MXM_DP_A_AUX_P 79 MXM MXM 3 3V3 280
MXM_PCIE_STD_SWING_L 19 PEX_STD_SW*
77
C8410 1 1 C8401

m
5 5V
DP_A_HPD 276 MXM_DP_A_HPD 79
0.001UF 22UF
9 CLK_100M_MXM_P 155 PEX_REFCLK 10% 20%
7
9 CLK_100M_MXM_N 153 PEX_REFCLK* DP_A_L0* 253 MXM_DP_A_ML_N<0> 79
50V 2 2 6.3V 9 E2
X7R CERM-X5R
255 MXM_DP_A_ML_P<0> 402 805-3 PWR_SRC E1 =PP12V_S0_MXM
DP_A_L0 79 6
9 MXM_RESET_L 156 PEX_RST*

co
DP_A_L1* 259 MXM_DP_A_ML_N<1> 79

93 78 MXM_PCIE_D2R_N<0> 147 PEX_RX0* DP_A_L1 261 MXM_DP_A_ML_P<1> 79 MXM MXM MXM MXM
93 78 MXM_PCIE_D2R_P<0> 149 PEX_RX0 DP_A_L2* 265 MXM_DP_A_ML_N<2> 79 C8400 1 1 C8412 1 C8413 1 C8414
93 78 MXM_PCIE_D2R_N<1> 141 PEX_RX1* DP_A_L2 267 MXM_DP_A_ML_P<2> 79 22UF 0.001UF 0.001UF 0.001UF
20% 10% 10% 10%
MXM_PCIE_D2R_P<1> 143 271 MXM_DP_A_ML_N<3> 35V 2 50V 50V 50V
93 78 PEX_RX1 DP_A_L3* 79 2 X7R 2 X7R 2 X7R
MXM SPEC POWER REQUIREMENTS ELEC

s.
MXM_PCIE_D2R_N<2> 135 273 MXM_DP_A_ML_P<3> 6.3X5.5-SM1 402 402 402
93 78 PEX_RX2* DP_A_L3 79
(NOT NECESSARILY THE SAME FOR EVERY MODULE)
93 78 MXM_PCIE_D2R_P<2> 137 PEX_RX2
DP_B_AUX* 270 MXM_DP_B_AUX_N 79 96 VOLTAGE CURRENT POWER
93 78 MXM_PCIE_D2R_N<3> 121 PEX_RX3*
C DP_B_AUX 272 MXM_DP_B_AUX_P
C
PCI-E
79 96
MXM_PCIE_D2R_P<3> 123

ic
93 78 PEX_RX3 3V3 1.0 A 3.3 W

DP
93 78 MXM_PCIE_D2R_N<4> 115 PEX_RX4* DP_B_HPD 274 MXM_DP_B_HPD 79 5V 2.5 A 12.5 W
93 78 MXM_PCIE_D2R_P<4> 117 PEX_RX4 PWR (7-20V) UP TO 10 A PLATFORM DEPENDENT
DP_B_L0* 246 MXM_DP_B_ML_N<0> 79 96
93 78 MXM_PCIE_D2R_N<5> 109 PEX_RX5*

at
DP_B_L0 248 MXM_DP_B_ML_P<0> 79 96
93 78 MXM_PCIE_D2R_P<5> 111 PEX_RX5
DP_B_L1* 252 MXM_DP_B_ML_N<1> 79 96
93 78 MXM_PCIE_D2R_N<6> 103 PEX_RX6*
DP_B_L1 254 MXM_DP_B_ML_P<1> 79 96
93 78 MXM_PCIE_D2R_P<6> 105 PEX_RX6
DP_B_L2* 258 MXM_DP_B_ML_N<2> 79 96
MXM_PCIE_D2R_N<7> 97 PEX_RX7*

em
93 78
DP_B_L2 260 MXM_DP_B_ML_P<2> 79 96
93 78 MXM_PCIE_D2R_P<7> 99 PEX_RX7
DP_B_L3* 264 MXM_DP_B_ML_N<3> 79 96
93 78 MXM_PCIE_D2R_N<8> 91 PEX_RX8*
DP_B_L3 266 MXM_DP_B_ML_P<3> 79 96
93 78 MXM_PCIE_D2R_P<8> 93 PEX_RX8
MXM_PCIE_D2R_N<9> 85 PEX_RX9* DP_C_AUX* 223 MXM_DP_C_AUX_N
93 78

93 78 MXM_PCIE_D2R_P<9> 87 PEX_RX9 DP_C_AUX 225 MXM_DP_C_AUX_P

84 96

84 96
MXM DP PORT ROUTING
93 78 MXM_PCIE_D2R_N<10> 79 PEX_RX10* K62 K60

ch
DP_C_HPD 234 MXM_DP_C_HPD 84
93 78 MXM_PCIE_D2R_P<10> 81 PEX_RX10 DP A EXT DP1 EXT DP1
93 78 MXM_PCIE_D2R_N<11> 73 PEX_RX11* DP_C_L0* 199 MXM_DP_C_ML_N<0> 84 96 DP B T29 DP2 T29 DP2
93 78 MXM_PCIE_D2R_P<11> 75 PEX_RX11 DP_C_L0 201 MXM_DP_C_ML_P<0> 84 96 DP C INT DP INT DP
93 78 MXM_PCIE_D2R_N<12> 67 PEX_RX12* DP_C_L1* 205 MXM_DP_C_ML_N<1> 84 96 DP D T29 DP1 T29 DP1
MXM_PCIE_D2R_P<12> 69 PEX_RX12 DP_C_L1 207 MXM_DP_C_ML_P<1> DP E

kS
93 78 84 96 EXT DP2
93 78 MXM_PCIE_D2R_N<13> 61 PEX_RX13* DP_C_L2* 211 MXM_DP_C_ML_N<2> 84 96

93 78 MXM_PCIE_D2R_P<13> 63 PEX_RX13 DP_C_L2 213 MXM_DP_C_ML_P<2> 84 96

93 78 MXM_PCIE_D2R_N<14> 55 PEX_RX14* DP_C_L3* 217 MXM_DP_C_ML_N<3> 84 96

93 78 MXM_PCIE_D2R_P<14> 57 PEX_RX14 DP_C_L3 219 MXM_DP_C_ML_P<3> 84 96

93 78 MXM_PCIE_D2R_N<15> 49 PEX_RX15*

oo
DP_D_AUX* 230 MXM_DP_D_AUX_N 79 96
93 78 MXM_PCIE_D2R_P<15> 51 PEX_RX15
DP_D_AUX 232 MXM_DP_D_AUX_P 79 96

93 78 MXM_PCIE_R2D_N<0> 148 PEX_TX0*

B 93 78 MXM_PCIE_R2D_P<0> 150 PEX_TX0
DP_D_HPD 236 MXM_DP_D_HPD 79
B
93 78 MXM_PCIE_R2D_N<1> 142 PEX_TX1* DP_D_L0* 206 MXM_DP_D_ML_N<0> 79 96

MXM_PCIE_R2D_P<1> MXM_DP_D_ML_P<0>
93 78 144 PEX_TX1 DP_D_L0 208
eb 79 96

93 78 MXM_PCIE_R2D_N<2> 136 PEX_TX2* DP_D_L1* 212 MXM_DP_D_ML_N<1> 79 96

93 78 MXM_PCIE_R2D_P<2> 138 PEX_TX2 DP_D_L1 214 MXM_DP_D_ML_P<1> 79 96

93 78 MXM_PCIE_R2D_N<3> 120 PEX_TX3* DP_D_L2* 218 MXM_DP_D_ML_N<2> 79 96

93 78 MXM_PCIE_R2D_P<3> 122 PEX_TX3 DP_D_L2 220 MXM_DP_D_ML_P<2> 79 96

MXM_PCIE_R2D_N<4> 114 224 MXM_DP_D_ML_N<3>

ot
93 78 PEX_TX4* DP_D_L3* 79 96

93 78 MXM_PCIE_R2D_P<4> 116 PEX_TX4 DP_D_L3 226 MXM_DP_D_ML_P<3> 79 96

93 78 MXM_PCIE_R2D_N<5> 108 PEX_TX5*

93 78 MXM_PCIE_R2D_P<5> 110 PEX_TX5
N

93 78 MXM_PCIE_R2D_N<6> 102 PEX_TX6*

93 78 MXM_PCIE_R2D_P<6> 104 PEX_TX6
93 78 MXM_PCIE_R2D_N<7> 96 PEX_TX7*
93 78 MXM_PCIE_R2D_P<7> 98 PEX_TX7
93 78 MXM_PCIE_R2D_N<8> 90 PEX_TX8*
93 78 MXM_PCIE_R2D_P<8> 92 PEX_TX8
93 78 MXM_PCIE_R2D_N<9> 84 PEX_TX9*
93 78 MXM_PCIE_R2D_P<9> 86 PEX_TX9
93 78 MXM_PCIE_R2D_N<10> 78 PEX_TX10*
93 78 MXM_PCIE_R2D_P<10> 80 PEX_TX10
93 78 MXM_PCIE_R2D_N<11> 72 PEX_TX11*
93 78 MXM_PCIE_R2D_P<11> 74 PEX_TX11
93 78 MXM_PCIE_R2D_N<12> 66 PEX_TX12*
93 78 MXM_PCIE_R2D_P<12> 68 PEX_TX12
MXM_PCIE_R2D_N<13> 60
A 93 78

93 78 MXM_PCIE_R2D_P<13> 62
PEX_TX13*
PEX_TX13 SYNC_MASTER=K62_AARON SYNC_DATE=N/A A
93 78 MXM_PCIE_R2D_N<14> 54 PEX_TX14* PAGE TITLE

93 78 MXM_PCIE_R2D_P<14> 56 PEX_TX14 MXM PCIe, DP & Power

93 78 MXM_PCIE_R2D_N<15> 48 PEX_TX15* DRAWING NUMBER SIZE
93 78 MXM_PCIE_R2D_P<15> 50 PEX_TX15
Apple Inc. 051-8442 D
REVISION
R
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
84 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 76 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Page Notes
Power aliases required by this page:
- =PP3V3_S0_MXM

Signal aliases required by this page:

- =SMB_MXM_THRM_DATA - =PM_MXM_PGOOD_PULLUP PULLUPS & PULLDOWNS AT MXM CONNECTOR
- =SMB_MXM_THRM_CLK

D BOM options provided by this page: D

FLOAT = NORMAL VGA MODE
GND = SECONDARY DISPLAY CARD NOSTUFF
R8510
2
0 1
MXM 77 MXM_VGA_DISABLE_L
MXM
MF-LF 5% 1/16W

J8400 J8400 402

MXM
B35P101-0121 B35P101-0121 FLOAT = LOW SWING
GND = HIGH SWING R8504
F-RT-SM F-RT-SM 0
(1 OF 4) (3 OF 4) 76 MXM_PCIE_STD_SWING_L 2 1
79 MXM_DP_E_AUX_P 35 LVDS_DDC_CLK
MF-LF 5% 1/16W
79 MXM_DP_E_AUX_N 33 LVDS_DDC_DAT VGA_DISABLE* 21 MXM_VGA_DISABLE_L 77 11 145
402
13 146
79 MXM_DP_E_HPD 31 DVI_HPD GPIO0 26 TP_MXM_GPIO0
15 151
GPIO1 28 TP_MXM_GPIO1
79 MXM_DP_E_ML_N<3> 176 LVDS_LCLK* 17 152
GPIO2 30 TP_MXM_GPIO2
MXM_DP_E_ML_P<3>

m
79 178 LVDS_LCLK 36 157
HDMI_CEC 29 TP_MXM_HDMI_CEC 37 166
79 MXM_DP_E_ML_N<2> 200 LVDS_LTX0*
46 173
79 MXM_DP_E_ML_P<2> 202 LVDS_LTX0 OEM0 38
47 174 =PP3V3_S0_MXM 6 21 64 76 77
OEM1 39

co
79 MXM_DP_E_ML_N<1> 194 LVDS_LTX1* 52 179
OEM2 40
79 MXM_DP_E_ML_P<1> 196 LVDS_LTX1 53 180
OEM3 41
58 185
79 MXM_DP_E_ML_N<0> 188 LVDS_LTX2* OEM4 42
59 186
79 MXM_DP_E_ML_P<0> 190 LVDS_LTX2 OEM5 43

LVDS
64 191
44

s.
OEM6
96 79 MXM_LVDS_A_DATA_N<3> 182 LVDS_LTX3* 65 192
OEM7 45
MXM_LVDS_A_DATA_P<3>
96 79 184 LVDS_LTX3 70 197 R8500
PNL_BL_EN 25 MXM_PNL_BL_EN 79 71 198 100K 2
C 96 79 MXM_LVDS_B_CLK_N 169 LVDS_UCLK*
76 203
77 MXM_DETECT_L 1
C

ic
96 79 MXM_LVDS_B_CLK_P 171 LVDS_UCLK PNL_BL_PWM 27 MXM_PNL_BL_PWM 84 100 MF-LF 5% 1/16W
77 204 402
GND GND PULLED TO GROUND ON MXM
96 79 MXM_LVDS_B_DATA_N<0> 193 LVDS_UTX0* PNL_PWR_EN 23 MXM_PNL_PWR_EN 79 82 209 WE DON’T USE CARD DETECT
96 79 MXM_LVDS_B_DATA_P<0> 195 LVDS_UTX0 77 76 64 21 6 =PP3V3_S0_MXM 83 210 R8501

at
RSVD0 10
88 215
1
100K 2
96 79 MXM_LVDS_B_DATA_N<1> 187 LVDS_UTX1* RSVD1 159 TP_MXM_N_TDO NOSTUFF 77 MXM_DETECT_R
89 216
96 79 MXM_LVDS_B_DATA_P<1> 189 LVDS_UTX1 RSVD2 12 R85791 MF-LF 5% 1/16W
SYSTEM MANAGEMENT

94 221 402
RSVD3 161 TP_MXM_N_TDI 4.7K
MXM_LVDS_B_DATA_N<2> 181 LVDS_UTX2* 95 222

em
96 79 5%
RSVD4 163 TP_MXM_N_TCK 1/16W
96 79 MXM_LVDS_B_DATA_P<2> 183 LVDS_UTX2 MF-LF 100 228
RSVD5 165 TP_MXM_N_TMS 402 2
101 244
96 79 MXM_LVDS_B_DATA_N<3> 175 LVDS_UTX3* RSVD6 167 TP_MXM_N_TRST_L
106 E3
96 79 MXM_LVDS_B_DATA_P<3> 177 LVDS_UTX3 RSVD7 227 MXM_A_TESTEN
107 250 =PM_MXM_PGOOD_PULLUP 64
RSVD8 229 TP_MXM_A_TRST_L
NOSTUFF 112 251
100 64 PM_MXM_EN 8 PWR_EN RSVD9 231 TP_MXM_A_TDO SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,
POWER/THERMAL

1
R8580 113 256

ch
100 77 64 PM_MXM_PGOOD 6 PWRGOOD RSVD10 233 TP_MXM_A_TDI OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR
4.7K
MANAGEMENT

118 257
47 MXM_PWR_LEVEL 18 PWR_LEVEL RSVD11 235 TP_MXM_A_TMS 5%
1/16W 119 262
RSVD12 237 TP_MXM_A_TCK MF-LF
49 =SMB_MXM_THRM_SCL 34 SMB_CLK 402 2 124 263 R8503
RSVD13 238
49 =SMB_MXM_THRM_SDA 32 SMB_DAT 125 268
PM_MXM_PGOOD 2
10K 1
RSVD14 239 100 77 64
133 269

kS
47 MXM_ALERT_L 22 TH_ALERT* RSVD15 240 MF-LF 5% 1/16W
134 275
47 MXM_OVERT_L 20 TH_OVERT* RSVD16 241 402
139 282
TP_MXM_TH_PWM 24 TH_PWM RSVD17 242
140 283
RSVD18 243
E4
ANALOG DISPLAY

TP_MXM_VGA_DDC_CLK 160 VGA_DDC_CLK RSVD19 245

oo
TP_MXM_VGA_DDC_DAT 158 VGA_DDC_DAT RSVD20 247
RSVD21 249
TP_MXM_VGA_BLUE 172 VGA_BLUE
RSVD22 14
B TP_MXM_VGA_GREEN
TP_MXM_VGA_HSYNC
170
164
VGA_GREEN
VGA_HSYNC
RSVD23 16 B
PRSNT_L* 281 MXM_DETECT_L 77
TP_MXM_VGA_RED 168 VGA_RED
MXM_DETECT_R
TP_MXM_VGA_VSYNC 162 VGA_VSYNC
PRSNT_R* 2
eb 77

WAKE* 4 TP_MXM_WAKE_L
ot
N

A SYNC_MASTER=K62_AARON SYNC_DATE=N/A A
PAGE TITLE

MXM I/O
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

MXM TX CAPS MXM RX CAPS

93 9 PEG_R2D_C_P<0> MXM C8600 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<15> 76 93 MXM C8632 0.1UF 1
IN OUT
93 76 IN
MXM_PCIE_D2R_P<15> 2 10% 16V X5R 402 PEG_D2R_N<0> OUT 9 93

93 9
PEG_R2D_C_N<0> MXM C8601 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<15> 76 93 MXM C8633 0.1UF 1
MXM_PCIE_D2R_N<15> PEG_D2R_P<0>
D
IN OUT
93 76 IN
2 10% 16V X5R 402
OUT 9 93
D
93 9 IN
PEG_R2D_C_N<1> MXM C8602 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<14> OUT 76 93 93 76 IN
MXM_PCIE_D2R_P<14> MXM C8634 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<1> OUT 9 93

PEG_R2D_C_P<1> MXM C8603 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<14> MXM_PCIE_D2R_N<14> MXM C8635 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<1>
93 9 IN OUT 76 93 93 76 IN OUT 9 93

93 9 IN
PEG_R2D_C_N<2> MXM C8604 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<13> OUT 76 93 93 76 IN
MXM_PCIE_D2R_P<13> MXM C8636 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<2> OUT 9 93

93 9 IN
PEG_R2D_C_P<2> MXM C8605 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<13> OUT 76 93 93 76 IN
MXM_PCIE_D2R_N<13> MXM C8637 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<2> OUT 9 93

93 9 IN
PEG_R2D_C_P<3> MXM C8606 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<12> OUT 76 93 93 76 IN
MXM_PCIE_D2R_P<12> MXM C8638 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<3> OUT 9 93

93 9 IN
PEG_R2D_C_N<3> MXM C8607 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<12> OUT 76 93 93 76 IN
MXM_PCIE_D2R_N<12> MXM C8639 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<3> OUT 9 93

m
93 9
PEG_R2D_C_N<4> MXM C8608 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<11> 76 93 MXM C8640 0.1UF 1
IN OUT
93 76 IN
MXM_PCIE_D2R_P<11> 2 10% 16V X5R 402 PEG_D2R_N<4> OUT 9 93

93 9
PEG_R2D_C_P<4> MXM C8609 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<11> 76 93 MXM C8641 0.1UF 1
MXM_PCIE_D2R_N<11> PEG_D2R_P<4>

co
IN OUT 2 10% 16V X5R 402
93 76 IN OUT 9 93

93 9 PEG_R2D_C_N<5> MXM C8610 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<10> 76 93 MXM C8642 0.1UF 1
IN OUT
93 76 IN
MXM_PCIE_D2R_P<10> 2 10% 16V X5R 402 PEG_D2R_N<5> OUT 9 93
PEG_R2D_C_P<5> MXM C8611 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<10>
93 9 IN OUT 76 93
MXM_PCIE_D2R_N<10> MXM C8643 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<5>

s.
93 76 IN OUT 9 93

93 9 IN
PEG_R2D_C_P<6> MXM C8612 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<9> OUT 76 93

C MXM C8613 0.1UF 1 MXM_PCIE_D2R_P<9> MXM C8644 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<6> C

ic
93 9 IN
PEG_R2D_C_N<6> 2 10% 16V X5R 402 MXM_PCIE_R2D_N<9> OUT 76 93
93 76 IN OUT 9 93

93 76 IN
MXM_PCIE_D2R_N<9> MXM C8645 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<6> OUT 9 93

PEG_R2D_C_N<7> MXM C8614 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<8>

at
93 9 IN OUT 76 93
MXM_PCIE_D2R_P<8> MXM C8646 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<7>
93 9 IN
PEG_R2D_C_P<7> MXM C8615 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<8> OUT 76 93
93 76 IN OUT 9 93

93 76 IN
MXM_PCIE_D2R_N<8> MXM C8647 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<7> OUT 9 93

em
93 9 IN
PEG_R2D_C_P<8> MXM C8616 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<7> OUT 76 93

PEG_R2D_C_N<8> MXM C8617 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<7> MXM_PCIE_D2R_P<7> MXM C8648 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<8>
93 9 IN OUT 76 93 93 76 IN OUT 9 93

93 76 IN
MXM_PCIE_D2R_N<7> MXM C8649 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<8> OUT 9 93

93 9 IN
PEG_R2D_C_P<9> MXM C8618 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<6> OUT 76 93

ch
PEG_R2D_C_N<9> MXM C8619 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<6> MXM_PCIE_D2R_P<6> MXM C8650 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<9>
93 9 IN OUT 76 93 93 76 IN OUT 9 93

93 76 IN
MXM_PCIE_D2R_N<6> MXM C8651 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<9> OUT 9 93

93 9 IN
PEG_R2D_C_N<10> MXM C8620 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<5> OUT 76 93

MXM C8621 0.1UF 1

kS
93 9 PEG_R2D_C_P<10> 2 10% 16V X5R 402 MXM_PCIE_R2D_N<5> 76 93 MXM C8652 0.1UF 1
IN OUT
93 76 IN
MXM_PCIE_D2R_P<5> 2 10% 16V X5R 402 PEG_D2R_N<10> OUT 9 93

93 76 IN
MXM_PCIE_D2R_N<5> MXM C8653 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<10> OUT 9 93

93 9 IN
PEG_R2D_C_N<11> MXM C8622 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<4> OUT 76 93

PEG_R2D_C_P<11> MXM C8623 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<4> MXM_PCIE_D2R_P<4> MXM C8654 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<11>

oo
93 9 IN OUT 76 93 93 76 IN OUT 9 93

93 76 IN
MXM_PCIE_D2R_N<4> MXM C8655 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<11> OUT 9 93

B 93 9 IN
PEG_R2D_C_P<12> MXM C8624 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<3> OUT 76 93
B
PEG_R2D_C_N<12> MXM C8625 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<3> MXM_PCIE_D2R_P<3> MXM C8656 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<12>
93 9 IN
eb OUT 76 93 93 76 IN OUT 9 93

MXM_PCIE_D2R_N<3> MXM C8657 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<12>

93 76 IN OUT 9 93

93 9 PEG_R2D_C_N<13> MXM C8626 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<2> 76 93 MXM C8658 0.1UF 1
IN OUT
93 76 IN
MXM_PCIE_D2R_P<2> 2 10% 16V X5R 402 PEG_D2R_P<13> OUT 9 93
C8627 0.1UF 1
ot
PEG_R2D_C_P<13> MXM 2 10% 16V X5R 402 MXM_PCIE_R2D_N<2>
93 9 IN OUT 76 93
93 76 IN
MXM_PCIE_D2R_N<2> MXM C8659 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<13> OUT 9 93

PEG_R2D_C_P<14> MXM C8628 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<1>

93 9 IN OUT 76 93
93 76 IN
MXM_PCIE_D2R_P<1> MXM C8662 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_P<14> OUT 9 93
PEG_R2D_C_N<14> MXM C8629 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<1>
93 9 IN OUT 76 93
93 76 IN
MXM_PCIE_D2R_N<1> MXM C8663 0.1UF 1 2 10% 16V X5R 402 PEG_D2R_N<14> OUT 9 93

93 9 PEG_R2D_C_N<15> MXM C8630 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_P<0> 76 93 MXM C8660 0.1UF 1
IN OUT
93 76 IN
MXM_PCIE_D2R_P<0> 2 10% 16V X5R 402 PEG_D2R_N<15> OUT 9 93

93 9
PEG_R2D_C_P<15> MXM C8631 0.1UF 1 2 10% 16V X5R 402 MXM_PCIE_R2D_N<0> 76 93 MXM C8661 0.1UF 1
IN OUT
93 76 IN
MXM_PCIE_D2R_N<0> 2 10% 16V X5R 402 PEG_D2R_P<15> OUT 9 93

A SYNC_MASTER=K62 SYNC_DATE=N/A A
PAGE TITLE

MXM PCIE CAPS

DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

Signal aliases required by this page:

(NONE)

D BOM options provided by this page:

(NONE)
D
T29 CONN POWER AND CONTROL ALIAS
MXM ALIAS 6 =PP3V3_SW_DPAPWR PP3V3_SW_DPAPWR 85 98

76 MXM_DP_A_ML_P<0..3> DP_EXTA_ML_C_P<0..3> 85 96
MAKE_BASE=TRUE NO_TEST=TRUE
76 MXM_DP_A_ML_N<0..3> DP_EXTA_ML_C_N<0..3> 85 96 6 =PP3V3_SW_DPBPWR PP3V3_SW_DPBPWR 87 98
MAKE_BASE=TRUE NO_TEST=TRUE
76 MXM_DP_A_AUX_P DP_EXTA_AUXCH_C_P 79 85 96
MAKE_BASE=TRUE NO_TEST=TRUE 100 36 33 19 PCIE_WAKE_L =T29_WAKE_L 85 87

76 MXM_DP_A_AUX_N DP_EXTA_AUXCH_C_N 79 85 96
MAKE_BASE=TRUE NO_TEST=TRUE
96 76 MXM_DP_B_ML_P<0..3> DP_T29SNK1_ML_C_P<0..3> 89 99
76 MXM_DP_A_HPD DP_EXTA_HPD 85 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
96 76 MXM_DP_B_ML_N<0..3> DP_T29SNK1_ML_C_N<0..3> 89 99
MAKE_BASE=TRUE NO_TEST=TRUE

m
96 76 MXM_DP_B_AUX_P DP_T29SNK1_AUXCH_C_P 89 99
77 MXM_DP_E_ML_P<0..3> DP_EXTB_ML_C_P<0..3> 87 96 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
96 76 MXM_DP_B_AUX_N DP_T29SNK1_AUXCH_C_N 89 99
77 MXM_DP_E_ML_N<0..3> DP_EXTB_ML_C_N<0..3> 87 96 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE

co
76 MXM_DP_B_HPD DP_T29SNK1_HPD 89
77 MXM_DP_E_AUX_P DP_EXTB_AUXCH_C_P 79 87 96 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
77 MXM_DP_E_AUX_N DP_EXTB_AUXCH_C_N 79 87 96
MAKE_BASE=TRUE NO_TEST=TRUE
96 76 MXM_DP_D_ML_P<0..3> DP_T29SNK0_ML_C_P<0..3> 89 99
MAKE_BASE=TRUE NO_TEST=TRUE
77 MXM_DP_E_HPD DP_EXTB_HPD 87
MXM_DP_D_ML_N<0..3> DP_T29SNK0_ML_C_N<0..3>

s.
MAKE_BASE=TRUE NO_TEST=TRUE 96 76 89 99
MAKE_BASE=TRUE NO_TEST=TRUE

96 76 MXM_DP_D_AUX_P DP_T29SNK0_AUXCH_C_P 89 99
MAKE_BASE=TRUE NO_TEST=TRUE
C MXM_DP_D_AUX_N DP_T29SNK0_AUXCH_C_N C

ic
96 76 89 99
MAKE_BASE=TRUE NO_TEST=TRUE
DDC/AUX ALIAS 76 MXM_DP_D_HPD DP_T29SNK0_HPD
MAKE_BASE=TRUE NO_TEST=TRUE
89

at
96 85 79 DP_EXTA_AUXCH_C_P DP_EXTA_DDC_CLK 85

96 85 79
MAKE_BASE=TRUE
DP_EXTA_AUXCH_C_N DP_EXTA_DDC_DATA 85
UNUSED MXM CONTROL SIGNALS
MAKE_BASE=TRUE

em
96 87 79 DP_EXTB_AUXCH_C_P DP_EXTB_DDC_CLK 87
MAKE_BASE=TRUE 77 MXM_PNL_BL_EN NC_MXM_PNL_BL_EN
96 87 79 DP_EXTB_AUXCH_C_N DP_EXTB_DDC_DATA 87 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE

77 MXM_PNL_PWR_EN NC_MXM_PNL_PWR_EN
MAKE_BASE=TRUE NO_TEST=TRUE
NO_TEST T29 & DP DC BIAS

ch
I81
T29_A_BIAS_R2D_P0 85 86 I99
T29_B_BIAS_R2D_P2 87 88
NO_TEST=TRUE NO_TEST=TRUE
I82
T29_A_BIAS_R2D_N0 85 86 I100
T29_B_BIAS_R2D_N2 87 88
NO_TEST=TRUE NO_TEST=TRUE
T29_A_BIAS_R2D_P1 T29_B_BIAS_R2D_P3

kS
I83 85 86 I101 87 88
NO_TEST=TRUE NO_TEST=TRUE
I84
T29_A_BIAS_R2D_N1 85 86 I102
T29_B_BIAS_R2D_N3 87 88
NO_TEST=TRUE NO_TEST=TRUE
I93
T29_A_BIAS 83 85 86 I103
T29_B_BIAS 83 87 88 99
NO_TEST=TRUE 99 NO_TEST=TRUE
I109
T29_A_BIAS_P1 86 I110
T29_B_BIAS_P3 88
NO_TEST=TRUE NO_TEST=TRUE
I111 T29_A_BIAS_N1 86 I112 T29_B_BIAS_N3 88
NO_TEST=TRUE NO_TEST=TRUE
I89
DP_A_BIAS_P_0 85 86 I104
DP_B_BIAS_P_0 87 88

oo
NO_TEST=TRUE NO_TEST=TRUE
I90
DP_A_BIAS_N_0 85 86 I105
DP_B_BIAS_N_0 87 88
NO_TEST=TRUE NO_TEST=TRUE
I92
DP_A_BIAS_P_2 85 86 I107
DP_B_BIAS_P_2 87 88
NO_TEST=TRUE NO_TEST=TRUE
B I91

I94
DP_A_BIAS_N_2
NO_TEST=TRUE
DP_A_BIAS
85 86

85 99
I106

I108
DP_B_BIAS_N_2
NO_TEST=TRUE
DP_B_BIAS
87 88

87
B
NO_TEST=TRUE NO_TEST=TRUE
eb
Unused MXM Interfaces
ot

96 77 MXM_LVDS_A_DATA_N<3> NC_MXM_LVDS_A_DATA_N<3>
MAKE_BASE=TRUE NO_TEST=TRUE
96 77 MXM_LVDS_A_DATA_P<3> NC_MXM_LVDS_A_DATA_P<3>
MAKE_BASE=TRUE NO_TEST=TRUE
N

96 77 MXM_LVDS_B_CLK_N NC_MXM_LVDS_B_CLK_N
MAKE_BASE=TRUE NO_TEST=TRUE
96 77 MXM_LVDS_B_CLK_P NC_MXM_LVDS_B_CLK_P
MAKE_BASE=TRUE NO_TEST=TRUE
96 77 MXM_LVDS_B_DATA_N<0> NC_MXM_LVDS_B_DATA_N<0>
MAKE_BASE=TRUE NO_TEST=TRUE
96 77 MXM_LVDS_B_DATA_P<0> NC_MXM_LVDS_B_DATA_P<0>
MAKE_BASE=TRUE NO_TEST=TRUE
96 77 MXM_LVDS_B_DATA_N<1> NC_MXM_LVDS_B_DATA_N<1>
MAKE_BASE=TRUE NO_TEST=TRUE
96 77 MXM_LVDS_B_DATA_P<1> NC_MXM_LVDS_B_DATA_P<1>
MAKE_BASE=TRUE NO_TEST=TRUE
96 77 MXM_LVDS_B_DATA_N<2> NC_MXM_LVDS_B_DATA_N<2>
MAKE_BASE=TRUE NO_TEST=TRUE
96 77 MXM_LVDS_B_DATA_P<2> NC_MXM_LVDS_B_DATA_P<2>
MAKE_BASE=TRUE NO_TEST=TRUE
96 77 MXM_LVDS_B_DATA_N<3> NC_MXM_LVDS_B_DATA_N<3>
MAKE_BASE=TRUE NO_TEST=TRUE

A 96 77 MXM_LVDS_B_DATA_P<3> NC_MXM_LVDS_B_DATA_P<3>
MAKE_BASE=TRUE NO_TEST=TRUE
SYNC_MASTER=K62_AARON SYNC_DATE=N/A A
PAGE TITLE

DP ALIAS
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

VDDIO_25M_A: SB power rail for XTAL circuit.

VDDIO_25M_B: Ethernet power rail for XTAL circuit.
VDDIO_25M_C: T29 power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

D For Cougar Point Desktop: VDDIO = VCCVRM

For Cougar Point Mobile: VDDIO = VCCVRM
(1.8V), Vclk = 1.1V Max, Divider: 604 / 1000
(1.5V), Vclk = 1.1V Max, Divider: 332 / 1000
D
For Caesar-IV (BCM57765): VDDIO = XTALVDDH (3.3V), Vclk = 3.3V Max. No Divider Necessary

m
co
6 =PP3V3_S3_SYSCLK

s.
Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell: 3.3V S5
C 80 37 36 =PP3V3_S3_ENET_PHY_FET
C

ic
R8812 1 0
80 37 36 =PP3V3_S3_ENET_PHY_FET 2 98 PPVDDIO_25M_B
MIN_LINE_WIDTH=0.3 mm

at
5% MIN_NECK_WIDTH=0.2 mm
1/16W VOLTAGE=3.3V
MF-LF 98 PPVBAT_G3_SYSCLK_R
402 MIN_LINE_WIDTH=0.3 mm
R8806 0 NOSTUFF MIN_NECK_WIDTH=0.2 mm
24 18 6 =PP1V05_S0_PCH 1 2 VOLTAGE=3.3V
1
R8808

em
5%
1/16W 10K
MF-LF 5%
402 1/16W
MF-LF
R8807 1 0 2 402
80 24 6 =PP1V8R1V5_S0_PCH_VCCVRM 2 98 PPVDDIO_25M_A
MIN_LINE_WIDTH=0.3 mm
5% MIN_NECK_WIDTH=0.2 mm
1/16W VOLTAGE=1.05V No bypass necessary R8825
MF-LF
402 40.2 (1.1V)
1 2 PCH_CLK25M_XTALIN OUT 18 27 94

ch +3.42V 13
1%

VDD_25M 5

+V3.3A 2
1/16W
1
T29 MF-LF
R8826
402
R8810 1 0 VBAT and +V3.3A are 140
90 89 81 6 =PP3V3_T29_RTR 2 98 PPVDDIO_25M_C 1%
internally ORed to 1/16W
5% T29 MF-LF
1/16W create VDD_RTC_OUT.

kS
402
MF-LF
402
C8824 1
C8822 1
C8820 1 1
C8802 2

0 NOSTUFF
0.1UF
20%
0.1UF
20%
0.1UF
20%
1UF
10%
U8800 +V3.3A should be first
80 24 6 =PP1V8R1V5_S0_PCH_VCCVRM R8809 1 2 10V
CERM 2
10V
CERM 2
10V
CERM 2 2
6.3V
CERM SLG3NB148V available ~3.3V power
MIN_LINE_WIDTH=0.3 mm
5% MIN_NECK_WIDTH=0.2 mm
402 402 402 402 TQFN to reduce VBAT draw.
1/16W VOLTAGE=3.3V CRITICAL
MF-LF
402 11 VDDIO_25M_A 32KHZ_A 12 TP_SYSCLK_CLK32K_RTC

oo
6 VDDIO_25M_B
14 9 R8843 T29
C8805 VDDIO_25M_C 25MHZ_A 99 SYSCLK_CLK25M_SB
R8815 33 R8845
B 2
12PF
1 99 SYSCLK_CLK25M_X2 1
0
2 99 SYSCLK_CLK25M_X2_R 3 X2
25MHZ_B
25MHZ_C
8
15
99

99
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_T29_CLK
1

5%
2

1
47
2
ENET_CLK25M_XTALI_OSC
SYSCLK_CLK25M_T29 (1.8V) OUT 89 99
(3.3V) OUT 36 99
B
1/16W
5% NOSTUFF 4 X1 For SB RTC Power MF-LF 5%
5%
50V
CRITICAL
1/16W
MF-LF 1
eb VDD_RTC_OUT 1 TP_PPVRTC_G3_OUT
402 1/16W
MF-LF
R8816
1

CERM 402 402

402 NC Y8805 1M
2

5% GND THRM
NC 25.000MHZ-12PF-20PPM 1/16W
PAD 1
C8810
4

10
16

17
C8806 MF-LF
3

1UF

7
SM-3.2X2.5MM 402
2 10%
12PF 6.3V
2 CERM
1 2 SYSCLK_CLK25M_X1
ot
99
402

5%
NOTE: 30 PPM crystal required
50V
CERM
402
N

A SYNC_MASTER=K62_AARON SYNC_DATE=N/A A
PAGE TITLE

GREEN CLOCK
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

D BOM options provided by this page:

402
2 402 T29
CRITICAL 1
T29
R8907
D

1
(NONE) VDD 100K
Platform (PCIe) Reset 5%
U8900 1/16W
MF-LF
100 27 T29_RESET_L 402
IN SLG4AP016V 2
TDFN =PP1V05_T29 6
=PP3V3_T29_RTR 6 80 81 89 90
R8903 2 + SENSE 2

10K - 0.7V
T29 CLKREQ# ISOLATION T29 5%
1/16W
T29 R8904 2 Open-Drain GPIO
MF-LF
402 DLY
10K 1
Q8950 5% RESET* 4 T29_RESET_RTR_L OUT 89 100

G 1
SSM3K15FV 1/16W 94 21 15 IN T29_SW_RESET_L 3 MR*
MF-LF DLY = 60 ms +/- 20%
SOD-VESM-HF 402
1
6 EN
=T29_CLKREQ_L 89

S
T29_CLKREQ_L T29_CLKREQ_FET_L 8 OUT IN
94 21 15 OUT (OD) IN 7 T29_CLKREQ_ISOL_L

2
MAKE_BASE=TRUE
Pull-up provided by SB page. THRM

m
GND PAD

co
s.
3.3V T29 Switch
U8910
C TPS22924 C

ic
6 =PP3V3_S0_P3V3T29FET PP3V3_T29_FET 6
CSP
A2 A1 Max Current = 1.7A (85C)
B2 VIN VOUT B1
T29
CRITICAL U8910

at
T29
C8910 1 C2 ON
1UF GND Part TPS22924C
10%

C1
6.3V
CERM 2 Type Load Switch

em
402
R(on) 18 mOhm Typ
50 mOhm Max

Max Output: 2A

ch
64 63 6 =PP12V_S0_PWRCTL
T29
1 C8930
0.1UF
10%
CRITICAL 2 16V
X5R
1.05V T29 Switch Q8930

kS
402
BSZ035N03MSG
P-TSDSON-8
T29 PP1V05_T29_FET 6
=PP1V05_S0_P1V05T29FET

3
6

2
oo

S
1
=PP3V3_S0_PWRCTL

G
74 64 63 6

B B

P1V05_S0_T29_EN 4
T29

1
1
R8930
eb 10K VCC
5%
1/16W
MF-LF
U8930
2 402
SLG5AP001
5D TDFN
ON 2
7G CRITICAL S6
ot
8 PG T29
PM_PGOOD_P1V05_S0_T29_FET NC 3

THRM
PAD GND
N

4
100 18 IN T29_PWR_EN

A SYNC_MASTER=K62_AARON SYNC_DATE=(MASTER) A
PAGE TITLE

T29 POWER
DRAWING NUMBER SIZE

Apple Inc. 051-8442 D

- =PP12V_S0_LCD
- =PP3V3_S0_VIDEO

Signal aliases required by this page:

INTERNAL DP INTERFACE INTERNAL DP POWER
(NONE)

BOM options provided by this page:

D IG, MXM, MLB_PNL_PWR, LCD_PNL_PWR CRITICAL

J9002
518S0778 D
CRITICAL
CABLINE-CA
F-RT-SM J9001
R9050 53780-8606
M-RT-SM
SMB_BLC_TCON_SDA 1
0 2
31
7
97 49 6 OUT
5%
1/16W 1 518S0787
I2C MASTER ON TCON 1
R9051 MF-LF
402 97 I2C_TCON_SDA 2
SMB_BLC_TCON_SCL 1
0 2 97 I2C_TCON_SCL 3
2
97 49 6 BI 3
5% 4
1/16W I2C SLAVE ON TCON 4
MF-LF NOSTUFF SMB_DP_TCON_SLA_SDA 5
NOSTUFF 49 IN 5
402 6
1 C9010 1 C9011 49 BI SMB_DP_TCON_SLA_SCL 6
47PF 47PF 7
5% 5%
50V 50V 8
2 CERM 2 CERM 100 84 OUT DP_INT_SPDIF_AUDIO 8
402 402 TP_OPTION1 9

m
100 84 DP_INTPNL_HPD 10
OUT
11
12
L9000
96 84 BI DP_INTPNL_AUX_N FERR-250-OHM
96 84 DP_INTPNL_AUX_P 13 6 =PP12V_S0_LCD
BI

co
1 2 98 PP12V_LCD
14 VOLTAGE=12V
SM MIN_LINE_WIDTH=0.5MM
DP_INTPNL_ML_P<0> 15 MIN_NECK_WIDTH=0.25MM 1 C9020 1 C9001
96 84 IN NO_TEST
96 84 DP_INTPNL_ML_N<0> NO_TEST 16 10UF 0.001uF
IN 10% 20%
17 16V 50V
2 X5R-CERM 2 CERM
18 0805 402
DP_INTPNL_ML_P<1> NO_TEST

s.
96 84 IN
96 84 DP_INTPNL_ML_N<1> NO_TEST 19
IN
20
DP_INTPNL_ML_P<2> 21
C 96 84 IN NO_TEST
C

ic
96 84 DP_INTPNL_ML_N<2> NO_TEST 22
IN
23

96 84 DP_INTPNL_ML_P<3> NO_TEST 24
IN

at
96 84 DP_INTPNL_ML_N<3> NO_TEST 25
IN
26

100 82 VIDEO_ON 27
OUT
R9010 TP_OPTION2 28
0

em
100 6 VSYNC_DP_CONN 100 1 2 VSYNC_DP 29
5% 30
1/10W
MF-LF
603
33
34
35
36

ch
37
38
39
40

kS
41

oo
B eb B

BACKLIGHT CONTROL SUPPORT

guarantee backlight is
only on when Panel has valid video
N

82 6 =PP3V3_S0_DP
82 6 =PP3V3_S0_DP
1 C9006
0.1UF 5 VIDEO_ON_L
OUT
20%
10V
1 C9005
2 CERM 22UF
402 used by diag LED 20%
6.3V
2 CERM
805
5 U9000 5 U9000
74AUP2G14GM
SOT886
D9000
SOT23
74AUP2G14GM
SOT886 R9011
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Apple Inc. 051-8442 D
REVISION
R
10.1.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE

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