L6235

DMOS driver for 3-phase brushless DC motor

Datasheet - production data

 60° and 120° hall effect decoding logic

 Brake function
 Tachometer output for speed loop
 Cross conduction protection
 Thermal shutdown
 Undervoltage lockout
 Integrated fast freewheeling diodes
3RZHU62

Description
The L6235 device is a DMOS fully integrated 3-
phase motor driver with overcurrent protection.
Realized in BCD technology, the device combines
isolated DMOS power transistors with CMOS and
bipolar circuits on the same chip.
The device includes all the circuitry needed to
62 drive a 3-phase BLDC motor including: a 3-phase
 DMOS bridge, a constant off time PWM current
controller and the decoding logic for single ended
hall sensors that generates the required
sequence for the power stage.
2UGHULQJQXPEHUV
/13RZHU',3 Available in PowerSO36 and SO24 (20 + 2 + 2)
/3'3RZHU62 packages, the L6235 device features a non-
/'62 dissipative overcurrent protection on the high-side
power MOSFETs and thermal shutdown.

Features
 Operating supply voltage from 8 to 52 V
 5.6 A output peak current (2.8 A DC)
 RDS(ON) 0.3  typ. value at Tj = 25 °C
 Operating frequency up to 100 KHz
 Non-dissipative overcurrent detection and
protection
 Diagnostic output
 Constant tOFF PWM current controller
 Slow decay synchr. rectification

October 2018 DocID7618 Rev 4 1/34

This is information on a product in full production. www.st.com
Contents L6235

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8 Decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9 Tachometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . 22

11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.1 Output current capability and IC power dissipation . . . . . . . . . . . . . . . . . 26
11.2 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

12 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.1 PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.2 SO24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2/34 DocID7618 Rev 4

L6235 Block diagram

1 Block diagram

Figure 1. Block diagram

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DocID7618 Rev 4 3/34

34
Maximum ratings L6235

2 Maximum ratings

Table 1. Absolute maximum ratings

Symbol Parameter Test conditions Value Unit

VS Supply voltage VSA = VSB = VS 60 V

Differential voltage between:
VSA = VSB = VS = 60 V;
VOD VSA, OUT1, OUT2, SENSEA and VSB, OUT3, 60 V
VSENSEA = VSENSEB = GND
SENSEB
VBOOT Bootstrap peak voltage VSA = VSB = VS VS + 10 V
VIN, VEN Logic inputs voltage range - -0.3 to 7 V
VREF Voltage range at pin VREF - -0.3 to 7 V
VRCOFF Voltage range at pin RCOFF - -0.3 to 7 V
VRCPULSE Voltage range at pin RCPULSE - -0.3 to 7 V
VSENSE Voltage range at pins SENSEA and SENSEB - -1 to 4 V
Pulsed supply current (for each VSA and VSB
IS(peak) VSA = VSB = VS; TPULSE < 1 ms 7.1 A
pin)
IS DC supply current (for each VSA and VSB pin) VSA = VSB = VS 2.8 A
Tstg, TOP Storage and operating temperature range - -40 to 150 °C

Table 2. Recommended operating condition

Symbol Parameter Test conditions Min. Max. Unit

VS Supply voltage VSA = VSB = VS 12 52 V

Differential voltage between:
VSA = VSB = VS;
VOD VSA, OUT1, OUT2, SENSEA and VSB, OUT3, - 52 V
VSENSEA = VSENSEB
SENSEB
VREF Voltage range at pin VREF - -0.1 5 V

(pulsed tW < trr) -6 6 V

VSENSE Voltage range at pins SENSEA and SENSEB
(DC) -1 1 V
IOUT DC output current VSA = VSB = VS - 2.8 A
fSW Switching frequency - - 100 KHz

4/34 DocID7618 Rev 4

L6235 Maximum ratings

Table 3. Thermal data

Symbol Description SO24 PowerSO36 Unit

Rth(j-pins) Maximum thermal resistance junction pins 14 - C/W

Rth(j-case) Maximum thermal resistance junction case - 1 C/W
(1)
Rth(j-amb)1 Maximum thermal resistance junction ambient 51 - C/W
Rth(j-amb)1 Maximum thermal resistance junction ambient(2) - 35 C/W
(3)
Rth(j-amb)1 Maximum thermal resistance junction ambient - 15 C/W
(4)
Rth(j-amb)2 Maximum thermal resistance junction ambient 77 62 C/W
1. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of
35 µm).
2. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm).
3. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm),
16 via holes and a ground layer.
4. Mounted on a multilayer FR4 PCB without any heatsinking surface on the board.

DocID7618 Rev 4 5/34

34
Pin connections L6235

3 Pin connections

Figure 2. Pin connections (top view)

GND 1 36 GND
N.C. 2 35 N.C.
H1 1 24 H3 N.C. 3 34 N.C.
DIAG 2 23 H2 VSA 4 33 VSB

SENSEA 3 22 VCP OUT2 5 32 OUT3

N.C. 6 31 N.C.
RCOFF 4 21 OUT2
VCP 7 30 VBOOT
OUT1 5 20 VSA
H2 8 29 BRAKE
GND 6 19 GND H3 9 28 VREF
GND 7 18 GND H1 10 27 EN
TACHO 8 17 VSB DIAG 11 26 FWD/REV
RCPULSE 9 16 OUT3 SENSEA 12 25 SENSEB

SENSEB 10 15 VBOOT RCOFF 13 24 RCPULSE

N.C. 14 23 N.C.
FWD/REV 11 14 BRAKE
OUT1 15 22 TACHO
EN 12 13 VREF
N.C. 16 21 N.C.
D01IN1194A
N.C. 17 20 N.C.
GND 18 19 GND

D01IN1195A

SO24 PowerSO6(1)

1. The slug is internally connected to pins 1, 18, 19 and 36 (GND pins).

Table 4. Pin description

Package

SO24 PowerSO36 Name Type Function

Pin no. Pin no.

1 10 H1 Sensor input Single ended hall effect sensor input 1.

Overcurrent detection and thermal protection pin. An
Open drain internal open drain transistor pulls to GND when an
2 11 DIAG
output overcurrent on one of the high-side MOSFETs is
detected or during thermal protection.
Half-bridge 1 and half-bridge 2 source pin. This pin
3 12 SENSEA Power supply must be connected together with pin SENSEB to power
ground through a sensing power resistor.
RC network pin. A parallel RC network connected
4 13 RCOFF RC pin between this pin and ground sets the current controller
OFF-time.
5 15 OUT1 Power output Output 1

6/34 DocID7618 Rev 4

L6235 Pin connections

Table 4. Pin description (continued)

Package

SO24 PowerSO36 Name Type Function

Pin no. Pin no.

Ground terminals. On SO24 package, these pins are

also used for heat dissipation toward the PCB. On
6, 7, 18, 19 1, 18, 19, 36 GND GND
PowerSO36 package the slug is connected on these
pins.
Frequency-to-voltage open drain output. Every pulse
Open drain
8 22 TACHO from pin H1 is shaped as a fixed and adjustable length
output
pulse.
RC network pin. A parallel RC network connected
between this pin and ground sets the duration of the
9 24 RCPULSE RC pin
monostable pulse used for the frequency-to-voltage
converter.
Half-bridge 3 source pin. This pin must be connected
together with pin SENSEA to power ground through
10 25 SENSEB Power supply
a sensing power resistor. At this pin also the inverting
input of the sense comparator is connected.
Selects the direction of the rotation. HIGH logic level
sets forward operation, whereas LOW logic level sets
11 26 FWD/REV Logic input reverse operation.
If not used, it has to be connected to GND or +5 V.
Chip enable. LOW logic level switches OFF all power
12 27 EN Logic input
MOSFETs. If not used, it has to be connected to +5 V.
Current controller reference voltage.
13 28 VREF Logic input
Do not leave this pin open or connect to GND.
Brake input pin. LOW logic level switches ON all high-
14 29 BRAKE Logic input side power MOSFETs, implementing the brake function.
If not used, it has to be connected to +5 V.
Supply Bootstrap voltage needed for driving the upper power
15 30 VBOOT
voltage MOSFETs.
16 32 OUT3 Power output Output 3.
Half-bridge 3 power supply voltage. It must be
17 33 VSB Power supply
connected to the supply voltage together with pin VSA.
Half-bridge 1 and half-bridge 2 power supply voltage. It
20 4 VSA Power supply must be connected to the supply voltage together with
pin VSB.
21 5 OUT2 Power output Output 2.
22 7 VCP Output Charge pump oscillator output.
23 8 H2 Sensor input Single ended hall effect sensor input 2.
24 9 H3 Sensor input Single ended hall effect sensor input 3.

DocID7618 Rev 4 7/34

34
Electrical characteristics L6235

4 Electrical characteristics

Table 5. Electrical characteristics

(VS = 48 V, Tamb = 25 °C, unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSth(ON) Turn ON threshold - 6.6 7.4 - V
VSth(OFF) Turn OFF threshold - 5.6 6 6.4 V
All bridges OFF;
IS Quiescent supply current - 5 10 mA
Tj = -25 to 125 °C(1)
TJ(OFF) Thermal shutdown temperature - - 165 - C
Output DMOS transistors
Tj = 25 °C - 0.34 0.4 
High-side switch ON resistance
Tj =125 °C(1) - 0.53 0.59 
RDS(ON)
Tj = 25 °C - 0.28 0.34 
Low-side switch ON resistance
Tj = 125 °C(1) - 0.47 0.53 
EN = low; OUT = VCC - - 2 mA
IDSS Leakage current
EN = low; OUT = GND -0.15 - - mA
Source drain diodes
VSD Forward ON voltage ISD = 2.8 A, EN = LOW - 1.15 1.3 V
trr Reverse recovery time If = 2.8 A - 300 - ns
tfr Forward recovery time - - 200 - ns
Logic input (H1, H2, H3, EN, FWD/REV, BRAKE)
VIL Low level logic input voltage - -0.3 - 0.8 V
VIH High level logic input voltage - 2 - 7 V
IIL Low level logic input current GND logic input voltage -10 - - A
IIH High level logic input current 7 V logic input voltage - - 10 A
Vth(ON) Turn-ON input threshold - - 1.8 2.0 V
Vth(OFF) Turn-OFF input threshold - 0.8 1.3 - V
VthHYS Input thresholds hysteresis - 0.25 0.5 - V
Switching characteristics
tD(on)EN Enable to out turn-ON delay time(2) ILOAD = 2.8 A, resistive load 110 250 400 ns
tD(off)EN Enable to out turn-OFF delay time (2)
ILOAD = 2.8 A, resistive load 300 550 800 ns
Other logic inputs to output turn-ON delay
tD(on)IN ILOAD = 2.8 A, resistive load - - 2 µs
time
Other logic inputs to out turn-OFF delay
tD(off)IN ILOAD = 2.8 A, resistive load - - 2 µs
time
tRISE Output rise time(2) ILOAD = 2.8 A, resistive load 40 - 250 ns
tFALL Output fall time(2) ILOAD = 2.8 A, resistive load 40 - 250 ns
tDT Deadtime 0.5 1 - µs
fCP Charge pump frequency Tj = -25 to 125 °C(1) - 0.6 1 MHz

8/34 DocID7618 Rev 4

L6235 Electrical characteristics

Table 5. Electrical characteristics (continued)

(VS = 48 V, Tamb = 25 °C, unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit

PWM comparator and monostable

IRCOFF Source current at pin RCOFF VRCOFF = 2.5 V 3.5 5.5 - mA
VOFFSET Offset voltage on sense comparator Vref = 0.5 V - ±5 - mV
(3)
tprop Turn OFF propagation delay Vref = 0.5 V - 500 - ns
tblank Internal blanking time on sense comparator - - 1 - µs
tON(min) Minimum on time - - 1.5 2 µs
ROFF = 20 k; COFF 1 nF - 13 - s
tOFF PWM recirculation time
ROFF= 100 k; COFF 1 nF - 61 - s
IBIAS Input bias current at pin VREF - - - 10 µA
TACHO monostable
IRCPULSE Source current at pin RCPULSE VRCPULSE = 2.5 V 3.5 5.5 - mA
RPUL = 20 k; CPUL 1 nF - 12 - s
tPULSE Monostable of time
RPUL = 100 k; CPUL 1 nF - 60 - s
RTACHO Open drain ON resistance - - 40 60 
Overcurrent detection and protection
ISOVER Supply overcurrent protection threshold TJ = -25 to 125 °C(1) 4.0 5.6 7.1 A
ROPDR Open drain ON resistance IDIAG = 4 mA - 40 60 
IOH OCD high level leakage current VDIAG = 5 V - 1 - µA
tOCD(ON) OCD turn-ON delay time(4) IDIAG = 4 mA; CDIAG < 100 pF - 200 - ns
tOCD(OFF) OCD turn-OFF delay time(4) IDIAG = 4 mA; CDIAG < 100 pF - 100 - ns
1. Tested at 25 °C in a restricted range and guaranteed by characterization.
2. See Figure 3: Switching characteristic definition.
3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
4. See Figure 4: Overcurrent detection timing definition.

DocID7618 Rev 4 9/34

34
Electrical characteristics L6235

Figure 3. Switching characteristic definition

EN

Vth(ON)

Vth(OFF)

t
IOUT

90%

10%
t
D01IN1316
tFALL tRISE
tD(OFF)EN tD(ON)EN

Figure 4. Overcurrent detection timing definition

IOUT

ISOVER

ON
BRIDGE
OFF

VDIAG

90%

10%

D02IN1387
tOCD(ON) tOCD(OFF)

10/34 DocID7618 Rev 4

L6235 Circuit description

5 Circuit description

5.1 Power stages and charge pump

The L6235 device integrates a 3-phase bridge, which consists of 6 power MOSFETs
connected as shown in Figure 1: Block diagram on page 3. Each power MOS has an
RDS(ON) = 0.3 (typical value at 25 °C) with intrinsic fast freewheeling diode. Switching
patterns are generated by the PWM current controller and the hall effect sensor decoding
logic (see Section 6: PWM current control on page 13 and Section 8: Decoding logic on
page 18). Cross conduction protection is implemented by using a deadtime (tDT = 1 µs
typical value) set by internal timing circuit between the turn off and turn on of two power
MOSFETs in one leg of a bridge.
Pins VSA and VSB MUST be connected together to the supply voltage (VS).
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 KHz
(typically) with 10 V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Table 6.

Table 6. Charge pump external component values

Component Value
CBOOT 22 0nF
CP 10 nF
RP 100 
D1 1N4148
D2 1N4148

Figure 5. Charge pump circuit

VS

D1 CBOOT
D2

RP

CP

VCP VBOOT VSA VSB D01IN1328

DocID7618 Rev 4 11/34

34
Circuit description L6235

5.2 Logic inputs

Pins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS compatible logic inputs. The
internal structure is shown in Figure 6. Typical value for turn-ON and turn-OFF thresholds
are respectively Vth(ON) = 1.8 V and Vth(OFF) = 1.3 V.
Pin EN (enable) may be used to implement overcurrent and thermal protection by
connecting it to the open collector DIAG output. If the protection and an external disable
function are both desired, the appropriate connection must be implemented. When the
external signal is from an open collector output, the circuit in Figure 7 can be used. For
external circuits that are push-pull outputs the circuit in Figure 8 could be used. The resistor
REN should be chosen in the range from 2.2 K to 180 K. Recommended values for REN
and CEN are respectively 100 K and 5.6 nF. More information for selecting the values can
be found in Section 10: Non-dissipative overcurrent detection and protection on page 22.

Figure 6. Logic input internal structure

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Figure 7. Pin EN open collector driving

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12/34 DocID7618 Rev 4

L6235 PWM current control

6 PWM current control

The L6235 device includes a constant off time PWM current controller. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense
resistor connected between the source of the three lower power MOS transistors and
ground, as shown in Figure 9. As the current in the motor increases the voltage across the
sense resistor increases proportionally. When the voltage drop across the sense resistor
becomes greater than the voltage at the reference input pin VREF the sense comparator
triggers the monostable switching the bridge off. The power MOS remains off for the time
set by the monostable and the motor current recirculates around the upper half of the bridge
in slow decay mode as described in Section 7: Slow decay mode on page 17. When the
monostable times out, the bridge will again turn on. Since the internal deadtime, used to
prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective
off time tOFF is the sum of the monostable time plus the deadtime.
Figure 10 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the pin RC voltage and the status of the bridge. More details
regarding the synchronous rectification and the output stage configuration are included in
Section 7.
Immediately after the power MOS turns on, a high peak current flows through the sense
resistor due to the reverse recovery of the freewheeling diodes. The L6235 device provides
a 1 µs blanking time tBLANK that inhibits the comparator output so that the current spike
cannot prematurely retrigger the monostable.

Figure 9. PWM current controller simplified schematic

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DocID7618 Rev 4 13/34

34
PWM current control L6235

Figure 10. Output current regulation waveforms

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Figure 11 shows the magnitude of the off time tOFF versus COFF and ROFF values. It can be
approximately calculated from the equations:

Equation 1
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated
deadtime with:

Equation 2
20 K  ROFF  100 K
0.47 nF  COFF  100 nF
tDT = 1 µs (typical value)
Therefore:

Equation 3
tOFF(MIN) = 6.6 µs
tOFF(MAX) = 6 ms

14/34 DocID7618 Rev 4

L6235 PWM current control

These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the rise time tRCRISE of the voltage at the
pin RCOFF. The rise time tRCRISE will only be an issue if the capacitor is not completely
charged before the next time the monostable is triggered. Therefore, the on time tON, which
depends by motors and supply parameters, has to be bigger than tRCRISE for allowing
a good current regulation by the PWM stage. Furthermore, the on time tON cannot be
smaller than the minimum on time tON(MIN).

Equation 4

 t ON  t ON  MIN  = 1.5s (typ. value)


 t ON  t RCRISE – t DT
tRCRISE = 600 · COFF
Figure 12 shows the lower limit for the on time tON for having a good PWM current
regulation capacity. It has to be said that tON is always bigger than tON(MIN) because the
device imposes this condition, but it can be smaller than tRCRISE - tDT. In this last case the
device continues to work but the off time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller on time and,
therefore, higher switching frequency), but, the smaller is the value for COFF, the more
influential will be the noises on the circuit performance.

Figure 11. tOFF versus COFF and ROFF


 

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DocID7618 Rev 4 15/34

34
PWM current control L6235

Figure 12. Area where tON can vary maintaining the PWM regulation


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16/34 DocID7618 Rev 4

L6235 Slow decay mode

7 Slow decay mode

Figure 13 shows the operation of the bridge in the slow decay mode during the off time. At
any time only two legs of the 3-phase bridge are active, therefore only the two active legs of
the bridge are shown in Figure 13 and the third leg will be off. At the start of the off time, the
lower power MOS is switched off and the current recirculates around the upper half of the
bridge. Since the voltage across the coil is low, the current decays slowly. After the deadtime
the upper power MOS is operated in the synchronous rectification mode reducing the
impedance of the freewheeling diode and the related conducting losses. When the
monostable times out, upper MOS that was operating the synchronous mode turns off and
the lower power MOS is turned on again after some delay set by the deadtime to prevent
cross conduction.

Figure 13. Slow decay mode output stage configurations

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DocID7618 Rev 4 17/34

34
Decoding logic L6235

8 Decoding logic

The decoding logic section is a combinatory logic that provides the appropriate driving of the
3-phase bridge outputs according to the signals coming from the three hall sensors that
detect rotor position in a 3-phase BLDC motor. This novel combinatory logic discriminates
between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 electrical
degrees. This decoding method allows the implementation of a universal IC without
dedicating pins to select the sensor configuration.
There are eight possible input combinations for three sensor inputs. Six combinations are
valid for rotor positions with 120 electrical degrees sensor phasing (see Figure 14, positions
1, 2, 3a, 4, 5 and 6a) and six combinations are valid for rotor positions with 60 electrical
degrees phasing (see Figure 15, positions 1, 2, 3b, 4, 5 and 6b). Four of them are in
common (1, 2, 4 and 5) whereas there are two combinations used only in 120 electrical
degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical
degrees sensor phasing (3b and 6b).
The decoder can drive motors with different sensor configuration simply by following
Table 7. For any input configuration (H1, H2 and H3) there is one output configuration
(OUT1, OUT2 and OUT3). The output configuration 3a is the same as 3b and analogously
output configuration 6a is the same as 6b.
The sequence of the hall codes for 300 electrical degrees phasing is the reverse of 60 and
the sequence of the hall codes for 240 phasing is the reverse of 120. So, by decoding the 60
and the 120 codes it is possible to drive the motor with all the four conventions by changing
the direction set.

Table 7. 60 and 120 electrical degree decoding logic in forward direction

Hall 120° 1 2 3a - 4 5 6a -

Hall 60° 1 2 - 3b 4 5 - 6b

H1 H H L H L L H L
H2 L H H H H L L L
H3 L L L H H H H L
OUT1 Vs High Z GND GND GND High Z Vs Vs
OUT2 High Z Vs Vs Vs High Z GND GND GND
OUT3 GND GND High Z High Z Vs Vs High Z High Z
Phasing 1 -> 3 2 -> 3 2 -> 1 2 -> 1 3 -> 1 3 -> 2 1 -> 2 1 -> 2

18/34 DocID7618 Rev 4

L6235 Decoding logic

Figure 14. 120° hall sensor sequence

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Figure 15. 60° hall sensor sequence

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DocID7618 Rev 4 19/34

34
Tachometer L6235

9 Tachometer

A tachometer function consists of a monostable, with constant off time (tPULSE), whose input
is one hall effect signal (H1). It allows developing an easy speed control loop by using an
external op amp, as shown in Figure 16. For component values refer to Section 11:
Application information on page 25.
The monostable output drives an open drain output pin (TACHO). At each rising edge of the
hall effect sensors H1, the monostable is triggered and the MOSFET connected to the pin
TACHO is turned off for a constant time tPULSE (see Figure 17). The off time tPULSE can be
set using the external RC network (RPUL, CPUL) connected to the pin RCPULSE. Figure 18
gives the relation between tPULSE and CPUL, RPUL. We have approximately:

Equation 5
tPULSE = 0.6 · RPUL · CPUL
where CPUL should be chosen in the range 1nF to 100 nF and RPUL in the range 20 K to
100 K.
By connecting the tachometer pin to an external pull-up resistor, the output signal average
value VM is proportional to the frequency of the hall effect signal and, therefore, to the motor
speed. This realizes a simple frequency-to-voltage converter. An op amp, configured as an
integrator, filters the signal and compares it with a reference voltage VREF, which sets the
speed of the motor.

Equation 6

t PULSE
V M = -----------------  V DD
T

Figure 16. TACHO operation waveforms

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20/34 DocID7618 Rev 4

L6235 Tachometer

Figure 17. Tachometer speed control loop

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DocID7618 Rev 4 21/34

34
Non-dissipative overcurrent detection and protection L6235

10 Non-dissipative overcurrent detection and protection

The L6235 device integrates an “Overcurrent Detection” circuit (OCD) for full protection.
This circuit provides output to output and output to ground short-circuit protection as well.
With this internal overcurrent detection, the external current sense resistor normally used
and its associated power dissipation are eliminated. Figure 19 shows a simplified schematic
for the overcurrent detection circuit.
To implement the overcurrent detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high-side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current IREF. When the
output current reaches the detection threshold (typically ISOVER = 5.6 A) the OCD
comparator signals a fault condition. When a fault condition is detected, an internal open
drain MOS with a pull down capability of 4 mA connected to pin DIAG is turned on.
The pin DIAG can be used to signal the fault condition to a C or to shut down the 3-phase
bridge simply by connecting it to pin EN and adding an external R-C (see REN, CEN).

Figure 19. Overcurrent protection simplified schematic

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Figure 20 shows the overcurrent detection operation. The disable time tDISABLE before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by CEN and REN values and its
magnitude is reported in Figure 21. The delay time tDELAY before turning off the bridge when
an overcurrent has been detected depends only by CEN value. Its magnitude is reported in
Figure 22.
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore
the value of CEN should be chosen as big as possible according to the maximum tolerable
delay time and the REN value should be chosen according to the desired disable time.
The resistor REN should be chosen in the range from 2.2 K to 180 K. Recommended
values for REN and CEN are respectively 100 K and 5.6 nF that allow obtaining 200 s
disable time.

22/34 DocID7618 Rev 4

L6235 Non-dissipative overcurrent detection and protection

Figure 20. Overcurrent protection waveforms

IOUT

ISOVER

VEN=VDIAG

VDD

Vth(ON)
Vth(OFF)
VEN(LOW)

ON
OCD
OFF

ON

BRIDGE tDELAY tDISABLE

OFF

tOCD(ON) tEN(FALL) tOCD(OFF) tEN(RISE) tD(ON)EN

tD(OFF)EN
D02IN1383

Figure 21. tDISABLE versus CEN and REN

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DocID7618 Rev 4 23/34

34
Non-dissipative overcurrent detection and protection L6235

Figure 22. tDELAY versus CEN



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24/34 DocID7618 Rev 4

L6235 Application information

11 Application information

A typical application using the L6235 device is shown in Figure 23. Typical component
values for the application are shown in Table 8. A high quality ceramic capacitor (C2) in the
range of 100 nF to 200 nF should be placed between the power pins VSA and VSB and
ground near the L6235 device to improve the high frequency filtering on the power supply
and reduce high frequency transients generated by the switching. The capacitor (CEN)
connected from the EN input to ground sets the shutdown time when an overcurrent is
detected (see Section 10: Non-dissipative overcurrent detection and protection). The two
current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistor
RSENSE with a trace length as short as possible in the layout. The sense resistor should be
non-inductive resistor to minimize the di/dt transients across the resistor. To increase noise
immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic
level) (see Table 4: Pin description on page 6). It is recommended to keep power ground
and signal ground separated on the PCB.

Table 8. Component values for typical application

Component Value
C1 100 µF
C2 100 nF
C3 220 nF
CBOOT 220 nF
COFF 1 nF
CPUL 10 nF
CREF1 33 nF
CREF2 100 nF
CEN 5.6 nF
CP 10 nF
D1 1N4148
D2 1N4148
R1 5.6 K
R2 1.8 K
R3 4.7 K
R4 1 M
RDD 1 K
REN 100 K
RP 100 
RSENSE 0.3 
ROFF 33 K
RPUL 47 K
RH1, RH2, RH3 10 K

DocID7618 Rev 4 25/34

34
Application information L6235

Figure 23. Typical application

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11.1 Output current capability and IC power dissipation

In Figure 24 is shown the approximate relation between the output current and the IC power
dissipation using PWM current control.
For a given output current the power dissipated by the IC can be easily evaluated, in order
to establish which package should be used and how large must be the on-board copper
dissipating area to guarantee a safe operating junction temperature (125 °C maximum).

Figure 24. IC power dissipation versus output power

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26/34 DocID7618 Rev 4

L6235 Application information

11.2 Thermal management

In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Selecting the
appropriate package and heatsinking configuration for the application is required to maintain
the IC within the allowed operating temperature range for the application. Figure 25 and 26
show the junction to ambient thermal resistance values for the PowerSO36 and SO24
packages.
For instance, using a PowerSO package with a copper slug soldered on a 1.5 mm copper
thickness FR4 board with a 6 cm2 dissipating footprint (copper thickness of 35 m), the
Rth(j-amb) is about 35 °C/W. Figure 27 shows mounting methods for this package. Using
a multilayer board with vias to a ground plane, thermal impedance can be reduced down to
15 °C/W.

Figure 25. PowerSO36 junction ambient thermal resistance versus on-board copper
area
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DocID7618 Rev 4 27/34

34
Application information L6235

Figure 27. Mounting the PowerSO package

Slug soldered Slug soldered Slug soldered to PCB with

to PCB with to PCB with dissipating area plus ground layer
dissipating area dissipating area contacted through via holes
plus ground layer

28/34 DocID7618 Rev 4

L6235 Application information

Figure 28. Typical quiescent current vs. supply Figure 29. Typical high-side RDS(ON) vs. supply
voltage voltage

Iq [m A]
5.6 RDS(ON) []
fsw = 1 kHz Tj = 25 °C
0.380
5.4 Tj = 85 °C 0.376
0.372
Tj = 125 °C Tj = 25 °C
5.2
0.368
0.364
0.360
5.0
0.356
0.352
4.8 0.348
0.344
4.6 0.340
0 10 20 30 40 50 60 0.336
V S [V] 0 5 10 15 20 25 30
VS [V]

Figure 30. Normalized typical quiescent current Figure 31. Normalized RDS(ON) vs. junction
vs. switching frequency temperature (typical value)

Iq / (Iq @ 1 kHz)
1.7 R DS (ON) / (RDS(ON) @ 25 °C)

1.6 1.8

1.5
1.6
1.4

1.3 1.4

1.2
1.2
1.1

1.0 1.0

0.9
0.8
0 20 40 60 80 100
fSW [kHz] 0 20 40 60 80 100 120 140
Tj [°C]

Figure 32. Typical low-side RDS(ON) vs. supply Figure 33. Typical drain-source diode forward
voltage ON characteristic

R DS(ON) []
ISD [A]
0.300
3.0
Tj = 25 °C
0.296
Tj = 25 °C 2.5
0.292
2.0
0.288
1.5
0.284
1.0
0.280
0.5

0.276
0.0
0 5 10 15 20 25 30
V S [V] 700 800 900 1000 1100 1200 1300
VSD [mV]

DocID7618 Rev 4 29/34

34
Package information L6235

12 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

12.1 PowerSO36 package information

Figure 34. PowerSO36 package outline

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30/34 DocID7618 Rev 4

L6235 Package information

Table 9. PowerSO36 package mechanical data

Dimensions

Symbol mm inch

Min. Typ. Max. Min. Typ. Max.

A - - 3.60 - - 0.141
a1 0.10 - 0.30 0.004 - 0.012
a2 - - 3.30 - - 0.130
a3 0 - 0.10 0 - 0.004
b 0.22 - 0.38 0.008 - 0.015
c 0.23 - 0.32 0.009 - 0.012
D(1) 15.80 - 16.00 0.622 - 0.630
D1 9.40 - 9.80 0.370 - 0.385
E 13.90 - 14.50 0.547 - 0.570
e - 0.65 - - 0.0256 -
e3 - 11.05 - - 0.435 -
(1)
E1 10.90 - 11.10 0.429 - 0.437
E2 - - 2.90 - - 0.114
E3 5.80 - 6.20 0.228 - 0.244
E4 2.90 - 3.20 0.114 - 0.126
G 0 - 0.10 0 - 0.004
H 15.50 - 15.90 0.610 - 0.626
h - - 1.10 - - 0.043
L 0.80 - 1.10 0.031 - 0.043
N 10° (max.)
S 8° (max.)
1. “D” and “E1” do not include mold flash or protrusions.
- Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch).
- Critical dimensions are “a3”, “E” and “G”.

DocID7618 Rev 4 31/34

34
Package information L6235

12.2 SO24 package information

Figure 35. SO24 package outline

 &

Table 10. SO24 package mechanical data

Dimensions (mm) Dimensions (inch)
Symbol
Min. Typ. Max. Min. Typ. Max.

A 2.35 - 2.65 0.093 - 0.104

A1 0.10 - 0.30 0.004 - 0.012
B 0.33 - 0.51 0.013 - 0.020
C 0.23 - 0.32 0.009 - 0.013
D(1) 15.20 - 15.60 0.598 - 0.614
E 7.40 - 7.60 0.291 - 0.299
e - 1.27 - - 0.050 -
H 10.0 - 10.65 0.394 - 0.419
h 0.25 - 0.75 0.010 - 0.030
L 0.40 - 1.27 0.016 - 0.050
k 0° (min.), 8° (max.)
ddd - - 0.10 - - 0.004
1. “D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm per side.

32/34 DocID7618 Rev 4

L6235 Revision history

13 Revision history

Table 11. Document revision history

Date Revision Changes

03-Sep-2003 1 Initial release.

Updated Section : Description on page 1 (removed “MultiPower-” from “MultiPower-
BCD technology”). Added Contents on page 2.
Updated Section 1 on page 3 (added section title, numbered and moved Figure 1:
Block diagram from page 1 to page 3).
Added title to Section 2 on page 4, added numbers and titles from Table 1 to Table 3.
Added title to Section 3 on page 6, added number and title to Figure 2, renumbered
note 1 below Figure 2, added title to Table 4.
Added title to Section 4 on page 8, added title and number to Table 5, renumbered
notes 1 to 4 below Table 5. Renumbered Figure 3 and Figure 4.
Added section numbers to Section 5 on page 11, Section 5.1 and Section 5.2.
Removed “and C” from first sentence in Section 5.2. Renumbered Table 6, added
header to Table 6. Renumbered Figure 5 to Figure 8.
Added section numbers to Section 6 on page 13. Renumbered Figure 9 to Figure 12.
Numbered Equation 1 to Equation 4.
03-Mar-2014 2 Added section number to Section 7 on page 17. Renumbered Figure 13.
Added section number to Section 8 on page 18. Renumbered Table 7. Renumbered
Figure 14 and Figure 15.
Added section number to Section 9 on page 20. Renumbered Figure 16 to Figure 18.
Numbered Equation 5 and Equation 6.
Added section number to Section 10 on page 22. Renumbered Figure 19 to Figure 22.
Added section numbers to Section 11 on page 25, Section 11.1 and Section 11.2.
Renumbered Table 8, added header to Table 8. Renumbered Figure 23 to Figure 34.
Updated Section on page 34 (added main title and ECOPACK text. Added titles from
Table 9 to Table 11 and from Figure 35 to Figure 37, reversed order of named tables
and figures. Removed 3D figures of packages, replaced 0.200 by 0.020 inch of max. B
value in Table 11).
Added cross-references throughout document.
Added Section 13 and Table 12.
Minor modifications throughout document.
Updated Table 5 on page 8 (replaced units “W” by “” , updated cross-references to
15-Oct-2014 3 notes of ISOVER and tOCD(OFF) symbols).
Minor modifications throughout document.
Removed PowerDIP24 package from the whole document.
04-Oct-2018 4 Removed “Tj“ from Table 2 on page 4.
Minor modifications throughout document.

DocID7618 Rev 4 33/34

34
 L6235

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2018 STMicroelectronics – All rights reserved

34/34 DocID7618 Rev 4