L9959

Single and dual PMOS high-side H-bridge

Datasheet - production data

 Current-monitoring with current feedback

output signal CF
 SPI-interface for configuration and diagnosis
 Error history in second diagnosis register
 Two independent enable pins: "/ABE" and
"DIS"
 Control of power stages by SPI or two input
'!0'03
signals, PWM and DIR (configurable via SPI)
'!0'03

PowerSSO24 PowerSSO36  Logic levels 5 V compatible

 Conformity to improved EMC requirements due
to smart H-bridge switching

Description
Features
L9959S/L9959U and L9959T are single and dual
 Full path RDSON less than 540 mΩ integrated H-bridges for resistive and inductive
 Continuous load current > 3 A loads featuring output current direction and
 Operating battery supply voltage 5 V to 28 V supervising functions.
 Operating VDD supply voltage 4.5 V to 5.5 V The PowerSSO24 houses one full H-Bridge, while
the PowerSSO36 houses both two H-Bridges that
 All ECU internal pins can withstand up to 18 V
can work in parallel, through independent input
 Output switching frequency up to 11 kHz driving commands, and one full H-bridge, by
 Monitoring of VDD supply voltage improving PCB footprint design versus different
target applications.
 SPI programmable output current limitation
from 5 A to 8.6 A (in 3 steps) Target application ranges from throttle control
 Over temperature and short circuit protection actuators to exhaust gas recirculation control
valves in automotive domain to a more general
 Full diagnosis capability use to drive DC and Stepper motors.
 Fast switch-off open-drain input/output

Table 1. Device summary

Order code Package Packing

L9959S-TR-D PowerSSO24 Tape & Reel

L9959T-TR-D PowerSSO36 Tape & Reel
L9959U-TR-D PowerSSO36 Tape & Reel

February 2016 DocID027540 Rev 3 1/49

This is information on a product in full production. www.st.com
Contents L9959

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 Outputs OUT1 and OUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 Temperature dependent current reduction . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Free-wheeling diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8 SPI / logic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 Power stage switching behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.1 PWM mode (same current direction) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.2 DIR-change mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Protection and monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.1 Current feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.2 Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.3 Temperature dependent current reduction . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.4 Short to battery (SCB) and short to Ground (SCG) . . . . . . . . . . . . . . . . 28
4.2.5 Short circuit over load (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.6 Open load (OL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3 VS-undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4 Inverse current at VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5 /ABE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6 VDD-monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.7 VDD-monitor test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.8 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/49 DocID027540 Rev 3

L9959 Contents

5 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.1 SPI select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.2 Serial data In (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.3 Serial clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.4 Serial out (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.5 SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 SPI-instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3 Device register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4 SPI - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.4.1 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.4.2 Configuration registers reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1 PowerSSO-24 (exposed pad) package information . . . . . . . . . . . . . . . . . 42
7.2 PowerSSO-36 (exposed pad) package information . . . . . . . . . . . . . . . . . 45

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

DocID027540 Rev 3 3/49

3
List of tables L9959

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. L9959S PSSO24 pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. L9959T (Two H-Bridge drivers in one package) PSSO36 pin-out . . . . . . . . . . . . . . . . . . . . 9
Table 4. L9959U (Single version in PSSO36) pin out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. VDD monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. On-resistance (4.5 V < VS < 28 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. Power output switching times (8 V < VS < 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 14. Current feedback (CF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 15. Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 16. Over-current detection (8 V < VS < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 17. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 18. Retest delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 19. Temperature dependent current reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 20. Free-wheel diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 21. Inputs: SI, SS, SCK, DIR, DIS and PWM; Output: SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 22. Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 23. Device states with respect to supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 24. SPI instruction byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 25. Check byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 26. Command overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 27. Device identifier (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 28. Revision register (REV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 29. DIA_REG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 30. Diagnosis bits (DIA_REG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 31. Diagnosis register 2 (DIA_REG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 32. Diagnosis bits (DIA_REG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 33. Configuration register (CONFIG_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 34. Current Level (CONFIG_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 35. Status and configuration register (STATCON_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 36. Special register (SPECIAL_REG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 37. PowerSSO-24 (exposed pad) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 38. PowerSSO-36 (exposed pad) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 39. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4/49 DocID027540 Rev 3

L9959 List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. PSSO24 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. PSSO36 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. PSSO36 (Single version) pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Output delay times (e.g. low-side output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Output rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Output disable and enable time (/ABE Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Output disable and enable time (DIS Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. SPI timing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. PWM mode current flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. PWM mode output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. DIR-change (current is changing its direction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. DIR-change current flow phase 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. DIR-change output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. Current feedback and current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. Current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. Temperature dependent current reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18. Current limiting and short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19. Write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. Read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21. Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 22. PowerSSO-24 (exposed pad) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 23. PowerSSO-36 (exposed pad) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DocID027540 Rev 3 5/49

5
Block diagram L9959

1 Block diagram

Figure 1. Block diagram

63
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#ONTROLLER

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-ONITORING

63
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$)3

3/
)N TERFACE

3)
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3#+

33

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!'.$

0'.$

'!0'03

6/49 DocID027540 Rev 3

L9959 Pins description

2 Pins description

Figure 2. PSSO24 pin connection (top view)

.#   .#

0'.$   /54

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.#   07-

3#+   $)2

33 
033/  $)3

3)   63

3/   6$$

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Figure 3. PSSO36 pin connection (top view)

0'.$   /54

/54   07-

3#+   $)2

33   $)3

3)   63

3/   63

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!"%   .#

'.$!"%   !'.$
033/
!'.$   '.$!"%

.#   !"%

6$$   #&

63   3/

63   3)

$)3   33

$)2   3#+

07-   /54

/54   0'.$

'!0'03

DocID027540 Rev 3 7/49

48
Pins description L9959

Figure 4. PSSO36 (Single version) pin connection (top view)

0'.$   /54

/54   07-

3#+   $)2

33   $)3

3)   63

3/   63

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*$3*36

2.1 Pin definitions and functions

Table 2. L9959S PSSO24 pin-out
Pin Symbol Function

1, 4,
12, 13,
NC To be connected to GND on PCB.
14, 16,
22, 24
2 PGND Power Ground
Bridge output 1 and 2:
3 OUT1
The bridge outputs are built of a high-side p-channel and a low-side N-channel transistor.
Serial clock input:
5 SCK
This input controls the internal shift register of the SPI.
Slave Select input:
6 SS The serial data transfer between the device and the micro controller is enabled by pulling
the input SS to low level.
Slave in (Serial data input):
7 SI
The input receives serial data from the microcontroller.
Slave Out (Serial data output):
8 SO
The diagnosis data is available via the SPI through this tristate-output.

8/49 DocID027540 Rev 3

L9959 Pins description

Table 2. L9959S PSSO24 pin-out (continued)

Pin Symbol Function

Current Proportional Feedback output:

9 CF The CF pin provides in conjunction with an external resistor an output current, which is
proportional to the H-Bridge current.
Bidirectional Ability/Enable Pin:
10 /ABE Open-Drain Output, which is pulled low in case of VDD over- and under-voltage. If the input
is pulled to low, all output stages are switched off.
11 GNDABE Sense Ground for VDD monitoring
15 AGND Device Ground. (Connected to Exposed PAD)
17 VDD VDD Supply: 5 V Supply
18 VS Power supply voltage for power stage outputs (external reverse protection required)
Disable input:
19 DIS
DIS switches OUT1 and OUT2 to tristate.
Direction input:
20 DIR
The DIR pin controls the switch direction of OUT1 and OUT2.
PWM input:
21 PWM
The PWM input switches OUT1 and OUT2.
Bridge output 1 and 2:
23 OUT2
The bridge outputs are built of a high-side p-channel and a low-side N-channel transistor.
Exposed Pad:
EP AGND
Connected to AGND.

Table 3. L9959T (Two H-Bridge drivers in one package) PSSO36 pin-out

Pin Symbol Function

Ground:
1 PGND1(1) Important: For the capability of driving the full current at the outputs, all ground pins must be
externally connected.
Bridge output 11, 12, 21, and 22:
2 OUT11 The bridge outputs are built of a high-side p-channel and a low-side N-channel transistor.
The bridge outputs of chip 1 are OUT11 and OUT12, of chip 2 OUT21 and OUT22.
Serial clock input:
3 SCK1 This input controls the internal shift register of the SPI.
SCK1 belongs to chip 1 and SCK2 to chip 2.
Slave Select input:
The serial data transfer between the device and the micro controller is enabled by pulling
4 SS1
the input SS to low level.
SS1 belongs to chip 1 and SS2 to chip 2.
Slave in (Serial data input):
5 SI1 The input receives serial data from the microcontroller.
SI1 belongs to chip 1 and SI2 to chip 2.
Slave Out (Serial data output):
6 SO1 The diagnosis data is available via the SPI through this tristate-output.
SO1 belongs to chip 1 and SO2 to chip 2.

DocID027540 Rev 3 9/49

48
Pins description L9959

Table 3. L9959T (Two H-Bridge drivers in one package) PSSO36 pin-out (continued)
Pin Symbol Function

Current Proportional Feedback output:

The CF pin provides in conjunction with an external resistor an output current, which is
7 CF1
proportional to the H-Bridge current. CF1 belongs to OUT11 and OUT12, CF2 to OUT21
and OUT22.
Bidirectional Ability/Enable Pin 1:
8 /ABE1 Open-Drain Output, which is pulled low in case of VDD over- and under-voltage. If the input
is pulled to low, all output stages are switched off. /ABE1 belongs to chip 1.
9 GNDABE1 Sense Ground for VDD monitoring
10, 28 AGND Device Ground. (Connected to Exposed PAD)
11, 29 NC To be connected to GND on PCB.
12 VDD2(2) VDD Supply: 5V Supply.
Power supply voltage for power stage outputs (external reverse protection required):
13, 14, VS2(3) Important: For the capability of driving the full current at the outputs all pins of VS must be
externally connected.
Disable input 2:
15 DIS2
DIS2 switches OUT21 and OUT22 to tristate.
Direction input 2:
16 DIR2
DIR2 pin controls the switch direction of OUT21 and OUT22.
PWM input 2:
17 PWM2
PWM1 input switches OUT21 and OUT22.
Bridge output 11, 12, 21, and 22:
18 OUT22 The bridge outputs are built of a high-side p-channel and a low-side N-channel transistor.
The bridge outputs of chip 1 are OUT11 and OUT12, of chip 2 OUT21 and OUT22.
Ground:
19 PGND2(1) Important: For the capability of driving the full current at the outputs, all ground pins must be
externally connected.
Bridge output 11, 12, 21, and 22:
20 OUT21 The bridge outputs are built of a high-side p-channel and a low-side N-channel transistor.
The bridge outputs of chip 1 are OUT11 and OUT12, of chip 2 OUT21 and OUT22.
Serial clock input:
21 SCK2 This input controls the internal shift register of the SPI.
SCK1 belongs to chip 1 and SCK2 to chip 2.
Slave Select input:
The serial data transfer between the device and the micro controller is enabled by pulling
22 SS2
the input SS to low level.
SS1 belongs to chip 1 and SS2 to chip 2.
Slave in (Serial data input):
23 SI2 The input receives serial data from the microcontroller.
SI1 belongs to chip 1 and SI2 to chip 2.
Slave Out (Serial data output):
24 SO2 The diagnosis data is available via the SPI through this tristate-output.
SO1 belongs to chip 1 and SO2 to chip 2.

10/49 DocID027540 Rev 3

L9959 Pins description

Table 3. L9959T (Two H-Bridge drivers in one package) PSSO36 pin-out (continued)
Pin Symbol Function

Current Proportional Feedback output:

The CF pin provides in conjunction with an external resistor an output current, which is
25 CF2
proportional to the H-Bridge current. CF1 belongs to OUT11 and OUT12, CF2 to OUT21
and OUT22.
Bidirectional Ability/Enable Pin 2:
26 /ABE2 Open-Drain Output, which is pulled low in case of VDD over- and under-voltage. If the input
is pulled to low, all output stages are switched off. /ABE2 belongs to chip 2.
27 GNDABE2 Sense Ground for VDD monitoring
30 VDD1(2) VDD Supply: 5V Supply.
Power supply voltage for power stage outputs (external reverse protection required):
31, 32 VS1(3) Important: For the capability of driving the full current at the outputs all pins of VS must be
externally connected.
Disable input 1:
33 DIS1
DIS1 switches OUT11 and OUT12 to tristate
Direction input 1:
34 DIR1
DIR1 pin controls the switch direction of OUT11 and OUT12.
PWM input 1:
35 PWM1
PWM1 input switches OUT11 and OUT12.
Bridge output 11, 12, 21, and 22:
36 OUT12 The bridge outputs are built of a high-side p-channel and a low-side N-channel transistor.
The bridge outputs of chip 1 are OUT11 and OUT12, of chip 2 OUT21 and OUT22.
EP AGND(4) Exposed PAD: connected to AGND
1. Pins 1 is referred to die 1, whereas 19 is referred to die 2.
2. Pins 12 is referred to die 2, whereas 30 is referred to die 1.
3. Pins 13 and 14 are referred to die 2, whereas pins 31 and 32 are referred to die1.
4. Pins 10 is referred to die 2, whereas 28 is referred to die 1.

DocID027540 Rev 3 11/49

48
Pins description L9959

Table 4. L9959U (Single version in PSSO36) pin out

Pin Symbol Function

Ground:
1 PGND Important: For the capability of driving the full current at the outputs, all ground pins must be
externally connected.
2 OUT1 The bridge outputs are built of a high-side p-channel and a low-side N-channel transistor.
Serial clock input:
3 SCK
This input controls the internal shift register of the SPI.
Current Proportional Feedback output:
7 CF The CF pin provides in conjunction with an external resistor an output current, which is
proportional to the H-Bridge current
Bidirectional Ability/Enable Pin:
8 /ABE Open-Drain Output, which is pulled low in case of VDD over- and under-voltage. If the input
is pulled to low, all output stages are switched off.
9 GNDABE Sense Ground for VDD monitoring
10,11,
12,13,
14,15,
16,17,
18,19,
NC To be connected to GND on PCB.
20,21,
22,23,
24,25,
26,27,
29
28 AGND Device Ground. (Connected to Exposed PAD)
30 VDD VDD Supply: 5 V Supply.
Power supply voltage for power stage outputs (external reverse protection required):
31, 32 VS1 Important: For the capability of driving the full current at the outputs all pins of VS must be
externally connected.
Disable input :
33 DIS
DIS switches OUT1 and OUT2 to tristate
Direction input:
34 DIR
DIR pin controls the switch direction of OUT1 and OUT2.
PWM input:
35 PWM
PWM input switches OUT1 and OUT2.
36 OUT2 The bridge outputs are built of a high-side p-channel and a low-side N-channel transistor.

12/49 DocID027540 Rev 3

L9959 Electrical specifications

3 Electrical specifications

3.1 Absolute maximum ratings

Warning: Stressing the device above the rating listed in the "Absolute
maximum ratings" table may cause permanent damage to the
device. These are stress ratings only and operation of the
device at these or any other conditions above those
indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to
the STMicroelectronics SURE program and other relevant
quality document.

Table 5. Absolute maximum ratings

Symbol Parameter / Test condition Value [DC Voltage] Unit

DC supply voltage
VVS The device is able to sustain load dump as -1.0 to +40 V
specified in the ISO16750 documentation
VVDD Stabilized supply voltage, logic supply -0.3 to 18 V
CF (1) Current feedback output -0.3 to 18 V
VSI, VSCK, VSS, VSO,
Logic input / output voltage range -0.3 to 18 V
VDIR, VPWM, VDIS
Output voltage (n = 1,2 or 11,12,21,22);
-1.0 to 40 V
VOUTn VOUTn < VS + 1 V
Dynamic pulse / t < 500ms; VOUTn < VS + 2 V -2.0 to 40 V
Operating junction temperature -40 to 150 °C
Tj
Dynamic junction temperature (1000hrs) 150 to 175 °C
Tstg Storage temperature -55 to 150 °C
1. It is withstood at VS = 18 V

3.2 ESD protection

Table 6. ESD protection
Parameter Value Unit

All pins versus ground group (AGND, PGND1, PGND2, GND_ABE1, GND_ABE2) ±2(1) kV
VS pin, Power Output Pins: OUT1, OUT2 or OUT11, OUT12, OUT21, OUT22
±4(2) kV
versus ground group (AGND, PGND1, PGND2, GND_ABE1, GND_ABE2)
1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.
2. HBM with all unzipped pins grounded.

DocID027540 Rev 3 13/49

48
Electrical specifications L9959

3.3 Thermal data

Table 7. Thermal data
Symbol Parameter Value Unit

Thermal resistance junction-to-case (max)

Rthj-case 2.0 °C/W
for L9959S, L9959T

3.4 Electrical characteristics

The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V  VS  18 V, 4.5 V  VDD  5.5 V; all outputs open; Tj = -40 °C to
150 °C, unless otherwise specified.

Table 8. Supply
Symbol Parameter Test condition Min. Typ. Max. Unit

VS Operating voltage range - 4.5 - 28 V

VDD = 5 V; VS = 5 V and
VS = 18 V; - - 5 mA
Bridge disabled
VDD = 5 V; VS = 5 V and
VS = 18 V; fOUT = 2 kHz; - - 6 mA
VS current consumption in IOUT = 0 A
IVS
active mode
VDD = 5 V; VS = 5 V and
VS = 18 V; fOUT = 10 kHz; - - 14 mA
IOUT = 0 A
VDD = 5 V; VS = 28 V;
- - 14 mA
fOUT = 10 kHz; IOUT = 0 A
VS current consumption in
IVS(stby) VDD = 0 V 0 - 2.5 mA
passive mode
VVS_slew(1) Slew rate on VS - - - 100 V/μs
(2)
VVS_slew Slew rate on VS - - - 20 V/μs
VDD Operating voltage range - 4.5 - 5.5 V
IVDD VDD supply current VS = 18 V; VDD = 5 V - - 10 mA
1. No change of parameters for VDD-monitoring and in SPI logic
2. No change of parameters

14/49 DocID027540 Rev 3

L9959 Electrical specifications

Table 9. Power-on reset

Symbol Parameter Test condition Min. Typ. Max. Unit

VDDRES Reset active threshold - 2.8 - 3.4 V

VDDPOR Power-on reset threshold - 3.3 - 4 V
VDDPORHYS Power-on reset hysteresis - - 600 - mV
tPOR Power-on reset extension time - - - 1 ms

Table 10. VDD monitoring

Symbol Parameter Test condition Min. Typ. Max. Unit

VDD VDD monitoring voltage range - VDDPOR - 18 V

VDD_THL Under voltage threshold VS = 0 V 4.2 - 4.5 V
VDD_THH Over voltage threshold VS = 0 V 5.25 - 5.5 V
tFIL_OFF Switch-off filtering time 60 - 135 μs
Guaranteed by scan.
tFIL_ON Switch-on filtering time 60 - 135 μs
VTEST_THL Under voltage test threshold - 5.25 - 5.5 V
VTEST_THH Over voltage test threshold - 4.2 - 4.4 V
VDD_MR Full VDD supply range - -0.3 - 18 V
VDD_SLEW VDD slew - - 500 mV/μs
Threshold (VDD_THH, VDD_THL)
VDD_THX - -0.1 - 0.1 V
shift during vs. inverse current
VABE_INL /ABE input low-level - -0.3 - 1.65 V
VABE_INH /ABE input high-level - 3.15 - 18 V
VABE_INHY
/ABE input hysteresis - 0.2 - 1.0 V
S

0 V < VABE < 1.5 V 0 - 60 μA

IABE_IN /ABE input pull-down current VABE = 2.1 V, 5 V, 18 V;

VS = 18 V; VDD = 5 V, 20 40 60 μA
18 V
2.5 V < VDD < VDD_THL;
VABE_OUTL /ABE output low voltage 0 - 1.0 V
IABE_OUTL < 2.5 mA
VDD_THH < VDD < 18V;
VABE_OUTL /ABE output low voltage 0 - 1.2 V
IABE_OUTL < 7.5 mA
/ABE output passive low
VABE_OUTL - 0 - 1.2 V
voltage
IABE Change during vs. inverse
IABE - -100 - 100 μA
current

DocID027540 Rev 3 15/49

48
Electrical specifications L9959

Table 11. Undervoltage shutdown

Symbol Parameter Test condition Min. Typ. Max. Unit

VUV_OFF VS UV threshold VS decreasing 3.1 3.8 4.5 V

VUV_ON VS UV threshold VS increasing 3.3 4.0 4.7 V
VUV_HYS VS UV hysteresis VUV_ON - VUV_OFF 0.1 - 1 V
tFUV VS UV detection time - - - 1.5 μs

3.5 Outputs OUT1 and OUT2

Table 12. On-resistance (4.5 V < VS < 28 V)
Symbol Parameter Test condition Min. Typ. Max. Unit

rONVS VDD = 5 V; VS = 10 V,
On-resistance to supply - - 315 m
OUT1,2 IOUT1,2 = 3 A
rONGND VDD = 5 V; VS = 10 V,
On-resistance to PGND - - 225 m
OUT1,2 IOUT1,2 = 3 A
VDD = 5 V; VS = 13 V;
-200 - - μA
Switched-off output current of VOUT = 0 V
ILEAK
OUT1,2 VDD = 5 V; VS = 13 V;
- - 200 μA
VOUT = VS

Table 13. Power output switching times (8 V < VS < 18 V)

Symbol Parameter Test condition Min. Typ. Max. Unit

td ON Output delay time driver on - - - 6 μs

td OFF Output delay time driver off - - - 20 μs
(1)
td dis Disable delay time - - 12.5 μs
Guaranteed through
td pwon Power-on delay time - - 1 ms
scan.
td en Enable delay time - - 50 μs
dIOUT/dt Current slew rate - - 1.6 A/μs
Output rise/fall slew-rate high-side
dVOUTHS/dt
(2) slow selected with bit SR = 0 0.975 - 2.7 V/μs
fast selected with bit SR = 1 2.8 8
VDD = 5 V; VS = 14 V
Output rise slew-rate low-side RLOAD1,2 = 2.6 Ω (8 VS),
dVrOUTLS/dt
(2) valid only after the toggling of DIR 6 Ω (18 V ) 0.975 - 2.7 V/μs
S
input
dVfOUTLS/dt
(2) Output fall slew-rate low-side 2.5 4 8 V/μs

fpwmmax PWM input frequency - - - 11 kHz

1. Driven by /ABE or DIS input.
2. The slew-rates (dVOUT/dt1) are defined by dV (voltage difference 20% - 80%) divided by the rise-/fall times (tr/tf see
Figure 6: Output rise and fall times).

16/49 DocID027540 Rev 3

L9959 Electrical specifications

Figure 5. Output delay times (e.g. low-side output)

6

07-
 


T

6OUT(


/54X


6OUT,
T
TD /. TD /&&
'!0'03

Figure 6. Output rise and fall times

6OUT(
 

/54X

 

6OUT,
TF TR T
'!0'03

Figure 7. Output disable and enable time (/ABE Input)

6

 
!"%


63 T

63


6/54




T
TDDIS TDEN '!0'03

DocID027540 Rev 3 17/49

48
Electrical specifications L9959

Figure 8. Output disable and enable time (DIS Input)

6

$)3
 


63 T

63


6/54




T
TDDIS TDEN
'!0'03

Table 14. Current feedback (CF)

Symbol Parameter Test condition Min. Typ. Max. Unit

VS > 6.5 V, OUTx = 0 A,

TJ = -40 °C; Current 0.01 0.05 0.20 V
level 2,3,4
VS > 6.5 V, OUTx =
250mA, TJ = 130 °C; 0.04 0.275 0.5 V
Current level 2,3,4
VCF (1) CF voltage range
VS > 6.5 V, OUTx = 0.4 *
Iclx, TJ = 130 °C; Current 1.71 1.80 1.89 V
level 2,3,4
VS > 6.5 V, OUTx = Iclx
TJ = -40°C to 150°C; 3.82 4.5 5.18 V
Current level 2,3,4
RCF(2) CF resistor range - - 5.1 - kΩ
IOFFSET CF offset current - - 10 - μA
1. Measured at a 5.1k resistor between CF and GND (RCF).
Levels see Table 34 Current Level (CONFIG_REG).
2. Defined by design, not tested.
Note: This signal has an individual error ±5 % in each of the three currents levels, at trimming temperature of 130 °C. Additional
an individual error ±10 % in each of the three current levels over temperature and aging. So the maximum error is of
±15 % in each of the three current levels. The offset and the gain errors may be different in each current level.
The adjustment is done at 130 °C and compensates the error corresponding to 0.4 * Iclx

18/49 DocID027540 Rev 3

L9959 Electrical specifications

Table 15. Current limiting

Symbol Parameter Test condition Min. Typ. Max. Unit

|ICL2|(1) Current limit2 4.25 5 5.75 A

(1)
|ICL3| Current limit3 RCF = 5.1 kΩ 5.6 6.6 7.6 A
(1)
|ICL4| Current limit4 7.3 8.6 9.9 A
-5% -10%
|IHYS2-4|(1) Current limit hysteresis1 - - A
ICL2-4 ICL2-4
tb Blanking time Guaranteed through 8 11 15 μs
ttrans Time between two transient scan. 90 - 130 μs
1. Programmable current levels see Table 34 Current Level (CONFIG_REG). Measured using a 5.1 kΩ resistor between CF
and GND (RCF).

Table 16. Over-current detection (8 V < VS < 18 V)

Symbol Parameter Test condition Min. Typ. Max. Unit

Low side over current

|IOC2_LSI(1) VDD = 5 V 4.9 - 8.2 A
threshold2
Low side over current
|IOC3_LS|(1) VDD = 5 V 6.7 - 11.1 A
threshold3
Low side over current
|IOC4_LS|(1) VDD = 5 V 8.4 - 14 A
threshold4
High side over current
|IOC2_HSI(1) VDD = 5 V 5.5 - 9.2 A
threshold2
High side over current
|IOC3_HS|(1) VDD = 5 V 6.9 - 11.5 A
threshold3
High side over current
|IOC4_HS|(1) VDD = 5 V 8.6 - 14.4 A
threshold4
ITRACK-2(2) |IOC2| - |ICL2| VDD = 5 V 0.4 - 5.5 A
ITRACK-3(2) |IOC3| - |ICL3| VDD = 5 V 0.4 - 5.5 A
ITRACK-4(2) |IOC4| - |ICL4| VDD = 5 V 0.4 - 5.5 A
tDF Delay time for fault detection guaranteed by design 1 2 4.5 μs
tDF_off Switch-off delay time - 6 μs
tDF_del Delayed switch-off time - 20 200 μs
tSC Short-circuit detection guaranteed through scan 292 350 413 μs
1. Programmable current levels see Table 34 Current Level (CONFIG_REG).
2. Tracking values are referred for both LS and HS.

DocID027540 Rev 3 19/49

48
Electrical specifications L9959

Table 17. Open-load detection

Symbol Parameter Test condition Min. Typ. Max. Unit

ROL Open-load detection threshold - 5 - 50 kΩ

tDIAGOL Open-load diagnosis enable delay 100 - 150 ms
Guaranteed through
tDIAGOL1 Open-load diagnosis filter time1 2.4 - 3.6 ms
scan.
tDIAGOL2 Open-load diagnosis filter time2 200 - 300 μs
Vout1_OFF Out1 voltage regulator - 1.67 - 1.97 V

Note: If the value of the connected load is below 5 kΩ no Open Load is detected; whereas if the
value of the connected load is more than 50 kΩ, Open Load is detected.
If the load is in the range between (5 to 50) kΩ, the Open Load diagnosis could be not
reliable.

Table 18. Retest delay

Symbol Parameter Test condition Min. Typ. Max. Unit

tdelay retest Retest delay for failures: SCB, SCG, SCL Guaranteed through scan. 290 350 410 μs

3.6 Temperature dependent current reduction

Table 19. Temperature dependent current reduction
Symbol Parameter Test condition Min. Typ. Max. Unit

|IL_TSD| Current limit at TSD - 1.4 2.5 3.6 A

Start of temperature dependent
TILR - 150 165 - °C
current reduction
TSD Thermal shut-down - 175 - - °C
Range of temperature dependent
TSD-TILR - 20 25 30 °C
current reduction
TfTSD Thermo-shut-down detection filter time Guaranteed through scan. 6 - 18 μs

Note: see also Figure 17: Temperature dependent current reduction.

3.7 Free-wheeling diodes

Table 20. Free-wheel diodes
Symbol Parameter Test condition Min. Typ. Max. Unit

UD Free-wheeling diode forward voltage IOUT = 3 A - - 2 V

(1)
Tit Free-wheeling diode reverse recovery time - - - 100 ns
1. Not subject to production test; specified by design.

20/49 DocID027540 Rev 3

L9959 Electrical specifications

3.8 SPI / logic electrical characteristics

The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V ≤ VS ≤ 18 V, 4.5 V ≤ VCC ≤ 5.5 V; all outputs open; Tj = -40 °C to
150 °C, unless otherwise specified.

Table 21. Inputs: SI, SS, SCK, DIR, DIS and PWM; Output: SO
Symbol Parameter Test condition Min Typ Max Unit

Inputs: SI, SS, SCK DIR, PWM

VIL Input voltage low-level VDD = 5 V -0.3 - 0.75 V

VIH Input voltage high-level VDD = 5 V 1.75 - VDD+0.3 V
VIHYS Input hysteresis VDD = 5 V 0.2 - 1.0 V
RPUin Input pull-up resistor VDD = 5 V 50 - 250 kΩ
IINx PWM, DIR input current VINx > 3.0V -5 - 5 μA
CSIin(1) SI input capacitance - - - 10 pF
CSCKin(1) SCK input capacitance - - - 10 pF
CSSin(1) SS Input Capacitance - - - 15 pF
CDIR,PWMin
(1) DIR, PWM input capacitance - - - 20 pF

Input: DIS

RDISPU Pull-up resistor 0 V < VDIS < 2.1 V 10 - 45 kΩ

IDISx DIS input current VDIS > 3 V -5 - 5 μA
(1)
CDIS in DIS input capacitance - - - 20 pF
tDIS DIS pulse width - 0.5 1 1.5 μs

Input pin disturbance (SI, SS, SCK DIR, PWM,DIS)

Change of VIH and VIL during

ΔVx_HL -0.1 - 0.1 V
inverse current on VS
Not subjected to test in
Change of input current of SPI production.
ΔISx input pins during inverse -100 - 100 μA
current on VS

Output: SO

VSOL Output voltage low level IOL = 2 mA, 0 - 0.4 V

VSOH Output voltage high level IOH = -2 mA VDD-0.5 - VDD V
SRSO(1) Slew rate CLOAD = 200 pF 0.3 - 0.6 V/ns
ISOLK Tristate leakage current VSS = VDD -10 - 10 μA
CSO out(1) SO output capacitance - - - 10 pF

Output pin disturbance (SO)

Change of ISOLK during

ISOLK - -100 - 100 μA
inverse Current on VS
1. Not measured in production test. Parameter guaranteed by design.

DocID027540 Rev 3 21/49

48
Electrical specifications L9959

Table 22. Dynamic characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

tcyc Cycle time - 490 - - ns

tlead Enable lead time - 300 - - ns
tlag Enable lag time - 150 - - ns
SCK = 2 V; SO = 0.2 V;
40 - - ns
CL = 40 pF
SCK = 2 V; SO = 0.2 V;
tv Data valid 150 - - ns
CL = 200 pF
SCK = 2 V; SO = 0.2 V;
230 - - ns
CL = 350 pF
tsu Data setup time - 40 - - ns
th Data hold time - 40 - - ns
tdis Disable time - 0 - 100 ns
tdt Transfer delay - 300 - - ns
tdld Disable lead time - 250 - - ns
tdlg Disable lag time - 250 - - ns
tacc Access time - 8.35 - - μs

Figure 9. SPI timing information

TAC C

33 T DT
TDLD TLEAD TC Y C T LAG T DLG

3#+
TDIS
TV
3/ "ITN  "ITN  x  "IT 
TSU TH

3) -3" ). "ITN  "ITN  "ITN  x  ,3"

'!0'03

22/49 DocID027540 Rev 3

L9959 Application information

4 Application information

4.1 Power stage switching behavior

The L9959 output stages can either be controlled by the pins PWM and DIR or by their
corresponding SPI registers (SPWM and SDIR: see Table 33 in Configuration Register
(CONFIG_REG)). The SPI bit MUX in the configuration register (CONFIG_REG) is used to
define the driving control strategy of the H-bridge. If the power stages are disabled by /ABE
or DIS, this bit is reset and the pins PWM and DIR control the outputs.
The active free-wheeling, in which the body diode is actively shorted by its associated
Power-MOS, can be disabled by the bit FW in the configuration register (CONFIG_REG).
By default, active free-wheeling is enabled.
The device minimizes electro-magnetic emission by switching the high-side and low-side
drivers in a special sequence. Two cases are distinguished: The PWM-mode, during which
the current direction does not change and the direction switches using the DIR, which
changes the current direction (see Figure 10, Figure 12 and Figure 13).

4.1.1 PWM mode (same current direction)

The PWM input pin switches the high-/low-side output of the half-bridge, which is selected
by the DIR pin.
DIR = '0': OUT1 is switched, DIR = '1': OUT2 is switched.
PWM = '0': Switched low-side is on, PWM = '1': Switched high-side is on.

Figure 10. PWM mode current flow

/. SLOW (3 (3

/&& SLOW

$)2   07-  
/54 /54

)NDUCTIVE ,OAD

$)2   07-  
/&& FAST ,3 ,3
/. FAST

'!0'03

DocID027540 Rev 3 23/49

48
Application information L9959

Figure 11. PWM mode output voltage

$)2   07-   $)2   07-   $)2   07-  

6OUT(

/54

6OUT,
T
6$
'!0'03

During PWM mode the high-side (e.g. Figure 10 HS1) output is switched off with a slow slew
rate until it is off and the low-side body-diode has taken over the entire current (passive
freewheeling). Then the associated low-side transistor (e.g. Figure 10 LS1) is turned on with
a fast slope to reduce the voltage across the device and to minimize the power.
The output is pulled to high voltage, by first turning off the low-side driver with a fast slew
rate and, after it is off, the high-side driver is switched on by a slow one (e.g. Figure 10 LS1,
HS1).
This assures, that the voltage and current change over the body diode is done smoothly,
reducing the electromagnetic emission.

4.1.2 DIR-change mode

The first part of the sequence is identical to the PWM-mode (s.a.). After this has been
finished and the associated low-side driver is on (e.g. Figure 12 LS1), in phase 1 the other
low-side driver is turned on (e.g Figure 12 LS2) to enter passive freewheeling phase. Then
in phase 2 the low-side output of OUT2 is switched-off slowly and the current through the
load is taken over by the body-diode of the high-side (e.g. Figure 13 HS2).
Depending on the inductance of the load, the current vanishes more or less quickly. After
the low-side driver is turned off, the high-side is switched on with a slow slew-rate.
This assures, that direction switch occurs while the current over the load has vanished,
which reduces the electromagnetic emission.

Figure 12. DIR-change (current is changing its direction)

2))VORZ +6 +6 2))

6WDUW
',5 3:0 
287 287

,QGXFWLYH/RDG

',5 3:0 
3KDVH
21IDVW /6 /6 21

*$3*36

24/49 DocID027540 Rev 3

L9959 Application information

Figure 13. DIR-change current flow phase 2

2)) +6 +6 21VORZ

',5 3:0 

287 287

,QGXFWLYH/RDG

3KDVH 
21 /6 /6 2))VORZ

*$3*36

Figure 14. DIR-change output voltage

',5 3:0  ',5 3:0 

9RXW+

287

9RXW/
W
9'

9'

9RXW+

287

9RXW/
3KDVH 3KDVH W *$3*36

4.2 Protection and monitoring

A set of failure as Short-circuit to Ground (SCG), Short-circuit to battery (SCB) and Short-
circuit to load (SCL) errors (SBC, SCG, SCL) are confirmed after their occurrence by
accessing the error condition after time tdelay_retest a second time. Only after the error is
confirmed, it is entered into the diagnosis register 1 (DIA_REG1), and the device is disabled
and no further diagnosis is run.
The device can be enabled again by the following actions: Power-on reset, disabling and
enabling the device using the pins /ABE or DIS (e.g. disabling - enabling sequence). The
diagnosis registers can be cleared by sending a reset command by SPI (STATCON_REG)
to either diagnosis register 1 (DIA_REG1) or 2 (DIA_REG2). The bit1 (Reset) of the
CONFIG_REG if forced to zero resets both the device registers configuration and diagnosis
registers to default but is not able to restart the device. In order to restart IC it is necessary

DocID027540 Rev 3 25/49

48
Application information L9959

to force a transition LOW/HIGH/LOW on DIS pin or a transition HIGH/LOW/HIGH on /ABE

pin.
The errors in the diagnosis register 1 (DIA_REG1) are transferred to the diagnosis register 2
by setting the bit DIACLR1 in the status and configuration register (STATCON_REG) or by
using the enabling -disabling sequence on /ABE or DIS. This will also clear the diagnosis
register 1.

4.2.1 Current feedback

A feedback current signal is provided at pin CF (Current Feedback). This current is
proportional to the current in the H-Bridge, but does not change its direction. It is measured
in the low-side transistor, which is not switched by PWM. This is determined by the input
DIR or the SDIR register respectively. Therefore, the direction of the current can be seen
from this direction signal.
One current sense monitoring circuit is present and it is connected to the output of the active
LS driver (DIR change mode).
After the DIR transition, the LSx reference output is switched only in the phase in which both
LS drivers are active for recirculation.
In the time-frame between HS turn-off and the start of active freewheeling, (including dead
time and passive freewheeling), the current sense monitors the current flowing in the
previous active LS driver.
This time-frame is not fixed but adaptative to real operative conditions (battery and selected
slew rate mode).
In Table 14: Current feedback (CF) the CF behavior over an external resistor of 5.1k Ohm is
specified. The current out of CF consists of a static offset current and a current proportional
to the current in the select low-side transistor. The voltage at pin CF scales with the resistor
at this pin.

Figure 15. Current feedback and current limiting

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Figure 15 Current Feedback and Current Limiting shows the current feedback in case the
OUT1 is controlled by PWM (DIR = 0). In this case, the current is measured through low-
side 2. If the direction is inverted, the current is measured through low-side 1.

26/49 DocID027540 Rev 3

L9959 Application information

4.2.2 Current limitation

The H-Bridge output current can be limited to three different values (see Table 15: Current
limiting). If the current reaches the current limiting threshold ICL, the output driver is
switched off after the blanking time tb, and switched on again after the current dropped
below the lower current limit hysteresis threshold (ICL – IHYS). The current limiting
thresholds can be adjusted using the resistor at pin CF. The values in Table 15 refer to a
5.1k Ohm external resistor. The current limiting threshold can be calculated by (4.5V/RCF -
IOFFSET) * (ICLx*5.1k/4.45V) from Table 15 and IOFFSET =10μA (typical). RCF is the resistor
used at pin CF.
The overcurrent threshold is not changed by RCF (see Table 16). The current limitation is
active as long as the output driver is switched on. The information that the device is in
current limitation is stored in the diagnosis register 2 (DIA_REG2).

Figure 16. Current limitation

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4.2.3 Temperature dependent current reduction

If the device reaches the temperature TILR, the current will be reduced (see Figure 17:
Temperature dependent current reduction). If the temperature reaches the temperature
shutdown threshold TSD, the outputs are switched off. The current limitation information is
written into the diagnosis register 2 (DIA_REG2).

Figure 17. Temperature dependent current reduction

)/54

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DocID027540 Rev 3 27/49

48
Application information L9959

4.2.4 Short to battery (SCB) and short to Ground (SCG)

While the power stages are on, the current through them is monitored. If the output current
reaches the current limit IL, the output is switched off after the blanking time tb. In case the
current reaches the limit IOC during this time, a short to battery (SCB) on low-sides or a short
to ground (SCG) on high-sides is diagnosed, and the affected output driver is switched off
immediately, the not affected one after the time tDF_del.
In order to confirm this error, the outputs are turned on again. If the error is detected for the
second time, it is confirmed but it is still not possible to determine to which of the following
types belongs to:
 SCB and SCL
 SCG and SCL
To discriminate the fault type, it is necessary to turn outputs on for the third time, and in case
the fault is detected, the diagnosis register (DIA_REG1) is updated consequently and the
device is disabled. Otherwise, the SCG and SCB faults are confirmed only.

Figure 18. Current limiting and short circuit

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The three different over-current limits are related to the programmable current limitation,
which can be programmed into the SPI register (Table 33: Configuration register
(CONFIG_REG)). The over-current limits are independent of the resistor at pin CF.
Note: SCG: Fault Detection works correctly if the following condition is respected: Duty (switch on
time) > Tdon + Slew rate + tDF.

4.2.5 Short circuit over load (SCL)

Short circuit over load (SCL) is diagnosed by a retest sequence after a short to battery
(SCB) or a short to ground (SCG) has been detected and confirmed by a retry on the
switched-on high-side and low-side driver. Then after the time tretest, the opposite driver is
switched off (i.e. the high-side in case of a short to battery on the low-side and vice versa). If
the failure then disappears, a short over load (SCL) is detected.
The error is only entered into the diagnosis register and the device is disabled, if it is
confirmed.

28/49 DocID027540 Rev 3

L9959 Application information

4.2.6 Open load (OL)

Open load can either be detected in active mode or while the output drivers are in a tri-state
condition, disabled by DIS or /ABE. Open load in active mode is enabled by setting the
OLDA in the configuration register (CONFIG_REG).

Open load in active mode

With OLDA = '1', the open load condition can only be diagnosed if an inductive load is used.
In normal operation, the output free wheels via the built-in diodes below ground, if the high-
side output driver is switched-off. If the output does not go below ground, an open load is
detected. It is possible to enable the filter OLDAFILTER by setting the dedicated bit 4 in
SPECIAL_REG (0 or 40ms). With OLDAFILTER = '1', the open-load will be recheck at the
next PWM cycle and if detected again, the failure will be confirmed in DIAG_REG1 (and
latched).
In case OLDAFILTER is set at '0' (40ms) the recheck will be executed after the filter time
expiration and next PWM pulse. If detected again, the failure will be confirmed (and
latched).
Note: For Open-load in active mode L9959 works properly in case the duration of the transient
conditions is less than 40msec (Transient condition: function of starting current, ending
current, load electrical parameters, DC MOTOR mechanical characteristics...).

Open load in inactive mode

In inactive mode the open load is independent from the OLDAFILTER status (don't care
condition) and it is detected by applying a pull-down current (IPD) to both outputs.
A pull-up current is generated at one output to compensate these two output currents.
If the pull-up current is in the range of one pull-down current, an open load is diagnosed.
If the load is connected, the pull up current is in the range of the sum of both pull-down
currents.
An open load is detected, if the load resistance is above the open load resistance threshold;
no open load is detected, if it is below this threshold (ROL).
After the outputs are disabled, it takes the time tDIAGOL until the open load diagnostic can be
enabled. The open load settling time to reach the correct pull up current is tdiagOL1, the
open load filter time is tdiagOL2.

4.3 VS-undervoltage
VS is monitored for under-voltage. If VS goes below the VS-undervoltage threshold, the
outputs are switched to tristate after the time tFUV.

4.4 Inverse current at VS

An inverse current of maximum 5 A, which decreases during a period of max 250 ms out of
the device at VS does not lead to any destruction. After the exposure to such an inverse
current the device returns to the specified functionality.

DocID027540 Rev 3 29/49

48
Application information L9959

4.5 /ABE pin

/ABE (Ability/Enable) is a bidirectional pin, with an open-drain output. In normal operating
condition, this pin is pulled up by an external resistor. If /ABE is set to low, the outputs enter
tristate mode.
/ABE can be used to switch off the outputs quickly by an external signal. It is possible to
connect the /ABE pins of several devices together, so all of them can be disabled in case
one detects an error, which is flagged by the /ABE pin.

4.6 VDD-monitor
VDD is monitored for under- and over-voltage referenced to GNDABE.
If VDD goes below VDD_THL or above VDD_THH, /ABE is pulled to low and the outputs enter
tristate mode after the time tFIL_OFF. The VDD-monitoring state is stored into the status and
control register (STACON_REG).
If VDD increases above VDD_THL, /ABE is pulled to high after the filter time tFIL_ON. The SPI
remains functional as long as VDD is above the power-on reset threshold.
The behavior of the pin /ABE and the output stages after VDD goes below VDD_THH from
VDD-over-voltage is determined by bit CONFIG 0 in the status and configuration register
(STATCON):
CONFIG0 = 1: /ABE is latched and the outputs remain in tristate
CONFIG0 = 0: /ABE goes to inactive and the output stages are enabled after the filtering
time tFIL_ON.

4.7 VDD-monitor test

VDD-Monitor blocks can be tested in the application via SPI. During this test, the output
stages are still switched off in case of over- and under-voltage.

Upper threshold
The over-voltage threshold can be reduced using the configuration registers 1 and 2
(CONFIG1 and CONFIG2) in the status and control register (STACON_REG) to VTEST_THH
(see Table 35: Status and configuration register (STATCON_REG)). Since VTEST_THH is
below the normal VDD voltage, the status bit STATUS0 shows a VDD over-voltage.

Lower threshold
The under-voltage threshold can be increased to VTEST_THL using CONFIG1 and CONFIG2
in the STATCON register. Since the VDD voltage is below VTEST_THL, the resulting VDD-
undervoltage resets STATUS0.
After leaving the VDD-monitor test mode, the bits in the STACON register return to their
normal state.

30/49 DocID027540 Rev 3

L9959 Application information

4.8 Power-on reset

At power-on, while VDD increases, the internal registers are cleared and the outputs are set
to tristate at the reset-active voltage VDDRES. Above the power-on reset threshold VDDPOR
the device starts to operate after the time tPOR. If VDD drops below VDDPOR, the device
enters its reset state, i.e. all internal registers are cleared and the outputs are set to tristate.

Table 23. Device states with respect to supply voltage

VS [V] VDD [V] Functional state
28 – 40 0 – 18 No damage to the device, no functional behavior guaranteed
4.5 – 6.5 4.5 – 5.5 Device functional, Current Feedback accuracy reduced
6.5 – 28 4.5 – 5.5 Device functional
Device functional, but power-outputs tristate by VDD-monitor, /ABE
4.5 – 28 4.0 – 4.5 5.5 - 18
pulled to low, SPI functional
0 – 4.5 4.5 – 28 VDDPOR – 4.5 Device in reset mode, SPI functional, power-outputs tristate, /ABE pulled to low
0 – 4.5 4.5 – 28 2.5 - VDDPOR Device in reset mode, SPI reset, power-outputs tristate, /ABE tristate
0 – 4.5 4.5 – 5.5 Device functional, outputs are tristate by VS-undervoltage
Device functional, outputs are tristate by VS-undervoltage and VDD-
0 – 4.5 4.0 – 4.5 5.5 - 18
monitor, /ABE pulled to low
Note: All voltages are nominal. Please refer to Section 3: Electrical specifications for their
specified values.

DocID027540 Rev 3 31/49

48
SPI functional description L9959

5 SPI functional description

5.1 General description

The SPI communication is based on a Serial Peripheral Interface structure using SS (SPI
Select), SI (Serial Data In), SO (Serial Data Out) and SCK (Serial Clock) signal lines. The
first data at pin SI is latched into the device with the first falling edge of the clock SCK after
the clock has changed from low to high, which is the second edge after SPI-Select has been
pulled to low.

5.1.1 SPI select (SS)

The SS input pin is used to select the serial interface of this device. When SS is high, the
output pin (SO) is in high impedance state. A low signal starts the serial communication. A
communication frame is the time between the falling edge of SS and its rising edge.

5.1.2 Serial data In (SI)

The SI input pin is used to transfer data serially into the device. The data applied to the SI is
sampled at the falling edge of the SCK signal.

5.1.3 Serial clock (SCK)

The Data Input (SI) is latched at the falling edge of Serial Clock SCK. Data on Serial Data
Out (SO) is shifted out at the rising edge of the serial clock (SCK). The serial clock SCK
must be active only during a frame (SS low).

5.1.4 Serial out (SO)

The content of the selected status or control register is transferred out of the device using
the SO pin on the rising edge of SCK. Each subsequent rising edge of the SCK will shift the
next bit out.

5.1.5 SPI communication flow

The SPI communication is started by sending an SPI instruction to the device beginning with
the MSB. The first two bits of this instruction are used as a device identifier (see Table 24:
SPI instruction byte). Whether the transfer is a read or a write access is determined by the
SPI command (see Table 26: Command overview). The SPI data is transmitted from the
device at the same time as the data is received, although on different SCK edges. While the
8-bit instruction is sent, the device responds with the check byte. Since the first two bits of
the instruction are used as a device identifier, the first two bits of the check byte are tristate.
This avoids bus conflicts on the SO line. During a write access, the 8-bit data byte is
received after the instruction byte. The device responds with 00H. In a read cycle the device
sends the 8-bit data, while the receive data bits are ignored (see Figure 19: Write access
and Figure 20: Read access). If an invalid instruction is detected, the register of the device
are not modified and the data byte FFH is transmitted instead of the data or 00H respectively.
The bit TRANS_F in the check byte is set in case of an invalid instruction and transmitted
during the next SPI-access. An instruction is invalid, if an unused instruction code is
detected, the previous transmission has not been completed or the number of clocks is not
equal to 16.

32/49 DocID027540 Rev 3

L9959 SPI functional description

Figure 19. Write access

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5.2 SPI-instruction
Table 24. SPI instruction byte
Bit 7 6 5 4 3 2 1 0

Name CPAD1 CPAD0 INST<5> INST<4> INST<3> INST<2> INST<1> INST<0>

Bit Name Content

7 CPAD1 Chip Address: 0

6 CPAD0 Chip Address: 0
5 INST<5> Read/Write: Read: 0 Write: 1
4:0 INST<4:0> SPI Instruction

DocID027540 Rev 3 33/49

48
SPI functional description L9959

Table 25. Check byte

Bit 7 6 5 4 3 2 1 0

Name Tristate Tristate 1 0 1 0 1 TRANS_F

Bit Name Content

7:6 Tristate Tristate

6:1 Fix Content: 10101
0 TRANS_F Transfer-Failure Invalid instruction TRANS_F = 1

5.3 Device register map

Table 26. Command overview
Command INST<5:0> Content

RD_ID 00_0100 Read Device ID

RD_REV 00_0110 Read Device Revision
RD_DIA1 01_0000 Read Diagnostic Information Register 1
RD_DIA2 01_1000 Read Diagnostic Information Register 2
RD_CONFIG 00_1000 Read Configuration
RD_STATCON 00_1100 Read VDD Monitoring Status
RD_SPECIAL 00_1110 Read information from SPECIAL
WR_DIA1 11_0000 Write to Diagnostic Information Register 1
WR_DIA2 11_1000 Write to Diagnostic Information Register 2
WR_CONFIG 10_1000 Write Configuration
WR_STATCON 10_1100 Write VDD Monitoring Status
WR_SPECIAL 10_1110 Write information to SPECIAL
All Other - Invalid Command: TRANS_F: 1

34/49 DocID027540 Rev 3

L9959 SPI functional description

5.4 SPI - control and status registers

Table 27. Device identifier (ID)
Bit 7 6 5 4 3 2 1 0

Name ID<7> ID<6> ID<5> ID<4> ID<3> ID<2> ID<1> ID<0>

Bit Name Content

7:0 ID<7:0> Device ID: DFH

Table 28. Revision register (REV)

Bit 7 6 5 4 3 2 1 0

Name SWR<3> SWR<2> SWR<1> SWR<0> MSR<3> MSR<2> MSR<1> MSR<0>

Bit Name Content

7:4 SWR<3:0> Software Revision: 0H

3:0 MSR<3:0> Mask Set Revision: 06H(1)
1. Here below the Mask set revision:
00H - AA
01H - BA
02H - CA
03H - CB
04H - DA
05H - DB
06H - DC

Table 29. DIA_REG1

Bit 7 6 5 4 3 2 1 0
Name /ABE / DIS OT Res Res DIA21 DIA20 DIA11 DIA10
Bit Name Content
H-bridge Disable:
7 /ABE / DIS
0, if /ABE = 0 or DIS = 1
6 OT Over temperature: 0:OT, 1: no OT
5:4 Reserved 0
3 DIA21
2 DIA20
Diagnose Bits (Table 30: Diagnosis bits (DIA_REG1))
1 DIA11
0 DIA10
Reset(5.4.
7 6 5 4 3 2 1 0
1)
POR X 1 1 1 1 1 1 1
SPIR X 1 X X 1 1 1 1
ENDISR X 1 X X 1 1 1 1
RDR X X X X X X X X
DIACLR1 X 1 X X 1 1 1 1

DocID027540 Rev 3 35/49

48
SPI functional description L9959

Table 30. Diagnosis bits (DIA_REG1)

DIA21 DIA20 DIA11 DIA10 Description Remark

0 0 0 1 Short Circuit to Ground at OUT1 (SCG1) Latched

0 0 1 0 Short Circuit to Ground at OUT2 (SCG2) Latched
0 1 0 1 Short Circuit to Battery at OUT1 (SCB1) Latched
0 1 1 0 Short Circuit to Battery at OUT2 (SCB2) Latched
0 1 1 1 Short Circuit over Load (SCL) Latched
1 0 0 0 Short Circuit to Battery at Disabled Output Latched
1 0 0 1 Short Circuit to Ground at Disabled Output Latched
1 0 1 0 Open Load at disabled or active Output (OL) Latched
1 1 0 1 Under Voltage at VS Not Latched
1 1 1 1 No Failure -

Note: Reading this register does not reset the bits. Writing STACON_REG.DIACLR1 = 0 transfers
all latched errors to DIA_REG2 and resets DIA_REG1 afterwards, if there is no VS-
undervoltage.

Table 31. Diagnosis register 2 (DIA_REG2)

Bit 7 6 5 4 3 2 1 0

Name CurrRed CurrLim OT Res DIA21 DIA20 DIA11 DIA10

Bit Name Content

Current Reduction:
7 CurrRed 0, if temperature dependent current reduction is active This information bit is reset after
each read access
Current Limitation:
6 CurrLim
0, if current limitation is active This information bit is reset after each read access
Over temperature
5 OT 1 no over-temperature
0 over-temperature
4 Res Reserved, 0
3 DIA21
2 DIA20
Diagnosis Bits (see Table 32: Diagnosis bits (DIA_REG2))
1 DIA11
0 DIA10

Reset(5.4.
7 6 5 4 3 2 1 0
1)

POR 1 1 1 0 1 1 1 1
SPIR 1 1 1 X 1 1 1 1
ENDISR 1 1 X X X X X X
RDR 1 1 X X X X X X
DIACLR2 1 1 1 X 1 1 1 1

36/49 DocID027540 Rev 3

L9959 SPI functional description

Table 32. Diagnosis bits (DIA_REG2)

DIA21 DIA20 DIA11 DIA10 Description Remark

0 0 0 1 Short Circuit to Ground at OUT1 (SCG1) Latched

0 0 1 0 Short Circuit to Ground at OUT2 (SCG2) Latched
0 1 0 1 Short Circuit to Battery at OUT1 (SCB1) Latched
0 1 1 0 Short Circuit to Battery at OUT2 (SCB2) Latched
0 1 1 1 Short Circuit over Load (SCL) Latched
1 0 0 0 Short Circuit to Battery at Disabled Output Latched
1 0 0 1 Short Circuit to Ground at Disabled Output Latched
1 0 1 0 Open Load at disabled or active Output (OL) Latched
1 1 1 1 No Failure -

Table 33. Configuration register (CONFIG_REG)

Bit 7 6 5 4 3 2 1 0

Name FW MUX SPWM SDIR CL1 CL2 RESET OLDA

Bit Name Content

Free-Wheeling mode selection 0:

7 FW
FW via Body Diode; 1: FW with active short of Body Diode
Multiplex Bit for H-bridge control strategy:
6 MUX
0: control by bits SPWM and SDIR; 1: Control by inputs PWM and DIR
5 SDIR SPI control for Direction: Same as input DIR
4 SPWM SPI control for PWM: Same as input PWM
3 CL1
See Table 34: Current Level (CONFIG_REG).
2 CL2
1 RESET Reset: 0: Reset of device configuration to default; 1: No change
0 OLDA Open-Load Diagnosis in active mode: 1: OLDA is enabled; 0: OLDA is disabled

Reset(5.4.
7 6 5 4 3 2 1 0
1)

POR 1 1 1 1 1 0 1 0
SPIR 1 1 1 1 1 0 1 0
ENDISR X X X X X X 1 X
RDR X X X X X X 1 X

DocID027540 Rev 3 37/49

48
SPI functional description L9959

Table 34. Current Level (CONFIG_REG)

CL1 CL2 Current Level Typical Current
0 0 No Change No Change
0 1 2 5.0 A
1 0 3 (default value) 6.6 A
1 1 4 8.6 A

Table 35. Status and configuration register (STATCON_REG)

Bit 7 6 5 4 3 2 1 0

Name CONFIG2 CONFIG1 CONFIG0 DIACLR2 DIACLR1 STATUS2 STATUS1 STATUS0

Bit Name Content

VDD Test Threshold:

7 CONFIG2
0: VDD Threshold Test is on 1: VDD Threshold test is off
VDD Test Threshold:
6 CONFIG1
1: Lower VDD Test Threshold is lifted 0:Upper VDD Test Threshold is lowered
5 CONFIG0 VDD Over-Voltage Latch: 0: Latch is disabled 1: Latch is enabled
Reset DIA_REG2:
4 DIACLR2
0: Reset errors in DIA_REG2 1: No action (Reading this bit always returns „1.)
Transfer Errors:
0: All latched errors of DIA_REG1 are transferred to DIA_REG2. DIA21,DIA20, DIA11,
3 DIACLR1 DIA10are set to “1111”.
During VS-Undervoltage DIACLR1 is disabled 1: No action (Reading this bit always
returns „1.)
2 STATUS2 Logic Level at Pin /ABE
VDD Under-Voltage:
1 STATUS1 0: Under-Voltage
1: No Under-Voltage
VDD Over-Voltage:
0: Over-Voltage
0 STATUS0 1: No Over-Voltage
This information is not reset during VS-Undervoltage. It will be reset by CONFIG0, SPI
reset or internal VDD reset

Reset(5.4.1) 7 6 5 4 3 2 1 0

POR 1 1 0 1 1 X X X
SPIR 1 1 0 1 1 X X X
ENDISR X X X 1 1 X X X
RDR X X X 1 1 X X X

Note: Only the bits ‘CONFIG’ and ‘DIACLR’ in this register can be written, all other bits are ‘read-
only’

38/49 DocID027540 Rev 3

L9959 SPI functional description

Table 36. Special register (SPECIAL_REG)

Bit 7 6 5 4 3 2 1 0

OLDAFILT Not Not SPRCSPE

Name Not specified SR
ER specified specified C
Controller access:
write-access: WR_SPECIAL
read-access: RD_SPECIAL

Bit Name Content

Not
7 -
specified
Not
6 -
specified
Not
5 -
specified
Open-load filter in active mode only.
OLDAFILT OLDAFILTER is a don't care in case of Off state
4
ER 1: open-load in on detected after one retry
0: openload in on detected after 40 ms
Not
3 -
specified
Voltage SR selection
2 SR 1: fast slew rate
0: slow slew rate
Not
1 -
specified
SPREADSPECTRUM mode selection
1: spread spectrum = active
SPRCSPE 0: spread spectrum = disabled
0
C Spread spectrum = active provides the internal state machine with slightly tittering clock.
Spread spectrum = disabled. The internal state machine runs with constant clock
frequency.

Reset
( 7 6 5 4 3 2 1 0
5.4.1)

POR 0 0 0 1 0 0 0 1
SPIR 0 0 0 1 0 0 0 1
ENDISR X X X X X X X X
RDR X X X X X X X X

DocID027540 Rev 3 39/49

48
SPI functional description L9959

5.4.1 Reset sources

 POR: Reset due to a VDD power up on VDD (Power-Up Reset)
 ENDISR: Reset caused by an enable or disable of the power stages (DIS or /ABE edge
triggered) (Enable-/Disable Reset)

5.4.2 Configuration registers reset sources

 POR: Reset due to a VDD power up on VDD (Power-Up Reset)
 SPIR: Reset by setting bit RESET in the configuration register (CONFIG_REG)
(SPIReset)
 RDIR: Reset caused by a read access to the corresponding register (Read Register)
 DIACLR1: Reset by setting bit DIACLR1 in the Status and Configuration Register
STATCON (Diagnosis Reset 1)
 DIACLR2: Reset by setting bit DIACLR2 in the Status and Configuration Register
STATCON (Diagnosis Reset 2)

40/49 DocID027540 Rev 3

L9959 Application circuit

6 Application circuit

Figure 21. Application circuit

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DocID027540 Rev 3 41/49

48
Package information L9959

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

7.1 PowerSSO-24 (exposed pad) package information

Figure 22. PowerSSO-24 (exposed pad) package outline
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L9959 Package information

Table 37. PowerSSO-24 (exposed pad) package mechanical data

Dimensions

Ref Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

Ө 0° - 8° 0° - 8°
Ө1 5° - 10° 5° - 10°
Ө2 0° - - 0° - -
A - - 2.45 - 0.0965
A1 0.0 - 0.1 0.0 0.0039
A2 2.15 - 2.35 0.0846 0.0925
b 0.33 - 0.51 0.013 0.0201
b1 0.28 0.40 0.48 0.011 0.0157 0.0189
c 0.23 - 0.32 0.0091 0.0126
c1 0.20 0.20 0.30 0.0079 0.0079 0.0118
(2)
D 10.30 BSC 0.4055 BSC
D1 VARIATION
D2 - 3.65 - - 0.1437 -
D3 - 4.30 - - 0.1693 -
e 0.80 BSC 0.0315 BSC
E 10.30 BSC 0.4055 BSC
(2)
E1 7.50 BSC 0.2953 BSC
E2 VARIATION
E3 - 2.30 - - 0.0906 -
E4 - 2.90 - - 0.1142 -
G1 - 1.20 - - 0.0472 -
G2 - 1.0 - - 0.0394 -
G3 - 0.80 - - 0.0315 -
h 0.30 - 0.40 0.0118 - 0.0157
L 0.55 0.70 0.85 0.0217 - 0.0335
L1 1.40 REF 0.0551 REF
L2 0.25 BSC 0.0098 BSC
N 24 (# lead)
R 0.30 - - 0.0118 - -
R1 0.20 - - 0.0079 - -
S 0.25 - - 0.0098 - -

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Package information L9959

Table 37. PowerSSO-24 (exposed pad) package mechanical data (continued)

Dimensions

Ref Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

Tolerance of form and position

aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.10 0.0039
ddd 0.20 0.0079
eee 0.10 0.0039
ffff 0.20 0.0079
ggg 0.15 0.0059
VARIATIONS

Option A

D1 6.5 - 7.1 0.2559 - 0.2795

E2 4.1 - 4.7 0.1614 - 0.1850

Option B

D1 4.9 - 5.5 0.1929 - 0.2165

E2 4.1 - 4.7 0.1614 - 0.1850
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimensions D and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is ‘0.25
mm’ per side D and ‘0.15 mm’ per side E1. D and E1 are Maximum plastic body size dimensions including
mold mismatch.

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L9959 Package information

7.2 PowerSSO-36 (exposed pad) package information

Figure 23. PowerSSO-36 (exposed pad) package outline

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Table 38. PowerSSO-36 (exposed pad) package mechanical data

Dimensions

Ref Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

Ө 0° - 8° 0° - 8°
Ө1 5° - 10° 5° - 10°
Ө2 0° - - 0° - -
A 2.15 - 2.45 0.0846 - 0.0965

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Package information L9959

Table 38. PowerSSO-36 (exposed pad) package mechanical data (continued)

Dimensions

Ref Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

A1 0.0 - 0.1 0.0 - 0.0039

A2 2.15 - 2.35 0.0846 - 0.0925
b 0.18 - 0.32 0.0071 - 0.0126
b1 0.13 0.25 0.3 0.0051 0.0098 0.0118
c 0.23 - 0.32 0.0091 - 0.0126
c1 0.2 0.2 0.3 0.0079 0.0079 0.0118
(2)
D 10.30 BSC 0.4055 BSC
D1 VARIATION
D2 - 3.65 - - 0.1437 -
D3 - 4.3 - - 0.1693 -
e 0.50 BSC 0.0197 BSC
E 10.30 BSC 0.4055 BSC
(2)
E1 7.50 BSC 0.2953 BSC
E2 VARIATION
E3 - 2.3 - - 0.0906 -
E4 - 2.9 - - 0.1142 -
G1 - 1.2 - - 0.0472 -
G2 - 1 - - 0.0394 -
G3 - 0.8 - - 0.0315 -
h 0.3 - 0.4 0.0118 - 0.0157
L 0.55 0.7 0.85 0.0217 - 0.0335
L1 1.40 REF 0.0551 REF
L2 0.25 BSC 0.0098 BSC
N 36 1.4173
R 0.3 - - 0.0118 - -
R1 0.2 - - 0.0079 - -
S 0.25 - - 0.0098 - -
Tolerance of form and position
aaa 0.2 0.0079
bbb 0.2 0.0079
ccc 0.1 0.0039
ddd 0.2 0.0079

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Table 38. PowerSSO-36 (exposed pad) package mechanical data (continued)

Dimensions

Ref Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

eee 0.1 0.0039

ffff 0.2 0.0079
ggg 0.15 0.0059
VARIATIONS

Option A

D1 6.5 - 7.1 0.2559 - 0.2795

E2 4.1 - 4.7 0.1614 - 0.1850

Option B

D1 4.9 - 5.5 0.1929 - 0.2165

E2 4.1 - 4.7 0.1614 - 0.1850

Option C

D1 6.9 - 7.5 0.2717 - 0.2953

E2 4.3 - 5.2 0.1693 - 0.2047
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimensions D and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is ‘0.25
mm’ per side D and ‘0.15 mm’ per side E1. D and E1 are Maximum plastic body size dimensions including
mold mismatch.

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Revision history L9959

8 Revision history

Table 39. Document revision history

Date Revision Changes
27-Jul-2015 1 Initial release.
Added:
– New commercial part number in Table 1: Device summary on
page 1;
– Figure 4: PSSO36 (Single version) pin connection (top view) on
28-Oct-2015 2 page 8;
– Table 4: L9959U (Single version in PSSO36) pin out on page 12.
Corrected in Table 10: VDD monitoring on page 15 the test
conditions of VABE_OUTL.
Updated Description on page 1.
Corrected typo in the Table 10: VDD monitoring on page 15 (Test
25-Feb-2016 3
condition column of the ‘VABE_OUTL’ parameter).

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