VND830LSP

Double channel high-side driver

Features

Type RDS(on) IOUT VCC

VND830LSP 60 mΩ(1) 18 A(1) 36 V 10

1. Per each channel.

1

■ CMOS compatible inputs PowerSO-10

■ Open drain status outputs
■ On-state open-load detection Description
■ Off-state open-load detection
The VND830LSP is a monolithic device designed
■ Shorted load protection using|STMicroelectronics™ VIPower™ M0-3
■ Undervoltage and overvoltage shutdown Technology. The VND830LSP is intended for
driving any type of multiple load with one side
■ Loss of ground protection
connected to ground.
■ Very low standby current
The Active VCC pin voltage clamp protects the
■ Reverse battery protection device against low energy spikes (see ISO7637
transient compatibility table). Active current
limitation combined with thermal shutdown and
automatic restart protects the device against
overload.
The open-load threshold is aimed at detecting the
5 W / 12 V standard bulb as an open-load fault in
the on-state.
The device detects the open-load condition in
both the on and off-state. In the off-state the
device detects if the output is shorted to VCC. The
device automatically turns off in the case where
the ground pin becomes disconnected.

Table 1. Device summary

Order codes
Package
Tube Tape and reel
PowerSO-10 VND830LSP VND830LSP13TR

October 2010 Doc ID 9431 Rev 4 1/27

www.st.com 1
Contents VND830LSP

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16
3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 17
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 19

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 PowerSO-10 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 PowerSO-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/27 Doc ID 9431 Rev 4

VND830LSP List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Switching (VCC = 13 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 10. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 11. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 13. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 14. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Doc ID 9431 Rev 4 3/27

List of figures VND830LSP

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 14. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. PowerSO-10 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 28. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29. Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10 . . . . . . . . . . . . . . . . . . . . 21
Figure 31. PowerSO-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. PowerSO-10 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. PowerSO-10 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 34. PowerSO-10 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4/27 Doc ID 9431 Rev 4

VND830LSP Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

Vcc

Vcc OVERVOLTAGE
CLAMP

UNDERVOLTAGE

GND CLAMP 1

OUTPUT1
INPUT1 DRIVER 1

CLAMP 2
STATUS1
CURRENT LIMITER 1 DRIVER 2
LOGIC
OVERTEMP. 1 OUTPUT2
OPEN LOAD ON 1
CURRENT LIMITER 2
INPUT2

OPEN LOAD OFF 1 OPEN LOAD ON 2

STATUS2

OPEN LOAD OFF 2

OVERTEMP. 2

Figure 2. Configuration diagram (top view)

GROUND 6 5 OUTPUT 1
INPUT 1 7 4 OUTPUT 1
STATUS 1 8 3 N.C.
STATUS 2 9 2 OUTPUT 2
INPUT 2 10 OUTPUT 2
1

11
VCC

Table 2. Suggested connections for unused and not connected pins

Connection / pin Status N.C. Output Input

Floating X X X X
Through 10KΩ
To ground X
resistor

Doc ID 9431 Rev 4 5/27

Electrical specifications VND830LSP

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VCC DC supply voltage 41 V

- VCC Reverse DC supply voltage - 0.3 V
- IGND DC reverse ground pin current - 200 mA
IOUT DC output current Internally limited A
- IOUT Reverse DC output current -6 A
IIN DC input current +/- 10 mA
ISTAT DC Status current +/- 10 mA

Electrostatic discharge (human body model: R = 1.5 KΩ;

C = 100 pF)
– INPUT 4000 V
VESD
– STATUS 4000 V
– OUTPUT 5000 V
– VCC 5000 V
Maximum switching energy
EMAX (L = 0.14 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C; 52 mJ
IL = 14 A)
Ptot Power dissipation (per island) at Tlead = 25 °C 74 W
Tj Junction operating temperature Internally limited °C
Tc Case operating temperature - 40 to 150
Tstg Storage temperature - 55 to 150 °C

6/27 Doc ID 9431 Rev 4

VND830LSP Electrical specifications

2.2 Thermal data

Table 4. Thermal data (per island)
Symbol Parameter Value Unit

Rthj-lead Thermal resistance junction-lead 2 °C/W

Rthj-amb Thermal resistance junction-ambient 52(1) 37(2) °C/W
2
1. When mounted on a standard single-sided FR-4 board with 0.5 cm of Cu (at least 35 µm thick) connected
to all VCC pins. Horizontal mounting and no artificial air flow.
2. When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35 µm thick) connected to
all VCC pins. Horizontal mounting and no artificial air flow.

2.3 Electrical characteristics

Values specified in this section are for 8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless
otherwise stated.

Figure 3. Current and voltage conventions

IS

IIN1 VF1 (*)

VCC
INPUT 1 VCC
VIN1 ISTAT1 IOUT1
STATUS 1 OUTPUT 1
VSTAT1 IIN2 VOUT1
INPUT 2 IOUT2
VIN2 ISTAT2 OUTPUT 2
VOUT2
STATUS 2
GND
VSTAT2
IGND

Note:
VFn = VCCn - VOUTn during reverse battery condition.

Doc ID 9431 Rev 4 7/27

Electrical specifications VND830LSP

Table 5. Power output

Symbol Parameter Test conditions Min. Typ. Max. Unit

Operating supply
VCC 5.5 13 36 V
voltage
VUSD Undervoltage shutdown 3 4 5.5 V
VOV Overvoltage shutdown 36 V
IOUT = 2A; Tj = 25°C 60 mΩ
RON On-state resistance
IOUT = 2A; VCC > 8V 120 mΩ
Off-state; VCC = 13 V;
12 40 µA
VIN = VOUT = 0 V
Off-state; VCC = 13 V;
IS Supply current VIN = VOUT = 0 V; 12 25 µA
Tj = 25 °C
On-state; VCC = 13 V; VIN = 5 V;
5 7 mA
IOUT = 0 A
IL(off1) Off-state output current VIN = VOUT = 0 V 0 50 µA
IL(off2) Off-state output current VIN = 0V; VOUT = 3.5 V -75 0 µA
VIN = VOUT = 0 V; VCC = 13 V;
IL(off3) Off-state output current 5 µA
Tj = 125 °C
VIN = VOUT = 0 V; VCC = 13 V;
IL(off4) Off-state output current 3 µA
Tj = 25 °C

Table 6. Protections
Symbol Parameter Test conditions Min. Typ. Max. Unit

TTSD Shutdown temperature 150 175 200 °C

TR Reset temperature 135 °C
Thyst Thermal hysteresis 7 15 °C
Status delay in overload
tSDL Tj > TTSD 20 µs
conditions
VCC = 13 V 18 23 29 A
Ilim Current limitation
5.5 V < VCC < 36 V 29 A
VCC - VCC - VCC -
Vdemag Turn-off output clamp voltage IOUT = 2 A; L = 6 mH V
41 48 55

Note: To ensure long term reliability under heavy overload or short circuit conditions, protection
and related diagnostic signals must be used together with a proper software strategy. If the
device is subjected to abnormal conditions, this software must limit the duration and number
of activation cycles.

8/27 Doc ID 9431 Rev 4

VND830LSP Electrical specifications

Table 7. VCC - output diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

VF Forward on voltage - IOUT = 1.3 A; Tj = 150 °C — — 0.6 V

Table 8. Switching (VCC = 13 V; Tj = 25 °C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

RL = 6.5 Ω from VIN rising

td(on) Turn-on delay time edge to VOUT = 1.3 V 5 30 60 µs
(see Figure 5)
RL = 6.5 Ω from VIN falling
td(off) Turn-off delay time edge to VOUT = 11.7 V 10 30 70 µs
(see Figure 5)
RL = 6.5 Ω from VOUT = 1.3 V
See
dVOUT/dt(on) Turn-on voltage slope to VOUT = 10.4 V 0.15 1.5 V/µs
Figure 10
(see Figure 5)
RL = 6.5 Ω from VOUT = 11.7 V
See
dVOUT/dt(off) Turn-off voltage slope to VOUT = 1.3 V 0.1 0.75 V/µs
Figure 12
(see Figure 5)

Table 9. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Input low level 1.25 V

IIL Low level input current VIN = 1.25 V 1 µA
VIH Input high level 3.25 V
IIH High level input current VIN = 3.25 V 10 µA
VI(hyst) Input hysteresis voltage 0.5 V
IIN = 1 mA 6 6.8 8 V
VICL Input clamp voltage
IIN = -1 mA -0.7 V

Table 10. Status pin

Symbol Parameter Test conditions Min. Typ. Max. Unit

VSTAT Status low output voltage ISTAT = 1.6 mA 0.5 V

ILSTAT Status leakage current Normal operation; VSTAT = 5V 10 µA
CSTAT Status pin Input capacitance Normal operation; VSTAT = 5V 100 pF
ISTAT = 1 mA 6 6.8 8 V
VSCL Status clamp voltage
ISTAT = - 1 mA -0.7 V

Doc ID 9431 Rev 4 9/27

Electrical specifications VND830LSP

Table 11. Open-load detection

Symbol Parameter Test conditions Min. Typ. Max. Unit

IOL Open-load on-state detection threshold VIN = 5 V 0.6 0.9 1.2 A

tDOL(on) Open-load on-state detection delay IOUT = 0 A 200 µs
Open-load off-state voltage detection
VOL VIN = 0 V 1.5 2.5 3.5 V
threshold
tDOL(off) Open-load detection delay at turn-off 1000 µs

Figure 4. Status timings

OPEN LOAD STATUS TIMING (with external pull-up) OVER TEMP STATUS TIMING
VOUT > VOL IOUT < IOL
Tj > TTSD
VINn
VINn

VSTATn
VSTATn
tSDL tSDL
tDOL(off)
tDOL(on)

Figure 5. Switching time waveforms

10/27 Doc ID 9431 Rev 4

VND830LSP Electrical specifications

Table 12. Truth table

Conditions Input Output Status

L L H
Normal operation
H H H
L L H
Current limitation H X (Tj < TTSD) H
H X (Tj > TTSD) L
L L H
Overtemperature
H L L
L L X
Undervoltage
H L X
L L H
Overvoltage
H L H
L H L
Output voltage > VOL
H H H
L L H
Output current < IOL
H H L

Table 13. Electrical transient requirements

ISO T/R Test level
7637/1
Test pulse I II III IV Delays and impedance

1 - 25V(1) - 50V(1) - 75V(1) - 100V(1) 2ms, 10Ω

(1)
2 + 25V + 50V(1) + 75V(1) + 100V(1) 0.2ms, 10Ω
3a - 25V(1) - 50V(1) - 100V(1) - 150V(1) 0.1µs, 50Ω
3b + 25V(1) + 50V(1) + 75V(1) + 100V(1) 0.1µs, 50Ω
(1) (1) (1) (1)
4 - 4V - 5V - 6V - 7V 100ms, 0.01Ω
(1) 46.5V(2) 66.5V(2) 86.5V(2)
5 + 26.5V + + + 400ms, 2Ω
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
proper operation without replacing the device.

Doc ID 9431 Rev 4 11/27

Electrical specifications VND830LSP

Figure 6. Waveforms

NORMAL OPERATION
INPUTn
LOAD VOLTAGEn
STATUSn

UNDERVOLTAGE
VCC VUSDhyst
VUSD
INPUTn
LOAD VOLTAGEn
STATUS undefined

OVERVOLTAGE
VCC<VOV VCC > VOV
VCC
INPUTn
LOAD VOLTAGEn
STATUSn

OPEN LOAD with external pull-up

INPUTn
VOUT > VOL
LOAD VOLTAGEn
VOL
STATUSn

OPEN LOAD without external pull-up

INPUTn

LOAD VOLTAGEn
STATUSn

OVERTEMPERATURE
Tj TTSD
TR

INPUTn
LOAD CURRENTn
STATUSn

12/27 Doc ID 9431 Rev 4

VND830LSP Electrical specifications

2.4 Electrical characteristics curves

Figure 7. Off-state output current Figure 8. High level input current
IL(off1) Iih (µA)
1.35 6

1.2 5.25
Off State
Vin=3.25V
1.05 Vcc=13V 4.5
Vin=Vout=0V
0.9
3.75
0.75
3
0.6
2.25
0.45

1.5
0.3

0.15 0.75

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (ºC) Tc (ºC)

Figure 9. Input clamp voltage Figure 10. Turn-on voltage slope

Vicl (V) dVout/dt(on) (V/ms)
8 800

7.8
700
Iin=1mA Vcc=13V
7.6
Rl=6.5Ohm
600
7.4

7.2 500

7 400

6.8
300
6.6
200
6.4

6.2 100

6 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (ºC)

Figure 11. Overvoltage shutdown Figure 12. Turn-off voltage slope

Vov (V) dVout/dt(off) (V/ms)
50 800

48 700
Vcc=13V
46 Rl=6.5Ohm
600
44
500
42

40 400

38 300

36
200
34
100
32

30 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175

Tc (°C) Tc (ºC)

Doc ID 9431 Rev 4 13/27

Electrical specifications VND830LSP

Figure 13. ILIM vs Tcase Figure 14. On-state resistance vs VCC

Ilim (A) Ron (mOhm)
35 160

32.5
Vcc=13V 140
30 Iout=2A
120
27.5

25 100

22.5 Tc=150ºC
80

20
60
17.5 Tc=25ºC
40
15 Tc= -40ºC

12.5 20

10 0
-50 -25 0 25 50 75 100 125 150 175 0 5 10 15 20 25 30 35 40
Tc (ºC) Vcc (V)

Figure 15. Input high level Figure 16. Input hysteresis voltage

Vih (V)
Vhyst (V)
4
1.5
3.8
1.4
3.6
1.3
3.4
1.2
3.2
1.1
3
1
2.8
0.9
2.6
0.8
2.4
0.7
2.2
0.6
2
0.5
-50 -25 0 25 50 75 100 125 150 175
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC) Tc (°C)

Figure 17. On-state resistance vs Tcase Figure 18. Input low level

Ron (mOhm) Vil (V)

100 2.25

90 2.125

80
Iout=2A
Vcc=13V 2
70
1.875
60

50 1.75

40 1.625

30
1.5
20
1.375
10

0 1.25
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175

Tc (ºC) Tc (ºC)

14/27 Doc ID 9431 Rev 4

VND830LSP Electrical specifications

Figure 19. Status leakage current Figure 20. Status low output voltage
Ilstat (µA) Vstat (V)
0.07 0.8

0.06 0.7
Istat=1.6mA
Vstat=5V
0.6
0.05

0.5
0.04
0.4
0.03
0.3

0.02
0.2

0.01 0.1

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (ºC) Tc (ºC)

Figure 21. Status clamp voltage Figure 22. Open-load on-state detection
threshold
Vscl (V) Iol (A)
8 2

7.8
1.75
Istat=1mA
7.6 Vin=5V
1.5
7.4
1.25
7.2

7 1

6.8
0.75
6.6
0.5
6.4
0.25
6.2

6 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (ºC)

Figure 23. Open-load off-state voltage

detection threshold
Vol (V)
5

4.5
Vin=0V
4

3.5

2.5

1.5

0.5

0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)

Doc ID 9431 Rev 4 15/27

Application information VND830LSP

3 Application information

Figure 24. Application schematic

+5V +5V

+5V
VCC

Rprot STATUS1

Dld

μC Rprot INPUT1
OUTPUT1

Rprot STATUS2

Rprot INPUT2

GND OUTPUT2

RGND
VGND DGND

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against
reverse battery.

3.1.1 Solution 1: a resistor in the ground line (RGND only)

This can be used with any type of load.
The following show how to dimension the RGND resistor:
1. RGND ≤ 600 mV / 2 (IS(on)max)
2. RGND ≥ ( -VCC) / ( -IGND)
where - IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC < 0 during reverse battery situations) is:
PD = ( -VCC)2/ RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.

16/27 Doc ID 9431 Rev 4

VND830LSP Application information

Please note that, if the microprocessor ground is not shared by the device ground, then the
RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift varies depending on how many devices are ON in the case of several high
side drivers sharing the same RGND .
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.

3.1.2 Solution 2: a diode (DGND) in the ground line

A resistor (RGND = 1 kΩ) should be inserted in parallel to DGND if the device is driving an
inductive load. This small signal diode can be safely shared amongst several different HSD.
Also in this case, the presence of the ground network produces a shift (≈600 mV) in the
input threshold and the status output values if the microprocessor ground is not common
with the device ground. This shift not varies if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the Absolute Maximum
Rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.

3.2 Load dump protection

Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCC maximum DC rating. The same applies if the device is subject to transients on the VCC
line that are greater than those shown in the ISO T/R 7637/1 table.

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent
the microcontroller I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:
- VCCpeak / Ilatchup ≤ Rprot ≤ (VOHμC - VIH - VGND) / IIHmax

Example
For the following conditions:
VCCpeak = -100 V
Ilatchup ≥ 20 mA
VOHμC ≥ 4.5 V
5 kΩ ≤ Rprot ≤ 65 kΩ.
Recommended values are:
Rprot = 10 kΩ

Doc ID 9431 Rev 4 17/27

Application information VND830LSP

3.4 Open-load detection in off-state

Off-state open-load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5 V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1) no false open-load indication when load is connected: in this case we have to avoid VOUT
to be higher than VOlmin; this results in the following condition
VOUT = (VPU / (RL + RPU))RL < VOlmin.
2) no misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2).
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-
up resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.

Figure 25. Open-load detection in off-state

V batt. VPU

VCC

RPU

DRIVER
INPUT + IL(off2)
LOGIC

OUT
+
R
-
STATUS
VOL
RL

GROUND

18/27 Doc ID 9431 Rev 4

VND830LSP Application information

3.5 Maximum demagnetization energy (VCC = 13.5 V)

Figure 26. Maximum turn-off current versus load inductance

I LM AX (A)
100

10

C B

1
0,01 0,1 1 10 100
L(mH)

A = single pulse at TJstart = 150 °C

B= repetitive pulse at TJstart = 100 °C
C= repetitive pulse at TJstart = 125 °C

VIN, IL
Demagnetization Demagnetization Demagnetization

Note:
Values are generated with RL = 0Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature
specified above for curves B and C.

Doc ID 9431 Rev 4 19/27

Package and PCB thermal data VND830LSP

4 Package and PCB thermal data

4.1 PowerSO-10 thermal data

Figure 27. PowerSO-10 PC board

Note:
Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness =
35 µm, Copper areas: from minimum pad lay-out to 8 cm2).

Figure 28. Rthj-amb vs PCB copper area in open box free air condition

RTHj_amb (°C/W)

55
Tj-Tamb=50°C
50

45

40

35

30
0 2 4 6 8 10
PCB Cu heatsink area (cm^2)

20/27 Doc ID 9431 Rev 4

VND830LSP Package and PCB thermal data

Figure 29. Thermal impedance junction ambient single pulse

ZTH (°C/W)
1000

100
0.5 cm2

6 cm2

10

0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)

Equation 1: pulse calculation formula

Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tp ⁄ T

Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10

Tj_1 C1 C2 C3 C4 C5 C6

R1 R2 R3 R4 R5 R6
Pd1

C1 C2
Tj_2
R1 R2

Pd2

T_amb

Doc ID 9431 Rev 4 21/27

Package and PCB thermal data VND830LSP

Table 14. Thermal parameters

Area / island (cm2) Footprint 6

R1 (°C/W) 0.15
R2 (°C/W) 0.8
R3 (°C/W) 0.7
R4 (°C/W) 0.8
R5 (°C/W) 12
R6 (°C/W) 37 22
C1 (W.s/°C) 0.0006
C2 (W.s/°C) 2.1E-03
C3 (W.s/°C) 0.013
C4 (W.s/°C) 0.3
C5 (W.s/°C) 0.75
C6 (W.s/°C) 3 5

22/27 Doc ID 9431 Rev 4

VND830LSP Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

5.2 PowerSO-10 mechanical data

Figure 31. PowerSO-10 package dimensions

0.10 A B
10

H E E2 E E4

1
SEATING
PLANE

e B DETAIL "A" A

0.25 C

D
h = D1 =
= =
SEATING
PLANE
A
F
A1 A1

L
DETAIL "A"

Doc ID 9431 Rev 4 23/27

Package and packing information VND830LSP

Table 15. PowerSO-10 mechanical data

mm
Dim.
Min. Typ. Max.

A 3.35 3.65

A(1) 3.4 3.6

A1 0 0.10

B 0.40 0.60

B(1) 0.37 0.53

C 0.35 0.55

C(1) 0.23 0.32

D 9.40 9.60

D1 7.40 7.60

E 9.30 9.50

E2 7.20 7.60

E2(1) 7.30 7.50

E4 5.90 6.10

E4(1) 5.90 6.30

e 1.27

F 1.25 1.35

F(1) 1.20 1.40

H 13.80 14.40

H(1) 13.85 14.35

h 0.50

L 1.20 1.80

L(1) 0.80 1.10

α 0° 8°

α(1) 2° 8°

1. Muar only POA P013P.

24/27 Doc ID 9431 Rev 4

VND830LSP Package and packing information

5.3 PowerSO-10 packing information

Figure 32. PowerSO-10 suggested Figure 33. PowerSO-10 tube shipment
pad layout (no suffix)
14.6 - 14.9

10.8 - 11
B CASABLANCA MUAR
C
6.30

A C
A

0.67 - 0.73 B
1 10
0.54 - 0.6
2 9
All dimensions are in mm.
3 8
9.5
4 7 1.27 Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1)
5 6 Casablanca 50 1000 532 10.4 16.4 0.8
Muar 50 1000 532 4.9 17.2 0.8

Figure 34. PowerSO-10 tape and reel shipment (suffix “TR”)

Reel dimensions

Base Q.ty 600

Bulk Q.ty 600
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 24.4
N (min) 60
T (max) 30.4

Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 24
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 11.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm. End

Start

Top No components Components No components

cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

Doc ID 9431 Rev 4 25/27

Revision history VND830LSP

6 Revision history

Table 16. Document revision history

Date Revision Changes

09-Sep-2004 1 Initial release.

Current and voltage convention update (page 2).
Configuration diagram (top view) & suggested connections for unused
and n.c. pins insertion (page 2).
6 cm2 Cu condition insertion in thermal data table (page 3).
03-Mar-2008 2
VCC - output diode section update (page 4).
Protections note insertion (page 4).
Revision history table insertion (page 18).
Disclaimers update (page 19).
Document reformatted and restructured.
09-Dec-2008 3 Added contents, list of tables and figures.
Added ECOPACK® packages information.
08-Oct-2010 4 Updated Figure 5: Switching time waveforms.

26/27 Doc ID 9431 Rev 4

VND830LSP

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Doc ID 9431 Rev 4 27/27