VNH3SP30-E

Automotive fully integrated H-bridge motor driver

Features

Type RDS(on) Iout Vccmax

45mΩ max
VNH3SP30-E 30A 40V
(per leg)

MultiPowerSO-30™
■ Output current: 30A
■ 5V logic level compatible inputs
■ Undervoltage and overvoltage shutdown The low-side switches are vertical MOSFETs
■ Overvoltage clamp manufactured using STMicroelectronics
proprietary EHD (“STripFET™”) process.The
■ Thermal shut down
three circuits are assembled in a MultiPowerSO-
■ Cross-conduction protection 30 package on electrically isolated lead frames.
■ Linear current limiter This package, specifically designed for the harsh
automotive environment, offers improved thermal
■ Very low standby power consumption
performance thanks to exposed die pads.
■ PWM operation up to 10 kHz Moreover, its fully symmetrical mechanical design
■ Protection against loss of ground and loss of provides superior manufacturability at board level.
VCC The input signals INA and INB can directly
interface with the microcontroller to select the
■ Package: ECOPACK®
motor direction and the brake condition. Pins
DIAGA/ENA or DIAGB/ENB, when connected to an
Description external pull-up resistor, enable one leg of the
bridge. They also provide a feedback digital
The VNH3SP30-E is a full-bridge motor driver diagnostic signal. The normal condition operation
intended for a wide range of automotive is explained in The speed of the motor can be
applications. The device incorporates a dual controlled in all possible conditions by the PWM
monolithic high-side driver (HSD) and two low- up to kHz. In all cases, a low level state on the
side switches. The HSD switch is designed using PWM pin will turn off both the LSA and LSB
STMicroelectronics proprietary VIPower™ M0-3 switches. When PWM rises to a high level, LSA or
technology that efficiently integrates a true Power LSB turn on again depending on the input pin
MOSFET with an intelligent signal/protection state.
circuit on the same die.

Table 1. Device summary

Order codes
Package
Tube Tape & reel

MultiPowerSO-30 VNH3SP30-E VNH3SP30TR-E

February 2008 Rev 7 1/33

www.st.com 33
Contents VNH3SP30-E

Contents

1 Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Open load detection in Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 MultiPowerSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.1 Thermal calculation in clockwise and anti-clockwise operation in steady-
state mode 26
4.1.2 Thermal resistances definition
(values according to the PCB heatsink area) . . . . . . . . . . . . . . . . . . . . . 26
4.1.3 Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.4 Single pulse thermal impedance definition
(values according to the PCB heatsink area) . . . . . . . . . . . . . . . . . . . . . 26

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 MultiPowerSO-30 package mechanical data . . . . . . . . . . . . . . . . . . . . . . 29
5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2/33
VNH3SP30-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Pin functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Switching (VCC = 13V, RLOAD = 1.1Ω, unless otherwise specified) . . . . . . . . . . . . . . . . . . 10
Table 10. Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 12. Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 13. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 14. Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 26
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16. MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3/33
List of figures VNH3SP30-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Definition of the low side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Definition of the high side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. On state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Off state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. High level enable pin current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15. Delay time during change of operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Enable clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. High level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 18. Low level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 19. PWM high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 20. PWM low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 21. PWM high level current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 22. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 23. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 24. Current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 25. On state high side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. On state low side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 27. On state high side resistance vs Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28. On state low side resistance vs Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 29. Output voltage rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 30. Output voltage fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 31. Enable output low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 32. ON state leg resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 33. Typical application circuit for DC to 10 kHz PWM operation short circuit protection . . . . . 20
Figure 34. Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 35. Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 36. Waveforms in full bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 37. Waveforms in full bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 38. MultiPowerSO-30™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 39. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 40. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 25
Figure 41. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . 27
Figure 42. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . 27
Figure 43. Thermal fitting model of an H-bridge in MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 44. MultiPowerSO-30 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 45. MultiPowerSO-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 46. MultiPowerSO-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 47. MultiPowerSO-30 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4/33
VNH3SP30-E Block diagram and pins description

1 Block diagram and pins description

Figure 1. Block diagram

Table 2. Block description

Name Description

Allows the turn-on and the turn-off of the high side and the low side switches
Logic control
according to the truth table
Overvoltage +
Shuts down the device outside the range [5.5V..36V] for the battery voltage
undervoltage
High side and low Protects the high side and the low side switches from the high voltage on the
side clamp voltage battery line in all configurations for the motor
High side and low Drives the gate of the concerned switch to allow a proper RDS(on) for the leg of
side driver the bridge
Limits the motor current by reducing the high side switch gate-source voltage
Linear current limiter
when short-circuit to ground occurs
Overtemperature In case of short-circuit with the increase of the junction’s temperature, shuts
protection down the concerned high side to prevent its degradation and to protect the die
Signals an abnormal behavior of the switches in the half-bridge A or B by
Fault detection
pulling low the concerned ENx/DIAGx pin

5/33
Block diagram and pins description VNH3SP30-E

Figure 2. Configuration diagram (top view)

Table 3. Pin definitions and functions

Pin No Symbol Function

1, 25, 30 OUTA, Heat Slug3 Source of high side switch A / Drain of low side switch A
2, 4, 7, 9, 12,
14, 17, 22, 24, NC Not connected
29
3, 13, 23 VCC, Heat Slug1 Drain of high side switches and power supply voltage
6 ENA/DIAGA Status of high side and low side switches A; open drain output
5 INA Clockwise input
8 PWM PWM input
11 INB Counter clockwise input
10 ENB/DIAGB Status of high side and low side switches B; open drain output
15, 16, 21 OUTB, Heat Slug2 Source of high side switch B / Drain of low side switch B
26, 27, 28 GNDA Source of low side switch A(1)
18, 19, 20 GNDB Source of low side switch B(1)
1. GNDA and GNDB must be externally connected together.

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VNH3SP30-E Block diagram and pins description

Table 4. Pin functions description

Name Description

VCC Battery connection

GNDA, GNDB Power grounds; must always be externally connected together
OUTA, OUTB Power connections to the motor
Voltage controlled input pins with hysteresis, CMOS compatible. These two pins
INA, INB control the state of the bridge in normal operation according to the truth table (brake
to VCC, brake to GND, clockwise and counterclockwise).
Voltage controlled input pin with hysteresis, CMOS compatible. Gates of low side
PWM FETs are modulated by the PWM signal during their ON phase allowing speed
control of the motor.
Open drain bidirectional logic pins. These pins must be connected to an external pull
up resistor. When externally pulled low, they disable half-bridge A or B. In case of
ENA/DIAGA,
fault detection (thermal shutdown of a high side FET or excessive ON state voltage
ENB/DIAGB
drop across a low side FET), these pins are pulled low by the device (see truth table
in fault condition).

7/33
Electrical specifications VNH3SP30-E

2 Electrical specifications

Figure 3. Current and voltage conventions

2.1 Absolute maximum ratings

Table 5. Absolute maximum ratings
Symbol Parameter Value Unit

Vcc Supply voltage -0.3...40 V

Imax1 Maximum output current (continuous) 30
A
IR Reverse output current (continuous) -30
IIN Input current (INA and INB pins) ±10
IEN Enable input current (DIAGA/ENA and DIAGB/ENB pins) ±10 mA
Ipw PWM input current ±10
Electrostatic discharge (R = 1.5kΩ, C = 100pF)
VESD – logic pins 4 kV
– output pins: OUTA, OUTB, VCC 5 kV
Tj Junction operating temperature Internally limited
Tc Case operating temperature -40 to 150 °C
TSTG Storage temperature -55 to 150

8/33
VNH3SP30-E Electrical specifications

2.2 Electrical characteristics

Vcc = 9V up to 18V; -40°C < Tj < 150°C, unless otherwise specified.

Table 6. Power section

Symbol Parameter Test Conditions Min Typ Max Unit

Operating supply
VCC 5.5 36 V
voltage
Off state:
INA = INB = PWM = 0; Tj = 25°C; VCC = 13V 20 30 µA
IS Supply current INA = INB = PWM = 0 40 µA
On state:
INA or INB = 5V, no PWM 15 mA

Static high side IOUT = 12A; Tj = 25°C 23 30

RONHS
resistance IOUT = 12A; Tj = -40 to 150°C 60
mΩ
Static low side IOUT = 12A; Tj = 25°C 11 15
RONLS
resistance IOUT = 12A; Tj = -40 to 150°C 30
High side free-
Vf wheeling diode If = 12 A 0.8 1.1 V
forward voltage
High side off state Tj = 25°C; VOUTX = ENX = 0V; VCC = 13V 3
IL(off) output current µA
Tj = 125°C; VOUTX = ENX = 0V; VCC = 13V 5
(per channel)

Table 7. Logic inputs (INA, INB, ENA, ENB)

Symbol Parameter Test conditions Min Typ Max Unit

VIL Input low level voltage 1.5

Normal operation (DIAGX/ENX pin acts
VIH Input high level voltage 3.25
as an input pin)
VIHYST Input hysteresis voltage 0.5 V
IIN = 1mA 6 6.8 8
VICL Input clamp voltage
IIN = -1mA -1 -0.7 -0.3
IINL Input low current VIN = 1.5V 1
µA
IINH Input high current VIN = 3.25V 10
Enable output low level Fault operation (DIAGX/ENX pin acts as
VDIAG 0.4 V
voltage an output pin); IEN = 1mA

9/33
Electrical specifications VNH3SP30-E

Table 8. PWM
Symbol Parameter Test Conditions Min Typ Max Unit

Vpwl PWM low level voltage 1.5 V

PWM low level pin
Ipwl Vpw = 1.5V 1 µA
current
Vpwh PWM high level voltage 3.25 V
PWM high level pin
Ipwh Vpw = 3.25V 10 µA
current
Vpwhhyst PWM hysteresis voltage 0.5
Ipw = 1mA VCC + 0.3 VCC + 0.7 VCC + 1 V
Vpwcl PWM clamp voltage
Ipw = -1mA -5 -3.5 -2
Test mode PWM pin
Vpwtest -3.5 -2 -0.5 V
voltage
Test mode PWM pin
Ipwtest VIN = -2 V -2000 -500 µA
current

Table 9. Switching (VCC = 13V, RLOAD = 1.1Ω, unless otherwise specified)

Symbol Parameter Test Conditions Min Typ Max Unit

f PWM frequency 0 10 kHz

Input rise time < 1µs
td(on) Turn-on delay time 100 300
(see Figure 6)
Input rise time < 1µs
td(off) Turn-off delay time 85 255
(see Figure 6)
µs
tr Rise time (see Figure 5) 1.5 3
tf Fall time (see Figure 5) 2 5
Delay time during change
tDEL (see Figure 4) 600 1800
of operating mode

Table 10. Protection and diagnostic

Symbol Parameter Test Conditions Min Typ Max Unit

VUSD Undervoltage shut-down 5.5

V
VOV Overvoltage shut-down 36 43
ILIM Current limitation 30 45 A
TTSD Thermal shut-down temperature VIN = 3.25V 150 170 200
TTR Thermal reset temperature 135 °C
THYST Thermal hysteresis 7 15

10/33
VNH3SP30-E Electrical specifications

Figure 4. Definition of the delay times measurement

VINA

t
VINB

t
PWM

ILOAD

tDEL
tDEL

Figure 5. Definition of the low side switching times

PWM

VOUTA, B
90% 80%

tf
20% 10% tr t

11/33
Electrical specifications VNH3SP30-E

Figure 6. Definition of the high side switching times

VINA tD(on) tD(off)

t
VOUTA

90%

10%

12/33
VNH3SP30-E Electrical specifications

Table 11. Truth table in normal operating conditions

INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB Operating mode

1 H Brake to VCC
1 H
0 L Clockwise (CW)
1 1
1 H Counterclockwise (CCW)
0 L
0 L Brake to GND

Table 12. Truth table in fault conditions (detected on OUTA)

INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB

1 H
1
0 L
1
1 H
0
0 0 OPEN L
X 0 OPEN
X 1 H
1
0 L

Fault Information Protection Action

Note: Notice that saturation detection on the low side power MOSFET is possible only if the
impedance of the short-circuit from the output to the battery is less than 100mΩ when the
device is supplied with a battery voltage of 13.5V.

13/33
Electrical specifications VNH3SP30-E

Table 13. Electrical transient requirements

ISO T/R - 7637/1 Test Level Test Level Test Level Test Level Test Levels
Test Pulse I II III IV Delays and Impedance

1 -25V -50V -75V -100V 2ms, 10Ω

2 +25V +50V +75V +100V 0.2ms, 10Ω
3a -25V -50V -100V -150V
0.1µs, 50Ω
3b +25V +50V +75V +100V
4 -4V -5V -6V -7V 100ms, 0.01Ω
5 +26.5V +46.5V +66.5V +86.5V 400ms, 2Ω

ISO T/R - 7637/1 Test Levels Test Levels Test Levels Test Levels
Test Pulse Result I Result II Result III Result IV

1
2
3a C C C
C
3b
4
5(1) E E E
1. For load dump exceeding the above value a centralized suppressor must be adopted

Class Contents

All functions of the device are performed as designed after exposure to

C
disturbance.
One or more functions of the device are not performed as designed after
E exposure to disturbance and cannot be returned to proper operation without
replacing the device.

14/33
VNH3SP30-E Electrical specifications

2.3 Electrical characteristics curves

Figure 7. On state supply current Figure 8. Off state supply current

Figure 9. High level input current Figure 10. Input clamp voltage

Figure 11. Input high level voltage Figure 12. Input low level voltage

15/33
Electrical specifications VNH3SP30-E

Figure 13. Input hysteresis voltage Figure 14. High level enable pin current

Figure 15. Delay time during change of Figure 16. Enable clamp voltage
operation mode

Figure 17. High level enable voltage Figure 18. Low level enable voltage

16/33
VNH3SP30-E Electrical specifications

Figure 19. PWM high level voltage Figure 20. PWM low level voltage

Figure 21. PWM high level current Figure 22. Overvoltage shutdown

Figure 23. Undervoltage shutdown Figure 24. Current limitation

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Electrical specifications VNH3SP30-E

Figure 25. On state high side resistance vs Figure 26. On state low side resistance vs
Tcase Tcase

Figure 27. On state high side resistance vs Figure 28. On state low side resistance vs Vcc
Vcc

Figure 29. Output voltage rise time Figure 30. Output voltage fall time

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VNH3SP30-E Electrical specifications

Figure 31. Enable output low level voltage Figure 32. ON state leg resistance

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Application information VNH3SP30-E

3 Application information

In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled high.
PWM pin usage: In all cases, a “0” on the PWM pin will turn off both LSA and LSB switches.
When PWM rises back to “1”, LSA or LSB turn on again depending on the input pin state.

Figure 33. Typical application circuit for DC to 10 kHz PWM operation short circuit
protection

µC

Note: The value of the blocking capacitor (C) depends on the application conditions and defines voltage and
current ripple onto supply line at PWM operation. Stored energy of the motor inductance may fly back
into the blocking capacitor, if the bridge driver goes into tri-state. This causes a hazardous overvoltage
if the capacitor is not big enough. As basic orientation, 500µF per 10A load current is recommended.

In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device.
The fault conditions are:
● overtemperature on one or both high sides
● short to battery condition on the output (saturation detection on the low side power
MOSFET)

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VNH3SP30-E Application information

Possible origins of fault conditions may be:

● OUTA is shorted to ground →overtemperature detection on high side A.
● OUTA is shorted to VCC →low side power MOSFET saturation detection(a).
When a fault condition is detected, the user can know which power element is in fault by
monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins.
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the
respective output (OUTX) again, the input signal must rise from low to high level.

3.1 Reverse battery protection

Three possible solutions can be considered:
1. a Schottky diode D connected to VCC pin
2. an N-channel MOSFET connected to the GND pin (see Figure 33: Typical application
circuit for DC to 10 kHz PWM operation short circuit protection on page 20
3. a P-channel MOSFET connected to the VCC pin
The device sustains no more than -30A in reverse battery conditions because of the two
body diodes of the power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH3SP30-E will be pulled down to the VCC line (approximately -1.5V). A series resistor
must be inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the
maximum target reverse current through µC I/Os, the series resistor is:

V IOs – V CC
R = ---------------------------------
I Rmax

3.2 Open load detection in Off mode

It is possible for the microcontroller to detect an open load condition by adding a simply
resistor (for example, 10k ohm) between one of the outputs of the bridge (for example,
OUTB) and one microcontroller input. A possible sequence of inputs and enable signals is
the following: INA = 1, INB = X, ENA = 1, ENB = 0.
● normal condition: OUTA = H and OUTB = H
● open load condition: OUTA = H and OUTB = L: In this case the OUTB pin is internally
pulled down to GND. This condition is detected on OUTB pin by the microcontroller as
an open load fault.

a. An internal operational amplifier compares the Drain-Source MOSFET voltage with the internal reference (2.7V
Typ.). The relevant low side power MOS is switched off when its Drain-Source voltage exceeds the reference
voltage.

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Application information VNH3SP30-E

3.3 Test mode

The PWM pin can be used to test the load connection between two half-bridges. In the Test
mode (Vpwm = -2V) the internal power MOS gate drivers are disabled. The INA or INB inputs
can be used to turn on the high side A or B, respectively, in order to connect one side of the
load at VCC voltage. The check of the voltage on the other side of the load can be used to
verify the continuity of the load connection. In case of load disconnection, the DIADX/ENX
pin corresponding to the faulty output is pulled down.

Figure 34. Half-bridge configuration

VCC

INA INA
INB INB
DIAGA/ENA DIAGA/ENA
DIAGB/ENB DIAGB/ENB
PWM PWM

OUTA OUTB M OUTA OUTB

GNDA GNDB GNDA GNDB

Note: The VNH3SP30-E can be used as a high power half-bridge driver achieving an On
resistance per leg of 22.5mΩ.

Figure 35. Multi-motors configuration

VCC

INA INA
INB INB
DIAGA/ENA DIAGA/ENA
DIAGB/ENB DIAGB/ENB
PWM PWM

OUTA OUTB M2 OUTA OUTB

GNDA GNDB GNDA GNDB

M1 M3

Note: The VNH3SP30-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow
to put unused half-bridges in high impedance.

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VNH3SP30-E Application information

Figure 36. Waveforms in full bridge operation

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Application information VNH3SP30-E

Figure 37. Waveforms in full bridge operation (continued)

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VNH3SP30-E Package and PCB thermal data

4 Package and PCB thermal data

4.1 MultiPowerSO-30 thermal data

Figure 38. MultiPowerSO-30™ PC board

Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58mm x 58mm, PCB
thickness = 2mm, Cu thickness = 35µm, Copper areas: from minimum pad layout to
16cm2).

Figure 39. Chipset configuration

HIGH SIDE
CHIP
HSAB

LOW SIDE LOW SIDE

CHIP A CHIP B
LSA LSB

Figure 40. Auto and mutual Rthj-amb vs PCB copper area in open box free air
condition

45
RthHS
40 RthLS
35 RthHSLS
30 RthLSLS
25
20
15
°C/W

10
5
0
0 5 10 15 20
cm2 of Cu area (refer to PCB layout)

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Package and PCB thermal data VNH3SP30-E

4.1.1 Thermal calculation in clockwise and anti-clockwise operation in

steady-state mode

Table 14. Thermal calculation in clockwise and anti-clockwise operation in steady-

state mode
HSA HSB LSA LSB TjHSAB TjLSA TjLSB

PdHSA x RthHS + PdLSB PdHSA x RthHSLS + PdHSA x RthHSLS + PdLSB

ON OFF OFF ON
x RthHSLS + Tamb PdLSB x RthLSLS + Tamb x RthLS + Tamb
PdHSB x RthHS + PdLSA PdHSB x RthHSLS + PdHSB x RthHSLS + PdLSA
OFF ON ON OFF
x RthHSLS + Tamb PdLSA x RthLS + Tamb x RthLSLS + Tamb

4.1.2 Thermal resistances definition

(values according to the PCB heatsink area)
RthHS = RthHSA = RthHSB = High Side Chip Thermal Resistance Junction to Ambient (HSA or
HSB in ON state)
RthLS = RthLSA = RthLSB = Low Side Chip Thermal Resistance Junction to Ambient
RthHSLS = RthHSALSB = RthHSBLSA = Mutual Thermal Resistance Junction to Ambient
between High Side and Low Side Chips
RthLSLS = RthLSALSB = Mutual Thermal Resistance Junction to Ambient between Low Side
Chips

4.1.3 Thermal calculation in transient mode(b)

TjHSAB = ZthHS x PdHSAB + ZthHSLS x (PdLSA + PdLSB) + Tamb
TjLSA = ZthHSLS x PdHSAB + ZthLS x PdLSA + ZthLSLS x PdLSB + Tamb
TjLSB = ZthHSLS x PdHSAB + ZthLSLS x PdLSA + ZthLS x PdLSB + Tamb

4.1.4 Single pulse thermal impedance definition

(values according to the PCB heatsink area)
ZthHS = High Side Chip Thermal Impedance Junction to Ambient
ZthLS = ZthLSA = ZthLSB = Low Side Chip Thermal Impedance Junction to Ambient
ZthHSLS = ZthHSABLSA = ZthHSABLSB = Mutual Thermal Impedance Junction to Ambient
between High Side and Low Side Chips
ZthLSLS = ZthLSALSB = Mutual Thermal Impedance Junction to Ambient between Low Side
Chips

b. Calculation is valid in any dynamic operating condition. Pd values set by user.

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VNH3SP30-E Package and PCB thermal data

Equation 1: pulse calculation formula

Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ)
where δ = t p ⁄ T

Figure 41. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse
100

Footprint
4 cm2
ZthHS 8 cm2
16 cm2
Footprint
10 4 cm2
ZthHSLS 8 cm2
16 cm2
°C/W

0.1
0.001 0.01 0.1 time (sec) 1 10 100 1000

Figure 42. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse

100

Footprint
4 cm2
8 cm2
16 cm2
Footprint
10 4 cm2
8 cm2
16 cm2
°C/W

0,1
0,001 0,01 0,1 time (sec) 1 10 100 1000

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Package and PCB thermal data VNH3SP30-E

Figure 43. Thermal fitting model of an H-bridge in MultiPowerSO-30

Table 15. Thermal parameters(1)

Area/island (cm2) Footprint 4 8 16
R1 = R7 (°C/W) 0.05
R2 = R8 (°C/W) 0.3
R3 (°C/W) 0.5
R4 (°C/W) 1.3
R5 (°C/W) 14
R6 (°C/W) 44.7 39.1 31.6 23.7
R9 = R10= R15= R16 (°C/W) 0.6
R11 = R17 (°C/W) 0.8
R12 = R18 (°C/W) 1.5
R13 = R19 (°C/W) 20
R14 = R20 (°C/W) 46.9 36.1 30.4 20.8
R21 = R22 = R23 (°C/W) 115
C1 = C7 = C9 = C15 (W.s/°C) 0.001
C2 = C8 (W.s/°C) 0.005
C3 = (W.s/°C) 0.02
C4 = C13 = C19 (W.s/°C) 0.3
C5 (W.s/°C) 0.6
C6 (W.s/°C) 5 7 9 11
C10 = C11= C16 = C17 (W.s/°C) 0.003
C12 = C18 (W.s/°C) 0.075
C14 = C20 (W.s/°C) 2.5 3.5 4.5 5.5
1. The blank space means that the value is the same as the previous one.

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VNH3SP30-E Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.2 MultiPowerSO-30 package mechanical data

Figure 44. MultiPowerSO-30 package outline

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Package and packing information VNH3SP30-E

Table 16. MultiPowerSO-30 mechanical data

Millimeters
Symbol
Min Typ Max
A 2.35
A2 1.85 2.25
A3 0 0.1
B 0.42 0.58
C 0.23 0.32
D 17.1 17.2 17.3
E 18.85 19.15
E1 15.9 16 16.1
e 1
F1 5.55 6.05
F2 4.6 5.1
F3 9.6 10.1
L 0.8 1.15
N 10deg
S 0deg 7deg

Figure 45. MultiPowerSO-30 suggested pad layout

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VNH3SP30-E Package and packing information

5.3 Packing information

Note: The devices can be packed in tube or tape and reel shipments (see the Device summary on
page 1 for packaging quantities).

Figure 46. MultiPowerSO-30 tube shipment (no suffix)

Dimension mm
A Tube length (± 0.5) 532
A 3.82
C B B 23.6
C (± 0.13) 0.8

Figure 47. MultiPowerSO-30 tape and reel shipment (suffix “TR”)

Reel dimensions

Dimension mm
A (max) 330
B (min) 1.5
C (± 0.2) 13
D (min) 20.2
G (+ 2 / -0) 32
N (min) 100
T (max) 38.4

Tape dimensions
According to Electronic Industries
Association (EIA) Standard 481 rev. A, Feb
1986

Description Dimension mm
Tape width W 32
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 24
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 2
Hole Position F (± 0.1) 14.2

End

Start

Top No components Components No components

cover
tape 500 mm min
500 mm min
Empty components pockets

User direction of feed

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Revision history VNH3SP30-E

6 Revision history

Table 17. Document revision history

Date Revision Description of changes

Initial release of lead-free version based on the VNH3SP30 datasheet

Aug-2004 1
(May 2004 - Rev.1)
Aug- 2005 2 Modified figure 5
Document converted into new ST corporate template.
Changed document title .
Changed features on page 1 to add ECOPACK® package.
Added section 1: device block description on page 5.
Added section 2: pinout description on page 6.
Added section 3: maximum ratings on page 8.
Added section 4: electrical characteristics on page 9.
Added “low” and “high” to parameters for IINL and IINH in Table 6 on
page 9.
20-Dec-2006 3 Added section 5: Waveforms and truth table on page 12.
Changed first of two fault conditions in section 5 on page 12.
Inserted note in Figure 4 on page 12.
Added vertical limitation line to left side arrow of tD(off) to Figure 7 on
page 17.
Added section 6: thermal data on page 26.
Added section 7: package characteristics on page 30.
Added section 8: packaging information on page 32.
Updated disclaimer (last page) to include a mention about the use of
ST products in automotive applications.
Document reformatted.
Changed Table 6: Power section on page 9 : supply current and static
resistance values.
20-Jun-2007 4
Added Table 7: Logic inputs (INA, INB, ENA, ENB) on page 9 : VDIAG
ROW .
Deleted Enable (Logic I/O pin) Table.
13-Sep-2007 5 Updated Table 2: Block description on page 5.
Corrected Figure 34 note : changed On resistance per leg from 9.5
15-Nov-2007 6
mΩ to 22.5 mΩ .
06-Feb-2008 7 Corrected Heat Slug numbers in Table 3: Pin definitions and functions.

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VNH3SP30-E

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