STBP120

Overvoltage protection device with thermal shutdown

Features
■ Input overvoltage protection up to 28 V
■ Integrated high voltage N-channel MOSFET
switch
■ Low RDS(on) of 90 mΩ
■ Integrated charge pump
■ Thermal shutdown protection
■ Softstart feature to control the inrush current TDFN – 10-lead (2.5 x 2 mm)
■ Enable input (EN)
■ Fault indication output (FLT)
■ IN input ESD withstand voltage up to ±15 kV
(air discharge), up to ±8 kV (contact discharge) Applications
in typical application circuit with 1µF input
■ Smart phones
capacitor (±2 kV HBM for standalone device)
■ Digital cameras
■ Certain overvoltage options compliant with the
China Communications Standard YD/T 1591- ■ PDA and palmtop devices
2006 (overvoltage protection only) ■ MP3 players
■ Small, RoHS compliant 2.5 x 2 mm TDFN – ■ Low-power handheld devices.
10-lead package.

September 2009 Doc ID15492 Rev 5 1/36

www.st.com 1
Contents STBP120

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Input (IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Power output (OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Fault indication output (FLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Enable input (EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 No Connect (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Ground (GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Undervoltage lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Overvoltage lockout (OVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Calculating the power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Calculating the junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8 Typical application performance (STBP120DVDK6F) . . . . . . . . . . . . . 19

9 Typical thermal characteristics (STBP120DVDK6F) . . . . . . . . . . . . . . . 24

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2/36 Doc ID 15492 Rev 5

STBP120 Contents

11 Tape and reel specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

13 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Doc ID 15492 Rev 5 3/36

List of tables STBP120

List of tables

Table 1. Pin description and signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .....8

Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. TDFN – 10-lead, 2.5 x 2.0 x 0.75 mm body, pitch 0.50 mm,
package mechanical data dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. Further tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4/36 Doc ID 15492 Rev 5

STBP120 List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Maximum MOSFET current at TA = 85 °C for various PCB thermal performance
and TJ = 125 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Disable (EN = high). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. FLT behavior in disable (EN = high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Startup delay, ton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. FLT indication delay (OK), tstart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Output turn-off time, toff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. FLT indication delay (FAULT), tstop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Disable time, tdis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Startup to overvoltage and startup VO(FLT) delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Startup inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Output short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18. Output short-circuit detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 19. ICC vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 20. ICC(STDBY) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 21. ICC(UVLO) at 2.9 V vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 22. VOVLO vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 23. VUVLO vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 24. VOL(FLT) at 1 mA vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 25. RDS(on) at 1 A vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 26. TDFN – 10-lead, 2.5 x 2.0 x 0.75 mm body, pitch 0.50 mm,
package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 27. Tape and reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 28. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 29. Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 30. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Doc ID15492 Rev 5 5/36

Description STBP120

1 Description

The STBP120 device provides overvoltage protection for input voltage up to +28 V. Its low
RDS(on) N-channel MOSFET switch protects the systems connected to the OUT pin against
failures of the DC power supplies in accordance with the China MII Communications
Standard YD/T 1591-2006.
In the event of an input overvoltage condition, the device immediately disconnects the DC
power supply by turning off an internal low R DS(on) N-channel MOSFET to prevent damage
to protected systems.
In addition, the device also monitors its own junction temperature and switches off the
internal MOSFET if the junction temperature exceeds the specified limit.
The device can be controlled by the microcontroller and can also provide status information
about fault conditions.
The STBP120 is offered in a small, RoHS-compliant TDFN – 10-lead (2.5 mm x 2 mm)
package.

Figure 1. Logic diagram

IN

OUT
STBP120
EN

FLT

GND
AM00240

Figure 2. Pinout(1)

NC 1 10 EN

PAD1
GND 2 9 NC

FLT 3 8 NC

IN 4 7 OUT
PAD2
IN 5 6 OUT

AM00239

1. Pin 1, PAD1 and PAD2 are No Connect (NC) and may be tied to IN or GND.

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STBP120 Pin descriptions

2 Pin descriptions

2.1 Input (IN)

Input voltage pin. This pin is connected to the DC power supply. External low ESR ceramic
capacitor of minimum value 1 µF must be connected between IN and GND. This capacitor is
for decoupling and also protects the IC against dangerous voltage spikes and ESD events.
This capacitor should be located as close to the IN pins as possible.
All IN pins (4, 5) must be hardwired to common supply.

2.2 Power output (OUT)

Output voltage pin. This pin is connected to the input through a low RDS(on) N-channel
MOSFET switch.
If no fault is detected and the STBP120 is not disabled (controlled by the EN input), this
switch is turned on and the output voltage follows the input voltage.
The output is disconnected from the input when the input voltage is under the UVLO
threshold or above the OVLO threshold, when the chip temperature is above the thermal
shutdown threshold or when the chip is disabled by the EN input.
There is a 50 ms delay, ton, between input voltage or junction temperature returns to
specified range and the power output is connected to the input (see Figure 6).
All OUT pins (6, 7) must be hardwired to common supply.

2.3 Fault indication output (FLT)

The fault indication output (active-low - open-drain) provides information on the STBP120
state to the application controller. When FLT is active (i.e. driven low), this indicates the
STBP120 is in the undervoltage or overvoltage condition or thermal shutdown mode is
active. When the input voltage and junction temperature is in specified range, the FLT output
is in high impedance (Hi-Z) state.
There is an additional 50 ms delay, tstart, between the power output is connected to the input
and the FLT output is deactivated (i.e. in Hi-Z state) (see Figure 6).
Since the FLT output is of open-drain type, it may be pulled up by an external resistor R P to
the controller supply voltage. If there is no need to use this output, it may be left
disconnected. The suitable RP resistor value is in range of 10 kΩ to 1 MΩ .
To improve safety and to prevent damage to application circuits in the event of extreme
voltage or current conditions, an optional protective resistor RFLT can be connected between
the FLT output and the controller input. The suitable RFLT resistor value is in range of 22 kΩ
to 100 kΩ.
The function of the FLT output is not affected by the EN input state (see Figure 9).

Doc ID 15492 Rev 5 7/36

Pin descriptions STBP120

2.4 Enable input (EN)

This logical input (active-low) can be used to enable or disable the device. When EN input is
driven high, the STBP120 enters the standby mode and the power output is disconnected
from the input. When EN input is driven low and all operating conditions are within specified
limits, the power output is connected to the input.
Since the EN input has no internal pull-down resistor, its logical level must be defined by the
controller or by an external resistor. If there is no need to use this input, it should be
connected to the GND.
To improve safety and to prevent damage to application circuits in the event of extreme
voltage or current conditions, an optional protective resistor REN can be connected between
the EN input and the controller output. The suitable resistor value is in range of 22 kΩ to
100 kΩ .
The EN input level has no impact on the functionality of FLT output (see Figure 8 and
Figure 9).

2.5 No Connect (NC)

Pins 1, 8, 9 and exposed pads PAD1, PAD2 are No Connect. Pin 1 and exposed pads PAD1,
PAD2 may be tied to IN or GND if necessary.

2.6 Ground (GND)

Ground. All voltages are referenced to GND.

Table 1. Pin description and signal names

Pin Name Type Function

1, PAD1, PAD2 NC — No Connect. May be tied to IN or GND.

2 GND Supply Ground
3 FLT Output Fault indication output (open-drain)
4, 5 IN Input / supply Input voltage
6, 7 OUT Output Output voltage
8, 9 NC — No Connect
10 EN Input Enable input (no internal pull-down resistor)

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STBP120 Pin descriptions

Figure 3. Block diagram

IN OUT

ESD Core SUPPLY CHARGE PUMP

negative OSCILLATOR OFF
protection protection REGULATOR MOSFET DRIVER

VCC

VREF
VOLTAGE
COUNTERS
REFERENCE

Input overvoltage
FLT
CONTROL LOGIC MCU
INTERFACE
Input undervoltage
EN

Temperature Thermal shutdown

detector ESD ESD
protection protection

GND
AM00306

Figure 4. Typical application circuit(1),(2)

PERIPHERAL
SUPPLY CURRENT DC-DC
SYSTEM
AC CONNECTOR CHARGING CURRENT
EN
adapter BATTERY
IN OUT PACK
OR C1 CHARGER SUPPLY
C2 IC CIRCUITS
1 µF STBP120 1 µF
ENABLE RPU

POWERED
RFLT
PERIPHERALS
FLT CONTROLLER

EN REN
GND
APPLICATION

AM00314a

1. Optional resistors REN, RFLT prevent damage to the controller under extreme voltage or current conditions and are not
required. Low ESR ceramic capacitor C1 is necessary to ensure proper function of the STBP120. Capacitor C2 is not
necessary for STBP120 but may be required by the charger IC.
2. The STBP120 MOSFET switch topology allows the current to also flow in the reverse direction, from OUT to IN, which can
be useful for powering external peripherals from the system connector. The charger IC should not contain the reverse
diode to prevent the battery pack voltage from appearing on the system connector. If the reverse current (supply current) is
undesirable, it may be prevented by connecting a Schottky diode in series with the OUT pin. The voltage drop between IN
and charger is increased by the voltage drop across the diode.

Doc ID 15492 Rev 5 9/36

Operation STBP120

3 Operation

The STBP120 provides overvoltage protection for positive input voltage up to 28 V using
a built-in low RDS(on) N-channel MOSFET switch.

3.1 Power-up
At power-up, with EN = low, the MOSFET switch is turned on after a 50 ms delay, ton, after
the input voltage exceeds the UVLO threshold to ensure the input voltage is stabilized. After
an additional 50 ms delay, tstart, the FLT indication output is deactivated (see Figure 6).
The FLT output state is valid for VIN input voltage 1.2 V or higher.

3.2 Normal operation

The device continuously monitors the input voltage and its own internal temperature so the
output voltage is kept within the specified range. Internal MOSFET switch is turned on and
the FLT output is not active.
The STBP120 enters normal operation state if the input voltage returns to the interval
between VUVLO and VOVLO - VHYS(OVLO) and the junction temperature falls below TOFF -
THYS(OFF). Internal MOSFET is turned on after the 50 ms delay ton to ensure that the
conditions have stabilized. Then, after an additional 50 ms delay, tstart, the FLT output is
deactivated (i.e. driven high). This behavior is equivalent to the startup shown on Figure 6.
Note: The STBP120 MOSFET switch topology allows the current to also flow in the reverse
direction, i.e. from OUT to IN, which can be useful e.g. for powering external peripherals
from the system connector (see the supply current in Figure 4). At first, the current flows
through the MOSFET body diode. If the voltage that appears on the IN terminal is above the
UVLO threshold, the MOSFET is (after the 50 ms startup delay) turned on so the voltage
drop across STBP120 is significantly reduced. The charger IC should not contain the
reverse diode to prevent the battery pack voltage from appearing on the system connector.
If the reverse current is undesirable, it may be prevented by connecting a properly rated low
drop Schottky diode in series with the OUT pin. The voltage drop between IN and charger is
increased by the voltage drop across the diode.
Due to the MOSFET body diode, thermal shutdown protection is not functional for the
supply current.

3.3 Undervoltage lockout (UVLO)

To ensure proper operation under any conditions, the STBP120 has an undervoltage lockout
(UVLO) threshold. For rising input voltage, the output remains disconnected from input until
VIN voltage exceeds the VUVLO threshold (3.25 V typ). The FLT output is driven low as long
as VIN is below the UVLO threshold (assuming the input voltage is above 1.2 V). For falling
input voltage, the UVLO circuit has a 50 mV hysteresis, VHYS(UVLO), to improve noise
immunity under transient conditions.

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STBP120 Operation

3.4 Overvoltage lockout (OVLO)

If the input voltage VIN rises above the threshold level VOVLO, the MOSFET switch is
immediately turned off (see Figure 7). At the same time, the fault indication output FLT is
activated (i.e. driven low). This device is equipped with hysteresis, VHYS(OVLO), to improve
noise immunity under transient conditions.
For available OVLO thresholds and hystereses, please see the Table 5.

3.5 Thermal shutdown

If the STBP120 internal junction temperature exceeds the TOFF threshold, internal MOSFET
switch is turned off and the fault indication output FLT is driven low.
To improve thermal stability, this circuit has a 20 °C hysteresis, THYS(OFF).

Doc ID 15492 Rev 5 11/36

Application information STBP120

4 Application information

4.1 Calculating the power dissipation

The maximum power dissipation of the STBP120 internal power MOSFET can be calculated
using following formula:
PD = I2 x RDS(on)(max),
Where I is current flowing through the MOSFET and RDS(on)(max) is maximum value of
MOSFET resistance.
Example:
Rload = 5 Ω, VIN = 5 V, R DS(on)(max) = 150 mΩ
I = VIN / (RDS(on)(max) + R load) = 5 / (5 + 0.150) = 0.97 A
PD = 0.972 x 0.15 = 0.14 W
The power dissipation of reverse diode (in powering peripherals mode) can be estimated as
PD = (VOUT - VIN) x I ≈ 0.7 x I.

4.2 Calculating the junction temperature

The maximum junction temperature for given power dissipation, ambient temperature and
thermal resistance junction - to - ambient can be calculated as
TJ = TA + 1.15 x PD x RthJA = TA + 1.15 x I2 x RDS(on)(max) x RthJA,
where TJ is junction temperature, TA is given ambient temperature, 1.15 is a derating factor
and RthJA is thermal resistance junction - to - ambient, depending on shape, dimension and
design of PCB. Two examples of PCB with appropriate thermal resistance are listed in
Table 3. The junction temperature may not exceed 125 °C (see Table 4), due to TOFF
(thermal shutdown threshold temperature).
Maximum allowed MOSFET current for ambient temperature TA = 85 °C and various RthJA
values are listed in Figure 5.
Example: For conditions listed in previous example, well designed PCB (RthJA = 82 °C/W)
and TA = 85 °C, the maximum junction temperature is
85 + 1.15 x 0.14 x 82 = 98.2 °C.

4.3 PCB layout recommendations

● This device is intended as a protection device to the application from overvoltage.
It must be ensured that the clearances between PCB tracks satisfy the high voltage
design rules.
● Input capacitor, C1, should be located as close as possible to the STBP120 device.
It should be a Low-ESR ceramic capacitor. Also the protective resistors RFLT, REN
(if used) should be located close to the STBP120.
● For good thermal performance, it is recommended to connect the STBP120 exposed
thermal pads with the PCB ground plane. In most designs, this requires thermal vias
between the copper pads on PCB and the ground plane.

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STBP120 Maximum rating

5 Maximum rating

Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

TSTG Storage temperature (VIN off) –55 to 150 C

TSLD(1) Lead solder temperature for 10 seconds 260 C
TJ (2) Operating junction temperature range –40 to 150 C
TA Operating ambient temperature range –40 to 85 C
VIN Input voltage (pins IN) –0.3 to 30 V
VIO(OUT) Input / output voltage (pins OUT) –0.3 to 12 V
VIO Input / output voltage (other pins) –0.3 to 7 V
IIN,
Input / output current through MOSFET (pins IN, OUT) 2000 mA
IOUT(MOSFET)
I(FLT) Output current (pin FLT) 15 mA
±15 (air),
ESD withstand voltage (IEC 61000-4-2, pins IN only)(3) kV
±8 (contact)
VESD
Human body model (HBM), Model = 2(4) 2000 V
Machine model (MM), Model = B(5) 200 V
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
2. Maximum junction temperature is internally limited by the thermal shutdown circuit (not valid for reverse
current, see Chapter 3.2).
3. System-level value (see Figure 4, C1 ≥ 1 µF low ESR ceramic capacitor).
4. Human body model, 100 pF discharged through a 1.5kΩ resistor according the JESD22/A114
specification.
5. Machine model, 200 pF discharged through all pins according the JESD22/A115 specification.

Doc ID 15492 Rev 5 13/36

Maximum rating STBP120

Table 3. Thermal data

Symbol Parameter Value Unit

204(1)
RthJA Thermal resistance (junction to ambient) °C/W
82(2)
RthJC Thermal resistance (junction to case) 43 °C/W
1. The package is mounted on a 2-layers (1S) JEDEC board as per JESD51-7 without thermal vias
underneath the exposed pads.
2. The package is mounted on a 4-layers (2S2P) JEDEC board as per JESD51-7 with 2 thermal vias (one
underneath each exposed pad) as per JESD-51-5. Thermal vias connected from exposed pad to 1'st
buried copper plane of PCB.

Figure 5. Maximum MOSFET current at TA = 85 °C for various PCB thermal

performance and TJ = 125 °C
2.10

1.90

1.70

I (MOSFET) 1.50
[A] 1.30

1.10

0.90

0.70
50 100 150 200 250 300 350

Rth JA [˚C/W]
AM00428b

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STBP120 DC and AC parameters

6 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow are derived from tests performed under the measurement conditions summarized in
Table 4. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.

Table 4. Operating and AC measurement conditions

Parameter Value Unit

Input voltage (VIN) 5 V

Ambient operating temperature (TA) –40 to 85 °C
Junction operating temperature (TJ) –40 to 125 °C
Output load resistance (Rload) 5 Ω

Table 5. DC and AC characteristics

Symbol Description Test condition(1) Min Typ Max Unit

VIN Input voltage range 1.2 28 V

Input undervoltage
VUVLO 3.1 3.25 3.4 V
lockout threshold
Undervoltage lockout
VHYS(UVLO) 20 50 100 mV
hysteresis
VIN rises up OVLO threshold, OVLO option A 5.25 5.375 5.50

Overvoltage lockout VIN rises up OVLO threshold, OVLO option B 5.30 5.50 5.70
VOVLO V
threshold VIN rises up OVLO threshold, OVLO option C 5.71 5.90 6.10
VIN rises up OVLO threshold, OVLO option D 5.70 6.02 6.40
Input overvoltage
VHYS(OVLO) 30 60 90 mV
hysteresis
RDS(on) IN to OUT resistance EN = 0 V, VIN = 5 V, Rload connected to OUT 90 150 mΩ
ICC Operating current EN = 0 V, no load on OUT, VIN = 5 V 170 250 µA
ICC(STDBY) Standby current EN = 5 V, no load on OUT, VIN = 5 V 96 150 µA
ICC(UVLO) UVLO operating current VIN = 2.9 V 70 100 µA

FLT output low level 1.2 V < VIN < VUVLO, ISINK(FLT) = 50 µA 20 400 mV
VOL(FLT)
voltage VIN > VOVLO, ISINK(FLT) = 1 mA 400 mV
FLT output leakage
IL(FLT) V(FLT) = 5 V 5 nA
current
EN low level input
VIL(EN) 0.4 V
voltage
EN high level input
VIH(EN) 1.2 V
voltage
EN input leakage
IL(EN) V(EN) = 0 V or 5 V 5 nA
current

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DC and AC parameters STBP120

Table 5. DC and AC characteristics (continued)

Symbol Description Test condition(1) Min Typ Max Unit

Timing parameters
Time measured from VIN > VUVLO
ton Startup delay 30 50 70 ms
to VOUT = 0.3 V (see Figure 6)
FLT indication delay Time measured from VOUT = 0.3 V
tstart 30 50 70 ms
(OK) to V(FLT) = 1.2 V (see Figure 6)
Time measured from VIN > VOVLO to VOUT ≤ 0.3 V.
toff(2) Output turn-off time VIN increasing from 5.0 V to 8.0 V at 3.0 V/µs, 1.5 5 µs
Rload connected to OUT. (see Figure 7)
Time measured from VIN > VOVLO to V(FLT) ≤ 0.4 V.
FLT indication delay
tstop(2) VIN increasing from 5.0 V to 8.0 V at 3.0 V/µs, 1 µs
(FAULT)
Rload connected to OUT. (see Figure 7)
Time measured from V(EN) ≥ 1.2 V
tdis(2) Disable time to VOUT < 0.3 V. Rload connected to OUT. 1 5 µs
(see Figure 8)
Thermal shutdown
Thermal shutdown
TOFF 130 145 °C
threshold temperature
Thermal shutdown
THYS(OFF) 20 °C
hysteresis
1. Test conditions described in Table 4 (except where noted).
2. Guaranteed by design. Not tested in production.

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STBP120 Timing diagrams

7 Timing diagrams

Figure 6. Startup(1)

OVLO
UVLO
VIN

0.3 V ton
VOUT
tstart
1.2 V
V(FLT)
AM00335

1. EN input is low.

Figure 7. Overvoltage protection(1)

OVLO

UVLO
VIN
toff

0.3 V
VOUT
tstop

0.4 V
V(FLT)
AM00336

1. EN input is low.

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Timing diagrams STBP120

Figure 8. Disable (EN = high)(1)

1.2 V
V(EN)

OVLO

UVLO
VIN

tdis

0.3 V
VOUT
AM00337

1. FLT output still indicates the VIN status.

Figure 9. FLT behavior in disable (EN = high)

1.2 V
V(EN)

OVLO

UVLO
VIN
equiv. to ton + tstart

1.2 V
VFLT
AM00338

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STBP120 Typical application performance (STBP120DVDK6F)

8 Typical application performance (STBP120DVDK6F)

Figure 10. Startup delay, ton

1. No load on the output. The “leakage” on the VOUT trace is a crosstalk caused mainly by the parasitic
capacitances of the MOSFET switch.

Figure 11. FLT indication delay (OK), tstart

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Typical application performance (STBP120DVDK6F) STBP120

Figure 12. Output turn-off time, toff

1. 5 Ω load on the output.

Figure 13. FLT indication delay (FAULT), tstop

1. 5 Ω load on the output.

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STBP120 Typical application performance (STBP120DVDK6F)

Figure 14. Disable time, tdis

1. No change in VO(FLT) status during disable.

2. 5 Ω load on the output.

Figure 15. Startup to overvoltage and startup VO(FLT) delay

1. 5 Ω load on the output.

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Typical application performance (STBP120DVDK6F) STBP120

Figure 16. Startup inrush current

1. Output load 5 Ω in parallel with C = 100 µF, power supply cable inductance 1 µH, power supply cable
resistance 0.3 Ω.

Figure 17. Output short-circuit

1. See also details on Figure 18.

2. Power supply cable inductance 1 µH, power supply cable resistance 0.3 Ω.

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STBP120 Typical application performance (STBP120DVDK6F)

Figure 18. Output short-circuit detail

1. Due to power supply cable impedance, during the output short-circuit the input voltage falls below the
VUVLO threshold, resulting in turning off the power MOSFET and preventing any damage to the
components.
2. Power supply cable inductance 1 µH, power supply cable resistance 0.3 Ω.

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Typical thermal characteristics (STBP120DVDK6F) STBP120

9 Typical thermal characteristics (STBP120DVDK6F)

Figure 19. ICC vs. temperature

180

170
160

150
140
ICC [µA]
130

120
110

100
90

80
–50 0 50 100 150
Temperature [˚C]
AM00415

Figure 20. ICC(STDBY) vs. temperature

120

110

100

90
ICC(STDBY)
[µA] 80

70

60

50

40
–50 0 50 100 150
Temperature [˚C]
AM00416

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STBP120 Typical thermal characteristics (STBP120DVDK6F)

Figure 21. ICC(UVLO) at 2.9 V vs. temperature

80.0

70.0

60.0
ICC(UVLO)
[µA] 50.0

40.0

30.0

20.0
–50 0 50 100 150
Temperature [˚C]
AM00417

Figure 22. VOVLO vs. temperature

6.3

6.2

6.1
VOVLO [V]

5.9

5.8
–50 0 50 100 150
Temperature [˚C]
AM00420

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Typical thermal characteristics (STBP120DVDK6F) STBP120

Figure 23. VUVLO vs. temperature

3.4

3.35

3.3
VUVLO [V]
3.25

3.2

3.15

3.1
–50 0 50 100 150
Temperature [˚C]
AM00422

Figure 24. VOL(FLT) at 1 mA vs. temperature

0.1

0.09

0.08

0.07
VOL(FLT)
[V] 0.06

0.05
0.04

0.03

0.02

0.01

0
–50 0 50 100 150
Temperature [˚C]
AM00424

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STBP120 Typical thermal characteristics (STBP120DVDK6F)

Figure 25. RDS(on) at 1 A vs. temperature

140.0

120.0

100.0

80.0
RDS(on)
[mΩ] 60.0

40.0

20.0

0.0
–50 0 50 100 150
Temperature [˚C]
AM00427

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Package mechanical data STBP120

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 26. TDFN – 10-lead, 2.5 x 2.0 x 0.75 mm body, pitch 0.50 mm,
package mechanical drawing

D
A
B

INDE X AREA

0.10 C 2x

0.10 C 2x

TOP VIEW
0.10 C
A1 C
A
SEATING
PLANE
SIDE VIEW
0.08 C
D2 -2
LEADS COPLA NARITY e

1 5
PI N#1 ID

K (x10)

0.350
INDEX AR EA
E2
0.195 0.195

L
(x10)

b (x 10) 10 0.02 5 D2- 1

0.10 C A B
BOTTOM VIEW
10L_ME

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STBP120 Package mechanical data

Table 6. TDFN – 10-lead, 2.5 x 2.0 x 0.75 mm body, pitch 0.50 mm,
package mechanical data dimensions(1)
(mm) (inches)
Symbol Note
Min. Nom. Max. Min. Nom. Max.

A 0.70 0.75 0.80 0.028 0.030 0.031

A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.18 0.25 0.30 0.007 0.010 0.012
D
2.50 0.098
BSC
D2-1 0.53 0.68 0.78 0.021 0.027 0.031
D2-2 0.93 1.08 1.18 0.037 0.043 0.046
E
2.00 0.079
BSC
E2 0.75 0.90 1.00 0.030 0.035 0.039
e 0.50 0.020
L 0.20 0.30 0.40 0.008 0.012 0.016
K 0.20 0.008
N 10 10 (2)

1. Controlling dimension: millimeters.

2. N is the total number of terminals.

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Tape and reel specification STBP120

11 Tape and reel specification

Figure 27. Tape and reel

P0

D P2
T
E

A0
F
Top cover
tape W
B0

K0 Center lines
of cavity P1

User direction of feed

AM03073v2

Table 7. Carrier tape dimensions

Tape
W D E Po P2 F
size

12 12.00 ± 0.30 1.50 +0.10 / –0.00 1.75 ± 0.10 4.00 ± 0.10 2.00 ± 0.10 5.50 ± 0.05

Table 8. Further tape and reel information

Reel
Package code W Ao Bo Ko P1 T Bulk Qty.
Diameter

2.30 ± 2.80 ± 1.10 ± 4.00 ± 0.30 ±

2 x 2.5mm TDFN 10 lead 12 3000 13
0.10 0.10 0.01 0.10 0.05

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STBP120 Tape and reel specification

Figure 28. Reel dimensions

40 mm min.
acces hole
at slot location

D C
N
A

Full radius

Tape slot
in core for
tape start
25 mm min width
G measured
at hub

AM00443

Table 9. Reel dimensions

Tape size A max. B min. C D min. N min. G T max.

12 mm 330 (13 inch) 1.5 13 ± 0.2 20.2 60 12.4 + 2 / – 0 18.4

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Tape and reel specification STBP120

Figure 29. Tape trailer/leader

End Start

Top No components Components 100 mm min. No components

cover
tape T RA IL ER L EA D ER
160 mm min. 400 mm min.

Sealed with cover tape

User direction of feed

AM00444

Figure 30. Pin 1 orientation

Direction of feed
AM00442a

Note: 1 Drawings are not to scale.

2 All dimensions are in mm, unless otherwise noted.

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STBP120 Part numbering

12 Part numbering

Table 10. Ordering information scheme

STBP120 D V DK 6 F

Device type
STBP120

Overvoltage threshold
A = 5.375 V
B = 5.50 V
C = 5.90 V
D = 6.02 V

Undervoltage threshold
V = 3.25 V

Package
DK = TDFN – 10-lead, 2.5 x 2 mm

Temperature range
6 = –40 °C to +85 °C

Shipping method
F = ECOPACK® package, tape and reel

Note: Other overvoltage thresholds are offered. Minimum order quantities may apply.
Contact local sales office for availability.

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Package marking information STBP120

13 Package marking information

Table 11. Marking description

Part number(1) Overvoltage threshold (V) Topside marking

STBP120AVxxxx 5.375 P12A

STBP120BVxxxx 5.50 P12B
STBP120CVxxxx 5.90 P12C
STBP120DVxxxx 6.02 P12D
1. Other overvoltage thresholds are offered. Minimum order quantities may apply.
Contact local sales office for availability.

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STBP120 Revision history

14 Revision history

Table 12. Document revision history

Date Revision Changes

20-Mar-2009 1 Initial release.

Updated Section 2, Section 3, Figure 5, ton and tstart in Table 5 and
07-Apr-2009 2
shipping method in Table 10, added Section 8 and Section 9.
29-Apr- 2009 3 Updated the revision history table - removed the draft revisions.
Updated Features, Section 4.3, Table 2, Figure 5, Table 5, Figure 10,
Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17,
01-Jun-2009 4
Figure 18, removed Figure 22, Figure 23, Figure 25, Figure 27,
Figure 29, Figure 30, added Section 11: Tape and reel specification.
Document reformatted, updated overvoltage threshold option C in
25-Sep-2009 5
Table 5, Table 10 and Table 11.

Doc ID 15492 Rev 5 35/36

 STBP120

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