ST1S40

3 A DC step-down switching regulator

Datasheet - production data

Applications
• µP/ASIC/DSP/FPGA core and I/O supplies
• Point of load for: STB, TVs, DVD
HSOP-8 SO8 • Optical storage, hard disk drive, printers,
VFQFPN 4 x 4 audio/graphic cards

Description
Features
The ST1S40 device is an internally compensated
• 3 A DC output current 850 kHz fixed-frequency PWM synchronous step-
down regulator. The ST1S40 operates from 4.0 V
• 4.0 V to 18 V input voltage
to 18 V input, while it regulates an output voltage
• Output voltage adjustable from 0.8 V as low as 0.8 V and up to VIN.
• 850 kHz switching frequency The ST1S40 integrates a 95 mΩ high side switch
• Internal soft-start and 69 mΩ synchronous rectifier allowing very
• Integrated 95 mΩ and 69 mΩ Power MOSFETs high efficiency with very low output voltages.
• All ceramic capacitor The peak current mode control with internal
compensation delivers a very compact solution
• Enable
with a minimum component count.
• Cycle-by-cycle current limiting
The ST1S40 is available in HSOP-8, VFQFPN 4
• Current fold back short-circuit protection mm x 4 mm - 8 lead, and standard SO8 package.
• Available in HSOP-8, VFQFPN4x4-8L, and
SO8 packages

Figure 1. Application circuit

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September 2023 DocID17928 Rev 7 1/31

This is information on a product in full production. www.st.com
Contents ST1S40

Contents

1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1 Internal soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 Error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.3 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.4 Thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.5 Layout consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7 Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31 DocID17928 Rev 7

ST1S40 Pin settings

1 Pin settings

1.1 Pin connection

Figure 2. Pin connection (top view)

1 8
VINA 1 8 PGND VINA 1 8 PGND SW VINSW

EN 2 7 SW EN 2 7 SW PGND GND
9 9
FB 3 6 VINSW FB 3 6 VINSW VINA AGND

GND 4 5 NC GND 4 5 NC EN FB
4 5

VFQFPN HSOP-8
HSOP8 SO8-BW

1.2 Pin description

Table 1. Pin description
N°
Type Description
VFQFPN
S08-BW
and HSOP-8

1 3 VINA Unregulated DC input voltage

Enable input. With EN higher than 1.2 V the device in ON and with EN lower
2 4 EN
than 0.4 V the device is OFF (ST1S40Ixx).
Feedback input. Connecting the output voltage directly to this pin the output
3 5 FB voltage is regulated at 0.8 V. To have higher regulated voltages an external
resistor divider is required from Vout to the FB pin.
4 6 AGND Ground
5 - NC It can be connected to ground
6 8 VINSW Power input voltage
7 1 SW Regulator output switching pin
8 2 PGND Power ground
- 7 Ground
9 - ePad Exposed pad mandatory connected to ground

DocID17928 Rev 7 3/31

31
Maximum ratings ST1S40

2 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

VINSW Power input voltage -0.3 to 20

VINA Input voltage -0.3 to 20
VEN Enable voltage -0.3 to VINA
V
-1 to VIN
VSW Output switching voltage
-2 V to -1 V for 50 nsec
VFB Feedback voltage -0.3 to 2.5
IFB FB current -1 to +1 mA
2.25 (HSOP-8/DFN4x4);
PTOT Power dissipation at TA < 60 °C W
1.6 SO8
TOP Operating junction temperature range -40 to 150 °C
Tstg Storage temperature range -55 to 150 °C

3 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

VFQFPN 40
RthJA Maximum thermal resistance junction-ambient(1) HSOP-8 40 °C/W
SO8 55
1. Package mounted on the demonstration board.

4/31 DocID17928 Rev 7

ST1S40 Electrical characteristics

4 Electrical characteristics

TJ = 25 °C, VCC= 12 V, unless otherwise specified.

Table 4. Electrical characteristics

Values
Symbol Parameter Test condition Unit
Min. Typ. Max.

Operating input voltage (1)

VIN 4 18
range
(1) V
VINON Turn-on VCC threshold 2.9
(1)
VINHYS Threshold hysteresis 0.250
High side switch ON
RDSON-P ISW = 750 mA mΩ
resistance 95
Low side switch ON
RDSON-N ISW = 750 mA 69 mΩ
resistance
ILIM Maximum limiting current (2) 4.0 6.0 A

Oscillator

FSW Switching frequency 0.7 0.85 1 MHz

(2)
DMAX Maximum duty cycle 100 %

Dynamic characteristics

0.784 0.8 0.816

VFB Feedback voltage V
(1)
0.776 0.8 0.824
%VOUT/ Reference load
Isw = 10 mA to ILIM(2) 0.5 %
∆IOUT regulation
%VOUT/
Reference line regulation VIN = 4.0 V to 18 V(2) 0.4 %
∆VIN

DC characteristics

Duty cycle = 0, no load

IQ Quiescent current 1.5 2.5 mA
VFB = 1.2 V
Total standby quiescent
IQST-BY OFF 2 15 µA
current
IFB FB bias current 50

Enable

Device ON level 1.2

VEN EN threshold voltage V
Device OFF level 0.4
IEN EN current 2 µA

DocID17928 Rev 7 5/31

31
Electrical characteristics ST1S40

Table 4. Electrical characteristics (continued)

Values
Symbol Parameter Test condition Unit
Min. Typ. Max.

Soft start

TSS Soft-start duration 1 ms

Protection

Thermal shutdown 150

TSHDN °C
Hysteresis 15
1. Specification referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are
assured by design, characterization and statistical correlation.
2. Guaranteed by design.

6/31 DocID17928 Rev 7

ST1S40 Functional description

5 Functional description

The ST1S40 device is based on a “peak current mode”, constant frequency control. The
output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference
(0.8 V) providing an error signal that, compared to the output of the current sense amplifier,
controls the ON and OFF time of the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
• A fully integrated oscillator that provides the internal clock and the ramp for the slope
compensation avoiding sub-harmonic instability
• The soft-start circuitry to limit inrush current during the startup phase
• The transconductance error amplifier with integrated compensation network
• The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switches
• The drivers for embedded P-channel and N-channel Power MOSFET switches
• The high side current sensing block
• The low side current sense to implement diode emulation
• A voltage monitor circuitry (UVLO) that checks the input and internal voltages
• A thermal shutdown block, to prevent thermal run-away.

Figure 3. Block diagram

VINA VINSW
OCP
OSC REF
I2V
I_SENSE RSENSE

COMP
REGULATOR

UVLO

OCP Vdrv_p
DRIVER
MOSFET
Vsum CONTROL
LOGIC
COMP Vdrv_n
Vc

SW

OTP DMD
E/A

SHUT-DOWN DRIVER
SOFTSTART

0.8V

FB EN GNDA GNDP

DocID17928 Rev 7 7/31

31
Functional description ST1S40

5.1 Internal soft-start

The soft-start is essential to assure correct and safe startup of the step-down converter. It
avoids inrush current surge and causes the output voltage to increase monothonically.
The soft-start is performed by ramping the non-inverting input (VREF) of the error amplifier
from 0 V to 0.8 V in around 1 ms.

5.2 Error amplifier and control loop stability

The error amplifier compares the FB pin voltage with the internal 0.8 V reference and it
provides the error signal to be compared with the output of the current sense circuitry, that is
the high side Power MOSFET current. Comparing the output of the error amplifier and the
peak inductor current implements the peak current mode control loop.
The error amplifier is a transconductance amplifier (OTA). The uncompensated
characteristics are listed in

Table 5. Error amplifier characteristics

Parameter Value

DC Gain 95 dB
Gm 251 µA/V
Ro 240 MΩ

The ST1S40 device embeds the compensation network that assures the stability of the loop
in the whole operating range. All the tools needed to check the loop stability are shown
below.

8/31 DocID17928 Rev 7

ST1S40 Functional description

Figure 4 shows the simple small signal model for the peak current mode control loop.

Figure 4. Block diagram of the loop for the small signal analysis

VIN

Slope GCO(s)
Compensation
High side
Switch

L GDIV (s)
Current sense VOUT
Logic Cout
And Low side
Driver Switch
PWM comparator

0.8V

R1
VC
VFB
Rc Error Amp
R2
Cc

G EA(s)

Three main terms can be identified to obtain the loop transfer function:
1. from control (output of E/A) to output, GCO(s)
2. from output (Vout) to the FB pin, GDIV(s)
3. from the FB pin to control (output of E/A), GEA(s).
The transfer function from control to output GCO(s) results:

Equation 1
 1 + ----- s
 -
R LOAD 1 ω z
G CO ( s ) = ------------------ ⋅ --------------------------------------------------------------------------------------------- ⋅ ---------------------- ⋅ F H ( s )
Ri R out ⋅ T SW  s
1 + ---------------------------- ⋅ [ m C ⋅ ( 1 – D ) – 0.5 ]  1 + ω ------
L p


where RLOAD represents the load resistance, Ri (0.3 Ω) the equivalent sensing resistor of
the current sense circuitry, ωp the single pole introduced by the LC filter and ωz the zero
given by the ESR of the output capacitor.
FH(s) accounts for the sampling effect performed by the PWM comparator on the output of
the error amplifier that introduces a double pole at one half of the switching frequency.

Equation 2
1
ω Z = -------------------------------
ESR ⋅ C OUT

DocID17928 Rev 7 9/31

31
Functional description ST1S40

Equation 3
1 m C ⋅ ( 1 – D ) – 0.5
ω p = -------------------------------------- + ---------------------------------------------
R LOAD ⋅ C OUT L ⋅ C OUT ⋅ fSW

where:

Equation 4

 Se
 m C = 1 + ------
Sn

S = V ⋅ f
 e pp SW
 V IN – V OUT
 S = -----------------------------
 n - ⋅ Ri
L

Sn represents the ON time slope of the sensed inductor current, Se the slope of the external
ramp (VPP peak-to-peak amplitude 1.25 V) that implements the slope compensation to
avoid sub-harmonic oscillations at duty cycle over 50%.
The sampling effect contribution FH(s) is:

Equation 5
1
F H ( s ) = ------------------------------------------
2
-
s s
1 + ------------------- + ------2
ωn ⋅ QP ω
n

where:

Equation 6
1
Q P = ----------------------------------------------------------
π ⋅ [ m C ⋅ ( 1 – D ) – 0.5 ]

and

Equation 7

ω n = π ⋅ fSW

The resistor to adjust the output voltage gives the term from output voltage to the FB pin.
GDIV(s) is:

R2
G DIV ( s ) = --------------------
R1 + R2

The transfer function from FB to Vcc (output of E/A) introduces the singularities (poles and
zeros) to stabilize the loop. Figure 5 shows the small signal model of the error amplifier with
the internal compensation network.

10/31 DocID17928 Rev 7

ST1S40 Functional description

Figure 5. Small signal model for the error amplifier

9 )%

9G 5R &R 5F &S
*P 9G
95() &F

RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect
system stability and can be neglected.
So GEA(s) results:

Equation 8
G EA0 ⋅ ( 1 + s ⋅ R c ⋅ C c )
G EA ( s ) = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2
-
s ⋅ R 0 ⋅ ( C 0 + C p ) ⋅ R c ⋅ C c + s ⋅ ( R0 ⋅ C c + R 0 ⋅ ( C 0 + C p ) + R c ⋅ C c ) + 1

where GEA= Gm · Ro
The poles of this transfer function are (if Cc >> C0+CP):

Equation 9
1
f P LF = ----------------------------------
2 ⋅ π ⋅ R0 ⋅ Cc

Equation 10

1
fP HF = ----------------------------------------------------
2 ⋅ π ⋅ Rc ⋅ ( C0 + Cp )

whereas the zero is defined as:

Equation 11
1
fZ = ---------------------------------
2 ⋅ π ⋅ Rc ⋅ Cc

The embedded compensation network is RC = 70 kΩ, CC = 195 pF while CP and CO can be

considered as negligible. The error amplifier output resistance is 240 MΩ so the relevant
singularities are:

Equation 12

f Z = 11, 6 kHz fP LF = 3, 4 Hz

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31
Functional description ST1S40

so by closing the loop, the loop gain GLOOP(s) is:

Equation 13

G LOOP ( s ) = G CO ( s ) ⋅ G DIV ( s ) ⋅ G EA ( s )

Example:
VIN = 12 V, VOUT = 1.2 V, Iomax = 3 A, L = 1.5 µH, Cout = 47 µF (MLCC), R1 = 10 kΩ,
R2 = 20 kΩ (see Section 6.2 and Section 6.3 for inductor and output capacitor selection
guidelines).
The module and phase Bode plot are reported in Figure 6.
The bandwidth is 100 kHz and the phase margin is 45 degrees.

Figure 6. Module and phase Bode plot

12/31 DocID17928 Rev 7

ST1S40 Functional description

5.3 Overcurrent protection

The ST1S40 device implements the pulse-by-pulse overcurrent protection. The peak
current is sensed through the high side Power MOSFET and when it exceeds the first
overcurrent threshold (OCP1) the high side is immediately turned off and the low side
conducts the inductor current for the rest of the clock period.
During overload condition, since the duty cycle is not set by the control loop but is limited by
the overcurrent threshold, the output voltage drops out of regulation. If the feedback falls
below 0.3 V the switching frequency is reduced to one fourth and the current limit threshold
is folded back to around 2 A. Thanks to the current and frequency fold back the stress on
the device and on the external power components is reduced in case of severe overload or
dead-short to ground of the output.
The current fold back is disabled during the startup, in order to allow the Vout to rise up
properly in case of the big output capacitor requiring high extra current to be charged.
An additional mechanism is protecting the device in case of short-circuit on the output and
high input voltage. A further threshold (OCP2, 1A higher than OCP1) is compared to the
inductor current. If the inductor current exceeds OCP2, the device stops switching and
restarts with a soft-start cycle.

5.4 Enable function

The enable feature allows the device to be put into standby mode. With the EN pin lower
than 0.4 V, the device is disabled and the power consumption is reduced to less than 15 µA.
With the EN pin higher than 1.2 V, the device is enabled. High level signal enables the
device. An external 100 k pull-down resistor is suggested to ensure device disabled when
the pin is left floating. Connect to VIN if not used.

5.5 Hysteretic thermal shutdown

The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C,
the device restarts in normal operation.

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31
Application information ST1S40

6 Application information

6.1 Input capacitor selection

The capacitor connected to the input must be capable of supporting the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:

Equation 14
2 2
2⋅D D
I RMS = I O ⋅ D – --------------- + ------2-
η η

where Io is the maximum DC output current, D is the duty cycle, η is the efficiency.
Considering η = 1, this function has a maximum at D = 0.5 and is equal to Io/2.
The peak-to-peak voltage across the input capacitor can be calculated as:

Equation 15
IO D D
V PP = ------------------------- ⋅  1 – ---- ⋅ D + ---- ⋅ ( 1 – D ) + ESR ⋅ I O
C IN ⋅ F SW  η η

where ESR is the equivalent series resistance of the capacitor.

Given the physical dimension, ceramic capacitors can well meet the requirements of the
input filter sustaining a higher input RMS current than electrolytic / tantalum types. In this
case the equation of CIN as a function of the target peak-to-peak voltage ripple (VPP) can be
written as follows:

Equation 16
IO D D
C IN = --------------------------- ⋅  1 – ---- ⋅ D + ---- ⋅ ( 1 – D )
V PP ⋅ F SW  η η

neglecting the small ESR of ceramic capacitors.

Considering η = 1, this function has its maximum in D = 0.5, therefore, given the maximum
peak-to-peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is:

Equation 17
IO
C IN_MIN = ------------------------------------------------
2 ⋅ VPP_MAX ⋅ F SW

Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage ripple in the order
of 1% of VINMAX.

14/31 DocID17928 Rev 7

ST1S40 Application information

In Table 6 some multi layer ceramic capacitors suitable for this device are reported.

Table 6. Input MLCC capacitors

Manufacturer Series Cap value (µF) Rated voltage (V)

GRM31 10 25
Murata
GRM55 10 25
TDK C3225 10 25

A ceramic bypass capacitor, as close as possible to the VINA pin, so that additional parasitic
ESR and ESL are minimized, is suggested in order to prevent instability on the output
voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1 µF.

6.2 Inductor selection

The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value, to have the expected current ripple, must be selected. The rule
to fix the current ripple value is to have a ripple at 20% to 40% of the output current.
In continuous current mode (CCM), the inductance value can be calculated by Equation 18

Equation 18
V IN – V OUT V OUT
∆IL = ------------------------------ ⋅ T ON = -------------- ⋅ T OFF
L L

where TON is the conduction time of the high side switch and TOFF is the conduction time of
the low side switch (in CCM, FSW = 1/(TON + TOFF)). The maximum current ripple, given the
Vout, is obtained at maximum TOFF, that is at minimum duty cycle. So by fixing ∆IL = 20% to
30% of the maximum output current, the minimum inductance value can be calculated:

Equation 19
V OUT 1 – D MIN
L MIN = ---------------- ⋅ -----------------------
∆I MAX F SWMIN

where FSWMIN is the minimum switching frequency, according to Table 4

The peak current through the inductor is given by:

Equation 20
∆IL
IL, PK = I O + --------
2

so if the inductor value decreases, the peak current (that must be lower than the current limit
of the device) increases. The higher the inductor value, the higher the average output
current that can be delivered, without reaching the current limit.

DocID17928 Rev 7 15/31

31
Application information ST1S40

In Table 7 below some inductor part numbers are listed.

Table 7. Inductors
Manufacturer Series Inductor value (µH) Saturation current (A)

XPL7030 2.2 to 4.7 6.8 to 10.5

Coilcraft MSS1048 2.2 to 6.8 4.14 to 6.62
MSS1260 10 5.5
WE-HC/HCA 3.3 to 4.7 7 to 11
Wurth WE-TPC typ XLH 3.6 to 6.2 4.5 to 6.4
WE-PD type L 10 5.6
TDK RLF7030T 2.2 to 4.7 4 to 6

6.3 Output capacitor selection

The current in the output capacitor has a triangular waveform which generates a voltage
ripple across it. This ripple is due to the capacitive component (charge or discharge of the
output capacitor) and the resistive component (due to the voltage drop across its ESR). So
the output capacitor must be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.

Equation 21
∆IMAX
∆V OUT = ESR ⋅ ∆IMAX + -------------------------------------
8 ⋅ COUT ⋅ f SW

For ceramic (MLCC) capacitors the capacitive component of the ripple dominates the
resistive one. Whilst for electrolytic capacitors the opposite is true.
Since the compensation network is internal, the output capacitor should be selected in order
to have a proper phase margin and then a stable control loop.
The equations of Section 5.2 help to check loop stability given the application conditions,
the value of the inductor, and of the output capacitor.
In Table 8 some capacitor series are listed.

Table 8. Output capacitors

Manufacturer Series Cap value (µF) Rated voltage (V) ESR (mΩ)

GRM32 22 to 100 6.3 to 25 <5

MURATA
GRM31 10 to 47 6.3 to 25 <5
ECJ 10 to 22 6.3 <5
PANASONIC
EEFCD 10 to 68 6.3 15 to 55
SANYO TPA/B/C 100 to 470 4 to 16 40 to 80
TDK C3225 22 to 100 6.3 <5

16/31 DocID17928 Rev 7

ST1S40 Application information

6.4 Thermal dissipation

The thermal design is important in order to prevent thermal shutdown of the device if
junction temperature goes above 150 °C. The three different sources of losses within the
device are:
a) conduction losses due to the ON resistance of high side switch (RHS) and low side
switch (RLS); these are equal to:

Equation 22

2 2
PCOND = R HS ⋅ I OUT ⋅ D + R LS ⋅ I OUT ⋅ ( 1 – D )

where D is the duty cycle of the application. Note that the duty cycle is theoretically given by
the ratio between VOUT and VIN, but is actually slightly higher to compensate the losses of
the regulator.
b) switching losses due to high side Power MOSFET turn ON and OFF; these can be
calculated as:

Equation 23

( T RISE + T FALL )
PSW = V IN ⋅ I OUT ⋅ ------------------------------------------- ⋅ Fsw = V IN ⋅ IOUT ⋅ T SW ⋅ F SW
2

where TRISE and TFALL are the overlap times of the voltage across the high side power
switch (VDS) and the current flowing into it during turn ON and turn OFF phases, as shown
in Figure 7. TSW is the equivalent switching time. For this device the typical value for the
equivalent switching time is 20 ns.
c) Quiescent current losses, calculated as:

Equation 24

P Q = V IN ⋅ I Q

where IQ is the quiescent current (IQ = 2.5 mA maximum).

The junction temperature TJ can be calculated as:

Equation 25

T J = T A + Rth JA ⋅ P TOT

where TA is the ambient temperature and PTOT is the sum of the power losses just seen.
RthJA is the equivalent thermal resistance junction to ambient of the device; it can be
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
of heat. The RthJA measured on the demonstration board described in the following
paragraph is about 40 °C/W for the VFQFPN and HSOP packages and about 55 °C/W for
the SO8 package.

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31
Application information ST1S40

Figure 7. Switching losses

VIN
VSW

ISW,HS

VDS,HS

PSW

PCOND,HS PCOND,LS

TFALL TRISE

6.5 Layout consideration

The PC board layout of switching DC-DC regulator is very important in order to minimize the
noise injected in high impedance nodes, to reduce interferences generated by the high
switching current loops, and to optimize the reliability of the device.
In order to avoid EMC problems, the high switching current loops must be as short as
possible. In the buck converter there are two high switching current loops: during the ON
time, the pulsed current flows through the input capacitor, the high side power switch, the
inductor and the output capacitor; during the OFF time, through the low side power switch,
the inductor and the output capacitor.
The input capacitor connected to VINSW must be placed as close as possible to the device,
to avoid spikes on VINSW due to the stray inductance and the pulsed input current.
In order to prevent dynamic unbalance between VINSW and VINA, the trace connecting the
VINA pin to the input must be derived from VINSW and design local ceramic bypass
capacitor (1 µF) as close as possible to the VINA pin.
The feedback pin (FB) connection to the external resistor divider is a high impedance node,
so the interferences can be minimized through the routing of the feedback node with a very
short trace and as far as possible from the high current paths.
A single point connection from signal ground to power ground is suggested.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane, soldered to the exposed pad,
enhances the thermal performance of the converter allowing high power conversion.

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ST1S40 Application information

Figure 8. PCB layout guidelines

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7RERWWRPRULQQHUJURXQGSODQH

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SRVVLEOHWR9,16:SLQ

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Demonstration board ST1S40

7 Demonstration board

Figure 9. Demonstration boards schematic

Table 9. Component list

Reference Part number Description Manufacturer

U1 ST1S40 STMicroelectronics®
L1 DRA74 3R3 3.3 µH, Isat = 5.4 A Coiltronics
C1 C3225X7RE106K 10 µF 25 V X7R TDK
C2 C3225X7R1C226M 22 µF 16 V X7R TDK
C3 1 µF 25 V X7R
C4 NC
R1 62.5 kΩ
R2 20 kΩ
R3 10 kΩ

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ST1S40 Demonstration board

Figure 10. Demonstration board PCB top and bottom: HSOP-8 package

Figure 11. Demonstration board PCB top and bottom: VFQFPN package

Figure 12. Demonstration board PCB top and bottom: SO8 package

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Typical characteristics ST1S40

8 Typical characteristics

Figure 13. Efficiency vs. IOUT Figure 14. Efficiency vs. IOUT
90
100
85

90 80

75
80

Efficiency [%]
70
Efficiency [%]

65
70
60

60 Vin=5V Vin=12V
55
Vo=1.8V
Vo=3.3V
50
Vo=1.2V
50 Vo=1.8V
45
Vo=1.2V

40 40
0.00 0.50 1.00 1.50 2.00 2.50 3.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00

Iout [A] Iout [A]

Figure 15. Efficiency vs. IOUT Figure 16. Overcurrent protection

100

90

80
Efficiency [%]

70
Vin=12V
Vo=5V
60
Vo=3.3V

50

40
0.00 0.50 1.00 1.50 2.00 2.50 3.00

Iout [A]

Figure 17. Short-circuit protection Figure 18. SO8 maximum IOUT

Maximum IOUT according to 1.6W power dissipation

Limit with SO8-BW package

Tamb=60degC
Tjmax=150degC

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ST1S40 Package information

9 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

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Package information ST1S40

Figure 19. VFQFPN8 (4 x 4 x 1.0 mm) package outline

%

Table 10. VFQFPN8 (4 x 4 x 1.0 mm) package mechanical data

Dimensions

Symbol mm inch

Min. Typ. Max. Min. Typ. Max.

A 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0.02 0.05 0.0008 0.0020
A3 0.20 0.0079

b 0.23 0.30 0.38 0.009 0.0117 0.0149

D 3.90 4.00 4.10 0.153 0.157 0.161
D2 2.82 3.00 3.23 0.111 0.118 0.127
E 3.90 4.00 4.10 0.153 0.157 0.161
E2 2.05 2.20 2.30 0.081 0.087 0.091
e 0.80 0.031
L 0.40 0.50 0.60 0.016 0.020 0.024

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ST1S40 Package information

Figure 20. SO8 package outline

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31
Package information ST1S40

Table 11. SO8 package mechanical data

Dimensions

Symbol mm

Min. Typ. Max.

A - - 1.75
A1 0.10 - 0.225
A2 1.30 1.40 1.50
A3 0.60 0.65 0.70
b 0.39 - 0.47
b1 0.38 0.41 0.44
c 0.20 - 0.24
c1 0.19 0.20 0.21
D 4.80 4.90 5.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27 BSC
L1 1.05 REF
h 0.25 - 0.50
L 0.50 - 0.80
Θ 0 - 8°

26/31 DocID17928 Rev 7

ST1S40 Package information

Figure 21. HSOP-8 package outline

' PP7\S
( PP7\S

$0Y

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31
Package information ST1S40

Table 12. HSOP-8 package mechanical data

Dimensions

Symbol mm inch

Min. Typ. Max. Min. Typ. Max.

A 1.70 0.0669
A1 0.00 0.150 0.00 0.0059
A2 1.25 0.0492
b 0.31 0.51 0.0122 0.0201
c 0.17 0.25 0.0067 0.0098
D 4.80 4.90 5.00 0.1890 0.1929 0.1969
E 5.80 6.00 6.20 0.2283 0.2362 0.2441
E1 3.80 3.90 4.00 0.1496 0.1535 0.1575
e 1.27 0.0500
h 0.25 0.50 0.0098 0.0197
L 0.40 1.27 0.0157 0.0500
k 0.00 8.00 0.3150
ccc 0.10 0.0039

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ST1S40 Order codes

10 Order codes

Table 13. Ordering information

Order codes Package Function

ST1S40IPUR VFQFPN 4 x 4 8L
ST1S40IPHR HSOP-8 Enable
ST1S40IDR SO8

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Revision history ST1S40

11 Revision history

Table 14. Document revision history

Date Revision Changes

15-Dec-2010 1 First release

04-Mar-2011 2 Updated: Table 1, Table 2, Table 3 and Table 13.
Updated cover page: Table 1, Table 2, Section 5
20-Dec-2011 3
Added Section 6, Section 7 and Section 8
01-Mar-2012 4 HSOP8 mechanical data and package dimensions have been updated.
Updated Table 2 - added value “-2 V to -1 V for 50 nsec” for parameter VSW.
Reformatted Section 9: Package information - reversed order of Figure 19 and
10-Oct-2013 5
Table 10, Figure 20 and Table 11, Figure 21 and Table 12.
Minor corrections throughout document.
28-Aug-2019 6 Updated Section 5.4: Enable function.
15-Sep-2023 7 Updated Figure 20 and Table 11.

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ST1S40

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2023 STMicroelectronics – All rights reserved

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