STA540SAN

4 x 10-watt dual/quad power amplifier

Features
„ High output-power capability:
– 4 x 9 W / 2 Ω at 12 V, 1 kHz, 10%
– 4 x 10 W / 4 Ω at 17 V, 1 kHz, 10%
– 2 x 26 W / 4 Ω at 14.4 V, 1 kHz, 10%
( s )
– 2 x 15 W / 8 Ω at 16 V, 1 kHz, 10%

u ct
„ Minimum external component count:
– No bootstrap capacitors
o d
Clipwatt15
– No Boucherot cells
P r
– Thermal cut-off limiter to prevent chip from

„
– Internally fixed gain of 20 dB
Standby function (CMOS compatible)
overheating

e te
– High inductive loads
„ No audible pop during standby operations – ESD
o l
„ Diagnostic facilities:
b s
Description
– Clip detector
O
)-
– Out to GND short circuit The STA540SAN contains four single-ended,
– Out to VS short circuit
– Soft short at turn-on
t ( s class-AB audio amplifiers assembled in a
Clipwatt15 package.
c
du
– Thermal shutdown proximity These amplifiers are used for high-quality sound
„ Protection for applications. Each amplifier has integrated

r o
– Output AC/DC short circuit short-circuit and thermal protection and

P
– Soft short circuit at turn-on
e
diagnostic functions. Two amplifiers can be paired
up for applications requiring high power output.

e t
ol
Table 1. Device summary

bs
Order code Temperature range Package Packaging

O
STA540SAN -40 to 150 °C Clipwatt15 Tube

December 2010 Doc ID 18306 Rev 1 1/26

www.st.com 26
Contents STA540SAN

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
)
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

( s
ct
3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4
d u
Test and applications board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

r o
5 P
Standard applications circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
e
6 l e t
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
s o
7 b
Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
O
) -
(s
8 General structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1
c t
High application flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.2
d u
Easy single-ended to bridge transition . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.3
r o
Internally fixed gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.4
e P Silent turn on/off and muting/standby functions . . . . . . . . . . . . . . . . . . . . 18

l e t
8.5 Standby driving (pin 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

o
bs
8.6 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.6.1 Rail-to-rail output voltage swing with no need of bootstrap capacitors . 19
O 8.6.2 Absolute stability without any external compensation . . . . . . . . . . . . . . 19
8.7 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.7.1 Diagnostic facilities (pin 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.7.2 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.8 Handling of the diagnostic information . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.9 PCB-layout grounding (general rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.10 Mute function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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 STA540SAN Contents

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

( s )
u ct
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P r
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b s
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(s )
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l e t
s o
O b

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 Block diagram STA540SAN

1 Block diagram

Figure 1. Block diagram

VCC2 VCC1

13 3 A1
+ 1
OUT1
-

4
IN1
A2 INV
+

)
2
7 OUT2
ST_BY -

( s
IN2
5
A3
u ct
+ 15

o d
r
OUT3
-

12

e P
IN3
A4 INV
+
l e t 14

s o-
OUT4

IN4
11

O b 10 DIAGNOSTIC
OUTPUT

( s )-
6 8 9

t
SVR P_GND S_GND
D06AU1630_bc

u c
o d
P r
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O

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 STA540SAN Pin description

2 Pin description

Figure 2. Pin connection (top view)

15 OUT3
14 OUT4
13 VCC2
12 IN3
11 IN4
10 DIAG
9 S_GND
8 P_GND
7 ST_BY

( s )
ct
6 SVR
5 IN2
4
3
IN1
VCC1

d u
2
1
OUT2
OUT1
r o
e P
t
clp15_pins_540san_bc

Table 2. Pin description

o l e
Pin Name Type
b s Function

1 OUT1 OUTPUT
- O
Channel 1 output
2 OUT2
)
OUTPUT

(s
Channel 2 output

ct
3 VCC1 POWER Power supply

du
4 IN1 INPUT Channel 1 input
5 IN2

r o INPUT Channel 2 input

6
PSVR INPUT Supply voltage rejection

ete
7 ST_BY INPUT Standby control pin

ol
8 P_GND POWER Power ground

b s 9
10
S_GND
DIAG
POWER
OUTPUT
Signal ground
Diagnostics

O 11
12
IN4
IN3
INPUT
INPUT
Channel 4 input
Channel 3 input
13 VCC2 POWER Power supply
14 OUT4 OUTPUT Channel 4 output
15 OUT3 OUTPUT Channel 3 output

Doc ID 18306 Rev 1 5/26

 Electrical specifications STA540SAN

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings
Symbol Parameter Value Unit

Supply voltage idle mode (no signal) 24 V

VSmax Supply voltage operating 22 V
Supply voltage AC-DC short safe 20 V
VST_BYmax Voltage on pin ST_BY VSmax

( s ) -

ct
Ptot Total power dissipation (Tcase = 70 °C) 35 W

du
Tstg, Tj Storage and junction temperature -40 to150 °C

ro
Top Operating temperature 0 to 70 °C

e P
3.2 Thermal data
l e t
Table 4. Thermal data
s o
Symbol

O b
Parameter Min Typ Max Unit

)-
Rth j-case Thermal resistance junction to case - - 2.5 °C/W

t(s
Rth j-amb Thermal resistance junction to ambient - - 45 °C/W

u c
3.3
d
Electrical characteristics
o
P r
The results in Table 5 below were measured under the conditions VS = 15 V, RL = 4 Ω,
f = 1 kHz and Tamb = 25 °C unless otherwise specified. Refer also to the test circuit in

e t e
Figure 3 on page 8

s ol Table 5. Electrical characteristics

O b Symbol

VS
Parameter

Supply voltage range -

Test condition

8
Min

-
Typ

22
Max Unit

V
Id Total quiescent drain current - - 80 150 mA
Vos Output offset voltage - -250 - 250 mV
THD = 10% 6.5 7.5 - W
THD = 10%, VS = 17 V
- 10 - W
Po Output power S.E. RL = 4 Ω
THD = 10%, VS = 17 V
- 20 - W
BTL, RL = 8 Ω
THD Distortion RL = 4 Ω, Po = 0.1 to 4 W - 0.02 - %
ISC Short-circuit current - - 3.5 - A

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 STA540SAN Electrical specifications

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min Typ Max Unit

f = 1 kHz 70
CT Crosstalk - - dB
f = 10 kHz 60
Rin Input impedance - 20 30 - kΩ
Gv Voltage gain - 19 20 21 dB
Gv Voltage gain match - - - 0.5 dB
Rg = 0, “A” weighted
EN Total output noise Inverting channels: - 50 - µV
Non-inverting channels: - 20 -
Rg = 0, f = 300 Hz,
( s )
ct
SVR Supply voltage rejection 50 - - dB
CSVR = 470 µF

du
ASB Standby attenuation - 80 90 - dB

ro
ISB ST_BY current consumption VST_BY = 0 to 1.5 V - - 100 µA
VSB ST_BY IN threshold voltage
ST_BY OUT threshold
-

e P - - 1.5 V

let
VSB - 3.5 - - V
voltage

so
Play mode VST_BY = 5 V - - 50 µA
IST_BY ST_BY pin current

Clipping detector output

O b
Driving current under fault - - 5 mA

)-
Icd off THD = 1% (1) - 90 - µA
average current

Icd on
t
average current ( s
Clipping detector output
THD = 5% (1) - 160 - µA

c
du
Sink current on pin DIAG
VDIAG Voltage saturation on DIAG - - 0.7 V
IDIAG = 1 mA
TW
r o
Thermal warning - - 140 - °C

e
TM P Thermal muting - - 150 - °C

e t TS Thermal shutdown - - 160 - °C

sol 1. Pin DIAG pulled-up to 5 V with 10 kΩ

O b

Doc ID 18306 Rev 1 7/26

 4 Test and applications board
8/26

Test and applications board

This chapter includes information about the test and applications board including the test circuit, board layout, and parts list.

Figure 3. Test circuit

( s )
ct
du
VCC VCC
VCC
SW1
CN7
CN-5-02P
1
1
SLIDSWITCH-2.54-3P

R2
r o R1

P
2
2 C6 C5
3 1K8 10K

e 1000 µF CN3

t
100 nF C7 2200 µF, 25 V CN-5-02P
PGND C13 C12 25 V 50 V 1

e
DO7

ol
10 µF 2
ZD1
SGND 100 nF 25 V
PGND JP1

s
JP1, JP2 :
SGND JUMPER2X1(DIP) Open = SE
2 IN1

b SGND PGND
Doc ID 18306 Rev 1

Closed = BTL

13
CN4

ST-BY 7

VCC1 3
1 SGND C8 2200 µF, 25 V CN-5-02P

)-
C1

VCC2
4 IN1 1
3 IN2 JP5
0.22uF OUT1 1 2

s
JUMPER2X1(DIP)
C2 0.22uF
CN1

c t
RCA4CH_6P ( 5 IN2

12 IN3
IC1
STA540SAN
OUT2 2 JP2
JUMPER2X1(DIP) PGND

du
CLIPWATT15
C3 0.22uF OUT3 15
JP6
5 IN4 C4

ro
JUMPER2X1(DIP) 11 IN4
CN5
OUT4 14

P_GND

S_GND
0.22uF C9 2200 µF, 25 V CN-5-02P

DIAG
4 6 SVR 1

e P 6 IN3
SGND
C11
2

10
8

9
JP3, JP4 :

let
47 µF Diagnostics JP3
25 V Open = SE
JUMPER2X1(DIP) PGND
Closed = BTL
CN6

o
SGND C10 2200 µF, 25 V CN-5-02P
TP 1

b s PGND SGND TP1 2

O JP4
JUMPER2X1(DIP)
PGND

STA540SAN
STA540SAN Test and applications board

Figure 4. Component layout

( s )
u ct
o d
Figure 5. Component side

P r
e te
o l
b s
- O
(s )
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let
Figure 6. Solder side

s o
Ob

Doc ID 18306 Rev 1 9/26

 Test and applications board STA540SAN

Table 6. List of components

Components Suggested value Purpose

R1 10 kΩ Standby time constant

R2 1.8 kΩ Ripple rejection
C1, C2, C3, C4 0.22 µF Input AC coupling
C5 0.1 µF Voltage supply decoupling
C6 1000 µF Voltage supply decoupling
C7, C8, C9, C10 2200 µF Output AC coupling
C11 47 µF Ripple rejection
C12 10 µF Standby time constant

( s )
ct
C13 100 nF Ripple rejection
ZD1 10 µF
u
Standby time constant
d
r o
e P
l e t
s o
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) -
c t(s
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10/26 Doc ID 18306 Rev 1

 STA540SAN Standard applications circuits

5 Standard applications circuits

Figure 7. Quad stereo

10K
ST-BY VS
10µF 100nF 1000µF

IN1 4 7 13 3 1
Suggested applications:
0.22µF 2200µF OUT1
IN2 5 4 x 12 W at 2 Ω, 14.4 V
2 4 x 10 W at 4 Ω, 17 V
0.22µF
2200µF OUT2 4 x 9 W at 2 Ω, 12 V
IN3
0.22µF
12
15
4 x 5 W at 4 Ω, 12 V

( s )
IN4
0.22µF
11 2200µF OUT3

u ct
6
8 9
14
10 2200µF OUT4
o d
47µF
DIAGNOSTICS
D04AU1555B
P r
P-GND S-GND

e t e
Figure 8. Audio performance option
o l
bs
1 14

2
- O
( s ) 15

c t 470 µF 470 µF

d u
r o
The best audio performance is obtained with the configuration where each speaker has its

e P
own DC blocking capacitor. If the application allows a little degradation of the spatial image it
is possible to connect a couple of speakers with only one low-value DC blocking capacitor.

l e t
Figure 9. Double bridge

so 10K

O b ST-BY

10µF 100nF
VS
1000µF

Suggested applications:
7 13 3
IN L 4 1 2 x 9 W at 8 Ω, 12 V
0.47µF 5 OUT L 2 x 18 W at 4 Ω, 12 V
2
2 x 13 W at 8 Ω, 14 V
IN R 11 2 x 26 W at 8 Ω, 14 V
14 2 x 15 W at 8 Ω, 16 V
0.47µF 12
OUT R
6 15
47µF 8 9 10

DIAGNOSTICS
D95AU1600

A dedicated evaluation board is available for this application (see Chapter 4 on page 8).

Doc ID 18306 Rev 1 11/26

 Standard applications circuits STA540SAN

Figure 10. Stereo Bridge

10K
ST-BY VS
10µF 100nF 1000µF

7 13 3
IN L 4 1
OUT L
0.22µF 2200µF
IN R 5 2
OUT R
0.22µF 2200µF
IN BRIDGE 11 14
0.47µF 12 OUT

)
BRIDGE
6 15
8 9 10
( s
ct
47µF
DIAGNOSTICS

u
D05AU1601

Suggested applications:

o d
2 x 9 W into 2 Ω + 1 x 18 W into 4 Ω, 12 V
2 x 12 W into 2 Ω + 1 x 26 W into 4 Ω, 14.4 V
2 x 8 W into 4 Ω + 1 x 16 W into 8 Ω, 16 V P r
e t e
l
A dedicated evaluation board is available for this application (see Chapter 4 on page 8).
o
b s
- O
(s )
c t
d u
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12/26 Doc ID 18306 Rev 1

STA540SAN Electrical characteristics curves

6 Electrical characteristics curves

Figure 11. Quiescent drain current vs supply Figure 12. Quiescent output voltage vs supply
voltage (single-ended and bridge) voltage (single-ended and bridge)

( s )
u ct
o d
P r
Figure 13. Output power vs supply voltage
e te
Figure 14. Distortion vs output power

o l
b s
- O
(s )
c t
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o
bs
Figure 15. Output power vs supply voltage Figure 16. Distortion vs output power

O
20
Po(W)
18
S.E.
16
Rl=4ohm
14 f=1KHz

12
T.H.D=10%
10

6 T.H.D=1%

0
+8 +10 +12 +14 +16 +18 +20 +22
Vs(V)

Doc ID 18306 Rev 1 13/26

Electrical characteristics curves STA540SAN

Figure 17. Output power vs supply voltage Figure 18. Distortion vs output power

( s )
u ct
Figure 19. Output power vs supply voltage
d
Figure 20. Crosstalk vs frequency
o
Po(W)
12

11
P r
10

9
S.E.
Rl=8ohm

e t e
l
f=1KHz
8

s o
b
6 T.H.D=10%

3
T.H.D=1%

- O
2

(s )
t
1

0
+8 +10 +12 +14 +16
Vs(V)

u c +18 +20 +22 +24

o d
Figure 21. Output power vs voltage
P r Figure 22. Standby attenuation vs threshold

e t e voltage

l
Po(W) 35

o
32.5

bs
30
BTL
27.5
Rl=8ohm
25 f=1KHz

O 22.5

20
17.5
T.H.D=10%

15

12.5
T.H.D=1%
10

7.5
5

2.5

0
+8 +10 +12 +14 +16 +18 +20 +22
Vs(V)

14/26 Doc ID 18306 Rev 1

 STA540SAN Electrical characteristics curves

Figure 23. Supply voltage rejection vs Figure 24. Total power dissipation and
frequency efficiency vs output power

( s )
u ct
o d
Figure 25. Total power dissipation and
efficiency vs output power
P r
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(s )
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 Thermal information STA540SAN

7 Thermal information

In order to avoid the thermal protection intervention that is placed at Tj =150 °C (thermal
muting) or Tj=160 °C (thermal shutdown), it is important to design the heatsink Rth (°C/W)
value correctly.
The parameters that influence the design are:
z Maximum dissipated power for the device (Pdmax)
z Maximum thermal resistance junction to case (Rth_j-case)
z Maximum ambient temperature Tamb_max
There is also an additional term that depends on the quiescent current, Iq, but this is
negligible in this case.
( s )
Example 1: 4-channel single-ended amplifier
u ct
d
VCC =14.4 V, RL = 4 Ω x 4 channels, Rth_j-case = 2.5 °C/W, Tamb_max = 50 °C, Pout = 4 x 7 W
o
V CC
P dmax = NChannel ⋅ -----------------
2
2
- = 4 ⋅ 2.62 = 10.5W
P r
2Π R L
e t e
The required thermal resistance for the heatsink is
o l
150 – T amb_max
b s - – R th_j-case = 150
"" R th_c-amb = -------------------------------------- – 50- – 2.5 = 7°C/W
---------------------
P dmax
- O 10.5

(s )
Example 2: 2-channel single-ended plus 1-channel (BTL) amplifier

c t
VCC = 14.4 V, RL = 2 x 2 Ω (SE) + 1 x 4 Ω (BTL), Pout = 2 x 12 W + 1 x 26 W
u
od
2 2
V CC 2V CC
P dmax = 2 ⋅ ----------------- - = 2 ⋅ 5.25 + 10.5 = 21W
- + ----------------

P r 2
2Π R L Π R L
2

t e
The required thermal resistance for the heatsink is
e
o l 150 – T amb_max
- – R th_j-case = 150
"" R th_c-amb = -------------------------------------- – 50- – 2.5 = 2.2°C/W
---------------------
b s P dmax 21

O Design notes on examples 1 and 2

The values found give a heatsink that is designed to sustain the maximum dissipated power.
But, as explained in the applications note AN1965, the heatsink can be smaller when a
realistic application is considered where a musical program is used.
When the average listening power concept is considered, the dissipated power is about 40%
less than the Pdmax. Therefore, in examples 1 and 2, the resulting average dissipated power
is reduced as follows:
– Example 1: 10.5 W - 40% = 6.3 W giving Rth_c-amb = 13.4 °C/W
– Example 2: 21 W - 40% = 12.6 W giving Rth_c-amb = 5.4 °C/W
Figure 26 below shows the power derating curve for the device.

16/26 Doc ID 18306 Rev 1

 STA540SAN Thermal information

Figure 26. Power derating curve

Pd(W) 30
1) Infinite
25 1
2) 3.5C/W
2
3 3) 5C/W
20 4) 7C/W
4

15

10

( s )
0
0 20 40 60 80 100 120 140
u ct
160
Tamb(C)

o d
P r
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b s
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(s )
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so
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 General structure STA540SAN

8 General structure

8.1 High application flexibility

The availability of four independent channels makes it possible to accomplish several kinds
of applications ranging from four-speaker stereo (F/R) to two-speaker bridge solutions.
When working with single-ended conditions, the polarity of the speakers driven by the
inverting amplifier must be reversed with respect to those driven by non-inverting channels.
This is to avoid phase irregularities causing sound alterations especially during the
reproduction of low frequencies.

8.2 Easy single-ended to bridge transition

( s )
u ct
The change from single-ended to bridge configurations is made simple by means of a short

d
circuit across the inputs (resulting in no need of additional external components).
o
P r
8.3 Internally fixed gain
e te
l
The gain is internally fixed to 20 dB in single-ended mode and 26 dB in bridge mode.
o
z components and space saving b s
The advantages of this design choice are in terms of:

z
- O
output noise, supply voltage rejection and distortion optimization.

(s )
8.4 t
Silent turn on/off and muting/standby functions
c
d u
Standby mode can be easily activated by means of a CMOS logic level applied to pin 7

r o
through a RC filter.

e P
Under standby conditions, the device is turned off completely (supply current = 1 mA typical,
output attenuation = 80 dB minimum).

l e t
All on/off operations are virtually pop-free. Furthermore, at turn-on the device stays in mute

s o condition for a time determined by the value assigned to the SVR capacitor. In mute mode,

O b the device outputs are insensitive to any kind of signal that may be present at the input
terminals. In other words, any transients coming from previous stages produce no
unpleasant acoustic effects at the speakers.

8.5 Standby driving (pin 7)

Some precautions need to be taken when defining standby driving networks. Pin 7 cannot
be directly driven by a voltage source having a current capability higher than 5 mA. In
practical cases a series resistance must be inserted, giving it the double purpose of limiting
the current at pin 7 and smoothing down the standby on/off transitions. And, when done in
combination with a capacitor, prevents output pop.
A capacitor of at least 100 nF from pin 7 to S_GND, with no resistance in between, is
necessary to ensure correct turn-on.

18/26 Doc ID 18306 Rev 1

 STA540SAN General structure

8.6 Output stage

The fully complementary output stage is possible with the power ICV PNP component.
This novel design is based on the connection shown in Figure 27 and allows the full
exploitation of its capabilities. The clear advantages this new approach has over classical
output stages are described in the following sections.

8.6.1 Rail-to-rail output voltage swing with no need of bootstrap capacitors

The output swing is limited only by the VCEsat of the output transistors, which are in the
range of 0.3 Ω (Rsat) each.
Classical solutions adopting composite PNP-NPN for the upper output stage have higher
saturation loss on the top side of the waveform.

( s )
ct
This unbalanced saturation causes a significant power reduction. The only way to recover
power includes the addition of expensive bootstrap capacitors.

d u
8.6.2 Absolute stability without any external compensation
r o
P
With reference to the circuit shown in Figure 27, the gain Vout/Vin is greater than unity, that
e
to all the channels.
l e t
is, approximately 1+R2/R1. The DC output (VCC/2) is fixed by an auxiliary amplifier common

s o
By controlling the amount of this local feedback, it is possible to force the loop gain (A*β) to

O b
less than unity at a frequency where the phase shift is 180 °. This means that the output
buffer is intrinsically stable and not prone to oscillation.

-
The above feature has been achieved even though there is very low closed-loop gain of the
)
(s
amplifier.

c t
This is in contrast with the classical PNP-NPN stage where the solution adopted for

Boucherot cells.
d u
reducing the gain at high frequencies makes use of external RC networks, namely the

r o
P
Figure 27. The new output stage

e
l e t
s o
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Doc ID 18306 Rev 1 19/26

General structure STA540SAN

8.7 Short-circuit protection

Reliable and safe operation in the presence of all kinds of short circuits involving the outputs
is assured by built-in protection. Additionally, a soft short-condition is signalled out (to the
AC/DC short circuit to GND, to VS, and across the speaker) during the turn-on phase to
ensure correct operation of the device and the speakers.
This particular kind of protection acts in such a way as to prevent the device being turned on
(by ST_BY) when a resistive path (less than 16 Ω) is present between the output and GND.
It is important to have the external current source driving the ST_BY pin limited to 5 mA.
This is because the associated circuitry is normally disabled with currents >5 mA.
This extra function becomes particularly attractive when, in the single-ended configuration,
one capacitor is shared between two outputs as shown in Figure 28.

( s )
ct
Figure 28. Sharing a capacitor

d u
r o
e P
l e t
If the output capacitor Cout is shorted for any reason, the loudspeaker is not damaged.

s o
8.7.1 Diagnostic facilities (pin 10)
O b
events:
) -
The STA540SAN is equipped with diagnostic circuitry that is able to detect the following

z
z t (s
Clipping in the output signal
Thermal shutdown
c
z
d
Output fault: u
–
r o
short to GND

e
–
P short to VS

let
– soft short at turn on
The information is available across an open collector output (pin 10) through a current

s o sinking when the event is detected.

Ob Figure 29. Clipping detection waveforms

A current sinking at pin 10 is provided when a certain distortion level is reached at each
output. This function initiates a gain-compression facility whenever the amplifier is
overdriven.

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 STA540SAN General structure

8.7.2 Thermal shutdown

With the thermal shutdown feature, the output (pin 10) signals the proximity of the junction
temperature to the shutdown threshold. Typically, current sinking at pin 10 starts at
approximately 10 °C before the shutdown threshold is reached.

Figure 30. Output fault waveforms

10

10

( s )
Figure 31. Fault waveforms
u ct
o d
ST_BY PIN
VOLTAGE

P r
e
2V

let
t
OUT TO Vs SHORT

OUTPUT

s o
b
WAVEFORM
SOFT SHORT

- O t

( s ) OUT TO GND SHORT

Vpin 10

c t CORRECT TURN-ON

d u FAULT DETECTION

o
t

Pr
CHECK AT TURN-ON SHORT TO GND
D05AU1603
(TEST PHASE) OR TO Vs

e t e
s ol
O b

Doc ID 18306 Rev 1 21/26

 General structure STA540SAN

8.8 Handling of the diagnostic information

As different diagnostic information is available at the same pin (clipping detection, output
fault, thermal proximity), the signal must be handled correctly in order to discriminate the
event. This could be done by taking into account the different timing of the diagnostic output
during each case.
Normally, clip-detector signalling under faulty conditions produces a low level at pin 10.
Based on this assumption, an interface circuitry to differentiate the information is shown in
Figure 33.

Figure 32. Waveforms

ST_BY PIN

( s )
ct
VOLTAGE

du
t

Vs
r o
OUTPUT
WAVEFORM

e P
e t
ol
t

Vpin 10
b s
WAVEFORM
O
( s )- CLIPPING
SHORT TO GND THERMAL
t

t
D05AU1604_bc
OR TO Vs PROXIMITY

u c
d
Figure 33. Interface circuit diagram

o
P r
e te
o l 10

b s
O

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STA540SAN General structure

8.9 PCB-layout grounding (general rules)

The device has two distinct ground leads, P_GND (power ground) and S_GND (signal
ground) which are practically disconnected from each other at chip level. Correct operation
requires that P_GND and S_GND leads be connected together on the PCB layout by means
of reasonably low-resistance tracks.
For the PCB ground configuration a star-like arrangement, where the center is represented
by the supply-filtering electrolytic capacitor ground, is recommended. In such context, at
least two separate paths must be provided; one for power ground and one for signal ground.
The correct ground assignments are as follows:
z standby capacitor (pin 7, or any other standby driving networks): on signal ground
z SVR capacitor (pin 6): on signal ground and to be placed as close as possible to the
device
( s )
z
z
input signal ground (from active/passive signal processor stages): on signal ground
supply filtering capacitors (pins 3 and 13): on power ground. The negative terminal of
u ct
the electrolytic capacitor must be directly tied to the battery negative line and this
o d
should represent the starting point for all the ground paths.

P r
8.10 Mute function
e t e
o l
s
If the mute function is required, it can be accessed on SVR (pin 6) as shown in Figure 34.

b
Figure 34. Components for layout
O
)-
10K

t ( s
ST-BY
10µF 100nF 1000µF
VS

c
du
0.22µF 7 13 3
IN L 4 1
OUT L

r o IN R
0.22µF
5
2200µF

P
2
OUT R
2200µF

e t e IN BRIDGE
0.47µF
12 15

o l MUTE R1 3.3K
11
6 14
OUT
BRIDGE

b s 0
5V
R2 10K
470µF
8 9 10

O PLAY DIAGNOSTICS

D06AU1632_bc

VS = 10 to 16 V, VSVR: mute off ≥ 0.6 to 0.8, mute on ≥ 0.2 V

Using a different value for R1 than the suggested 3.3 kΩ, results in two different situations:
z R1 > 3.3 kΩ:
– Pop noise improved
– Lower mute attenuation
z R1 < 3.3 kΩ:
– Pop noise degradation
– Higher mute attenuation

Doc ID 18306 Rev 1 23/26

 Package mechanical data STA540SAN

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 35. Mechanical data and package dimensions

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
OUTLINE AND
MECHANICAL DATA

)
A 3.2 0.126

B 1.05 0.041

( s
ct
C 0.15 0.006 Weight: 1.92gr
D

E 0.49
1.50

0.55 0.019
0.061

0.022
d u
F 0.67 0.73 0.026 0.029
r o
G 1.14 1.27 1.4 0.045 0.050 0.055

e P
t
G1 17.57 17.78 17.91 0.692 0.700 0.705

H1

H2
12

18.6
0.480

0.732
o l e
H3 19.85 0.781

b s
O
L 17.9 0.704

L1

L2 10.7
14.55

11 11.2
)
0.421- 0.572

0.433 0.441

L3

M
5.5

2.54
ct (s 0.217

0.100 Clipwatt15

du
M1 2.54 0.100

r o
e P
e t
s ol
O b

0044538 G

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 STA540SAN Revision history

10 Revision history

Table 7. Document revision history

Date Revision Changes

16-Dec-2010 1 Initial release

( s )
u ct
o d
P r
e te
o l
b s
- O
(s )
c t
du
r o
e P
l e t
s o
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 STA540SAN

Please Read Carefully:

( s )
u ct
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

time, without notice.

o d
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

All ST products are sold pursuant to ST’s terms and conditions of sale.
P r
t e
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

e
o l
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

b s
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.

- O
(s )
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

c t
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

d u
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

r o
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

P
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

e t e
o l
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

s
liability of ST.

b
O ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

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26/26 Doc ID 18306 Rev 1