L99ASC03

Brushless / sensorless 3-phase motor pre-driver

for automotive applications
Datasheet - production data

• TQFP48 7 x 7 x 1 mm with Exposed Pad

(4.5 x 4.5 mm) package

Applications
• Mechatronic three-phase motor application
TQFP48-EP such as engine cooling fans, fuel pumps, water
pumps, oil pumps

Features Description
• Automotive qualified The L99ASC03 is a multifunctional system IC
designed for three-phase motor control
• 5 V low-drop voltage regulator (200 mA applications.
continuous mode)
The device features a voltage regulator to supply
• Very low current consumption in standby mode
an external microcontroller and an operation
(typ. 15 µA)
amplifier for motor current sensing. It is designed
• ST SPI interface for control and diagnostics to control six external
• Window watchdog and fail-safe functionality N-channel MOSFETs in bridge configuration to
drive three-phase motors in automotive
• Two separate power supply pins
applications. All gate driver outputs are controlled
• Three half-bridge drivers to control external by separate inputs.
MOSFETs (configurable by SPI)
The integrated Serial Peripheral Interface (SPI)
• Full drive of external MOSFETs down to 6 V makes it possible to adjust device parameters,
input voltage control all operating modes and read out
• Input pin for each gate driver (with cross- diagnostic information.
current protection)
• Two-stage charge pump supporting 100% duty
cycle
• PWM operation up to 80 kHz (not restricted)
• Current-sense amplifier (configurable by SPI)
• Disable input to turn off gate driver outputs
• Analog multiplexer output to monitor external
power supply voltages and internal junction
temperature Table 1. Device summary
• Advanced BEMF detection IP Order codes
Package
• Overcurrent protection (programmable) Tube Tape and real
• Drain-source monitoring and open-load
TQFP48-EP L99ASC03 L99ASC03TR
detection

August 2015 DocID023504 Rev 7 1/73

This is information on a product in full production. www.st.com
Contents L99ASC03

Contents

1 Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Supply pins (VS, VSREG, VSMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.1 VS, VSREG and VSMS overvoltage warning . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 VS, VSREG and VSMS overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 VS, VSREG and VSMS undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 VDD (5V) voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 NRES reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.4 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.1 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.2 Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.3 VDD Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.4 VBAT Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.5 Device mode state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.6 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6 DIS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7 INH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8 Thermal warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8.1 Normal mode: TEMPM = ‘0’ (TW1, TSD1, TSD2) . . . . . . . . . . . . . . . . . 18
2.8.2 Warning mode: TEMP = ‘1’ (TW1, TW2, TSD2) . . . . . . . . . . . . . . . . . . 18
2.9 Wake-up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.10 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.11 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.12 Drain-source monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.12.1 Drain-source monitoring in ON state (short-circuit detection) . . . . . . . . 22
2.12.2 Drain-source monitoring in OFF state (open-load / short-circuit detection)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.13 Current-sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.14 Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.15 BEMF module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.15.1 BEMF comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2/73 DocID023504 Rev 7

L99ASC03 Contents

2.15.2 BEMF comparator sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.15.3 BEMF commutation driving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.16 Digital multiplexer (DOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.17 Analog multiplexer (AOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.18 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.19 Serial peripheral interface (ST SPI standard) . . . . . . . . . . . . . . . . . . . . . . 29

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6 SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4 ST-SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1 Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1.1 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1.2 Clock and data characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2.1 SDI frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2.2 SDO frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3 Addresses and data definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.1 Device information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.4.1 SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.4.2 Device Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4.3 Device Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.4.4 Device Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4.5 Device Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.4.6 Device Control Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.4.7 Device Control Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.4.8 Device Control Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.4.9 Device Control Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.4.10 Device Status Registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.4.11 Device Status Registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

DocID023504 Rev 7 3/73

4
Contents L99ASC03

4.4.12 Device Status Registers 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.4.13 Device Status Registers 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.4.14 Device Status Registers 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4.15 Device Status Registers 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4.16 Device Status Registers 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2 TQFP48-EP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4/73 DocID023504 Rev 7

L99ASC03 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Wake-up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Diagnostics overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Forced VBAT standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Operation junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. Power-on RESET (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Voltage regulator VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15. NRES reset output (VDD supervision), NINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 16. Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 18. Gate driver for external MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 19. Drain source monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20. VS, VSREG, VSMS and Tj monitoring (AOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. Current-sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 22. Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 23. BEMF detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 24. I/Os; IHx, ILx, DIS, BC, BEMF, DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 25. INH input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 26. CSN input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 27. SCK, SDI input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 28. SDO output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 29. SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 30. SPI pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 31. Operation codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 32. Device application access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 33. Device information read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 34. Address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 35. Device information read access operation code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 36. Device information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 37. Complete device SPI register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 38. TQFP48-EP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 39. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

DocID023504 Rev 7 5/73

5
List of figures L99ASC03

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Supply voltage operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Watchdog in normal operation mode (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Watchdog in normal operation mode (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Watchdog in Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Watchdog in failure mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Operating mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Temperature modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. CPLOW and NRDY bit behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. HARDOFF functionality by using internal dead time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. HARDOFF functionality by using external dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Persistent watchdog failure (VBAT Standby Mode entered after 15 watchdog faults). . . . . 29
Figure 14. Persistent TSD2 failure (VBAT Standby Mode entered after 7 VDD turn-offs) . . . . . . . . . . . 29
Figure 15. Watchdog timing (Long, Early, Late and Safe Window) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. Watchdog missing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17. Watchdog early, late and safe window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18. Cross-current protection time generation when IHx and ILx are tied together . . . . . . . . . . 39
Figure 19. Cross-current protection time generation when at tDT > tCCP is provided an input. . . . . . . 40
Figure 20. SPI – timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 21. SPI global status register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22. SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 23. SDI frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 24. SDO frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 25. BEMF detection stepping of BEMFCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 26. TQFP48-EP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6/73 DocID023504 Rev 7

L99ASC03 Block diagram and pin descriptions

1 Block diagram and pin descriptions

Figure 1. Block diagram

VBAT
R
100kΩ

CCP1 CCP2 RCP

Ignition / 220nF 220nF 10kΩ
Klemme 15 VBAT CTANK
1μF
VS
CP1+ CP1- CP2+ CP2- CP
C* CVS
100nF

VS
Central 2 Step Charge Pump
EMC optimized „Spread Spectrum“
L99ASC03
VSREG
RINH
10kΩ Undervoltage Temperature
CVSREG
Overvoltage Det. Prewarning
C* & Temperature
100nF
* Size according application Shutdown VSMS
requirements (Voltage dropout
test, warm cranking, …) Control Logic VCP VSMS

INH Wake up GH3

CINH From GH2
Control
100nF Sleep mode Gate
DIS GH1
Driver
IH1 HS SH3
IL1 20k
Diagnosis SH2
IH2 MOSFET VCP SH1
IL2 Control GL3
IH3 Control
Gate GL2
IL3 Driver GL1
LS 20k SL1
Diagnosis x3 SL2
SCK SL3
SPI
CSN Programmable
Interface
SDI VDSTH & tDead
BLDC Motor
SDO Programmable Gain & Shutdown
Window Watchdog
x3
BC BEMF
Detection
FS_FLAG
STM8A
AOUT T Juntion
AMUX CSI+
VS Monitoring
CSO +
RSense
BEMFOUT - CSI-
DOUT
DMUX
VDD AGND
DAC
VSREG CSA
NRES 100k

5V Voltage
Regulator
VDD (and Reset)
Note: This is a very simplified example of
NINT an application circuit. The function must be
verified in the real application. The
external componant values should be used
as guidline only.

SGND1 SGND2 SGND3

GAPGCFT00013

Table 2. Pin definition and function

Pin number Symbol Function I/O type

1 SL3 Source of external low-side MOSFET 3 I/O

2 CSI+ Current-sense amplifier positive input I
3 CSI- Current-sense amplifier negative input I
4 SGND2 Signal Ground 2 GND
5 CSO Current-sense amplifier output O
6 IL3 Input of low-side switch 3 I
7 IH3 Input of high-side switch 3 I
8 IL2 Input of low-side switch 2 I
9 IH2 Input of high-side switch 2 I
10 IL1 Input of low-side switch 1 I
11 IH1 Input of high-side switch 1 I

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72
Block diagram and pin descriptions L99ASC03

Table 2. Pin definition and function (continued)

Pin number Symbol Function I/O type

12 SGND1 Signal ground 1 GND

13 SDI SPI Serial data input I
14 SCK SPI clock input I
15 SDO SPI Serial data output O
16 CSN SPI Chip Select Not input I
17 BC Block Commutation Sync Pin I
18 DIS Disable input I
19 NRES NReset output O
20 AOUT Analog multiplexer output O
21 BEMFOUT Back EMF output O
22 DOUT Digital multiplexer output O
23 NINT Interrupt output O
24 SGND3 Signal ground 3 GND
Not to be
25 Reserved Pin must be kept not connected
connected
26 AGND Analog ground GND
27 VDD Voltage regulator output O
Not to be
28 Reserved Pin must be kept not connected
connected
29 INH Inhibit input (wake-up) I
30 VSREG Voltage regulator power supply I
31 VS Charge pump power supply I
32 CP1- Charge pump pin for capacitor 1, negative side O
33 CP1+ Charge pump pin for capacitor 1, positive side O
34 CP2- Charge pump pin for capacitor 2, negative side O
35 CP2+ Charge pump pin for capacitor 2, positive side O
36 CP Charge pump output O
37 VSMS Motor supply sense pin I
38 GH1 Gate of external high-side MOSFET 1 O
39 SH1 Source of external high-side MOSFET 1 I/O
40 GL1 Gate of external low-side MOSFET 1 O
41 SL1 Source of external low-side MOSFET 1 I/O
42 GH2 Gate of external high-side MOSFET 2 O
43 SH2 Source of external high-side MOSFET 2 I/O
44 GL2 Gate of external low-side MOSFET 2 O

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L99ASC03 Block diagram and pin descriptions

Table 2. Pin definition and function (continued)

Pin number Symbol Function I/O type

45 SL2 Source of external low-side MOSFET 2 I/O

46 GH3 Gate of external high-side MOSFET 3 O
47 SH3 Source of external high-side MOSFET 3 I/O
48 GL3 Gate of external low-side MOSFET 3 O

Figure 2. Pin connection (top view)

VSMS
GH1
GH3

GH2
SH3

SH2

SH1
GL1
GL3

GL2
SL2

SL1
45

37
48

40
47

46

44

43

42
41

39

38
SL3 1 36 CP
TQFP48-EP
CSI+ 2 35 CP2+
CSI- 3 34 CP2-
SGND2 4 L99ASC03 33 CP1+
CSO 5 32 CP1-
IL3 6 Leadframe 31 VS
IH3 7 & 30 VSREG
IL2 8 Slug 29 INH
IH2 9 28 Reserved
IL1 10 27 VDD
IH1 11 26 AGND
SGND1 12 25 Reserved
16

24
13

21
14

15

17

18

19
20

22

23
SDI
SCK
SDO
CSN
BC
DIS
NRES
AOUT
BEMFOUT
DOUT
NINT
SGND3

GAPGCFT00654

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72
Device description L99ASC03

2 Device description

2.1 Supply pins (VS, VSREG, VSMS)

The device has three different supply input pins. VS and VSREG have to be protected against
negative voltages, while VSMS is robust against negative voltages.
The two-stage charge pump is supplied from VS. External capacitors are used to achieve
high current capability of the charge pump. The gate drivers (for both high-side and low-side
MOSFETs) are supplied from the charge pump to ensure full drive of the external
MOSFETs.
The internal power-on reset (POR) circuitry and the VDD voltage regulator are supplied from
the VSREG pin. Some external protection has to be provided in the application for VS and
VSREG to prevent the capacitor connected to these pins from being discharged by negative
transients or low input voltage.
VSMS is used to monitor the power supply of the external MOSFETs and as a reference for
the BEMF detection.

2.1.1 VS, VSREG and VSMS overvoltage warning

In case any of the supply inputs reach the overvoltage warning threshold, the corresponding
overvoltage warning flag is set. This flag can be cleared by an SPI “Read & Clear” command
provided that the cause of the warning is no longer present.

2.1.2 VS, VSREG and VSMS overvoltage

In case any of the supply inputs reach the overvoltage threshold, the corresponding
overvoltage flag is set. This flag can be cleared by an SPI “Read & Clear” command
provided that the cause of the overvoltage is no longer present.
In case of VS and VSMS overvoltage, the gate drivers are disabled, along with other
functions (for further details see Table 5). VSREG overvoltage is used only for information.

2.1.3 VS, VSREG and VSMS undervoltage

In case any of the supply inputs reach the undervoltage threshold, the corresponding
undervoltage flag is set. This flag can be cleared by an SPI “Read & Clear” command
provided that the cause of the undervoltage is no longer present.
The Vs, VSMS and VSREG undervoltage flags are used only for information.

2.2 VDD (5V) voltage regulator

The device integrates a fully protected low-drop voltage regulator, which is designed for very
fast transient response.
The voltage regulator provides a 5 V output and a continuous load current up to 200 mA to
supply external devices (e.g.an external microcontroller). In addition, this regulator powers
the internal 5 V loads such as the I/O pins and the current-sense amplifier (CSA). The
voltage regulator is protected against overload and overtemperature. The output voltage is

10/73 DocID023504 Rev 7

L99ASC03 Device description

stable for output capacitor greater/eqaul than 660 nF (ESR < 50 mΩ) close to the device. An
additional external capacitor up to 47 µF is permitted.
In case of a short circuit to GND on VDD when VDD is turned on (VDD < VDDFAIL for at least
4 ms), the device automatically enters the VBAT Standby Mode and the VDDFAIL flag is set.
Reactivation of the device is possible through a wake-up event. The VDDFAIL flag can be
cleared by an SPI “Read & Clear” command, once the short circuit is removed and the
device leaves the VBAT Standby Mode.

2.3 NRES reset output

In case the VDD regulator is turned on and its output voltage rises above the VDD reset
threshold, the reset pin NRES is pulled up to VDD by an internal pull-up resistor after a delay
equal to tRP (typ. 2 ms).
A reset pulse is generated if:
• VDD drops below the VDD reset threshold (VRT1 or VRT2, configurable by SPI through
the VDD_VTH bit). In this case, the VDDUV flag is also set and can be cleared by an SPI
"Read & Clear" command, once the VDD rises back above the programmed VDD_UV
threshold.
• a watchdog failure occurs.

Figure 3. Supply voltage operation summary

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DocID023504 Rev 7 11/73

72
Device description L99ASC03

2.4 Watchdog
A window watchdog is integrated in the device. The watchdog supervises the operation of
the external microcontroller in Active Mode and, if the ICMP bit is set to ‘0’ and IVDD > ICMP,
also in VDD Standby Mode.
When the device powers up and the NRES pin is released, the watchdog is started with a
long open window (typ. 65 ms). The microcontroller has to write the WDTRIG bit to ‘1’ within
this time in order to terminate the long open window and start the window watchdog. After
that, the watchdog has to be serviced properly by alternating the logic value written to the
WDTRIG bit within the watchdog open window. A correct watchdog trigger immediately
starts the next cycle.
After eight consecutive watchdog failures, the VDD regulator is turned off for a time equal to
tVDDoff (typ. 200 ms). In case seven additional and consecutive watchdog failures occur, the
VDD regulator is completely turned off and the device enters VBAT Standby Mode.
A watchdog failure causes a reset pulse at the NRES pin and the deactivation of the gate
drivers (fail-safe condition, for further details see Table 5).
When the device is in Flash Mode, the watchdog is disabled. Besides even in VDD Standby
Mode with ICMP = 1 the WDG is always disabled. If the WDDIS bit is set to ‘1’ in Flash Mode
and then a transition to Active Mode occurs, the watchdog remains disabled in Active Mode
until the next POR.
After a WDG failure event, after a VDD_UV event or after a wake event from VBAT Standby
Mode the watchdog starts again in LOW mode. Once properly toggled the WDGTRIG bit,
writing the same WDGTRIG bit value anywhere within the WDG window does not generate
any WDG failure event.

Figure 4. Watchdog in normal operation mode (part 1)

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12/73 DocID023504 Rev 7

L99ASC03 Device description

Figure 5. Watchdog in normal operation mode (part 2)

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DocID023504 Rev 7 13/73

72
Device description L99ASC03

Figure 7. Watchdog in failure mode

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2.5 Device operating modes

The device can be operated in four different modes:
• Active Mode
• Flash Mode
• VDD Standby Mode
• VBAT Standby Mode

2.5.1 Active Mode

The device operates with all its functions being available (VDD regulator, watchdog, gate
drivers, etc).

2.5.2 Flash Mode

To program the system microcontroller, the L99ASC03 can be operated in Flash Mode
where the internal watchdog is disabled and the other functions (see Table 3) remain
available. Flash mode is entered by applying on the BC pin a voltage higher than VBC,rising;
to guarantee the proper behavior of the device, the rising VBC slope must not exceed
10 V/µs.
In case VBC = VBC,rising during device power-up (VSREG connecting to VBAT), it has to be
assured that the SDI pin is at GND level (VSDI < 1.3 V, no external pull-up).

14/73 DocID023504 Rev 7

L99ASC03 Device description

2.5.3 VDD Standby Mode

When the device is in VDD Standby Mode, the gate drivers, the charge pump and the CSA
are disabled (SPI activation or INH pin will act as a wake-up). To supply the microcontroller
in a low-power mode, the VDD voltage regulator remains active. After any wake-up event,
the device switches to Active Mode and a negative pulse (typ. 56 µs) is generated on NINT
pin.
The transition from Active Mode to VDD Standby Mode is selected through the STBYSEL
and the GOSTBY bits.

2.5.4 VBAT Standby Mode

When in VBAT Standby Mode, the VDD voltage regulator is turned off to achieve the lowest
current consumption and the device monitors the occurrence of a wake-up event. After any
wake-up event, the device transitions to Active Mode. The internal SPI register content is
preserved.
The transition from Active Mode to VBAT Standby Mode is selected through the STBYSEL
and the GOSTBY bits. This transition can also occur in case of persistent fault conditions.

DocID023504 Rev 7 15/73

72
Device description L99ASC03

2.5.5 Device mode state diagram

Figure 8. Operating mode transitions

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16/73 DocID023504 Rev 7

L99ASC03 Device description

2.5.6 Functional overview

Table 3. Functional overview

Operating mode

Function Active mode

VDD VBAT
FLASH mode
standby standby
Normal Fail-safe
(1)
VDD voltage regulator ON ON ON OFF
Reset generator ON ON ON OFF
Interrupt generator OFF OFF ON ON
Window watchdog ON OFF OFF(2) OFF
Gate driver ON OFF ON OFF OFF
Charge pump ON OFF ON OFF OFF
CSA ON OFF ON OFF OFF
BEMF module ON OFF ON OFF OFF
Oscillator ON ON OFF(3) OFF(3)
Diagnostics ON ON OFF(4) OFF
1. OFF in case Tj > TSD2
2. ON when IVDD > ICMP and SPI bit ICMP = 0
3. ON during wake-up event, temperature and ICMP filtering
4. Temperature, ICMP monitoring and VDD undervoltage detection are active

2.6 DIS pin

The DIS pin allows turning off the gate drivers when applying an external signal to it. A logic
low signal enables the gate drivers, whereas a logic high signal disables the gate drivers.
The state of the DIS pin is reported in the DISABLE flag. To activate the gate drivers, the
DIS pin has to be pulled low and the DISABLE flag has to be cleared by an SPI "Read &
Clear" command. An internal pull-up resistor is integrated for this pin.

2.7 INH pin

The INH pin can be used as a wake-up source connected to ignition through an external
resistor. An internal comparator detects a high level and generates a wake-up event. The
INHST bit reflects the current logic state of this pin.

2.8 Thermal warning and thermal shutdown

To allow for different application requirements, two temperature modes with their respective
diagnostics can be selected via SPI.

DocID023504 Rev 7 17/73

72
Device description L99ASC03

2.8.1 Normal mode: TEMPM = ‘0’ (TW1, TSD1, TSD2)

If the junction temperature reaches the TW1 threshold, the TW1 flag is set and latched as a
thermal warning for the external microcontroller. In case the junction temperature increases
and reaches the TSD1 threshold, the gate drivers and the charge pump are disabled and
the TSD1/TW2 flag is set and latched. If the junction temperature rises further and reaches
the TSD2 threshold, the VDD regulator is also turned off to reduce power dissipation and the
TSD2 flag is set and latched. A counter (VDDR bits) is increased upon the VDD turn-off.
After a time equal to tTSD, the VDD regulator is turned on again. If the VDDR bits reach the
'111' state, the device is forced into VBAT Standby Mode. This mode is left upon any wake-
up event.
The TW1, TSD1/TW2 and TSD2 flags can all be cleared by an SPI Read & Clear command,
provided that the junction temperature is below the respective temperature threshold.

2.8.2 Warning mode: TEMP = ‘1’ (TW1, TW2, TSD2)

If the junction temperature reaches the TW1 threshold, the TW1 flag is set and latched as a
first thermal warning for the external microcontroller. In case the junction temperature
increases and reaches the TW2 threshold, the TSD1/TW2 flag is set and latched as a
second thermal warning. If the junction temperature rises further and reaches the TSD2
threshold, the gate drivers and the charge pump are disabled, the VDD regulator is turned
off to reduce power dissipation and the TSD2 flag is set and latched. A counter (VDDR bits)
is increased upon the VDD turn-off. After a time equal to tTSD, the VDD regulator is turned
on again. If the VDDR bits reach the '111' state, the device is forced into VBAT Standby
Mode. This mode is left upon any wake-up event.
The TW1, TSD1/TW2 and TSD2 flags can all be cleared by an SPI Read & Clear command,
provided that the junction temperature is below the respective temperature threshold.

18/73 DocID023504 Rev 7

L99ASC03 Device description

Figure 9. Temperature modes

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DocID023504 Rev 7 19/73

72
Device description L99ASC03

2.9 Wake-up events

A wake-up event in standby mode generates a transition to Active Mode. Three possible
wake-up sources are defined, as illustrated in Table 4.

Table 4. Wake-up events

Wake-up source Description

CSN pin low and first rising edge on SCK pin, active only in VDD
SPI Access
Standby Mode
INH High level on the INH pin, active in both standby modes

All wake-up events from VDD Standby Mode generate a low-pulse on NINT pin for
56 μs (typical).

2.10 Charge pump

The two-stage charge pump is supplied from the VS pin. External charging capacitors are
used to achieve a high current capability of the charge pump. In VBAT Standby Mode, VDD
Standby Mode or after thermal shutdown the charge pump is disabled. It is also possible to
disable the charge pump by setting the CPDIS bit to "1".
In case the charge pump output voltage remains below the VCPLOW threshold for longer
than tfCP, all gate drivers are switched off (resistive path to source) and the CPLOW flag is
set and latched. The NRDY flag shows that the charge pump is not ready after a startup
condition.
In order to minimize electromagnetic emissions, the charge pump frequency can be
modulated in a programmable range through the WOBM and WOBF bits.

Figure 10. CPLOW and NRDY bit behavior

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2.11 Gate drivers

Each of the three half-bridge drivers is controlled independently by dedicated inputs for the
high-side driver (IHx, active low, with internal pull-up resistor) and for the low-side driver
(ILx, active high, with internal pull-down resistor). All the gate drivers feature a minimum
cross-current protection time (dead-time) tCCP (programmable through the CCT bits) and

20/73 DocID023504 Rev 7

L99ASC03 Device description

shoot-through protection. The minimum tCCP is applied between outputs GHx and GLx only
if a lower (or null) dead-time is present between inputs ILx and IHx (see Figure 18). In case
the IHx and the ILx input of a half bridge are active at the same time, both gate driver
outputs (high side and low side) are turned off. In addition, if IHx and ILx are both driven
active for longer than tCCP, the affected half bridge is disabled and the ST(x) error flag is set.
To re-enable the half bridge, this fault condition has to be removed and the corresponding
ST(x) flag has to be reset through an SPI "Read & Clear" command.
The gate driver circuit limits the gate-source voltage of the external MOSFETs. All gate
driver circuits are independent of each other and use their source connection to the external
MOSFET as a reference.
In order to drive different MOSFETs and adjust the gate currents according to external
conditions (e.g. temperature), the source and sink current (i.e. the charging and discharging
current) of the gate driver can be programmed via SPI.
The HARDOFF feature is an additional measure against cross-current conduction in a half
bridge. When the HOFFCONT bit is set to 0, any of the outputs GHx and GLx is switched off
using maximum sink current (max PCSI) after a tCCP from related turn-off command. When
the HOFFCONT bit is set to 1, any of the outputs GHx and GLx is switched off using
maximum sink current (max PCSI) as soon as the complementary output signal
(respectively GLx or GHLx) goes to high.

Figure 11. HARDOFF functionality by using internal dead time

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DocID023504 Rev 7 21/73

72
Device description L99ASC03

Figure 12. HARDOFF functionality by using external dead time

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2.12 Drain-source monitoring

2.12.1 Drain-source monitoring in ON state (short-circuit detection)

The drain-source voltage of each activated external MOSFET is monitored by internal
comparators to detect short circuits to ground or battery. In case the voltage drop over the
external MOSFET exceeds the threshold voltage VSCd, the corresponding DSHS(x) or
DSLS(x) flag is set. In addition, if the DSFT_DIS bit is set to "0", the affected MOSFET is
turned off and the related gate driver is disabled.
The drain-source monitoring has a filter time and is only active when the corresponding gate
driver is in source condition.
The threshold voltage VSCd can be programmed in four steps between 0.5 V and 2 V via
SPI.

2.12.2 Drain-source monitoring in OFF state (open-load / short-circuit

detection)
In Active Mode, each gate driver sources a current of typ. 500 µA at the SHx pins in OFF
condition. By programming the ISTEST(x) bits to "1", a sink current of typ. 800 µA is applied
to the corresponding pin.
By using these internal test currents, an open load, a leakage to GND or to battery can be
detected on each motor phase in OFF state, i.e. without turning on the external MOSFETs.
If the ISTEST_EN bit is set to "1", the drain-source voltage monitoring is enabled also in
OFF condition and the Status Register 7 reflects the result of the voltage comparison (i.e.
drain-source voltage below or above the programmed threshold) in real time (i.e. the status
bits are not latched) and without setting the FE bit in the Global Status Byte. See
Section 2.18: Diagnostics for more details about diagnostics.

22/73 DocID023504 Rev 7

L99ASC03 Device description

In order to allow the SHx pins to go below GND, the current sink has a diode in series and
the sink current will disappear below 0.8V. Therefore, when using the test currents, the
drain-source voltage threshold should be programmed to a value greater than 0.8V.

2.13 Current-sense amplifier

The current-sense amplifier (CSA) is designed for low-side current measurement in
automotive motor control applications. The CSA differential input stage measures the
voltage generated by the motor current over an external shunt resistor. The input common-
mode range allows the CSA input pins to go below GND, as typically required in PWM motor
control applications due to switching transients. The CSA gain can be programmed over a
wide range by setting the GCSA bits.
In case of zero differential input voltage, the output voltage is at half scale:
VCSO = 0.5 * VDD

2.14 Overcurrent detection

To protect the application from overcurrent, an overcurrent threshold can be programmed
via SPI by setting the OCTH bits. The CSA output is compared to the programmed
threshold. In case of overcurrent, the CSAOC flag is set and, depending on the DMUX bit,
the DOUT output goes high. In addition, if the OCSHUTD bit is set, the gate drivers are
disabled.
The overcurrent detection feature can be used to estimate the rotor position of the motor at
standstill without any rotation by applying voltage to the motor windings and detecting
overcurrent with respect to an appropriate threshold.

2.15 BEMF module

The programmable BEMF (back electromotive force) module integrated in the device
provides a flexible means to support those applications where the BLDC motor is driven in
sensorless mode and that are based on BEMF detection.

2.15.1 BEMF comparator

Depending on the PWM driving method used in the application, three different comparators
can be selected through the BEMFMOD bits to detect the BEMF zero-crossing point. BEMF
detection can be done during the PWM ON state or the PWM OFF state. In the former case,
the VSMS/2 comparator (i.e. internally referenced to half of the VSMS supply) can be used. In
the latter case, the GND comparator (i.e. internally referenced to GND) or the VSMS
comparator (i.e. internally referenced to the VSMS supply) can be used, depending on
whether the PWM signal is applied to the external high-side or low-side MOSFET (this
reflects the setting of the BEMFSW bit).
As some applications may require advancing the timing of a phase commutation (“pre-
commutation”), it is possible to add an offset to the internal reference voltage of the VSMS/2
comparator. The absolute offset value can be programmed through the BEMFOS bits. To
achieve pre-commutation, the offset sign (i.e. positive or negative) has to vary, depending
on whether the BEMF is rising or falling. The offset sign can be selected via SPI by
programming the BEMFSIGN bit.

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2.15.2 BEMF comparator sampling

In order to avoid unwanted commutations of the BEMF comparator due to PWM switching
and spurious noise on the motor phases, an intelligent sampling mechanism is implemented
to detect the BEMF zero-crossing point. Depending on the BEMFSW bit (PWM switching
mode), BEMFMOD bit (comparator selection) and BEMFPOL bit, it is possible to select the
triggering instant used to sample and latch the output of the selected BEMF comparator,
which is in turn made available at the BEMFOUT pin. The following cases are possible:
• PWM on high-side MOSFET
– BEMF detection in PWM ON state, BEMF sampling on PWM switch turn-off
– BEMF detection in PWM OFF state, BEMF sampling on PWM switch turn-on or
complementary PWM switch turn-off
• PWM on low-side MOSFET
– BEMF detection in PWM ON state, BEMF sampling on PWM switch turn-off
– BEMF detection in PWM OFF state, BEMF sampling on PWM switch turn-on or
complementary PWM switch turn-off
It is worth noting that this method allows having a stabilized BEMF signal at the motor phase
before the phase voltage can change, thanks to the turn-on and turn-off delay associated to
the gate driver and the external MOSFET.
If no PWM is applied to the motor (100% duty cycle), the output of the BEMF comparator
can be sampled by using an internal clock edge. In this case, the BEMFBY bit has to be set.

2.15.3 BEMF commutation driving mode

The BEMFCNT bits are used to set the motor phase to be monitored by the BEMF
comparator. According to BEMFCM bit value, BEMFCNT bits can be either programmed
through SPI by the system microcontroller or automatically updated by L99ASC03.
In particular:
• If BEMFCM = '0', the external microcontroller is intended to update BEMFCNT bits
through SPI command every time the BEMF comparator has to monitor another motor
phase.
• If BEMFCM = '1', the BMFCNT bits are automatically increased (if BEMFDIR = '0') or
decreased (if BEMFDIR = '1') whenever the L99ASC03 receives a triggering pulse on
BC pin. In order to properly operates, triggering pulse amplitude on BC pin must be
coherent with Vin H (see Table 24) electrical parameter.

2.16 Digital multiplexer (DOUT)

An integrated digital multiplexer provides a digital signal on the DOUT pin. Depending on
the setting of the DMUX bit and of the OCFT_DIS bit, it is possible to select between a fail-
safe flag signal, a CSA overcurrent flag signal or the overcurrent comparator output.

2.17 Analog multiplexer (AOUT)

By setting the AMUX bits via SPI, an integrated analog multiplexer provides an output
voltage proportional to the input supply voltages (VS, VSREG or VSMS), to the internal chip
temperature Tj or to the CSA reference voltage.

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2.18 Diagnostics
All diagnostic functions are internally filtered and each fault/warning condition has to be
valid for a defined time before the corresponding status bit is set in the status register. The
filters are used to improve the noise immunity of the device. Several error types and
warnings can be distinguished. All errors and warnings are reported in the corresponding
status bits and are mirrored in the associated bits of the Global Status Byte (GSB).
• The device reacts to several error types by changing its state. The different error types
can be grouped as follows:
• fail-safe errors (mirrored in the FS bit of the GSB)
• device errors (mirrored in the DE bit of the GSB)
• functional errors (mirrored in the FE bit of the GSB)
• physical-layer errors (mirrored in the PLE bit of the GSB)
• SPI errors (mirrored in the SPIE bit of the GSB)
In order for the device to recover from an error condition, the error itself must be removed
and the associated status bit in the device has to be cleared via SPI by a “Read & Clear”
command.
Warning functions are intended only for information and will not change the state of the
device. Warnings are mirrored in the GW bit of the GSB. To clear a warning, the source of
the warning must be removed and the associated flag has to be cleared via SPI by a “Read
& Clear” command.

Table 5. Diagnostics overview

Clear error /
Source Cause Event type Diagnosis Device action
warning flag

– After NRES is
– NRES asserted low
released,
– Gate drivers
write
actively discharged; WDTRIG = 1
charge pump, CSA during
Watchdog not
FSWD = 1; and BEMF module
triggered or FS (FS = 1 in the watchdog
MCU Watchdog fail OFF long open
triggered out of the GSB)
counter WDF>0 – Control registers window to
open window
(except Control reset WDF
Register 1 and counter bits
DSFT_DIS) reset to
– Read & Clear
default value FSWD

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Table 5. Diagnostics overview (continued)

Clear error /
Source Cause Event type Diagnosis Device action
warning flag

– Gate drivers
actively discharged;
charge pump, CSA
and BEMF module
Short circuit at VDD FS (FS = 1 in the OFF Read & Clear
VDDFAIL = 1
turn-on GSB) – Control registers VDDFAIL
(except Control
Register 1 and
DSFT_DIS) reset to
default value
– NRES asserted low
– Gate drivers
VDD actively discharged;
charge pump, CSA
Undervoltage and BEMF module
FS (FS = 1 in the Read & Clear
(VDD < reset VDDUV = 1 OFF
GSB) VDDUV
threshold) – Control registers
(except Control
Register 1 and
DSFT_DIS) reset to
default value
Undervoltage
warning GW (GW = 1 in Read & Clear
VRT2LOW = 1 – None
(VDD_VTH = 0 and the GSB) VRT2LOW
VDD < VRT2)
– Gate drivers
actively discharged;
charge pump, CSA
and BEMF module
FS and SPIE OFF
SPI_DI = 1 and
SDI short circuit to (FS = 1 and – Control registers Read & Clear
SPIE = 1 in the
GND or VDD SPIE = 1 in the (except Control SPI_DI
GSB
GSB) Register 1 and
SPI DSFT_DIS bits)
reset to default
value
– SPI frame ignored
GW and SPIE
CSN timeout or SPI_FL = 1 and
(GW = 1 and Read & Clear
SCK clock count SPIE = 1 in the SPI frame ignored
SPIE = 1 in the SPI_FL
other than 0 or 16 GSB
GSB)

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L99ASC03 Device description

Table 5. Diagnostics overview (continued)

Clear error /
Source Cause Event type Diagnosis Device action
warning flag

VS undervoltage DE (DE = 1 in the Read & Clear

VSUV = 1 None
(VS < VSUV) GSB) VSUV
Gate drivers actively
VS overvoltage DE (DE = 1 in the Read & Clear
VSOV = 1 discharged; charge
(VS > VSOV) GSB) VSOV
pump disabled
Gate drivers actively
VSMS overvoltage DE (DE = 1 in the Read & Clear
VSMSOV = 1 discharged; charge
(VSMS > VSMSOV) GSB) VSMSOV
pump disabled

Input supply VSREG or VSMS

Read & Clear
undervoltage GW (GW = 1 in VSREGUV = 1 or
None VSREGUV or
(VSREG < VSREGUV the GSB) VSMSUV = 1
VSMSUV
or VSMS < VSMSUV)
VSREG overvoltage GW (GW = 1 in Read & Clear
VSREGOV = 1 None
(VSREG > VSREGOV) the GSB) VSREGOV
Read & Clear
VS, VSREG or VSMS VSOVW = 1 or
GW (GW = 1 in VSOVW,
overvoltage VSREGOVW = 1 None
the GSB) VSREGOVW or
warning or VSMSOVW = 1
VSMSOVW
FE (FE = 1 in the Gate drivers actively Read & Clear
DIS pin DIS pin at logic high DISABLE = 1
GSB) discharged DISABLE
– GW (GW = 1 in
the GSB) if
OCSHUTD = 0 Gate drivers actively
Read & Clear
CSA Overcurrent CSAOC = 1 discharged if
– FE (FE = 1 in CSAOC
OCSHUTD = 1
the GSB) if
OCSHUTD = 1
– GW (GW=1 in
the GSB) if
DSFT_DIS=1 Affected gate driver Read & Clear
Drain-source DSLS(x) = 1 or
actively discharged if DSLS(x) or
monitor threshold – FE (FE=1 in DSHS(x) = 1
Gate drivers DSFT_DIS = 0 DSHS(x)
the GSB) if
DSFT_DIS=0
Shoot-through FE (FE = 1 in the Affected half-bridge Read & Clear
ST(x) = 1
protection activated GSB) actively discharged ST(x)

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Table 5. Diagnostics overview (continued)

Clear error /
Source Cause Event type Diagnosis Device action
warning flag

GW (GW = 1 in Read & Clear

Tj > TW1 TW1 = 1 None
the GSB) TW1
Read & Clear
GW (GW = 1 in TW1 = 1
Tj > TW2 None TSD1/TW2 (and
the GSB) TSD1/TW2 = 1
TW1)
Gate drivers actively
Read & Clear
DE (DE = 1 in TW1 = 1 discharged; charge
Tj > TSD1 TSD1/TW2 (and
the GSB) TSD1/TW2 = 1 pump, CSA and
TW1)
BEMF module OFF

Temperature – Gate drivers

actively discharged;
charge pump, CSA
and BEMF module
OFF
TW1 = 1
FS (FS = 1 in the – Control registers Read & Clear
Tj > TSD2 TW2/TSD1 = 1
GSB) (except control TSD2
TSD2 = 1
register 1 and
DSFT_DIS bit)
reset to default
value
– VDD turned off
- GW (GW = 1 in
Charge pump
the GSB) if
undervoltage
CPLOWM = 0 Gate drivers disabled Read & Clear
(VCP<VCPLOW) CPLOW = 1
- FE (FE = 1 in if CPLOWM = 1 CPLOW
when charge pump
the GSB) if
running
CPLOWM = 1
Charge pump
- GW (GW = 1 in
Charge pump the GSB) if Gate drivers disabled
undervoltage CPLOWM = 0 regardless of
(VCP<VCPLOW) NRDY = 1 Self cleared
- FE (FE = 1 in CPLOWM control bit
after charge pump
the GSB) if value
is enabled
CPLOWM = 1

Some specific fail-safe errors will force the device to transition to VBAT Standby Mode in
order to avoid potential damage to the system. Table 6 provides an overview of these cases.
The device leaves the VBAT Standby Mode upon any wake-up event.

Table 6. Forced VBAT standby mode

Source Cause Diagnosis Clear error flag

Watchdog not triggered or

triggered out of the open window
MCU FSWD = 1 Read & Clear FSWD
for 15 consecutive times
(WDF = 1111)

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L99ASC03 Device description

Table 6. Forced VBAT standby mode

Source Cause Diagnosis Clear error flag

VDD Short circuit at VDD turn-on VDDFAIL = 1 Read & Clear VDDFAIL
Tj>TSD2 for 7 times
Temperature TSD2 = 1 Read & Clear TSD2
(VDDR = 111)

Figure 13. Persistent watchdog failure (VBAT Standby Mode entered after 15 watchdog faults)

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Figure 14. Persistent TSD2 failure (VBAT Standby Mode entered after 7 VDD turn-offs)

tTSD
VDD

t
Forced
VBAT Standby

Counter 1 2 3 4 5 6 7

2.19 Serial peripheral interface (ST SPI standard)

A 16-bit ST SPI is used for bi-directional communication with an external microcontroller.
Through SPI it is possible to trigger the watchdog, control the operating modes, adjust some
device parameters and read out diagnostic information of several device modules.
During standby modes, the SPI is generally deactivated.
The SPI has to be driven in the following mode:

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CPOL = 0 and CPHA = 0.

For this mode, input data are sampled on the low-to-high transition of the clock SCK and
output data are changed on the high-to-low transition of SCK.
This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible
output pins and one input pin will be needed to communicate with the device. A fault
condition can be detected by setting CSN to low. If CSN = 0, the SDO pin will reflect the
global error flag (fault condition) of the device.
• Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (SDO) will be in high-impedance state. In case CSN is stuck at GND, a
timeout is implemented which sets the SDO back to high-impedance to release the SPI
network. A low signal activates the output driver and a serial communication can be
started. The state during CSN = 0 is called a communication frame.
• Serial Data In (SDI)
The input pin is used to transfer data serially into the device. The data applied to the
SDI will be sampled on the rising edge of the SCK signal and shifted into an internal 16-
bit shift register. On the rising edge of the CSN signal, the contents of the shift register
will be transferred to Data Input Register. The writing to the selected Data Input
Register is only enabled if exactly 16 bits are transmitted within one communication
frame (CSN low). Only frames with 0 or 16 clock pulses are accepted. All others will be
ignored and a communication error will be reported with the next SPI command. This
safety function is implemented to avoid activating of the output stages in case of a
wrong communication frame.
Note: Due to this safety functionality, SPI daisy chaining is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC’s is
recommended.
• Serial Data Out (SDO)
The data output driver is activated by a logical low level at the CSN input and will go
from high impedance to a low or high level, depending on the global error flag (fault
condition). The first rising edge of the SCK input after a high-to-low transition of the
CSN pin will transfer the content of the selected status register into the data out shift
register. Each subsequent falling edge of the SCK will shift the next bit out.
• Serial Clock (SCK)
The SCK input is used to synchronize the input and output serial bit streams. The data
input (SDI) is sampled on the rising edge of the SCK and the data output (SDO) will
change with the falling edge of the SCK signal. The SPI can be driven with a SCK
frequency up to 4.5 MHz.

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3 Electrical specifications

3.1 Absolute maximum ratings

Table 7. Absolute maximum ratings
Symbol Parameter Value Unit

VSREG Voltage regulator power supply voltage -0.3 to 40 V

VS Charge pump power supply voltage -0.3 to 40 V
VSMS (1)
Sensed motor supply voltage -5 to 40 V
VDD Stabilized supply voltage -0.3 to 6 V
VIHX, VILX Gate driver control voltage range -0.3 to VDD V
VSLX, VSHX Source signal voltage range -5 to 40(1) V
VGLX -5 to VSLX + 15(1) V
Gate signal voltage range
VGHX -5 to VSHX + 15(1) V
VCSIP, VCSIN Current sense amplifier input voltage range -5 to VDD(1) V
Current sense amplifier output voltage range;
VCSO, VAOUT -0.3 to VDD V
analog output MUX
VCP1-, VCP2- HV signal range -0.3 to VS V
VCP1+, VCP2+,
HV signal range VS - 0.3 to VS + 17 V
VCP
VSDI, VSCK,
SPI logic I/O voltage range -0.3 to VDD V
VSDO
VTXD, VRXD/NINT,
VDIS, VNRESET,
Logic I/O voltage range -0.3 to VDD V
VDOUT, VBEMF,
VCSN
VINH High Voltage Logic I/O voltage range -0.3 to 40 V
VBC High Voltage Logic I/O voltage range -0.3 to 20 V
1. -7 V for < 1.5 µs transients

Note: All maximum ratings are absolute ratings. Exceeding any these values may cause an
irreversible damage of the integrated circuit!

3.2 Operating range

Table 8. Operating range
Symbol Parameter Value Unit

VSREG Voltage regulator power supply voltage 6 to 28 V

VS Charge pump power supply voltage 6 to 28 V

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Table 8. Operating range (continued)

Symbol Parameter Value Unit

VSMS Sensed motor supply voltage 6 to 28 V

VCSIP, VCSIN Current sense amplifier input voltage range -1 to 1 V
VSDI, VSCK, VCSN SPI logic input voltage range 0 to VDD V
VTXD, VDIS, VINH Logic input voltage range 0 to VDD V

3.3 ESD protection

Table 9. ESD protection
Parameter Value Unit

HBM all pins ±2 kV

CDM all pins ±500 V
CDM corner pins ±750 V
MM ±200 V

Note: HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-D

HBM with all unzapped pins grounded

3.4 Thermal data

Table 10. Operation junction temperature
Symbol Parameter Test condition Min. Typ. Max. Unit

Tstg Storage temperature -55 150 °C

Tj Operating junction temperature -40 150 °C
Dynamic junction temperature
TJ_Peak 160 °C
100hrs over lifetime(1)
Rth j-amb Thermal resistance to ambient(2) 33 °C/W
Rth j-case Thermal resistance to case 12 °C/W
1. According to the mission profile.
2. IC soldered on 2s2p PCB thermally enhanced.

Table 11. Temperature warning and thermal shutdown

Symbol Parameter Test condition Min. Typ. Max. Unit

TW1 Temp. warning threshold 1 TEMPM = X 120 135 150 °C

TW2 Temp. warning threshold 2 TEMPM = 1 °C
140 155 170
TSD1 Thermal shutdown threshold 1 TEMPM = 0 °C
TSD2 Thermal shutdown threshold 2 TEMPM = X 160 175 190 °C

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Table 11. Temperature warning and thermal shutdown

Symbol Parameter Test condition Min. Typ. Max. Unit

TSDH Thermal shutdown hysteresis 5 °C

tTW/TSD Thermal filter time 16 µs

3.5 Electrical characteristics

Voltages are referred to ground and currents are assumed positive, when the current flows
into the pin. The device is operated in the specified operating range, unless otherwise
specified.

Table 12. Supply and supply monitoring

Symbol Parameter Test condition Min. Typ. Max. Unit

VSOVW,
VSREGOVW, Overvoltage warning threshold 18 20 22 V
VSMSOVW
VSOV,
VSREGOV, Overvoltage threshold 28.1 30 32 V
VSMSOV
VSOVH,
VSREGOVH, Overvoltage hysteresis 2 V
VSMSOVH
VSUV,
VSREGUV, Under-voltage threshold VS, VSREG, VSMS decreasing 5.2 5.5 5.7 V
VSMSUV
VSUVH,
VSREGUVH, Undervoltage hysteresis 0.4 V
VSMSUVH
tfVS, tfVREG, Overvoltage and undervoltage
30 80 µs
tfVSMS filter time
VS = VSREG = VSMS = 12 V;
IS Current consumption 5 10 mA
active mode; open outputs
VS = VSREG = VSMS = 12 V;
ISREG Current consumption 15 25 mA
active mode; open outputs
VS = VSREG = VSMS = 12 V;
VBAT standby (no wakeup); 20 µA
TTest = -40°C to 25°C; open outputs

ISREGQ + ISQ VS quiescent supply current VS = VSREG = VSMS = 12 V;

VDD standby;
SCK = INH = SDI = ILx = 0; 60 µA
CSN = DIS = IHx = 1;
TTest = -40°C to 25°C; open outputs

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Table 12. Supply and supply monitoring (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

VS = VSREG = VSMS = 12 V;
ISMS VSMS DC input current 2 mA
active mode; SLx vs. GND
VS = VSREG = VSMS = 12 V;
ISMSQ VSMS quiescent input current INH = 0; TTest = -40°C to 25°C; 10 µA
open outputs

Table 13. Power-on RESET (VSREG)(1)

Symbol Parameter Test condition Min. Typ. Max. Unit

VPORSREG,rising Threshold (VSREG increasing) 4.5 V

VPORSREG,falling Threshold (VSREG decreasing) 3 4 V
VPORSREG,hyst Hysteresis 0.3 V
1. All outputs open

Table 14. Voltage regulator VDD

Symbol Parameter Test condition Min. Typ. Max. Unit

VDD Output voltage 5.0 V

ILOAD = 0 mA to 200 mA;
Output voltage tolerance,
VDD 6 V < VS < 18 V; -2 2 %
active mode
-40 °C < Tj < 25 °C
Output voltage tolerance, ILOAD = 0 mA to 200 mA; full
VDD -3.5 3.5 %
active mode temperature range
20 µA to 50 mA;
VDD ± 2%; CEXT = 47 µF; 250 µs
Startup settling time from VDD dI/dt = 50 mA/µs
tSST(1) standby to Active mode (no
NRES) 20 µA to 100 mA;
VDD ± 2.5%; CEXT = 47 µF; 130 µs
dI/dt = 100 mA/µs
ILOAD = 50 mA; VSREG = 4.5 V 0.2 0.4 V
VDP Drop-out Voltage
ILOAD = 100 mA; VSREG = 4.5 V 0.3 0.5 V
IDD Output current in active mode Max. continuous load current 200 mA
VSREG > 6 V; VDD > VRT2;
IDDinrush(1) Inrush current capability 200 mA
CEXT ≥ 4.7 µF
IDDpeak Peak output current VSREG > 6 V; VDD > VRT2 300 mA
IDDshort Short circuit output current Current limitation 300 600 950 mA
VDD deactivation time after
tTSD 0.8 1.0 1.5 s
thermal shutdown
Current comparator rising
ICMPRISE Rising current 3.6 4.6 mA
threshold
Current comparator falling
ICMPFALL Falling current 2.0 3.4 mA
threshold

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Table 14. Voltage regulator VDD (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

ICMPH Current comparator hysteresis 0.2 mA

VDD short to ground during
VDDFAIL VDD fail threshold 1.8 2 2.2 V
startup
VDD short to ground detection VDD short to ground during
tVDDFAIL 3.4 4.0 7.0 ms
time startup
CCER = 680 nF; CELE = 47 µF;
I(VDD) = 10 mA. Slope from
0.5 V to 1 V and slope from 1 V
to 0.9 * VDD.
dVDD/dt dVDD/dt at regulator turn-on 3 30 V/ms
If current limitation is reached,
the slope is controlled by the
current limitation and output
capacitor.
CCER = 680 nF; CELE = 47 µF;
Maximum VDD output voltage
VDDso,max I(VDD) = 10 mA. Internal soft- 5.3 V
at regulator turn-on
start function
Power supply rejection ratio Vr = 0.5 Vpp; fr = 100 Hz;
PSRR(1) 60 dB
(specified by design) CCER = 680 nF
1. Guaranteed by design.

Table 15. NRES reset output (VDD supervision), NINT

Symbol Parameter Test condition Min. Typ. Max. Unit

VDD increasing; VDD_VTH = 0 3.55 3.7 3.85 V

VRT1 VDD reset threshold 1
VDD decreasing; VDD_VTH = 0 3.15 3.3 3.45 V
VDD reset threshold 1
VRT1H 0.4 V
hysteresis
VDD increasing; VDD_VTH = 1 4.45 4.65 4.8 V
VRT2 VDD reset threshold 2 VVDD decreasing;
4.4 4.6 4.75 V
VDD_VTH = 1
VDD reset threshold 2
VRT2H 0.06 V
hysteresis
VRESETL NRES pin low output voltage VDD > 1 V; IRESET = 1 mA 0.2 0.4 V
NRES pull up internal
RRESET 60 110 204 kΩ
resistor
tRR NRES reaction time At ILOAD = 1 mA 20 µs
tRP NRES pulse time 1.7 2 3.5 ms
tVDDoff VDD turn-off time 200 ms
tVDDUV VDD undervoltage filter time 13 28 µs
tNINT NINT pulse time 56 µs

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Table 16. Watchdog

Symbol Parameter Test condition Min. Typ. Max. Unit

tLOW Long open window 48 65 70 ms

tCW Closed window 2.6 4.7 ms
tWDP Watchdog period 16 23 ms

Figure 15. Watchdog timing (Long, Early, Late and Safe Window)

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L99ASC03 Electrical specifications

Figure 17. Watchdog early, late and safe window

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Table 17. Charge pump output

Symbol Parameter Test condition Min. Typ. Max. Unit

VS = 6 V; ICP = -20 mA;

VS + 7.7 V
CCPx = 220 nF; CCP = 1 µF
VS = 6 V; ICP = 20 mA;
VCP Charge pump output voltage CCPx = 220 nF; CCP = 1 µF; VS + 8.3 V
-40 °C < Tj < 25 °C
VS = 12 V; ICP = 0 mA;
VS + 11 VS + 13 VS + 16.5 V
CCPx = 220 nF; CCP = 1 µF
VS = 12 V; VCP = VS + 10 V;
ICP Charge pump output current 20 mA
CCPx = 220 nF; CCP = 1 µF
Charge pump low voltage
VCPLOW VS + 5.6 VS + 6.0 VS + 6.75 V
threshold
Clock frequency (internal
fCP 140 200 260 kHz
oscillator)
tfCP Charge pump low filter time 6 14 µs

Table 18. Gate driver for external MOSFET

Symbol Parameter Test condition Min. Typ. Max. Unit

High-side gate drivers DC parameter

Turn-on maximum peak

Tj = 25°C; PCSO = 1111 -250 mA
current (SOURCE stage)
IGHx(on)
Turn-on minimum peak
Tj = 25°C; PCSO = 0001 -20 mA
current (SOURCE stage)

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Table 18. Gate driver for external MOSFET (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Turn-off maximum peak VSHx = 0 V; PCSI = 1111;

500 mA
current (SINK stage) Tj = 25°C
IGHx(off)
Turn-off minimum peak VSHx = 0 V; PCSI = 0001;
40 mA
current (SINK stage) Tj = 25°C
VS = 6 V; ICP = 20 mA VSHx + 7 V
VGHxH High-level voltage
VS = 12 V; ICP = 20 mA VSHx + 9 VSHx + 11 VSHx + 13 V
Gate-source passive
RGSHx 16 20 24 kΩ
discharge resistance

Low-side driver DC parameter

Turn-on maximun peak

Tj = 25°C; PCSO = 1111 -185 mA
current (SOURCE stage)
IGLx(on)
Turn-on minimum peak
Tj = 25°C; PCSO = 0001 -12 mA
current (SOURCE stage)
Turn-off maximun peak VSLx = 0 V; PCSI = 1111;
700 mA
current (SINK stage) Tj = 25°C
IGLx(off)
Turn-off minimum peak VSLx = 0 V; PCSI = 0001;
40 mA
current (SINK stage) Tj = 25°C
VS = 6 V; ICP = 20 mA VSLx + 7 V
VGLxH High-level voltage
VS = 12 V; ICP = 20 mA VSLx + 9 VSLx + 11 VSLx + 13 V
Gate-source passive
RGSLx 16 20 24 kΩ
discharge resistance

Gate drivers dynamic parameters

Propagation delay time, low to

VS = 12 V; CG = 10 nF 300 700 ns
high
tPGXxLH
Propagation delay time, high
VS = 12 V; CG = 10 nF 100 170 ns
to low
Propagation delay time,
tPGXx VS = 12 V; CG = 10 nF 115 ns
channel difference
tGXxR Rise time (20% to 80%) VS = 12 V; CG = 10 nF 250 ns
tGXxF Fall time (80% to 20%) VS = 12 V; CG = 10 nF 150 ns
CCT = 000 100 200 ns
CCT = 001 300 400 ns
CCT = 010 500 600 ns

Programmable cross-current CCT = 011 700 800 ns

tCCP
protection time CCT = 100 900 1000 ns
CCT = 101 1200 1300 ns
CCT = 110 1600 1700 ns
CCT = 111 2000 2100 ns

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Timings are measured at 20% and 80% for falling and rising transitions.

Figure 18. Cross-current protection time generation when IHx and ILx are tied together

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Electrical specifications L99ASC03

Figure 19. Cross-current protection time generation when at tDT > tCCP is provided an input

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Table 19. Drain source monitoring

Symbol Parameter Test condition Min. Typ. Max. Unit

VSCd1 Drain-source voltage threshold 1 DSMTH = 00 0.4 0.5 0.6 V

VSCd2 Drain-source voltage threshold 2 DSMTH = 01 0.9 1.0 1.1 V
VSCd3 Drain-source voltage threshold 3 DSMTH = 10 1.35 1.5 1.65 V
VSCd4 Drain-source voltage threshold 4 DSMTH = 11 1.85 2.0 2.15 V
tb1 Blanking time DS Monitor DSMFT = 0 1.0 1.2 1.5 µs
tb2 Blanking time DS Monitor DSMFT = 1 2.0 2.4 3.0 µs
tf1 Filter time DS Monitor DSMFT = 0 1.0 1.2 1.5 µs
tf2 Filter time DS Monitor DSMFT = 1 2.0 2.4 3.0 µs
Diagnostic source current All gate drivers off; ISTEST(x) = 0 -500 µA
ISHx
Diagnostic sink current All gate drivers off; ISTEST(x) = 1 1 mA

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Table 20. VS, VSREG, VSMS and Tj monitoring (AOUT)

Symbol Parameter Test condition Min. Typ. Max. Unit

VSxOUT VSxOUT voltage ratio AOUT sinking/ sourcing 2 mA 0.106 0.125 0.144
VTROOM TSENSE output voltage (5 * VBE) VS = 12 V, Tj = 25°C — 3.7 — V
ΔV/ΔTj Temperature coefficient Tj = -40°C to 130°C — -7.85 — mV/°C

Table 21. Current-sense amplifier

Symbol Parameter Test condition Min. Typ. Max. Unit

CSA DC parameters

A20 DC gain GCSA = 00 18.4 19.6 20.4

A30 DC gain GCSA = 01 29.4 30 30.6
(1)
A70 DC gain GCSA = 10 67.9 70 72.1
A100 (1) DC gain GCSA = 11 97.5 100 102.5
ΔAX/ΔTj Gain temperature drift 100 ppm/°C
VIO Input offset voltage -200 mV < CSI- < 1 V -3.5 3 mV
VICM Common-mode input voltage range -1 1 V
VCSOH Output high level IL = -1 mA VDD - 0.2 V
VCSOL Output low level IL = 1 mA 0.2 V
VCS-IL=0 Output level at ILOAD = 0 CSI+ = CSI-; ICSO = 0 VDD / 2
ICSO Current output capability 2 mA

CSA dynamic parameters

SR Slew rate VCSO 10% to 90% RL = 10 kΩ; CL = 100 pF 2 V/µs

RL = 10 kΩ; CL = 100 pF;
tset Recovery time VCSO = 95% Vdiff: 1 V step to 100 mV; 3 µs
Gain = 20
Input common mode rejection ratio VICM = 0.7 * sin (2*π*0.1 MHz
CMRR(1) 60 dB
20 * log ((VICM / ΔVCSO) * AX) )
1. Guaranteed by design.

Table 22. Overcurrent detection

Symbol Parameter Test condition Min. Typ. Max. Unit

Minimum output overcurrent

VoOCMIN OCTH = 00001 140 mV
threshold voltage(1)
Maximum output overcurrent
VoOCMAX OCTH = 11111 2.35 V
threshold voltage(1)
tfOC Overcurrent filter time 4 6 µs
1. Positive threshold referred to VDD/2.

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Table 23. BEMF detection

Symbol Parameter Test condition Min. Typ. Max. Unit

Comparator threshold VSMS = 12 V; VSMS / 2 VSMS / 2

VBEMFx VSMS / 2 V
of VSMS / 2 comparator BEMFMOD = 1 - 0.13 + 0.13
Minimum comparator VSMS = 12 V;
0.0025 *
ΔVBEMFx offset of VSMS / 2 BEMFMOD = 1; mV
VSMS
comparator BEMFOS = 001
Maximum comparator VSMS = 12 V;
0.16 * VSMS 0.16 * 0.16 * VSMS
ΔVBEMFx offset of VSMS / 2 BEMFMOD = 1; V
- 0.13 VSMS + 0.13
comparator BEMFOS = 111
VSMS = 12 V;
Comparator threshold
VBEMFx BEMFMOD = 0; -0.1 0 0.1 V
of GND comparator
BEMFSW = 0
VSMS = 12V;
Comparator threshold
VBEMFx BEMFMOD = 0; VSMS - 0.1 VSMS VSMS + 0.1 V
of VSMS comparator
BEMFSW = 1
tCOMP Comparator delay time (VSMS ± 200 mV) / 2 2 µs

Table 24. I/Os; IHx, ILx, DIS, BC, BEMF, DOUT

Symbol Parameter Test condition Min. Typ. Max. Unit

Vin L Input low level 1.6 V

Vin H Input high level 1.8 5.5 V
Vin Hyst Input hysteresis 0.4 V
Threshold for entering Flash
VBC,rising 11.4 12.4 13.5 V
Mode, rising voltage
Threshold for entering Flash
VBC,falling 10.9 11.9 13.0 V
Mode, falling voltage
RDIS Pull up resistor at input DIS,
50 100 200 kΩ
RIHx IHx

RBC Pull down resistor at input BC,

50 100 200 kΩ
RILx ILx

tdDIS(1) Activation delay time 4.5 µs

VBEMFL
Output low level ILOAD = 1 mA 0.2 0.4 V
VDOUTL
VBEMFH VDD -
Output high level ILOAD = -1 mA V
VDOUTH 0.4 V

IBEMF
Current output capability 2 mA
IDOUT
CI(1) Input capacitance 10 pF
CO (1)
Output capacitance 30 pF
1. Not tested guaranteed by design.

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Table 25. INH input

Symbol Parameter Test condition Min. Typ. Max. Unit

ITH Current threshold 80 120 µA

IPD Pull-down current VIN = 12 V 30 70 µA
IH Current hysteresis 5 10 20 µA
tAMIN Minimum activation time 55 110 µs

3.6 SPI electrical characteristics

Table 26. CSN input
Symbol Parameter Test condition Min. Typ. Max. Unit

Vin,L Input voltage low level 1.3 V

Vin,H Input voltage high level 2.0 VDD V
Vin,Hyst Input hysteresis 0.4 V
RCSN CSN pull-up resistor 50 100 200 kΩ

Table 27. SCK, SDI input

Symbol Parameter Test condition Min. Typ. Max. Unit

Switching from standby

to active mode. Time
Delay time from standby
tset until output drivers are 160 300 µs
to active mode
enabled after CSN going
to high.
Vin,L Input voltage low level 1.3 V
Vin,H Input voltage high level 2.0 VDD V
Vin,Hyst Input hysteresis 0.4 V
Pull-down resistor at SCK
RSCK, RSDI 50 100 200 kΩ
and SCI

Table 28. SDO output

Symbol Parameter Test condition Min. Typ. Max. Unit

VSDOL Output low level ISDO = 1 mA 0.2 0.4 V

VSDOH Output high level ISDO = -1 mA VDD - 0.4 V
ISDOLK Output leakage current VSDO = VDD -1 1 µA

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Table 29. SPI timing

Symbol Parameter Test condition Min. Typ. Max. Unit

fSCK Serial clock frequency 4.5 MHz

CSN falling until SDO
tCSNQV Cout = 50 pF 100 ns
valid
CSN rising until SDO
tCSNQT Cout = 50 pF 150 ns
tristate
SCK falling until SDO
tSCKQV Cout = 50 pF 90 ns
valid
CSN setup time before
tSCSN 100 ns
SCK rising
SDI setup time before
tSSDI 40 ns
SCK rising
SDI hold time after SCK
tHSDI 40 ns
rising
tHSCK Minimum SCK high time 105 ns
tLSCK Minimum SCK low time 105 ns
tHCSN Minimum CSN high time 4 µs
SCK setup time before
tSSCK 100 ns
CSN rising
SDO rise time
tr SDO COUT = 50 pF; ILOAD = -1 mA 50 100 ns
(20 % / 80 %)
SDO fall time
tf SDO COUT = 50 pF; ILOAD = 1 mA 50 100 ns
(20 % / 80 %)
tCSNTimeout CSN low timeout 65 ms

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Figure 20. SPI – timing

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4 ST-SPI Protocol

4.1 Physical layer

Table 30. SPI pin description

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4.1.1 Signal description

Chip Select Not (CSN)
The communication interface is deselected, when this input signal is logically high. A falling
edge on CSN enables and starts the communication while a rising edge finishes the
communication and the sent command is executed when a valid frame was sent. During
communication start and stop the Serial Clock (SCK) has to be logically low. The Serial Data
Out (SDO) is in high impedance when CSN is high or a communication timeout was
detected.

Serial Clock (SCK)

This SCK provides the clock of the SPI. Data present at Serial Data Input (SDI) is latched on
the rising edge of Serial Clock (SCK) into the internal shift registers while on the falling edge
data from the internal shift registers are shifted out to Serial Data Out (SDO).

Serial Data Input (SDI)

This input is used to transfer data serially into the device. Data is latched on the rising edge
of Serial Clock (SCK).

Serial Data Output (SDO)

This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (SCK).

4.1.2 Clock and data characteristics

A microcontroller with its SPI peripheral running in following mode can driven ST-SPI:
CPOL = 0 and CPHA = 0.

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Figure 22. SPI signal description

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The communication frame starts with the falling edge of the CSN (Communication Start).
SCK has to be low.
The SDI data is then latched at all following rising SCK edges into the internal shift registers.
After Communication Start the SDO will leave tristate mode and present the MSB of the data
shifted out to SDO. At all following falling SCK edges data is shifted out through the internal
shift registers to SDO.
The communication frame is finished with the rising edge of CSN. If a valid communication
took place (e.g. correct number of SCK cycles), the requested operation by the OpCode will
be performed (Write or Clear operation).

4.2 Protocol

4.2.1 SDI frame

The Data-In Frame consist of 16 bits (OpCode+Address+Data).
The first two transmitted bits (MSB, MSB-1) contain the Operation Code, which represents
the instruction which will be performed. The following 6 bits (MSB-2 to MSB-7) represent the
address on which the operation will be performed.
The subsequent byte contains the payload data.

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Figure 23. SDI frame

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Operating codes

Table 31. Operation codes

OC1 OC0 Description

0 0 Write operation
0 1 Read operation
1 0 Read & Clear operation
1 1 Read Device information

The operating code is used to distinguish between different access modes to the registers of
the slave device.
A Write Operation writes the payload data to the addressed register if a write access is
allowed (e.g. Control Register, valid data). In addition, the content of the addressed register
(the data present at Communication Start) is shifted out on the SDO pin.
A Read Operation shifts out the data present in the addressed register at Communication
Start. The payload data is ignored and internal data are not modified. In addition a Burst
Read can be performed.
A Read & Clear Operation will lead to a clear of addressed status bits. The bits to be cleared
are defined first by address, second by payload bits set to ‘1’. In addition, the content of the
addressed register (the data present at Communication Start) is shifted out on the SDO pin.
Status registers that change their status during a communication frame could be cleared by
an ongoing Read & Clear Operation and would be reported neither in the ongoing
communication frame nor in the next communication frame. To avoid missing information
about any status change, it is recommended to clear the status bits that have been already
reported in previous communication frames (Selective Bitwise Clear).

Address
Following the OpCode bits, the six Address bits are a fixed part of the communication frame.
The six bits, in combination with the OpCode, allow access to a 2 x 64-wide address range.

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Table 32. Device application access

Operating code

OC1 OC0

0 0
0 1
1 0

Table 33. Device information read access

Operating code

OC1 OC0

1 1

Table 34. Address range

Address Data Type Address Data Type

3FH Advanced operation code 3FH Advanced operation code

3EH R/W or C 3EH <GSB options> R
...
11H <WD type> R
10H R

03H <Device number 2> R

02H <Device number 1> R
01H <Device family> R
00H R/W or C 00H <Company code> R

The data contained in the Device Information address range is predefined by the ST-SPI
Standard v4.0. The data is read only and represent device specific data like Device ID, SPI
settings and Watchdog information. For details, please refer to Section 4.3.1

Advanced operation codes

Two Advanced Operation Codes can be used to set all control registers to the default value
and to clear all status registers.
A 'set all control registers to default' command is performed when an OpCode '11' at
address b'111111 is performed.
The Device Register 1 and DSFT_DIS bit are not cleared with this command and hold their
content.
A 'clear all status registers' command is performed when an OpCode '10' at address
b'111111 is performed.

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Data-in payload
The Payload is the data transferred to the slave device with every SPI communication
frame. The Payload always follows the OpCode and the Address bits.
For write accesses, the Payload represents the new data written to the addresses registers.
For Read & Clear operations, the Payload indicates the clear of a Status Register in case of
a '1' in the corresponding bit position.
For a Read Operation the Payload is not used. For functional safety reasons it is
recommended to set unused Payload to '0'.

4.2.2 SDO frame

The Data-Out Frame consist of 16 bits (GSB+Data).
The first eight transmitted bits contain device status information and are latched into the shift
register at the time of the Communication Start. These 8 bits are transmitted at every SPI
transfer.
The subsequent byte contains the payload data and is latched into the shift register on the
eighth positive SCK edge. This could lead to an inconsistency of data between the GSB and
Payload due to different shift register load times. Anyhow, no unwanted Status Register
clear should appear, as status information should just be cleared with a dedicated bit clear
after read.

Figure 24. SDO frame

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Data-out payload
The Payload is the data transferred from the slave device to the microcontroller with every
SPI communication frame. The Payload always follows the OpCode and the Address bits of
the frame that is currently being sent (In-Frame Response).

4.3 Addresses and data definition

4.3.1 Device information registers

The Device Information Registers can be read by using OpCode ‘11’. After shifting out the
GSB, the 8-bit payload is transmitted.

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Table 35. Device information read access operation code

Operating code

OC1 OC0

1 1

Table 36. Device information registers

Address Data Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

3FH <Advanced option>

3EH <GSB options> R 0 0 0 0H
... ... 00H
20H <SPI CPHA test> R 0 1 0 1 0 1 0 1
1FH <WD bit pos. 14>opt. R 00H
... ... R 00H
14H <WD bit pos. 2>opt. R C0H
13H <WD bit pos. 1>opt. R 41H
12H <WD type 2> R 99H
11H <WD type 1> R 49H
10H <SPI mode> R 90H
... ... R 00H
0AH <Silicon version> R 0H 0H
09H <Device number 8> R 00H
... ... R 00H
04H <Device number 3> R 10H
03H <Device number 2> R 49H
02H <Device number 1> R 55H
01H <Device family> R 01H
00H <Company code> R 00H

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4.4 SPI registers

Table 37. Complete device SPI register table
Address

Register name Bit number Mode

15 14 13 12 11 10 9 8
Global status byte GSBN RSTB SPIE PLE FE DE GW FS R

7 6 5 4 3 2 1 0
0x01 Device Control Reg. 1 WDDIS CPDIS TEMPM ICMP VDD_VTH STBYSEL GOSTBY WDTRIG R/W

0x02 Device Control Reg. 2 BEMFCM BEMFDIR BEMFMOD BEMFPOL BEMFSW DSMFBT DSMTH(1) DSMTH(0) R/W

0x03 Device Control Reg. 3 BEMFSIGN BEMFOS(2) BEMFOS(1) BEMFOS(0) BEMFBY BEMFCNT(2) BEMFCNT(1) BEMFCNT(0) R/W

0x04 Device Control Reg. 4 PCSO(3) PCSO(2) PCSO(1) PCSO(0) PCSI(3) PCSI(2) PCSI(1) PCSI(0) R/W

0x05 Device Control Reg. 5 DMUX AMUX(2) AMUX(1) AMUX(0) WOBM WOBF Reserved Reserved R/W

0x06 Device Control Reg. 6 GCSA(1) GCSA(0) OCSHUTD OCADC(4) OCADC(3) OCADC(2) OCADC(1) OCADC(0) R/W

0x07 Device Control Reg. 7 HOFFCONT CCT(2) CCT(1) CCT(0) CPLOWM ISTEST(3) ISTEST(2) ISTEST(1) R/W

0x08 Device Control Reg. 8 — — — — — DSFT_DIS ISTEST_EN OCFT_DIS R/W

0x11 Device Status Reg. 1 CPLOW NRDY DISABLE INHWAKE SPIWAKE Reserved DEVST(1) DEVST(0) R/C

0x12 Device Status Reg. 2 SPI_DI Reserved Reserved Reserved INHST VRT2LOW VDDUV VDDFAIL R/C

0x13 Device Status Reg. 3 WDF(3) WDF(2) WDF(1) WDF(0) FSWD WD75% WD50% WD25% R/C

0x14 Device Status Register 4 — VDDR(2) VDDR(1) VDDR(0) — TSD2 TSD1/TW2 TW1 R/C

0x15 Device Status Register 5 — VSOV VSOVW VSUV — VSREGOV VSREGOVW VSREGUV R/C

0x16 Device Status Register 6 ST(3) ST(2) ST(1) CSAOC SPI_FL VSMSOV VSMSOVW VSMSUV R/C

0x17 Device Status Register 7 — — DSLS(3) DSHS(3) DSLS(2) DSHS(2) DSLS(1) DSHS(1) R/C

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4.4.1 SPI Control Registers

Global status byte

15 14 13 12 11 10 9 8
GSBN RSTB SPIE Reserved FE DE GW FS

Type: R

Bit Bit description

[15] GSBN: GlobaleStatusByte Not
The GSBN bit is a logically NOR combination of Bit 8 to Bit 14. This bit can also be used as
Global Status Flag without starting a complete communication frame, as it is present at SDO
immediately after pulling CSN low.
[14] RSTB: Reset Bit
The RSTB bit indicates a device POR. In case this bit is set, all internal Control Registers are
set to default and kept in that state until the bit is cleared. It is automatically cleared by any valid
SPI communication.
[13] SPIE: SPI Error
The SPIE bit is a logical OR combination of errors related to a wrong SPI communication
(wrong SCK count, CSN time-out and SDI stuck at errors). The SPIE is automatically cleared by
a valid SPI communication.
[12] Reserved
[11] FE: Functional Error
The FE bit is a logical OR combination of errors caused by specific events. Functional errors
turn into sink mode all or specific gate driver blocks.
[10] DE: Device Error
The DE bit is a logical OR combination of errors related to device specific blocks. Device Errors
lead to the turn-off of specific functional blocks.
[9] GW: Global Warning
The GW bit is a logical OR combination of warning flags implemented in the device. Warning do
not have any effects at all on the device.
[8] FS: Fail Safe
The FS bit is a logical OR combination of errors caused by specific events. Fail-safe Errors lead
to the turn-off of specific functional blocks. All Device Control Registers are set to their default
values, except Device Control Register 1 and DSFT_DIS bit.

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4.4.2 Device Control Register 1

Device Control Register 1

7 6 5 4 3 2 1 0
Bit name WDDIS CPDIS TEMPM ICMP VDD_VTH STBYSEL GOSTBY WDTRIG
Default values 0 0 0 0 1 0 0 0

Address: 0x1
Type: R/W
Description: In this register, device operating information is stored. This register is not set to
default in case of fail-safe errors.

Bit Bit description

[7] WDDIS: WatchDog DISable (writable in FLASH mode only)
0: window watchdog enabled
1: window watchdog disabled
[6] CPDIS: Charge Pump DISable
0: charge pump enabled
1: charge pump disabled
[5] TEMPM: TEMPerature Mode selector
0: TW1 / TSD1 / TSD2 are active
1: TW1 / TW2 / TSD2 are active
[4] ICMP: VDD load current monitoring in VDD Standby Mode
0: monitoring enabled. The watchdog is disabled in VDD Standby Mode only if IVDD < ICMP
1: monitoring disabled. The watchdog is always disabled in VDD Standby mode
[3] VDD_VTH: VDD undervoltage monitoring reset threshold
0: low threshold selected
1: high threshold selected
[2] STBYSEL: STandBY SELect
0: VBAT Standby mode
1: VDD Standby mode
[1] GOSTBY: Go to Standby
0: no action
1: go-to-standby command (this bit is automatically cleared upon state transition).
[0] WDTRIG: WatchDog TRIGger Bit
Watchdog trigger bit (for a detailed description, please refer to Section 2.4).

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4.4.3 Device Control Register 2

Device Control Register 2

7 6 5 4 3 2 1 0
Bit name BEMFCM BEMFDIR BEMFMOD BEMFPOL BEMFSW DSMFBT DSMTH(1) DSMTH(0)
Default values 0 0 0 0 0 0 0 0

Address: 0x2
Type: R/W
Description: In this register static BEMF parameters and the drain-source monitoring parameters
are set.

Bit Bit description

[7] BEMFCM: BEMFCNT updating source selection
0: The BEMFCNT can be updated only via SPI
1: The BEMFCNT can be updated only via positive pulses applied at the BC input pin
[6] BEMFDIR: BEMFCNT update direction (active only if BEMFCM = 1)
0: BEMFCNT increased at each positive pulse at the BC input pin
1: BEMFCNT decreased at each positive pulse at the BC input pin
[5] BEMFMOD: BEMF comparator selection
0: BEMF GND comparator (if BEMFSW = 0) used for BEMF detection
0: BEMF VSMS comparator (if BEMFSW = 1) used for BEMF detection
1: BEMF VSMS/2 comparator used for BEMF detection
[4] BEMFPOL: BEMF sampling point selection (active only if BEMFMOD=0)
0: BEMF detection upon turn-on of the PWM switch
1: BEMF detection upon turn-off of the complementary PWM switch
[3] BEMFSW: PWM switching method to drive the external MOSFET in a half bridge
0: PWM signal applied on HS
1: PWM signal applied on LS
[2] DSMFBT: drain-source monitoring filter and blanking time
0: 1.2 µs blanking and filter time selected
1: 2.4 µs blanking and filter time selected
[1:0] DSMTH: Drain Source Monitor threshold
00: 0.5 V
01: 1.0 V
10: 1.5 V
11: 2.0 V

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4.4.4 Device Control Register 3

Device Control Register 3

7 6 5 4 3 2 1 0
Bit name BEMFSIGN BEMFOS(2) BEMFOS(1) BEMFOS(0) BEMFBY BEMFCNT(2) BEMFCNT(1) BEMFCNT(0)
Default values 0 0 0 0 0 0 0 0

Address: 0x3
Type: R/W
Description: In this register, dynamic BEMF parameters are set.

Bit Bit description

[7] BEMFSIGN: offset sign for BEMF VSMS/2 comparator
0: threshold of BEMF VSMS/2 comparator increased by offset
1: threshold of BEMF VSMS/2 comparator decreased by offset
[6:4] BEMFOS: Offset Selection for BEMF VSMS/2 comparator
000: BEMF offset = 0 V
001: BEMF offset = 0.0025 * VSMS
010: BEMF offset = 0.005 * VSMS
011: BEMF offset = 0.01 * VSMS
100: BEMF offset = 0.02 * VSMS
101: BEMF offset = 0.04 * VSMS
110: BEMF offset = 0.08 * VSMS
111: BEMF offset = 0.16 * VSMS
[3] BEMFBY: BEMF comparator output sampling source selection
0: BEMF comparator output sampled on PWM edge, depending on BEMFMOD, BEMFPOL and
BEMFSW
1: BEMF comparator output sampled by internal system clock
[2:0] BEMFCNT: BEMF motor-phase/step counter (see Figure 25)

Switch where Switch always on BEMF monitored

Step
PWM is applied at pin

Not used (phase multiplexer is OFF)

000

001 1 GH1 or GL1 GL2 or GH2 SH3

010 2 GH1 or GL1 GL3 or GH3 SH2
011 3 GH2 or GL2 GL3 or GH3 SH1
100 4 GH2 or GL2 GL1 or GH1 SH3
101 5 GH3 or GL3 GL1 or GH1 SH2
110 6 GH3 or GL3 GL2 or GH2 SH1
111 Not used (phase multiplexer is OFF)

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Figure 25. BEMF detection stepping of BEMFCNT

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4.4.5 Device Control Register 4

Device Control Register 4

7 6 5 4 3 2 1 0
Bit name PCSO(3) PCSO(2) PCSO(1) PCSO(0) PCSI(3) PCSI(2) PCSI(1) PCSI(0)
Default values 0 0 0 0 0 0 0 0

Address: 0x4
Type: R/W
Description: In this register, the current for charging and discharging the gates of the external
MOSFETs can be selected.

Bit Bit description

[7:4] PCSO: peak source current of gate drivers.
0000: PCSO = 0 mA
0001: PCSO = 15 mA
0010: PCSO = 25 mA
.....
1111: PCSO = 215 mA
[3:0] PCSI: Peak SInk Current of gate drivers.
0000: PCSI = 0 mA
0001: PCSI = 40 mA
0010: PCSI = 60 mA
.....
1111: PCSI = 600 mA

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4.4.6 Device Control Register 5

Device Control Register 5

7 6 5 4 3 2 1 0
Bit name DMUX AMUX(2) AMUX(1) AMUX(0) WOBM WOBF Reserved Reserved
Default values 0 0 0 0 0 0 0 1

Address: 0x5
Type: R/W
I

Bit Bit description

[7] DMUX: digital multiplexer output
0: FS flag selected
1: OC flag selected. In case the OCFT_DIS bit in Control Register 8 is "1", then the DOUT pin
reflects directly the overcurrent comparator output and the CSAOC bit in Status Register 6 is not
set if an overcurrent event occurs.
[6:4] AMUX: analog multiplexer output
000: OFF
001: 1/8 VS
010: 1/8 VSREG
011: 1/8 VSMS
100: TJ
101: CSA reference voltage
110: CSA reference voltage is muxed to AOUT and CSO pins at the same time
111: not used
[3] WOBM: charge pump frequency modulation
0: frequency modulation enabled
1: frequency modulation disabled
[2] WOBF: charge pump modulation frequency
0: 16 kHz
1: 32 kHz
[1] Reserved, keep default value [0]
[0] Reserved

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4.4.7 Device Control Register 6

Device Control Register 6

7 6 5 4 3 2 1 0
Bit name GCSA(1) GCSA(0) OCSHUTD OCADC(4) OCADC(3) OCADC(2) OCADC(1) OCADC(0)
Default values 0 0 1 0 0 0 0 0

Address: 0x6
Type: R/W

Bit Bit description

[7:6] GCSA: CSA gain
00: 20
01: 30
10: 70
11: 100
[5] OCSHUTD: overcurrent shutdown
0: gate drivers are not deactivated in case of overcurrent (global warning reported)
1: gate drivers are deactivated in case of overcurrent (functional error reported)
[4:0] OCADC: overcurrent threshold
00000: OFF
00001: 150 mV
00010: 220mV
00011: 300mV
00100: 370 mV
00101: 440 mV
00110: 520 mV
00111: 590 mV
01000: 660 mV
01001: 740 mV
01010: 800 mV
01011: 880 mV
01100: 960 mV
01101: 1.03 V
01110: 1.1 V
01111: 1.18 V
10000: 1.25 V
10001: 1.32 V
10010: 1.39 V
10011: 1.47 V
10100: 1.54 V
10101: 1.61 V
10110: 1.68 V
10111: 1.76 V
11000: 1.84 V
11001: 1.9 V
11010: 1.98 V
11011: 2.05 V
11100: 2.13 V
11101: 2.2 V
11110: 2.28 V
11111: 2.35 V

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4.4.8 Device Control Register 7

Device Control Register 7

7 6 5 4 3 2 1 0
Bit name HOFFCONT CCT(2) CCT(1) CCT(0) CPLOWM ISTEST(3) ISTEST(2) ISTEST(1)
Default values 0 1 1 1 1 0 0 0

Address: 0x7
Type: R/W

Bit Bit description

[7] HOFFCONT: HARDOFF control
0: the full current discharge capability is activated when programmed cross-current time has
elapsed
1: the full current discharge capability is activated upon the turn-on command of the
complementary switch
[6:4] CTT: cross-current time.
See Table 18: Gate driver for external MOSFET
[3] CPLOWM: charge pump undervoltage monitoring
0: in case of charge pump undervoltage, only the CPLOW flag is set (global warning reported)
1: in case of charge pump undervoltage, the gate drivers are deactivated (functional error
reported)
[2] ISTEST(3): sink current enable (used for open-load and short-circuit test)
0: disabled
1: sink current at SH3
[1] ISTEST(2): sink current enable (used for open-load and short-circuit test)
0: disabled
1: sink current at SH2
[0] ISTEST(1): sink current enable (used for open-load and short-circuit test)
0: disabled
1: sink current at SH1

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4.4.9 Device Control Register 8

Device Control Register 8

7 6 5 4 3 2 1 0
Bit name — — — — — DSFT_DIS ISTEST_EN OCFT_DIS
Default values — — — — — 0 0 0

Address: 0x8
Type: R/W

Bit Bit description

[7:3] Reserved
[2] DSFT_DIS: drain-source fault disable.
This bit can be written only when the DISABLE bit (in status register 1) is "1", otherwise the write
operation to this bit is ignored. Note: this bit is not set to default in case of fail-safe errors.
0: a drain-source monitoring error causes the turn-off of the affected driver (functional error
reported)
1: a drain-source monitoring error does not cause the turn-off of the affected driver (global
warning reported)
[1] ISTEST_EN: ISTEST enable
0: ISTEST disabled
1: ISTEST enabled
[0] OCFT_DIS: overcurrent filter time disable (for RPD)
0: overcurrent filter time enabled
1: overcurrent filter time disabled

4.4.10 Device Status Registers 1

Device Status Registers 1

7 6 5 4 3 2 1 0
CPLOW NRDY DISABLE INHWAKE SPIWAKE Reserved DEVST(1) DEVST(0)
GSB reported GW/FE(1) GW/FE(1) FE Information Information — Information Information

Clear mode Read & Clear Auto cleared Read & Clear Read & Clear Read & Clear — Read & Clear

1. Depending on CPLOWM bit:

CPLOWM = 0, than GW
CPLOWM = 1, than FE

Address: 0x11
Type: R/C
I

Bit Bit description

[7] CPLOW: charge pump undervoltage detected
[6] NRDY: charge pump not ready (VCPLOW threshold not reached after charge pump startup)
[5] DISABLE: DIS pin high detected
[4] WAKEINH: wake-up from INH detected

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[3] WAKESPI: wake-up from SPI detected

[2] Reserved
[1:0] DEVST: device status
00: Active mode
01: VDD standby mode
10: VBAT standby mode/ POR
11: Flash mode

After a device state transition to Active mode or Flash mode, the DEVST bits always report
the previous device state. If an SPI "Read & Clear" command is performed on these bits,
they will then report the current device state.

4.4.11 Device Status Registers 2

Device Status Registers 2

7 6 5 4 3 2 1 0
SPI_DI Reserved Reserved Reserved INHST VRT2LOW VDDUV VDDFAIL
GSB reported FS — — — Information GW FS FS
Clear mode Read & Clear — — — Information Read & Clear Read & Clear Read & Clear

Address: 0x12
Type: R/C

Bit Bit description

[7] SPI_DI: short circuit on SDI pin detected (all 0's or all 1's detected on SDI pin)
[6] Reserved
[5] Reserved
[4] Reserved
[3] INHST: INH pin status (0: logic LOW; 1: logic HIGH)
[2] VRT2LOW: VDD detected to be below the VRT2 threshold, in case the VRT1 reset threshold is
selected (VDD_VTH = 0).
[1] VDDUV: VDD undervoltage detected
[0] VDDFAIL: VDD FAIL detected

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4.4.12 Device Status Registers 3

Device Status Registers 3

7 6 5 4 3 2 1 0
WDF(3) WDF(2) WDF(1) WDF(0) FSWD WD75% WD50% WD25%
GSB reported Information FS Information Information Information
Clear mode Auto cleared with valid WDTRIG toggle Read & Clear — — —

Address: 0x13
Type: R/C

Bit Bit description

[7:4] WDF: watchdog fault counter
[3] FSWD: watchdog fault occurred
[2:0] WD: counter monitor (these bits represent the percentage of the time elapsed between the POR
or the last watchdog trigger and the end of the watchdog period)

4.4.13 Device Status Registers 4

Device Status Registers 4

7 6 5 4 3 2 1 0
— VDDR(2) VDDR(1) VDDR(0) — TSD2 TSD1/TW2 TW1

GSB reported Information — FS DE/GW(1) GW

Clear mode Read & Clear on any of the VDD_R(x) bits — Read & Clear Read & Clear Read & Clear

1. Depending on TEMPM bit

If TEMPM = 0, then DE
If TEMPM = 1, then GW

Address: 0x14
Type: R/C

Bit Bit description

[7] Reserved
[6:4] VDDR: thermal shutdown event counter
[3] Reserved
[2] TSD2 detected
[1] TSD1/TW2 detected
[0] TW1 detected

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4.4.14 Device Status Registers 5

Device Status Registers 5

7 6 5 4 3 2 1 0
— VSOV VSOVW VSUV — VSREGOV VSREGOVW VSREGUV
GSB reported — DE GW DE — GW GW GW
Clear mode — Read & Clear Read & Clear Read & Clear — Read & Clear Read & Clear Read & Clear

Address: 0x15
Type: R/C

Bit Bit description

[7] Reserved
[6] VSOV: VS overvoltage detected
[5] VSOVW: VS overvoltage warning detected
[4] VSUV: VS undervoltage detected
[3] Reserved
[2] VSREGOV: VSREG overvoltage detected
[1] VSREGOVW: VSREG overvoltage warning detected
[0] VSREGUV: VSREG undervoltage detected

4.4.15 Device Status Registers 6

Device Status Registers 6

7 6 5 4 3 2 1 0
ST(3) ST(2) ST(1) CSAOC SPI_FL VSMSOV VSMSOVW VSMSUV

GSB reported FE FE FE GW/FE(1) GW DE GW GW

Clear mode Read & Clear Read & Clear Read & Clear Read & Clear Read & Clear Read & Clear Read & Clear Read & Clear

1. Depending on OCSHUTD bit

If OCSHUTD = 0, then GW
If OCSHUTD = 1, then FE

Address: 0x16
Type: R/C

Bit Bit description

[7] ST(3): HS3 and LS3 driven active at the same time (forbidden state / shoot-through detection)
[6] ST(2): HS2 and LS2 driven active at the same time (forbidden state / shoot-through detection)
[5] ST(1): HS1 and LS1 driven active at the same time (forbidden state / shoot-through detection)
[4] CSAOC: CSA overcurrent event detected
[3] SPI_FL: CS timeout or wrong number of SCLK cycles (other than 0 or 16) detected

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[2] VSMSOV: VSMS overvoltage detected

[1] VSMSOVW: VSMS overvoltage warning detected
[0] VSMSUV: VSMS undervoltage detected

4.4.16 Device Status Registers 7

Device Status Registers 7

7 6 5 4 3 2 1 0
— — DSLS(3) DSHS(3) DSLS(2) DSHS(2) DSLS(1) DSHS(1)

GSB reported — — FE/GW(1) FE/GW(1) FE/GW(1) FE/GW(1) FE/GW(1) FE/GW(1)

Clear mode — — Read & Clear Read & Clear Read & Clear Read & Clear Read & Clear Read & Clear

1. Depending on DSFT_DIS bit

If DSFT_DIS = 0, then FE
If DSFT_DIS = 1, then GW

Address: 0x17
Type: R/C

Bit Bit description

[7] Reserved
[6] Reserved
[5] DSLS3: drain-source overvoltage detected on LS3
[4] DSHS3: drain-source overvoltage detected on HS3
[3] DSLS2: drain-source overvoltage detected on LS2
[2] DSHS2: drain-source overvoltage detected on HS2
[1] DSLS1: drain-source overvoltage detected on LS1
[0] DSHS1: drain-source overvoltage detected on HS1

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5 Package information

5.1 ECOPACK® packages

n order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

5.2 TQFP48-EP mechanical data

Figure 26. TQFP48-EP package dimensions

Note: D2 and E2 not in scale in the drawing.

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Table 38. TQFP48-EP mechanical data

Millimeters
Symbol
Min. Typ. Max.

A 1.20

A1 0.05 0.15

A2 0.95 1.00 1.05

b 0.17 0.22 0.27

c 0.09 0.20

D 8.80 9.00 9.20

D1 6.80 7.00 7.20

D2 4.50

D3 5.50

E 8.80 9.00 9.20

E1 6.80 7.00 7.20

E2 4.50

E3 5.50

e 0.50

L 0.45 0.60 0.75

L1 1.00

k 0° 3.5° 7°

ccc 0.08

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6 Revision history

Table 39. Document revision history

Date Revision Changes

30-Jul-2012 1 Initial release

Updated following sections:
– Section 2.1: Supply pins (VS, VSREG, VSMS)
– Section 2.1.1: VS, VSREG and VSMS overvoltage warning
– Section 2.1.2: VS, VSREG and VSMS overvoltage
– Section 2.1.3: VS, VSREG and VSMS undervoltage
– Section 2.2: VDD (5V) voltage regulator
– Section 2.3: NRES reset output
– Section 2.4: Watchdog
Updated Figure 8: Operating mode transitions
Removed Figure: BEMF block diagram
Table 5: Diagnostics overview:
– MCU, VDD, Charge pump: updated device action
Table 12: Supply and supply monitoring
– VSUV, VSREGUV, VSMSUV: updated test condition and values
Table 14: Voltage regulator VDD:
– VDD: added condition
– VDDLiR: removed row
Table 15: NRES reset output (VDD supervision), NINT:
– VRT2, VRT2H: updated values
03-May-2013 2
Table 17: Charge pump output:
– VCP: updated minimum and maximum values
– VCPLOW: updated maximum value
Table 18: Gate driver for external MOSFET:
– IGHx(on), IGHx(off), IGLx(on), IGLx(off): updated values
– VGHxH: updated parameter definition
Table 19: Drain source monitoring:
– ISHx: updated typical value for ISTEST(x) = 1
Table 20: VS, VSREG, VSMS and Tj monitoring (AOUT):
– VSxOUT: updated test condition and values
– IAOUT: removed row
Table 21: Current-sense amplifier:
– VCS-IL=0: updated typical value
Table 29: SPI timing:
– tSCKQV, tSSCK: updated parameter definition
– tHSDI: added row
Updated Figure 20: SPI – timing and Figure 21: SPI global status
register access
Updated Table 37: Complete device SPI register table

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Table 39. Document revision history (continued)

Date Revision Changes

Updated Features list and Description

Updated Figure 1: Block diagram
Updated Table 2: Pin definition and function
Updated Figure 2: Pin connection (top view)
Updated following sections:
– Section 2.1: Supply pins (VS, VSREG, VSMS)
– Section 2.1.3: VS, VSREG and VSMS undervoltage
– Section 2.5.2: Flash Mode
– Section 2.5.3: VDD Standby Mode
– Section 2.5.5: Device mode state diagram
– Section 2.5.6: Functional overview
– Section 2.8.1: Normal mode: TEMPM = ‘0’ (TW1, TSD1, TSD2)
– Section 2.8.2: Warning mode: TEMP = ‘1’ (TW1, TW2, TSD2)
– Section 2.10: Charge pump
– Section 2.11: Gate drivers
– Section 2.12.2: Drain-source monitoring in OFF state (open-load
/ short-circuit detection)
Updated Table 5: Diagnostics overview, Table 7: Absolute
maximum ratings and Table 9: ESD protection
Table 10: Operation junction temperature:
– Rthj-case: updated typical value
01-Aug-2013 3
Table 14: Voltage regulator VDD:
– VDD: updated test condition
– dVDD/dt: updated values
Table 15: NRES reset output (VDD supervision), NINT:
– VRT2: updated values
Table 17: Charge pump output:
– VCP: updated value, added test condition
Table 18: Gate driver for external MOSFET:
– IGHx(on), IGLx(on), tPGXxLH: updated values
– IGHx(off), VGHxH, IGLxH: updated parameter and values
– IGLxH: updated parameter
Updated Figure 18: Cross-current protection time generation when
IHx and ILx are tied together
Added Figure 19: Cross-current protection time generation when
at tDT > tCCP is provided an input
Table 21: Current-sense amplifier:
– A20, A100, VIO, VCS-IL=0: updated values
Table 22: Overcurrent detection:
– VoOCMIN, VoOCMAX: updated value
Table 23: BEMF detection:
– VBEMFx, ΔVBEMFx: updated value

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Table 39. Document revision history (continued)

Date Revision Changes

Section 4.2.1: SDI frame: updated Advanced operation codes

Table 37: Complete device SPI register table:
– Address 0x02, bit 0: updated value
– Address 0x05, bit 1 and bit 0: updated values
– Address 0x11, bit 2: updated value
– Address 0x12, bit 7, bit 6, bit 5, bit 4, bit3 and bit 2: updated
values
– Address 0x16, bit 3: updated value
Section 4.4.1: SPI Control Registers:
– Bits [15], [14], [13], [9] and [8]: updated definitions
– Bit [13]: set as reserved
Section 4.4.2: Device Control Register 1:
– Updated access type
– Bits [4] and [3]: updated definitions
3
01-Aug-2013 Section 4.4.3: Device Control Register 2:
(continued)
– Bits [7] and [6]: updated definitions
Section 4.4.4: Device Control Register 3:
– Bits [3] and [2:0]: updated definitions
Section 4.4.5: Device Control Register 4:
– Bits [7:4] and [3:0]: updated definitions
Section 4.4.6: Device Control Register 5:
– Bits [1:0]: set as reserved
Section 4.4.10: Device Status Registers 1:
– Bits [1:0]: updated definition
– Bits [2]: set as reserved
Section 4.4.11: Device Status Registers 2:
– Bits [6:4]: set as reserved
Section 4.4.15: Device Status Registers 6:
– Bit [4]: updated definition
19-Sep-2013 4 Updated Disclaimer.

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Table 39. Document revision history (continued)

Date Revision Changes

Updated Features list

Updated Section 2.5.2: Flash Mode and Section 2.15.3: BEMF
commutation driving mode
Table 14: Voltage regulator VDD:
– VDD: updated parameter definition
– ICMPRISE, ICMPFALL, ICMPH: updated values
Table 15: NRES reset output (VDD supervision), NINT:
– VRT2: updated min value
11-Nov-2013 5
Table 24: I/Os; IHx, ILx, DIS, BC, BEMF, DOUT:
– Vin L: updated max value
– Vin H: updated min value
Section 4.4.5: Device Control Register 4:
– Bits [7:4] and [3:0]: updated definitions
Section 4.4.7: Device Control Register 6:
– Bits [4:0]: updated definitions
Updated Section 5.2: TQFP48-EP mechanical data
Table 20: VS, VSREG, VSMS and Tj monitoring (AOUT):
31-Jul-2014 6
– VTROOM: updated value
Updated Figure 8: Operating mode transitions
Table 7: Absolute maximum ratings:
06-Aug-2015 7
– VCP1+, VCP2+, VCP: updated value
Updated Figure 25: BEMF detection stepping of BEMFCNT

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IMPORTANT NOTICE – PLEASE READ CAREFULLY

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2015 STMicroelectronics – All rights reserved

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