®

OPA606

Wide-Bandwidth Difet ®
OPERATIONAL AMPLIFIER

FEATURES APPLICATIONS
● WIDE BANDWIDTH: 13MHz typ ● OPTOELECTRONICS
● HIGH SLEW RATE: 35V/µs typ ● DATA ACQUISITION
● LOW BIAS CURRENT: 10pA max at ● TEST EQUIPMENT
TA = +25°C ● AUDIO AMPLIFIERS
● LOW OFFSET VOLTAGE: 500µV max
● LOW DISTORTION: 0.0035% typ at 10kHz

DESCRIPTION
The OPA606 is a wide-bandwidth monolithic Laser-trimmed thin-film resistors offer improved off-
dielectrically-isolated FET (Difet®) operational ampli- set voltage and noise performance.
fier featuring a wider bandwidth and lower bias cur- The OPA606 is internally compensated for unity-gain
rent than BIFET® LF156A amplifiers. Bias current is stability.
specified under warmed-up and operating conditions,
as opposed to a junction temperature of +25°C.

1 5 7
Trim Trim +VCC

2
–In

3
+In

VOUT
6

–VCC
Simplified Circuit 4

Difet®; Burr-Brown Corp.

BIFET®; National Semiconductor Corp.

International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

©
1985 Burr-Brown Corporation PDS-598D Printed in U.S.A. July, 1995

SBOS143
SPECIFICATIONS
ELECTRICAL
At VCC = ±15VDC and TA = +25°C unless otherwise noted.

OPA606KM OPA606LM OPA606KP

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
FREQUENCY RESPONSE
Gain Bandwidth Small Signal 10 12.5 11 13 9 12 MHz
Full Power Response 20Vp-p, RL = 2kΩ 515 550 470 kHz
Slew Rate VO = ±10V, 22 33 25 35 20 30 V/µs
RL = 2kΩ
Settling Time(1): 0.1% Gain = –1, 1.0 1.0 1.0 µs
RL = 2kΩ
0.01% 10V Step 2.1 2.1 2.1 µs
Total Harmonic Distortion G = +1, 20Vp-p 0.0035 0.0035 0.0035 %
RL = 2kΩ
f = 10kHz
INPUT OFFSET VOLTAGE(2)
Input Offset Voltage VCM = 0VDC ±180 ±1.5mV ±100 ±500 ±300 ±3mV µV
Average Drift TA = TMIN to TMAX ±5 ±3 ±5 ±10 µV/°C
Supply Rejection VCC = ±10V to ±18V 82 100 90 104 80 90 dB
±10 ±79 ±6 ±32 ±32 ±100 µV/V
BIAS CURRENT(2)
Input Bias Current VCM = 0VDC ±7 ±15 ±5 ±10 ±8 ±25 pA
OFFSET CURRENT(2)
Input Offset Current VCM = 0VDC ±0.6 ±10 ±0.4 ±5 ±1 ±15 pA
NOISE
Voltage, fO = 10Hz 100% tested (L) 37 30 40 37 nV/√Hz
100Hz 100% tested (L) 21 20 28 21 nV/√Hz
1kHz 100% tested (L) 14 13 16 14 nV/√Hz
10kHz (3) 12 11 13 12 nV/√Hz
20kHz (3) 11 10.5 13 11 nV/√Hz
fB = 10Hz to 10kHz (3) 1.3 1.2 1.5 1.3 µVrms
Current, fO = 0.1Hz thru 20kHz (3) 1.5 1.3 2 1.7 fA/√Hz
IMPEDANCE
Differential 1013 || 1 1013 || 1 1013 || 1 Ω || pF
Common-Mode 1014 || 3 1014 || 3 1014 || 3 Ω || pF
VOLTAGE RANGE
Common-Mode Input Range ±10.5 ±11.5 ±11 ±11.6 ±10.2 ±11 V
Common-Mode Rejection VIN = ±10VDC 80 95 85 96 78 90 dB
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain RL ≥ 2kΩ 95 115 100 118 90 110 dB
RATED OUTPUT
Voltage Output RL = 2kΩ ±11 ±12.2 ±12 ±12.6 ±11 ±12 V
Current Output VO = ±10VDC ±5 ±10 ±5 ±10 ±5 ±10 mA
Output Resistance DC, Open Loop 40 40 40 Ω
Load Capacitance Stability Gain = +1 1000 1000 1000 pF
Short Circuit Current 10 20 10 20 10 20 mA
POWER SUPPLY
Rated Voltage ±15 ±15 ±15 VDC
Voltage Range,
Derated Performance ±5 ±18 ±5 ±18 ±5 ±18 VDC
Current, Quiescent IO = 0mADC 6.5 9.5 6.2 9 6.5 10 mA
TEMPERATURE RANGE
Specification Ambient Temperature
KM, KP, LM 0 +70 0 +70 0 +70 °C
Operating Ambient Temperature –55 +125 –55 +125 –40 +85 °C
θJA 200 200 155 °C/W

NOTES: (1) See settling time test circuit in Figure 2. (2) Offset voltage, offset current, and bias current are measured with the units fully warmed up. (3) Sample
tested–this parameter is guaranteed on L grade only.

OPA606 2
ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS)
At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted.

OPA606KM OPA606LM OPA606KP

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
TEMPERATURE RANGE
Specification Range Ambient Temp. 0 +70 0 +70 0 +70 °C
INPUT OFFSET VOLTAGE(1)
Input Offset Voltage VCM = 0VDC ±400 ±2mV ±335 ±750 ±750 ±3.5mV µV
Average Drift ±5 ±3 ±5 ±10 µV/°C
Supply Rejection VCC = ±10V to ±18V 80 98 85 100 78 95 dB
±13 ±100 ±10 ±56 ±18 ±126 µV/V
BIAS CURRENT(1)
Input Bias Current VCM = 0VDC ±158 ±339 ±113 ±226 ±181 ±566 pA
OFFSET CURRENT(1)
Input Offset Current VCM = 0VDC ±14 ±226 ±9 ±113 ±23 ±339 pA
VOLTAGE RANGE
Common-Mode Input Range ±10.4 ±11.4 ±10.9 ±11.5 ±10 ±10.9 V
Common-Mode Rejection VIN = ±10VDC 78 92 82 95 75 88 dB
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain RL ≥ 2kΩ 90 106 95 112 88 104 dB
RATED OUTPUT
Voltage Output RL = 2kΩ ±10.5 ±12 ±11.5 ±12.4 ±10.4 ±11.8 V
Current Output VO = ±10VDC ±5 ±10 ±5 ±10 ±5 ±10 mA
POWER SUPPLY
Current, Quiescent IO = 0mADC 6.6 10 6.4 9.5 6.6 10.5 mA

NOTES: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up.

ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS

Supply Voltage .............................................................................. ±18VDC Top View TO-99
Internal Power Dissipation (1) ......................................................... 500mW NC
Differential Input Voltage ............................................................... ±36VDC
Input Voltage Range ..................................................................... ±18VDC 8
Storage Temperature Range ................................... M = –65°C to +150°C Offset Trim +VCC
P = –40°C to +85°C 1 7
Operating Temperature Range ................................ M = –55°C to +125°C
P = –40°C to +85°C
Lead Temperature (soldering, 10s) ................................................ +300°C –In 2 6 Output
(3)
Output Short-Circuit Duration ................................................ Continuous
Junction Temperature .................................................................... +175°C
3 5
NOTES: (1) Packages must be derated based on θJC = 15°C/W or θJA. (2) +In Offset Trim
For supply voltages less than ±18VDC, the absolute maximum input 4
voltage is equal to the negative supply voltage. (3) Short circuit may be to –VCC
power supply common only. Rating applies to +25°C ambient. Observe
Case is connected to VCC.
dissipation limit and TJ.

PACKAGE INFORMATION Top View DIP

PACKAGE DRAWING
MODEL PACKAGE NUMBER(1) Offset Trim 1 8 NC

OPA606KM TO-99 001 –In 2 7 +VCC

OPA606LM TO-99 001
OPA606KP Plastic DIP 006 +In 3 6 Output
NOTE: (1) For detailed drawing and dimension table, please see end of data –VCC 4 5 Offset Trim
sheet, or Appendix D of Burr-Brown IC Data Book.

ORDERING INFORMATION
TEMPERATURE
MODEL PACKAGE RANGE
OPA606KM TO-99 0°C to 70°C
OPA606LM TO-99 0°C to 70°C
OPA606KP Plastic DIP 0°C to 70°C

3 OPA606
DICE INFORMATION

PAD FUNCTION
1 Offset Trim
2 –In
3 +In
4 –VS
5 Offset Trim
6 Output
7 +VS
8 NC
NC No Connection
Substrate Bias: No Connection.

MECHANICAL INFORMATION
MILS (0.001") MILLIMETERS
Die Size 65 x 54 ±5 1.65 x 1.37 ±0.13
Die Thickness 20 ±3 0.51 ±0.08
Min. Pad Size 4x4 0.10 x 0.10
Backing None
OPA606 DIE TOPOGRAPHY Transistor Count 43

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

OPA606 4
TYPICAL PERFORMANCE CURVES
TA = +25°C, VCC = ±15VDC unless otherwise noted.

OPEN-LOOP FREQUENCY RESPONSE INPUT VOLTAGE NOISE SPECTRAL DENSITY

140 1k
LM
120 –45

Voltage Noise (nV/ √Hz)

Phase Shift (degrees)
100
Voltage Gain (dB)

100
80 –90
θ
60

Gain 10
40 –135

20

0 –180 1
10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

BIAS AND OFFSET CURRENT vs

BIAS AND OFFSET CURRENT vs TEMPERATURE INPUT COMMON-MODE VOLTAGE
10nA 10nA 1nA 1nA

1nA 1nA
Offset Current (pA)

Offset Current (pA)

Bias Current (pA)

Bias Current (pA)

100 100
100 IB 100

IB
10 IOS 10
10 I OS 10

1 1

0.1 0.1 1 1
–50 –25 0 25 50 75 100 125 –15 –10 –5 0 5 10 15
Ambient Temperature (°C) Common-Mode Voltage (V)

POWER SUPPLY REJECTION COMMON-MODE REJECTION

vs FREQUENCY vs FREQUENCY
140 140

120 120
Common-Mode Rejection (dB)
Power Supply Rejection (dB)

100 100
+VCC
80 80
–VCC
60 60

40 40

20 20

0 0
10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)

5 OPA606
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VCC = ±15V unless otherwise noted.

MAXIMUM UNDISTORTED OUTPUT GAIN-BANDWIDTH AND SLEW RATE

VOLTAGE vs FREQUENCY vs SUPPLY VOLTAGE
30 14 40

GBW

Gain-Bandwidth (MHz)
Output Voltage (V p-p)

Slew Rate (V/µs)

20 12 35

S/R

10 10 30

0 8 25
10k 100k 1M 10M 0 5 10 15 20
Frequency (Hz) Supply Voltage (±VCC)

SUPPLY CURRENT vs TEMPERATURE OPEN-LOOP GAIN vs TEMPERATURE

8 130

7 120
Supply Current (mA)

Voltage Gain (dB)

6 110

5 100

4 90
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Ambient Temperature (°C) Ambient Temperature (°C)

GAIN-BANDWIDTH AND SLEW RATE OPEN-LOOP GAIN AND SUPPLY CURRENT

vs TEMPERATURE vs SUPPLY VOLTAGE
16 38 10

GBW 120 9
Gain-Bandwidth (MHz)

14 36
Supply Current (mA)
Voltage Gain (dB)
Slew Rate (V/µs)

12 34 110 7

S/R 6
10 32
100 5

8 30 4
–75 –50 –25 0 25 50 75 100 125 0 5 10 15 20
Ambient Temperature (°C) Supply Voltage (±VCC)

OPA606 6
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VCC = ±15V unless otherwise noted.

TOTAL HARMONIC DISTORTION

SETTLING TIME vs CLOSED-LOOP GAIN vs FREQUENCY
10 0.01
G = +1
VO = 7Vrms

Total Harmonic Distortion (%)

8 0.008
Settling Time (µs)

6 0.006

4 0.004

2 0.002
Test Equipment
Limit
0 0
1 10 100 1k 100 1k 10k 100k
Closed-Loop Gain (V/V) Frequency (Hz)

SMALL SIGNAL TRANSIENT RESPONSE LARGE SIGNAL TRANSIENT RESPONSE

+80 +15

+40
Output Voltage (mV)

Output Voltage (V)

0 0

+40

–80 –15
0 0.5 1 0 2.5 5
Time (µs) Time (µs)

APPLICATIONS INFORMATION +VCC

(1)
OFFSET VOLTAGE ADJUSTMENT NOTE: (1) 10kΩ to 1MΩ
Trim Potentiometer
The OPA606 offset voltage is laser-trimmed and will require (100kΩ Recommended)
no further trim for most applications. As with most amplifi- 7 100kΩ
1
ers, externally trimming the remaining offset can change 2 5
drift performance by about 0.5µV/°C for each millivolt of OPA606 6
adjusted offset. Note that the trim (Figure 1) is similar to 3

operational amplifiers such as LF156 and OP-16. The ±50mV Typical

4
Trim Range
OPA606 can replace most other amplifiers by leaving the –VCC
external null circuit unconnected.
FIGURE 1. Offset Voltage Trim.

7 OPA606
INPUT PROTECTION Noninverting Buffer
Static damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device. In
2 2
precision operational amplifiers (both bipolar and FET types),
6 6
this may cause a noticeable degradation of offset voltage and OPA606 OPA606 Out
In 3 Out 3
drift. Static protection is recommended when handling any In
precision IC operational amplifier.
Inverting TO-99 Bottom View
If the input voltage exceeds the amplifier’s negative supply In
voltage, input current limiting must be used to prevent
4 5
damage. 2 3 6
6 7
OPA606
3 2
Out
CIRCUIT LAYOUT 1 8
Wideband amplifiers require good circuit layout techniques
and adequate power supply bypassing. Short, direct connec-
tions and good high frequency bypass capacitors (ceramic or Mini-DIP Bottom View
tantalum) will help avoid noise pickup or oscillation.
BOARD LAYOUT 8 1
FOR INPUT GUARDING
GUARDING AND SHIELDING Guard top and bottom of board. 7 2
Alternate: use Teflon® standoff
As in any situation where high impedances are involved, for sensitive input pins. 6 3
careful shielding is required to reduce “hum” pickup in input
Teflon® E. I. Du Pont
leads. If large feedback resistors are used, they should also de Nemours & Co. 5 4
be shielded along with the external input circuitry.
Leakage currents across printed circuit boards can easily FIGURE 3. Connection of Input Guard.
exceed the bias current of the OPA606. To avoid leakage
problems, it is recommended that the signal input lead of the APPLICATIONS CIRCUITS
OPA606 be wired to a Teflon® standoff. If the OPA606 is to
be soldered directly into a printed circuit board, utmost care 10kΩ
must be used in planning the board layout.
+15VDC
A “guard” pattern should completely surround the high 0.1µF
impedance input leads and should be connected to a low 1kΩ
2 7
impedance point which is at the signal input potential (see Input
6
Figure 3). BANDWIDTH > 1MHz 3
OPA606 Output
0.1µF
TS ≈ 1.8µsec (0.01%) 4
GAIN = –10V/V
0.1%
–15VDC
2kΩ
+15V
FIGURE 4. Inverting Amplifier.
+5V 0.1%
2 7
–5V
6
2kΩ DUT 2N4416
0.1% 3
4
5kΩ 100pF +15VDC
3kΩ VOUT 0.1µF
–15V
Summing 0.1% G = –1
Node 2 7
6
5kΩ OPA606 Output
Scope 3
+15V Input 0.1µF
2N4416 4
Bandwidth > 12MHz
2k Ω Gain = +1V/V
RIN ≈ 1013Ω –15VDC

FIGURE 5. Noninverting Buffer.

FIGURE 2. Settling Time Test Circuit.

OPA606 8
 1MΩ
10kΩ

C1
+15V
20pF

Current Output 2
2 7 R1 Load
Input Voltage 6
6 OPA606
i OPA606 EO 3
3 Input 100Ω
4 EO = |i| R = 1V/µA
Optimize response for particular
load condition with C1 and R1.
1MΩ
i –15V

0
FIGURE 8. Isolating Load Capacitance from Buffer.
0

3 Differential Gain = 1 + (2 x 10kΩ)/RG

6
OPA606
FIGURE 6. Absolute Value Current-to-Voltage Circuit. 2

10kΩ

≈ 0.2pF if necessary to RG
prevent gain peaking Differential Differential
2kΩ
Input Output

150kΩ 150kΩ 150kΩ 10kΩ

3 Metal-film
2
resistors
6
+15V OPA606
3
0.01µF 1. Bandwidth ≈1.2MHz
2. Differential Gain = 11
2 7 3. Differential Output ≈ 50Vp-p
Pin Photodiode 6
Output 4. Differential Slew Rate ≈ 65V/µs
OPA606
Motorola 3
MRD721 0.01µF FIGURE 9. Differential Input/Differential Output Amplifier.
4
0.1µF

–15V
1. Circuit must be well shielded.
10kΩ 2. Stray capacitance is critical.
3. Bandwidth ≈ 1MHz
4. Output ≈ 22V/mW/cm2
+15V

FIGURE 7. High-Speed Photodetector.

49.9Ω 2.49kΩ

Total Mid-band Gain = 40dB

See: "Topology Considerations for RIAA Phono Preamplifiers".

AES reprint #1719.
2 October 1980, by Walter G. Jung
Moving Magnet 6
Cartridge OPA37EJ
3
G ≈ 51V/V
7.32kΩ
G ≈ 20V/V
47.5kΩ 150pF (1)
3
10µF Output
6
OPA606
0.1µF 2
1.05kΩ
3.74kΩ

10kΩ
1. Load R and C per cartridge manufacturer's recommendations. 0.3µF
200Ω
2. Use metal film resistors and plastic film capacitors.
3. Bypass ±VCC adequately.

FIGURE 10. Low Noise/Low Distortion RIAA Preamplifier.

®

9 OPA606
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA606KP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 OPA606KP

OPA606KPG4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 OPA606KP

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA606KP P PDIP 8 50 506 13.97 11230 4.32
OPA606KPG4 P PDIP 8 50 506 13.97 11230 4.32

Pack Materials-Page 1
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