M93S66, M93S56

M93S46
4Kbit, 2Kbit and 1Kbit (16-bit wide)
MICROWIRE Serial Access EEPROM with Block Protection

FEATURES SUMMARY
■ Industry Standard MICROWIRE Bus Figure 1. Packages
■ Single Supply Voltage:
– 4.5 to 5.5V for M93Sx6
– 2.5 to 5.5V for M93Sx6-W
– 1.8 to 5.5V for M93Sx6-R
■ Single Organization: by Word (x16) 8
■ Programming Instructions that work on: Word
or Entire Memory
■ Self-timed Programming Cycle with Auto-
1
Erase PDIP8 (BN)
■ User Defined Write Protected Area
■ Page Write Mode (4 words)
■ Ready/Busy Signal During Programming
8
■ Speed:
– 1MHz Clock Rate, 10ms Write Time
(Current product, identified by process 1
identification letter F or M)
– 2MHz Clock Rate, 5ms Write Time (New SO8 (MN)
Product, identified by process 150 mil width
identification letter W or G)
■ Sequential Read Operation
■ Enhanced ESD/Latch-Up Behavior
■ More than 1 Million Erase/Write Cycles
■ More than 40 Year Data Retention
TSSOP8 (DS)
3x3mm body size

TSSOP8 (DW)
169 mil width

April 2004 1/34

M93S66, M93S56, M93S46

TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

POWER-ON DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Instruction Set for the M93S46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Instruction Set for the M93S66, M93S56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. READ, WRITE, WEN and WDS Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. PAWRITE and WRAL Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. PREAD, PRWRITE and PREN Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. PRCLEAR and PRDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

WRITE PROTECTION AND THE PROTECTION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Protection Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Operating Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Operating Conditions (M93Sx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Operating Conditions (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. AC Measurement Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . 17

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 M93S66, M93S56, M93S46

Figure 9. AC Testing Input Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. DC Characteristics (M93Sx6, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. DC Characteristics (M93Sx6, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. DC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. DC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. DC Characteristics (M93Sx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. AC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. AC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19. AC Characteristics (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10.Synchronous Timing (Start and Op-Code Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 28
Table 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 28
Figure 14.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 29
Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
29
Figure 15.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
30
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
30
Figure 16.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 31
Table 23. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 31

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 25. How to Identify Current and New Products by the Process Identification Letter . . . . . . . 32

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 26. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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M93S66, M93S56, M93S46

SUMMARY DESCRIPTION
This specification covers a range of 4K, 2K, 1K bit and instructions used to set the memory protec-
serial Electrically Erasable Programmable Memo- tion. These are summarized in Table 2. and Table
ry (EEPROM) products (respectively for M93S66, 3.).
M93S56, M93S46). In this text, these products are A Read Data from Memory (READ) instruction
collectively referred to as M93Sx6. loads the address of the first word to be read into
an internal address pointer. The data contained at
Figure 2. Logic Diagram this address is then clocked out serially. The ad-
dress pointer is automatically incremented after
the data is output and, if the Chip Select Input (S)
is held High, the M93Sx6 can output a sequential
VCC stream of data words. In this way, the memory can
be read as a data stream from 16 to 4096 bits (for
the M93S66), or continuously as the address
counter automatically rolls over to 00h when the
D highest address is reached.
Within the time required by a programming cycle
C Q (tW), up to 4 words may be written with help of the
Page Write instruction. the whole memory may
S M93Sx6 also be erased, or set to a predetermined pattern,
by using the Write All instruction.
PRE Within the memory, a user defined area may be
protected against further Write instructions. The
W size of this area is defined by the content of a Pro-
tection Register, located outside of the memory ar-
ray. As a final protection step, data may be
VSS
permanently protected by programming a One
AI02020
Time Programming bit (OTP bit) which locks the
Protection Register content.
Programming is internally self-timed (the external
clock signal on Serial Clock (C) may be stopped or
left running after the start of a Write cycle) and
does not require an erase cycle prior to the Write
instruction. The Write instruction writes 16 bits at a
Table 1. Signal Names time into one of the word locations of the M93Sx6,
S Chip Select Input the Page Write instruction writes up to 4 words of
16 bits to sequential locations, assuming in both
D Serial Data Input cases that all addresses are outside the Write Pro-
tected area. After the start of the programming cy-
Q Serial Data Output cle, a Busy/Ready signal is available on Serial
Data Output (Q) when Chip Select Input (S) is driv-
C Serial Clock en High.
PRE Protection Register Enable
Figure 3. DIP, SO and TSSOP Connections
W Write Enable

VCC Supply Voltage M93Sx6

VSS Ground S 1 8 VCC

C 2 7 PRE
The M93Sx6 is accessed through a serial input (D)
and output (Q) using the MICROWIRE bus proto- D 3 6 W
col. The memory is divided into 256, 128, 64 x16 Q 4 5 VSS
bit words (respectively for M93S66, M93S56, AI02021
M93S46).
The M93Sx6 is accessed by a set of instructions
which includes Read, Write, Page Write, Write All Note: See PACKAGE MECHANICAL section for package dimen-
sions, and how to identify pin-1.

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 M93S66, M93S56, M93S46

An internal Power-on Data Protection mechanism INSTRUCTIONS

in the M93Sx6 inhibits the device when the supply The instruction set of the M93Sx6 devices con-
is too low. tains seven instructions, as summarized in Table
2. to Table 3.. Each instruction consists of the fol-
lowing parts, as shown in Figure 4.:
■ Each instruction is preceded by a rising edge
POWER-ON DATA PROTECTION on Chip Select Input (S) with Serial Clock (C)
To prevent data corruption and inadvertent write being held Low.
operations during power-up, a Power-On Reset ■ A start bit, which is the first ‘1’ read on Serial
(POR) circuit resets all internal programming cir- Data Input (D) during the rising edge of Serial
cuitry, and sets the device in the Write Disable Clock (C).
mode. ■ Two op-code bits, read on Serial Data Input
– At Power-up and Power-down, the device (D) during the rising edge of Serial Clock (C).
must not be selected (that is, Chip Select Input (Some instructions also use the first two bits of
(S) must be driven Low) until the supply the address to define the op-code).
voltage reaches the operating value VCC ■ The address bits of the byte or word that is to
specified in Table 5. to Table 6.. be accessed. For the M93S46, the address is
– When VCC reaches its valid level, the device is made up of 6 bits (see Table 2.). For the
properly reset (in the Write Disable mode) and M93S56 and M93S66, the address is made up
is ready to decode and execute incoming of 8 bits (see Table 3.).
instructions. The M93Sx6 devices are fabricated in CMOS
For the M93Sx6 devices (5V range) the POR technology and are therefore able to run as slow
threshold voltage is around 3V. For the M93Sx6- as 0 Hz (static input signals) or as fast as the max-
W (3V range) and M93Sx6-R (2V range) the POR imum ratings specified in Table 16. to Table 19..
threshold voltage is around 1.5V.

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M93S66, M93S56, M93S46

Table 2. Instruction Set for the M93S46

Required
Start Op- Additional
Instruction Description W PRE
bit Code Address1 Data Clock
Comments
Cycles
Read Data
READ X 0 1 10 A5-A0 Q15-Q0
from Memory
Write is executed if
Write Data to the address is not
WRITE 1 0 1 01 A5-A0 D15-D0 25
Memory inside the Protected
area
Write is executed if
Page Write to Nx all the N addresses
PAWRITE 1 0 1 11 A5-A0 9 + N x 16
Memory D15-D0 are not inside the
Protected area
Write All
Write all data if the
Memory
WRAL 1 0 1 00 01 XXXX D15-D0 25 Protection Register
with same
is cleared
Data
WEN Write Enable 1 0 1 00 11 XXXX 9
WDS Write Disable X 0 1 00 00 XXXX 9
Data Output =
Protection Q5-Q0 Protection Register
PRREAD X 1 1 10 XXXXXX
Register Read + Flag content + Protection
Flag bit
Data above specified
Protection
PRWRITE 1 1 1 01 A5-A0 9 address A5-A0 are
Register Write
protected
Protect Flag is also
Protection
PRCLEAR 1 1 1 11 111111 9 cleared (cleared
Register Clear
Flag = 1)
Protection
PREN Register 1 1 1 00 11XXXX 9
Enable
Protection
OTP bit is set
PRDS Register 1 1 1 00 000000 9
permanently
Disable
Note: 1. X = Don’t Care bit.

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 M93S66, M93S56, M93S46

Table 3. Instruction Set for the M93S66, M93S56

Required
Start Op- Additional
Instruction Description W PRE
bit Code Address1,2 Data Clock
Comments
Cycles
Read Data
READ X 0 1 10 A7-A0 Q15-Q0
from Memory
Write is executed if
Write Data to the address is not
WRITE 1 0 1 01 A7-A0 D15-D0 27
Memory inside the
Protected area
Write is executed if
all the N
Page Write to Nx
PAWRITE 1 0 1 11 A7-A0 11 + N x 16 addresses are not
Memory D15-D0
inside the
Protected area
Write All
Write all data if the
Memory
WRAL 1 0 1 00 01XXXXXX D15-D0 27 Protection
with same
Register is cleared
Data
WEN Write Enable 1 0 1 00 11XXXXXX 11
WDS Write Disable X 0 1 00 00XXXXXX 11
Data Output =
Protection Q7-Q0 Protection
PRREAD X 1 1 10 XXXXXXXX
Register Read + Flag Register content +
Protection Flag bit
Data above
Protection specified address
PRWRITE 1 1 1 01 A7-A0 11
Register Write A7-A0 are
protected
Protect Flag is also
Protection
PRCLEAR 1 1 1 11 11111111 11 cleared (cleared
Register Clear
Flag = 1)
Protection
PREN Register 1 1 1 00 11XXXXXX 11
Enable
Protection
OTP bit is set
PRDS Register 1 1 1 00 00000000 11
permanently
Disable
Note: 1. X = Don’t Care bit.
2. Address bit A7 is not decoded by the M93S56.

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M93S66, M93S56, M93S46

Figure 4. READ, WRITE, WEN and WDS Sequences

READ PRE

D 1 1 0 An A0

Q Qn Q0

ADDR DATA OUT

OP
CODE

WRITE PRE

CHECK
STATUS
D 1 0 1 An A0 Dn D0

ADDR DATA IN BUSY READY

OP
CODE

WRITE PRE WRITE PRE

ENABLE DISABLE

W S

S D 1 0 0 0 0 Xn X0

D 1 0 0 1 1 Xn X0 OP
CODE

OP
CODE
AI00889D

Note: For the meanings of An, Xn, Qn and Dn, see Table 2. and Table 3..

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 M93S66, M93S56, M93S46

Read Write
The Read Data from Memory (READ) instruction The Write Data to Memory (WRITE) instruction is
outputs serial data on Serial Data Output (Q). composed of the Start bit plus the op-code fol-
When the instruction is received, the op-code and lowed by the address and the 16 data bits to be
address are decoded, and the data from the mem- written.
ory is transferred to an output shift register. A dum- Write Enable (W) must be held High before and
my 0 bit is output first, followed by the 16-bit word, during the instruction. Input address and data, on
with the most significant bit first. Output data Serial Data Input (D) are sampled on the rising
changes are triggered by the rising edge of Serial edge of Serial Clock (C).
Clock (C). The M93Sx6 automatically increments
the internal address register and clocks out the After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
next byte (or word) as long as the Chip Select In-
rising edge of Serial Clock (C). If Chip Select Input
put (S) is held High. In this case, the dummy 0 bit
(S) is brought Low before or after this specific time
is not output between bytes (or words) and a con-
tinuous stream of data can be read. frame, the self-timed programming cycle will not
be started, and the addressed location will not be
Write Enable and Write Disable programmed.
The Write Enable (WEN) instruction enables the While the M93Sx6 is performing a write cycle, but
future execution of write instructions, and the Write after a delay (tSLSH) before the status information
Disable (WDS) instruction disables it. When power becomes available, Chip Select Input (S) can be
is first applied, the M93Sx6 initializes itself so that driven High to monitor the status of the write cycle:
write instructions are disabled. After an Write En- Serial Data Output (Q) is driven Low while the
able (WEN) instruction has been executed, writing M93Sx6 is still busy, and High when the cycle is
remains enabled until an Write Disable (WDS) in- complete, and the M93Sx6 is ready to receive a
struction is executed, or until V CC falls below the new instruction. The M93Sx6 ignores any data on
power-on reset threshold voltage. To protect the the bus while it is busy on a write cycle. Once the
memory contents from accidental corruption, it is M93Sx6 is Ready, Serial Data Output (Q) is driven
advisable to issue the Write Disable (WDS) in- High, and remains in this state until a new start bit
struction after every write cycle. The Read Data is decoded or the Chip Select Input (S) is brought
from Memory (READ) instruction is not affected by Low.
the Write Enable (WEN) or Write Disable (WDS)
instructions. Programming is internally self-timed, so the exter-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.

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M93S66, M93S56, M93S46

Figure 5. PAWRITE and WRAL Sequence

PAGE PRE
WRITE

CHECK
STATUS
D 1 1 1 An A0 Dn D0

ADDR DATA IN BUSY READY

OP
CODE

WRITE PRE
ALL

CHECK
STATUS
D 1 0 0 0 1 Xn X0 Dn D0

ADDR DATA IN BUSY READY

OP
CODE

AI00890C

Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
Page Write The Page Write to Memory (PAWRITE) instruction
A Page Write to Memory (PAWRITE) instruction will not be executed if any of the 4 words address-
contains the first address to be written, followed by es the protected area.
up to 4 data words. Write Enable (W) must be held High before and
After the receipt of each data word, bits A1-A0 of during the instruction. Input address and data, on
the internal address register are incremented, the Serial Data Input (D) are sampled on the rising
high order bits remaining unchanged (A7-A2 for edge of Serial Clock (C).
M93S66, M93S56; A5-A2 for M93S46). Users After the last data bit has been sampled, the Chip
must take care, in the software, to ensure that the Select Input (S) must be taken Low before the next
last word address has the same upper order ad- rising edge of Serial Clock (C). If Chip Select Input
dress bits as the initial address transmitted to (S) is brought Low before or after this specific time
avoid address roll-over. frame, the self-timed programming cycle will not

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 M93S66, M93S56, M93S46

be started, and the addressed location will not be Write Enable (W) must be held High before and
programmed. during the instruction. Input address and data, on
While the M93Sx6 is performing a write cycle, but Serial Data Input (D) are sampled on the rising
after a delay (tSLSH) before the status information edge of Serial Clock (C).
becomes available, Chip Select Input (S) can be After the last data bit has been sampled, the Chip
driven High to monitor the status of the write cycle: Select Input (S) must be taken Low before the next
Serial Data Output (Q) is driven Low while the rising edge of Serial Clock (C). If Chip Select Input
M93Sx6 is still busy, and High when the cycle is (S) is brought Low before or after this specific time
complete, and the M93Sx6 is ready to receive a frame, the self-timed programming cycle will not
new instruction. The M93Sx6 ignores any data on be started, and the addressed location will not be
the bus while it is busy on a write cycle. Once the programmed.
M93Sx6 is Ready, Serial Data Output (Q) is driven While the M93Sx6 is performing a write cycle, but
High, and remains in this state until a new start bit after a delay (tSLSH) before the status information
is decoded or the Chip Select Input (S) is brought becomes available, Chip Select Input (S) can be
Low. driven High to monitor the status of the write cycle:
Programming is internally self-timed, so the exter- Serial Data Output (Q) is driven Low while the
nal Serial Clock (C) may be disconnected or left M93Sx6 is still busy, and High when the cycle is
running after the start of a write cycle. complete, and the M93Sx6 is ready to receive a
Write All new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a write cycle. Once the
The Write All Memory with same Data (WRAL) in-
M93Sx6 is Ready, Serial Data Output (Q) is driven
struction is valid only after the Protection Register
High, and remains in this state until a new start bit
has been cleared by executing a Protection Reg- is decoded or the Chip Select Input (S) is brought
ister Clear (PRCLEAR) instruction. The Write All
Low.
Memory with same Data (WRAL) instruction simul-
taneously writes the whole memory with the same Programming is internally self-timed, so the exter-
data word given in the instruction. nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.

11/34
M93S66, M93S56, M93S46

Figure 6. PREAD, PRWRITE and PREN Sequences

Protect PRE
Register
READ

D 1 1 0 Xn X0

Q An A0 F

ADDR DATA F = Protect Flag

OP OUT
CODE

Protect PRE
Register
WRITE

CHECK
STATUS
D 1 0 1 An A0

ADDR BUSY READY

OP
CODE

Protect PRE
Register
ENABLE

D 1 0 0 1 1 Xn X0

OP
CODE
AI00891D

Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..

12/34
 M93S66, M93S56, M93S46

Figure 7. PRCLEAR and PRDS Sequences

Protect PRE
Register
CLEAR

CHECK
STATUS
D 111 111

ADDR BUSY READY

OP
CODE

Protect PRE
Register
DISABLE

CHECK
STATUS
D 100 000

ADDR BUSY READY

OP
CODE

AI00892C

Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..

13/34
M93S66, M93S56, M93S46

WRITE PROTECTION AND THE PROTECTION REGISTER

The Protection Register on the M93Sx6 is used to able (PREN) instruction does not modify the Pro-
adjust the amount of memory that is to be write tection Flag bit value.
protected. The write protected area extends from Note: A Write Enable (WEN) instruction must be
the address given in the Protection Register, up to executed before the Protection Register Enable
the top address in the M93Sx6 device. (PREN) instruction. Both the Protection Enable
Two flag bits are used to indicate the Protection (PRE) and Write Enable (W) signals must be driv-
Register status: en High during the instruction execution.
– Protection Flag: this is used to enable/disable Protection Register Clear
protection of the write-protected area of the The Protection Register Clear (PRCLEAR) in-
M93Sx6 memory struction clears the address stored in the Protec-
– OTP bit: when set, this disables access to the tion Register to all 1s, so that none of the memory
Protection Register, and thus prevents any is write-protected by the Protection Register. How-
further modifications to the value in the ever, it should be noted that all the memory re-
Protection Register. mains protected, in the normal way, using the
The lower-bound memory address is written to the Write Enable (WEN) and Write Disable (WDS) in-
Protection Register using the Protection Register structions.
Write (PRWRITE) instruction. It can be read using The Protection Register Clear (PRCLEAR) in-
the Protection Register Read (PRREAD) instruc- struction clears the Protection Flag to 1. Both the
tion. Protection Enable (PRE) and Write Enable (W)
The Protection Register Enable (PREN) instruc- signals must be driven High during the instruction
tion must be executed before any PRCLEAR, execution.
PRWRITE or PRDS instruction, and with appropri- Note: A Protection Register Enable (PREN) in-
ate levels applied to the Protection Enable (PRE) struction must immediately precede the Protection
and Write Enable (W) signals. Register Clear (PRCLEAR) instruction.
Write-access to the Protection Register is Protection Register Write
achieved by executing the following sequence: The Protection Register Write (PRWRITE) instruc-
– Execute the Write Enable (WEN) instruction tion is used to write an address into the Protection
– Execute the Protection Register Enable Register. This is the address of the first word to be
(PREN) instruction protected. After the Protection Register Write
(PRWRITE) instruction has been executed, all
– Execute one PRWRITE, PRCLEAR or PRDS memory locations equal to and above the speci-
instructions, to set a new boundary address in
fied address are protected from writing.
the Protection Register, to clear the protection
address (to all 1s), or permanently to freeze The Protection Flag bit is set to 0, and can be read
the value held in the Protection Register. with Protection Register Read (PRREAD) instruc-
tion. Both the Protection Enable (PRE) and Write
Protection Register Read
Enable (W) signals must be driven High during the
The Protection Register Read (PRREAD) instruc- instruction execution.
tion outputs, on Serial Data Output (Q), the con-
Note: A Protection Register Enable (PREN) in-
tent of the Protection Register, followed by the struction must immediately precede the Protection
Protection Flag bit. The Protection Enable (PRE)
Register Write (PRWRITE) instruction, but it is not
signal must be driven High before and during the
necessary to execute first a Protection Register
instruction.
Clear (PRCLEAR).
As with the Read Data from Memory (READ) in- Protection Register Disable
struction, a dummy 0 bit is output first. Since it is
not possible to distinguish between the Protection The Protection Register Disable (PRDS) instruc-
Register being cleared (all 1s) or having been writ- tion sets the One Time Programmable (OTP) bit.
ten with all 1s, the user must check the Protection This instruction is a ONE TIME ONLY instruction
Flag status (and not the Protection Register con- which latches the Protection Register content, this
tent) to ascertain the setting of the memory protec- content is therefore unalterable in the future. Both
tion. the Protection Enable (PRE) and Write Enable (W)
signals must be driven High during the instruction
Protection Register Enable execution. The OTP bit cannot be directly read, it
The Protection Register Enable (PREN) instruc- can be checked by reading the content of the Pro-
tion is used to authorize the use of instructions that tection Register, using the Protection Register
modify the Protection Register (PRWRITE, Read (PRREAD) instruction, then by writing this
PRCLEAR, PRDS). The Protection Register En- same value back into the Protection Register, us-

14/34
 M93S66, M93S56, M93S46

ing the Protection Register Write (PRWRITE) in- COMMON I/O OPERATION
struction. When the OTP bit is set, the Ready/Busy Serial Data Output (Q) and Serial Data Input (D)
status cannot appear on Serial Data Output (Q). can be connected together, through a current lim-
When the OTP bit is not set, the Busy status ap- iting resistor, to form a common, single-wire data
pears on Serial Data Output (Q). bus. Some precautions must be taken when oper-
Note: A Protection Register Enable (PREN) in- ating the memory in this way, mostly to prevent a
struction must immediately precede the Protection short circuit current from flowing when the last ad-
Register Disable (PRDS) instruction. dress bit (A0) clashes with the first data bit on Se-
rial Data Output (Q). Please see the application
note AN394 for details.

Figure 8. Write Sequence with One Clock Glitch

An An-1 An-2

START "0" "1" Glitch D0

ADDRESS AND DATA

WRITE ARE SHIFTED BY ONE BIT
AI01395

CLOCK PULSE COUNTER aborted, and the contents of the memory are not
In a noisy environment, the number of pulses re- modified.
ceived on Serial Clock (C) may be greater than the The number of clock cycles expected for each in-
number delivered by the Bus Master (the micro- struction, and for each member of the M93Sx6
controller). This can lead to a misalignment of the family, are summarized in Table 2. to Table 3.. For
instruction of one or more bits (as shown in Figure example, a Write Data to Memory (WRITE) in-
8.) and may lead to the writing of erroneous data struction on the M93S56 (or M93S66) expects 27
at an erroneous address. clock cycles from the start bit to the falling edge of
To combat this problem, the M93Sx6 has an on- Chip Select Input (S). That is:
chip counter that counts the clock pulses from the 1 Start bit
start bit until the falling edge of the Chip Select In- + 2 Op-code bits
put (S). If the number of clock pulses received is + 8 Address bits
not the number expected, the WRITE, PAWRITE,
WRALL, PRWRITE or PRCLEAR instruction is + 16 Data bits

15/34
M93S66, M93S56, M93S46

MAXIMUM RATING
Stressing the device above the rating listed in the plied. Exposure to Absolute Maximum Rating con-
Absolute Maximum Ratings" table may cause per- ditions for extended periods may affect device
manent damage to the device. These are stress reliability. Refer also to the STMicroelectronics
ratings only and operation of the device at these or SURE Program and other relevant quality docu-
any other conditions above those indicated in the ments.
Operating sections of this specification is not im-

Table 4. Absolute Maximum Ratings

Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering See note 1 °C

VOUT Output range (Q = VOH or Hi-Z) –0.50 VCC+0.5 V

VIN Input range –0.50 VCC+1 V

VCC Supply Voltage –0.50 6.5 V

VESD Electrostatic Discharge Voltage (Human Body model) 2 –4000 4000 V

®
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

16/34
 M93S66, M93S56, M93S46

DC AND AC PARAMETERS
This section summarizes the operating and mea- ment Conditions summarized in the relevant
surement conditions, and the DC and AC charac- tables. Designers should check that the operating
teristics of the device. The parameters in the DC conditions in their circuit match the measurement
and AC Characteristic tables that follow are de- conditions when relying on the quoted parame-
rived from tests performed under the Measure- ters.

Table 5. Operating Conditions (M93Sx6)

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 4.5 5.5 V

Ambient Operating Temperature (Device Grade 6) –40 85 °C

TA
Ambient Operating Temperature (Device Grade 3) –40 125 °C

Table 6. Operating Conditions (M93Sx6-W)

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.5 5.5 V

TA Ambient Operating Temperature (Device Grade 6) –40 85 °C

Table 7. Operating Conditions (M93Sx6-R)

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 1.8 5.5 V

TA Ambient Operating Temperature (Device Grade 6) –40 85 °C

Table 8. AC Measurement Conditions (M93Sx6)

Symbol Parameter Min. Max. Unit

CL Load Capacitance 100 pF

Input Rise and Fall Times 50 ns

Input Pulse Voltages 0.4 V to 2.4 V V

Input Timing Reference Voltages 1.0 V and 2.0 V V

Output Timing Reference Voltages 0.8 V and 2.0 V V

Note: Output Hi-Z is defined as the point where data out is no longer driven.

Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6-R)

Symbol Parameter Min. Max. Unit

CL Load Capacitance 100 pF

Input Rise and Fall Times 50 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input Timing Reference Voltages 0.3VCC to 0.7VCC V

Output Timing Reference Voltages 0.3VCC to 0.7VCC V

Note: Output Hi-Z is defined as the point where data out is no longer driven.

17/34
M93S66, M93S56, M93S46

Figure 9. AC Testing Input Output Waveforms

M93SXX
2.4V
2V 2.0V

1V 0.8V
0.4V
INPUT OUTPUT

M93SXX-W & M93SXX-R

0.8VCC
0.7VCC

0.3VCC
0.2VCC

AI02791

Table 10. Capacitance

Symbol Parameter Test Condition Min Max Unit
COUT Output 5 pF
VOUT = 0V
Capacitance
CIN Input 5 pF
VIN = 0V
Capacitance
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 1 MHz.

18/34
 M93S66, M93S56, M93S46

Table 11. DC Characteristics (M93Sx6, Device Grade 6)

Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA

VCC = 5V, S = VIH, f = 1 MHz, Current

1.5 mA
Product 1
ICC Supply Current
VCC = 5V, S = VIH, f = 2 MHz, New
2 mA
Product 2
VCC = 5V, S = VSS, C = VSS,
50 µA
Current Product 1
ICC1 Supply Current (Stand-by)
VCC = 5V, S = VSS, C = VSS,
15 µA
New Product 2
VIL Input Low Voltage VCC = 5V ± 10% –0.45 0.8 V

VIH Input High Voltage VCC = 5V ± 10% 2 VCC + 1 V

VOL Output Low Voltage VCC = 5V, IOL = 2.1mA 0.4 V

VOH Output High Voltage VCC = 5V, IOH = –400µA 2.4 V

Note: 1. Current product: identified by Process Identification letter F or M.
2. New product: identified by Process Identification letter W or G.

Table 12. DC Characteristics (M93Sx6, Device Grade 3)

Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA

VCC = 5V, S = VIH, f = 1 MHz, Current

1.5 mA
Product 1
ICC Supply Current
VCC = 5V, S = VIH, f = 2 MHz, New
2 mA
Product 2
VCC = 5V, S = VSS, C = VSS,
50 µA
Current Product 1
ICC1 Supply Current (Stand-by)
VCC = 5V, S = VSS, C = VSS,
15 µA
New Product 2
VIL Input Low Voltage VCC = 5V ± 10% –0.45 0.8 V

VIH Input High Voltage VCC = 5V ± 10% 2 VCC + 1 V

VOL Output Low Voltage VCC = 5V, IOL = 2.1mA 0.4 V

VOH Output High Voltage VCC = 5V, IOH = –400µA 2.4 V

Note: 1. Current product: identified by Process Identification letter F or M.
2. New product: identified by Process Identification letter W or G.

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M93S66, M93S56, M93S46

Table 13. DC Characteristics (M93Sx6-W, Device Grade 6)

Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA

VCC = 5V, S = VIH, f = 1 MHz, Current

1.5 mA
Product 1
VCC = 2.5V, S = VIH, f = 1 MHz, Current
1 mA
Supply Current (CMOS Product 1
ICC
Inputs) VCC = 5V, S = VIH, f = 2 MHz, New
2 mA
Product 2
VCC = 2.5V, S = VIH, f = 2 MHz, New
1 mA
Product 2
VCC = 2.5V, S = VSS, C = VSS,
10 µA
Current Product 1
ICC1 Supply Current (Stand-by)
VCC = 2.5V, S = VSS, C = VSS,
5 µA
New Product 2

VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V

VIH Input High Voltage (D, C, S) 0.7 VCC VCC + 1 V

VCC = 5V, IOL = 2.1mA 0.4 V

VOL Output Low Voltage (Q)
VCC = 2.5V, IOL = 100µA 0.2 V

VCC = 5V, IOH = –400µA 2.4 V

VOH Output High Voltage (Q)
VCC = 2.5V, IOH = –100µA VCC–0.2 V
Note: 1. Current product: identified by Process Identification letter F or M.
2. New product: identified by Process Identification letter W or G.

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 M93S66, M93S56, M93S46

Table 14. DC Characteristics (M93Sx6-W, Device Grade 3)

Symbol Parameter Test Condition Min 1. Max. 1 Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA

Supply Current (CMOS VCC = 5V, S = VIH, f = 2 MHz 2 mA

ICC
Inputs) VCC = 2.5V, S = VIH, f = 2 MHz 1 mA

ICC1 Supply Current (Stand-by) VCC = 2.5V, S = VSS, C = VSS 5 µA

VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V

VIH Input High Voltage (D, C, S) 0.7 VCC VCC + 1 V

VCC = 5V, IOL = 2.1mA 0.4 V
VOL Output Low Voltage (Q)
VCC = 2.5V, IOL = 100µA 0.2 V

VCC = 5V, IOH = –400µA 2.4 V

VOH Output High Voltage (Q)
VCC = 2.5V, IOH = –100µA VCC–0.2 V
Note: 1. New product: identified by Process Identification letter W or G.

Table 15. DC Characteristics (M93Sx6-R)

Symbol Parameter Test Condition Min. 1 Max. 1 Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA

Supply Current (CMOS VCC = 5V, S = VIH, f = 2 MHz 2 mA

ICC
Inputs) VCC = 1.8V, S = VIH, f = 1 MHz 1 mA

ICC1 Supply Current (Stand-by) VCC = 1.8V, S = VSS, C = VSS 2 µA

VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V

VIH Input High Voltage (D, C, S) 0.8 VCC VCC + 1 V

VOL Output Low Voltage (Q) VCC = 1.8V, IOL = 100µA 0.2 V

VOH Output High Voltage (Q) VCC = 1.8V, IOH = –100µA VCC–0.2 V
Note: 1. Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office.

21/34
M93S66, M93S56, M93S46

Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3)

Test conditions specified in Table 8. and Table 5.

Symbol Alt. Parameter Min.3 Max.3 Min.4 Max.4 Unit

fC fSK Clock Frequency D.C. 1 D.C. 2 MHz

tPRVCH tPRES Protect Enable Valid to Clock High 50 50 ns

tWVCH tPES Write Enable Valid to Clock High 50 50 ns

tCLPRX tPREH Clock Low to Protect Enable Transition 0 0 ns

Chip Select Low to Write Enable

tSLWX tPEH 250 250 ns
Transition
tSLCH Chip Select Low to Clock High 250 50 ns

Chip Select Set-up Time

50 50 ns
M93C46, M93C56, M93C66
tSHCH tCSS
Chip Select Set-up time
100 50 ns
M93C76, M93C86

tSLSH2 tCS Chip Select Low to Chip Select High 250 200 ns

tCHCL1 tSKH Clock High Time 250 200 ns

tCLCH1 tSKL Clock Low Time 250 200 ns

tDVCH tDIS Data In Set-up Time 100 50 ns

tCHDX tDIH Data In Hold Time 100 50 ns

tCLSH tSKS Clock Set-up Time (relative to S) 100 50 ns

tCLSL tCSH Chip Select Hold Time 0 0 ns

tSHQV tSV Chip Select to Ready/Busy Status 400 200 ns

tSLQZ tDF Chip Select Low to Output Hi-Z 200 100 ns

tCHQL tPD0 Delay to Output Low 400 200 ns

tCHQV tPD1 Delay to Output Valid 400 200 ns

tW tWP Erase/Write Cycle time 10 5 ms

Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. Current product: identified by Process Identification letter F or M.
4. New product: identified by Process Identification letter W or G.

22/34
 M93S66, M93S56, M93S46

Table 17. AC Characteristics (M93Sx6-W, Device Grade 6)

Test conditions specified in Table 9. and Table 6.

Symbol Alt. Parameter Min.3 Max.3 Min.4 Max.4 Unit

fC fSK Clock Frequency D.C. 1 D.C. 2 MHz

tPRVCH tPRES Protect Enable Valid to Clock High 50 50 ns

tWVCH tPES Write Enable Valid to Clock High 50 50 ns

tCLPRX tPREH Clock Low to Protect Enable Transition 0 0 ns

Chip Select Low to Write Enable

tSLWX tPEH 250 250 ns
Transition
tSLCH Chip Select Low to Clock High 250 50 ns

tSHCH tCSS Chip Select Set-up Time 100 50 ns

tSLSH2 tCS Chip Select Low to Chip Select High 1000 200 ns

tCHCL1 tSKH Clock High Time 350 200 ns

tCLCH1 tSKL Clock Low Time 250 200 ns

tDVCH tDIS Data In Set-up Time 100 50 ns

tCHDX tDIH Data In Hold Time 100 50 ns

tCLSH tSKS Clock Set-up Time (relative to S) 100 50 ns

tCLSL tCSH Chip Select Hold Time 0 0 ns

tSHQV tSV Chip Select to Ready/Busy Status 400 200 ns

tSLQZ tDF Chip Select Low to Output Hi-Z 200 100 ns

tCHQL tPD0 Delay to Output Low 400 200 ns

tCHQV tPD1 Delay to Output Valid 400 200 ns

tW tWP Erase/Write Cycle time 10 5 ms
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. Current product: identified by Process Identification letter F or M.
4. New product: identified by Process Identification letter W or G.

23/34
M93S66, M93S56, M93S46

Table 18. AC Characteristics (M93Sx6-W, Device Grade 3)

Test conditions specified in Table 9. and Table 6.

Symbol Alt. Parameter Min.3 Max.3 Unit

fC fSK Clock Frequency D.C. 2 MHz

tPRVCH tPRES Protect Enable Valid to Clock High 50 ns

tWVCH tPES Write Enable Valid to Clock High 50 ns

tCLPRX tPREH Clock Low to Protect Enable Transition 0 ns

tSLWX tPEH Chip Select Low to Write Enable Transition 250 ns

tSLCH Chip Select Low to Clock High 50 ns

tSHCH tCSS Chip Select Set-up Time 50 ns

tSLSH2 tCS Chip Select Low to Chip Select High 200 ns

tCHCL1 tSKH Clock High Time 200 ns

tCLCH1 tSKL Clock Low Time 200 ns

tDVCH tDIS Data In Set-up Time 50 ns

tCHDX tDIH Data In Hold Time 50 ns

tCLSH tSKS Clock Set-up Time (relative to S) 50 ns

tCLSL tCSH Chip Select Hold Time 0 ns

tSHQV tSV Chip Select to Ready/Busy Status 200 ns

tSLQZ tDF Chip Select Low to Output Hi-Z 100 ns

tCHQL tPD0 Delay to Output Low 200 ns

tCHQV tPD1 Delay to Output Valid 200 ns

tW tWP Erase/Write Cycle time 5 ms

Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. New product: identified by Process Identification letter W or G.

24/34
 M93S66, M93S56, M93S46

Table 19. AC Characteristics (M93Sx6-R)

Test conditions specified in Table 9. and Table 7.

Symbol Alt. Parameter Min.3 Max.3 Unit

fC fSK Clock Frequency D.C. 1 MHz

tPRVCH tPRES Protect Enable Valid to Clock High 50 ns

tWVCH tPES Write Enable Valid to Clock High 50 ns

tCLPRX tPREH Clock Low to Protect Enable Transition 0 ns

tSLWX tPEH Chip Select Low to Write Enable Transition 250 ns

tSLCH Chip Select Low to Clock High 250 ns

tSHCH tCSS Chip Select Set-up Time 50 ns

tSLSH2 tCS Chip Select Low to Chip Select High 250 ns

tCHCL1 tSKH Clock High Time 250 ns

tCLCH1 tSKL Clock Low Time 250 ns

tDVCH tDIS Data In Set-up Time 100 ns

tCHDX tDIH Data In Hold Time 100 ns

tCLSH tSKS Clock Set-up Time (relative to S) 100 ns

tCLSL tCSH Chip Select Hold Time 0 ns

tSHQV tSV Chip Select to Ready/Busy Status 400 ns

tSLQZ tDF Chip Select Low to Output Hi-Z 200 ns

tCHQL tPD0 Delay to Output Low 400 ns

tCHQV tPD1 Delay to Output Valid 400 ns

tW tWP Erase/Write Cycle time 10 ms

Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office.

25/34
M93S66, M93S56, M93S46

Figure 10. Synchronous Timing (Start and Op-Code Input)

PRE

tPRVCH

tWVCH tCHCL

tCLSH tSHCH tCLCH

tDVCH tCHDX

D START OP CODE OP CODE

OP CODE INPUT
START
AI02025

Figure 11. Synchronous Timing (Read or Write)

tCLSL

tDVCH tCHDX tCHQV tSLSH

D An A0

tCHQL tSLQZ
Hi-Z
Q Q15 Q0

ADDRESS INPUT DATA OUTPUT

AI002026

26/34
 M93S66, M93S56, M93S46

Figure 12. Synchronous Timing (Read or Write)

PRE

tCLPRX

tSLWX

tSLCH

tCLSL

tSLSH

tDVCH tCHDX

D An A0/D0

tSHQV tSLQZ
Hi-Z
Q BUSY READY

tW

ADDRESS/DATA INPUT WRITE CYCLE

AI02027

27/34
M93S66, M93S56, M93S46

PACKAGE MECHANICAL

Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline

b2 E

A2 A

A1 L

b e c
eA

eB
D

E1

1
PDIP-B

Note: Drawing is not to scale.

Table 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 5.33 0.210
A1 0.38 0.015
A2 3.30 2.92 4.95 0.130 0.115 0.195
b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1.52 1.14 1.78 0.060 0.045 0.070
c 0.25 0.20 0.36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280
e 2.54 – – 0.100 – –
eA 7.62 – – 0.300 – –
eB 10.92 0.430
L 3.30 2.92 3.81 0.130 0.115 0.150

28/34
 M93S66, M93S56, M93S46

Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline

h x 45˚

A
C
B
e CP

E H
1

A1 α L

SO-a

Note: Drawing is not to scale.

Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N 8 8
CP 0.10 0.004

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M93S66, M93S56, M93S46

Figure 15. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline

8 5 c

E1 E

1 4

A1 L
A A2
CP L1

b e
TSSOP8BM

Note: Drawing is not to scale.

Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
mm inches
Symbol
Typ. Min. Max. Typ. Min. Max.
A 1.100 0.0433
A1 0.050 0.150 0.0020 0.0059
A2 0.850 0.750 0.950 0.0335 0.0295 0.0374
b 0.250 0.400 0.0098 0.0157
c 0.130 0.230 0.0051 0.0091
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
E 4.900 4.650 5.150 0.1929 0.1831 0.2028
E1 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
CP 0.100 0.0039
L 0.550 0.400 0.700 0.0217 0.0157 0.0276
L1 0.950 0.0374
α 0° 6° 0° 6°

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 M93S66, M93S56, M93S46

Figure 16. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline

8 5
c

E1 E

1 4

A1 L
A A2
CP L1

b e
TSSOP8AM

Note: Drawing is not to scale.

Table 23. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm inches
Symbol
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α 0° 8° 0° 8°

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M93S66, M93S56, M93S46

PART NUMBERING

Table 24. Ordering Information Scheme

Example: M93S66 – W MN 6 T P

Device Type
M93 = MICROWIRE serial access EEPROM (x16) with
Block Protection

Device Function
66 = 4 Kbit (256 x 16)
56 = 2 Kbit (128 x 16)
46 = 1 Kbit (64 x 16)

Operating Voltage
blank = VCC = 4.5 to 5.5V
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V

Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
DS2 = TSSOP8 (3x3mm body size)

Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
3 = Automotive: device tested with High Reliability Certified Flow 1 over –40 to 125 °C

Option
blank = Standard Packing
T = Tape & Reel Packing

Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-
tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. Available only on new products: identified by the Process Identification letter W or G.
Devices are shipped from the factory with the For a list of available options (speed, package,
memory content set at all 1s (FFh). etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.

Table 25. How to Identify Current and New Products by the Process Identification Letter
Markings on Current Products1 Markings on New Products1
M93S46W6 M93S46W6
AYWWF (or AYWWM) AYWWW (or AYWWG)
Note: 1. This example comes from the S08 package. Other packages have similar information. For further information, please ask your ST
Sales Office for Process Change Notice PCN MPG/EE/0059 (PCEE0059).

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 M93S66, M93S56, M93S46

REVISION HISTORY

Table 26. Document Revision History

Date Rev. Description of Revision
Document reformatted, and reworded, using the new template. Temperature range 1 removed.
TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added,
07-Mar-2002 2.0
with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other ranges (and
corresponding parameters adjusted).
Value of standby current (max) corrected in DC characteristics tables for -W and -R ranges
26-Mar-2003 2.1
VOUT and VIN separated from VIO in the Absolute Maximum Ratings table

Values corrected in AC characteristics tables for -W range (tSLSH, tDVCH, tCLSL) for devices
14-Apr-2003 2.2
with Process Identification Letter W.
Standby current corrected for -R range. Four missing parameters restored to all AC
23-May-2003 2.3
Characteristics tables

24-Nov-2003 3.0 Table of contents, and Pb-free options added. VIL(min) improved to -0.45V.

Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature
19-Apr-2004 4.0 information clarified for RoHS compliant devices. Device Grade 3 clarified, with reference to
HRCF and automotive environments. Process identification letter “G” information added

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M93S66, M93S56, M93S46

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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All other names are the property of their respective owners.

© 2004 STMicroelectronics - All rights reserved

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