DHANALAKSHMI SRINIVASAN

COLLEGE OF ENGINEERING
COIMBATORE-641 105

LABORATORY MANUAL

NAME :
REGISTER NUMBER :
SUB CODE :: BM8411
SUBJECT TITLE :: INTEGRATED CIRCUITS LABORATORY

SEMESTER :IV
:
YEAR :II
:
DEPARTMENT :ELECTRONICS
: AND COMMUNICATION
ENGINEERING
 DHANALAKSHMI SRINIVASAN
COLLEGE OF ENGINEERING
COIMBATORE-641 105
BONAFIDE CERTIFICATE

This is to certify that this ……………………………………………………… (Lab Name)

Record work done by Mr/Ms………………………………………………………………..
For the Course B.E…………………………………………………………………During
….……………………………….(Year/Sem) of academic year 2019 – 2020 is Bonafide.

Staff-in-charge H.O.D

This Record is Submitted for ………………………………………………………semester B.E

Practical Examinations of Anna university held on ……………………………………

INTERNAL EXAMINER EXTERNAL EXAMINER

 BM8411 - Integrated Circuits Laboratory LPTC
00 4 2
LIST OF EXPERIMENTS

DESIGN AND TESTING OF

1. Inverting, Non Inverting and Differential amplifiers.
2. RC Phase shift oscillator and Wien Bridge Oscillator.
3. Instrumentation amplifier.
4. Active low-pass, high pass and band-pass filters.
5. Astable and monostable multivibrators and Schmitt trigger using op-amp.
6. RC Phase shift and wein bridge oscillators using op-amp.
7. Astable and monostable multivibrators using NE555 Timer.
8. PLL characteristics and its use as frequency Multiplier.
9. DC power supply using LM317 and LM723.
10.SPICE Simulation studies.

LIST OF DIGITAL EXPERIMENTS

11.Design and implementation of code converters using logic gates.
(i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice versa
12.Design and implementation of 4-bit binary Adder/Subtractor and BCD adder using IC
7483.
13.Design and Implementation of Multiplexer and De-multiplexer using logic gates.
14.Design and implementation of encoder and decoder using logic gates.
15.Construction and verification of 4-bit ripple counter andMod-10/Mod-12 counters.
16.Design and implementation of 3-bit synchronous up/down counter.
17.Implementation of SISO,SIPO,PIPO,PISO and shift registers using Flip-flops.

TOTAL : 45 PERIODS
 BM8411 - Integrated Circuits Laboratory
LTPC
0 0 3 2
LIST OF ANALOG EXPERIMENTS:
1. Inverting, Non inverting and Differential amplifiers.
2. Integrator and Differentiator.
3. Darlington Amplifier
4. Active low-pass, High-pass and band-pass filters.
5. Astable &Monostable multivibrators and Schmitt Trigger using op-amp.
6. Phase shift and Wein bridge oscillators using op-amp.
7. Astable and monostable multivibrators using NE555 Timer.
8. PLL characteristics and its use as Frequency Multiplier.
9. DC power supply using LM317 & LM723

LIST OF DIGITAL EXPERIMENTS

10. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa
11. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
12. Design and implementation of Multiplexer and De-multiplexer using logic gates.
13. Design and implementation of encoder and decoder using logic gates
14. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
15. Design and implementation of 3-bit synchronous up/down counter
16. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops.
17. SPICE Simulation studies.

TOTAL PERIODS: 45 PERIODS

 INDEX
ANALOG CIRCUITS

EXPT.NO NAME OF THE EXPERIMENT PAGE

NO

1 INVERTING, NON-INVERTING AND

DIFFERENTIAL AMPLIFIERS USING OP-AMP

2 INTEGRATOR AND DIFFERENTIATOR USING OP-

AMP.

3 INSTRUMENTATION AMPLIFIER

4 ACTIVE LOWPASS, HIGH PASS AND BAND PASS

FILTER USING OP-AMP.

5 ASTABLE, MONOSTABLE MULTIVIBRATOR AND

SCHMITT TRIGGER USING OP-AMP.

6 RC PHASE SHIFT AND WIEN BRIDGE

OSCILLATOR
USING OP-AMP

7 ASTABLE & MONOSTABLE MULTIVIBRATOR

USING IC 555 TIMER.

8 PLL CHARACTERISTICS AND FREQUENCY

MULTIPLIER USING PLL

9 DC POWER SUPPLY USING LM317 AND LM723

10 STUDY OF SMPS
DIGITAL CIRCUITS

1 STUDY OF LOGIC GATES

2a DESIGN OF ADDER AND SUBTRACTOR

DESIGN AND IMPLEMENTATION OF
2b CODE CONVERTORS

3 DESIGN OF 4-BIT ADDER AND

SUBTRACTOR
4 DESIGN AND IMPLEMENTATION
OF MULTIPLEXER AND
DEMULTIPLEXER

5 DESIGN AND IMPLEMENTATION OF

ENCODER AND DECODER

CONSTRUCTION AND VERIFICATION

6
OF 4 BIT RIPPLE COUNTER AND MOD
10/MOD 12 RIPPLE COUNTER

7 DESIGN AND IMPLEMENTATION OF 3

BIT SYNCHRONOUS UP/DOWN
COUNTER

8 DESIGN AND IMPLEMENTATION OF

SHIFT REGISTER
INVERTING AMPLIFIER:-
CIRCUIT DIAGRAM:-

Rf

+15v

R1=10K 2 7
-
IC 741
Signal
Generator + 3 + 4
6
+
~
Vin CRO
-15v
- -

TABULATION:

Theoretical Gain Practical Gain

S.No Rf (KΩ) Vin (Volts) Vout (Volts)
A = -Rf / R1 A = V0 / Vin
1. 1K
2. 10K
3. 33K
4. 100K

MODEL GRAPH:
Vin

INPUT

Time (ms)

Vout

OUTPUT

Time (ms)
 Dept of Electronics & Communication Engg

INVERTING, NON-INVERTING AND DIFFERENTIAL

AMPLIFIERS USING OP-AMP

EXP.NO: 01 DATE:
AIM:
To design the Inverting, Non-Inverting and Differential Amplifiers using
Op-amp IC741 and test their performance.

APPARATUS REQUIRED:
S.NO COMPONENTS RANGE QUANTITY
1. IC 741 01
1KΩ, 33KΩ EACH 01
2. RESISTORS
10KΩ, 100 KΩ. EACH 02
3. DIGITAL TRAINER KIT --- 01
4. SIGNAL GENERATOR (0-3)MHz 01
5. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
6. CONNECTING WIRES --- FEW

THEORY:
Op-amp in open-loop configuration has a very few application because
of its enormous open-loop gain. Controlled gain can be can be achieved by taking a
part of output signal to the input with the help of feedback. This is called as Closed-
Loop Configuration. The three basic types of closed-loop amplifier configuration
are: 1. Inverting amplifier.
2. Non-inverting amplifier.
3. Differential amplifier.
The entire configuration can be operated with either AC or DC input.

INVERTING AMPLIFIER:-

If the input signal is applied to the inverting terminal through an input

resistance, a part of output is feedback to the inverting terminal through feedback
resistance Rf and the non-inverting terminal grounded, then the configuration is said
to be Inverting Amplifier. It provides 1800 phase shift or polarity reversal for the
given input.

Rf
The circuit closed-loop voltage gain is Avcl .
R1

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 Dept of Electronics & Communication Engg

NON-INVERTING AMPLIFER:-
CIRCUIT DIAGRAM:-

Rf

+15v
R1=10K 2 7
-
IC 741
+ 6
+ 3 4 +
Signal Vin
~ CRO
Generator - -15v
-

TABULATION:

Vin Vout Theoretical Gain Practical Gain

S.No Rf (KΩ)
(Volts) (Volts) A = 1+(Rf / R1) A = V0 / Vin
1. 1K
2. 10K
3. 33K
4. 100K

MODEL GRAPH:

Vin

INPUT

Time (ms)

OUTPUT

Vout
Time (ms)

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 Dept of Electronics & Communication Engg
THEORY – (NON-INVERTING AMPLIFIER):-
If the input signal is given to non inverting terminal & the feedback
from output is connected to inverting terminal of an op-amp through a potential
divider network, then it is called as Non-Inverting Amplifier Configuration. It
operates in a same way as a voltage follower (unity gain buffer), except that the
output voltage is potentially divided before it is fedback to the inverting input
terminal. No phase shift or change in the circuit closed loop polarity occurs voltage

Rf
gain is Avcl 1
R1

PROCEDURE-(INVERTING & NON-INVERTING AMPLIFIER):-

1. Select R1 as a constant value and choose a value of Rf.
2. Connect the circuit as per as the circuit diagram.
3. Apply the constant amplitude input voltage to the circuit.
4. Measure the output voltage amplitude for different value of Rf from CRO.
5. Calculate the practical gain for different value of Rf & compare it with
theoretical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for any one practical case.

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DIFFERENTIAL AMPLIFIER:-
CIRCUIT DIAGRAM:-
Rf=R2=100K

+15v
2 7
R1=10k -
Signal IC 741
Generators R1=10K 3 + 4
6
+
+ +
~ ~ R2=100K CRO
Vin1 Vin2 -15v
-

TABULATION:

Vin1 Vin2 Vin2 - Vin1 V0 Theoretical Gain Practical Gain

S.No
(Volts) (Volts) (Volts) (Volts) A = -Rf / R1 A=V0 / (Vin2 - Vin1)
1.

2.

3.

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 Dept of Electronics & Communication Engg

THEORY-(DIFFERENTIAL AMPLIFIER):-
A configuration which combines inverting & non-inverting
configuration with both input terminals are supplied with Vin1 & Vin2, then it is
called as Differential Amplifier configuration. This circuit amplifies the difference
between the two inputs. Differential amplifier with a single op-amp has the exact gain
of an inverting amplifier and it is given as

Vo Rf
AD (Using One Op- AVCL
Amp) (Vin1 Vin2 ) R1

A differential amplifier with two op-amps has the exact gain of a non-inverting
amplifier and it is given as:

Vo Rf
AD (Using Two Op-Amps) AVCL 1 .
(Vin1 Vin2 ) R1

PROCEDURE:
1. Select the value of R1, R2, R3 & Rf such that R1=R2 and R3=Rf.
2. Connect the circuit as per as the circuit diagram.
3. Provide constant input voltage Vin1 to Non-inverting terminal of op-amp
through R1 & constant input voltage Vin2 to inverting terminal of op-amp
through R2.
4. Measure the output voltage using CRO.
5. Calculate the theoretical gain and compare it with practical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for any one practical case.

RESULT:
Thus the Inverting, Non-Inverting and Differential Amplifiers are
designed and their performance was successfully tested using op-amp IC 741.

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 Dept of Electronics & Communication Engg

INTEGRATOR:- CIRCUIT
DIAGRAM:-
Cf=0.01uf

Rf=15k
+15v
R1=1.5k 2 - 7
6
Signal IC 741
Generat+ors +
3 4 +
V~
1.5K RL=10k
in Rcomp CRO
-15v
-

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

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MODELGRAPH:

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 Dept of Electronics & Communication Engg

INTEGRATOR AND DIFFERENTIATOR USING OP-AMP.

EXP.NO: 02 DATE:
AIM:
To design an Integrator and Differentiator using op-amp IC 741 and to test their
performance.

APPARATUS REQUIRED:
S.NO COMPONENTS RANGE QUANTITY
1. IC 741 --- 01
100 Ω, 1.5KΩ Each 02
2. RESISTORS
10KΩ, 15KΩ Each 01
0.1μf, 0.01μf Each 01
3. CAPACITOR
0.001μf, 05
4. DIGITAL TRAINER KIT --- 01
5. SIGNAL GENERATOR (0-3)MHz 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW
THEORY – (INTEGRATOR):-
A circuit in which the output voltage waveform is the integral of the
input voltage waveform is the integrator or integration amplifier; Such a circuit is
obtained by using basic inverting amplifier configuration, if the feed back resistor Rf
is replaced by a capacitor Cf. The Output voltage expression is given as
t
1
VO Vin dt C.
R1C f o

The frequency of input at which the gain is 0 db is given as fb 1

2 R1C f

The point up to which the gain is constant & maximum is called as gain limiting
frequency & given as fa 1 Where Rf is the feedback resistor used to correct
2 Rf Cf
the stability & roll-off problems. Between fa & fb the circuit acts as an integrator and
it is similar to a LPF. Integrator is most commonly used in analog computers, A/D
converter & signal wave shaping circuits.
Integrator as LPF (Characteristics of integrator)
Design of integrator with a lower frequency (Break Frequency) limit of
integration at fa = 1 KHz & the frequency at which 0dB results fb = 10 KHz.
PROCEDURE:
1. From the given frequency fa & fb, the values of Rf, Cf, R1 & Rcomp are
calculated as given in the design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the sinusoidal input as the constant amplitude to the inverting terminal
of op-amp.
4. Gradually increase the frequency & observe the output amplitude.
5. Calculate the gain with respect to frequency & plot its graph.
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 Dept of Electronics & Communication Engg

CIRCUIT DIAGRAM:
Cf=0.005μf

Rf=1.5k
+15v
R1=100Ω C1=0.1μf 2 - 7 6
IC 741
+ 3 + 4 +
Signal ROM=100Ω R3=10K CRO
Generators -15v
-

0
TABULATION:

1. Frequency (Input)
2. Input Voltage (Vin peak)
3. Input Time Period (tVin)
4. Output Voltage (Vout peak)
5. Output Time Period (tVo)

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MODEL GRAPH:
(i) SINE WAVE INPUT

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 Dept of Electronics & Communication Engg

THEORY- (DIFFERENTIATOR):-
A differentiator or differentiation amplifier is a circuit which performs
the mathematical operation of differentiation; that is, the output waveform is the
derivative of the input waveform. The differentiator may be constructed from the
basic inverting amplifier if an input resistor R1 is replaced by capacitor C1. The
differentiation is very useful to find the rate at which a signal varies with time. For
maintaining the stability of differentiator, a series resistor R1 is connected with input
capacitor C1. the circuit will provide differentiation function but only over a limited
frequency range & over this range differentiator tend to oscillate (or) poor stability

dVin
results. The expression for output voltage is Vo R fC 1
dt

PROCEDURE:
1. Select fa equal to the highest frequency of the input signal to be differentiated.
Calculate the component values of C1 & Rf.
2. Choose fb = 20fa & calculate the values of R1 & Cf, so that R1C1=Rf Cf.
3. Connect the components as shown in the circuit diagram.
4. Apply a sinusoidal & square wave input to the inverting terminal of op-amp
through R1 C1.
5. Observe the shape of the output signal for the given input in CRO.
6. Note down the reading and plot the graph of input versus output wave for both
cases.
(ii) SQUARE WAVE INPUT

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DESIGN PROCEDURE-(INTEGRATOR):-
Design of integrator to integrate at cut-off frequency 1 KHz.
1
Take fa =
2 Rf C f

= 1KHz.
Always take Cf < μf and

Let Cf = 0.01μf

1
Rf =
2 C f fa

Rf = 15.9KΩ ≡

Rf = 15KΩ

1
Take fb = = 10KHz.
2 R1C f

1
R1 = = 1.59KΩ.
2 fb C f

R1 ≡1.5KΩ

R1 Rf
Rcomp = R1 // Rf = ≡R1, Assume RL = 10KΩ
R1 R f

Rcomp = 1.5KΩ

DESIGN PROCEDURE-(DIFFERENTIATOR):-
Design a differentiator to differentiate an input signal that varies in frequency
from 10Hz to 1KHz. Apply a sine wave & square wave of 2Vp-p & 1KHz frequency
& observe the output.
To find Rf & C1
Given: fa = 1KHz.
1
fa =
2 R f C1

fa = 1KHz.

Assume C1 = 0.1μf

Rf = 1.59KΩ ≡1.5KΩ

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 Dept of Electronics & Communication Engg

To find R1 & Cf
Select fb = 20fa with R1 C1 = Rf Cf
1
fb = 20KHz =
2 R1C1

R1 = 79.5Ω ≡100Ω

R1C1 82 X 0.1X10 6
Cf = =
Rf 1.5K

Cf = 0.005μf.

Rom ≡R1 // Rf = 100Ω

SINE WAVE INPUT:

Vp-p = 2V f=1KHz
Vp = 1V,
Vin = Vp sin t
= sin (2 )(103)t
dVin
Vo = -Rf c1
dt
d
= -(1.5KΩ) (0.1μf) [sin [(2 )(103)t]
dt
= -(1.5KΩ) (0.1μf) (2 ) (103) cos [(2 )(103)t]
= - 0.94 cos [(2 )(103)t]

RESULT:
Thus an Integrator and Differentiator using op-amp are designed and their
performance was successfully tested using op-amp IC 741.

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 Dept of Electronics & Communication Engg

CIRCUIT DIAGRAM:

+15v

3 7
+ Rf=1K
IC 741
6
2 - 4
+15v
R2=1K
-15v
R1=1K 2 7
-
IC 741
6
RG 22K 3 + 4
+ R1=1K

~
V1 -15v
R2=1K
- +

+15v R1=1K V
-
2 7
-
IC 741
6
+ 3 + 4

~
V2
-15v
-

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 Dept of Electronics & Communication Engg

INSTRUMENTATION AMPLIFIER

EXP.NO: 03 DATE:

AIM:
To construct and test the CMRR of an instrumentation amplifier using op-amp
IC741.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 03
1KΩ. 06
2. RESISTORS
22KΩ 01
3. DIGITAL TRAINER KIT --- 01
4. SIGNAL GENERATOR (0-3)MHz 02
5. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
6. CONNECTING WIRES --- FEW

THEORY:

An instrumentation amplifier is the intermediate stage of a instrumentation

system. The signal source of the instrumentation amplifier is the output of the
transducer. Many transducers output do not have the ability or sufficient strength to
drive the next following stages. Therefore, instrumentation amplifiers are used to
amplify the low-level output signal of the transducer so that it can drive the following
stages such as indicator or displays.
The major requirements of a instrumentation amplifier are precise,
low-level signal amplification where low-noise, low thermal and time drifts, high
input resistance & accurate closed-loop gain, low power consumption, high CMRR &
high slew rate for superior performance.

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 Dept of Electronics & Communication Engg

TABULATION:

COMMON MODE GAIN CALCULATION AC

Vo
RG VI V2 Vo Ac =
S.No V1 V2
(KΩ) (Volts) (Volts) (Volts)
2

1.

2.

3.

4.

5.

DIFFERENTIAL MODE GAIN AD & CMRR CALCULATION.

V1 V2 Vo Vo CMRR =
S.No RG (KΩ) Ad =
20 log ( Ad Ac )(dB)
(Volts) (Volts) (Volts) V1 V2

1.

2.

3.

4.

5.

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 Dept of Electronics & Communication Engg

PROCEDURE:
1. Select the entire resistor with same value of resistance R. Let RG be the gain
varying resistor with different values of resistance for simplicity let RG, be a
constant value.
2. Connect the circuit as shown in the circuit diagram.
3. Give the input V1 & v2 to the non-inverting terminals of first & second op-
amp respectively.
4. By varying the value of RG, measure the output voltage for common mode and
differential mode operation. Since RG is selected as constant value, provide
different input value of V1 & V2.
5. Calculate the differential mode gain Ad and common mode gain Ac to
Ad
calculate the CMRR as CMRR=20 log .
Ac

RESULT:
Thus an instrumentation amplifier was constructed and CMRR is
tested using op-amp IC 741.

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 Dept of Electronics & Communication Engg

LOWPASS FILTER:-
CIRCUIT DIAGRAM:-
RF=20K
R1=27K

+15v
2 - 7
Signal IC 741
Generator 1.5K
+ 6
3 4
+ +
Vin ~ 0.1uf
-15v
RL=10K CRO
-

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

MODEL GRAPH:

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Dept of Electronics & Communication Engg

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 Dept of Electronics & Communication Engg

ACTIVE LOWPASS, HIGH PASS AND BAND PASS FILTER

USING OP-AMP.
EXP.NO: 04 DATE:
AIM:
To design an Active Lowpass and Band Pass Filter using op-amp and to test
their performance

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 --- 02
1.5 KΩ,22KΩ, 27KΩ EACH 02
2. RESISTORS
10KΩ 01
3. CAPACITORS 0.1μf, 0.01μf 01
4. DIGITAL TRAINER KIT --- 01
5. SIGNAL GENERATOR (0-3)MHz 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW

THEORY – (ACTIVE LPF):-

A filter circuit which allows only low frequency range up to a higher

cut-off frequency fH is called as Low Pass Filter. An active filter uses transistor and
components such as resistor & capacitor for its design. An active filter offers the
following advantages over a passive filter.
1. Gain & frequency adjustment flexibility.
2. No loading problem because of high input impedance & low output impedance.
3. More economical because of variety of op-amps and absence of inductors.

From the frequency response, when f<fH; the gain is maximum lAl. When

f=f ; the gain is 70.7% of the maximum gain A and when f f the gain drops or
H H;
2
rolls off. The frequency range from 0 to fH is called as Passband & fH to is called
as Stopband. Out of Butterworth, chebyshev & cauer filters, Butterworth filter is
preferred because it has flat pass band as well as flat stop band (flat-flat) filter.

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 Dept of Electronics & Communication Engg

CIRCUIT DIAGRAM - (HIGH PASS FILTER):-

R1=27K RF=22K

+15v
2 7
Signal 0.1μf
-
IC 741
Generator
+ 6
3 4 +
+
Vin ~ 1.5K -15v
RL=10K CRO
-

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

MODEL GRAPH:

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 Dept of Electronics & Communication Engg

THEORY- (ACTIVE HPF):-

An active high pass filter is simply formed by interchanging the
frequency determining resistor and capacitor in lowpass filter. A filter circuit which
allows only high frequency range greater then a lower cut-off frequency fL is called
as HIGH PASS FILTER. From the frequency response, when f<fL; the gain
gradually increases from the lowest value. When f = fL; the gain reaches 70.7% of the
A
maximum gain and when f > fL, the gain is maximum lAl. The frequency range
2
from 0 to fL is called as Stopband & fL to is called as Passband. (This is exactly
opposite to active LPF)The order of the filter tells the roll-off rate at stop band. Order
n = 1 indicates -20dB / dec (-6db / octave); Order n = 2 indicates -40dB / dec & so on.
Higher the order of the filter, better the quality will be & complex the circuit will be.

DESIGN PROCEDURE: (ACTIVE HPF):

Design a HPF at cutoff frequency fL of 1KHZ & P.B gain of 2. Follow the same
procedure as LPF & interchange the R & C position with capacitor first & resistor in
parallel.
Vo Af ( f / f L )
In high pass filter Theoretical gain is given as =
Vin 1 (f/f )2
H

PROCEDURE - (LPF & HPF):

1. Connect the circuit as shown in the circuit diagram.
2. Select the corresponding cut-off frequency (higher or lower) and determine the
value of C&R. select the value of R1 & Rf depending on desired passband
gain Af..
3. Apply a constant voltage input sinusoidal signal to the non-inverting terminal
of op-amp.
4. Tabulate the output voltage Vo with respect to different values of input
frequency.
5. Calculate passband gain and plot the graph of frequency versus voltage gain &
check the graph to get approximately the same characteristic as shown in the
model graph.

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 Dept of Electronics & Communication Engg

CIRCUIT DIAGRAM: (BANDPASS FILTER)

R1=27K RF=20K
R1=27K RF=20K

+15v
+15v
2 7
2 7
-
- IC 741
6
Signal
Generator
0.1uf
IC 741 3 + 4
+ 3 + 4
6 1.5K
+
CRO
Vin ~ 1.5K -15v
0.01uf -15v
RL=10K -

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)

MODEL GRAPH:

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 Dept of Electronics & Communication Engg

THEORY – (ACTIVE BANDPASS FILTER):-

A filter which has a pass band between two cut-off frequencies fH & fL
is called as Bandpass filter. Where fH > fL BPF is basically of two types
(i) Wide band pass filter. (ii) Narrow band pass filter.
Based on figure of merit or quality factor Q, the types are classified as follows. If
Q<10, selectivity is poor & allows higher bandwidth & such BPF is called as wide
BPF.
If Q > 10, selective is more and allows only narrow bandwidth & such
BPF is called as Narrow BPF. Relationship between Q & center frequency fC is
given as

fc fc
Q & fc fH fL
BW fH fL

When frequency fL < f < fH then gain is maximum. At f < fL the gain is
gradually increasing (positive roll-off) from lower value & at f > fH the gain is
gradually decreasing (Negative roll-off) & exactly when f = fL & f = fH the gain is
A
70.7% of maximum gain .
2
PROCEDURE:
1. Select the lower and higher cut-off frequency and calculate the value of R & C
for the given frequencies.
2. Design for LPF & HPF separately and then combine the circuit by first placing
the HPF followed by a LPF (i.e) HPF in series with LPF.
3. Connect the circuit as shown in the circuit diagram.
4. Apply a constant voltage input sinusoidal signal to the non-inverting terminal
of op-amp.
5. Tabulate the output voltage Vo with respect to different values of input
frequency.
6. Calculate passband gain and plot the graph of frequency versus voltage gain &
check the graph to get approximately the same characteristic as shown in the
model graph.

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DESIGN PROCEDURE - (ACTIVE BPF):-
Design a BPF to pass a band of 1KHz to 10KHz with a passband gain of 4.
1. Select the highest cut-off frequency of LPF as fH = 10 KHz and the lowest cut-
off frequency of HPF as fL = 1 KHz.
2. Design the HPF first by taking fL = 1KHz. Assume the value of C < 1μf.
Let C = 0.1μf.
3. Calculate R from the expression.
1 1
FL = ; Therefore R1 =
2 RC 2 f LC
1
R= ;
2 (1KHz)(0.1X10 6 )
R = 1.59KΩ ≡ R=1.5KΩ
4. Then design the LPF by taking fH = 10KHz. Assume the value of C < 1μf. Let
C = 0.01μf.
1 1
5. Calculate R from the expression fH = ; Therefore R =
2 RC 2 f HC

1
R= ;
2 (10KHz)(0.01X10 6 )

R = 1.59KΩ ≡ R=1.5KΩ

6. Calculate the values of Rf & R1 with the use of pass band gain.
Overall P.B gain of BPF = 4 = 2 (HPF) X 2 (LPF)

Therefore for both HPF & LPF the value of Rf = R1 to obtain a individual
Rf
P.B gain of 2. Af = (1+ ) = 2 (for HPF)
R1
Rf
Af = (1+ ) = 2 (for LPF)
R1
Let Rf = R1 = 22KΩ.

fc fc
7. Q of the filters is calculated as =
B.W fH fL

Where fC = f H f L is the center frequency.

8. Cascade HPF & then LPF to form BPF.
Calculate the practical gain dB using 20 log (Vo/Vin)
f
And Theoretical gain is Vo = AfT ( f )
L
Vin f f
[1 ( ) 2 ][1 ( )2 ]
f H f L

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DESIGN PROCEDURE (ACTIVE LPF):
Design a LPF at cutoff frequency fH of 1KHz with a passband gain of 2.
1. Choose the given value of fH = 1KHz.

2. Select the value of C < 1μf

1
3. Assume C = 0.1μf. Calculate R from FH =
2 RC
1
R=
2 f HC

1
R= = 1.5KΩ
2 X1X103 X 0.1 f
R = 1.5KΩ C = 0.1μf

4. Determine the value of R1 & Rf from pass band gain of the filter.
Rf
Af = 1 + = 2.
R1
Therefore Rf =R1 to select Af = 2.
Assume Rf = R1 = 22KΩ & Assume RL = 10KΩ

5. Calculate the practical gain in dB using Gain (dB)=20log (Vo/Vin);

Vo Af
Theoretical gain is given as =
Vin 1 (f/f H
)2
Af – P.B gain.
f – Input frequency.
fH – Higher cut-off frequency of LPF.

RESULT:
Thus an Active Lowpass, High pass and Band Pass Filters are designed
and tested using op-amp IC 741.

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CIRCUIT DIAGRAM - (ASTABLE):-

R=47K

+15v
0.01uf
2 - 7
IC 741
Vc + 6 R2=DRB
3 4
+
CRO
-
Vref R1=10K

TABULATION:

DESIGN VALUE OBSERVED VALUE

Amplitude
Waveforms tH tL t F tH tL t F
(volts)
(ms) (ms) (ms) (Hz) (ms) (ms) (ms) (Hz)

Output
waveform

Capacitive
waveform

MODEL GRAPH:

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 Dept of Electronics & Communication Engg

ASTABLE, MONOSTABLE MULTIVIBRATOR AND

SCHMITT TRIGGER USING OP-AMP.

EXP.NO: 05 DATE:
AIM:
To design an Astable, Monostable multivibrator and Schmitt trigger
using op-amp IC 741 and to test their characteristics.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 --- 01
100Ω, 100KΩ, EACH 01
2. RESISTORS
10KΩ, 47KΩ, EACH 03
3. DRB (0-10)MΩ 01
4. CAPACITORS 0.01μf, 0.1μf 01
5. DIODE 1N4007 02
6. DIGITAL TRAINER KIT --- 01
7. SIGNAL GENERATOR (0-3)MHz 01
7. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
8. CONNECTING WIRES --- FEW

THEORY-(ASTABLE MULTIVIBRATOR):-

An op-amp Astable multivibrator is also called as free running

oscillator. The basic principle of generation of square wave is to force an op-amp to
R2
operate in the saturation region (±Vsat). A fraction β = of the output is
R1 R2
fedback to the positive input terminal of op-amp. The charge in the capacitor
increases & decreases upto a threshold value called ±βVsat. This charge in the
capacitor triggers the op-amp to stay either at +Vsat or –Vsat. Asymmetrical square
wave can also be generated with the help of zener diodes. Astable multivibrator do
not require a external trigger pulse for its operation & output toggles from one state to
another and does not contain a stable state. Astable multivibrator are mainly used in
timing applications & waveforms generators.

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 Dept of Electronics & Communication Engg

DESIGN PROCEDURE:-
Design of square wave generator at f0 = 1 KHz.
1. The expression of fo is obtained from the charging period t1 & t2 of capacitor
1
as fo =
2RC ln[1 (2R1 / R2 )]

2. To simplify the above expression, the value of R1 & R2 should be taken as R2

1
= 1.16R1, such that fo simplifies to fo =
2RC

3. Assume the value of R1 = 10KΩ and find R2. R2 = 1.16KΩ (10K)

R2 = 11.6KΩ (DRB)

1
4. Assume the value of C & Determine R from fo =
2RC
Let C = 0.01μf
1 1
R= =
3 6
2 fo C 2 X (1X10 )(0.01X10 )

R = 50KΩ ≡ R = 47KΩ

5. Calculate the threshold point from

R1
lVTl or lβVSATl = lβVSATl where β is the feedback ratio.
R1 R2

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PROCEDURE:
1. Calculate the value of components using the design procedure given.
2. Connect the circuit as per as the circuit diagram.
3. As there is no specific input signal for this circuit switch ON the power
supply.
4. Note down the reading for output square wave (i.e) time & amplitude and
tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.

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CIRCUIT DIAGRAM - (MONOSATBLE):

RF=R3=47K

+15v

2 7
- R3=47K
IC 741
C=0.01uf D1 3 + 4
6
R1=10K
-15V
+
D2 CRO
C1=0.1uf -
R2=10K
Triggering
R4=100Ω
Input
Vin

TABULATION:
Amplitude Time period
S.No Waveforms
(volts) (ms)
1. Input waveform

2. Output waveform

3. Capacitive waveform

MODEL GRAPH:
INPUT

TIME (ms)

AMPLITUDE

OUTPUT

TIME (ms)

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THEORY - (MONOSTABLE MULTIVIBRATOR):-

A multivibrator which has only one stable and the other is quasi-stable
state is called as Monostable multivibrator or one-short multivibrator. This circuit is
useful for generating single output pulse of adjustable time duration in response to a
triggering signal. The width of the output pulse depends only on the external
components connected to the op-amp. Usually a negative trigger pulse is given to
make the output switch to other state. But, it then returns to its stable state after a time
interval determined by circuit components. The pulse width T can be given as T =
0.69RC. For Monostable operation the triggering pulse width Tp should be less then
T, the pulse width of Monostable multivibrator. This circuit is also called as time
delay circuit or gating circuit.

DESIGN PROCEDURE:

1. Assume R1 = R2 = 10KΩ & calculate β from expression

R1 10K = 0.5.
β= =
R1 R2 20K
2. Find the value of R & C from the pulse width time expression.
(1 VD /Vsat )
T = RC ln
1
T = RC ln (1 VD /Vsat )
0.5
T ≡0.69RC.

3. Assume c = 0.01μf and R = 50KΩ ≡47KΩ. Find T where Rf = R3 = R T

= 0.69 (50X103) (0.01X10-6)
T = 0.345ms.
4. Triggering pulse width Tp must be much smaller than T. Tp < T.
5. Assume a HPF in the input session with C1=0.1μf (Assumption) & R4 = 100Ω.

PROCEDURE:
1. Calculate the value of components using the design procedure given.
2. Connect the circuit as per as the circuit diagram.
3. Apply the negative trigger voltage to the non-inverting terminal.
4. Note down the reading for output voltage Vo & ON & OFF time period &
tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.

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SCHMITT TRIGGER:-
CIRCUIT DIAGRAM:-
+15v
ROM=R1//R2 7
-
10KΩ IC 741
+ 6
3 4
+
-15V RL=10K +
Vin ~ R2=100K
CRO
-
R1
10K

TABULATION:

O/P
I/P Voltage I/P Time VUT (UTP) VLT (LTP) O/P Time
Voltage
(Volts) (ms) (Volts) (Volts) (ms)
(ms)

MODEL GRAPH:

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THEORY-(SCHMITT TRIGGER):-

A circuit which converts a irregular shaped waveform to a square wave

or pulse is called a Schmitt trigger or squaring circuit. The input voltage Vin triggers
the output Vo every time it exceeds certain voltage levels called upper threshold
voltage VUT and lower threshold voltage VLT. The threshold voltages are obtained by
using the voltage divider. A comparator with positive feedback is said to exhibit
hysteresis, a dead band condition. The hysteresis voltage is the difference between
VUT & VLT.
There are two types of Schmitt trigger based on where the irregular wave is
given. They are, Inverting & non-inverting Schmitt trigger. Schmitt trigger finds
application in wave shaping circuits. The other name given to Schmitt trigger is
regenerative comparator.

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 Dept of Electronics & Communication Engg

DESIGN PROCEDURE:-
1. Select the desire value of Vut & Vlt with same magnitude & opposite polarity.
Let Vut = 1V & Vlt = -1V.

2. For Op-amp 741C ± Vsat ≡ ±13V to ± 14V. And assume Vref = 0, Since the
another end of R1 is grounded.

3. if Vo = +Vsat the voltage at the positive terminal will be (voltage

from potential divider R1 & R2).
R1
Vut = Vref + (Vsat - Vref )
R1 R2
Therefore Vref = 0.
R1
Vut = (+ Vsat).
R1 R2
R1
4. Similarly Vlt will be Vlt = ( ) – Vsat.
R1 R2
5. Sub Vut & assume R1 or R2 & find the other component value.
R1
1V = (13)
R1 R2
R1 + R2 = 13R1
R2 = 12R1 if R1 = 10K then R2 = 120K ≡100K.

6. Calculate ROM by
R1R2 (10K )(100K )
ROM = R1 // R2 = .
R1 R2 110K
1000K
ROM = ≡ 10KΩ. & select RL = 10KΩ (Assumption)
110K
7. Calculate hystersis voltage
Vhy = Vut – Vlt
R1
= [+Vsat – (-Vsat)]
R1 R2
10K
= [26V] Since Vsat = 13V
110K
= 0.0909 [26V]
Vhy = 2.363V

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 Dept of Electronics & Communication Engg

PROCEDURE:
1. Design the value of circuit components and select VUT & VLT as given in the
design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the input signal to the input terminal of op-amp & set VUT & VLT
values.
4. Note down the readings from the output waveform.
5. Plot the graph & show the relationship between Input sine wave & Output
square wave.

RESULT:
Thus an Astable, Monostable multivibrator and Schmitt trigger are
designed and tested using op-amp IC 741.

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RC PHASE SHIFT OSCILLATOR:-

CIRCUIT DIAGRAM:-

Rf=1MΩ
+15v
R1=33K 2 7
-
IC 741
+ 6
3 4
R1//Rf
33K -15v
+
CRO
C=0.1μf C=0.1μf0 C=0.1μf
-

R=3.3K R=3.3K R=3.3K

TABULATION:.

OBSERVED OUTPUT WAVEFORM

Amplitude Design Frequency
Time period Frequency (Hz)
(volts)
(ms) (Hz)

MODEL GRAPH:

Vout

OUTPUT Time (ms)

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 Dept of Electronics & Communication Engg

RC PHASE SHIFT AND WIEN BRIDGE OSCILLATOR

USING OP-AMP

EXP.NO: 06 DATE:
AIM:
To design RC Phase Shift and Wien Bridge Oscillator using op-amp IC
741 and to test its performance.

APPARATUS REQUIRED:
S.NO COMPONENTS RANGE QUANTITY
1. IC 741 --- 01
1.5KΩ 3.3KΩ, 33KΩ, EACH 03
2. RESISTORS
10 KΩ 22 KΩ, 1MΩ, EACH 01
3. CAPACITORS 0.1μf 03
4. DIGITAL TRAINER KIT --- 01
5. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
6. CONNECTING WIRES --- FEW

THEORY:
RC phase shift oscillator produces 360° of phase shift in two parts. Firstly,
each and every RC pair in the feedback network produces 60° phase shift and totally
there were three pairs, thus producing 180° Phase shift and secondly, the feedback
input is given to the inverting terminal of op-amp to produce another 180° phase shift
and a total phase shift of 360°.
The frequency of oscillation is given by f0 = 1 ; If an inverting
2 6RC
amplifier is used, the gain must be atleast equal to 29 to ensure the oscillations with
constant amplitude that is, AV < 1. Otherwise the oscillation will die out.

DESIGN PROCEDURE:
Design a RC phase shift oscillator to oscillate at 200Hz.
1. Select fo = 200Hz.
2. Assume C = 0.1μf & determine R from fo.
1 1
fo = =R= = 3.3K.
2 6RC

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 Dept of Electronics & Communication Engg
2 6 f oc
3. To prevent the loading of amp because it is necessary that R1>>10R.
Therefore R1=10R=33K.
4. At this frequency the gain must be atleast 29 (i.e)Rf / R1 =29.
Therefore Rf = 29R1.
Rf = 29 (33K) = 957KΩ. Therefore use Rf = 1MΩ.

WIEN BRIDGE OSCILLATOR:-

CIRCUIT DIAGRAM:-

R1=10K Rf=22K
+15v
2 - 7
IC 741
+ 6
3 4
R=1.5K C=0.1uf
-15v +
CRO
R=1.5K -
C=0.1uf

TABULATION:

OBSERVED OUTPUT WAVEFORM

Amplitude Design Frequency
Time period Frequency (Hz)
(volts)
(ms) (Hz)

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MODEL GRAPH:

Vout

OUTPUT Time (ms)

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PROCEDURE- (RC PHASE SHIFT):-

1. Select the given frequency of oscillation f0 = 200Hz.
1
2. Assume either R or C to find out the other using formula f0 = .
2 6RC
3. The gain is selected such that Rf / R1 = 29K. Assume Rf or R1 to find the other.
4. Connect the circuit as per as the circuit diagram.
5. Measure the amplitude frequency of the output signal plot the graph.

THEORY – (WIEN BRIDGE):-

A bridge circuit with two components connected in series and parallel
combination is used to archived the required of phase shift of 00. When the bridge is
balanced the phase shift of 00 is achieved and the feedback signal is connected to the
positive terminal; of Op-amp. So the Op-amp is acting as a non-inverting amplifier
and the feedback network do not provide any phase shift.
The major drawback of wien bridge oscillator is difficulty in balancing
the bridge circuit. This occurs because of drift in component values due to external
1
and internal disturbances. The frequency of oscillation is given as f0 = .
2 RC
DESIGN PROCEDURE:

(i) Select frequency f0 = 1KHz.

1
(ii) Use f0 = , A = 1+(Rf / R1) = 3. To find R & Rf.
2 RC
(iii) Therefore Rf = 2R1 & assume C = 0.1μf & find R from
1
R= = 1.59KΩ.
2 f oC
(iv) Assume R1 = 10K & find Rf from Rf = 2R1
Therefore Rf = 20K ≡22KΩ
PROCEDURE:
1. Select the given frequency of oscillation f0 = 1 KHz.
1
2. Assume either R or C to find out the other using formula . Also
2 RC
determine the value of other components as given in design procedure.
3. Connect the circuit as per as the circuit diagram.
4. Measure the amplitude and frequency of the output signal to plot the graph.
RESULT:
Thus RC Phase Shift and Wien Bridge Oscillator were designed and tested using op-amp IC
741.

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PIN CONFIGURATION OF 555 TIMER IC

Features of 555 IC:-

1. The load can be connected to o/p in two ways i.e. between pin 3 & ground 1 or
between pin 3 & VCC (supply)
2. 555 can be reset by applying negative pulse, otherwise reset can be connected to
+Vcc to avoid false triggering.
3. An external voltage effects threshold and trigger voltages.
4. Timing from micro seconds through hours.
5. Monostable and bistable operation
6. Adjustable duty cycle
7. Output compatible with CMOS, DTL, TTL
8. High current output sink or source 200mA
9. High temperature stability
10. Trigger and reset inputs are logic compatible.
Specifications:-
1. Operating temperature : SE 555-- -55oC to 125oC
NE 555-- 0o to 70oC
2. Supply voltage : +5V to +18V
3. Timing : μSec to Hours
4. Sink current : 200mA
5. Temperature stability : 50 PPM/oC change in temp or 0-005% /oC.
Applications:-
1. Monostable and Astable Multivibrator
2. dc-ac converters
3. Digital logic probes
4. Waveform generators
5. Analog frequency meters
6. Tachometers
7. Temperature measurement and control
8. Infrared transmitters
9. Regulator & Taxi gas alarms etc.

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Block Diagram of IC 555:

Function of Various Pins of 555 IC:

Pin (1) of 555 is the ground terminal; all voltages r measured with respect to this pin.
Pin (2) of 555 is the trigger terminal, If the voltage at this terminal is held greater than
one-third of VCC, the output remains low. A negative going pulse from Vcc to less
than Vec/3 triggers the output to go high. The amplitude of the pulse should be able to
make the comparator (inside the IC) change its state. However the width of the
negative going pulse must not be greater than the width of the expected output pulse.
Pin (3) is the output terminal of IC 555. There are 2 possible output states. In the
low output state, the output resistance appearing at pin (3) is very low (approximately
10 Ω). As a result the output current will goes to zero , if the load is connected from
Pin (3) to ground , sink a current I Sink (depending upon load) if the load is connected
from Pin (3) to ground, and sinks zero current if the load is connected between +VCC
and Pin (3).
Pin (4) is the Reset terminal. When unused it is connected to +Vcc. Whenever the
potential of Pin (4) is drives below 0.4V, output is immediately forced to low state.
The reset terminal enables the timer over-ride command signals at Pin (2) of the IC.
Pin (5) is the Control Voltage terminal. This can be used to alter the reference levels
at which the time comparators change state. A resistor connected from Pin (5) to
ground can do the job. Normally 0.01μF capacitor is connected from Pin (5) to
ground. This capacitor bypasses supply noise and does not allow it affect the
threshold voltages.
Pin (6) is the threshold terminal. In both Astable as well as Monostable modes, a
capacitor is connected from Pin (6) to ground. Pin (6) monitors the voltage across the
capacitor when it charges from the supply and forces the already high O/p to Low
when the capacitor reaches +2/3 VCC.
Pin (7) is the discharge terminal. It presents an almost open circuit when the output is
high and allows the capacitor charge from the supply through an external resistor and
presents an almost short circuit when the output is low.
Pin (8) is the +Vcc terminal. 555 can operate at any supply voltage from +3 to +18V.
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 Dept of Electronics & Communication Engg

CIRCUIT DIAGRAM - (ASTABLE):

6.8K +5V HI

RA

3.3K 7 8 4 3
RB IC 555
5
6 2 1 +
CRO Vo
-
Vc C=0.1μf 0.01uf

TABULATION:

DESIGN VALUE OBSERVED VALUE

Amplitude
Waveforms
(volts) tH tL t F tH tL t F
(ms) (ms) (ms) (Hz) (ms) (ms) (ms) (Hz)

Output
waveform

Capacitor
waveform
(Capacitor
voltage Vc)

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 Dept of Electronics & Communication Engg

ASTABLE & MONOSTABLE MULTIVIBRATOR

USING IC 555 TIMER.

EXP.NO: 07 DATE:
AIM:
To Design and test Astable and Monostable multivibrator using 555 timer IC.

APPARATUS REQUIRED:
S.NO COMPONENTS RANGE QUANTITY
1. IC 555 --- 01

2. RESISTORS 3.3KΩ,6.8KΩ,10KΩ. EACH 01

3. CAPACITORS 0.1μf, 0.01μf. EACH01

4. DIGITAL TRAINER KIT --- 01
5. SIGNAL GENERATOR (0-3)MHz 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW

THEORY:
When the power supply VCC is connected, the external timing capacitor „C”
charges towards VCC with a time constant (RA+RB) C. During this time, pin 3 is high
(≈VCC) as Reset R=0, Set S=1 and this combination makes Q = 0 which has
unclamped the timing capacitor „C‟.
When the capacitor voltage equals 2/3 VCC, the upper comparator triggers the
control flip flop on that Q =1. It makes Q1 ON and capacitor „C‟ starts discharging
towards ground through RB and transistor Q1 with a time constant RBC. Current also
flows into Q1 through RA. Resistors RA and RB must be large enough to limit this
current and prevent damage to the discharge transistor Q1. The minimum value of RA
is approximately equal to VCC/0.2 where 0.2A is the maximum current through the
ON transistor Q1.
During the discharge of the timing capacitor C, as it reaches VCC/3, the lower
comparator is triggered and at this stage S=1, R=0 which turns Q =0. Now Q =0
unclamps the external timing capacitor C. The capacitor C is thus periodically
charged and discharged between 2/3 VCC and 1/3 VCC respectively. The length of
time that the output remains HIGH is the time for the capacitor to charge from 1/3
VCC to 2/3 VCC.
The capacitor voltage for a low pass RC circuit subjected to a step input of VCC
volts is given by VC = VCC [1- exp (-t/RC)]
Total time period T = 0.69 (RA + 2 RB) C
f = 1/T = 1.44/ (RA + 2RB) C

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MODEL GRAPH:

(a) : Square wave output

(b) : Capacitor voltage of Square wave output

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DESIGN PROCEDURE:-
Design of Astable multivibrator of operation frequency = 1 KHz & duty cycle of 30%
using 555 timer IC.
Given Frequency=1000Hz
Duty cycle=30%
D= T low/T high = RB/RA+2RB*100 ------------------------------------- (1)
T high =0.69(RA+RB)C
T low = 0.69 RBC
From equation 1
0.30 T high = T low
0.30 * 0.69(RA+RB)C = 0.69 RBC
0.201(RA+RB)C = 0.69 RBC
0.483 RB-0.207 RA= -----------------------------------------------(2)
0
given f=1khz we know that T=1/f
T=1ms
T= T high + T low
0.69(RA+RB)C +0.69 RBC= 1ms.
0.69(RA+RB) +0.69 RB = 1ms./C
Let C=0.1μF
0.69RA+0.69RB +0.69 RB = 1ms./0.1*10-6
0.69R +1.38R = 10 4 ------------------------------------------------ (3)
A B

Solving equation 2 & 3 we get

RA=6.8K
RB= 2.674K ≡3.3KΩ

Procedure:
1. Calculate the component values using the design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Observe and note down the output waveform.
4. Measure the frequency of oscillations and duty cycle and then compare with
the given values.
5. Plot both the waveforms to the same time scale in a graph.

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MONOSATBLE MULTIVIBRATOR:-

CIRCUIT DIAGRAM:-
HI

+5V
10K

7 8 4 3
IC 555
5
6 2 1 +
Vo 0.1uf CRO
Vc
Trigger -
Input
0.01uf
Vin

TABULATION:

Waveforms Amplitude (volts) Time period (ms)

S
.
N
o

1Input waveform
.

Output
2 waveform
.
Capacitive waveform
(Capacitor
3 voltage Vc)
.

MODEL GRAPH:

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 Dept of Electronics & Communication Engg
THEORY- (MONOSATBLE):-
A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse- generating circuit in which the duration of
the pulse is determined by the RC network connected externally to the 555 timer. In a stable or stand by mode the output of
the circuit is approximately Zero or at logic-low level. When an external trigger pulse is given, the output is forced to go
high ( VCC). The time for which the output remains high is determined by the external RC network connected to the
timer. At the end of the timing interval, the output automatically reverts back to its logic-low stable state. The output stays
low until the trigger pulse is again applied. Then the cycle repeats. The Monostable circuit has only one stable state (output
low), hence the name Monostable. Normally the output of the Monostable Multivibrator is low.

DESIGN PROCEDURE:-
Let, RA = 10K
Out put pulse width tp = 10μs
tp=1.1RAC C= 0.909μF C=0.1μF

PROCEDURE:-
Calculate the value of R & C using design procedure.
Connect the circuit as shown in the circuit diagram.
Apply Negative triggering pulses at pin 2 of frequency 1 KHz.
Observe the output waveform and measure the pulse duration.
Theoretically calculate the pulse duration as Thigh=1.1 RAC

RESULT:

Thus the Astable and Monostable multivibrator is designed and tested using 555 timer IC

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Pin Configuration:

Specifications:
Operating frequency range : 0.001 Hz to 500 KHz
Operating voltage range : ±6 to ±12V
Inputs level required for tracking : 10mV rms minimum to 3v (p-p) max.
Input impedance : 10 KΩ typically
Output sink current : 1mA typically
Drift in VCO center frequency : 300 PPM/oC typically (fout) with temperature
Drif in VCO centre frequency with : 1.5%/V maximum supply voltage
Triangle wave amplitude : typically 2.4 VPP at ± 6V
Square wave amplitude : typically 5.4 VPP at ± 6V
Output source current : 10mA typically
Bandwidth adjustment range : <±1 to >± 60% Center frequency fout = 1.2/4R1C1 Hz
= free running frequency FL = ± 8 fout/V Hz
V = (+V) – (-V)
fc = ± f L 1/2
2 (3.6)x103 xC2
Applications:
Frequency multiplier
Frequency shift keying (FSK) demodulator
FM detector

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 Dept of Electronics & Communication Engg
THEORY:-
PLL IC 565
The Signetics SE/NE 560 series is monolithic phase locked loops. The SE/NE 560, 561, 562, 564, 565, & 567 differ mainly
in operating frequency range, power supply requirements and frequency and bandwidth adjustment ranges. The device is
available as 14 Pin DIP package and as 10-pin metal can package. Phase comparator or phase detector compare the
frequency of input signal fs with frequency of VCO output fo and it generates a signal which is function of difference
between the phase of input signal and phase of feedback signal which is basically a d.c voltage mixed with high frequency
noise. LPF remove high frequency noise voltage. Output is error voltage. If control voltage of VCO is 0, then frequency is
center frequency (fo) and mode is free running mode. Application of control voltage shifts the output frequency of VCO
from fo to f. On application of error voltage, difference between fs & f tends to decrease and VCO is said to be locked.
While in locked condition, the PLL tracks the changes of frequency of input signal.

Diagram Block of IC 565

PROCEDURE:
Determine the component values using the design procedure given here.
Connect the components as shown in the circuit diagram.
Note down the readings of output waveform with respect to input signal.

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CIRCUIT DIAGRAM:

NE 565 PLL connection diagram

DESIGN PROCEDURE:-
If C= 0.01μF and the frequency of input trigger signal is 2KHz, output pulse width of 555 in Monostable mode is given by
1.1RAC = 1.2T =1.2/f
RA= 1.2/(1.1Cf)=54.5KΩ
fIN=fOUT/N Under locked conditions,
fOUT = NfIN = 2fIN = 4KHz

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 Dept of Electronics & Communication Engg

PLL CHARACTERISTICS AND FREQUENCY

MULTIPLIER USING PLL

EXP.NO: 08 DATE:
AIM:
To design & test the characteristics of PLL and to construct and test frequency multiplier using PLL
IC565.

APPARATUS REQUIRED:
S COMPONENT VALUE QUANTITY
.
N
O
1 IC 565 --- 01
2 IC 555 --- 01
12KΩ, 54.5 KΩ,
3 RESISTORS 6.8K Each one

0.01μF 4
CAPACITORS
4
0.1 μf, 10μf, 1 μf EACH 01

5 DIGITAL TRAINER KIT --- 01

REGULATED
6 POWER SUPPLY (0 -30V), 1A 1
CATHODE
7 RAY OSCILLOSCOPE (0 – 30MHz) 1
8 CONNECTING WIRES --- FEW

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PLL as Frequency Multiplier

: Input
: PLL output under locked conditions without 555
: Output at pin4 of 565 with 555 connected in the feedback

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Theory The frequency divider is inserted between the VCO and the phase
comparator of PLL. Since the output of the divider is locked to the input frequency fIN, the VCO is actually running at a
multiple of the input frequency .The desired amount of multiplication can be obtained by selecting a proper
divide– by – N network ,where N is an integer. To obtain the output frequency fOUT=2fIN, N = 2 is chosen. One
must determine the input frequency range and then adjust the free running frequency f OUT of the VCO by means
of R1 and C1 so that the output frequency of the divider is midway within the predetermined input frequency
range. The output of the VCO now should be 2fIN . The output of the VCO should be adjusted by varying
potentiometer R1. A small capacitor is connected between pin7 and pin8 to eliminate possible oscillations. Also,
capacitor C2 should be large enough to stabilize the VCO frequency.

SAMPLE READINGS:
PARAMETER INPUT OUTPUT

Amplitude (Vp-p)

Frequency (KHz)

PROCEDURE:-
The circuit is connected as per the circuit diagram.
Apply a square wave input to the pin2 of the 565
Observe the output at pin4 of 565 under locked condition.
Give the output of 565 to the pin2 of 555 IC.
Observe the output of 555 at pin3.
Now give the output of 555 as feedback to the pin5 of the 565.
Observe the frequency of output signal fo at pin4 of 565 IC.
Plot the waveforms in graph.

RESULT:
Thus the PLL characteristics are designed and tested and Frequency multiplier using IC 565 is constructed and tested.

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PIN DIAGRAM:

CIRCUIT DIAGRAM - (LM723):

Vin (0-30) V
HI
Vref=5V
HI

12 11 R4=100E
6 10 Vo

R1=1K
IC 723
2
R2=3.3K 5
3 R3=30E

7
13 4

C=220pf

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 Dept of Electronics & Communication Engg

DC POWER SUPPLY USING LM317 AND LM723.

EXP.NO: 09 DATE:

AIM:
To design and test the power supply voltage regulator using LM317 and
LM723

APPARATUS REQUIRED:

COMPONENTS
S RANGE QUANTITY
.
N
O

1 LM317 and LM723 --- EACH 01

.
30Ω, 100Ω, 1KΩ,
2 RESISTORS 3.3KΩ, 220Ω, EACH 01
.
3 DIGITAL TRAINER KIT --- 01
.
4 ANALOG VOLTMETER (0-10)V 01
.
5 DUAL POWER SUPPLY (0-30)V 01
.

THEORY:
A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load current and input voltage
variations. Using IC 723, we can design both low voltage and high voltage regulators with adjustable voltages.
For a low voltage regulator, the output VO can be varied in the range of voltages Vo < Vref, where as for high voltage
regulator, it is VO > Vref. The voltage Vref is generally about 7.5V. Although voltage regulators can be designed using Op-
amps, it is quicker and easier to use IC voltage Regulators.IC 723 is a general purpose regulator and is a 14-pin IC with
internal short circuit current limiting, thermal shutdown, current/voltage boosting etc. Furthermore it is an adjustable
voltage regulator which can be varied over both positive and negative voltage ranges. By simply varying the connections
made externally, we can operate the IC in the required mode of operation. Typical performance parameters are line and
load regulations which determine the precise characteristics of a regulator

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TABULATION:

INPUT VOLTAGE OUTPUT VOLTAGE

S. (Volts) (Volts)
N
O
1.

2.

3.

4.

5.

6.

7.

8.

MODEL GRAPH:

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 Dept of Electronics & Communication Engg

CHARACTERISTICS OF THE LM317HVK:

The LM317HVK will provide a regulated output current of upto 1.5A,Provided that if is not subjected to a power
dissipation of more than about 15W.This means it should be electrically isolated from, and fastened to, a large heat sink
such as the metal chassis of the power supply.The LM317 requires a minimum “dropout” voltage of 3v across its input
and output terminals or it will drop out of regulation. Thus the upper limit of Vo is 3V below the minimum input voltage
from the unregulated supply.It is good practice to connect bypass capacitors .This reduces the ripple voltage from the
rectifier.The LM317HVK protects itself against over heating, too much internal power dissipation and too much current.
When the chip temperature reaches 175 degrees, the 317 shuts down. If the product of output current and input-to-output
voltage exceeds 15 to 20W, or if currents greater than about 1.5A are required the LM317 also shuts down. When the
overload condition is removed the Operation is resumed. All these features are made possible by the remarkable internal
circuitry of LM317.Along with the simple 3 pin fixed regulators; a number of adjustable or programmable devices are
available. Some devices also include features such as programmable current limiting. It is also possible to configure
multiple regulators so that they track or follow each other.

DESIGN PROCEDURE: (IC723)

Given :
Vref =5v Vo=4v
We know that Vo=Vref(R2/(R1+R2)) 4R1+4R2=5R2 R2=4R1
Let R1=1k R2=4K ≡3.3KΩ

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PIN DIAGRAM:

CIRCUIT DIAGRAM - (LM317):

MODEL GRAPH:

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TABULATION:

S.NO INPUT VOLTAGE OUTPUT VOLTAGE

(Volts) (Volts)

PROCEDURE:
Connections are made as per the circuit diagram.
The reference voltage of 5v is set and the input voltage is varied between (0-30) v
The corresponding output is taken using voltmeter.
The readings are tabulated and the graph is plotted.

RESULT:
The 723 & 317 voltage regulators are designed and the regulation of supply voltage was tested.

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PIN DETAILS:

FUNCTION
P
I
N

N
O
.
Inverting
1 input
Non
2 Inverting input
Oscillator
3 output
(+)CL
4 sense
(-)CL
5 sense
RT
6
CT
7
Ground(-ve
8 supply voltage)
Compensation
9
Shutdown
1
0
Emitter-A
1
1
Collector-A
1
2
Collector-B
1
3
Emitter-B
1
4
Vin
1
5
Vref
1
6

TECHNICAL INFROMATION:

DESCRIPTION TEMPERATURE
RANGE
SG3524N(16-pin plastic DIP) 0 C to 70 C
SG3524F(16-pin cerdip) 0 C to 70 C
SG3524D(16-pin SO) 0 C to 70 C

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STUDY OF SMPS

EXP.NO: 10 DATE:
AIM:
To study the control of SMPS

THEORY:
The switching regulator is also called as switched mode regulator. In this case, the pass transistor is used as a controlled
switch and is operated at either cutoff or saturated state. Hence the power transmitted across the pass device is in discrete
pulses rather than as a steady current flow. Greater efficiency is achieved since the pass device is operated as a low
impedance switch. When the pass device is at cutoff, there is no current and dissipated power. Again when the pass device
is in saturation, a negligible voltage drop appears across it and thus dissipates only a small amount of average power,
providing maximum current to the load. The efficiency is switched mode power supply is in the range of 70-90%.
A switching power supply is shown in figure. The bridge rectifier and capacitor filters are connected directly to the ac line
to give unregulated dc input. The reference regulator is a series pass regulator. Its output serves as a power supply voltage
for all other circuits. The transistors Q1, Q2 are alternatively switched „on‟ &; off, these transistors are either fully „on‟
or „cut-off, so they dissipate very little power. These transistors drive the primary of the main transformer. The
secondary is centre tapped and full wave rectification is achieved by diodes D1 and D2. This unidirectional square wave is
next filtered through a two stage LC filter to produce output voltage Vo.
SG 3524:
FUNCTION:

Switched Mode Power Supply Control Circuit

FEATURES:
Complete PWM Power Controlled circuitry.
Single ended or push-pull outputs.
Line and Load regulation of 0.2%.
1% maximum temperature variation.
Total Supply current is less than 10mA Operation beyond 100KHz

RESULT:
Thus the control of SMPS IC SG3524 had been studied.

62
V
E
E
1

0
V
C
C
2

9
V
E
E
2

0
V
C
C
3

1
4
V
E
E
3

0
V
1

7
V
2

1
R
1

3
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
 INTRODUCTION ABOUT CIRCUITS AND SIMULATION LAB

CIRCUITS LAB

BREAD BOARD:
In order to build the circuit, a digital design kit that contains a power supply, switches for input,
light emitting diodes (LEDs), and a breadboard will be used. Make sure to follow your instructor's
safety instructions when assembling, debugging, and observing your circuit. You may also need other
items for your lab such as: logic chips,wire, wire cutters, a transistor, etc. Exhibit 1.2 shows a common
breadboard, while Exhibit 1.3 shows how each set of pins are tied together electronically. Exhibit 1.4
shows a fairly complex circuit built on a breadboard. For these labs, the highest voltage used in your
designs will be five volts or +5V and the lowest will be 0V or ground.

The breadboard

The breadboard is typically a white piece of plastic with lots of tiny little holes in it. You stick
wires and component leads into the holes to make circuits. Some of the holes are already electrically
connected with each other. The holes are 0.1 inch apart, which is the standard spacing for leads on
integrated circuit dual in-line packages. You will verify the breadboard internal connections in this lab.

A few words of caution regarding the use of the breadboard:

➢ Keep the power off when wiring the circuit.

➢ Make sure to keep things neat, as you can tell from Exhibit 1.4, it is easy for designs to get
complex and as a result become difficult to debug.
➢ Do not strip more insulation off of the wires used than is necessary. This can cause wires that
are logically at different levels to accidentally touch each other. This creates a short circuit.
➢ Do not push the wires too far into each hole in the breadboard as this can cause two different
problems.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 ➢ The wire can be pushed so far that only the insulation of the wire comes into contact with the
breadboard, causing an open circuit.
➢ Too much wire is pushed into the hole; it curls under and ends up touching another component
at a different logical level. This causes a short circuit.
➢ Use the longer outer rows for +5V on one side and ground on the other side.
➢ Wire power to the circuit first using a common color (say red) for +5V and another (black) for
ground.
Laboratory Procedures, Measurements and Questions
Record your data and the answers to questions on a separate sheet (or sheets) of paper and hand
it in at recitation section when the lab is due. You will also have to bring your breadboard with
designated circuits on it to your recitation section the week the lab is due.

Procedure 1 Continuity Check (5 points)

Use your multimeter to verify the connections in your breadboard in the first 5 columns and the
top two rows of the breadboard as indicated on the diagram below
Set your multimeter on resistance. To find out if any two holes are connected, measure the
resistance between them with the multimeter.
a. (2 points) Measure and record the resistance between two holes in a row of 5 connected holes.
Measure and record the resistance between two holes at the opposite ends of a long side row (+
or -). Explain the difference (or lack thereof).
b. (2 points) What resistance did you measure between unconnected holes? What did your
multimeter read?
c. (1 point) Does it make a difference which probe goes in which hole?

Some hints on measuring resistance:

Never try to measure resistance in energized circuits (ones with the power on). You won't get an
accurate value and you could damage your multimeter or the circuit. Your multimeter probes probably

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

don't fit into the breadboard holes. Stick the stripped end of a wire into each hole, and touch the other
stripped ends of the wires with the multimeter probes. If you have clips at the end of your multimeter
leads, or you bought those optional alligator clips, you can clip on to the ends of the wires and move the
wires from hole to hole. Resistor leads also work for this purpose, but make sure you are not measuring
the resistor resistance as well as the breadboard resistance.

Because the multimeter uses a low voltage to measure resistance, you can safely use your fingers to
press the wires to the multimeter probes to be sure you have a good contact. If you do, though, you will
put your body in parallel with the resistance you are measuring. This can be important for certain large
values of resistance, those near or greater than your body resistance. It's usually not a problem for
continuity checks.

➢ Switch the multimeter to off or to the voltage setting when you are not actively measuring
resistance. This minimizes battery use in the multimeter and is also a generally saferpractice.

CIRCUIT SIMULATION
A common tool (computer aided design or CAD / electronic design automation or EDA
software) for the electronic circuit designer is circuit simulation software. Although most often called
simply a simulator, it is a software application that typically may include many functions beyond
electrical circuit simulation, including schematic capture, printed circuit board layout, and bill of
materials generation.

Most circuit simulator software grew out of a public domain program called SPICE (Simulation
Program with Integrated Circuit Emphasis) developed at UC Berkeley[1] in the 1970s. The original
SPICE program operated in a batch mode and was text based. That is, the user created a text file which
described the circuit using a special circuit netlist syntax. This file also included simulation directives
which told the software what type of simulation is to be performed. The SPICE program read the input
file, performed the appropriate analyses, and produced a text output file that contained the results.

Over time EDA companies began adding graphical “back-ends” that could produce better
looking graphs and plots of the simulation results. A next obvious step was to add a graphical interface
for building the circuit (GUI). This had the dual benefit of both describing the circuit for the simulation
engine (generating the SPICE net list) and allowing for the production of publication quality schematic
diagrams. Some of the early popular graphical versions included PSpice and Electronics Workbench
(EW being the precursor to Multisim).

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 More recent features include instrumentation simulation. That is, simulations of real world
commercial measurement devices may be used as part of the circuit simulation. In this way, a sort of
“virtual lab bench” may be created. Some packages, such as Fritzing[2], also include physical imagery
of devices and proto-boards. With this feature, the circuit being designed will look very similar to the
actual circuit sitting on your lab bench. That is, if a transistor is used in the simulation, it will look like
a real transistor instead of the standard schematic symbol. While this may initially appear to be very
useful, especially for beginners, in practical terms it sometimes slows down the design process by
making the schematic less clear and more cluttered to the user.

PROCEED AS FOLLOWS TO OBTAIN THE ANSWER USING PSPICE.

1. Run the CAPTURE program.

2. Select File/New/Project from the File menu.
3. On the New Project window select Analog or Mixed A/D, and give a name to your project then click
OK.
4. The Create PSpice Project window will pop up, select Create a blank project, and then click OK.
5. Now you will be in the schematic environment where you are to build your circuit.
6. Select Place/Part from the Place menu.
7. Click ANALOG from the box called Libraries:, then look for the part called R. You can do it
either by scrolling down on the Part List: box or by typing R on the Part box. Then click OK.
8.Use the mouse to place the resistor where you want and then click to leave the resistor there.
You can continue placing as many resistors as you need and once you have finished placing
the resistors right-click your mouse and select end mode.
9. To rotate the components there are two options:
➢ Rotate a component once it is placed: Select the component by clicking on it then Ctrl-R
➢ Rotate the component before it is placed: Just Ctrl-R.
10. Select Place/Part from the Place menu.
11. Click SOURCE from the box called Libraries:, then look for the part called VDC. You can do it
either by scrolling down on the Part List: box or by typing VDC on the Part box, and then click OK.
Place the Source.
12. Repeat steps 10 - 12 to get and place a current source named IDC.
13. Select Place/Wire and start wiring the circuit. To start a wire click on the component terminal

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 where you want it to begin, and then click on the component terminal where you want it to
finish. You can continue placing wires until all components are wired. Then right-click and
select end wire.
14. Select Place/Ground from the Place menu, click on GND/CAPSYM. Now you will see the
ground symbol. Type 0 on the Name: box and then click OK. Then place the ground. Wire it
if necessary.
16. Now change the component values to the required ones. To do this you just need to double-
click on the parameter you want to change. A window will pop up where you will be able to
set a new value for that parameter.
17. Once you have finished building your circuit, you can move on to the next step – prepare it
for simulation.
18. Select PSpice/New Simulation Profile and type a name, this can be the same name as your
project, and click Create.
19. The Simulations Settings window will now appear. You can set up the type of analysis you
want PSpice to perform. In this case it will be Bias Point. Click Apply then OK.
20. Now you are ready to simulate the circuit. Select Pspice /Run and wait until the Pspice
finishes. Go back to Capture and see the voltages and currents on all the nodes.
21. If you are not seeing any readout of the voltages and currents then select PSpice/Bias
Point/Enable Bias Voltage Display and PSpice/Bias Point/Enable Bias Current Display. Make
sure that PSpice/ Bias Point/Enable is checked.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 INTRODUCTION ABOUT DIGITAL LABORATORY

In today‟s modern world, the usage of digital technology is mandatory and unavoidable,
applications such as internet, wireless broadcasting systems, Smart Television, computers, industry
automation systems, music players etc., are really very reliable and accurate in quality and
performance.

In this Lab, we learn the fundamental aspects of digital mathematical and logical operations by
hardware and software (HDL simulator) methodologies.

Circuit that takes the logical decision and the process are called logic gates. Each gate has one
or more input and only one output. OR, AND and NOT are basic gates. NAND and NOR are known as
universal gates.
A half adder has two inputs for the two bits to be added and two outputs one from the sum „ S‟
and other from the carry „ c‟ into the higher adder position. Above circuit is called as a carry signal
from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate.
A conversion circuit must be inserted between the two systems if each uses different codes for
same information. Thus, code converter is a circuit that makes the two systems compatible even though
each uses different binary code.

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can
be constructed with full adders connected in cascade, with the output carry from each full adder
connected to the input carry of next full adder in chain.

The comparison of two numbers is an operator that determines one number is greater than, less
than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares
two numbers A and B and determine their relative magnitude.

A parity bit is used for detecting errors during transmission of binary information. A parity bit is
an extra bit included with a binary message to make the number is either even or odd. The message
including the parity bit is transmitted and then checked at the receiver ends for errors.
An error is detected if the checked parity bit doesn‟t correspond to the one transmitted. The
circuit that generates the parity bit in the transmitter is called a „parity generator‟ and the circuit that
checks the parity in the receiver is called a „parity checker‟.
Multiplexer means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to a single output line.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 The function of Demultiplexer is in contrast to multiplexer function. It takes information from
one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also
known as a data distributor. Decoder can also be used as demultiplexer.
An encoder is a digital circuit that perform inverse operation of a decoder. An encoder has 2n
input lines and n output lines. In encoder the output lines generates the binary code corresponding to
the input value.

A decoder is a multiple input multiple output logic circuits which converts coded input into
coded output where input and output codes are different. The input code generally has fewer bits than
the output code.

A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. A specified sequence of states appears as
counter output. This is the main difference between a register and a counter. There are two types of
counter, synchronous and asynchronous. A register is capable of shifting its binary information in one
or both directions is known as shift register. The logical configuration of shift register consist of a D-
Flip flop cascaded with output of one flip flop connected to input of next flip flop.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EX. NO: 1
DATE:
STUDY OF LOGIC GATES

AIM: -

To study about logic gates and verify their truth tables.

APPARATUS REQUIRED: -

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8 Bread Board 1

THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each gate has one
or more input and only one output.
OR, AND and NOT are basic gates. NAND and NOR are known as universal gates. Basic gates
form these gates.
AND GATE

The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is low.

OR GATE
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT GATE

The NOT gate is called an inverter. The output is high when the input is low. The output is
low when the input is high.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

X- OR GATE

The output is high when any one of the inputs is high. The output is low when both the inputs
are low and both the inputs are high.
NAND GATE

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR GATE

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.

PROCEDURE
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 NOT GATE :
SYMBOL: PIN DIAGRAM:

X-OR GATE :
SYMBOL : PIN DIAGRAM :

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

2- INPUT NAND GATE

SYMBOL PIN DIAGRAM

3- INPUT NAND GATE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

NOR GATE

RESULT:

Thus the logic gates were studied and their truth tables have been verified.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EX. NO:2
DATE: DESIGN AND IMPLEMENTATION OF CODE CONVERTORS

AIM:

To design and implement 4-bit

(i) Binary to gray code converter

(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. X-OR GATE IC 7486 1

2. AND GATE IC 7408 1

3. OR GATE IC 7432 1

4. NOT GATE IC 7404 1

5. IC TRAINER KIT - 1

6. PATCH CORDS - 35

THEORY:

The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes
the two systems compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses four bits to
represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted code.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 The input variable are designated as B3, B2, B1, B0 and the output variables are designated as
C3, C2, C1, Co. from the truth table, combinational circuit is designed. The Boolean functions are
obtained from K-Map for each output variable.
BINARY TO EXCESS-3 CODE CONVERTOR:

A code converter is a circuit that makes the two systems compatible even though each uses a
different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit
combination of elements as specified by code and the output lines generate the corresponding bit
combination of code. Each one of the four maps represents one of the four outputs of the circuit as a
function of the four input variables.
PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR

K-Map for G3:

G3 = B3

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K-Map for G2:

K-Map for G1:

K-Map for G0:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

TRUTH TABLE:

Binary input Gray code output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

K-Map for B3:

B3 = G3

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K-Map for B2:

K-Map for B1:

K-Map for B0:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

TRUTH TABLE:

Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR

K-Map for E3:

E3 = B3 + B2 (B0 + B1)

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K-Map for E2:

K-Map for E1:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

K-Map for E0:

TRUTH TABLE:

BCD input Excess – 3 output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A = X1 X2 + X3 X4 X1

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

K-Map for B:

K-Map for C:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

K-Map for D:

TRUTH TABLE:
Excess – 3 Input BCD Output
B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

RESULT: -

Thus the code converter circuits were designed and their logic verified.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
EX NO:3
DATE:

DESIGN OF 4-BIT ADDER AND SUBTRACTOR

AIM:
To design and implement the 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can
be constructed with full adders connected in cascade, with the output carry from each full adder
connected to the input carry of next full adder in chain. The augends bits of „A‟ and the addend bits of
„B‟ are designated by subscript numbers from right to left, with subscript 0 denoting the least
significant bits. The carries are connected in chain through the full adder. The input carry to the adder is
C0 and it ripples through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data
input „B‟ and the corresponding input of full adder. The input carry C0 must be equal to 1 when
performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one common
binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When
M=1, it becomes subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an input carry
from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than
19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in BCD and
should appear in the form listed in the columns.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits,
together with the input carry, are first added in the top 4 bit adder to produce the binary sum.
PROCEDURE:

Connections were given as per circuit diagram.

(i) Logical inputs were given as per truth table

(ii) Observe the logical output and verify with the truth tables.

LOGIC DIAGRAM:

4- BIT BINARY ADDER

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LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PIN DIAGRAM FOR IC 7483:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LOGIC DIAGRAM:
4- BIT BINARY ADDER/SUBTRACTOR

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

LOGIC DIAGRAM:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

BCD ADDER

K MAP

Y = S4 (S3 + S2
TRUTH TABLE:

BCD SUM CARR

Y
S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

RESULT: -

Thus the 4 bit adder and subtractor circuits were designed and their logic was verified.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EX NO: 4

DATE:

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER

AIM:
To design and implement multiplexer and demultiplexer using logic gates and study of IC
74150 and IC 74154.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2n input line and n selection lines whose bit
combination determine which input is selected.
The function of Demultiplexer is in contrast to multiplexer function. It takes information from
one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also
known as a data distributor. Decoder can also be used as Demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select
lines enable only one gate at a time and the data on the data input line will pass through the selected
gate to the associated data output line.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PIN DIAGRAM FOR IC 74150:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CIRCUIT DIAGRAM FOR 4X1 MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT

0 0 X → D0 = X S1’ S0’

0 1 X → D1 = X S1’ S0

1 0 X → D2 = X S1 S0’

1 1 X → D3 = X S1 S0

D0 = X S1’ S0’

D1 = X S1’ S0

D2 = X S1 S0’

D3 = X S1 S0

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE:

INPUT OUTPUT

S1 S0 I/P D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PIN DIAGRAM FOR IC 74154:

RESULT: -

Thus the Multiplexer/Demultiplexer circuits were designed and their logic was verified.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EX NO:5

DATE:

DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

AIM:
To design and implement encoder and decoder using logic gates , study of IC 7445 and IC
74147.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27

THEORY:

ENCODER:
An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2n
input lines and n output lines. In encoder the output lines generates the binary code corresponding to
the input value. In octal to binary encoder it has eight inputs, one for each octal digit and three output
that generate the corresponding binary code. In encoder it is assumed that only one input has a value of
one at any given time otherwise the circuit is meaningless. It has an ambiguila that when all inputs are
zero the outputs are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input into
coded output where input and output codes are different. The input code generally has fewer bits than
the output code. Each input code word produces a different output code word i.e there is one to one
mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded
information is present as n input producing 2n possible outputs. 2n output values are from 0 through out
2n – 1.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table

PIN DIAGRAM FOR IC 7445:

BCD TO DECIMAL DECODER:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PIN DIAGRAM FOR IC 74147:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE:

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

RESULT: -

Thus the encoder/decoder circuits were designed and their logic was verified

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EX NO:6

DATE:

CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER AND MOD 10/MOD

12 RIPPLE COUNTER

AIM:
To design and verify 4 bit ripple counter and Mod 10/ Mod 12 ripple counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. A specified sequence of states appears as
counter output. This is the main difference between a register and a counter. There are two types of
counter, synchronous and asynchronous. In synchronous common clock is given to all flip flop and in
asynchronous first flip flop is clocked by external pulse and then each successive flip flop is clocked by
Q or Q output of previous stage. A soon the clock of second stage is triggered by output of first stage.
Because of inherent propagation delay time all flip flops are not activated at same time which results in
asynchronous operation.
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

TRUTH TABLE:

CLK QD QC QB QA

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:

CLK QD QC QB QA

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 0 0 0

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

TRUTH TABLE:

CLK QD QC QB QA
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0

RESULT: -

Thus the 4bit ripple counter and Mod counter circuits were designed and their logic was
verified.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EX NO:7

DATE:

DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER

AIM:
To design and implement the 3 bit synchronous up/down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter is
also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down
signal. When this signal is high counter goes through up sequence and when up/down signal is low
counter follows reverse sequence.
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

STATE DIAGRAM:

CHARACTERISTICS TABLE:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

TRUTH TABLE:

Input Present State Next State A B C

Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC

0 0 0 0 1 1 1 1 X 1 X 1 X

0 1 1 1 1 1 0 X 0 X 0 X 1

0 1 1 0 1 0 1 X 0 X 1 1 X

0 1 0 1 1 0 0 X 0 0 X X 1

0 1 0 0 0 1 1 X 1 1 X 1 X

0 0 1 1 0 1 0 0 X X 0 X 1

0 0 1 0 0 0 1 0 X X 1 1 X

0 0 0 1 0 0 0 0 X 0 X X 1

1 0 0 0 0 0 1 0 X 0 X 1 X

1 0 0 1 0 1 0 0 X 1 X X 1

1 0 1 0 0 1 1 0 X X 0 1 X

1 0 1 1 1 0 0 1 X X 1 X 1

1 1 0 0 1 0 1 X 0 0 X 1 X

1 1 0 1 1 1 0 X 0 1 X X 1

1 1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 1 0 0 0 X 1 X 1 X 1

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

K MAP

K MAP

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LOGIC DIAGRAM:

RESULT: -

Thus the 3 bit synchronous up/down counter circuits were designed and their logic was
verified.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EX. NO:8

DATE:

DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

AIM:

To design and implement

(i) Serial in serial out

(ii) Serial in parallel out
(iii) Paral lel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2

2. OR GATE IC 7432 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 35

THEORY:

A register is capable of shifting its binary information in one or both directions is known as shift
register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of one
flip flop connected to input of next flip flop. All flip flops receive common clock pulses which causes
the shift in the output of the flip flop. The simplest possible shift register is one that uses only flip flop.
The output of a given flip flop is connected to the input of next flip flop of the register. Each clock
pulse shifts the content of register one bit position to right.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PIN DIAGRAM:

LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK Serial in Serial out

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EC8361 ANALOG AND DIGITAL CIRCUITS LAB

LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:

TRUTH TABLE (SERIAL IN PARALLEL OUT):

OUTPUT

CLK DATA QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 0

4 1 1 0 0 1

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EC8361 ANALOG AND DIGITAL CIRCUITS LAB

LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT

TRUTH TABLE (PARALLEL IN SERIAL OUT):

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EC8361 ANALOG AND DIGITAL CIRCUITS LAB

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

DATA INPUT OUTPU

T
CLK DA DB DC DD QA QB QC Q
D
1 1 0 0 1 1 0 0 1
2 0 1 0 1 0 1 0 1
3 0 0 0 1 0 0 0 1
4 1 1 1 1 1 1 1 1
5 0 0 0 0 0 0 0 0

RESULT: -

Thus the shift register circuits were designed and their logic was verified

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING