Bari

May 2005

Phase Locked Loop-Circuits &

Applications:
Theory, Analysis and Design
Pasquale Lamanna Texas Instruments France
ABB & RF_IC Designer e-mail:p-lamanna@ti.com

4/29/2005 1
 • Brief History
Talk Outline
• PLLs Classification
• Basic Concepts
• Phase-Locked Loops
• Charge-pump PLL
• Loop Components
• What is Frequency Synthesizers ?
• Phase Noise Analysis and its Effects on PLL
• Basic PLL-Based Frequency Synthesizer
• Integer-N Frequency Synthesizer
• Fractional-N Frequency Synthesizer
• Direct Digital Synthesizer
• All Digital PLLs & Software PLLs Overview
4/29/2005 2
 PLLs’ History
• A first description of what is known as PLL was presented by H. de Bellescise in 1932
and coincides with the invention of “coherent communication”
• First PLL IC arrived around 1965. This created an explosion in the use of PLLs.
• The first digital PLL appeared around 1970. This was a classical digital PLL.
• Few years later the firs all digital PLL appeared.
• first Software PLL in the late year 80s
• PLLs Today:
- In every cell phone, television, radio, pager, computers…
- The most Prolific feedback system built by engineers.
§ To generate an output signal whose output frequency is programmable and rationale
multiple of a fixed input frequency
§ To perform frequency modulation and demodulation.
§ To generate the carrier from an input signal in which the carrier has been suppressed.
§ Clock Recovery Circuits.
§ Generation of Clock Signal.
§ Frequency Synthesizer

4/29/2005 3
 Classification of PLL Types
Phase Controlled
PLL Type Loop Filter
Detector oscillator
Analog
APLL Multiplier
RC Voltage

Digital
DPLL RC Voltage
Detector

Digital Digitally
ADPLL Detector
Digital
Controlled
Software
SPLL Multiplier
Software Software

4/29/2005 4
 Analog PLL
•PLL syncronises the phase generated by an oscillator with the phase
of a reference signal by means of the phase difference of the two signals.
φ in φ error V ctrl
VCO

φ out

• Operates on excess phase of Vi(t) and Vo(t).

• Negative feedback system with PD as an error amplifier.
• “Locked” when phase difference between input and output
is constant with time:
φin − φout = cons tan t

d(φin − φout )
4/29/2005 = 0 ⇒ fin = f out in average. 5
dt
 DIGITAL PLL
qDigital PFD Replace Analog Multiplier
qPull in Range is limited only by VCO Tunability Range

Fref UP
PFD Charge Loop Filter VCO
Fout Pump
DN

qPFD +CP introduce another pole @0 giving a Type II PLL

in this way it is possible to decouple BW and gain!
q ! φe=0 for an input step frequency!
4/29/2005 6
 Region of Operations
There are four basic regions of operations describing PLL in dynamic
and static states.
• PLL is in dynamic state when the output is not locked or syncronised in
phase with the reference.
• PLL is in a static state when output is locked with reference.

hold range

pull in range

lock in range

4/29/2005 7
 PLL REGIONS OF OPERATIONS
Hold range: Describes PLL in a static or locked state, it is the frq range in which a PLL
can statically mantain phase tracking ( PLL is initially locked with ref signal, if the ref
signal’s frq is slowly reduced or increased too much PLL will lose lock at the edge of the
hold range.
• PLL is conditionally stable only within the hold range.

Pull in range :Describes the PLL in a dynamic state ( aquisition mode ) it is the range
within which a pll will always become locked through the aquisition process.
PLL is initially unlocked , it will aquire lock if a ref frq wiithin the pull in range is applied. If
the ref frq is outside the pull in range the PLL will not be able to lock onto the ref signal.

Lock range: Is a subset of lock in range, it is the frq range in which a PLL lock within a
single-bit mode between the ref frq and output frq.
PLL is initially unlocked

Pull out range: Describes the PLL in a static state, it is the dynamic limit for stable
operation; it is the value for a frq step applied to the ref frq that causes the PLL to unlock(
PLL is initially locke dwith the ref signal, if a ref frq that is less than the pull out range is
applied to the ref signal the PLL will remain in lock; However , if the frq step excedees the
pull out , the PLL will not be able to track the output signal and will fell out the lock.
PLL may aquire lock again, but it may be a slow pull in process. 8
4/29/2005
 Phase Detector

q Compare the phase difference between the input

reference signal and the oscillator output signal and its
output is a function of the phase difference between the
two input signals.

Ø Is a multiplier in Analog PLL

Ø Is formed by logic gates in digital PLL

4/29/2005 9
 Analog Phase detector
x1 ( t ) = A1 cos ω1t , x 2 ( t ) = A 2 cos( ω2 t + ∆φ)
Analog Multiplier
y ( t ) = αA1 cos ω1t × A 2 cos( ω2 t + ∆φ) x1(t) y(t)

α A1A 2
= cos[( ω1 + ω2 ) t + ∆φ] x2(t)
2
α A1A 2 y
+ cos[( ω1 ω2 ) t + ∆φ]
2
Lock
π π ∆φ
-
αA1A 2 2 2
y( t ) = cos ∆φ
2
4/29/2005 10
 Digital Phase Detector

• Purpose: To produce a signal current or voltage, proportional to

the difference in phase or frequency between two input signals.

Phase Vout(t)
Detector

∆φ
Vout

Vout = KD ∆φ KD
∆φ
• Example

4/29/2005 11
 Phase Frequency Detector

S1 R S2 R S3
R Up Up=0 Up=0 Up=1
PFD V R
V Dn Dn=1 Dn=0 Dn=0

Symbol V
V
State Diagram

R R R R

V V V V

Up Up
Up Up
Dn Dn Dn Dn
fR > fV fR < fV V lagging R R lagging V

4/29/2005 12
 Phase Frequency Detector
1 Vdd
-2π
Up
2π radians
D Q
τd
R CK R

Gain = 1 / 2 π DL
V CK R
Kd
D Q Dn

radians • Locks for 0 degree phase error

• Edge triggered -- duty cycle
Dead zone at zero phase error independent

R
θd
V
τd
Up
4/29/2005 13
Dn
 PFD with Charge Pump
• A switched current source is a good choice for a PFD output stage:
- highly integrated
- high impedance insures loop filter pole at zero
- low noise because of tri-state operation
- fast

• Configure the charge pump with equal up and down currents.

The value of the current is used to calculate PFD gain : Id / 2π
Phase error :
Id θe = θr - θv
Up “ On” time of either Up or Dn
R S1 > tp = |θe|/ωr for each period of
PFD VCTL 2π/ωr of the reference signal.
V S2
Dn C Average error current over a cycle
Id t p θe ωr I
iD = = ⋅ Id = d θe
2π ωr 2π 2π
ωr
i (s ) I
KD = D = d
θe (s ) 2π
4/29/2005 14
PFD gain :
 PFD with Charge Pump
When in lock ΦE = 0 and When in lock no current is injected (ideally)

Id
Up Y
R S1
PFD VCTL
V S2
Dn C
Id
UP

Down

4/29/2005 15
 Charge Pump Design
VDD
VDD VDD

VDD/2
Ipump
up up on off
GND
up up
Vtune Vpol
VDD/2 GND
Vtune
VDD/2 Vtune
VDD
C2 R1
G(s)
down down C1
down down on off GND

VDD/2

Basic structure: Between two

fast current switching phase comparisons GND

Complete Differential
Charge Pump
4/29/2005 16
Circuit
 Type I Second-Order PLL
R
1
F(s ) = , τ = RC
C 1 + sτ

ω2n K DK V 1 1
B(s ) = , ωn = and ζ =
s 2 + 2ζωn s + ω2n τ 2 τK D K V

• Limitations of simple type-I second-order PLL :

- Coupling between ζ, ωn, and K=KDKV

> if K ⇑ to reduce static phase error, then ζ ⇓
> if ωLPF = 1/τ ⇓ to reduce high-frequency output of PD, then ζ ⇓

- Coupling between loop bandwidth, suppression of high-frequency output

of PD, and capture range.

- Finite DC loop gain causes large static phase error.

4/29/2005 17
 Type II Second-Order PLL I
1 + sτz
Iqp ZLPF (s ) =
( )(
s 2 Cz + Cp 1 + sτp )
CZ τz = R z C z
CP
−1
RZ  1 1 
τp = R z  +
 Cz Cp 
 

• Defining with b the ratio of two capacitors b = C Z CP the loop filter impedance

can be written as
 b  1 + sτ z
ZLPF (s ) =  
 b + 1  sC 1 + sτz 
z 
 1+ b 
4/29/2005 18
 Type II Second-Order PLL II
q open loop transfer function is
Iqp K VCO  b  1 + sτ z
G 0 (s ) =  
2πN  b + 1  2  sτ 
s C z 1 + z 
 1+ b 
q The cross-over frequency equals approximately
Iqp K VCO R z Cz Iqp K VCO R z
ωc = ≈
2πN Cz + Cp 2πN

q The phase margin of the loop is:

τ ω 
PM = arctan (τz ωc ) − arctan g z c 
 b +1 

4/29/2005 19
 Type II Second-Order PLL II
q By differentiating the PM equation respect to ωc it the maximum
phase margin is achieved at
b +1
ωc =
τz
q and the maximum phase margins is:
 b +1
PM = arctan b + 1 − arctan g 
 b +1 
q Notice that the maximum phase margin is only a function of b
parameter.
q To complete loop analysis forcing ωc to be the crossover frequency
of the loop and getting it in (2) results in:
b +1 Iqp K VCO 1 b
=
τ2z 2πN C z b + 1
4/29/2005 20
 Type II Second-Order PLL II
Ø From previous equations a rigorous algorithmic can be developed
to determine the loop filter parameters for an optimal open loop
gain characteristics.

q Algorithm: [1]

I. Define KVCO gain

II. Choose a desired phase margin and find b from PM equation
III. Choose the loop bandwidth and find τz
IV. Select Cz and Iqp such that they satisfied the last equation
V. Calculate the noise contribution of R, if the calculated noise is
negligible the design is complete otherwise go back to step four
and increase Cz
4/29/2005 21
 Filter G(s)
Im(s)
|Gloop|dB

-40dB/dec
C ωο Re(s)
unstabile
ω
Zero for phase margin
Im(s)
|Gloop|dB
C
-40dB/dec
ωο = ωz
R
ω
Re(s)

G ( s) =
(1 + sC1R)
sCP ⋅ s (1 + sCΣ )
CP = (C1 + C2 )
Im(s)
C1 |Gloop|dB

CΣ = C1C2 ( C1 + C2 )
C2
-40dB/dec
ωο Re(s)
R
ω

4/29/2005 22
 Exercise

4/29/2005 23
 Voltage Control Oscillator

VOUT has an angular frq that is controllable by output voltage of the loop filter Vc.

Vc k VCO ωOUT
s
ωOUT ( t ) = ω0 + ∆ωOUT ( t ) = ω0 + k VCO Vc ( t )
-θ0 is the center frq of VCO (i.e. the out frq when Vc=0)
-kVCOis the voltage controlled oscillator conversion gain.

t
y ( t ) = A C cos[ ωFR t + K VCO ∫ v cont ( t )dt ]
∞
φOUT = ∫ ∆ωOUT ( t )dt = k VCO ∫ Vcdt
•Output phase is equal to the integral on the frq variation ∆θ(t).
k VCO
φOUT (s) = Vc (s)
4/29/2005
s 24
 A Walk Around the Loop
Vi(t)
PD LPF VCO Vo(t)

Vi(t)

Vo(t)

PD
output

LPF
output
t

4/29/2005 25
 Phase Locked Loop
• The open loop transfer function of any PLL is:
1 K VCO
φe G (s ) = K CP F(s )
N s
φref
Phase Charge Low Pass Filter VCO φout
frequency Pump KVCO
F(s)
Detector KCP

1
N
φo (s ) K CPK VCOF(s )
H PLL (s ) = = - - - Low pass characteristics
φi (s ) s + K VCOK CPF(s )
φe (s ) s
He (s ) = = - - - High pass characteristics
φi (s ) s + K VCOK CPF(s )
4/29/2005 26
 Phase Error Function
Φe ( s ) φ e ( t = ∞) = lim sφ e ( s )
He ( s ) = Φin ( s ) s→0

2ς
s 2 + 2ς ωn s = Δω
He ( s ) = 1 H( s ) = 2 ωn
s + 2ς ωn s + ωn2
Δω
=
Φout ( s ) = H( s )Φin ( s ) K
ωn2 Δω ωin ∆ω
= 2
s + 2ς ωn s + ωn2 s 2
Φe ( s ) = He ( s )Φin ( s ) ωout ∆ω
s 2 + 2ς ωn s Δ ω
= 2 Δω
s + 2ς ωn s + ωn2 s 2 Φe
K
4/29/2005 27
t
 Voltage-Controlled Oscillator

ωout = ω FR + K vVcont
Vcont ωout
ωout φc (t) = ∫ (ω FR + K vVcont ) dt

ωFR Kv
( )
Vout(t) = A cos ω R F t + K v ∫t− ∞Vcontdt

Vcont
Excess phase :
Example:
φexcess = K v ∫Vcontdt
Vout
Vcont φ (s) Kv
=
GND Vcont (s) s

• VCO is an ideal integrator.

• Output phase depends on the history of control voltage.
4/29/2005 28
 VCO Model ( Feedback Model )

Basic Idea :
Vi G(A,ω) Vo Loop gain should be 1 at a
steady state to achieve oscillation.

H(ω) - Start-up
H(ω) G(0,ω) >1
Arg (H(ω) G(0,ω) )=2nπ
Vo G ( A ,ω ) - Steady State
B ( A ,ω ) = =
Vi 1 − H (ω )G ( A ,ω ) H(ω) G(A,ω) =1
Ang (H(ω) G(A,ω) )=2nπ

Vo has finite value even though Vi=0. This requires loop gain
H(ω) G(A,ω) =1 to have a pair of nonzero poles in right half plane ,
which gives

Vo (t) = Voe αt cos( βt)

4/29/2005 29
 VCO Model ( Negative Resistance Model )

i = f (V)
Active Frequency Basic Idea :
V Determining
Circuit Circuit Losses in the frequency determining
circuit are compensated by a negative
Za (A,ω) Zf (ω)
resistance seen into the active circuit.
i = f(V) Start-up conditions:

Xa(ωo) + Xf(ωo) = 0
C L G V - Ga VCNR
Ra(ωo) + Rf (ωo ) < 0

Parallel Resonator At steady state:

i Xa(A, ωo) + Xf(ωo) = 0

Ra(R, ωo) + Rf (ωo ) = 0

V
4/29/2005 30
 Frequency Step at Input

Vi(t)
PD LPF VCO Vo(t)

ωo ωo+∆ω

Vi(t)

Vo(t)

PD
output
KD∆φ
LPF
output
t
to

4/29/2005
• PLL system has memory. 31
• In lock, input and output frequencies are equal.
 Charge Pump PLL

Ip
Up
R S1 Vcont
PFD VCO
V S2
Dn C
Ip

Ip 1
⋅ KV Ip 1
B(s ) = 2 π C s = ±j ⋅ KV
Ip 1 2π C
s2 + ⋅ K V
2π C

• Oscillation!!
• Need loop-stabilizing zero to keep the PLL stable.

4/29/2005 32
 Charge Pump PLL with Zero

Id C1 Filter the high

Up frequency ripple
R S1 Vcont
PFD VCO
V S2
Dn C
C1
Id R

Ip  1 + sCR 
Vcont (S) =  θe (s ) IP
2π  sC 
Ip
(1 + sCR )K V Vcont
B(s ) = 2 πC Ip/C
Ip Ip
s2 + K V Rs + KV
2π 2πC
I pR
Ip R I pC
ωn = KV , ζ= KV
4/29/2005 2πC 2 2π Modulate VCO frequency 33
=> cause reference sideband spurs
 Divide-by 4 or 5 Cell

000
MC MC: X
001 X
D Q D Q D Q 100
Q1 Q2 Q3 0
1
C Qb C Qb C Qb 010
0 X
0
CK 1
OUT 110

4/5 decision
1
point 011

CK
Q1
Q2/OUT

Q3
4/29/2005MC 34
 D-Type Flip-Flop with Merged NAND Gate

Vdd
M15 M16 M17
Pbias M18
Q
Qb
A M1 M2
M7 M8 M14 M13
Ab M9 M10

B M3 M4

Bb
M5 M6 M11 M12

CK
CKb
IB IB

GND
4/29/2005 35
 Dual Modulus Prescaler ( P/P+1)

MC

MC D Q D Q D Q D Q OUT
4/5
CK CK OUT C Qb C Qb C Qb C Qb

Divide-by 64/65 Prescaler

• Dual modulus prescaler consists of synchronous and asynchronous

counters
• Each stage of extender runs at 1/2 frequency of previous stage.
• For fast operation and low digital noise, CML is used
• In current mode logic design, supply current may be scaled down
in slower stages
4/29/2005 36
 True Single Phase Clock /2 divider
& Divider operation
VDD VDD VDD

ck ck ck ck
VDD D VDD D D D
D D D

ck ck ck ck
GND GND GND

CK frequency halved CK=0 CK=VDD

CK
D

4/29/2005 37
 Basic divider component: Latch
VDD VDD

out out out

out
in in

ck ck ck ck

Vbias Vbias

In-data sample Hold

4/29/2005
Source Coupled Logic (SCL) Latch 38
 E-TSCP for 2/3 divider
MC
÷2 ÷2 ÷2/3 D Q
D Q FF
FF Q
Q out
in
MC

VDD

in in
3 2 3 1.5 3 3 2 3

out
in in in in
0.5 1.3 2 2 0.5 0.5 1.3 3

GND
MC

4/29/2005 Extended TSPC logic: “ratioed” logic 39

 Frequency Synthesizer
• A frequency synthesizer generates a user selectable set of
frequencies from a fixed frequency reference.

• Goals in frequency synthesizers for wireless communications:

Low Cost : consumer
Low power consumption & low supply voltage : Portable
High performance
- Signal quality : phase noise & spurs
- Frequency accuracy
- Frequency switching time

• Frequency Synthesizer : PLL-based frequency synthesizer

- Integer-N synthesizer
- Fractional-N synthesizer
Direct digital frequency synthesizer(DDFS)
4/29/2005 40
 Phase Noise Overview
qNoise Sources
qLinear Time Invariant model
qThe Linear Time Variant (LTI) Model
qNoise in Voltage Controlled Oscillators
qPhase Noise in Digital and Analog World
qFrom Phase Noise to jitter
4/29/2005 41
 Noise
Ø Device Noise Ø Interferer
q Thermal Noise qPower Supply Noise
q Flicker Noise qSubstrate Noise
q Shot Noise

Massive grown in wireless communications demands for

more available channels imposing prohibitive
requirements on phase noise in local oscillator LO
In digital applications noise manifests himself as jitter
limiting the max clock frequency as well as A/D and D/A
4/29/2005 interface circuits resolutions 42
 Ideal vs Real Oscillator
qIdeal Sinusoidal Oscillator
Vo (t ) = A cos(ω0 t + φ0 )

φ0 = const
Spectrum is a couple of impulses @ ± ω0 − ω0 ω0 ω

qReal Sinusoidal Oscillator

Vo (t ) = A(t ) ⋅ f [ω0 t + φ0 (t )]
− ω0 ω0 ω
Noise impacts Amplitude as phase, its spectrum is not anymore an impulse but
presents skirts.
The function f (•) is a periodic function of period 2π
4/29/2005 43
 single sideband noise spectral
density
• There are many ways for quantifying fluctuations due to noise. Signal’s short-term
instabilities are usually characterized in terms of the single sideband noise spectral
density.
 Psideband (ω0 + ∆ω,1Hz )  dBc 
L {∆ω} = 10 log    
 P carrier   Hz 

spur
L(ωm) dBc

ω0 + ∆ω
ω
• Psideband (ω0 + ∆ω,1Hz ) represents the single sideband power at a frequency offset
of from the carrier with a measurement bandwidth of 1Hz.

• Note that the above definition includes the effect of both amplitude and phase
fluctuations.
4/29/2005 44
 Phase Noise in Transceveir I
FILTER
blocker
Desired
Band ω0 ω LO = ω IF
ωint ωs = ωIF
LNA
ωo ωint ωIF ω
Band Pass IF
blocker blocker
Desired Desired Filter
Band Band

ωo ω ωo ωint
ωint

Frequency Channel
Duplexer Synthesizer Selection
ω LO ω
Filter

PA
Band Pass
Filter
Base Band
4/29/2005 45
 Phase Noise in Transceveir II FILTER
• Phase Noise Limits the ω0 ω LO = ω IF
blocker

receiver sensitivity! Desired

Band

LNA ωIF ω
ωint ω s = ωIF
ωo ωint
Band Pass IF
blocker blocker
Desired Desired Filter
Band Band

ωo ω ωo ωint
ωint

Frequency Channel
Duplexer Synthesizer Selection
Filter ωLO ω

PA
Band Pass
Filter
Base Band
4/29/2005 46
 Linear Time Invariant Phase
• Simpler Oscillator
Noise Theory
• At anti-resonant frequency, admittance
is zero
RESTORING
1 R L C ENERGY
ω0 =
LC LOSSLESS

• Quality Factor
 1 
Q=ω
EnergyStored Y(ω) = G + jωC1 − 2 
AveragePowerDissitated  ω LC 

• Restoring circuit gives energy to oscillator in periodic manner to

restore oscillation amplitude

4/29/2005 47
 Oscillator –Few Equations
• For frequencies near to the resonant frequency ω = ω0 + ∆ω
 ∆ω(∆ω + 2ω0 )LC 
Y(ω0 + ∆ω) = G + j  ≈ G + j2∆ωC
 (∆ω + ω0 )L 

1 1 1 1 1
Z(ω0 + ∆ω) ≈ = ⋅ = ⋅
G + j2∆ωC G 1 + j 2∆ωC G 1 + j 2∆ωQ
G ω0

• Complete impedance is:

RESTORING
1 1
Z(ω0 + ∆ω) ≈ ⋅ R L C ENERGY
G j 2∆ωQ LOSSLESS
ω0
• Where –R is the mean equivalent resistance
• of active circuit -R
4/29/2005 48
 single sideband noise spectral
•
density
R is the only noise element in Oscillator and its noise is
i 2
= 4kTG
∆f
1 
 Psideband (ω0 + ∆ω,1Hz ) 
From L {∆ω} = 10 log  2 
Pcarrier
 
 

½ taking in account the equiripartion theorem of thermodynamics

2
2  ω0 
Psideband = i 2 Z G = 4kT 
 2 ∆ω Q 

 2FkT  ω 2 
L {∆ω} = 10 log   0
 
 Pcarrier  2∆ωQ  
F takes in account all other noise elements present in the restoring energy lossless
4/29/2005 49
 Linear Time Invariant Model
 2FkT  ω 2   dBc 
• L{∆ω} = 10 log   0
   Hz 
 carrier 
P 2 ∆ω Q  

• For reducing phase noise High Q values are demanding as well as maximize output
swing.
Unfortunatly maximize Q involves also a higher F values.
q This equation predict the phase noise of Oscillator but is not able to catch a
quantitative model for real Oscillator.
L(∆ω)
-3

-2

q Real Oscillator
4/29/2005 50
log∆ω
 Leeson LTI Model and its Limits
•
 2  ∆ω 1 
  ω   
{∆ ω} = 10 log  2 FkT f3
L P
 carrier
1 +  0
 1 +
  2 ∆ ω Q    ∆ω


 
q It is empiric L(∆ω)
q Factor F is note a posteriori -3

q It is not able to predict the noise corner1/f

q It is not possible to predict the corner of
-2
White noise plateau as its value 2 FkT
Pcarrier

∆ω 1 log∆ω
f3

q The Leeson Model is not able to quantify in a correct way phase noise aspects of a
real oscillator ( What is wrong?)

4/29/2005 51
 Understand Noise in Oscillators
q LTI Model gives qualitative but not exhaustive quantitative informations:
!something missing?

Oscillator WRONG
LTI ω0 ωnoise
ωnoise
ω0 ω0 ± ωnoise

Real
Oscillator ω0
ωnoise
ω0
q LTI not able to explains the creation of new harmonics!
q LTV model, extensive invocated due to high non linearity of Oscillators, can
explain these phenomena but fails on quantifying their amplitudes.
q What about sinusoidal Oscillators? (XTAL)
4/29/2005 52
 Oscillator Noise Model
qOscillator is a circuit with n inputs, one for each
noise source, and two outputs
qFrequency Oscillation is an intrinsic
characteristic of Oscillator
Vo (t ) = A(t ) ⋅ f [ω0 t + φ0 (t )]

Real A (t )
inputs noise Oscillator
ω0 φ0 ( t )

qThe “Oscillator System” is a Linear Time Variant

System!
4/29/2005 53
 The
q Effect of same
Oscillator System I
noise current
impulse on a
sinusoidal
(linear) LC
oscillator
injected at
different times
q
∆V =
C
in
q In both cases
output present a
same variation

4/29/2005 54
 •
The Oscillator System II
Phase-to-Noise Transfer Function is Linear even if the active elements
constituting the Oscillator experiments high non linearities!
• The effect of noise on phase is high dependently from the time it appears in
the system.
• Whereas variation on amplitudes are absorbed by system, variation on
phase persists indefinitely in the Oscillator
• What is noise? It is a perturbation superimposed on an existing oscillations.
The assertion of linearity is held for q noise ≤ q max
.
• How we can represent it?
φ(t ) A (t )

h φ (t , τ ) τ h A (t , τ ) τ
in φ(t ) in A (t )

τ τ
Ø Oscillator in its noise behaviour is a "Linear Time Invariant System !”
q Could be characterized by its impulse response
4/29/2005 55
 Phase Noise Impulse response I
Γ(ω0 τ )
h φ (t , τ ) = u (t − τ )
q max
• Γ(ω0τ) Is a periodic function of period 2p. Thake account of different
sensitivity of Oscillator to the noise injected @ phase ω0τ !
• It is called Impulse Sensitivity Function (ISF) and it is a-dimensional
independent from frequency.
• Output of Oscillator de to input noise present a time varying phase:
+∞ t
1
φ(t ) = ∫ h φ (t, τ) ⋅i(τ)dτ = q ∫ Γ(ωo τ) ⋅i(τ)dτ
−∞ max −∞
• Γ(ω0τ)is periodic could be expandend in taylor series
co ∞
Γ(ωo τ ) = + ∑ c n cos(nωo τ + θn )
2 n =1
• Only few terms of series give not negligible contribute
4/29/2005 56
 Phase Noise Impulse response II
q Important quantitative informations for designing a low phase noise
Oscillator inside equation!
1  c0 t t 
φ(t ) =  ∫ i(τ )dτ + ∑ c n ∫ i(τ ) cos(nωo τ )dτ
q max  2 −∞ −∞ 
+∞ t
1
q Block Diagram of φ(t ) = ∫ h φ (t, τ) ⋅i(τ)dτ = q ∫ Γ(ωo τ) ⋅i(τ)dτ
−∞ max −∞

Γ(ω0 τ ) Γ(ω0 τ )

i(t ) t φ(t ) i(t ) φ(t )

q max
∫ q max
−∞

q Block Diagram of Mathematic sequences is the same as a Direct

Conversion RF Receiver
4/29/2005 57
 Phase Noise Impulse response III
1  c0 t t 
φ(t ) =  ∫ i(τ )dτ + ∑ c n ∫ i(τ ) cos(nωo τ )dτ
q max  2 −∞ −∞ 

c0 i(t ) = I0 cos ∆ωt

2 I 0c0 t
φ(t ) = ∫ cos ∆ωτdτ
2q max −∞
I 0c 0
c1 cos(ω0 t + φ1 )
φ(t ) = sin (∆ω ⋅ t )
2q max ∆ω
i(t ) φ(t )
q max
cn cos(nω0 t + φn ) i(t ) = I m cos[(mω0 + ∆ω)t ]
Imcm t
φ(t ) = ∫ cos ∆ωτdτ
2q max −∞
I c
φ(t ) = m m sin (∆ω ⋅ t )
4/29/2005 2q max ∆ω 58
 Phase Noise Impulse response IV
in φ(t )
Oscillator
ω LTV
nω0 + ∆ω ω0 ω
∆ω
Γ(ω0 τ )

c0 c c2 cn cm
1
2
q A noise tone at an offset ∆ω from carrier or harmonics generates a new
tone at a different frequency. More again its amplitude is a linear function of
input amplitude as confirmed by simulations and measurements.
q !! Spectrum of phase φ(t) has been determined not the spectrum of output
voltage !!
4/29/2005 59
 •
Phase – Voltage Conversion
Amount of Voltage power due phase noise
Vo (t ) = A cos(ω0 t + φ(t ))

Ø Even in Phase-Voltage conversion is a non linear transform LTV

model entails in f(t) quantification. The concept of nonlinearity helds
in PM modulation for determining the voltage spectrum
Vo (t ) = A cos(ω0 t + φ(t )) ≅ A cos ω0 t − Aφ(t )sin ω0 t
I mcm
φ(t ) = sin (∆ω ⋅ t )
2q max ∆ω
1 I c
Vo (t ) = A cos(ω0 t + φ(t )) ≅ A cos ω0 t + A m m [cos(ω0 + ∆ω)t + cos(ω0 − ∆ω)t ]
4 q max ∆ω
Ø Hence injecting a sinusoidal tone at an offset from oscillator
frequency or its harmonics produces a couple of tones in the
Spectrum of Vat as simulations and measures confirm
4/29/2005 60
 single sideband noise spectral
density using LTV Model
 Psideband (ω0 + ∆ω,1Hz )
From L {∆ω} = 10 log  
 Pcarrier 

The term ½ is not present because we have that all noise transforms in phase noise
2
 1 AImc m 
Psideband =  
 4 q max ∆ω 
  1 I c 2 
L{ }
∆ω = 10 log 2 m m  
 
  4 q max ∆ω  
q !! Noise amplitude is a linear function !!
q You want less phase noise? ! Reduce cn coefficients and maximize qmax !

4/29/2005 61
 single sideband noise spectral
density using LTV Model
 i 2n ∞ 2 
 1 I 2m c 2m 
 ∑ cn 
1 ∆f
From L {∆ω} = 10 log  2 2
∆ω} = 10 log  2 n =0 2 
{L  4 q ∆ω 
 q max ∆ω 
8
 max 
 
2
∞ 1 2π
If we use Parsifal Theorem ∑ cn = ∫ Γ(x ) dx = 2Γrms
2 2
n =0 π0
 i 2n 2 
1 Γrms 
L {∆ω} = 10 log  ∆2 f 2

 2 q max ∆ω 
 
 
q Alert ! This equation contains less information than previous one!

4/29/2005 62
 Phase Noise - Exercise 1-
 i 2n 2 
1 Γrms 
• Use LTV model L {∆ω} = 10 log 
∆ f  to determine the LTI equation
2 2
 2 q max ∆ω 
 
 
2 2
i n 4kT q max = Cload Vmax 1 Vmax
= Pcarrier =
∆f R 2 R

 2FkT  ω 2 
• L{∆ω} = 10 log 2 ⋅   0
 
 carrier 
P 2 ∆ω Q  

v Result is two time bigger because the assertion all noise is converted in phase noise
4/29/2005 63
 Flicker Noise in Oscillators
ω1
2 2
i 1 = in ⋅ f ∆ω ≤ ω 1
n,
f ∆ω f

ω1
• LTV model asserts this noise is weigthed by c0 coefficient only f

 i 2n 2  Whereas for white noise we have:

 c0 ⋅ ω 1   i 2n 2 
1 ∆ 1
L {∆ω} = 10 log 
f f  1 Γrms 
•
 8 q max ∆ω ∆ω 
2 2
L {∆ω} = 10 log  2 ∆f 
  2
 q max ∆ω 
2
   
• Equating the arguments we find an important design equation
 

c02 1
∆ω 1 = ⋅ 2 ω1
f3
2 Γrms f
• In High Deep CMOS technologies where flicker noise is very high it is mandatory to reduce c0
coefficient for low noise oscillators.
4/29/2005 64
 Simulated Impulse Sensitivity
Function
ISF vs Tinject (N=3, fo=1.8GHz)
0.3

0.2

0.1
ISF

0.0
0 1 2 3 4 5 6 7

-0.1

-0.2

-0.3
4/29/2005 Tinject (rad) 65
 LTV Model – Conclusions-
Ø LTV Model quantify in mathematical way constraints to follow for
design Low Phase Noise Oscillators
q Maximize qmax Maximize Output Voltage Swing
q Reduce Γrms
q The active circuit used in each Oscillator to supply for losses must
delivery energy all at once at the phase in which circuit is less
sensitive to the noise
q Duty Cycle of 50% is mandatory because this waveform reduces the
value of cn coefficients for n even
q Reduce c0 coefficient to minimize Flicker Noise
1 2π
c0 = ∫ Γ(x )dx
π0
is two times d.c. value and to minimize its value it is mandatory
having a symmetric output voltage( rise fall)
q The output impedance must be linear

4/29/2005 66
 Impulse Sensitivity Function ISF
How to calculate
qBy means of simulations:
Noise impulse is injected at different phase
moments (0…..2π) then after few cycles the
phase shift is measured
∆t
∆φ = 2π
T
then h φ (t, τ) is calculated and multiplied by qmax

qDirectly from output signal properties

4/29/2005 67
 JITTER vs PHASE NOISE
• Why different definitions for the same phenomena?

Digital World Analog World

PLL
Clock Generation Frequency
Synthesis

always

Jitter Phase
Noise

constraints

4/29/2005 68
 Phase Noise and Timing Jitter
analysis
• Phase noise and timing jitter
– Phase noise
• Measure of spectral density of clock frequency
• Units: dBc/Hz (decibels below the carrier per Hz)
• à Analog people care about this

– Timing Jitter
• Measurement of clock transition edge to reference
• Units: Seconds (usually pS)
• à More intuitive, useful in digital systems
4/29/2005 69
 Jitter Definition
q The n-th period is defined as: Tn = t n +1 − t n

Ideal Clock

tj tn

Real Clock

Long term jitter

T + ∆T1 T + ∆T2

q For an ideal clock this time difference is independent of n, but in reality it varies with
n as a result of noise in the circuit. This results in a deviation from its mean period :
∆Tn = Tn − T
q The quantity ∆Tn is an indication of jitter.
4/29/2005 70
 Jitter Definitions
q {t n } is a sequence of transition times with nominal period T
If

q The sequence A j (n ) = {t n − n T} characterizes the long term jitter and limits the resolution of
A/D Converters

q period jitter characterizes the variation in the period from the nominal or average period
{Pjittern (T ) = t n+1 − t n − T}
it reduces the time available for data processing per clock cycle; the period jitter is the first difference
of absolute jitter.

q Jitter over k-period is

{Pjittern (kT) = t n+k − t n − kT = t n+k − (n + k )T − (t n − nT )}
q The first difference of period jitter provides another measure of jitter called adjacent period jitter

{∆jittern = Pjittern +1 (T ) − Pjittern (T ) = (t n +2 − t n +1 ) + (t n+1 − t n )}

It characterizes the local changes in the period from one cycle to the adjacent one

4/29/2005 71
 •
Jitter from Phase Noise I
The variance for stationary absolute jitter is related to the total area
of its power spectrum +∞
1
σ 2A = ∫ Sφ (f )df
(2πf0 )2
−∞
• From relation between period jitter and absolute jitter it is possible to
write
Pjitter = A j (n + 1) − A j (n )
n

• the variance for period jitter is

+∞
1
σ 2j ∫ sin (πfT )Sφ (f )df
2
=
(πf 0 )2 −∞

• more generally the variance over k period is

+∞
1
σ 2j (kT ) = ∫ sin (πfkT )Sφ (f )df
2
4/29/2005 (πf 0 )2 −∞ 72
 Jitter from Phase Noise II
Exercise
q determine the variance for adjacent absolute jitter
{
∆jn (kT ) = Pjn (n + k ) − Pjn (n ) }

( )
P∆jn (kT ) (z ) = z k Pjn z − Pjn (z ) = Pjn (z ) z k + 1 = A jn (z ) z k + 1 ( )2

n
2
SP∆j (kT ) = P∆jn (kT ) (z ) = A jn (z ) z + 1
2
( k
)
22
(
= Sφ (z ) z + 1
k
) 22

+∞ +∞
1 4
σ 2∆j (kT ) = ∫ SP∆ jn (kT ) (f )df = ∫ sin (πfkT )Sφ (f )df
4
(2πf0 )2 −∞ (πf0 )2 −∞
4/29/2005 73
 PLL Noise Transfer Functions NTF
q Each building block in the closed loop structure of PLL is an inherit source of noise ,
and its contribution to the output total noise could be easily obtained using following
2
formula S (f ) φi = S (f ) ⋅ H ( jω)
φi ni
φXTAL n closed
φe φPFD n iCPn VLPFn φVCOn

φref Charge
Phase Low Pass VCO φout
frequency Pump KVCO
Filter
Detector KCP F(s)

1
N

φDIVn
q
i
( )
where H n jω is the noise transfer function from each input noise to the PLL output whereas
the open loop function is: 1 K VCO
4/29/2005
G s ()
= K CP F s () 74
N s
 PLL Noise Transfer Functions NTF II
q The closed loop transfer function of PLL is
G (s ) ⋅ N
H PLL (s ) =
1 + G(s )
q The contribution of the input noise on the output is
φCLKOUT (s ) G (s ) ⋅ N
H XTALn (s ) = = = H PLL (s )
φXTALn (s ) 1 + G (s )
q The PFD introduces noise contribute that manifests as jitter on DN and UP outputs
K VCO
K CP ⋅ F(s ) ⋅
( φ
s ) = CLKOUT =
(s ) s = 1 G (s ) ⋅ N = 1 ⋅ H
Hφ PLL (s )
PFDn φPFD n (s ) 1 + G (s ) K PFD 1 + G (s ) K PFD
q Charge pump block introduces different noise contributions as mismatch in UP and
DN currents, Dead Zone and PSR and its noise transfer function at system level is:
K VCO
F(s ) ⋅
φCLKOUT (s ) 1 G (s ) ⋅ N 1
HiCP (s ) = = s = = ⋅ H PLL (s )
iCP (s ) 1 + G (s ) K PFD ⋅ K CP 1 + G (s ) K PFD ⋅ K CP
4/29/2005 75
 PLL Noise Transfer Functions NTF III
q Loop Filter is the third critical component in the loop because the noise
present at output module the VCO by means of its KVCO gain
K VCO
φ
H VLPF (s ) = CLKOUT =
(s ) s =
1 G (s ) ⋅ N
=
1
⋅ H PLL (s )
n VLPFn (s ) 1 + G (s ) K PFD ⋅ K CP F(s ) 1 + G (s ) K PFD ⋅ K CP F(s )

q Error introduced by the VCO is a phase error and its transfer function is:

Hφ (s) = φCLKOUT(s) = 1 = 1 G(s) ⋅ N

=
s
⋅ H (s)
φVCO(s) 1 + G(s) K KVCO 1 + G(s) KCPKCPF(s)KVCO PLL
CP ⋅ KCPF(s )
VCO
s
q Finally error introduced by the loop feedback divider N is:

φCLKOUT (s ) G (s ) ⋅ N
H φDIV (s ) = = = H PLL (s )
n φDIVn (s ) 1 + G (s )
4/29/2005 76
 Jitter and Phase noise in First
Order PLL
• l φXTAL n
φe φPD n φVCOn

φref
Phase VCO φout
Detector KVCO

1
N

φCLKOUT (s )
= Hφ (s ) = K 1 ⋅ K =
s
φVCO n (s ) VCO
1 + PFD VCO s + ωl
ωl = K PFD ⋅ K VCO
s
4/29/2005 77
 Jitter and Phase noise in First
q
Order PLL – VCO Noise -
The power spectral noise of output is
ω2
Sφ (ω) SφCLKOUT (ω) = ⋅ SφVCO (ω)
SφVCO (ω) ω 2
+ ω2L n
n

c
σ2A =
SφVCO (ω) 2ωL
n
ω1
ω
(
σ 2j (kT ) = 2σ 2A 1 − e
−ωL kT
)
HφVCO (ω)
n
q Due to the fact that for the phase noise of output CLKOUT is the same as the phase noise of
VCO. This equation emphasizes as the loop adjusts VCO control voltage to compensate for its
slow random variations which are slower than loop’s dynamics but is not able to react fast enough
to high frequency random changes in the VCO output and hence these fast variations appear
directly on the output
4/29/2005 78
 Jitter and Phase noise in First
Order PLL - XTAL input noise -
qThe power spectral noise of output is
Sφ (ω)
ω2L
SφCLKOUT (ω) = 2
⋅ SφXTAL (ω)
SφOUT (ω) ω + ω2L n

SφXTAL (ω)
n

HφXTAL (ω)
n
ωL ω
4/29/2005 79
 Frequency Spectrum of RF Signal

Carrier

In-band phase noise

Noise peaking due to loop transfer function

VCO inherent phase noise

fBW
Spurs

20 log(N2) 20 log(N1)
Synthesizer phase noise floor
N1 > N2

4/29/2005 80
 Phase Noise

4/29/2005 Phase noise : -59.7 dBc/Hz @ 500Hz offset with a carrier frequency 81
of 1.8 GHz.
 BEHAVIORAL MODELING OF
APLL
Manuel CAMUS
April - September 2004

Training supports : Francois Bauduin & Pasquale Lamanna

4/29/2005 82
 BEHAVIORAL MODELING OF APLL
LO C K
LO CKDET

N
ACCMOD
D igital blocks
UP2 D N Z2 Analog blocks PLL’s characteristics
RCK UP

FOUT
– 2 modes over 5 are fractional
CP LF VCTL
VCO (prescaler mode N/N+1)
PFD
DAC
CKF DNZ
– Compensation of the phase error by
opposite current injection ( by
means of DAC )
IBIAS

N
– Integrated Loop Filter

LO O P C N T

PLL’s equations :
Open loop Close
Close loop

Φr Icp ⋅ Z LF ( s ) ⋅ Kv GO ( s )
GO ( s ) = = Gc ( s ) =
Φi N ⋅s 1 + GO ( s )

4/29/2005 83
 BEHAVIORAL MODELING OF APLL
APLL’s Model

• PLL Modeling:
– Main function : Not complicated
– The major point : understand the significant non-ideal parameters to
modeling
– Model’s description :

PLL's blocks Type of Model Supply noise Phase Noise Other Non-ideal Parameters
PFD Verilog or VerilogA no yes Dead Zone
Delay on Up & Dnz
CP VerilogA yes no Mismatch beetwen UP & DNZ
Output Resistor
DAC VerilogA and Verilog no no Current Mismatches
LOOPFILTER VerilogA or Spice yes no Leakage Current
Parasitic capcitor
VCO VerilogA yes yes Intrinsic Jitter
DIVIDER VerilogA or Verilog no yes Delay
IBIAS VerilogA yes no
ACCMOD Verilog no no
4/29/2005 LOCKDET VerilogA no no 84
TEST Verilog no no
 BEHAVIORAL MODELING OF APLL
Example of critical Block : VCO
• Main function plus Supply Noise, Phase Noise & Intrinsic jitter

FVCO = Fc − KVCO ⋅ (VCTL − (VDDA − VCTLLOCKED )) + K 0 ⋅ VNOISE

FVCO ∆T = ∆Tintrinsic + ∆T phase _ noise
FVCO =
1 + FVCO ⋅ ∆T 70

• Model’s Parameters : only 8 60

VCO Supply noise Model
– Free running frequency ( Hz ) F
:c 50
– VCO gain ( Kv in Hz/V) :

P2P Jitter (ps)

40
– VCTL Locked ( in Volts ) : KVCO
– VCO intrinsic Jitter VCTLLOCKED 30

– Power supply rejection : 20

Schema
• Static sensitivity : K O Model
10
• Variation vs. frequency ( filter effect )
– Phase Noise : Sideband Power (dBc) at 0
100 1000 10000 100000
delta frequency ( Hz ) : σ (T ) = f ⋅10Γ( f ) 20 Supply noise frequency (kHz)
∆T 3/ 2
fc

4/29/2005 85
 BEHAVIORAL MODELING OF APLL
• Time simulation comparison • Waveforms comparison :
: Model :
Output
( Transient Analyze : 20us ) period
Schematic Model
10 850 min 24 min

÷450
• Output results comparison : VCTL

Clean Supplies Supply Noise 10MHz 50mV P2P

Model Schema Model Schema
VCTL CLKOUT VCTL CLKOUT VCTL CLKOUT VCTL CLKOUT
MC384 Mode (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps)
integer 1
fractionnal 1
0.21
3.53
12
99
0.31
3.76
13
100
49.45
50.92
104
174
48.87
51.22
101
177
Schematic :
fractionnal 2 3.85 106 3.43 106 50.37 142 50.35 143
integer 2 0.34 16 0.35 19 49.51 107 48.94 102 Output
period

Supply Noise 1MHz 50mV P2P Supply Noise 100KHz 50mV P2P
Model Schema Model Schema
VCTL CLKOUT VCTL CLKOUT VCTL CLKOUT VCTL CLKOUT
MC384 Mode (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps) (P2P mV) P2P Jitter (ps)
integer 1 50.55 36 50.62 34 50.59 16 50.64 14
fractionnal 1 53.03 120 53.29 126 52.98 97 53.15 102 VCTL
fractionnal 2 51.26 113 51.68 108 53.97 107 53.51 110
integer 2 50.58 46 50.22 40 50.81 28 50.27 20

4/29/2005 86
 BEHAVIORAL MODELING OF APLL
Appendix 3 : VCO phase Noise Model
• Period Jitter : ∆Tn = t n +1 − t n − T
E[θ 2 (t )] E[θ (t + ∆T )] 2 ⋅ E[θ (t ) ⋅θ (t + ∆T )]
{ }
2
1
• Variance : σ 2 ∆T = E [θ (t + ∆T ) − θ (t ) ]2
= + −
ϖ0 ϖ0 ϖ0 ϖ0
2 2 2 2

Rθ (τ ) = E[θ (t ) ⋅ θ (t + τ )] σ ∆2T =
2
[ Rθ (0) − Rθ (∆T )]
ϖ0
2

σ ∆2T = c ⋅ T
∞
8
• Khinchin theorem:σ 2
∆T = 2 ∫ Sθ ( f ) ⋅ sin2 (πf∆T )df
ϖ0 0
∞
Rθ (τ ) = ∫S
−∞
θ ( f )e j 2πfτ df

c cFN
VCO Phase noise spectrumS : ( f ) = f ⋅( +
2
• Φ c )
f2 f3
f Γ( f )
σ ∆T (T ) = 3/ 2
⋅10 20
fc
1 1 fc
• Model : Fvco = = =
T Tc + ∆T 1 + fc ⋅ ∆T
Schema Model
RMS Jitter (ps) 5.7 5.7
P2P Jitter / 300 samples (ps) 33.2 32.3
• Results : P2P Jitter / 30000 samples (ps) 46.9 52.9

4/29/2005 87
 BEHAVIORAL MODELING OF APLL
Appendix
Reference
Noiseφ
4 : Noise in PLL
nr
PFD CP VCO
Noise φnc Noise

RCK φnv
+ PFD Icp VCTL FOUT
φi
CKF CP
+ LF VCO +

Divider
Noise φnd

+ LOOPCNT
Divider M

Kv
Icp ⋅ Z ( s) ⋅
φ
• Reference Noise : T 1( s ) = 0 =
φnr
s = N ⋅ G0 ( s )
Icp ⋅ Z ( s) ⋅ Kv 1 + G0 ( s )
1+
N s
Kv
Z ( s) ⋅
φ
• CHPUMP Noise : T 2( s ) = 0 =
φnc
s =
N
⋅
G0 ( s )
Icp ⋅ Z ( s ) ⋅ Kv Icp 1 + G0 ( s )
1+
N s

φ0 1 1
• VCO Noise : T 3( s ) =
φnv
= =
Icp ⋅ Z ( s ) ⋅ Kv 1 + G0 ( s )
1+
N s
Kv
Icp ⋅ Z ( s ) ⋅
• Divider Noise : φ
T 4( s) = 0 =
φnd
s = N ⋅ G0 ( s )
Icp ⋅ Z ( s) ⋅ Kv 1 + G0 ( s )
1+
N s
4/29/2005 88
 BEHAVIORAL MODELING OF APLL
Appendix 5 :Loopfilter
• Second order LoopFilter :
1 + RC1
H ( s) =
CC -20dB/dec

(C0 + C1 ) ⋅ s ⋅ (1 + R 0 1 s )
C0 + C1
f ( log )

fz fp
R=20k C1=80pF C2=1.8pF -20dB/dec

• Integrated LoopFilter : Capacitor with transistor

– Current Leakage
– Capacitor Variation vs. VCTL

Current Leakage
effect on VCTL :

4/29/2005 89
 BEHAVIORAL MODELING OF APLL
Appendix 6 : Fractional Mode
• ACCUMULATOR MODULO-P :
99 5 8
Example: 13->99 MHz : = 7 + 8 = 7.61538
13 13 13

M=8
P=13

• Phase Error Compensation :

4/29/2005 90
 PCS CDMA Transceiver

1840-1870MHz I
1855 MHz 220.38 MHz

LNA ÷2

1619.62-1649.62MHz Resonator

Duplex
PLL ADC & DAC

Filters
1900MHz
130.38MHz Q
SAW
Modem

1750-1780 MHz I
1619.62-1649.62 MHz
÷2
PLL

Tank

4/29/2005 260.76 MHz 91

 Synthesizer Circuits
q Reference Oscillators

q Phase Frequency Detectors (PFDs)

q Charge Pump and Loop Filters

qVoltage-Controlled Oscillators (VCOs)

q Frequency Dividers
4/29/2005 92
 Reference Oscillators

• Generally based on Quartz Crystal ( Q > 10000 )

• Crystals are designed to operate at a single frequency in

range 1 to 100 MHz.

• Key spec is frequency stability which is expressed in ppm

over a fixed temp. range.

- Temperature compensation circuit can be built.

- Tuning mechanism can be built.

4/29/2005 93
 Sideband Spurs in PLL

• Result from systematic fluctuation of the PLL

• Mathematical View

Vc(t)=∆V sin(2πfreft)
PFD/CP LPF VCO : Kvf (Hz/V)

- Peak frequency deviation from the carrier frequency : ∆fpeak=Kvf ∆V

- Modulation index : β = ∆fpeak /fref
- Then, single sideband-to-carrier ratio : 20 log (β/2 ) dBc
=> Spurs can be reduced not only by decreasing ∆fpeak, but also by increasing fref.
• Approaches to reduction in spurs :
- Choose much narrower loop bandwidth than reference frequency
- Use high- order loop filter if possible.
- Choose higher reference frequency if possible.
- Use dead-zone free phase frequency detector and charge pump.
- Minimize mismatch in currents and switching in charge pump.
- Use fully differential configuration if possible.
4/29/2005 - Reduce leakage current. 94
……
 Charge Pump PLL-Based Synthesizer
Vc
Id VC F(s) C1 C
Up LPF
fr S1
PFD fo R
fv S2
Dn C
1 + sτ 2
Id F (s ) =
s(C + C 1)(1 + sτ1)
1/N
C C1
w here τ1 = R and τ 2 = R C
C + C1
• Close-loop transfer function:
K d Kv
(1 + sτ 2 )
B (s) =
(C + C 1)
1 K K τ K d Kv
s3 + s 2 + d v 2 s +
τ1 N (C + C 1) N (C + C 1)τ1

• Open-loop transfer function:

Type 2 third-order PLL
K d Kv 1 + sτ 2
4/29/2005 G (s)H (s ) = ⋅ 95
N (C + C 1) s2 (1 + sτ1)
 Phase Frequency Detector and Charge Pump
q Purpose: To produce a signal current, proportional to the
difference in phase or frequency between two input signals.

q Design Issues
§ - Gain and linearity
§ - Dead-zone free PFD/CP
§ - Mismatch between sourcing and sinking currents
§ - Mismatch in switching time between UP and Down
§ - Charge charging
§ - Leakage current
§ - Voltage compliance
§ - Others

4/29/2005 96
 VCOs

• Key Specs
- Spectral Purity ( Phase Noise )
- Tuning Range
- Tuning Linearity
- Supply and Substrate Noise Rejection (Integrated VCO)
=> Differential operation is very important

• Typical Approach
- Ring Oscillator --- too much phase noise!?
- LC Oscillator
- Colpitts, Hartley Configurations

• VCO Design & Analysis Models

- Feedback Model
- Negative Resistance Model
4/29/2005 97
 Frequency Dividers

• Reference Divider

- Max input frequency typically < 50MHz for low power

- Programmability to accommodate multiple channel spacings
or reference frequencies
- Any programmable ripple or synchronous counter will do.
=> Synchronous counter preferred ( low noise )

• Loop Frequency Divider

- Max input frequency = synthesizer output frequency
- Low power & low noise design ( current mode logic)
- Use specialized pulse-swallower architecture

4/29/2005 98
 Pulse Swallower Counter
A
Program
P/P+1 Prescaler counter
fout A-B
fin CK MC OUT CK LD OUT

B
Program B
counter
CK LD OUT

• Counter functionality:
- asynchronous load of value at Program data when LD is high.
- count down to terminal state $0 when LD is low.

4/29/2005 • Effective divide ratio N: N = B ( P+1 ) + ( A - B ) P = AP + B 99

 Fractional Divider

P/P+1 Prescaler
fin CK OUT fout
MC

Carry
K
M bit
D
CK

CK

• Mean value of divide ratio :

N eff =
( )
K ⋅ (P + 1) + 2m − K ⋅ P
=P +
K
w here 0 ≤ K < 2m
2m 2m 100
4/29/2005
 Design Example of PLL

- 40 dB/dec. • Design loop filter:

dB

− K d KV (1 + jωτ 2 ) τ1
G ( jω )H ( jω ) =
ω 2C 1N (1 + jωτ1) τ 2
GH

- 20 dB/dec.

0
φ (ω ) = 180 + a tan(ωτ 2 ) − a tan(ωτ1)
- 40 dB/dec.

ωp F (Hz) dφ τ2 τ1
= − =0
Ph. of GH

d ω 1 + (ωτ )2 1 + (ωτ )2
2 1

φp 1
ωp =
-180 F (Hz) τ1τ 2

For a given desired loop bandwidth and phase margin

K K τ 1 + (ωp τ 2 )
2
sec φp − tan φp 1 τ  τ
τ1 = , τ2 = , C1 = d v 1 , C = C 1 2 − 1 , R = 2
4/29/2005 ωp ωp2τ1 ωp2N τ 2 1 + (ωp τ1)2  τ1  C 101
 Integer-N Frequency Synthesizer
VCO
fref θo F
÷R PFD LPF fo = ref ⋅ N = fref ⋅ N
θref fo R
Fref
θo/N fo/N Channel Spacing
= Reference Freq.
N

• Drawback of single loop integer-N frequency synthesizer

- Channel Spacing Divide Ratio In-band Phase Noise

- Channel Spacing Loop Bandwidth Switching Time

• Design tradeoffs for a given system :

- Phase noise improves with higher PLL bandwidth
4/29/2005 - Spurious tones improve with lower PLL bandwidth 102
 Fractional-N Frequency Synthesizer

 k 
fo =  N + ⋅f
m  ref
fref PFD LPF VCO
 2
÷N or N+1 (N+1)fref

overflow
clock (N.F)fref
k m-bit Accum.
m bit Nfref

• Divider modulus is a periodic function of time.

• Reference frequency can be greater than the resolution frequency.

• In-band gain is reduced when reference frequency is increased

==> lower in-band noise.

• Typically, loop bandwidth of PLL can be increased compared to

integer-N divide ==> faster lock

4/29/2005 • Spurs generated by time-manipulation of divider modulus 103

==> fractional spurs
B.H. Park, 6/23/99
 Fractional Division Example

Consider fractional division which controlled by a 3-bit accumulator with k=1.

Reference frequency fref =240 kHz. Synthesize frequency 1200.03 MHz.
Accumulator contents vs. time
Radians at VCO ouput
cycle contents carry divide ratio
or divider input
2π 1 001 0 5000
2 010 0 5000
3 011 0 5000
4 100 0 5000
5 101 0 5000
6 110 0 5000
7 111 0 5000
8 000 1 5001
clock 9 001 0 5000
cycles 10 010 0 5000
Spurs at VCO output
average divide ratio over 8 cycles is 5000.125

4/29/2005 104
f ( kHz )
CENTER FREQ. 30 60 90 120 150

B.H. Park, 6/23/99

 Phase Estimation by DAC

fr PFD LPF fo fr
fv
N/N+1 fv

Phase
DAC carry error

m bit DAC
accum. output

K
Effective
Pd. error

• Cancels fixed spurs by phase interpolation

• Cancellation is limited by analog mismatch in the DAC

4/29/2005 105

B.H. Park, 6/23/99

 Fractional-N Synthesizer with Σ∆ Modulator

• Idea : Eliminate fractional spurs by modulating divide ratio using

high-order Σ∆ modulator.

• First-Order Σ∆ Modulator
input k output
m bit D residue
R
ck

+ + A(z)
+ + + Q(z)
F(z) Y(z)
- +
- +
z -1 A(z) Y(z)
2m 2m
4/29/2005 z -1 106
0

B.H. Park, 6/23/99

 Modeling of First-Order Σ∆ Modulator
Q(z)
+
+ 1
+ + Y(z)
1- z -1 +
F(z) -
z -1
+
-
+

- Q(z)

Y(z) = F(z) + ( 1 - z -1 ) Q(z)

4/29/2005 107

B.H. Park, 6/23/99

 Cascaded High-Order Σ∆ Modulator

f(n) First-Order Σ−∆ y1(n)

Modulator

-q1(n) y2(n)
First-Order Σ−∆
Modulator Bit
y(n)

-q2(n) First-Order Σ−∆ y3(n)

Manipulation
Modulator

First-Order Σ−∆ yn(n)

-qn-1(n)
Modulator

This system is always stable because the structure use a

noise feed-forward scheme.

4/29/2005 108
Y(z) = F(z) + ( 1 - z -1 )n Qn (z)
B.H. Park, 6/23/99
 Third-Order Delta-Sigma Modulator Implementation

output

{-3, -2, -1, 0, 1, 2, 3, 4}

+
+
+
-

z -1 z -1

{-1, 0, 1, 2}
+
+
- +

z -1 z -1 z -1

{0, 1} {0, 1} {0, 1}

+ + +
input + z -1 + z -1 + z -1
- - -
4/29/2005 109

B.H. Park, 6/23/99

 Fully-Integrated CMOS Fractional-N Synthesizer Example

fref PFD/CP LPF

Output

Multimodulus
Fref Buffer
Prescaler VCO
/R
Ref.
Input

k
Freq.
Setting High-Order Σ∆ Modulator
Data m bits

4/29/2005 110
fo = 1/R ( N + k / 2m ) Fref = ( N +k / 2m ) fref
B.H. Park, 6/23/99
 Swallow counter divider
Number of pulses
fRef fVCO counted
Program
Counter
M/M+1
Prescaler ( M + 1) S + ( P − S ) M =
/P
Modulus
( PM + S )
Swallow control

fVCO = ( PM + S ) ⋅ f Ref
Counter
/S
S = 1,2...

4/29/2005 111
 Tracking and Acquisition

• Tracking
: Extent to which the loop can follow variation
in the input frequency

• Acquisition
: How the loop goes from unlocked state to complete
phase lock

4/29/2005 112
 Integer-N Architecture

fREF fout
PD LPF VCO

÷M

Modulus Selection

- Drawback
Reference Spur
Loop Bandwidth
4/29/2005 Phase Noise 113
 Pulse Swallow Frequency Divider

÷M Program
Prescaler Counter
fin fout
÷(N+1)/N ÷P
Modulus
Control Reset
÷S Swallow
Counter
Modulus Selection

4/29/2005 114
 Fractional-N Synthesizer

fREF fout
PFD LPF VCO

Pulse
Remover

Remove

fREF fout
PFD LPF VCO

Pulse
÷M Remover

4/29/2005 Remove 115

 Dual-Modulus Divider
fREF fout
PFD LPF VCO

÷ (N+1)/N

Modulus Control

fREF fout
PD LPF VCO

÷10/11
Modulus Control
÷M TREF
4/29/2005 t 116
9TREF
 Randomization & Noise Shaping

To PD From VCO To PD From VCO

÷ (N+1)/N ÷ (N+1)/N

Randomizer Randomization
and
Noise Shaping

4/29/2005 117
 Dual-Modulus Divider

To PD From VCO

xF(t) ÷ (N+1)/N fout

b(t)
Σ∆
Modulator

4/29/2005 118
 Dual-Loop Synthesizer

fREF1
PLL1
Frequency
fc + M fREF2
Adder
PLL1
fREF2

Channel
Selection

4/29/2005 119
 Dual-Loop Synthesizer

fREF1
× LPF VCO1
I
×
Q

fout
÷N +
×
I

fREF2
LPF VCO2
Q ×
SSB Mixer
÷M

Channel
4/29/2005 120
Selection
 Dual-Loop Architecture

×
fREF1 I
fout
LPF VCO1
Q

SSB
÷M
Mixer
f2 I Q
Channel
Selection PLL2

0 f
fREF1
× LPF

SSB
÷N
Mixer
4/29/2005 fREF1 f 121
 Why All Digital PLL?
Improvements in digital designs

*Progress in increasing *Progress in reducing

• Performance • Size
• Speed
• Cost
• Reliability
* Portability/ Reusability
* Programmability
4/29/2005 122

* Testability
 Why All Digital PLL?
Solves Problems Related to Analog PLLs(APLL)
• Sensitivity to DC Drifts
• Component Saturations
• Difficulties building higher order loops
• Initial calibration and periodic adjustments

4/29/2005 123
 Issues of ADPLLs versus APLLs
• Limitation on operating speed
• Chip area
• Power Consumption
• Worse jitter performance due to D/A
converter resolution limitation
* Note: The above issues need further
exploration[7] as some papers have
4/29/2005 reported better ADPLL performance. 124
 Example ADPLL Loop Filter
• Up/Down control from the Phase Detector
Controls the Counter value or the Digital
Phase difference – Transfer Function ~ 1/sTi

Up/Down Counter

4/29/2005 125
 Example Digital VCO (DCO)
• Up/Down Counter Value or the Phase
Error is utilized to create the clock

%N Counter

4/29/2005 126
 Results[2]
• Shorter Locking in time
• Better Jitter Performance
• Better Portability (cell-based design)
• Reduced circuit complexity
• Reduced Design Time
• Note: Some other papers have reported
ADPLLs area and power statistics better
than APLLs
4/29/2005 127
 Summary- Why are ADPLLs
• Stability Better?
• Fast Acquisition Time
• Large hold-in range
• Large lock-in range
• Better phase jitter performance
• No need for off-chip components
• Technology portability
• Testability
• Programmability
4/29/2005 128
• Simpler design and faster simulation
ECE1352F – Topic Presentation - ADPLL
 Future of ADPLL
• Digital IP (Intellectual Property) vendors
are already creating ADPLL products
• As technology progress happens skew
problems will require ADPLLs within the
design components to synchronize the
clock signal between various blocks

4/29/2005 129