GAL20XV10

High-Speed E2CMOS PLD

Generic Array Logic™

Features Functional Block Diagram

• HIGH PERFORMANCE E2CMOS ® TECHNOLOGY
— 10 ns Maximum Propagation Delay I/CLK
— Fmax = 100 MHz
— 7 ns Maximum from Clock Input to Data Output 4
— TTL Compatible 16 mA Outputs OLMC I/O/Q
— UltraMOS® Advanced CMOS Technology I

4
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR OLMC I/O/Q
— 90mA Maximum Icc I
— 75mA Typical Icc 4
OLMC I/O/Q
• ACTIVE PULL-UPS ON ALL PINS I

PROGRAMMABLE
• E2 CELL TECHNOLOGY 4
I OLMC I/O/Q
— Reconfigurable Logic

AND-ARRAY
— Reprogrammable Cells

(40 X 40)
— 100% Tested/100% Yields 4
I I/O/Q
— High Speed Electrical Erasure (<100 ms) OLMC

— 20 Year Data Retention

4
I
• TEN OUTPUT LOGIC MACROCELLS OLMC I/O/Q
— XOR Gate Capability on all Outputs
— Full Function and Parametric Compatibility with 4
I
PAL12L10, 20L10, 20X10, 20X8, 20X4 OLMC I/O/Q
— Registered or Combinatorial with Polarity
I 4
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS OLMC I/O/Q

• APPLICATIONS INCLUDE: I 4
— High Speed Counters OLMC I/O/Q
— Graphics Processing
— Comparators I
4
OLMC I/O/Q
• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description I/OE

The GAL20XV10 combines a high performance CMOS process

with electrically erasable (E2) floating gate technology to provide
Pin Configuration
the highest speed Exclusive-OR PLD available in the market. At
90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides DIP
a substantial savings in power when compared to bipolar counter- PLCC
parts. E2CMOS technology offers high speed (<100ms) erase I/CLK 1 24 Vcc
times providing the ability to reprogram, reconfigure or test the de- I I/O/Q
I/CLK

I/O/Q

I/O/Q

vices quickly and efficiently.

Vcc
NC

I I/O/Q
I
I

The generic architecture provides maximum design flexibility by 4 2 28 26

I
GAL I/O/Q
I 5 25 I/O/Q
allowing the Output Logic Macrocell (OLMC) to be configured by 20XV10
I I/O/Q I I/O/Q
the user. An important subset of the many architecture configu- I 7 23 I/O/Q
rations possible with the GAL20XV10 are the PAL® architectures NC
GAL20XV10 NC
I 6 I/O/Q
listed in the macrocell description section of this document. The I 9 Top View 21 I/O/Q I 18 I/O/Q
GAL20XV10 is capable of emulating these PAL architectures with I I/O/Q I I/O/Q
full function and parametric compatibility. I 11 19 I/O/Q
12 14 16 18 I I/O/Q
Unique test circuitry and reprogrammable cells allow complete AC,
I

NC
GND

I/O/Q
I/O/Q
I/OE

DC, and functional testing during manufacturing. As a result, Lattice I I/O/Q

Semiconductor delivers 100% field programmability and function- I I/O/Q
ality of all GAL products. In addition, 100 erase/write cycles and GND 12 13 I/OE
data retention in excess of 20 years are specified.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

20xv10_02 1
 Specifications GAL20XV10

GAL20XV10 Ordering Information

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
10 6 7 90 GAL20XV10B-10LP 24-Pin Plastic DIP

GAL20XV10B-10LJ 28-Lead PLCC

15 8 8 90 GAL20XV10B-15LP 24-Pin Plastic DIP

GAL20XV10B-15LJ 28-Lead PLCC

20 10 10 90 GAL20XV10B-20LP 24-Pin Plastic DIP

GAL20XV10B-20LJ 28-Lead PLCC

Part Number Description

XXXXXXXX _ XX X X X

GAL20XV10B Device Name

Speed (ns) Grade Blank = Commercial

L = Low Power Power Package P = Plastic DIP

J = PLCC

2
 Specifications GAL20XV10

Output Logic Macrocell (OLMC)

The following discussion pertains to configuring the Output Logic Exclusive-OR macrocells. In Feedback mode, the state of the
Macrocell. It should be noted that actual implementation is register is available to the AND array via an internal feedback
accomplished by development software/hardware and is com- path on all macrocells. In Input mode, the state of the register
pletely transparent to the user. is available to the AND array via an internal feedback path on
macrocells 2 through 9 only, macrocells 1 and 10 have no feedback
The GAL20XV10 has two global architecture configurations that into the AND array.
allow it to emulate PAL architectures. The Input mode emulates
combinatorial PAL devices, with the I/CLK and I/OE pins used as REGISTERED CONFIGURATION
inputs. The Feedback mode emulates registered PAL devices with The Macrocell is set to Registered configuration when AC0 = 1 and
the I/CLK pin used as the register clock and the I/OE pin as an AC1 = 0. Three of the four product terms are used as sum-of-
output enable for all registers. The following is a list of PAL archi- product terms for the D input of the register. The inverting output
tectures that the GAL20XV10 can emulate. It also shows the buffer is enabled by the fourth product term. The output is en-
global architecture mode used to emulate the PAL architecture. abled while this product term is true. The XOR bit controls the po-
larity of the output. The register is clocked by the low-to-high tran-
sition of the I/CLK. In Feedback mode, the state of the register
PAL Architectures Emulated by GAL20XV10 Global
is available to the AND array via an internal feedback path on
GAL20XV10 OLMC Mode
all macrocells. In Input mode, the state of the register is available
PAL12L10 Input Mode
to the AND array via an internal feedback path on macrocells
PAL20L10 Input Mode
2 through 9 only, macrocells 1 and 10 have no feedback into the
PAL20X10 Feedback Mode AND array.
PAL20X8 Feedback Mode
PAL20X4 Feedback Mode XOR COMBINATORIAL CONFIGURATION
The Macrocell is set to the Exclusive-OR Combinatorial configu-
INPUT MODE ration when AC0 = 0 and AC1 = 1. The four product terms are seg-
The Input mode architecture is defined when the global mented into two OR-sums of two product terms each, which are
architecture bit SYN = 1. In this mode, the I/CLK pin becomes an then combined by an Exclusive-OR gate and fed to an output
input to the AND array and also provides the clock source for buffer. The inverting output buffer is enabled by the I/OE pin,
all registers. The I/OE pin becomes an input into the AND array which is an active low output enable that is common to all XOR
and provides the output enable control for any macrocell config- macrocells. In Feedback mode, the state of the I/O pin is avail-
ured as an Exclusive-OR function. Feedback into the AND array able to the AND array via an internal feedback path on all
is provided from macrocells 2 through 9 only. In this mode, macrocells. In Input mode, the state of the I/O pin is available to
macrocells 1 and 10 have no feedback into the AND array. the AND array via an input buffer path on macrocells 2 through
9 only, macrocells 1 and 10 have no input into the AND array.
FEEDBACK MODE
The Feedback mode architecture is defined when the global COMBINATORIAL CONFIGURATION
architecture bit SYN = 0. In this mode the I/CLK pin becomes a The Macrocell is set to Combinatorial mode when AC0 = 1 and
dedicated clock source for all registers. The I/OE pin is a dedi- AC1 = 1. Three of the four product terms are used as sum-of-
cated output enable control for any macrocell configured as an product terms for the combinatorial output. The XOR bit controls
Exclusive-OR function. The I/CLK and I/OE pins are not avail- the polarity of the output. The inverting output buffer is enabled
able to the AND array in this mode. Feedback into the AND array by the fourth product term. The output is enabled while this product
is provided on all macrocells 1 through 10. term is true. In Feedback mode, the state of the I/O pin is avail-
able to the AND array via an internal feedback path on all
FEATURES macrocells. In Input mode, the state of the I/O pin is available
Each Output Logic Macrocell has four possible logic function to the AND array via an input buffer path on macrocells 2 through
configurations controlled by architecture control bits AC0 and AC1. 9 only, macrocells 1 and 10 have no input into the AND array.
Four product terms are fed into each macrocell.

XOR REGISTERED CONFIGURATION

The Macrocell is set to the Exclusive-OR Registered configuration
when AC0 = 0 and AC1 = 0. The four product terms are seg-
mented into two OR-sums of two product terms each, which are
then combined by an Exclusive-OR gate and fed into a D-type
register. The register is clocked by the low-to-high transition of the
I/CLK pin. The inverting output buffer is enabled by the
I/OE pin, which is an active low output enable common to all

3
 Specifications GAL20XV10
Input Mode

OE
XOR Registered Configuration
- SYN = 1.
- AC0 = 0.
D Q - AC1 = 0.
- OLMC 1 and OLMC10 do not have the
Q feedback path.
- Pin 1(2) can be CLK and/or Input.
- Pin 13(16) can be OE and/or Input.

CLK

Registered Configuration
- SYN = 1.
- AC0 = 1.
- AC1 = 0.
D Q - XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
XOR Q - OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 1(2) can be CLK and/or Input.
- OE controlled by product term.
CLK

OE
XOR Combinatorial Configuration
- SYN = 1.
- AC0 = 0.
- AC1 = 1.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 13(16) can be OE and/or Input.

Combinatorial Configuration
- SYN = 1.
- AC0 = 1.
- AC1 = 1.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
XOR - OLMC 1 and OLMC10 do not have the
feedback path.
- OE controlled by product term.

4
 Specifications GAL20XV10

Input Mode Logic Diagram

DIP (PLCC) Package Pinouts
1(2)
0 4 8 12 16 20 24 28 32 36
0 OLMC
120
XOR - 1600 23(27)
AC0 - 1610
AC1 - 1620

2(3)
160 OLMC
280
XOR - 1601 22(26)
AC0 - 1611
3(4) AC1 - 1621

320 OLMC
440
XOR - 1602 21(25)
AC0 - 1612
4(5) AC1 - 1622

480 OLMC
600 XOR - 1603 20(24)
AC0 - 1613
5(6) AC1 - 1623

640 OLMC
760 XOR - 1604 19(23)
AC0 - 1614
6(7) AC1 - 1624

800 OLMC
920 XOR - 1605 18(21)
AC0 - 1615
7(9) AC1 - 1625

960 OLMC
1080 XOR - 1606 17(20)
AC0 - 1616
8(10) AC1 - 1626

1120 OLMC
1240 XOR - 1607 16(19)
AC0 - 1617
9(11) AC1 - 1627

1280 OLMC
XOR - 1608 15(18)
1400
AC0 - 1618
10(12) AC1 - 1628

1440 OLMC
1560 XOR - 1609 14(17)
AC0 - 1619
AC1 - 1629

11(13) 13(16)

40-USER ELECTRONIC SIGNATURE FUSES

1631, 1632, .... .... 1669, 1670
SYN - 1630
Byte4 Byte3 .... .... Byte1 Byte0

5
 Specifications GAL20XV10

Feedback Mode

OE

XOR Registered Configuration

- SYN = 0.
D Q - AC0 = 0.
- AC1 = 0.
Q - Dedicated CLK input on Pin 1(2).
- Dedicated OE input on Pin 13(16).

CLK

Registered Configuration
- SYN = 0.
- AC0 = 1.
- AC1 = 0.
D Q
- XOR = 1 defines Active Low Output.
XOR Q
- XOR = 0 defines Active High Output.
- Dedicated CLK input on Pin 1(2).
- OE controlled by product term.
- Pin 13(16) is not connected to this configura-
CLK tion.

OE

XOR Combinatorial Configuration

- SYN = 0.
- AC0 = 0.
- AC1 = 1.
- Dedicated OE input on Pin 13(16).
- Pin 1(2) is not connected to this configura-
tion.

Combinatorial Configuration
- SYN = 0.
- AC0 = 1.
- AC1 = 1.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
XOR
- OE controlled by product term.
- Both pin1(2) and pin 13(16) are not con -
nected to this configuration.

6
 Specifications GAL20XV10
Feedback Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
0 4 8 12 16 20 24 28 32 36
0 OLMC
120
XOR - 1600 23(27)
AC0 - 1610
2(3) AC1 - 1620

160 OLMC
280 XOR - 1601 22(26)
AC0 - 1611
3(4) AC1 - 1621

320 OLMC
440 XOR - 1602 21(25)
AC0 - 1612
4(5) AC1 - 1622

480 OLMC
600 XOR - 1603 20(24)
AC0 - 1613
5(6) AC1 - 1623

640 OLMC
760 XOR - 1604 19(23)
AC0 - 1614
6(7) AC1 - 1624

800 OLMC
920 XOR - 1605 18(21)
AC0 - 1615
7(9) AC1 - 1625

960 OLMC
1080 XOR - 1606 17(20)
AC0 - 1616
8(10) AC1 - 1626

1120 OLMC
1240 XOR - 1607 16(19)
AC0 - 1617
9(11) AC1 - 1627

1280 OLMC
1400 XOR - 1608 15(18)
AC0 - 1618
10(12) AC1 - 1628

1440 OLMC
1560 XOR - 1609 14(17)
AC0 - 1619
11(13) AC1 - 1629

13(16)

40-USER ELECTRONIC SIGNATURE FUSES

1631, 1632, .... .... 1669, 1670 SYN - 1630
Byte4 Byte3 .... .... Byte1 Byte0

7
 Specifications GAL20XV10
Absolute Maximum Ratings(1) Recommended Operating Conditions
Supply voltage Vcc ....................................... –0.5 to+7V Commercial Devices:
Input voltage applied .......................... –2.5 to VCC +1.0V Ambient Temperature (TA) ............................. 0 to +75°C
Off-state output voltage applied ......... –2.5 to VCC +1.0V Supply voltage (VCC)
Storage Temperature ............................... –65 to 150°C with Respect to Ground ..................... +4.75 to +5.25V
Ambient Temperature with
Power Applied .......................................... –55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while pro-
gramming, follow the programming specifications).

DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.3 MAX. UNITS

VIL Input Low Voltage VSS – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — VCC+1 V

IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 µA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

IOL Low Level Output Current — — 16 mA

IOH High Level Output Current — — –3.2 mA

IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25°C –50 — –150 mA

COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -10/-15/-20 — 75 90 mA
Supply Current ftoggle = 15MHz Outputs Open

1) The leakage current is due to the internal pull-up on all input and I/O pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at VCC = 5V and TA = 25 °C

8
 Specifications GAL20XV10

AC Switching Characteristics
Over Recommended Operating Conditions

COM COM COM

-10 -15 -20

TEST DESCRIPTION
PARAMETER UNITS
COND.1 MIN. MAX. MIN. MAX. MIN. MAX.
tpd A Input or I/O to Combinatorial Output 3 10 3 15 3 20 ns

tco A Clock to Output Delay 2 7 2 8 2 10 ns

tcf2 — Clock to Feedback Delay — 4 — 4 — 4 ns

tsu — Setup Time, Input or Feedback before Clock↑ 6 — 8 — 10 — ns

th — Hold Time, Input or Feedback after Clock↑ 0 — 0 — 0 — ns

A Maximum Clock Frequency with 76.9 — 62.5 — 50 — MHz
External Feedback, 1/(tsu + tco)

fmax3 A Maximum Clock Frequency with 100 — 83.3 — 71.4 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 100 — 83.3 — 71.4 — MHz

No Feedback

twh — Clock Pulse Duration, High 4 — 6 — 7 — ns

twl — Clock Pulse Duration, Low 4 — 6 — 7 — ns

B Input or I/O to Output Enabled 3 10 3 15 3 20 ns
ten
B OE to Output Enabled 2 9 2 10 2 15 ns

C Input or I/O to Output Disabled 3 9 3 15 3 20 ns

tdis
C OE to Output Disabled 2 9 2 10 2 15 ns

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V

CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V

*Characterized but not 100% tested

9
 Specifications GAL20XV10

Switching Waveforms

INPUT or
I/O FEEDBACK VALID INPUT
INPUT or
I/O FEEDBACK VALID INPUT ts u th

t pd CLK
COMBINATORIAL tc o
OUTPUT REGISTERED
OUTPUT
1 / fm a x
Combinatorial Output (external fdbk)
Registered Output

INPUT or OE
I/O FEEDBACK

t dis t en tdis ten

OUTPUT OUTPUT

Input or I/O Feedback to Enable/Disable

OE to Output Enable/Disable

CLK
tw h tw l
1/ fmax (internal fdbk)
CLK t cf tsu
1 / fm a x REGISTERED
(w/o fdbk) FEEDBACK
Clock Width
fmax with Feedback

Input/Output Equivalent Schematics

PIN
PIN

Feedback

Vcc Active Pull-up

(Vref Typical = 3.2V) Circuit
Active Pull-up
Circuit Vcc (Vref Typical = 3.2V)
Tri-State Vref
Control
Vcc Vref Vcc
ESD
Protection
Circuit
Data
PIN
Output
PIN

ESD
Protection Feedback
Circuit (To Input Buffer)

Typical Input Typical Output

10
 Specifications GAL20XV10

fmax Descriptions
CLK

LOGIC
REGISTER
ARRAY CLK

LOGIC
ARRAY
tsu tco REGISTER

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from measured

tsu and tco. t cf
t pd
CLK

fmax with Internal Feedback 1/(tsu+tcf)

LOGIC
Note: tcf is a calculated value, derived by subtracting tsu from
REGISTER the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
ARRAY
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
tsu + th
to a combinatorial output is equal to tcf + tpd.
fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.

Switching Test Conditions

+5V
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns 10% – 90%
Input Timing Reference Levels 1.5V R1
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active FROM OUTPUT (O/Q)
TEST POINT
level. UNDER TEST

C L*
Output Load Conditions (see figure) R2

Test Condition R1 R2 CL
A 300Ω 390Ω 50pF
Active High ∞ 390Ω 50pF
B
Active Low 300Ω 390Ω 50pF
Active High ∞ 390Ω 5pF *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
C
Active Low 300Ω 390Ω 5pF

11
 Specifications GAL20XV10
Electronic Signature Latch-Up Protection
An electronic signature word is provided in every GAL20XV10 GAL20XV10 devices are designed with an on-board charge pump
device. It contains 40 bits of reprogrammable memory that con- to negatively bias the substrate. The negative bias is of sufficient
tains user defined data. Some uses include user ID codes, revi- magnitude to prevent input undershoots from causing the circuitry
sion numbers, pattern identification or inventory control codes. The to latch. Additionally, outputs are designed with n-channel pullups
signature data is always available to the user independent of the instead of the traditional p-channel pullups to eliminate any pos-
state of the security cell. sibility of SCR induced latching.

NOTE: The electronic signature bits, if programmed to any value Input Buffers
other then zero(0) will alter the checksum of the device.
GAL20XV10 devices are designed with TTL level compatible in-
Security Cell put buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than bi-
A security cell is provided in every GAL20XV10 device as a deter- polar TTL devices.
rent to unauthorized copying of the device pattern. Once pro-
grammed, this cell prevents further read access of the device GAL20XV10 input buffers have active pull-ups within their input
pattern information. This cell can be only be reset by reprogram- structure. This pull-up will cause any un-terminated input or
ming the device. The original pattern can never be examined once I/O to float to a TTL high (logical 1). Lattice Semiconductor
this cell is programmed. The Electronic Signature is always avail- recommends that all unused inputs and tri-stated I/O pins be
able regardless of the security cell state. connected to another active input, Vcc, or GND. Doing this will tend
to improve noise immunity and reduce Icc for the device.
Device Programming
Typical Input Pull-up Characteristic
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu- 0
facturers. Complete programming of the device takes less than a
Input Current (µA)

second. Erasing of the device is transparent to the user, and is done -20
automatically as part of the programming cycle.
-40

-60
0 1.0 2.0 3.0 4.0 5.0

Input Voltage (Volts)

Power-Up Reset
Circuitry within the GAL20XV10 provides a reset signal to all reg- of system power-up, some conditions must be met to provide a valid
isters during power-up. All internal registers will have their Q outputs power-up reset of the GAL20XV10. First, the VCC rise must be
set low after a specified time (tpr, 1µs MAX). As a result, the state monotonic. Second, the clock input must be at static TTL level as
on the registered output pins (if they are enabled) will always be shown in the diagram during power up. The registers will reset
high on power-up, regardless of the programmed polarity of the within a maximum of tpr time. As in normal system operation, avoid
output pins. This feature can greatly simplify state machine design clocking the device until all input and feedback path setup times
by providing a known state on power-up. The timing diagram for have been met. The clock must also meet the minimum pulse width
power-up is shown below. Because of the asynchronous nature requirements.

Vcc (min.)
Vcc

t su

CLK t wl

t pr
INTERNAL REGISTER Internal Register
Q - OUTPUT Reset to Logic "0"

FEEDBACK/EXTERNAL Device Pin

OUTPUT REGISTER Reset to Logic "1"

12
 Specifications GAL20XV10

Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc

1.2 1.2 1.2

PT H->L RISE PT H->L

Normalized Tpd

Normalized Tsu
Normalized Tco
1.1 1.1 1.1
PT L->H FALL PT L->H

1 1 1

0.9 0.9 0.9

0.8 0.8 0.8

4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50

Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)

Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp

1.3 1.3 1.4

PT H->L 1.2 RISE 1.3 PT H->L

1.2
Normalized Tco

Normalized Tsu
Normalized Tpd

1.2
1.1 PT L->H 1.1 FALL PT L->H
1.1
1 1
1
0.9 0.9
0.9
0.8 0.8 0.8

0.7 0.7 0.7

-55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125

Temperature (deg. C) Temperature (deg. C) Temperature (deg. C)

Delta Tpd vs # of Outputs Delta Tco vs # of Outputs

Switching Switching
0 0
Delta Tpd (ns)

Delta Tco (ns)

-0.5 -0.5

-1 -1
RISE RISE
-1.5 -1.5
FALL FALL
-2 -2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10

Number of Outputs Switching Number of Outputs Switching

Delta Tpd vs Output Loading Delta Tco vs Output Loading

12 12

10 RISE 10 RISE
Delta Tco (ns)
Delta Tpd (ns)

8 FALL 8 FALL
6 6

4 4

2 2

0 0

-2 -2
0 50 100 150 200 250 300 0 50 100 150 200 250 300

Output Loading (pF) Output Loading (pF)

13
 Specifications GAL20XV10
Typical AC and DC Characteristic Diagrams

Vol vs Iol Voh vs Ioh Voh vs Ioh

3 5 4.5

2.5
4
4.25
2

Voh (V)

Voh (V)
Vol (V)

3
1.5 4
2
1
3.75
1
0.5

0 0 3.5
0.00 20.00 40.00 60.00 80.00 100.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 0.00 1.00 2.00 3.00 4.00

Iol (mA) Ioh(mA) Ioh(mA)

Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq.

1.20 1.2 1.70

1.60
1.50
Normalized Icc

Normalized Icc
Normalized Icc

1.10 1.1
1.40
1.30
1.00 1 1.20
1.10
1.00
0.90 0.9
0.90
0.80
0.80 0.8 0.70
4.50 4.75 5.00 5.25 5.50 -55 -25 0 25 50 75 100 125 0 25 50 75 100

Supply Voltage (V) Temperature (deg. C) Frequency (MHz)

Delta Icc vs Vin (1 input) Input Clamp (Vik)

10 0

20
8
Delta Icc (mA)

40
Iik (mA)

6
60
4
80

2
100

0 120
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 -2.00 -1.50 -1.00 -0.50 0.00

Vin (V) Vik (V)

14
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