Preliminary

Commercial

PEEL 20V8 -15/-25

CMOS Programmable Electrically Erasable Logic Device
Features
Icc
20mA typical Icc

Compatible with Popular 20V8 Devices

20V8 socket and function compatible
Programs with standard 20V8 JEDEC file
24-pin DIP/SOIC, 28-pin PLCC packages

Development/Programmer Support
Third party software and programmers
ICT PLACE Development Software and
PDS-3 programmer
Automatic programmer translation and
JEDEC file translation software available
for the most popular PAL devices

CMOS Electrically Erasable Technology

Superior factory testing
Reprogrammable in plastic package
Reduces retrofit and development costs
Application Versatility
Replaces random logic
Super-sets standard 24-pin PLDs (PALs)

General Description
The PEEL20V8 is a Programmable Electrically
Erasable Logic (PEEL) device providing an attractive alternative to ordinary PLDs. The PEEL20V8
offers the performance, flexibility, ease-of-design
and production practicality needed by logic designers today. The PEEL20V8 is available in 24-pin DIP
and PLCC packages (see Figure 1) with speeds
ranging from 15ns to 25ns and power consumption
as low as 20mA. EE-reprogrammability provides the
convenience of instant reprogramming for development and a reusable production inventory minimizing the impact of programming changes or errors.
EE-reprogrammability also improves factory testability, thus ensuring the highest quality possible.

The PEEL20V8 is socket and function compatible

with other 20V8 devices. Its architecture allows it to
replace many standard 24-pin PALs. See Figure 2.
ICTs PEEL20V8 can be programmed with any existing 20V8 JEDEC file. Some programmers also
allow the PEEL20V8 to be programmed directly
from PAL 20L8, 20R4, 20R6 and 20R8 JEDEC files.
Additional development and programming support for
the PEEL20V8 is provided by popular third-party programmers and development software. ICT also offers
free PLACE development software and a low-cost
development system (PDS-3).

Pin Configuration (Figure 1)

Block Diagram (Figure 2)

I/CLK

CLK
I

PEEL
"AND"
ARRAY
64 TERMS
X
40 INPUTS

DIP
I/OE

PLCC
3 - 25

MACRO
CELL

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

PEEL 20V8
Functional Description
The PEEL20V8 implements logic functions as sumof-products expressions in a programmableAND/fixed-OR logic array. User-defined functions
are created by programming the connections of input signals into the array. User-configurable output
structures in the form of macrocells further increase
logic flexibility.
Architecture Overview
The PEEL20V8 features fourteen dedicated input
pins and eight I/O pins, which allow a total of up to
20 inputs and 8 outputs for creating logic functions.
At the core of the device is a programmable electrically-erasable AND array which drives a fixed OR
array. With this structure the PEEL20V8 can implement up to 8 sum-of-products logic expressions.
Associated with each of the eight OR functions is a
macrocell which can be independently programmed
to one of up to four different basic configurations:
active-high or active-low registered logic output
(with registered feedback) or active-high or activelow combinatorial logic output (with I/O pin feedback).
Three different device modes: Simple, Complex and
Registered, support various user configurations. In
Simple mode, a macrocell can be configured for
combinatorial function with the output buffer permanently enabled, or the output buffer can be disabled
and the I/O pin used as a dedicated input. In Complex mode a macrocell is configured for combinatorial function with the output buffer enable controlled
by a product term. In Registered mode, a macrocell
can be configured for registered operation with the
register clock and output buffer enable controlled
directly from pins, or can be configured for combinatorial function with the output buffer enable controlled by a product term. In most cases, the device
mode is set automatically by the development software based on the features specified in the design.

64 product terms:
56 product terms (arranged in 8 groups of 7) form
sum-of-product functions for macrocell combinatorial or registered logic
8 product terms (arranged 1 per macrocell) add
an additional product term for macrocell sum-ofproducts functions or I/O pin output enable control
At each input-line/product-term intersection there is
an EEPROM memory cell which determines
whether or not there is a logical connection at that
intersection. Each product term is essentially a 32input AND gate. A product term which is connected
to both the true and complement of an input signal
will always be FALSE and thus will not affect the OR
function that it drives. When all the connections on
a product term are opened, that term will always be
TRUE.
When programming the PEEL20V8, the device programmer first performs a bulk erase to remove the
previous pattern. The erase cycle opens every logical connection in the array. The device is configured
to perform the user-defined function by programming selected connections in the AND array. (Note
that PEEL device programmers automatically program at least one pair of complementary inputs on
unused product terms so that they will have no
effect on the output function.)
Table 1. PEEL20V8/PAL Device Compatibility

The three device modes support designs created

explicitly for the PEEL20V8, as well as designs created originally for popular PAL devices such as the
20R4, 20R8 and 20L8. Table 1 shows the device
mode used to emulate the various PALs. Design
conversion into the 20V8 is accommodated by several programmers which can read the original PAL
JEDEC file and automatically program the 20V8 to
perform the same function.
AND/OR Logic Array
The programmable AND array of the PEEL20V8 is
formed by input lines intersecting product terms. The
input lines and product terms are used as follows:
40 input lines:
24 input lines carry the true and complement of
the signals applied to the 12 dedicated input pins
16 additional lines carry the true and complement
of 8 macrocell feedback signals or inputs from I/O
pins or the clock/OE pins

3 - 26

PAL Architecture

Compatibility

PEEL20V8

Device Mode
14H8

Simple

14L8

Simple

14P8

Simple

16H6

Simple

16L6

Simple

16P6

Simple

18H4

Simple

18L4

Simple

18P4

Simple

20H2

Simple

20L2

Simple

20P2

Simple

20H8

Complex

20L8

Complex

20P8

Complex

20R4

Registered

20R6

Registered

PEEL 20V8
20R8

Registered

20RP4

Registered

20RP6

Registered

20RP8

Registered

Programmable Macrocell
The macrocell provides complete control over the
architecture of each output. The ability to configure
each output independently permits users to tailor
the configuration of the PEEL20V8 to the precise
requirements of their designs.
Macrocell Architecture
Each macrocell consists of an OR function, a D-type
flip-flop, an output polarity selector and a programmable feedback path. Four EEPROM architecture
bits MS0, MS1, OP and RC control the configuration
of each macrocell. Bits MS0 and MS1 are global,
and select between Simple, Complex and Registered mode for the whole device. Bits OP and RC
are local for each macrocell; bit OP controls the
output polarity and bit RC selects between registered and combinatorial operation and also specifies the feedback path. Table 2 shows the architecture bit settings for each possible configuration.
Equivalent circuits for the possible macrocell configurations are illustrated in Figures 3, 4 and 5.
When creating a PEEL device design, the desired
macrocell configuration generally is specified explicitly in the design file. When the design is assembled
or compiled, the macrocell configuration bits are
defined in the last lines of the JEDEC programming
file.

Simple Mode
In Simple mode, all eight product terms feed the OR
array which can generate a purely combinatorial
function for the output pin. The programmable output polarity selector allows active-high or active-low
logic, eliminating the need for external inverters.
For output functions, the buffer can be permanently
enabled. Feedback into the array is available on all
macrocell I/O pins, except for DIP/SOIC pins 18 and
19 (PLCC pins 21 and 23). Figure 6 shows the logic
array of the PEEL20V8 configured in Simple mode.
1 Simple Mode
Active Low Output

VCC

Simple Mode
Active High Output
VCC

Simple Mode
I/O Pin Input

Figure 3. Macrocell Configurations for the Simple

Mode of the PEEL20V8

Table 2. PEEL20V8 Device Mode/Macrocell Architecture Configuration Bits

Config.

Architecture Bits

Mode

Function

MS0

MS1

OP

RC

Polarity

Feedback

Simple

Combinatorial

Active Low

I/O Pin

Simple

Combinatorial

Active High

I/O Pin

Simple

None

None

I/O Pin

Complex

Combinatorial

Active Low

I/O Pin

Complex

Combinatorial

Active High

I/O Pin

Registered

Registered

Active Low

Registered

Registered

Registered

Active High

Registered

Registered

Combinatorial

Active Low

I/O Pin

Registered

Combinatorial

Active High

I/O Pin

3 - 27

PEEL 20V8
Simple mode also provides the option of configuring
an I/O pin as a dedicated input. In this case, the
output buffer is permanently disabled and the I/O
pin feedback is used to bring the input signal from
the pin into the logic array. This option is available
for all I/O pins except pins 18 and 19 (PLCC pins
21 and 23).
Complex Mode
In Complex mode, seven product terms feed the OR
array which can generate a purely combinatorial
function for the output pin. The programmable output polarity selector provides active-high or activelow logic, eliminating the need for external inverters.
1 Complex Mode
Active L ow Output
PRODUCT T ERM

Registered Mode
Active L ow R egistered Output

2 Registered Mode

Active High R egistered Outupt

OE P IN

OE P IN

CLK P IN

Registered Mode
Active L ow Combinatorial Output

PRODUCT T ERM

CLK P IN

Registered Mode
Active High Combinatorial Output

PRODUCT T ERM

Complex Mode
Active High Output

Figure 5. Macrocell Configurations for the Registered Mode of the PEEL20V8

PRODUCT T ERM

for input or bidirectional functions is available on all

I/O pins.
Figure 4. Macrocell Configurations for the Complex Mode of the PEEL20V8
The output buffer is controlled by the eighth product
term, allowing the macrocell to be configured for
input, output or bidirectional functions. Feedback
into the array for input or bidirectional functions is
available on all pins except DIP pins 15 and 22
(PLCC pins 18 and 26). Figure 7 shows the logic
array of the PEEL20V8 configured in Complex
mode.
Registered Mode
Registered mode provides eight product terms to
the OR array for registered functions. The programmable output polarity selector provides active-high
or active-low logic, eliminating the need for external
inverters. (Note, however, that PEEL20V8 registers
power-up reset and so before the first clock arrives
the output at the pin will be low if the user has
selected active-high logic and high if the user has
selected active-low logic.) For registered functions,
the output buffer enable is controlled directly from
the /OE control pin. Feedback into the array comes
from the macrocell register. In Registered mode,
DIP input pins 1 and 13 (PLCC pins 2 and 16) are
permanently allocated as CLK and /OE, respectively. Figure 8 shows the logic array of the
PEEL20V8 configured in Registered mode.

Input and I/O Pin Pull-ups

The input and I/O pins on this device feature pull-up
circuitry. The pull-ups cause input and I/O pins to be
pulled high through nominally 100k ohms.
Design Security
The PEEL20V8 provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The
security bit is set by the PLD programmer, either at
the conclusion of the programming cycle, or as a
separate step after the device has been programmed. Once the security bit has been set, it is
impossible to verify (read) or program the PEEL
until the entire device has first been erased with the
bulk-erase function.
Signature Word
The signature word feature allows a 64-bit code to
be programmed into the PEEL20V8. The code cannot be read back after the security bit has been set.
The signature word can be used to identify the
pattern programmed into the device or to record the
design revision, etc.

Registered mode also provides the option of configuring a macrocell for combinatorial operation, with
seven product terms feeding the OR function.
The programmable output polarity selector provides
active-high or active-low logic. The output buffer enable is controlled by the eighth product term, allowing the macrocell to be configured for input, output
or bidirectional functions. Feedback into the array
3 - 28

PEEL 20V8
I

1
(2)

23

(3)

22

MACRO
CELL
I

(27)

I/O

(26)

3
(4)
21

MACRO
CELL
I

I/O

(25)

4
(5)
20

MACRO
CELL
I

I/O

(24)

5
(6)
19

MACRO
CELL
I

I/O

(23)

6
(7)
18

MACRO
CELL
I

I/O

(21)

7
(9)
17

MACRO
CELL
I

I/O

(20)

8
(10)
16

MACRO
CELL
I

I/O

(19)

9
(11)
15

MACRO
CELL
I

10
(12)

11
(13)

Figure 6. PEEL20V8 Logic Array - Simple Mode

(Pin numbers is for DIP package, PLCC pin numbers shown in parentheses.)

3 - 29

I/O

(18)

14
(17)

13
(16)

PEEL 20V8
I

1
(2)

23

(3)

22

(27)

MACRO
CELL

(26)

MACRO
CELL

(25)

MACRO
CELL

(24)

MACRO
CELL

(23)

MACRO
CELL

(21)

MACRO
CELL

(20)

MACRO
CELL

(19)

MACRO
CELL

(18)

I/O

3
(4)
21

I/O

4
(5)
20

I/O

5
(6)
19

I/O

6
(7)
18

I/O

7
(9)
17

I/O

8
(10)
16

I/O

9
(11)
15

10
14

11

(17)
13

(13)

(16)

(12)

I/O

Figure 7. PEEL20V8 Logic Array - Complex Mode

(Pin numbers is for DIP and package, PLCC pin numbers shown in parentheses.)

3 - 30

PEEL 20V8
CLK

1
(2)

23

(3)

(27)

22

MACRO
CELL

(26)

MACRO
CELL

(25)

MACRO
CELL

(24)

MACRO
CELL

(23)

MACRO
CELL

(21)

MACRO
CELL

(20)

MACRO
CELL

(19)

MACRO
CELL

(18)

I/O

3
(4)
21

I/O

4
(5)
20

I/O

5
(6)
19

I/O

6
(7)
18

I/O

7
(9)
17

I/O

8
(10)
16

I/O

9
(11)
15

I/O

10
(12)

14
(17)

11
(13)

13
(16)

Figure 8. PEEL20V8 Logic Array - Registered Mode

(Pin numbers is for DIP and package, PLCC pin numbers shown in parentheses.)

3 - 31

I
OE

PEEL 20V8
This device has been designed and tested for the
specified operating ranges. Proper operation outside
of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage.

Absolute Maximum Ratings

Symbol Parameter

Conditions

Rating

VCC

Supply Voltage

Relative to Ground

-0.5 to + 7.0

VI, VO

Voltage Applied to Any Pin2

Relative to Ground1

-0.5 to VCC + 0.6

IO

Output Current

Per pin (IOL, IOH)

25

mA

TST

Storage Temperature

-65 to +150

TLT

Lead Temperature

+300

Soldering 10 seconds

Unit

Operating Ranges
Symbol Parameter

Conditions

Min

Max

Unit

VCC

Supply Voltage

Commercial

4.75

5.25

TA

Ambient Temperature

Commercial

+70

TR

Clock Rise Time

See Note 3

20

ns

TF

Clock Fall Time

See Note 3

20

ns

TRVCC

VCC Rise Time

See Note 3

250

ms

Max

Unit

D.C. Electrical Characteristics Over the operating range

Symbol Parameter

Conditions

Min

VOH

Output HIGH Voltage

VCC = Min, IOH = -4.0mA

2.4

VOL

Output LOW Voltage

VCC = Min, IOL = 16mA

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

IIL

Input and I/O Leakage Current

LOW

VCC = Max, VIN = GND, I/O = High Z

IIH

Input and I/O Leakage Current

HIGH

VCC = Max, VIN = VCC, I/O = High Z

ISC

Output Short Circuit Current

VCC = 5V, VO = 0.5V9, TA = 25C

ICC10

VCC Current

VIN = 0V or 3V
f = 25MHz
All outputs disabled4

CIN7
COUT

Input Capacitance
7

Output Capacitance

TA = 25C, VCC = 5.0V

@ f = 1MHz

3 - 32

V
0.5

2.0

VCC + 0.3

-0.3

0.8

-100

10

-30

-150

mA

-15

30 (typ)

35

25

20 (typ)

25

mA

pF

12

pF

PEEL 20V8
A.C. Electrical Characteristics

Over the Operating Range

-15

Symbol Parameter
tPD

Input5 to non-registered output

-25

Unit

Min

Max

Min

Max

15

25

ns

tOE

Input to output enable

15

20

ns

tOD

Input5 to output disable6

15

20

ns

tCO1

Clock to output

12

ns

tCO2

Clock to comb. output delay via

internal registered feedback

25

35

ns

tCF

Clock to Feedback

10

ns

tSC

Input5 or feedback setup to clock

tHC

8, 11

Input hold after clock

8

10

12

15

ns

ns

tCL, tCH

Clock low time, clock high time

12

ns

tCP

Min clock period Ext (tSC + tCO1)

22

27

ns

50

40

MHz

45.5

37

MHz

62.5

41.6

MHz

15

25

ns

fMAX1

Internal Feedback (1/tSC+tCF)

fMAX2

External Feedback (1/tCP)12

12

12

fMAX3

No Feedback (1/tCL+tCH)

tAW

Asynchronous Reset pulse width

tAP

Input5 to Asynchronous Reset

15

25

ns

tAR

Asynchronous Reset recovery time

15

25

ns

tRESET

Power-on reset time for registers in

clear state

Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs

Notes
1. Minimum DC input is -0.5V, however inputs may
undershoot to -2.0V for periods less than 20ns.
2. VI and VO are not specified for program/verify operation.
3. Test points for Clock and VCC in tR, tF are referenced at
10% and 90% levels.
4. I/O pins are 0V or 3V.
5. Input refers to an Input pin signal.
6. tOE is measured from input transition to VREF 0.1V,
tOD is measured from input transition to VOH - 0.1V or
VOL + 0.1V; VREF = VL see test loads in Section 6 of
the1995/1996 Data Book.
7. Capacitances are tested on a sample basis.

8. Test conditions assume: signal transition times of 3ns

or less from the 10% and 90% points, timing reference
levels of 1.5V (unless otherwise specified).
9. Test one output at a time for a duration of less than 1
sec.
10. ICC for a typical application: This parameter is tested
with the device programmed as an 8-bit Counter.
11. PEEL Device test loads are specified in Section 6 of
the 1995/1996 Data Book.
12. Parameters are not 100% tested. Specifications are
based on initial characterization and are tested after
any design or process modification which may affect
operational frequency.

3 - 33

PEEL 20V8

Ordering Information
PART NUMBER
PEEL20V8P-15
PEEL20V8J-15
PEEL20V8P-25
PEEL20V8J-25

SPEED
15ns
15ns
25ns
25ns

TEMPERATURE
C
C
C
C

PACKAGE
P24
J28
P24
J28

Part Number

Device

Suffix

PEEL20V8P-25

Package
P = Plastic 300mil DIP
J = Plastic (J) Leaded Chip Carrier (PLCC)

3 - 34

Speed
-15 = 15ns tpd
-25 = 25ns tpd