Unit 4 Electrical Principles

Index

Introduction

Unit 4 - HDL Languages

4.1. Programmable Logic Devices

4.1.1. Types

4.1.2. Characteristics

4.1.3. Manufacturers

4.1.4. Steps for designing with CPLDs

4.2. National combi circuit programming with HDL

4.2.1. By schematic capture

4.2.2. By truth table

4.2.3. By boolean equations

4.2.4. By behavior description

4.3. Programming sequential circuits with HDL

4.3.1. By schematic capture

4.3.2. By truth table

4.3.3. By boolean equations

4.3.4. By behavior description

4.3.5. By status table

4.3.6. By transition diagram
Conclusion
Consulted Sources
UNIT 4 - HDL LANGUAGES

4.1. PROGRAMMABLE LOGIC DEVICES

A Programmable Logic Device (PLD) is any logic device whose function is

specified by the user, after the device is manufactured. They are used to replace
SSI and MSI logic, thereby saving on cost and time in design. Among them, we find:

Programmable Logic Arrays

A Programmable Logic Array (PLA) is a PLD circuit that can be programmed to
execute a complex function. They are usually used to implement logic
combinational, but some PLAs can be used to implement logical designs
sequential. The PLA is a solution with a single integrated circuit to many problems
logical, which can have many inputs and many outputs.
It is a combinational two-level AND-OR solution that can be programmed.
to carry out any logical expansion of sum of products, subject to the limitations
of the product. These limitations are the number of inputs (n), the number of outputs (m) and
the number of product terms (p). It
It can be described as a 'PLA n x m with p product terms'. Therefore, its utility is
limited to functions that can be expressed as a sum of products using p or
fewer product terms.

A special case of PLA is that of one of the most popular PLDs, the PAL (Programmable Array Logic)
ArrayProgramable). In this device, only the part corresponding to the
AND, while the OR is fixed.

Other programmable logic devices of interest are:

ROM, read-only memory
PROM, programmable read-only memory
EPROM, erasable programmable read-only memory
EEPROM, electrically erasable programmable read-only memory
RAM, random access memory
SRAM, static random access memory
DRAM, dynamic random access memory

4.1.1. TYPES

ASICS
Since the late 1970s, digital electronic equipment has been using circuits.
Integrated (IC or
Fixed-function logic chips, produced in small or medium scale integration
(SSI, MSI).
For the implementation of very complex applications, which require a great
number of fixed function circuits, making it more convenient to integrate them into a
custom-made device, which are called: ASICS,
Application Specific Integrated Circuits.
custom circuits).
Among the advantages of using ASICs, we can mention that: They save
space, they reduce the
number of devices, have lower cost, reduce assembly time, low
power consumption, lower heating, ease of verification (quality control)
and better reliability.
ASICs can be classified by their manufacturing technology into four categories:
Gate Arrays, Standard Cells, Full Custom, and Programmable Logic

Classification of ASICs

The technologies of Gate Arrays, Standard Cells, and Full Custom, are
aimed at high-volume industrial production and require equipment
specialized for ASIC manufacturing.
On the other hand, with Programmable Logic it is possible to design and implement functions.
from a single circuit using only one computer, a programmer and
Electronic Design Automation software (Electronic Design Assistant).

PLD
A programmable logic device (PLD) is an integrated circuit whose structure
Final logic is directly configured by the user, without the need to carry out
no manufacturing process.
Peggy Aycinena of the electronic magazine Integrated System Design asserts that the
programmable logic devices are the wave of the future because they present the following
features: 10,000 gates in 1 in2, configurable inputs and outputs
reprogrammable and remotely programmable for different functions.
PLDs facilitate the design process and reduce development time when they are
require prototypes or low-scale production, as the entire process can be
carry out with the help of a personal computer, application programs and the
programmers who are currently available at a low cost.

The different types of programmable logic devices that exist today can
classified by their technology or their capacity (Figure 2) such as:
Simple Programmable Logic Device SPLDs.
• Complex Programmable Logic Devices CPLDs.
Field Programmable Gate Array devices FPGAs.
Field Programmable Inter Connect FPICs.

From the previous classification in this document, we will only focus, as examples, on
the Simplex Programmable Logic Devices (SPLDs).
The SPLDs consist of an arrangement of AND gates, followed by another.
gate arrangement
OR, with one or both programmable arrays. Some include Flip-Flops.

And Or arrangement of a SPLD.

In turn, SPLDs can be classified according to their internal structure into:

PAL Programmable Array Logic, VANTIS.

GAL Generic Array Logic, Lattice Semiconductor.

PLA Programmable Logic Array.

PLD Programmable Logic Device.

Classification of SPLDs
Of these types of SPLDs, the GAL stands out for its low price and versatility.
we will describe in the following point.

GAL
GAL (GenericArrayLogic), in Spanish Generic Logical Array, are a type of circuit
integrated, trademarked by Lattice Semiconductor, which has been designed with the
purpose of replacing most of the PALs, while maintaining compatibility with their
terminals.
The GAL is basically made up of a reprogrammable AND matrix and a fixed OR matrix.
with programmable output and/or input configuration.

Basic structure of a GAL

As an example of the features offered by this type of device, to

The most relevant specifications of the GAL16V8 circuit are listed below.
Lattice Semiconductor brand.
250 MHz
3.5 ns maximum propagation time.
• 2.5 ns maximum propagation time from clock input to output data.
Reprogrammable Cells.
Vcc = 5 Volts ± 5%
Current consumption 90 mA.
Speed in deletion < 100 ms.
20 years of data retention.
8 Output LogicMacroCells (OLMC)
Programmable output polarity.
Operating temperature from 0 to 75 °C.
In the GAL16V8, the terminals have the following functions: Terminal 1 is the input.
From the CLK, terminals 2 to 9 are eight fixed Inputs, terminal 10 is GND, terminal
11 as a Control Input O/E (Output/Enable), from 12 to 19 eight terminals
programables OLMC and terminal 20 of VCC.

Distribution of terminals of a GAL16V8

The terminals from 12 to 19 corresponding to the OLMC (Output Logic Macrocell) can
to be programmed to work as inputs and/or outputs, and in case they are used as
outputs can be combinational or registered (Flip-Flops), which gives it the
versatility of being programmed in different ways and for different requirements.

Internal configuration of the OLMC of a GAL16V8.

The programming of PLDs is generally carried out through programs for

specialized applications being the two most commonly used programming strategies
the schematic capture and the hardware description language (HDL).
The great advantage of these tools is to make designs on the computer,
where errors are easily detectable and correctable.

PLA and PAL

The following diagram shows the structure of a 2-input, 1-output PLA (not real)
which will help us describe its operation. A typical commercial product can
to have up to 20 inputs and 10 outputs. The AND-OR solution can be observed that
implement any boolean expression in minterms. Only the AND part can be
programmed in this case. To program it, the fuses that must be burned need to be replaced.
remain open. In the figure it is as provided by the manufacturer

Here is the previous PLA programmed to perform a boolean function.

in mini-terms:

To prevent the diagrams from becoming too large, a system is used to

Abbreviated notation, referred to as a fuse diagram. Here each door seems to have a
Single input although in reality the NAND gates have 4 and the OR gates have 3.

This figure shows a more complex PLA circuit. Here it can be programmed.
both the AND part and the OR part:

This is the fuse diagram of a commercial device: PAL10H8ANC,

To program it, it is necessary to indicate what the 'coordinates' of the fuses are.
to burn.

4.1.2. CHARACTERISTICS

Type
ASIC | *They are user-defined devices.* They can contain analog functions.
digitals and combinatorial.
PROM | *They are read-only programmable memories.*They are logical.*They are used for
encode the input combinations into output functions.
PAL | *They are programmable array devices.* They are the programmable devices by
user plus employees.
GAL | *GALs are generic logic array devices.* They are electronic.
erasable.
PLA | *They are programmable logic arrays.* They have greater flexibility than others.
devices.
FPGA | *They are fields of programmable gate arrays.* They contain multiple levels
of logic.

4.1.3. MANUFACTURERS

Some manufacturers of FPGAs are:

Actel (www.actel.com): It is a manufacturer of FPGAs and programmable logic solutions.

Altera Corp. (www.altera.com): It is a leading manufacturer of logic devices.

programmable.

AtmelCorp. (www.atmel.com): It is a semiconductor manufacturer.

Chip Express (www.chipexress.com)

Cypress Sem. (www.cypress.com): It is a company dedicated to design
semiconductor.

Lattice Sem. (www.latticesemi.com)

Quicklogic Corp. (www.quicklogic.com): They are suppliers of gate arrays.
field programmable devices, with devices programmed only once.

Xilinx Inc. (www.xilinx.com): Supplier of programmable logic devices.

4.1.4. STEPS FOR DESIGNING WITH PLDs

Stages of design and implementation of a digital system using PLDs.

Specifications

Connection List Verification

Design description

Functional Simulation

List of connections

Compilation and/or Synthesis

Temporal Simulation.

List of connections
Implementation

Delay analysis.

List of connections

Circuit test.
Circuit programming.

4.2. PROGRAMMING OF NATIONAL COMBI CIRCUITS WITH HDL

4.2.1. BY SCHEMATIC CAPTURE

Schematic Capture is understood as the process of description, through a drawing, of
an electric circuit, in which the different components of the circuit are represented and
Only interconnections are made between them.

There are several programs with the Schematic Capture application such as 'Schematic'.
the IspStarter from Lattice Semiconductor or "Foundation" from XILINX among others.

This technique allows to virtually simulate the circuit on the computer and verify its
operation before its manufacture or implementation in a PLD, thus reducing the
design cycle and the time to obtain a product.

Schematic Capture Program.

The four basic components of schematic capture are: Symbols, Connectors,
Labels and Input and/or Output Ports.

Using the IspStarter program from Lattice Semiconductor, the first step in the process
to obtain the circuit is precisely the schematic capture where a is generated
.SCH file extension, then it goes to the linking process where
It is validated whether the components are allowed on the selected device, as well as if the
the device has the ability to integrate the required elements (FitDesign). Also
it is possible to perform the simulation before obtaining the final circuit with the intention of
ensure that this meets the requested requirements.

During the linking process, a report file with the .REP extension is generated that indicates us,
among other things, the assignment of terminals (Pin Out) and the JEDEC file with which
We will carry out the programming of the circuit through a programmer.

Diagram of the digital design process through schematic capture.

The disadvantage of schematic capture is that in the design of large circuits it is not
It is possible to understand them due to the fact that there are too many components and interconnections in the

screen, for those cases it is advisable to use description languages

dehardware.

4.2.2. BY TRUTH TABLE

To clarify the process, a specific example is necessary, the specific truth table.
a combinational circuit with two inputs and two outputs. The Boolean functions
they can be expressed as a sum of minimal terms.

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The design of combinational circuits starts from the problem specification and culminates in
a logical circuit diagram or a set of Boolean functions from the
What can be obtained from the logical diagram? The procedure involves the following steps:
From the circuit specification, deduce the required number of inputs and outputs;
assign a symbol to each one.
Deduce the truth table that defines the required relationship between the inputs and the outputs.
outputs.
Obtain the simplified boolean functions for each output based on variables
as an entry.
Draw the logic diagram and verify that the design is correct.
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4.2.3. FOR BOOLEAN EQUATIONS

If it is necessary to reduce the function that the circuit performs. This process starts from the diagram.
logical given and culminates in a set of BOOLEAN functions, a truth table or
a possible explanation of how the circuit works. If the logical diagram is analyzed
accompanied by a function name or an explanation of what it is supposed to
thus, the analysis problem reduces to a verification of the planned function. The
analysis is carried out manually by finding the BOOLEAN functions or the TABLE
REALLY, or by using a computer simulation program.
The first step of the analysis is to ensure that the given circuit is
combinational and not sequential. The diagram of the combinational circuit has gates.
logic without feedback paths or memory elements. A path of
Feedback is an output connection from a gate to the input of a
second gate that is part of the entrance to the first gate.
The analysis of the combinational circuit illustrated in the figure is a circuit that has three
binary inputs A, B, and C and two binary outputs F1 and F2. The outputs of various
gates that are solely a function of input variables are T1 and T2. The output
F2 is easily deduced from the input variables. The BOOLEAN functions of this
output are:

F2 = AB + AC + BC
F1= A+B+C
T2= ABC

4.2.4. BY BEHAVIOR DESCRIPTION

Very High Speed Integrated Circuit Hardware Description Language (VHDL)

VHDL is the acronym that represents the combination of VHSIC and HDL, where VHSIC is
the acronym Very High Speed Integrated Circuit and HDL is in turn the acronym for
Hardware Description Language.

It is a language defined by the IEEE (Institute of Electrical and Electronics Engineers)

(ANSI/IEEE 1076-1993) used by engineers to describe digital circuits. Others
Methods for designing circuits include schematic capture (with CAD tools) and the
block diagrams, but these are not practical in complex designs. Other languages
For the same purpose are Verilog and ABEL.

Although it can be used generally to describe any circuit, it is used

mainly for programming PLD (Programmable Logic Device)
Programmable, FPGA (Field Programmable Gate Array), ASIC and similar

Within VHDL there are several ways we can design the same circuit and it is
The designer's task is to choose the most appropriate one.

* Functional: We describe the way the circuit behaves. This is the way that
It resembles software languages since the description is sequential.
These sequential statements are found within the so-called processes.
in VHDL. The processes are executed in parallel with each other, and in parallel with
concurrent signal assignments and with instances to other components.
 Dataflow: describes concurrent (in parallel) assignments of signals.

Structural: the circuit is described with instances of components. These instances

they form a design of higher hierarchy by connecting the ports of these instances with the
internal signals of the circuit, or with ports from a higher hierarchy circuit.

Mixed: a combination of all or some of the above.

In VHDL there are also methodical ways for designing state machines,
digital filters, test benches etc.

4.3. Programming of sequential circuits with HDL

Sequential switching circuits have the property that the output not only
It depends on the current input, but also on the sequence of previous inputs.

It is the acronym for Programmable Logic Design of programmable logic devices. These
integrated circuits allow for the generation within them of functions that we do not have
in Commercial I.C. (decoders, comparators, adders, etc). The PLDs
they can replace application-specific integrated circuits in the design of
digital circuits. A single PLD is functionally equivalent to devices that have
from 5 to 10,000 logic gates.

These devices are based on bipolar transistors, special transistors that

when a strong current flows, they stop conducting, but they can return to
drive by applying a potential difference in the circuit.

4.3.1. BY SCHEMATIC CAPTURE

Schematic capture programs are applications created to sketch circuits.

electronics and export the schematics as netlist files; which satisfy the
syntax of some particular simulation core.
Within this group of programs, which delegate the task of linking to the user
netlist files generated with the simulation core are: XCircuit 11, and
gschem 12; belonging to the Open Circuit Design groups and
gEDA, respectively. The main feature of both programs is that they can
generate high-quality circuit drawings, due to the technology used in its
implementation: the Postscript language for diagram description. However,
a slight difference can be appreciated between these two applications, which could help to
discriminate between one and the other. On one hand, the author of gschem acknowledges
that XCircuit produces better graphic outputs; on the other hand, gschem is more oriented
the design of circuits that to quality drawings in itself, which is appreciated in its
functionality. Unfortunately, the downside of programs of this type is the fact that
having to explicitly link the simulation core; which increases the curve of
learning of users coming from more friendly environments

4.3.2. BY TRUTH TABLE

The truth table is a tool used for the simplification of digital circuits to
through its boolean equation.
Truth tables can have many columns, but all tables work in
the same way.
There is always an output column (the last column on the right) that represents
the result of all possible combinations of the inputs.
The total number of columns in a truth table is the sum of the entries plus
1 (the output column).

The number of rows in the truth table is the number of combinations that can be made
achieve with the entries and it is equal to 2n, where n is the number of columns in the table
truth (not considering the output column)
Example: in the following truth table there are 3 input columns, then there will be:
23 = 8 combinations (8 rows)
A circuit with 3 input switches (with binary states '0' or '1') will have 8
possible combinations. The result (the output column) being determined by the state
from the input switches.

4.3.3. BY BOOLEAN EQUATIONS

We know the Real Numbers very well, as well as all the defined operations.
in him. We are used to working with them since we were little, that's why this type of
Equations seem intuitive and simple to us, even if we do not understand what they mean.
the variables used. We have said that digital circuits work with numbers, and that
these numbers are expressed in binary. We will see later how with a set of
Equations can describe what a circuit does, which transforms the numbers from the
input and takes them out through the exit.
However, since these numbers are expressed in binary, the variables and
the numbers used ARE NOT REAL.
To describe a digital circuit we will use equations. To describe a digital circuit
we will use mathematical equations. However, these equations have variables and
numbers that are NOT REAL, so we cannot apply the same properties
and operations that we know. We need to use new operations and new
properties, defined in BOOLEAN ALGEBRA.
Therefore, we are going to work with equations that we are NOT used to.
They are very simple, but at first they may seem unintuitive. In this chapter
we will learn to work with them.

The operations of Boolean Algebra

In Boolean Algebra, there are two operations, denoted by the symbols + and ( - ) _ but
that have nothing to do with the operations we all know of addition and
product!! Don’t confuse them!!!! The + and the _ of Boolean Algebra apply to bits,
that is, to numbers that can only be '0' or '1'.
The operation +
This operation is defined as follows:
0+0=0
0+1=1
1+0=1
1+1=1
The first three operations seem obvious to us, they are the same as the sum that
we know, however the expression 1 + 1 = 1 may seem shocking to us. But not
I had been told all my life that 1+1=2??, we may be wondering. Yes, but there is
it is worth remembering that here we are using another operation that is NOT ADDITION, the
we denote with the same symbol '+', but it's not a normal sum!! It needs to be changed
chip
Now we are with Boolean Algebra!!

4.3.4. BY BEHAVIOR DESCRIPTION

Behavioral VHDL description.- This is perhaps the most important stage of

design, as key decisions are made in it for the final outcome.
The method is clarified with an example, in which the application of has also been sought
the criteria of hierarchy, modularity, and regularity. To this end, it is intended that all of the
steps of the sequence are the same, when this is possible. The following were also followed
recommendations not to use auxiliary logic in clock signals (all changes of the
systems are produced synchronized with the clock signal which is unique for all
Flip Flops.
Synthesis.- The division of the circuit into a part is already present in the initial description.
of control and a part of data. Therefore, the synthesis will consist of moving from the
description of behavior to a description of structure (and behavior) that
consider the stated requirements.
At this stage, the choice of the type of logic to use and the strategy of
clock, this can be appreciated in the example that consists of a control circuit for a
Successive approximation A/D converter. Behavior.
In a specification of this type, we state what function the system fulfills.

4.3.5. BY STATUS TABLE

A circuit whose output depends not only on the input combination but also on the
The history of the previous entries is called Sequential Circuit. The history of the
previous entries at any given moment are summarized in the state of the circuit,
which is expressed in a set of state variables.
The sequential circuit must be able to maintain its state for some time, in order to
It becomes necessary to use memory devices. Memory devices
used in sequential circuits can be as simple as a simple delay.
(inclusive, the natural delay associated with logic gates can be used) or so
complexes like a complete memory circuit called a bistable multivibrator or
Flip Flop.
As can be seen then, in sequential circuits there is a factor that does not
I had considered in the combinational aspects, said factor is time. In fact, the
sequential circuits are classified according to how they handle time in
synchronous sequential circuits and asynchronous sequential circuits.
In an asynchronous sequential circuit, state changes occur at the natural rhythm.
marked by the delays associated with the logic gates used in their
implementation, that is, these circuits do not use special memory elements, because
they make use of their own delays (propagation times) of the logic gates
used in them. This way of operating can cause some problems of
operation, since these natural delays are not under the control of the designer and
furthermore, they are not identical in each logic gate.
Synchronous sequential circuits only allow a state change at the instants
marked by a synchronization signal of the oscillator type called clock. With this, it
they can avoid the problems that asynchronous circuits have caused by changes
of state not uniform throughout the circuit.

4.3.6. BY TRANSITION DIAGRAM

Draw the state transition diagram and output production, the tables of
transition and the logical expression of the functions f and g for the sequential circuit of the
figure. Note that there is now feedback from the output and consequently to the
Input calculates functions of x(t) and Q(t) but Q(t) comes from the values of D in (t-
If the D flip-flop is triggered on rising edges, draw the temporal evolution of the signal in Q
when the input x(t) and the clock Ck show the following signals:
Consulted Sources

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http://aristotelesanato.blogspot.com/2008_01_01_archive.html
http://electronicaintegrada.blogspot.com/2008/02/cpld-verilog.html
http://en.wikipedia.org/wiki/Programmable_logic_device
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