Dr \ Marwa

Logic 2
Report Of :
Programmable Logic Devices

1
prepared by \ Zyad Abdallah Abd-Ellhamid

Introduction :
An IC that contains large numbers of gates, flip-flops, etc. that can be configured
by

the user to perform different functions is called a Programmable Logic Device

(PLD).

The internal logic gates and/or connections of PLDs can be changed/configured

by a

programming process.

One of the simplest programming technologies is to use fuses. In the original

state of

the device, all the fuses are intact.

Programming the device involves blowing those fuses along the paths that must
be

removed in order to obtain the particular configuration of the desired logic

function.

PLDs are typically built with an array of AND gates (AND-array) and an array of

OR gates (OR-array).

Advantages of PLDs:
Problems of using standard ICs:

2
Problems of using standard ICs in logic design are that they require hundreds or

thousands of these ICs, considerable amount of circuit board space, a great deal

of

time and cost in inserting, soldering, and testing. Also require keeping a
significant

inventory of ICs.

Advantages of using PLDs:

Advantages of using PLDs are less board space, faster, lower power
requirements

(i.e., smaller power supplies), less costly assembly processes, higher reliability
(fewer

ICs and circuit connections means easier troubleshooting), and availability of

design

software.

There are three fundamental types of standard PLDs: PROM, PAL, and PLA.

A fourth type of PLD, which is discussed later, is the Complex Programmable

Logic

Device (CPLD), e.g., Field Programmable Gate Array (FPGA).

A typical PLD may have hundreds to millions of gates.

In order to show the internal logic diagram for such technologies in a concise
form, it

is necessary to have special symbols for array logic.

3
Figure shows the conventional and array logic symbols for a multiple input AND
and

a multiple input OR gate.

Types of PLDs:
The three fundamental types of PLDs differ in the placement of programmable
connections in the AND-OR arrays. Figure shows the locations of the
programmable connections for the three types.

4
• The PROM (Programmable Read Only Memory) has a fixed AND array

(constructed as a decoder) and programmable connections for the output OR

gates

array. The PROM implements Boolean functions in sum-of-minterms form.

• The PAL (Programmable Array Logic) device has a programmable AND array
and fixed connections for the OR array.

• The PLA (Programmable Logic Array) has programmable connections for both

AND and OR arrays. So it is the most flexible type of PLD.

The ROM (Read Only Memory) or PROM (Programmable Read Only

Memory) :

The input lines to the AND array are hard-wired and the output lines to the OR
array are programmable.

Each AND gate generates one of the possible AND products (i.e., minterms).

In the previous lesson, you have learnt how to implement a digital circuit using
ROM.

The PLA (Programmable Logic Array):

In PLAs, instead of using a decoder as in PROMs, a number (k) of AND gates is

used where k < 2n

, (n is the number of inputs).

5
Each of the AND gates can be programmed to generate a product term of the
input variables and does not generate all the minterms as in the ROM.

The AND and OR gates inside the PLA are initially fabricated with the links
(fuses)

among them.

The specific Boolean functions are implemented in sum of products form by

opening appropriate links and leaving the desired connections.

A block diagram of the PLA is shown in the figure. It consists of n inputs, m

outputs,

and k product terms

Architecture :

A programmable
logic device (PLD) is an electronic component used to build reconfigurable digital
circuits. Unlike digital logic constructed using discrete logic gates with fixed
functions, the function of a PLD is undefined at the time of manufacture. Before

6
the PLD can be used in a circuit it must be programmed to implement the desired
function.[1] Compared to fixed logic devices, programmable logic devices
simplify the design of complex logic and may offer superior performance.[2]
Unlike for microprocessors, programming a PLD changes the connections made
between the gates in the device.

PLDs can broadly be categorised into, in increasing order of complexity, Simple

Programmable Logic Devices (SPLDs), comprising programmable array logic,
programmable logic array and generic array logic; Complex Programmable Logic
Devices (CPLDs); and Field-Programmable Gate Arrays (FPGAs).

The PAL (Programmable Array Logic):

The PAL device is a PLD with a fixed OR array and a programmable AND array.

As only AND gates are programmable, the PAL device is easier to program but
it is not as flexible as the PLA.

Complex Programmable Logic Devices (CPLDs):

7
A CPLD contains a bunch of PLD blocks whose inputs and outputs are
connected

together by a global interconnection matrix.

Thus a CPLD has two levels of programmability: each PLD block can be
programmed, and then the interconnections between the PLDs can be
programmed.

Field Programmable Gate Arrays (FPGAs):

The FPGA consists of 3 main structures:

1. Programmable logic structure, 2.

Programmable routing structure, and

3. Programmable Input/Output (I/O).

8
1. Programmable logic structure

The programmable logic structure FPGA consists of a 2-dimensional array of

configurable logic blocks (CLBs).

2. Programmable routing structure

To allow for flexible interconnection of CLBs, FPGAs have 3 programmable

routing resources:

1. Vertical and horizontal routing channels which consist of different length wires
that can be connected together if needed. These channel run vertically and
horizontally between columns and rows of CLBs as shown in the Figure. 2.
Connection boxes, which are a set of programmable links that can connect input

9
and output pins of the CLBs to wires of the vertical or the horizontal routing
channels.

3. Switch boxes, located at the intersection of the vertical and horizontal

channels.

These are a set of programmable links that can connect wire segments in the

horizontal and vertical channels. (see animation in authorware version)

3. Programmable I/O

These are mainly buffers that can be configured either as input buffers, output
buffers

or input/output buffers.

They allow the pins of the FPGA chip to function either as input pins, output pins
or

input/output pins.

10
 ‫‪Team names:‬‬
‫زياد عبدهللا عبدالحميد عبدالرحمن‬
‫زياد حسام‬
‫ديموند‬
‫سلمى محمد فرغلي‬
‫خلود حسين‬
‫مريم محمد‬

‫‪11‬‬
12