Faculty of Electrical and Electronic Engineering

BEJ20701 ELECTRONIC ENGINEERING LABORATORY 1

Group
No. Student’s Name Matric. No. Section
No.
1. PHAVITTRA A/P YOORTHTHERAN DE200027 2 2

2. MOHAMAD YASIN BIN ABDUL KAREEM CE210237

3. MAHAD ABDIRAHMAN AHMED BE190022

Digital Analog
Experiment No. 4
Electronics* Electronics*
Lecturer’s Name: DR. NURMIZA BINTI OTHMAN ✓
*Tick  where relevant

Lab Report Assessment Percentage Student 1 Student 2 Student 3

(Cognitive - 20%)
Prelab: (Individual) 3%
Data & Result 5%
Analysis & Discussion 10%
Conclusion 2%
Total

Lab Work Assessment Percentage Student 1 Student 2 Student 3

(Pyschomotor - 25%)
Demonstration & Operational 10%
Organisation 10%
Communication skills 5%
Total

Affective (5%) Percentage Student 1 Student 2 Student 3

Ethics 2.5%
Professionalism 2.5%
Total
fiO'

•• «ms‹a » <e eeco•A ino•i o*ue sa•o 9=›« • °"••›•e '•• °é•i

* av;iq setup ubic.

O ( 1 D i 0

Scanned with CamScanner

No:

a lo9i *ai \ i,p + ¥o 4 \og\c o a»\•vt 7es•\‹ in a \ogi‹ o ouy>•¥ +°

au^^ + °•9 * \h » ex¥«no I \npu¥ \s Removed

Scanned with CamScanner

Scanned with CamScanner
MOHAMAD YASIN BIN ABDUL KAREEM

CE210237

Prelab 4

1. Concept of a "latch" circuit is important to creating memory devices. In 1st NAND gate, as Q and S'
inputs are 1, Q=0(RESET state). When S=R=1, both Q and Q' becomes 1 which is not allowed. So, the
input condition is prohibited. A Gated SR latch is a SR latch with enable input which works when enable
is 1 and retain the previous state when enable is 0.

2. Truth table
S’ R’ Q Q’

1 1 Q Q’

0 1 1 0

1 0 0 1

0 0 1 1

3. Logic circuit figure 1

1. The NOR LATCH is where S and R stand for set and reset. It can be constructed from a pair of cross-
coupled NOR logic gates. The stored bit is present on the output marked Q. While the S and R inputs
are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q.
If S (Set) is pulsed highwhile R (Reset) is held low, then the Q output is forced high, and stays high
when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced
low, and stays low when R returns to low.

2. Truth table
S R Q Q’

0 0 Q Q’

0 1 0 1

1 0 1 0

1 1 0 0

3. Logic circuit figure 3

1. An edge triggered flip-flop is a modification to the latch which allows the state to only change during a
small period of time when the clock pulse is changing from 0 to 1. It is said to trigger on the edge ofthe
clock pulse, and thus is called an edge-triggered flip-flop. The flip-flop can be triggered by a raising edge
(0->1, or positive edge trigger) or falling edge (1->0, or negative edge trigger). All flip-flops in this text will
be positive edgetrigger.

2. Truth table
S R Q Q’

0 0 0 1

0 1 0 1

1 0 1 0

1 1 ∞ ∞

3. Logic circuit
1. The J-K flip-flop is versatile and is a widely used type of flip-flop. The J and K designations for the
inputs have no known significance except that they are adjacent letters in the alphabet. The function
of J-K flip-flop is identical to that of the S-R flip-flop in the SET, RESET and no-change conditions
of operation. The difference is that the J-K flip-flop has no invalid state as does the S-R flip-flop. The
input mark J is for set and the input mark K is for reset. When both inputs J and K are equal to 1, the
flip flop switches to its complement state, that is, if Q = 1, it switches to Q = 0 and vice versa. A J-K
flip-flop constructed with two crossed coupled NOR gates and two AND gates. Output Q is ANDed
with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1.
Similarly output Q' is ANDed with J and CP inputs so that the flip is set with a clock pulse only when
Q' was previously 1. When both J and K are 1, the input pulse is transmitted through one AND gate
only; the one whose input is connected to the flip-flop output that is presently equal to 1. Thus if Q
= 1, the output of the upper AND gate becomes 1 upon application of the clock pulse and the flip-flop
is cleared. If Q' = 1, the output of the lower of the lower AND gate becomes 1 and the flip-flop is set.
In either case the output of the flip-flop is complemented. It is very important to realize that because
of the feedback connection in the JK flip-flop, a CP pulse that remains in the 1 state while both J and
K are equal to 1 will cause the output to complement again and repeat complementing until the pulse
goes back to 0. To avoid this undesirable operation, the clock pulse must have a time duration that is
shorter than the propegation delay time of the flip-flop.
2. Truth table

3. Logic circuit
Scanned with CamScanner
Scanned with CamScanner
 Faculty of Electrical and Electronic Page 4/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

RESULTS (PART 1)
 Faculty of Electrical and Electronic Page 5/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

Figure 2. Timing diagram with initial Input Q set to low.

 Faculty of Electrical and Electronic Page 6/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

DISCUSSION (PART 1)
Discuss the observation made from your results. Explain the term “Illegal input” for NAND
Latch.

From the result we obtained, the outputs which is Q are determined from inputs set and clear.
The Q and not-Q outputs are supposed to be in opposite states. LOW S and LOW C is
INVALID, while LOW HIGH is SET, HIGH LOW is RESET and lastly HIGH S and HIGH
C is HOLD. The illegal input states for NAND latch, the both inputs LOW turns ON both
output LEDs. By having both S and C equal to 0 is called an invalid or illegal state for the
SC Latch. Otherwise, making S=1 and C=0 will set the multivibrator so that Q LED is ON
and not-Q LED is OFF. Conversely, making S=0 and C=1 will reset the latch in the opposite
state. When S and C NAND latch inputs are both equal to 1, the outputs "latch" in their prior
states or called hold.
 Faculty of Electrical and Electronic Page 7/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

CONCLUSION (PART 1)
For Part 1, The lab results and theoretical part in pre-lab achieved the first objective of this experiment which to
investigate the characteristic of NAND latch. In these studies, students have some knowledge on how to design
the NAND latch, the operation of NAND latch and build the truth table for NAND latch. Based on this
experiment, students also able to understand the concept of a latch circuit is to create a memory device. The latch
responds of NAND latch is active-HIGH inputs. It considered as a very important component due to the complex
type of circuits are formed by combining the set-clear latch with other type of components. NAND latch has
invalid states which as it cannot both of stable state to be LOW.
 Faculty of Electrical and Electronic Page 8/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

PART 2: INVESTIGATION OF NOR LATCH CHARACTERISTIC

START

(1) Write the operation of NOR latch.

(2) Build the truth table.
(3) Draw its logic circuit and label as Figure 3. PRE-LAB

Construct the circuit in Figure 3 on the breadboard

Analyse the
Analyse the circuit.
circuit
LAB
EXPERIMENT
Complete the timing diagram of the NOR latch
in Figure 4.

Discuss and conclude your findings.

POST-LAB

DONE
(PART 2)
Figure 4. Timing diagram with initial Input Q set to low.
 Faculty of Electrical and Electronic Page 10/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

DISCUSSION (PART 2)
Discuss the observation made from your results. Explain the term “Illegal input” for
NOR Latch.

LOW S and LOW C are HOLD in NOR Latch, while LOW HIGH is RESET, HIGH
LOW is SET, and HIGH S and HIGH C are INVALID. Both output LEDs are turned
off when the Illegal input for this NOR latch is HIGH. For the SC multivibrator,
having both S and C equal to 1 is referred to as an invalid or illegal state. Making S=1
and C=0, on the other hand, will set the multivibrator to Q=1 and not-Q=0. Making
R=1 and C=0, on the other hand, will reset the multivibrator to the opposite state.
When S and C are both 0, the multivibrator's outputs "latch" or "hold" in their
previous states.
 Faculty of Electrical and Electronic Page 11/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

CONCLUSION (PART 2)

In Part 2, in the lab results and the theoretical part of the prelab, we investigated the characteristics of
the NOR latch, the second goal of this experiment. These studies have some knowledge of how NOR
latches are designed, how NOR latches work, and how NOR latch truth tables are created. Based on
this experiment, students can also understand the concept of latch circuits. This corresponds to a NAND
latch intended to create a storage device or temporary storage device with two stable states (bistable).
The latch response from the NOR latch is the active HIGH input. This is considered a very important
component due to the complex nature of the circuit formed by combining the Set clear latch with other
types of components. The NOR latch has an invalid state and both cannot be stabilized and set to HIGH.
 Faculty of Electrical and Electronic Page 13/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

PART 3: INVESTIGATION OF SC FLIP FLOP

START

(1) Write the operation of edge triggered SC flip-flop.

(2) Build the truth table.
(3) Draw its logic circuit and label as Figure 5. PRE-LAB

Construct the SC flip-flop on the breadboard. Use a

pulse signal as the clock input.

Analyse
Analysethe circuitT
thecircuit.
LAB
EXPERIMENT
Complete the timing diagram of the SC flip-flop in
Figure 6.

Discuss and conclude your findings.

POST LAB

DONE
 Faculty of Electrical and Electronic Page 14/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

RESULTS (PART 3)
Faculty of Electrical and Electronic Page 14/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date
Faculty of Electrical and Electronic Page 14/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date
 Faculty of Electrical and Electronic Page 14/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date
Figure 6. Timing diagram for SC flip flop with initial Q set to low.
 Faculty of Electrical and Electronic Page 14/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

DISCUSSION (PART 3)
Discuss the observation made from your results. Explain the “illegal input” operation of
edge triggered SC flip flop.

In this part of the experiment with CLOCK, LOW S and LOW C is HOLD, while LOW
HIGH is RESET, HIGH LOW is SET and lastly HIGH S and HIGH C is INVALID.
An edge triggered flip-flop is a latch modification that permits the state to change only
for a short duration when the clock pulse changes from 0 to 1. It is dubbed an edge-
triggered flip-flop because it is claimed to trigger on the edge of the clock pulse. A
rising edge that is 0 to 1, positive edge trigger or a falling edge that is 1 to 0, negative
edge trigger can both cause the flip-flop. This text's flip-flops will all have a positive
edge trigger. In the SC flip flop, S=1, R=1 is invalid stat. In the invalid state (S=R=1).
 Faculty of Electrical and Electronic Page 16/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

CONCLUSION (PART 3)
Based on this experiment, students have some knowledge on how to design the SC flip-flop, the operation
of SC flip-flop and build the truth table for SC flip-flop. This flip-flop has invalid states which it cannot
both of stable state to be HIGH. By this experiment, students also able to differentiate between latch and
flip-flop which the basic difference is a clocking mechanism in SC flip-flop. SC flip-flop has two or more
gates involved which AND and NOR gates. Meanwhile, the latch has a less gates involved either it is
NAND or NOR gates. Both of latch and flip-flop still remains it two stable states, but in flip-flop there is a
clock pulse. Both are used as data storage elements as it is the basic storage element in sequential logic.
 Faculty of Electrical and Electronic Page 17/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

PART 4: INVESTIGATION OF JK FLIP FLOP

START

(1) Write the operation of edge triggered JK flip-flop.

(2) Build the truth table.
(3) Draw its logic circuit and label as Figure 7. PRE-LAB

Construct the JK flip-flop on the breadboard. Use

a pulse signal as the clock input.

LAB
EXPERIMENT
Analyse the circuit
Analyse the circuit.T

Complete the timing diagram of the JK flip flop in

Figure 8

Discuss and conclude your findings. POST LAB

DONE
 Faculty of Electrical and Electronic Page 18/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

RESULTS (PART 4)
 Faculty of Electrical and Electronic Page 19/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

Figure 8. Timing diagram for JK flip flop with initial Q set to low.
 Faculty of Electrical and Electronic Page 20/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

DISCUSSION (PART 4)
Discuss the observation made from your results. Explain the asynchronous inputs operation of edge
triggered JK flip-flop. Why is JK flip flop better than SC flip flop?

In this experiment with additional of CLOCK, PRESET and CLEAR. The inputs are replaced with
J and K with the same outputs Q. Asynchronous inputs on a flip flop have control over the outputs
Q and notQ regardless of clock input status. These inputs are called the PRESET and CLEAR. The
PRESET input drives the flip flop to a SET state while the clear input drives it to a RESET state. It
is possible to drive the outputs of a JK flip flop to an invalid condition using the asynchronous
inputs, because all feedback within the multivibrator circuit is overridden. JK flip flop is just the
same as SC flip flop but with more advantageous. The reason is why, it is because JK flip flop has
no INVALID input states of the SC Latch even when S and C are both at logic “1”.
 Faculty of Electrical and Electronic Page 20/21
Engineering
Department of Electronic Exp. No. 4
Engineering
Experiment Title: Latches and Digital Amendment January 2021
Flip-Flop Date

CONCLUSION (PART 4)
We used the 7476 ic in the last experiment because it has the CLR and PRESET functions. This experiment differs
from the other two in that it has four inputs and two outputs. The clk and preset switches have been added, and the
output from the J K input will be changed. The output from 0 0 to 1 0 is identical to the previous three experiments.
However, in the 1 1 condition, we may toggle the output, which means that when we press the clock's button, the
output can be changed from our instructions. When the preset and clr buttons are turned on, the output remains
constant and does not vary. The main difference between JK flip flop and SR flip flop is that when both inputs of SR
flip flop are set to 1, JK flip flop is superior than SR flip flop.