SBqM mini-project

Supervised by Dr. Ahmed Shalaby

Team name: Design architects

Team members:

1- Eslam Mahmoud Abd El

Gawad (Team leader).
2- Ahmed Abdel.
3- Mohammed Essam Abd El
Samee.
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Contents
1. Table of inputs & outputs..................................................................................... 1
2. System Icon:........................................................................................................ 2
3. Block structure diagram:...................................................................................... 2
4. The FSM module:.................................................................................................. 3
5. The Test plan:....................................................................................................... 3
6. The simulation results:......................................................................................... 4
7. Test benches results............................................................................................. 6
8. The transcript :..................................................................................................... 7

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1. Inputs and outputs table:

Inputs
Signal Widt Description
name h
Tcount 2 Determines the number of tailers
bits
Reset 1 bit Active low signal to reset the system
E_phcell 1 bit Active low sensor at entrance
O_phcell 1 bit Active low sensor at exit
Clk 1 bit 10 MHz clk signal
Outputs
Wtime 5 Determines the waiting time of customer
bits
Empty 1 bit Determines when the queue is empty
Full 1 bit Determines when the queue is full
alarm 1 bit Determines when the queue is full and another customer
wants to enter

2. System Icon:

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3. Block structure diagram:

4. The FSM module:

State Description
S0 The queue is empty initial state
S1 The queue is occupied but not full
S2 The queue is full.

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5. The Test plan:

1 Test the number of customers till the full queue while the entrance sensor is
hit
2 Test the full flag when the queue is full
3 During the test the work of the entrance sensor for more than one cycle to
ensure that it increments only once.
4 Try to add an extra customer to test the alarm signal
5 Test the number of customers till the empty queue while the exit sensor is hit
6 During the test, the waiting time was being tested for different cases

6. The simulation results:

During Empty:

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Full Case:

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7. Test benches results

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8. The transcript :

   Control Block
The block is the main FSM responsible of mapping the persons counted in the
queue and outputs to the interface an empty and full signal that indicates
the status of the queue.

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Port width Type description

Clk 1 Input Clock of the system
Reset 1 Input Reset signal for
resetting the system
and initializing it.
pcount 3 Input Persons count in the
queue
empty 1 Input Empty flag indicating
the states of the
queue
full 1 Output Full flag indicating
the states of the
queue

  Control Sensor

The block is a FSM responsible of mapping the sensors value to an output that
drives the persons counter block.

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Port width Type description

Clk 1 Input Clock of the system
Reset 1 Input Reset signal for
resetting the system
and initializing it.
e_phcell 1 Input Active low sensor at
entrance
o_phcell 1 Input Active low sensor at
exit
Phcell 2 Output Mapped Sensors
value

  Wtime Block

The block is mainly responsible for calculating the waiting time for customers in a
queue. It was supposed that that the time is calculated according to equation:

Wtime (Pcount  0,Tcount) = 3*(Pcount+Tcount-1)/Tcount

But it was decided to use a look-up table representing values for different values
of customers and tellers available.

The block consists of a ROM and another block required for selecting the
equivalent waiting time according to number of customers and tellers.

Port Type description

Clk Input Clock of the system
Reset Input Reset signal for resetting

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the system and

initializing it.
tcount Input Number of tellers
pcount Input Number of customers in
queue
Wtime Output Waitng time.

 Pcounter block

We built the (Pcounter) to count the number of customer in a queue according

the status of the entrance and exit sensors and we make an alarm signal to
detect when an extra customer tries to enter when the queue is full.
We used a sequential always block to describe the counter with active low reset
with the system, the (phcell) signal which is coming from the FSM of the system
and deliver the alarm signal to be an output of the system.

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