17 Computer Networks

Computer Organisation
15 14 8 7 0
Ch-1-Computer Arithmetic

Practice Questions
Sign Bit Excess-64 Mantissa
Exponent
01. Booth’s coding in 8 bits for the decimal number
-57 is: 04. Mantissa is a pure fraction in signed magnitude
(a) 0 - 1 0 0 + 1 0 0 0 form. The decimal number 0.239×213 has the
(b) 0 - 1 0 0 + 1 0 0 - 1 following hexadecimal representation without
(c) 0 - 1 + 1 0 0 - 1 0 +1 normalization and rounding off
(d) 0 0 -1 0 + 1 0 0 - 1 (a) 0D 24 (b) 0D 4D
(c) 4D 0D (d) 4D 3D
02. Sign extension is the step in
(a) Floating point multiplication 05. The normalized representation for the above
(b) Signed 16 bit integer addition format is specified as follows. The mantissa has
(c) Arithmetic left shift an implicit preceding the binary (radix) point.
(d) Converting a signed integer from one size Assume that only 0’s are padded in while
to another shifting a field. The normalized representation
of the above (0.239×213) is
03. A 4-bit carry lookahead adder, which adds two (a) 0A 20 (b) 11 34
4-bit numbers, is designed using AND, OR, NOT, (c) 4D D0 (d) 4A E8
NAND, NOR gates only. Assuming that all the
inputs are available in both complemented 06. In a lookahead carry generator, the carry
and un-complemented forms and the delay of generate function Gi and the carry propagate
each gate is one time unit, what is the overall function Pi for inputs, Ai and Bi are given by
propagation delay of the adder? Assume that
Pi = Ai ⊕ Bi and Gi = AiBi.
the carry network has been implemented using
The expression for the sum bit Si and carry bit
two-level AND-OR logic.
Ci+1 of the look ahead carry adder are given
(a) 4 time units
by Si = Pi ⊕ Ci and Ci+1 = Gi + PiCi, where C0 is
(b) 6 time units
the input carry. Consider a two–level logic
(c) 10 time units
implementation of the look–ahead carry
(d) 12 time units
generator.
Assume that all Pi and Gi are available for the
Common Data for Questions 04 & 05.
carry generator circuit and that the AND and
The data is given below. Solve the problems and OR gates can have any number of inputs. The
choose the correct answer. number of AND gates and OR gates needed
to implement the look– ahead carry generator
for a 4-bit adder with S3, S2, S1, S0 and C4 as its
outputs are respectively

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(a) 6, 3 (b) 10, 4

(c) 6, 4 (d) 10, 5

07. The value of a float type variable is represented

using the single-precision 32-bit floating point
format of IEEE-754 standard that uses 1 bit for
sign, 8 bits for biased exponent and 23 bits for
mantissa. A float type variable X is assigned the
decimal value of –14.25. The representation of
X in hexadecimal notation is
(a) C1640000H (b) 416C0000H
(c) 41640000H (d) C16C0000H

08. In a IEEE 754 single precision floating point

standard
(A) All thirty two bits ‘0’s represents special
value ± 0
(B) All thirty two bits ‘0’s represent + 0
(C) Used to represent ± 0, ± ∝ and NOT a
number (NAN) values
(D) Used to represent ± 0 and ± ∝ only but not
Not a number (NAN) values

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Ch-2-Memory Organization (a) 200 words/sec

(b) 5 × 103 words/sec.
Practice Questions
(c) 5 × 106 words/sec
Memory Basics (d) 5 × 109 words/sec.

01. A memory has 16-bit address bus. Then how 07. A function table is required in very large

many memory locations are there? numbers. The memory most suitable for this

(a) 64k (b) 65,536 purpose would be

(c) 216 (d) All (a) ROM (b) RAM

(c) EPROM (d) EAPROM

02. Memory size of a memory IC can be specified

as 08. When the power supply of a ROM is switched

(a) M×N where M = no. of memory locations, off, its contents

N= no. of bits in each location (a) Become all zero’s

(b) N×M, where N = no. of bits in each location, (b) Become all one’s

M = no. of locations (c) Remain same

(c) 2n × m, n= no. of address bits, m= no. of bits (d) Are unpredictable

in each location
(d) either a or c Cache Concept

03 The main disadvantage of DRAM over SRAM is

Common Data for Q.01 & 02
_____.
(a) High package density A CPU has 32–bit memory address and a 256 KB
(b) Costly Cache memory. The Cache is organized as a
(c) External memory refresh logic is required 4–way set associative Cache with Cache block size
(d) High power consumption of 16 bytes.

04. The address bus width of a memory of size 01. What is the size (in bits) of the tag field per
2048 × 8 bits is Cache block?
(a) 10 (b) 11 (c) 12 (d) 13 (a) 16 bits (b) 9 bits
(c) 19 bits (d) 12 bits
05. It is desired to have a 64 × 8 memory. The
memory IC’s available is of 16 × 4 size. The 02. From the above question, What is the number
number of ICs required and size of the comparator required for tag
(a) 8 (b) 4 matching?
(c) 6 (d) 2 (a) four 4–bit comparators
(b) sixteen 16–bit comparators
06. The write cycle time of a memory is 200 nsec. (c) four 16–bit comparators
The maximum rate at which data can be (d) one 4-bit comparator
stored.

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03. The capacity of a memory unit is defined by Statement for Linked Answer Questions 07 and 08:
the number of words multiplied by the number A computer has a 256 K Byte, 4-way set associative,
of bits per word. How many separate address write back data cache with block size of 32 Bytes.
and data lines are needed for a memory of The processor sends 32 bit addresses to the cache
4 K × 16? controller. Each cache tag directory entry contains,
(a) 10 address, 16 data lines in addition to address tag, 2 valid bits, 1 modified bit
(b) 11 address, 8 data lines and 1 replacement bit.
(c) 12 address, 16 data lines
(d) 12 address, 12 data lines 07. The number of bits in the tag field of an address

04. The main memory of a computer has 2cm is

blocks while the cache has 2c blocks. If the (a) 11 (b) 14 (c) 16 (d) 27

cache uses the set associative mapping

08. The size of the cache tag directory is
scheme with 2 blocks per set, then block ‘k’ of
(a) 160 K bits (b) 136 K bits
the main memory maps to the set:
(c) 40 K bits (d) 32 K bits
(a) (k mod m) of the cache
(b) (k mod c) of the cache
(c) (k mod 2 c) of the cache 09. A 4-way set-associative cache memory unit
(d) (k mod 2 cm) of the cache with a capacity of 16 KB is built using a block
size of 8 words. The word length is 32 bits. The
05. A processor can support a maximum memory
size of the physical address space is 4 GB. The
of 4GB, where the memory is word-addressable
number of bits for the TAG field is ________.
(a word consists of two bytes). The size of the
address bus of the processor is at least _______ 10. If the associativity of a processor cache is
bits. doubled while keeping the capacity and block
size unchanged, which one of the following is
06. An 8KB direct-mapped write-back cache
guaranteed to be NOT affected?
is organized as multiple blocks, each of size
(a) Width of tag comparator
32-bytes. The processor generates 32-bit
(b) Width of set index decoder
addresses. The cache controller maintains
(c) Width of way selection multiplexer
the tag information for each cache block
(d) Width of processor to main memory data bus
comprising of the following.
• 1 Valid bit
Common Data for Questions 11 & 12
• 1 Modified bit
• As many bits as the minimum needed to Consider two cache organizations: The first one is

identify the memory block mapped in the 32KB 2-way set associate with 32-byte block size. The

cache. second one is of the same size but direct mapped.

What is the total size of memory needed at the The size of an address is 32 bits in both cases. A

cache controller to store meta-data (tags) for 2-to-1 multiplexer has latency of 0.6 ns while a k-bit

the cache? comparator has a latency of k/10 ns. The hit latency

(a) 4864 bits (b) 6144 bits of the set associative organization is h1 while that of

(c) 6656 bits (d) 5376 bits the direct mapped one is h2.
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11. The value of h1 is (a) The words 50 and 132 are available in the
(a) 2.4 ns (b) 2.3 ns cache
(c) 1.8 ns (d) 1.7 ns (b) The words 150 and 132 are available in the
cache
12. The value of h2 is (c) The words 178 and 150 are available in the
(a) 2.4 ns (b) 2.3 ns cache
(c) 1.8 ns (d) 1.7 ns (d) The words 35 and 50 are available in the
cache
13. Let the Cache and main memory be divided
16. Consider a fully associative cache blocks
into equi sized partitions having 16 words. If
(numbered 0-7) and the following sequence of
cache has 256 blocks & main memory has 4096
main memory blocks of references are made
blocks and Cache is 4–way set associative the
4,3,25,8,19,6,25,8,16,35,45,22,8,3,16,25,7
number of Tag bits is
If LRU replacement policy is used, which cache
(a) 5 (b) 6 (c) 7 (d) 9
block will have memory block 7?
(a) 4 (b) 5
14. Consider a 4-way set-associative cache
(c) 6 (d) 7
(initially empty) with total 16 cache blocks. The
main memory consists of 256 blocks and the 17. If 2-way set associate cache with LRU cache
request for memory blocks is in the following contains Blocks 4, sets 2, the number of cache
order: misses for the following sequence of block
0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, address is
73, 92, 155. 8 12 0 12 8
Which one of the following memory block will (a) 2 (b) 3
NOT be in cache if LRU replacement policy is (c) 4 (d) 5

used?
18. Assume that for a certain processor, a read
(a) 3 (b) 8
request takes 50 nanoseconds on a cache miss
(c) 129 (d) 216 and 5 nanoseconds on a cache hit. Suppose
while running a program, it was observed that
15. A 64 word cache and 256 word main memories 80% of the processor’s read requests result in
are partitioned into 16 word blocks. The tag a cache hit. The average read access time in
information is shown below: (Current values in nanoseconds is ______.
cache)
Block Tag 19. Consider a machine with a byte addressable
0 10 main memory of 220 bytes, block size of 16 bytes
1 10 and a direct mapped cache having 212 cache
2 00 lines. Let the addresses of two consecutive bytes
in main memory be (E201F)16 and (E2020)16.
3 01
What are the tag and cache line address (in
Identify the correct statements with respect to
hex) for main memory address (E201F)16?
the availability of main memory words in the
(a) E, 201 (b) F, 201
cache
(c) E, E20 (d) 2, 01F

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Common Data Questions for Q20 & Q121 24. A 32-bit wide main memory unit with a capacity

Consider a machine with a byte addressable main of 1 GB is built using 256M × 4 - bit DRAM chips.

memory of 216 bytes. Assume that a direct mapped The number of rows of memory cells in the

data cache consisting of 32 lines of 64 bytes each DRAM chip is 214. The time taken to perform

is used in the system. A 50×50 two-dimensional array one refresh operation is 50 nanoseconds. The

of bytes is stored in the main memory starting from refresh period is 2 milliseconds. The percentage

memory location 1100H. Assume that data cache (rounded to the closest integer) of the time

is initially empty. The complete array is accessed available for performing the memory read/

twice. Assume that the contents of the data cache write operations in the main memory unit

do not change in between the two accesses. is _________.

25. The size of the physical address space of a

20. How many data cache misses will occur in
processor is 2P bytes. The word length is 2W
total?
bytes. The capacity of cache memory is 2N
(a) 48 (b) 50
bytes. The size of each cache block is 2M words.
(c) 56 (d) 59
For a K-way set-associative cache memory,

21. Which of the following lines of the data cache the length (in number of bits) of the tag fields is

will be replaced by new blocks in accessing (a) P – N – log2 K

the array? (b) P – N + log2 K

(a) line 4 to line 11 (c) P – N – M – W – log2 K

(b) line 4 to line 12 (d) P – N – M – W + log2 K

(c) line 0 to line 7

(d) line 0 to line 8 26. Associative memory
(a) Is faster than cache memory
22. The width of the physical address on a machine (b) Requires complex hardware circuit for
is 40 bits. The width of the tag field in a 512 KB each cell design
8-way set associative cache is ______bits. (c) Is also known as Content Addressable
Memory
23. Consider a 2-way set associative cache (d) Is used to design main memory in a system
with 256 blocks and uses LRU replacement.
Initially the cache is empty. Conflict misses are
those misses which occur due to contention
of multiple blocks for the same cache set.
Compulsory misses occur due to first time
access to the block. The following sequence of
accesses to memory blocks
(0, 128, 256, 128, 0, 128, 256, 128, 1, 129, 257,
129, 1, 129, 257, 129)
is repeated 10 times. The number of conflict
misses experienced by the cache is_____.

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Ch-3-Pipeline Organization until the branch outcome is known. A program

executes 109 instructions out of which 20% are
Practice Questions
conditional branches. If each instruction takes
01. A 4–stage pipeline has stage delays of 150, 120, one cycle to complete on average, then total
160, 140 ns respectively. Interstage buffer delay execution time of the program is
is 5 ns. Registers used constant clock rate. The (a) 1.0 second (b) 1.2 seconds
total time taken to process 1000 data items on
(c) 1.4 seconds (d) 1.6 seconds
this pipeline
(a) 120.4 µs (b) 160.5 µs
05. The stage delays in a 4-stage pipeline are
(c) 165.5 µs (d) 590 .0 µs
800,500,400 and 300 picoseconds. The first
stage (with delay 800 picoseconds) is replaced
02. For a pipelined CPU with a single ALU, consider
with a functionally equivalent design involving
the following situations
1. The (j + 1)th instruction uses the result of the two stages with respective delays 600 and 350

jth instruction as an operand picoseconds. The throughput increase of the

2. The execution of a conditional jump pipeline is ____ percent.
instruction
3. The jth and (j + 1)th instructions require the 06. A 5-stage pipelined processor has Instruction
ALU at the same time Fetch (IF), Instruction Decode (ID), Operand

Which of the above can cause a hazard? Fetch (OF), perform Operation (PO) and Write
Operand (WO) stages. The IF, ID, OF and
(a) 1 and 2 only (b) 2 and 3 only
WO stages take 1 clock cycle each for any
(c) 3 only (d) All the three
instruction. The PO stage takes 1 clock cycle

03. Register renaming is done in pipelined for ADD and SUB instructions, 3 clock cycles

processors for MUL instruction, and 6 clock cycles for DIV

(a) as an alternative to register allocation at instruction respectively. Operand forwarding
compile time is used in the pipeline. What is the number of
(b) for efficient access to function parameters clock cycles needed to execute the following
and local variables sequence of instructions?
(c) to handle certain kinds of hazards
(d) as part of address translation Instruction Meaning of instruction
I0 : MUL R2, R0, R1 R2 ← R0∗R1
04. A CPU has five - stages pipeline and run at I1 : DIV R5, R3, R4 R5 ← R3/R4
1 GHz frequency. Instruction fetch happens
I2 : ADD R2, R5, R2 R2 ← R5 + R2
in the first stage of the pipeline. A conditional
I3 : SUB R5, R2, R6 R5 ← R2 – R6
branch instruction computes the target address
and evaluates the condition in the third stage
(a) 13 (b) 15
of the pipeline. The processor stops fetching
(c) 17 (d) 19
new instructions following a conditional branch

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07. Consider an instruction pipeline with four stages (S1, S2, S3, and S4) each with combinational circuit only.
The pipeline registers are required between each stage and at the end of the last stage. Delays for the
stages and for the pipeline registers are as given in the figure.

Pipeline Register (Delay 1ns)

Pipeline Register (Delay 1ns)

Pipeline Register (Delay 1ns)

Pipeline Register (Delay 1ns)

Stage Stage Stage Stage
S1 S2 S3 S4
Delay Delay Delay Delay
5ns 6ns 11ns 8ns

What is the approximate speed up of the pipeline in steady state under ideal conditions when
compare to the corresponding non-pipeline implementation?
(a) 4.0 (b) 2.5 (c) 1.1 (d) 3.0

08. Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI),
Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The
stage delays for
FI, DI, FO, EI and WO are 5 ns, 7ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage
buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions
I1, I2, I3, ...., I12 is executed in this pipelined processor. Instruction I4 is the only branch instruction and its
branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed
to complete the program is
(a) 132 (b) 165
(c) 176 (d) 328

Common Data for Q. 09 & Q.10

An instruction pipeline has five stages where each stage takes 2 nano seconds and all instructions use all
five stages. Branch instructions are not overlapped, i.e., the instruction after the branch is not fetched till the
branch instruction is completed. Under ideal conditions.

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09. Calculate the average instruction execution

S1 S2 S3 S4
time assuming that 20% of all instructions
executed are branch instructions. Ignore the I1 1 2 1 2
fact that some branch instructions may be I2 2 1 2 1
conditional
I3 1 1 2 1
(a) 3 milli seconds
(b) 4 milli seconds I4 2 1 2 1
(c) 4.6 nano seconds
The output of I1 for i = 2 will be available after
(d) 3.6 nano seconds
(a) 11 ns (b) 12 ns
(c) 13 ns (d) 28 ns
10. From above question, if a branch instruction is
a conditional branch instruction, the branch
13. Consider a non-pipelined processor with a
need not be taken; if the branch is not taken,
clock rate of 2.5 gigahertz and average cycles
the following instructions can be overlapped.
per instruction of four. The same processor is
When 80% of all branch instructions are
upgraded to a pipelined processor with five
conditional branch instructions, and 50% of
stages; but due to the internal pipelined delay,
the conditional branch instructions are such
the clock speed is reduced to 2 gigahertz.
that the branch is taken, what is the average
Assume that there are no stalls in the pipeline.
instruction execution time?
The speed up achieved in this pipelined
(a) 4 milli secs
processor is _____.
(b) 3.6 milli secs
(c) 2.96 nano secs
14. Consider the sequence of machine instructions
(d) 3.74 nano secs
given below.
MUL R5, R0, R1
11. A pipeline is to provide speedup 6.6 operating
DIV R6, R2, R3
at 100 MHz and with 88% efficiency. How many
ADD R7, R5, R6
stages are existing in the pipeline?
SUB R8, R7, R4
(a) 10 (b) 5
(c) 8 (d) 3
In the above sequence, R0 to R8 are general
purpose registers. In the instruction shown, the
12. Consider a 4 stage pipelined CPU from S1 to S4,
first register stores the result of the operation
we want to execute the following loop
performed on the second and the third
for (i = 1, i <= 1000; i++)
registers. This sequence of instructions is to be
{
executed in a pipelined instruction processor
I1, I2, I3, I4;
with the following 4 stages:
}
(1) Instruction Fetch and Decode(IF),
Where the time taken by the instruction I1 to I4
(2) Operand Fetch (OF),
for stages S1 to S4 are given below.
(3) Perform Operation(PO) and
(4) Write back the result (WB).

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The IF, OF and WB stages take 1 clock cycle 16. Consider a 6-stage instruction pipeline, where
each for any instruction. The PO stage takes all stages are perfectly balanced. Assume that
1 clock cycle for ADD and SUB instructions. there is no cycle-time overhead of pipelining.
3 clock cycles for MUL instruction and 5 clock When an application is executing on this
cycles for DIV instruction. The pipelined 6-stage pipeline, the speedup achieved with
processor uses operand forwarding from the respect to non-pipelined execution if 25%
PO stage to the OF stage. The number of clock of the instructions incur 2 pipeline stall cycles
cycles taken for the execution of the above is ________.
sequence of instructions is _________.
17. Consider the following processors (ns stands
15. Consider the following code sequence having for nanoseconds). Assume that the pipeline
five instructions I1 to I5. Each of these instructions registers have zero latency.
has the following format. P1: Four-stage pipeline with stage latencies
OP Ri, Rj, Rk 1 ns, 2 ns, 2 ns, 1 ns.
Where operation OP is performed on contents P2: Four-stage pipeline with stage latencies
of registers Rj and Rk and the result is stored in 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
register Ri. P3: Five-stage pipeline with stage latencies
0.5 ns, 1ns, 1ns, 0.6 ns, 1ns.
I1: ADD R1, R2, R3 P4: Five-stage pipeline with stage latencies
I2: MUL R7, R1, R3 0.5 ns, 0.5 ns, 1ns, 1ns, 1.1ns.
I3: SUB R4, R1, R5 Which processor has the highest peak clock
I4: ADD R3, R2, R4 frequency?
I5: MUL R7, R8, R9 (a) P1 (b) P2
Consider the following three statements. (c) P3 (d) P4

S1: There is an anti-dependence between 18. An instruction pipeline has five stages namely,
instructions I2 and I5 instruction fetch (IF), instruction decode and
S2: There is an anti-dependence between register fetch (ID/RF), instruction execution
instructions I2 and I4 (EX), memory access (MEM), and register
S3: Within an instruction pipeline an anti- writeback (WB) with stage latencies 1 ns, 2.2 ns,
dependence always creates one or more
2 ns, 1 ns, and 0.75 ns, respectively (ns stands for
stalls
nanoseconds). To gain in terms of frequency,

the designers have decided to split the ID/RF
Which one of above statements is/are correct?
stage into three stages (ID, RF1, RF2) each of
(a) Only S1 is true
latency 2.2/3 ns. Also, the EX stage is spilt into
(b) Only S2 is true
two stages (EX1, EX2) each of latency 1 ns. The
(c) Only S1 and S3 are true
(d) Only S2 and S3 are true new design has a total of eight pipeline stages.
A program has 20% branch instructions which
execute in the EX stage and produce the next
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instruction pointer at the end of the EX stage in processor are contemplated:

the old design and at the end of the EX2 stage in (i) a naive pipeline implementation (NP) with
the new design. The IF stage stalls after fetching 5 stages and
a branch instruction until the next instruction (ii) an efficient pipeline (EP) where the OF

pointer is computed. All instructions other than stage is divided into stages OF1 and OF2
with execution times of 12 ns and 8 ns
the branch instruction have an average CPI of
respectively.
one in both the designs. The execution times
The speedup (correct to two decimal places)
of this program on the old and the new design
achieved by EP over NP in executing 20
are P and Q nanoseconds, respectively. The
independent instructions with no hazards
value of P/Q is ___________.
is______.

19. We have 2 designs D1 and D2 for a synchronous

22. The instruction pipeline of a RISC processor
pipelined CPU. D1 has 5 stages with execution
has the following stages. Instruction Fetch (IF),
times of 3ns, 2ns, 4ns, 2ns and 3ns. While the
Instruction Decode (ID). Operand Fetch (OF),
design D2 has 8 pipeline stages each with 2ns
Perform Operation (PO) and Writeback (WB).
execution time. How much time can be saved
The IF, ID, OF and WB stages take 1 clock
using design D2 over D1 for executing 100
cycle each for every instruction. Consider a
instructions.
sequence of 100 instructions. In the PO stage,
(a) 214 ns (b) 202 ns
40 instructions take 3 clock cycles each, 35
(c) 86 ns (d) 200 ns
instructions take 2 clock cycles each, and the
remaining 25 instructions take 1 clock cycle
20. A CPU takes 12 cycles to complete an
each. Assume that there are no data hazards
instruction. The corresponding pipelined CPU
and no control hazards.
uses 6 stages with execution of 3, 2, 5, 4, 6 and
The number of clock cycles required for
2 clocks. What is the speed up assuming that
completion of execution of the sequence of
a very large number of instructions are to be
instructions is _________.
executed?
(a) 1.83 (b) 2
23. Write After Read (WAR) Hazard in a pipelined
(c) 3 (d) 6
processor
(a) Is also known as True dependency conflict
21. Instruction execution in a processor is
(b) Is also known as Anti-dependency conflict
divided into 5 stages. Instruction Fetch (IF),
(c)
Can be minimized by using register
Instruction Decode (ID), Operand Fetch (OF),
renaming technique
Execute (EX), and Write Back (WB). These
(d) Can be minimized by using Two Address
stages take 5, 4, 20, 10, and 3 nanoseconds
instructions
(ns) respectively. A pipelined implementation
of the processor requires buffering between
each pair of consecutive stages with a delay
of 2 ns. Two pipelined implementation of the

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Ch-4-CPU Organization (a) RRC A, # 1 : Right rotate A through carry

by one bit
Practice Questions
(b) NOP ; no operation
Common Data For Q.no.01 & Q.no 02 (c) LRC A, #1 ; left rotate A through
carry flag by one Bit
Consider the following assembly language program
(d) ADD A, #1.
for a hypothetical processor. A, B and C are 8 bit
registers. The meanings of various instructions are
Common Data for Q.03,04 & 05
shown as comments.
Consider the following program segment. Here R1,
R2 and R3 are the general purpose registers.
MOV B, # 0 ; B←0
MOV C, # 8 ; C←8 Instruction
Z: CMP C, # 0 ; compare C with 0 Instruction Operation size
JZ: X ; jump to X if zero (in words)
flag is set MOV R1, (3000) R1 ← M[3000] 2
SUB C, # 1 ; C← C-1
Loop: MOV R2, [R3] R2 ← M[R3] 1
RRC A, # 1 ;
ADD R2, R1 R2 ← R1 + R2 1
Right rotate A through carry by one bit. Thus:; if the
initial values of A and the carry flag are a7 … a0 and; MOV (R3), R2 M [R3] ← R2 1
c0 respectively, their values after the execution of
INC R3 R3 ← R3 + 1 1
this instruction will be c0 a7 … a1 and a0 respectively.
DEC R1 R1 ← R1 - 1 1
JC : Y ; jump to Y if carry flag is set Branch on
BNZ Loop 2
JMP : Z ; jump to Z not zero
Y: ADD B,# 1 ; B←B+1 HALT Stop 1
JMP : Z ; jump to Z
X: Assume that the content of memory location 3000
is 10 and the content of the register R3 is 2000. The
01. If the initial value of register A is A0, the value of content of each of the memory locations from
register B after the program execution will be 2000 to 2010 is 100. The program is loaded from
(a) the number of 0 bits in A0 the memory location 1000. All the numbers are in
(b) the number of 1 bits in A0 decimal. (GATE-06)
(c) A0
(d) 8. 03. Assume that the memory is word addressable.
The number of memory references for
02. Which of the following instructions when accessing the data in executing the program
inserted at location X will ensure that the value completely is
of register A after program execution is the (a) 10 (b) 11
same as its initial value? (c) 20 (d) 21

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04. Assume that the memory is word addressable. 10. Consider a three word machine instruction
After the execution of this program, the content ADD A [R0], @ B
of memory location 2010 is The first operand (destination) “A[R0]” uses
(a) 100 (b) 101 indexed addressing mode with R0 as the index
(c) 102 (d) 110 register. The second operand (source) “@B”
used indirect addressing mode. A and B are
05. Assume that the memory is byte addressable
memory addresses residing at the second
and the word size is 32 bits. If an interrupt
occurs during the execution of the instruction and the third words, respectively. The first
“INC R3”, what return address will be pushed word of the instruction specifies the opcode,
on to the stack? the index register designation and the source
(a)1005 (b) 1020 and destination addressing modes. During
(c) 1024 (d) 1040 execution of ADD instruction, the two operands
are added and stored in the destination (first
06. A system has 13 bit instruction and supports operand).
one address and zero address instructions. The number of memory cycles needed during
If there are 32 one address instructions, how
the execution cycle of the instruction is
many zero address instructions are supported
by the processor (Assume 128– word memory). (a) 3 (b) 4
(a) 2048 (b) 1024 (c) 5 (d) 6
(c) 3072 (d) 4096

11. If we use internal data forwarding to speed up

07. Which of the following statement is true?
the performance of a CPU (R1, R2 and R3 are
(a) ROM is a Read/Write memory
registers and M [100] is a memory reference),
(b) PC points to the last instruction that was
then the sequence of operation.
executed
R1 → M [100]
(c) Stack works on the principle of LIFO
(d) All instructions affect the flags. M [100] → R2
M [100] → R3
08. Relative mode of addressing is most relevant to Can be replaced by
writing.
(a) Co-routines (a) R1 → R3 (b) M [100] → R2
(b) Position - independent code R2 → M [100] R1 → R2
(c) Shareable code
R1 → R3
(d) Interrupt handlers

09. Which of the following addressing modes (c) R1 → M [100] (d) R1 → R2

permits relocation without any change what R2 → R3 R1 → R3
so ever in the code? R1 → M [100]
(a) Indirect addressing
(b) Indexed addressing 12. For computers based on three-address
(c) Base register addressing instruction formats, each address field can be
(d) PC relative addressing. used to specify which of the following.
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S1: A memory operand (a) Immediate Addressing

S2: A processor register (b) Register Addressing
S3: An implied accumulator register (c) Register Indirect and Scaled Addressing
(a) Either S1 or S2 (d) Based or Indexed Addressing
(b) Either S2 or S3
(c) only S2 and S3 15. A machine has a 32-bit architecture, with
(d) All of S1, S2 and S3 1-word long instruction. It has 64 registers, each
of which is 32 bits long. It needs to support
13. Consider a processor with byte-addressable 45 instructions, which have an immediate
memory. Assume that all registers, including operand in addition to two register operands.
Program Counter (PC) and Program Status Assuming that the immediate operand is an
Word (PSW), are of size 2 bytes. A stack in the unsigned integer, the maximum value of the
main memory is implemented from memory immediate operand is _____.
location (0100)16 and it grows upward. The
stack pointer(SP) points to the top element of 16. Certain CPU uses expanding op-code. It has 16
the stack. The current value of SP is (016E)16. The bit instructions with 6 bit address. It supports one
CALL instruction is of two words, the first is the address and 2 address instructions only. If there
op-code and the second word is the starting are ‘n’ two address instructions, the maximum
address of the subroutine(one word = 2 bytes). number of one address instructions is
The CALL instruction is implemented as follows. (a) 210 (b) 210– n
• Store the current value of PC in the stack (c) 216– n (d) (24–n) × 26
• Store the value of PSW register in the stack
• Load the starting address of the subroutine 17. A processor has 40 distinct instructions and 24
in PC general purpose registers. A 32-bit instruction
The content of PC just before the fetch of CALL word has an opcode, two register operands
instruction is (5FA0)16. After execution of the and an immediate operand. The number of
CALL instruction, the value of the stack pointer bits available for the immediate operand field
is is_____.
(a) (016A)16 (b) (016C)16
(c) (0170)16 (d) (0172)16 18. Consider a processor with 64 registers and an
instruction set of size twelve. Each instruction has
14. Consider a hypothetical processor with an five distinct fields, namely, opcode, two source
instruction of type LW R1, 20 (R2), which during
register identifiers, one destination register
execution reads a 32-bit word from memory
identifier, and a twelve-bit immediate value.
and stores it in a 32-bit register R1. The effective
Each instruction must be stored in memory in
address of the memory location is obtained by
a byte-aligned fashion. If a program has 100
the addition of a constant 20 and the contents
instructions, the amount of memory (in bytes)
of register R2. Which of the following best
reflects the addressing mode implemented by consumed by the program text is_______.
this instruction for the operand in memory?

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19. Consider a RISC machine where each 22. The following are some events that occur after
instruction is exactly 4 bytes long. Conditional a device controller issues an interrupt while
and unconditional branch instructions use PC- process L is under execution.
relative addressing mode with Offset specified P. The processor pushes the process status of
in bytes to the target location of the branch L onto the control stack.
instruction. Further the Offset is always with Q. The processor finishes the execution of the
respect to the address of the next instruction in current instruction.
the program sequence. Consider the following R. The processor executes the interrupt
instruction sequence
service routine.
Instr. No. Instruction
S. The processor pops the process status of L
i : add R2, R3, R4
from the control stack.
i+1 : sub R5, R6, R7
T. The processor loads the new PC value
i+2 : cmp R1, R9, R10
based on the interrupt.
i+3: beq R1, offset
If the target of the branch instruction is i, then
Which one of the following is the correct order
the decimal value of the offset is_______.
in which the events above occur?
(a) QPTRS (b) PTRSQ
Common data for Q.20 & Q.21:
(c) TRPQS (d) QTPRS
A computer system has 13 – bit instruction and
support zero address & 1 address instructions. The 23. In PC relative addressing mode
memory contains 128 words. (a) Current PC value is used to compute the
Effective Addressing
20. If there exists 32 one address instructions, how (b) Current PC value is not altered after
many zero address instructions are supported computing the Effective Address
by system. (c) The displacement given in the instruction is
(a) 2048 (b) 1024 added to the current P.C. value and result
(c) 3072 (d) 4096 is placed in P.C
(d) Size of the opcode is minimum when
21. For above system which of the following is valid compared to the opcode size of the
(a) If 32-one address, then 1024 zero address general branch instruction
instructions
(b) If 64-one address, then 1024 zero address
instructions
(c) If 63-one address, then 128 zero address
instructions
(d) If 64-one address, then 256 zero address
instructions

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Ch-5-Control Unit Design 04. The micro instructions stored in the control
memory of a processor have a width of 26
Practice Questions bits. Each microinstruction is divided into three
01. An instruction set of a processor has 125 signals fields : a micro operation field of 13 bits, a next
which can be divided in 5 groups of mutually address field (X), and a MUX select field (Y).
exclusive signals as follows: There are 8 status bits in the inputs of the MUX.
G1 = 20
G2 = 70
G3 = 2 Load
Control Address
G4 = 10 Register
G5 = 23

How many bits can be saved by using vertical

MUX Control Memory
micro-program over horizontal micro program?
8 Y 13
(a) 125 (b) 22 Status bits Micro
X Operations
(c) 147 (d) 103
How many bits are there in the X and Y fields,
02. The main differences between a CISC and a and what is the size of the control memory in
RISC processor is / are that a RISC processor number of words?
typically. (a) 10, 3, 1024 (b) 8, 5, 256
(a) Has fewer instructions (c) 5, 8, 2048 (d) 10, 3, 512
(b) Has fewer addressing mode
(c) Has more registers 05. A hardware CPU has 8 control signals S1 to S8
(d) Is easier to implement using hard–wired require in the following time steps T1 to T4 to
control logic implement the 4 instructions I1 to I4.

03. Consider the following sequence of micro- T1 T2 T3 T4

operations I1 S1,S2,S3 S2,S4 S1,S7 S3,S8
MBR ← PC I2 S1,S3,S5 S3,S6 S6,S7 S6,S8
MAR ←X I3 S1,S3,S7 S6,S7 S1,S7 S7,S8
PC ←Y I4 S1,S2,S3 S4,S5 S6,S7 S7,S8
Memory ← MBR
Identify the correct statement with respect to
Which one of the following is a possible
the control signal instructions and timings.
operation performed by this sequence?
(a) S8 = T4 , S7 = T3
(a) Instruction fetch
(b) Operand fetch (b) S8 = T4 , S1 = T1

(c) Conditional branch (c) S8 = T4 , S4 = I1 T4 + T2 I1

(d) Initiation of interrupt service (d) S8 = T4 , S7 = T3 + I3 + T4 × I4

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06. Arrange the following configuration for CPU in 09. Hardwired control unit is
decreasing order of operating speed: (a) Faster than micro-programmed control
Hardwired control, vertical micro– programming, unit
horizontal micro– programming. (b) Costlier technique compared to micro-
(a) Hardwired control, vertical micro– programmed control unit
programming, horizontal micro– (c) Free from control memory of ROM portion
programming (d) Used in R.I.S.C processors
(b) Hardwired control, horizontal micro-
programming, vertical micro– programming
(c) Horizontal micro – programming, vertical
micro – programming, hardwired control
(d) Vertical micro – programming, horizontal
micro – programming, hardwired control

07. Horizontal micro-programming

(a) Does not require use of signal decoders.
(b) Results in larger sized micro-instructions
than vertical micro-programming
(c) Uses one bit for each one control signal
(d) All of the above

08. Consider the following processor design

characteristics.
I. Register-to register arithmetic operations only
II. Fixed-length instruction format
III. Hardwired control unit

Which of the characteristics above are used in

the design of a RISC processor?

(a) I and II only

(b) II and III only
(c) I and III only
(d) I, II and III

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Ch-6-I.O Organization 05. Which one of the following is true for a CPU
having a single interrupt request line and single
Practice Questions interrupt grant line?
01. In a vectored interrupt (a) Neither vectored interrupt nor multiple
interrupting devices are possible
(a) The branch address is assigned to a fixed
(b) Vectored interrupts are not possible but
location in memory
multiple interrupting devices are possible
(b) The interrupting source supplies the branch
(c) Vectored interrupts and multiple
information to the processor through an
interrupting devices are both possible
interrupt vector
(d) None of these
(c) The branch address is obtained from a
register in the processor 06. A device with data transfer rate 10 KB/sec is
(d) None of the above connected to a CPU. Data is transferred byte-
wise. Let the interrupt overhead be 4 µsec.
The byte transfer time between the device
02. The size of the data count register of a DMA
interface register and CPU or memory is
controller is 16 bits. The processor needs to
negligible. What is the minimum performance
transfer a file of 29,154 kilobytes from disk to main
gain of operating the device under interrupt
memory. The memory is byte addressable. The
mode over operating it under program
minimum number of times the DMA controller
controlled mode?
needs to get the control of the system bus from (a) 15 (b) 25 (c) 35 (d) 45
the processor to transfer the file from the disk to
main memory is ____. 07. A computer handles several interrupt sources
of which of the following are relevant for this
question.
03. The correct matching of the following pairs is
• Interrupt from CPU temperature sensor
List – I List – II (raises interrupt if CPU temperature is too
(P) DMA I/O 1. High speed RAM high)
(Q) Cache 2. Disk • Interrupt from Mouse (raises interrupt if the
(R) Interrupt I/O 3. Printer mouse is moved or a button is pressed)
(S) Condition code 4. ALU register • Interrupt from Keyboard (raises interrupt
when a key is pressed or released)
Codes: • Interrupt from Hard Disk (raises interrupt
(a) P-4, Q-3, R-1, S-2 when a disk read is completed)
(b) P-2, Q-1, R-3, S-4
(c) P-4, Q-3, R-2, S-1 Which one of these will be handled at the
(d) P-2, Q-3, R-4, S-1 HIGHEST priority?
(a) Interrupt from Hard Disk
(b) Interrupt from Mouse
04. Which of the following devices should get
(c) Interrupt from Keyboard
highest priority in assigning interrupts?
(d) Interrupt from CPU temperature sensor
(a) Hard disk (b) Printer
(c) Keyboard (d) Floppy disk

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08. On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service
routine, is given to transfer 500 bytes from an I/O device to memory.
Initialize the address register
Initialize the count to 500.
LOOP: Load a byte from device
Store in memory at address given by address register
Increment the Address register
Decrement the count
If count! = 0 go to LOOP
Assume that each statement in this program is equivalent to a machine instruction which takes one
clock cycle to execute if it is a non-load-store instruction. The load-store instructions take two clock
cycles to execute.
The designer of the system also has an alternate approach of using the DMA controller to implement the
same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each
DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.
What is the approximate speed up when the DMA controller based design is used in place of the
interrupt driven program based input-output?

(a) 3.4 (b) 4.4 (c) 5.1 (d) 6.7

09. The memory mapped IO technic (used for connecting the IO devices)
(a) Is used for connecting more no. of IO devices compared to I/O mapped I/O technique
(b) Blocks some valuable memory locations
(c) Is used when user/programmer wants to connect less. no. of IO devices
(d) Used IO read and IO write control signals

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Ch-7-Secondary Memories 05. An application loads 100 libraries at startup.

Loading each library requires exactly one disk
Practice Questions
access. The seek time of the disk to a random
location is given as 10 ms. Rotational speed of
01. A certain moving arm disk-storage, with one disk is 6000 rpm. If all 100 libraries are loaded
head, has the following specifications: from random locations on the disk, how long
Number of tracks / recording surface = 200 does it take to load all libraries? (The time to
Disk rotation speed = 2400 rpm transfer data from the disk block once the
Track storage capacity = 62,500 bits
head has been positioned at the start of the
The Average latency of this device is P msec
block may be neglected).
and the data transfer rate is Q bits/sec.
(a) 0.50 s (b) 1.50 s
Write the values of P & Q.
(c) 1.25 s (d) 1.00 s

02. A hard disk with a transfer rate of 10 Mbytes/second

is constantly transferring data to memory 06. Consider a hard disk with 16 recording surfaces
using DMA. The processor runs at 600 MHz, (0-15) having 16384 cylinders (0-16383) and
and takes 300 and 900 clock cycles to initiate each track contains 64 sectors (0-63). Data
and complete DMA transfer respectively. If storage capacity in each sector is 512 bytes.
the size of the transfer is 20 Kbytes. What is the Data are organized cylinder-wise and the
percentage of processor time consumed for addressing format is <cylinder no., surface no.,
the transfer operation? sector no.>. A file of size 42797 KB is stored in
(a) 5.0 % (b) 1.0 % the disk and the starting disk location of the file
(c) 0.5% (d) 0.1 % is <1200, 9, 40>. What is the cylinder number
of the last sector of the file, if it is stored in a
Common Data for Question numbers 03 & 04
contiguous manner?
(a) 1281 (b) 1282
A hard disk has 63 sectors per track, 10 platters each
(c) 1283 (d) 1284
with 2 recording surfaces and 1000 cylinders. The
address of a sector is given as a triple (c,h,s), where
07. Consider a disk pack with a seek time of 4
c is the cylinder number, h is the surface number
and s is the sector number. Thus, the 0th sector is milliseconds and rotational speed of 10000
addressed as (0,0,0), the 1st sector as (0,0,1), and so rotations per minute (RPM). It has 600 sectors
on. per track and each sector can store 512 bytes
of data. Consider a file stored in the disk. The file
03. The address (400, 16, 29) corresponds to sector contains 2000 sectors. Assume that every sector
number access necessitates a seek, and the average
(a) 505035 (b) 505036 rotational latency for accessing each sector is
(c) 505037 (d) 505038 half of the time for one complete rotation. The
total time (in milliseconds) needed to read the
04. The address of 1039th Sector is entire file is _______.
(a) (0, 15, 31) (b) (0, 16, 30)
(c) (0, 16, 31) (d) (0, 17, 31)

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08. Consider a typical disk that rotates at 15000

rotations per minute (RPM) and has a transfer
rate of 50×106 bytes/sec. If the average seek
time of the disk is twice the average rotation
delay and the controller’s transfer time is 10
times the disk transfer time, the average time(in
milliseconds) to read or write a 512-byte sector
of the disk is _____.

09. DVD memory

(a) Is faster than magnetic tape memory
(b)
Requires Electro mechanical devices
(Head and Motor) to perform read and
write operations
(c) Is costlier than flash memory
(d)
Is virus free compared to magnetic
memories.

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