TABLE 6.

3
Field Effect Transistors

Symbol and Input Resistance

Type Basic Relationships Transfer Curve and Capacitance
JFET
(n-channel)

Ri 7 100 M
Ci: (1 - 10) pF

MOSFET
depletion type
(n-channel)

Ri 7 1010 
Ci: (1 - 10) pF

MOSFET
enhancement type
(n-channel)

Ri 7 1010 
Ci: (1 - 10) pF

MESFET
depletion type
(n-channel)

Ri 7 1012 
Ci: (1 - 5) pF

MESFET
enhancement type
(n-channel)

Ri 7 1012 
Ci: (1 - 5) pF
416 FIELD-EFFECT 6. The transfer characteristics (ID versus VGS) are characteristics of the device itself and
TRANSISTORS are not sensitive to the network in which the JFET is employed.
7. When VGS = VP>2, ID = IDSS >4; and at a point where ID = IDSS >2, VGS ⬵ 0.3 V.
8. Maximum operating conditions are determined by the product of the drain-to-source
voltage and the drain current.
9. MOSFETs are available in one of two types: depletion and enhancement.
10. The depletion-type MOSFET has the same transfer characteristics as a JFET for drain
currents up to the IDSS level. At this point the characteristics of a depletion-type MOSFET
continue to levels above IDSS, whereas those of the JFET will end.
11. The arrow in the symbol of n-channel JFETs or MOSFETs will always point in to the
center of the symbol, whereas those of a p-channel device will always point out of
the center of the symbol.
12. The transfer characteristics of an enhancement-type MOSFET are not defined by
Shockley’s equation but rather by a nonlinear equation controlled by the gate-to-source
voltage, the threshold voltage, and a constant k defined by the device employed. The
resulting plot of ID versus VGS rises exponentially with incrseasing values of VGS.
13. Always handle MOSFETs with additional care due to the static electricity that exists
in places we might least suspect. Do not remove any shorting mechanism between the
leads of the device until it is installed.
14. A CMOS (complementary MOSFET) device employs a unique combination of a p-
channel and an n-channel MOSFET with a single set of external leads. It has the
advantages of a very high input impedance, fast switching speeds, and low operating
power levels, all of which make it very useful in logic circuits.
15. A depletion-type MESFET includes a metal–semiconductor junction, resulting in char-
acteristics that match those of an n-channel depletion-type JFET. Enhancement-
type MESFETs have the same characteristics as enhancement-type MOSFETs. The
result of this similarity is that the same type of dc and ac analysis techniques can be
applied to MESFETs as was applied to JFETs.

Equations
JFET:
VGS 2
ID = IDSS a 1 - b
VP
IDSS
ID = IDSS 0 VGS = 0 V, ID = 0 mA 0 VGS = VP, ID = ` , VGS ⬵ 0.3VP 0 ID = IDSS>2
4 VGS = VP>2
ID
VGS = VP a 1 - b
A IDSS
PD = VDSID
ro
rd =
(1 - VGS >VP)2
MOSFET (enhancement):
ID = k(VGS - VT)2
ID(on)
k =
(VGS(on) - VT)2

6.15 COMPUTER ANALYSIS

●
PSpice Windows
The characteristics of an n-channel JFET can be displayed using the same procedure
employed for the transistor in Section 3.13. The series of curves across the characteristics
plotted against various values of voltage requires a nested sweep within the sweep for the
drain-to-source voltage. The required configuration of Fig. 6.51 is constructed using pro-
cedures described in the previous chapters. In particular, note the complete absence of
resistors since the input impedance is assumed to be infinite, resulting in a gate current of 0 A.
426 FET BIASING
EXAMPLE 7.1 Determine the following for the network of Fig. 7.6:
a. VGSQ. 16 V
b. IDQ.
c. VDS.
d. VD. 2 kΩ
e. VG.
f. VS.
D

G I DSS = 10 mA
+ VP = –8 V

VGS
1 MΩ – S
–
2V
+

FIG. 7.6
Example 7.1.

Solution:
Mathematical Approach
a. VGSQ = -VGG = ⴚ2 V
VGS 2 -2 V 2
b. IDQ = IDSS a 1 - b = 10 mA a 1 - b
VP -8 V
= 10 mA(1 - 0.25)2 = 10 mA(0.75)2 = 10 mA(0.5625)
= 5.625 mA
c. VDS = VDD - ID RD = 16 V - (5.625 mA)(2 k⍀)
= 16 V - 11.25 V = 4.75 V
d. VD = VDS = 4.75 V
e. VG = VGS = ⴚ2 V
f. VS = 0 V

Graphical Approach The resulting Shockley curve and the vertical line at VGS = -2 V
are provided in Fig. 7.7. It is certainly difficult to read beyond the second place without

ID (mA)

IDSS = 10 mA
9
8
7
6
Q-point I D = 5.6 mA
Q
5
4
3 IDSS = 2.5 mA
2 4

–8 –7 – 6 – 5 – 4 – 3 –2 –1 0 VGS
VP = –8 V VP VGSQ = –VGG = –2 V
= –4 V
2

FIG. 7.7
Graphical solution for the network of Fig. 7.6.
 ID SELF-BIAS 429
CONFIGURATION
IDSS

IDSS
2
Q-point
ID
Q

VP VGSQ 0 VGS
I R
VGS = _ DSS S
2

FIG. 7.11
Sketching the self-bias line.

but ID = IS

and VDS = VDD - ID(RS + RD) (7.11)

In addition,
VS = ID RS (7.12)

VG = 0 V (7.13)

and VD = VDS + VS = VDD - VRD (7.14)

EXAMPLE 7.2 Determine the following for the network of Fig. 7.12:
a. VGSQ.
b. IDQ.
c. VDS.
RD
d. VS.
e. VG.
f. VD.

RG

FIG. 7.12
Example 7.2.

Solution:
a. The gate-to-source voltage is determined by
VGS = -IDRS
Choosing ID = 4 mA, we obtain
VGS = -(4 mA)(1 k⍀) = -4 V
The result is the plot of Fig. 7.13 as defined by the network.
430 FET BIASING ID = 8 mA, VGS = –8 V
ID (mA)
8
7
ID = 4 mA, VGS = – 4V
6
Network
5
4
3
2
1 V = 0 V, I = 0 mA
GS D

– 8 –7 – 6 – 5 – 4 – 3 – 2 – 1 0 VGS (V)

FIG. 7.13
Sketching the self-bias line for the network of Fig. 7.12.

If we happen to choose ID = 8 mA, the resulting value of VGS would be -8 V, as

shown on the same graph. In either case, the same straight line will result, clearly dem-
onstrating that any appropriate value of ID can be chosen as long as the corresponding
value of VGS as determined by Eq. (7.10) is employed. In addition, keep in mind that
the value of VGS could be chosen and the value of ID determined graphically.
For Shockley’s equation, if we choose VGS = VP >2 = -3 V, we find that
ID = IDSS >4 = 8 mA>4 = 2 mA, and the plot of Fig. 7.14 will result, representing the
characteristics of the device. The solution is obtained by superimposing the network
characteristics defined by Fig. 7.13 on the device characteristics of Fig. 7.14 and finding
the point of intersection of the two as indicated on Fig. 7.15. The resulting operating
point results in a quiescent value of gate-to-source voltage of
VGSQ = ⴚ2.6 V

ID (mA)

8
7
6
5
4
3
Q-point I D = 2.6 mA
Q
2
1

– 6 – 5 – 4 – 3 –2 –1 0 VGS (V)
VGSQ = – 2.6 V

FIG. 7.14 FIG. 7.15

Sketching the device characteristics for the Determining the Q-point for the network of
JFET of Fig. 7.12. Fig. 7.12.

b. At the quiescent point

IDQ = 2.6 mA
c. Eq. (7.11): VDS = VDD - ID (RS + RD)
= 20 V - (2.6 mA)(1 k⍀ + 3.3 k⍀)
= 20 V - 11.18 V
= 8.82 V
d. Eq. (7.12): VS = IDRS VOLTAGE-DIVIDER 431
BIASING
= (2.6 mA)(1 k⍀)
= 2.6 V
e. Eq. (7.13): VG = 0 V
f. Eq. (7.14): VD = VDS + VS = 8.82 V + 2.6 V = 11.42 V
or VD = VDD - ID RD = 20 V - (2.6 mA)(3.3 k⍀) = 11.42 V

EXAMPLE 7.3 Find the quiescent point for the network of Fig. 7.12 if:
a. RS = 100 ⍀.
b. RS = 10 k⍀.

Solution: Both RS ⫽ 100 ⍀ and RS ⫽ 10 k⍀ are plotted on Fig. 7.16.

a. For RS ⫽ 100 ⍀:
IDQ ⬵ 6.4 mA
and from Eq. (7.10),
VGSQ ⬵ ⴚ0.64 V
b. For RS = 10 k⍀
VGSQ ⬵ ⴚ4.6 V
and from Eq. (7.10),
IDQ ⬵ 0.46 mA
In particular, note how lower levels of RS bring the load line of the network closer to the
ID axis, whereas increasing levels of RS bring the load line closer to the VGS axis.

ID (mA)

8
RS = 100 Ω 7
I D = 4 mA, VGS = – 0.4 V Q-point I D ≅ 6.4 mA
6 Q

RS = 10 kΩ 4
VGS = –4 V, ID = 0.4 mA 3
2
Q-point 1

– 6 – 5 – 4 – 3 –2 –1 0 VGS (V)
VGSQ ≅ – 4.6 V

FIG. 7.16
Example 7.3.

7.4 VOLTAGE-DIVIDER BIASING

●
The voltage-divider bias arrangement applied to BJT transistor amplifiers is also applied to
FET amplifiers as demonstrated by Fig. 7.17. The basic construction is exactly the same,
but the dc analysis of each is quite different. IG = 0 A for FET amplifiers, but the magni-
tude of IB for common-emitter BJT amplifiers can affect the dc levels of current and volt-
age in both the input and output circuits. Recall that IB provides the link between input and
output circuits for the BJT voltage-divider configuration, whereas VGS does the same for
the FET configuration.
434 FET BIASING

FIG. 7.20
Effect of RS on the resulting Q-point.

shown in Fig. 7.20. It is fairly obvious from Fig. 7.20 that:

Increasing values of RS result in lower quiescent values of ID and declining values
of VGS.
Once the quiescent values of IDQ and VGSQ are determined, the remaining network analy-
sis can be performed in the usual manner. That is,

VDS = VDD - ID(RD + RS) (7.19)

VD = VDD - ID RD (7.20)

VS = ID RS (7.21)
VDD
IR1 = IR2 = (7.22)
R1 + R2

EXAMPLE 7.4 Determine the following for the network of Fig. 7.21:
a. IDQ and VGSQ.
b. VD.
c. VS.
d. VDS.
e. VDG. RD
R1

D
C1 C2
G

R2
RS CS

FIG. 7.21
Example 7.4.
Solution: VOLTAGE-DIVIDER 435
BIASING
a. For the transfer characteristics, if ID = IDSS >4 = 8 mA>4 = 2 mA, then VGS =
VP >2 = -4 V>2 = -2 V. The resulting curve representing Shockley’s equation
appears in Fig. 7.22. The network equation is defined by
R2VDD
VG =
R1 + R2
(270 k⍀)(16 V)
=
2.1 M⍀ + 0.27 M⍀
= 1.82 V
and VGS = VG - IDRS
= 1.82 V - ID(1.5 k⍀)

ID (mA)
8 (IDSS )
7
6
5
4
3
Q-point I D = 2.4 mA
2 Q
I D = 1.21 mA ( VGS = 0 V)
1

–4 –3 –2 –1 0 1 2 3
(VP) VGSQ = –1.8 V VG = 1.82 V
( I D = 0 mA )
FIG. 7.22
Determining the Q-point for the network of Fig. 7.21.

When ID = 0 mA,
VGS = +1.82 V
When VGS = 0 V,
1.82 V
ID = = 1.21 mA
1.5 k⍀
The resulting bias line appears on Fig. 7.22 with quiescent values of
IDQ = 2.4 mA
and VGSQ = ⴚ1.8 V
b. VD = VDD - IDRD
= 16 V - (2.4 mA)(2.4 k⍀)
= 10.24 V
c. VS = IDRS = (2.4 mA)(1.5 k⍀)
= 3.6 V
d. VDS = VDD - ID(RD + RS)
= 16 V - (2.4 mA)(2.4 k⍀ + 1.5 k⍀)
= 6.64 V
or VDS = VD - VS = 10.24 V - 3.6 V
= 6.64 V
436 FET BIASING e. Although seldom requested, the voltage VDG can easily be determined using
VDG = VD - VG
= 10.24 V - 1.82 V
= 8.42 V

7.5 COMMON-GATE CONFIGURATION

●
The next configuration is one in which the gate terminal is grounded and the input signal
typically applied to the source terminal and the output signal obtained at the drain terminal
as shown in Fig. 7.23a. The network can also be drawn as shown in Fig. 7.23b.

VDD
ID

RD
C2 I DSS
D Vo VP
C1 C2
G S D
I DSS Vi Vo
VP

S Vi RS G RD
C1
RS
– +
VSS
+ –VDD
VSS
(a) (b)

FIG. 7.23
Two versions of the common-gate configuration.

The network equation can be determined using Fig. 7.24.

Applying Kirchhoff’s voltage law in the direction shown in Fig. 7.24 will result in
-VGS - ISRS + VSS = 0
and VGS = VSS - ISRS
but IS = ID

so VGS = VSS - ID RS (7.23)

Applying the condition ID = 0 mA to Eq. 7.23 will result in

VGS = VSS - (0)RS

and VGS = VSS 0 ID = 0mA (7.24)

FIG. 7.24
Determining the network
equation for the configuration of Applying the condition VGS = 0 V to Eq. 7.23 will result in
Fig. 7.23. 0 = VSS - IDRS

VSS
and ID = ` (7.25)
RS VGS = 0 V

The resulting load-line appears in Fig. 7.25 intersecting the transfer curve for the JFET
as shown in the figure.
The resulting intersection defines the operating current IDQ and voltage VDQ for the net-
work as also indicated in the network.
 ID (mA) COMMON-GATE 437
IDSS CONFIGURATION

Q-point ID
Q
VSS
ID =
RS

VP 0
VGSQ VSS
( I D = 0 mA )
FIG. 7.25
Determining the Q-point for the network of Fig. 7.24.

Applying Kirchhoff’s voltage law around the loop containing the two sources, the JFET
and the resistors RD and RS in Fig. 7.23a and Fig. 7.23b will result in
+VDD - IDRD - VDS - ISRS + VSS = 0
Substituting IS = ID we have
+VDD + VSS - VDS - ID(RD + RS) = 0

so that VDS = VDD + VSS - ID(RD + RS) (7.26)

with VD = VDD - ID RD (7.27)

and VS = -VSS + ID RS (7.28)

EXAMPLE 7.5 Determine the following for the common-gate configuration of Fig. 7.26:
a. VGSQ
b. IDQ
c. VD
d. VG
e. VS
f. VDS

RD

C2

C1

RS

FIG. 7.26
Example 7.5.
438 FET BIASING Solution: Even though VSS is not present in this common-gate configuration the equa-
tions derived above can still be used by simply substituting VSS = 0 V into each equation
in which it appears.
a. For the transfer characteristics Eq. 7.23 becomes
VGS = 0 - IDRS
and VGS = -IDRS
For this equation the origin is one point on the load line while the other must be
determined at some arbitrary point. Choosing ID = 6 mA and solving for VGS will
result in the following:
VGS = -IDRS = -(6 mA)(680 ⍀) = -4.08 V
as shown in Fig. 7.27.

ID (mA)

12 I DSS
11
10
9
8
7
6
5
4
Q-point I D ≅ 3.8 mA
Q
3
2
1

–6 –5 –4 –3 –2 –1 0
VP VGSQ ≅ –2.6 V

FIG. 7.27
Determining the Q-point for the network of Fig. 7.26.

The device transfer curve is sketched using

IDSS 12 mA
ID = = = 3 mA(at VP >2)
4 4
and VGS ⬵ 0.3VP = 0.3(-6 V) = -1.8 V (at ID = IDSS >2)
The resulting solution is:
VGSQ ⬵ ⴚ2.6 V
b. From Fig. 7.27,
IDQ ⬵ 3.8 mA
c. VD = VDD - IDRD
= 12 V - (3.8 mA)(1.5 k⍀) = 12 V - 5.7 V
= 6.3 V
d. VG = 0 V
e. VS = ID RS = (3.8 mA)(680 ⍀)
= 2.58 V
f. VDS = VD - VS
= 6.3 V - 2.58 V
= 3.72 V
7.6 SPECIAL CASE: VGSQ ⴝ 0 V DEPLETION-TYPE 439
● MOSFETs
A network of recurring practical value because of its relative simplicity is the configuration
of Fig. 7.28. Note that direct connection of the gate and source terminals to ground resulting
in VGS = 0 V. It specifies that for any dc condition the gate to source voltage must be zero
volts. This will result in a vertical load line at VGSQ = 0 V as shown in Fig. 7.29.

ID
VDD

Q-point IDSS

RD

D
G I DSS
+ VP
VGSQ = 0V load line
VGS – S

VP 0 VGS

FIG. 7.28 FIG. 7.29

Special case VGSQ = 0 V Finding the Q-point for the network of Fig. 7.28.
configuration.

Since the transfer curve of a JFET will cross the vertical axis at IDSS the drain current
for the network is set at that level.

Therefore, IDQ = IDSS (7.29)

Applying Kirchhoff’s voltage law:

VDD - IDRD - VDS = 0

and VDS = VDD - IDRD (7.30)

with VD = VDS (7.31)

and VS = 0 V (7.32)

7.7 DEPLETION-TYPE MOSFETs

●
The similarities in appearance between the transfer curves of JFETs and depletion-type
MOSFETs permit a similar analysis of each in the dc domain. The primary difference
between the two is the fact that depletion-type MOSFETs permit operating points with posi-
tive values of VGS and levels of ID that exceed IDSS. In fact, for all the configurations dis-
cussed thus far, the analysis is the same if the JFET is replaced by a depletion-type MOSFET.
The only undefined part of the analysis is how to plot Shockley’s equation for positive
values of VGS. How far into the region of positive values of VGS and values of ID greater than
IDSS does the transfer curve have to extend? For most situations, this required range will be
fairly well defined by the MOSFET parameters and the resulting bias line of the network.
A few examples will reveal the effect of the change in device on the resulting analysis.

EXAMPLE 7.6 For the n-channel depletion-type MOSFET of Fig. 7.30, determine:
a. IDQ and VGSQ.
b. VDS.
440 FET BIASING

RD
R1
C2
D Vo

G
Vi
C1
S

R2
RS

FIG. 7.30
Example 7.6.

Solution:
a. For the transfer characteristics, a plot point is defined by ID = IDSS >4 = 6 mA>4 = 1.5 mA
and VGS = VP >2 = -3 V>2 = -1.5 V. Considering the level of VP and the fact that
Shockley’s equation defines a curve that rises more rapidly as VGS becomes more positive,
a plot point will be defined at VGS = +1 V. Substituting into Shockley’s equation yields
VGS 2
ID = IDSS a 1 - b
VP
+1 V 2 1 2
= 6 mA a 1 - b = 6 mA a 1 + b = 6 mA (1.778)
-3 V 3
= 10.67 mA
The resulting transfer curve appears in Fig. 7.31. Proceeding as described for JFETs,
we have
10 M⍀(18 V)
Eq. (7.15): VG = = 1.5 V
10 M⍀ + 110 M⍀
Eq. (7.16): VGS = VG - IDRS = 1.5 V - ID(750 ⍀)

FIG. 7.31
Determining the Q-point for the network of Fig. 7.30.
 Setting ID = 0 mA results in DEPLETION-TYPE 441
MOSFETs
VGS = VG = 1.5 V
Setting VGS = 0 V yields
VG 1.5 V
ID = = = 2 mA
RS 750 ⍀
The plot points and resulting bias line appear in Fig. 7.31. The resulting operating
point is given by
IDQ = 3.1 mA
VGSQ = ⴚ0.8 V
b. Eq. (7.19):
VDS = VDD - ID(RD + RS)
= 18 V - (3.1 mA)(1.8 k⍀ + 750 ⍀)
⬵ 10.1 V

EXAMPLE 7.7 Repeat Example 7.6 with RS = 150 ⍀.

Solution:
a. The plot points are the same for the transfer curve as shown in Fig. 7.32. For the bias line,
VGS = VG - ID RS = 1.5 V - ID (150 ⍀)
Setting ID = 0 mA results in
VGS = 1.5 V
Setting VGS = 0 V yields
VG 1.5 V
ID = = = 10 mA
RS 150 ⍀

FIG. 7.32
Example 7.7.

The bias line is included on Fig. 7.32. Note in this case that the quiescent point results
in a drain current that exceeds IDSS, with a positive value for VGS. The result is
IDQ = 7.6 mA
VGSQ = ⴙ0.35 V
b. Eq. (7.19):
VDS = VDD - ID(RD + RS)
= 18 V - (7.6 mA)(1.8 k⍀ + 150 ⍀)
= 3.18 V
442 FET BIASING
EXAMPLE 7.8 Determine the following for the network of Fig. 7.33:
a. IDQ and VGSQ.
b. VD.

20 V

RD 6.2 kΩ

C2
D Vo

I DSS = 8 mA
G
Vi VP = – 8 V
C1 S

RG 1 MΩ RS 2.4 kΩ

FIG. 7.33
Example 7.8.

Solution:
a. The self-bias configuration results in
VGS = -IDRS
as obtained for the JFET configuration, establishing the fact that VGS must be less than
0 V. There is therefore no requirement to plot the transfer curve for positive values of
VGS, although it was done on this occasion to complete the transfer characteristics. A
plot point for the transfer characteristics for VGS 6 0 V is
IDSS 8 mA
ID = = = 2 mA
4 4
VP -8 V
and VGS = = = -4 V
2 2
and for VGS 7 0 V, since VP = -8 V, we will choose
VGS = +2 V
VGS 2 +2 V 2
and ID = IDSS a 1 - b = 8 mA a 1 - b
VP -8 V
= 12.5 mA
The resulting transfer curve appears in Fig. 7.34. For the network bias line, at
VGS = 0 V, ID = 0 mA. Choosing VGS = -6 V gives
VGS -6 V
ID = - = - = 2.5 mA
RS 2.4 k⍀
The resulting Q-point is given by
IDQ = 1.7 mA
VGSQ = ⴚ4.3 V
b. VD = VDD - IDRD
= 20 V - (1.7 mA)(6.2 k⍀)
= 9.46 V
The example to follow employs a design that can also be applied to JFET transistors. At
first impression it appears rather simplistic, but in fact it often causes some confusion
when first analyzed due to the special point of operation.
 ENHANCEMENT-TYPE 443
MOSFETs

FIG. 7.34
Determining the Q-point for the network of Fig. 7.33.

EXAMPLE 7.9 Determine VDS for the network of Fig. 7.35.

Solution: The direct connection between the gate and source terminals requires that
VGS = 0 V +
IDSS = 10 mA
Since VGS is fixed at 0 V, the drain current must be IDSS (by definition). In other words, VDS
VP = – 4 V
VGSQ = 0 V –
and IDQ = 10 mA
There is therefore no need to draw the transfer curve, and
VD = VDD - IDRD = 20 V - (10 mA)(1.5 k⍀)
= 20 V - 15 V
= 5V FIG. 7.35
Example 7.9.

7.8 ENHANCEMENT-TYPE MOSFETs

●
The transfer characteristics of the enhancement-type MOSFET are quite different from
those encountered for the JFET and depletion-type MOSFETs, resulting in a graphical
solution quite different from those of the preceding sections. First and foremost, recall that
for the n-channel enhancement-type MOSFET, the drain current is zero for levels of gate-
to-source voltage less than the threshold level VGS(Th), as shown in Fig. 7.36. For levels of
VGS greater than VGS(Th), the drain current is defined by

ID = k(VGS - VGS(Th))2 (7.33)

Since specification sheets typically provide the threshold voltage and a level of drain
current (ID(on)) and its corresponding level of VGS(on), two points are defined immedi-
ately as shown in Fig. 7.36. To complete the curve, the constant k of Eq. (7.33) must be
determined from the specification sheet data by substituting into Eq. (7.33) and solving
for k as follows:
ID = k(VGS - VGS(Th))2
ID(on) = k(VGS(on) - VGS(Th))2
444 FET BIASING ID (mA)

ID2

ID = k (VGS – VGS(Th) )2

ID (on)

ID1

VGS(Th) VGS1 VGS2 VGS

ID = 0 mA VGS(on)

FIG. 7.36
Transfer characteristics of an n-channel enhancement-type MOSFET.

ID(on)
and k = (7.34)
(VGS(on) - VGS(Th))2

Once k is defined, other levels of ID can be determined for chosen values of VGS. Typically,
a point between VGS(Th) and VGS(on) and one just greater than VGS(on) will provide a sufficient
number of points to plot Eq. (7.33) (note ID1 and ID2 on Fig. 7.36).

Feedback Biasing Arrangement

A popular biasing arrangement for enhancement-type MOSFETs is provided in Fig. 7.37.
The resistor RG brings a suitably large voltage to the gate to drive the MOSFET “on.” Since
IG = 0 mA, VRG = 0 V and the dc equivalent network appears as shown in Fig. 7.38.

IG = 0 A
RG C2

C1

FIG. 7.37 FIG. 7.38

Feedback biasing arrangement. DC equivalent of the
network of Fig. 7.37.

A direct connection now exists between drain and gate, resulting in

VD = VG

and VDS = VGS (7.35)

For the output circuit,

VDS = VDD - IDRD
which becomes the following after substituting Eq. (7.27): ENHANCEMENT-TYPE 445
MOSFETs
VGS = VDD - IDRD (7.36)

The result is an equation that relates ID to VGS, permitting the plot of both on the same set
of axes.
Since Eq. (7.36) is that of a straight line, the same procedure described earlier can be
employed to determine the two points that will define the plot on the graph. Substituting
ID = 0 mA into Eq. (7.36) gives

VGS = VDD 0 ID = 0 mA (7.37)

Substituting VGS = 0 V into Eq. (7.36), we have

VDD
ID = ` (7.38)
RD VGS = 0 V

The plots defined by Eqs. (7.33) and (7.36) appear in Fig. 7.39 with the resulting operating
point.

FIG. 7.39
Determining the Q-point for the network of Fig. 7.37.

EXAMPLE 7.10 Determine IDQ and VDSQ for the enhancement-type MOSFET of Fig. 7.40.

RD

RG C2

C1
G

FIG. 7.40
Example 7.10.
446 FET BIASING Solution:
Plotting the Transfer Curve Two points are defined immediately as shown in Fig. 7.41.
Solving for k, we obtain
ID(on)
Eq. (7.34): k =
(VGS(on) - VGS(Th))2
6 mA 6 * 10-3
= = A>V2
(8 V - 3 V)2 25
= 0.24 : 10ⴚ3 A , V2

VGS = 10 V, ID = 11.76 mA

I D(on)

VGS = 6 V, ID = 2.16 mA

VGS(Th) VGS(on)

FIG. 7.41
Plotting the transfer curve for the MOSFET of Fig. 7.40.

For VGS = 6 V (between 3 and 8 V):

ID = 0.24 * 10-3(6 V - 3 V)2 = 0.24 * 10-3(9)
= 2.16 mA
as shown on Fig. 7.41. For VGS = 10 V (slightly greater than VGS(Th)),
ID = 0.24 * 10-3(10 V - 3 V)2 = 0.24 * 10-3(49)
= 11.76 mA
as also appearing on Fig. 7.41. The four points are sufficient to plot the full curve for the
range of interest as shown in Fig. 7.41.

For the Network Bias Line

VGS = VDD - IDRD
= 12 V - ID(2 k⍀)
Eq. (7.37): VGS = VDD = 12 V 0 ID = 0 mA
VDD 12 V
Eq. (7.38): ID = = = 6 mA 0 VGS = 0 V
RD 2 k⍀
The resulting bias line appears in Fig. 7.42.
At the operating point,
IDQ = 2.75 mA
and VGSQ = 6.4 V
with VDSQ = VGSQ = 6.4 V
 ID = mA ENHANCEMENT-TYPE 447
MOSFETS

12
11
10
9
8
7
VDD
6
RD
5
4
I D = 2.75 mA 3 Q-point
Q
2
1

0 1 2 3 4 5 6 7 8 9 10 11 12 VGS
(VDD)
VGS = 6.4 V
Q

FIG. 7.42
Determining the Q-point for the network of Fig. 7.40.

Voltage-Divider Biasing Arrangement

A second popular biasing arrangement for the enhancement-type MOSFET appears in
Fig. 7.43. The fact that IG = 0 mA results in the following equation for VGG as derived
from an application of the voltage-divider rule:

R2VDD
VG = (7.39)
R1 + R2 IG = 0 A

Applying Kirchhoff’s voltage law around the indicated loop of Fig. 7.43 results in
+ VGS –
+VG - VGS - VRS = 0
and VGS = VG - VRS

or VGS = VG - IDRS (7.40)

For the output section,

FIG. 7.43
VRS + VDS + VRD - VDD = 0 Voltage-divider biasing
and VDS = VDD - VRS - VRD arrangement for an n-channel
enhancement MOSFET.
or VDS = VDD - ID(RS + RD) (7.41)

Since the characteristics are a plot of ID versus VGS and Eq. (7.40) relates the same two
variables, the two curves can be plotted on the same graph and a solution determined at their
intersection. Once IDQ and VGSQ are known, all the remaining quantities of the network such
as VDS, VD, and VS can be determined.

EXAMPLE 7.11 Determine IDQ, VGSQ, and VDS for the network of Fig. 7.44.
Solution:
Network
R2VDD (18 M⍀)(40 V)
Eq. (7.39): VG = = = 18 V
R1 + R2 22 M⍀ + 18 M⍀
Eq. (7.40): VGS = VG - IDRS = 18 V - ID(0.82 k⍀)
which is plotted on the same graph (Fig. 7.45). From Fig. 7.45, COMBINATION 449
NETWORKS
IDQ ⬵ 6.7 mA
VGSQ = 12.5 V
Eq. (7.41): VDS = VDD - ID(RS + RD)
= 40 V - (6.7 mA)(0.82 k⍀ + 3.0 k⍀)
= 40 V - 25.6 V
= 14.4 V

7.9 SUMMARY TABLE

●
Table 7.1 reviews the basic results and demonstrates the similarity in approach for a num-
ber of FET configurations. It also reveals that the analysis of dc configurations for FETs is
fairly straightforward. Once the transfer characteristics are established, the network bias
line can be drawn and the Q-point determined at the intersection of the device transfer
characteristic and the network bias curve. The remaining analysis is simply an application
of the basic laws of circuit analysis.

7.10 COMBINATION NETWORKS

●
Now that the dc analysis of a variety of BJT and FET configurations is established, the
opportunity to analyze networks with both types of devices presents itself. Fundamentally,
the analysis simply requires that we first approach the device that will provide a terminal
voltage or current level. The door is then usually open to calculating other quantities and
concentrating on the remaining unknowns. These are usually particularly interesting prob-
lems due to the challenge of finding the opening and then using the results of the past few
sections and Chapter 4 to find the important quantities for each device. The equations and
relationships used are simply those we have employed on more than one occasion—there
is no need to develop any new methods of analysis.

EXAMPLE 7.12 Determine the levels of VD and VC for the network of Fig. 7.46.

RD

R1
G

RG

R2
RE

FIG. 7.46
Example 7.12.
 TABLE 7.1
FET Bias Configurations

Type Configuration Pertinent Equations Graphical Solution

VDD ID
RD IDSS
JFET VGSQ = - VGG
Fixed-bias RG VDS = VDD - IDRS Q-point
VGG –
+ VP VGG 0 VGS

ID
VDD
IDSS
RD
JFET VGS = - IDRS
I'D
Self-bias VDS = VDD - ID(RD + RS) Q-point
RG RS
VP V' 0 VGS
GS

VDD ID
R2VDD IDSS
JFET R1 RD VG =
R1 + R2 VG
Voltage-divider
VGS = VG - IDRS Q-point RS
bias R2 RS
VDS = VDD - ID(RD + RS)
VP 0 VG VGS

VDD ID
RD IDSS
JFET VGS = VSS - IDRS VSS
Q-point
Common-gate VDS = VDD + VSS - ID(RD + RS) RS
RS
–VSS VP 0 VSS VGS

ID
VDD VGS = - IDRS IDSS
RD
JFET VD = VDD
(RD = 0 ⍀) VS = IDRS I'D
Q-point
VDS = VDD - ISRS
VP V'GS 0 VGS

VDD ID
RD Q-point IDSS
JFET
VGSQ = 0 V
Special case VGS = 0 V
IDQ = IDSS Q
(VGSQ = 0 V) RG
VGG
VP 0 VGS

ID
VDD
Depletion-type Q-point
MOSFET VGSQ = + VGG IDSS
Fixed-bias RG VDS = VDD - IDRS
RS
(and MESFETs)
VP 0 VGG VGS

VG ID
Depletion-type VDD R2VDD
MOSFET R1 RD VG = RS Q-point
R1 + R2 IDSS
Voltage-divider
R2 VGS = VG - ISRS
bias RS
VDS = VDD - ID(RD + RS)
(and MESFETs) VP 0 VG VGS

VDD ID
Enhancement VDD
RD RD
type MOSFET RG ID(on)
VGS = VDS
Feedback Q-point
VGS = VDD - IDRD
configuration
(and MESFETs) 0 VGS(Th) VDD VGS
VGS(on)

Enhancement VDD VG ID
R2VDD RS
type MOSFET RD
R1 VG =
Voltage-divider R1 + R2 Q-point
bias R2 RS VGS = VG - IDRS
(and MESFETs) 0 VGS(Th) VG VGS

450
Solution: From experience we now realize that VGS is typically an important quantity to COMBINATION 451
determine or write an equation for when analyzing JFET networks. Since VGS is a level for NETWORKS
which an immediate solution is not obvious, let us turn our attention to the transistor con-
figuration. The voltage-divider configuration is one where the approximate technique can
be applied (bRE = 180 * 1.6 k⍀ = 288 k⍀ 7 10R2 = 240 k⍀), permitting a determi-
nation of VB using the voltage-divider rule on the input circuit.
For VB,
24 k⍀(16 V)
VB = = 3.62 V
82 k⍀ + 24 k⍀
Using the fact that VBE = 0.7 V results in
VE = VB - VBE = 3.62 V - 0.7 V
= 2.92 V
VRE VE 2.92 V
and IE = = = = 1.825 mA
RE RE 1.6 k⍀
with IC ⬵ IE = 1.825 mA
Continuing, we find for this configuration that
ID = IS = IC
and VD = 16 V - ID(2.7 k⍀)
= 16 V - (1.825 mA)(2.7 k⍀) = 16 V - 4.93 V
= 11.07 V
The question of how to determine VC is not as obvious. Both VCE and VDS are unknown
quantities, preventing us from establishing a link between VD and VC or from VE to VD. A
more careful examination of Fig. 7.46 reveals that VC is linked to VB by VGS (assuming that
VRG = 0 V). Since we know VB if we can find VGS, VC can be determined from
VC = VB - VGS
The question then arises as to how to find the level of VGSQ from the quiescent value of
ID. The two are related by Shockley’s equation:
VGSQ 2
IDQ = IDSS a 1 - b
VP
and VGSQ could be found mathematically by solving for VGSQ and substituting numerical
values. However, let us turn to the graphical approach and simply work in the reverse
order employed in the preceding sections. The JFET transfer characteristics are first
sketched as shown in Fig. 7.47. The level of IDQ = ISQ = ICQ = IEQ is then established by
a horizontal line as shown in the same figure. VGSQ is then determined by dropping a line
down from the operating point to the horizontal axis, resulting in
VGSQ = ⴚ3.7 V

ID (mA)

12 I DSS

10

Q-point 2
I D = 1.825 mA
Q
– 6 –5 –4 –3 –2 –1 0
VP
VGS ≅ – 3.7 V
Q

FIG. 7.47
Determining the Q-point for the network of Fig. 7.46.
 452 FET BIASING The level of VC is given by
VC = VB - VGSQ = 3.62 V - (-3.7 V)
= 7.32 V

EXAMPLE 7.13 Determine VD for the network of Fig. 7.48.

Solution: In this case, there is no obvious path for determining a voltage or current level for
RC the transistor configuration. However, turning to the self-biased JFET, we can derive an equa-
RB
tion for VGS and determine the resulting quiescent point using graphical techniques. That is,
C VGS = -IDRS = -ID(2.4 k⍀)
B resulting in the self-bias line appearing in Fig. 7.49, which establishes a quiescent point at
VGSQ = -2.4 V
D, E
IDQ = 1 mA

ID (mA)
G 8 IDSS
S 7
6
RS 5
4
3
2 1.67 mA
FIG. 7.48 1 I D = 1 mA
Q
Example 7.13.
– 4 –3 –2 –1 0
VP
VGS = –2.4 V
Q

FIG. 7.49
Determining the Q-point for the network of Fig. 7.48.

For the transistor,

IE ⬵ IC = ID = 1 mA
IC 1 mA
and IB = = = 12.5 mA
b 80
VB = 16 V - IB(470 k⍀)
= 16 V - (12.5 mA)(470 k⍀) = 16 V - 5.88 V
= 10.12 V
and VE = VD = VB - VBE
= 10.12 V - 0.7 V
= 9.42 V
D
G
7.11 DESIGN
●
S The design process is a function of the area of application, level of amplification desired,
signal strength, and operating conditions. The first step is normally to establish the proper dc
levels of operation.
For example, if the levels of VD and ID are specified for the network of Fig. 7.50, the
level of VGSQ can be determined from a plot of the transfer curve and RS can then be de-
termined from VGS = -IDRS. If VDD is specified, the level of RD can then be calculated
FIG. 7.50 from RD = (VDD - VD)>ID. Of course, the values of RS and RD may not be standard
Self-bias configuration commercial values, requiring that the nearest commercial values be employed. However,
to be designed. with the tolerance (range of values) normally specified for the parameters of a network,
the slight variation due to the choice of standard values will seldom cause a real concern DESIGN 453
in the design process.
The above is only one possibility for the design phase involving the network of Fig. 7.50.
It is possible that only VDD and RD are specified together with the level of VDS. The device to
be employed may have to be specified along with the level of RS. It appears logical that the
device chosen should have a maximum VDS greater than the specified value by a safe margin.
In general, it is good design practice for linear amplifiers to choose operating points
that do not crowd the saturation level (IDSS) or cutoff (VP) regions. Levels of VGSQ close to
VP >2 or levels of IDQ near IDSS >2 are certainly reasonable starting points in the design. Of
course, in every design procedure the maximum levels of ID and VDS as appearing on the
specification sheet must not be exceeded.
The examples to follow have a design or synthesis orientation in that specific levels are
provided and network parameters such as RD, RS, VDD, and so on, must be determined. In
any case, the approach is in many ways the opposite of that described in previous sections.
In some cases, it is just a matter of applying Ohm’s law in its appropriate form. In particular,
if resistive levels are requested, the result is often obtained simply by applying Ohm’s law
in the following form:

VR
Runknown = (7.42)
IR

where VR and IR are often parameters that can be found directly from the specified voltage
and current levels.

EXAMPLE 7.14 For the network of Fig. 7.51, the levels of VDQ and IDQ are specified. Deter-
mine the required values of RD and RS. What are the closest standard commercial values?
20 V
I D = 2.5 mA
Q
RD

VD = 12 V
G
I DSS = 6 mA
VP = – 3 V
S

RS

FIG. 7.51
Example 7.14.

Solution: As defined by Eq. (7.42),

ID (mA)
VRD VDD - VDQ
RD = = 6 IDSS
IDQ IDQ 5
20 V - 12 V 8V 4
and = = = 3.2 k⍀ 3
2.5 mA 2.5 mA I = 2.5 mA
2 DQ
Plotting the transfer curve in Fig. 7.52 and drawing a horizontal line at IDQ = 2.5 mA 1
results in VGSQ = -1 V, and applying VGS = -IDRS establishes the level of RS:
-(VGSQ ) -(-1 V) –3 –2 –1 0 VGS
RS = = = 0.4 k⍀ VP
IDQ 2.5 mA VGS = – 1 V
Q
The nearest standard commercial values are
FIG. 7.52
RD = 3.2 k⍀ 1 3.3 k⍀ Determining VGSQ for the network
RS = 0.4 k⍀ 1 0.39 k⍀ of Fig. 7.51.
454 FET BIASING
EXAMPLE 7.15 For the voltage-divider bias configuration of Fig. 7.53, if VD = 12 V and
VGSQ = -2 V, determine the value of RS.

RD
R1
D
G

S
R2
RS

FIG. 7.53
Example 7.15.

Solution: The level of VG is determined as follows:

47 k⍀(16 V)
VG = = 5.44 V
47 k⍀ + 91 k⍀
VDD - VD
with ID =
RD
16 V - 12 V
= = 2.22 mA
1.8 k⍀
The equation for VGS is then written and the known values substituted:
VGS = VG - IDRS
-2 V = 5.44 V - (2.22 mA)RS
-7.44 V = -(2.22 mA)RS
7.44 V
and RS = = 3.35 k⍀
2.22 mA
The nearest standard commercial value is 3.3 k⍀.

EXAMPLE 7.16 The levels of VDS and ID are specified as VDS = 12VDD and ID = ID(on)
for the network of Fig. 7.54. Determine the levels of VDD and RD.
VDD
Solution: Given ID = ID(on) = 4 mA and VGS = VGS(on) = 6 V, for this configuration,
RD VDS = VGS = 12VDD
10 MΩ and 6 V = 12VDD
so that VDD = 12 V
VGS(on) = 6 V
I D(on) = 4 mA
Applying Eq. (7.42) yields
VGS(Th) = 3 V VRD VDD - VDS VDD - 12VDD 1
2 VDD
RD = = = =
ID ID(on) ID(on) ID(on)
6V
and RD = = 1.5 k⍀
4 mA
FIG. 7.54 which is a standard commercial value.
Example 7.16.
7.12 TROUBLESHOOTING p-CHANNEL FETs 455
●
How often has a network been carefully constructed only to find that when the power is
applied, the response is totally unexpected and fails to match the theoretical calculations?
What is the next step? Is it a bad connection? A misreading of the color code for a resistive
element? An error in the construction process? The range of possibilities seems vast and
often frustrating. The troubleshooting process first described in the analysis of BJT transis-
tor configurations should narrow down the list of possibilities and isolate the problem area
following a definite plan of attack. In general, the process begins with a rechecking of the
network construction and the terminal connections. This is usually followed by the check-
ing of voltage levels between specific terminals and ground or between terminals of the red
network. Seldom are current levels measured since such maneuvers require disturbing the
network structure to insert the meter. Of course, once the voltage levels are obtained, cur-
rent levels can be calculated using Ohm’s law. In any case, some idea of the expected volt-
age or current level must be known for the measurement to have any importance. In total,
therefore, the troubleshooting process can begin with some hope of success only if the black
basic operation of the network is understood along with some expected levels of voltage or
current. For the n-channel JFET amplifier, it is clearly understood that the quiescent value
of VGSQ is limited to 0 V or a negative voltage. For the network of Fig. 7.55, VGSQ is limited
to negative values in the range 0 V to VP. If a meter is hooked up as shown in Fig. 7.55,
with the positive lead (normally red) to the gate and the negative lead (usually black) to the
FIG. 7.55
source, the resulting reading should have a negative sign and a magnitude of a few volts.
Checking the dc operation of the
Any other response should be considered suspicious and needs to be investigated. JFET self-bias configuration.
The level of VDS is typically between 25% and 75% of VDD. A reading of 0 V for VDS
clearly indicates that either the output circuit has an “open” or the JFET is internally short-
circuited between drain and source. If VD is VDD volts, there is obviously no drop across RD,
due to the lack of current through RD, and the connections should be checked for continuity.
If the level of VDS seems inappropriate, the continuity of the output circuit can easily be
checked by grounding the negative lead of the voltmeter and measuring the voltage levels
from VDD to ground using the positive lead. If VD = VDD, the current through RD may be
zero, but there is continuity between VD and VDD. If VS = VDD, the device is not open be-
tween drain and source, but it is also not “on.” The continuity through to VS is confirmed,
however. In this case, it is possible that there is a poor ground connection between RS and
ground that may not be obvious. The internal connection between the wire of the lead and
the terminal connector may have separated. Other possibilities also exist, such as a shorted
device from drain to source, but the troubleshooter will simply have to narrow down the
possible causes for the malfunction.
The continuity of a network can also be checked simply by measuring the voltage across
any resistor of the network (except for RG in the JFET configuration). An indication of 0 V im-
mediately reveals the lack of current through the element due to an open circuit in the network.
The most sensitive element in the BJT and JFET configurations is the amplifier itself.
The application of excessive voltage during the construction or testing phase or the use
of incorrect resistor values resulting in high current levels can destroy the device. If you
question the condition of the amplifier, the best test for the FET is the curve tracer since
it not only reveals whether the device is operable, but also its range of current and voltage
levels. Some testers may reveal that the device is still fundamentally sound but do not reveal
whether its range of operation has been severely reduced.
The development of good troubleshooting techniques comes primarily from experience
and a level of confidence in what to expect and why. There are, of course, times when the
reasons for a strange response seem to disappear mysteriously when you check a network.
In such cases, it is best not to breathe a sigh of relief and continue with the construction.
The cause for such a sensitive “make or break” situation should be found and corrected, or
it may reoccur at the most inopportune moment.

7.13 p-CHANNEL FETs

●
The analysis thus far has been limited solely to n-channel FETs. For p-channel FETs, a
mirror image of the transfer curves is employed, and the defined current directions are
reversed as shown in Fig. 7.56 for the various types of FETs.
456 FET BIASING

D
G

S ID
Q

VGS
Q

(a)

S ID
Q

VGS
Q

(b)

G ID
Q - point Q

S
VGS
Q

(c)

FIG. 7.56
p-Channel configurations: (a) JFET; (b) depletion-type MOSFET;
(c) enhancement-type MOSFET.

Note for each configuration of Fig. 7.56 that each supply voltage is now a negative volt-
age drawing current in the indicated direction. In particular, note that the double-subscript
notation for voltages continues as defined for the n-channel device: VGS, VDS, and so on. In
this case, however, VGS is positive (positive or negative for the depletion-type MOSFET)
and VDS negative.
Due to the similarities between the analysis of n-channel and p-channel devices, one can
assume an n-channel device and reverse the supply voltage and perform the entire analysis.
When the results are obtained, the magnitude of each quantity will be correct, although the
current direction and voltage polarities will have to be reversed. However, the next example
will demonstrate that with the experience gained through the analysis of n-channel devices, p-CHANNEL FETs 457
the analysis of p-channel devices is quite straightforward.

EXAMPLE 7.17 Determine IDQ, VGSQ, and VDS for the p-channel JFET of Fig. 7.57.

ID
RD
R1
+

VDS
+
VGS – –
R2
RS

FIG. 7.57
Example 7.17.

Solution: We have
20 k⍀(-20 V)
VG = = -4.55 V
20 k⍀ + 68 k⍀
Applying Kirchhoff’s voltage law gives
VG - VGS + IDRS = 0
and VGS = VG + IDRS
Choosing ID = 0 mA yields
VGS = VG = -4.55 V
as appearing in Fig. 7.58.

ID (mA)

8
7
6
5
4
I D = 3.4 mA Q- point
Q

2
1

– 5 – 4 –3 – 2 – 1 0 1 2 3 4 VGS
VP
VGS = 1.4 V
Q

FIG. 7.58
Determining the Q-point for the JFET configuration of Fig. 7.57.

Choosing VGS = 0 V, we obtain

VG -4.55 V
ID = - = - = 2.53 mA
RS 1.8 k⍀
as also appearing in Fig. 7.58.
458 FET BIASING The resulting quiescent point from Fig. 7.58 is given by
IDQ = 3.4 mA
VGSQ = 1.4 V
For VDS, Kirchhoff’s voltage law results in
-IDRS + VDS - IDRD + VDD = 0
and VDS = -VDD + ID(RD + RS)
= -20 V + (3.4 mA)(2.7 k⍀ + 1.8 k⍀)
= -20 V + 15.3 V
= ⴚ4.7 V

7.14 UNIVERSAL JFET BIAS CURVE

●
Since the dc solution of a FET configuration requires drawing the transfer curve for each
analysis, a universal curve was developed that can be used for any level of IDSS and VP.
The universal curve for an n-channel JFET or depletion-type MOSFET (for negative val-
ues of VGSQ) is provided in Fig. 7.59. Note that the horizontal axis is not that of VGS but of
a normalized level defined by VGS > 0 VP 0 , the 0 VP 0 indicating that only the magnitude of VP
is to be employed, not its sign. For the vertical axis, the scale is also a normalized level of
ID >IDSS. The result is that when ID = IDSS, the ratio is 1, and when VGS = VP, the ratio
VGS > 0 VP 0 is -1. Note also that the scale for ID >IDSS is on the left rather than on the right as
encountered for ID in past exercises. The additional two scales on the right need an intro-
duction. The vertical scale labeled m can in itself be used to find the solution to fixed-bias
configurations. The other scale, labeled M, is employed along with the m scale to find the

ID VP VGG
I DSS m= M= m

+
RS IDSS VP
1.0 5 1.0

0.8 4 0.8

0.6 3 0.6

Normalized curve
V 2
of ID = I DSS 1 – GS
VP
0.4 2 0.4

0.2 1 0.2

0
–1 – 0.8 – 0.6 – 0.4 – 0.2 0
VGS
VP

FIG. 7.59
Universal JFET bias curve.
solution to voltage-divider configurations. The scaling for m and M come from a mathe- UNIVERSAL JFET 459
matical development involving the network equations and normalized scaling just intro- BIAS CURVE
duced. The description to follow will not concentrate on why the m scale extends from 0 to
5 at VGS > 0 VP 0 = -0.2 and the M scale ranges from 0 to 1 at VGS > 0 VP 0 = 0, but rather on
how to use the resulting scales to obtain a solution for the configurations. The equations
for m and M are the following, with VG as defined by Eq. (7.15):

0 VP 0
m = (7.43)
IDSS RS

VG
M = m * (7.44)
0 VP 0

R2VDD
with VG =
R1 + R2
Keep in mind that the beauty of this approach is the elimination of the need to sketch the
transfer curve for each analysis, that the superposition of the bias line is a great deal easier,
and that the calculations are fewer. The use of the m and M axes is best described by
examples employing the scales. Once the procedure is clearly understood, the analysis can
be quite rapid, with a good measure of accuracy.

EXAMPLE 7.18 Determine the quiescent values of ID and VGS for the network of Fig. 7.60.

I DQ

RD

D
C1 C2
G
+
VGSQ
–S
RG
RS

FIG. 7.60
Example 7.18.

Solution: Calculating the value of m, we obtain

0 VP 0 0 -3 V 0
m = = = 0.31
IDSS RS (6 mA)(1.6 k⍀)
The self-bias line defined by RS is plotted by drawing a straight line from the origin through
a point defined by m = 0.31, as shown in Fig. 7.61.
The resulting Q-point:
ID VGS
= 0.18 and = -0.575
IDSS 0 VP 0
The quiescent values of ID and VGS can then be determined as follows:
IDQ = 0.18IDSS = 0.18(6 mA) = 1.08 mA
and VGSQ = -0.575 0 VP 0 = -0.575(3 V) = ⴚ1.73 V
460 FET BIASING ID VP
M= m
VG G
m=

+
I DSS IDSS RS VP

1.0 5 1.0

0.8 4 0.8

0.6 3 0.6
ID Q - point (Ex. 6.20)
= 0.53
I DSS
m = 0.625

0.4 2 0.4
0.365

ID 0.2 Q - point (Ex. 6.19) 1 0.2

= 0.18
I DSS

m = 0.31

–1.0 –0.8 –0.6 –0.4 –0.2 0

VGS VGS
= –0.575 = –0.26
VP VP

FIG. 7.61
Universal curve for Examples 7.18 and 7.19.

EXAMPLE 7.19 Determine the quiescent values of ID and VGS for the network of Fig. 7.62.

I DQ

RD
R1

C2
C1

+
VGSQ
–
R2
RS

FIG. 7.62
Example 7.19.

Solution: Calculating m gives

0 VP 0 0 -6 V 0
m = = = 0.625
IDSS RS (8 mA)(1.2 k⍀)
Determining VG yields PRACTICAL 461
APPLICATIONS
R2VDD (220 k⍀)(18 V)
VG = = = 3.5 V
R1 + R2 910 k⍀ + 220 k⍀
Finding M, we have
VG 3.5 V
M = m * = 0.625a b = 0.365
ƒVP ƒ 6V
Now that m and M are known, the bias line can be drawn on Fig. 7.61. In particular, note
that even though the levels of IDSS and VP are different for the two networks, the same
universal curve can be employed. First find M on the M axis as shown in Fig. 7.61. Then
draw a horizontal line over to the m axis and, at the point of intersection, add the magni-
tude of m as shown in the figure. Using the resulting point on the m axis and the M inter-
section, draw the straight line to intersect with the transfer curve and define the Q-point.
That is,
ID VGS
= 0.53 and = -0.26
IDSS 0 VP 0
and IDQ = 0.53IDSS = 0.53(8 mA) = 4.24 mA
with VGSQ = -0.26 0 VP 0 = -0.26(6 V) = ⴚ1.56 V

7.15 PRACTICAL APPLICATIONS

●
The applications described here take full advantage of the high input impedance of field-
effect transistors, the isolation that exists between the gate and drain circuits, and the linear
region of JFET characteristics that permit approximating the device by a resistive element
between the drain and source terminals.

Voltage-Controlled Resistor (Noninverting Amplifier)

One of the most common applications of the JFET is as a variable resistor whose resis-
tance value is controlled by the applied dc voltage at the gate terminal. In Fig. 7.63a, the
linear region of a JFET transistor has been clearly indicated. Note that in this region
the various curves all start at the origin and follow a fairly straight path as the drain-to-
source voltage and drain current increase. Recall from your basic dc courses that the plot
of a fixed resistor is nothing more than a straight line with its origin at the intersection
of the axes.
In Fig. 7.63b, the linear region has been expanded to a maximum drain-to-source voltage
of about 0.5 V. Note that even though the curves do have some curvature to them, they can
easily be approximated by fairly straight lines, all having their origin at the intersection of
the axes and a slope determined by the gate-to-source dc voltage. Recall from earlier dis-
cussions that for an I–V plot where the current is the vertical axis and the voltage the
horizontal axis, the steeper the slope, the less is the resistance; and the more horizontal
the curve, the greater is the resistance. The result is that a vertical line has 0 ⍀ resistance
and a horizontal line has infinite resistance. At VGS = 0 V, the slope is the steepest and
the resistance the least. As the gate-to-source voltage becomes increasingly negative, the
slope decreases until it is almost horizontal near the pinch-off voltage.
It is important to remember that this linear region is limited to levels of VDS that are
relatively small compared to the pinch-off voltage. In general, the linear region of a JFET
is defined by VDS f VDSmax and 0 VGS 0 f 0 VP 0 .
Using Ohm’s law, let us calculate the resistance associated with each curve of Fig. 7.63b
using the current that results at a drain-to-source voltage of 0.4 V.
VDS 0.4 V
VGS = 0 V: RDS = = = 100 ⍀
IDS 4 mA
VDS 0.4 V
VGS = -0.5 V: RDS = = = 160 ⍀
IDS 2.5 mA
VDS 0.4 V
VGS = -1 V: RDS = = = 267 ⍀
IDS 1.5 mA
 6. The method of analysis applied to depletion-type MOSFETs is the same as applied to COMPUTER ANALYSIS 471
JFETs, with the only difference being a possible operating point with an ID level
above the IDSS value.
7. The characteristics and method of analysis applied to enhancement-type MOSFETs
are entirely different from those of JFETs and depletion-type MOSFETs. For values
of VGS less than the threshold value, the drain current is 0 A.
8. When analyzing networks with a variety of devices, first work with the region of the
network that will provide a voltage or current level using the basic relationships asso-
ciated with those devices. Then use that level and the appropriate equations to find other
voltage or current levels of the network in the surrounding region of the system.
9. The design process often requires finding a resistance level to establish the desired volt-
age or current level. With this in mind, remember that a resistance level is defined by the
voltage across the resistor divided by the current through the resistor. In the design
process, both of these quantities are often available for a particular resistive element.
10. The ability to troubleshoot a network requires a clear, firm understanding of the termi-
nal behavior of each of the devices in the network. That knowledge will provide an
estimate of the working voltage levels of specific points of the network, which can be
checked with a voltmeter. The ohmmeter section of a multimeter is particularly helpful
in ensuring that there is a true connection between all the elements of the network.
11. The analysis of p-channel FETs is the same as that applied to n-channel FETs except
for the fact that all the voltages will have the opposite polarity and the currents the
opposite direction.

Equations
JFETs/depletion-type MOSFETs:
Fixed@bias configuration: VGS = -VGG = VG
Self@bias configuration: VGS = -ID RS
R2VDD
Voltage@divider biasing: VG =
R1 + R2
VGS = VG - ID RS
Enhancement-type MOSFETs:
Feedback biasing: VDS = VGS
VGS = VDD - ID RD
R2VDD
Voltage@divider biasing: VG =
R1 + R2
VGS = VG - ID RS

7.17 COMPUTER ANALYSIS

●
PSpice Windows
JFET Voltage-Divider Configuration The results of Example 7.19 will now be verified
using PSpice Windows. The network of Fig. 7.72 is constructed using computer methods
described in the previous chapters. The J2N3819 JFET is obtained from the EVAL library,
and Edit-PSpice model is used to set Beta to 0.222 mA/V2 and Vto to -6 V. The Beta
value is determined using beta = IDSS > VP2 Eq. (6.17) and the provided IDSS and VP. The
results of the Simulation appear in Fig. 7.73 with the dc bias voltage and current levels.
The resulting drain current is 4.225 mA, compared to the calculated level of 4.24 mA—an
excellent match. The voltage VGS is 3.504 V - 5.070 V = -1.57 V versus the calculated
level of -1.56 V in Example 7.19—another excellent match.

Combination Network Next, the result of Example 7.12 with both a transistor and JFET
will be verified. For the transistor Bf is set to 180, whereas for the JFET, Beta is set to
0.333 mA/V2 and Vto to -6 V as called for in the example. The results for all the dc levels
appear in Fig. 7.73. Note again the excellent comparison with the calculator solution, with
VD at 11.44 V compared to 11.07 V, VS = VC at 7.138 V compared to 7.32 V, and VGS at
3.380 V - 7.138 V = ⫺3.76 V compared to -3.7 V.
so that FIXED-BIAS 491
CONFIGURATION
Vo
Av = = -gm (rd 储 RD) (8.16)
Vi
If rd Ú 10RD,

Vo
Av = = -gmRD (8.17)
Vi rd Ú 10RD

Phase Relationship The negative sign in the resulting equation for Av clearly reveals a
phase shift of 180° between input and output voltages.

EXAMPLE 8.7 The fixed-bias configuration of Example 7.1 had an operating point defined
by VGSQ = -2 V and IDQ = 5.625 mA, with IDSS = 10 mA and VP = -8 V. The network
is redrawn as Fig. 8.14 with an applied signal Vi. The value of yos is provided as 40 mS.
a. Determine gm.
b. Find rd.
c. Determine Zi.
d. Calculate Zo.
e. Determine the voltage gain Av.
f. Determine Av ignoring the effects of rd.

20 V

RD 2 kΩ
C2
D
C1 +
G IDSS = 10 mA
+ VP = −8 V
RG 1 MΩ S Vo
Vi Zo
Zi –
2V
– + –

FIG. 8.14
JFET configuration for Example 8.7.

Solution:
2IDSS 2(10 mA)
a. gm0 = = = 2.5 mS
0 VP 0 8V
VGSQ (-2 V)
gm = gm0 a 1 - b = 2.5 mS a 1 - b = 1.88 mS
VP (-8 V)
1 1
b. rd = = = 25 k⍀
yos 40 mS
c. Zi = RG = 1 M⍀
d. Zo = RD 储 rd = 2 k 储 25 k = 1.85 k⍀
e. Av = -gm(RD 储 rd) = -(1.88 mS)(1.85 k)
= ⴚ3.48
f. Av = -gmRD = -(1.88 mS)(2 k) = ⴚ3.76
As demonstrated in part (f), a ratio of 25 k:2 k = 12.5:1 between rd and RD results
in a difference of 8% in the solution.
496 FET AMPLIFIERS
EXAMPLE 8.8 The self-bias configuration of Example 7.2 has an operating point defined
by VGSQ = -2.6 V and IDQ = 2.6 mA, with IDSS = 8 mA and VP = -6 V. The network
is redrawn as Fig. 8.20 with an applied signal Vi. The value of gos is given as 20 mS.
a. Determine gm.
b. Find rd.
c. Find Zi.
d. Calculate Zo with and without the effects of rd. Compare the results.
e. Calculate Av with and without the effects of rd. Compare the results.

20 V

RD 3.3 kΩ
C2
D Vo
C1
Vi
G IDSS = 8 mA
VP = −6 V

S
Zi Zo
RG 1 MΩ RS 1 kΩ

FIG. 8.20
Network for Example 8.8.

Solution:
2IDSS 2(8 mA)
a. gm0 = = = 2.67 mS
0 VP 0 6V
VGSQ (-2.6 V)
gm = gm0 a 1 - b = 2.67 mS a 1 - b = 1.51 mS
VP (-6 V)
1 1
b. rd = = = 50 k⍀
yos 20 mS
c. Zi = RG = 1 M
d. With rd,
rd = 50 k 7 10RD = 33 k
Therefore,
Zo = RD = 3.3 k⍀
If rd =  ,
Zo = RD = 3.3 k⍀
e. With rd,
-gmRD -(1.51 mS)(3.3 k)
Av = =
RD + RS 3.3 k + 1 k
1 + gmRS + 1 + (1.51 mS)(1 k) +
rd 50 k
= ⴚ1.92
With rd    (open-circuit equivalence),
-gmRD -(1.51 mS)(3.3 k)
Av = = = ⴚ1.98
1 + gmRS 1 + (1.51 mS)(1 k)
As above, the effect of rd is minimal because the condition rd Ú 10(RD + RS) is satisfied.
Note also that the typical gain of a JFET amplifier is less than that generally encountered
for BJTs of similar configurations. Keep in mind, however, that Zi is magnitudes greater than
the typical Zi of a BJT, which will have a very positive effect on the overall gain of a system.
500 FET AMPLIFIERS Vo - Vi
and Ird =
rd
Applying Kirchhoff’s current law at node b in Fig. 8.25 results in
Ird + ID + gmVgs = 0
and ID = -Ird - gmVgs
Vo - Vi
= -c d - gm 3 -Vi 4
rd
Vi - Vo
ID = + gmVi
rd
Vi - Vo
so that Vo = ID RD = c + gmVi d RD
rd
Vi RD Vo RD
= - + gm
rd rd
RD RD
and Vo c 1 + d = Vi c + gmRD d
rd rd

RD
c gmRD + d
Vo rd
with Av = = (8.38)
Vi RD
c1 + d
rd

For rd Ú 10RD, the factor RD>rd of Eq. (8.38) can be dropped as a good approximation, and

Av ⬵ gmRD (8.39)
rd Ú 10RD

Phase Relationship The fact that Av is a positive number will result in an in-phase rela-
tionship between Vo and Vi for the common-gate configuration.

EXAMPLE 8.9 Although the network of Fig. 8.27 may not initially appear to be of the
common-gate variety, a close examination will reveal that it has all the characteristics of
Fig. 8.24. If VGSQ = -2.2 V and IDQ = 2.03 mA:
a. Determine gm.
b. Find rd.
c. Calculate Zi with and without rd. Compare results.
d. Find Zo with and without rd. Compare results.
e. Determine Vo with and without rd. Compare results.
+12 V

RD 3.6 kΩ

10 μ F
D Vo

IDSS = 10 mA
G
VP = − 4 V
gos = 50 μS

S
+ 10 μ F
Vi = 40 mV RS 1.1 kΩ
–

FIG. 8.27
Network for Example 8.9.
Solution: SOURCE-FOLLOWER 501
(COMMON-DRAIN)
2IDSS 2(10 mA) CONFIGURATION
a. gm0 = = = 5 mS
0 VP 0 4V
VGSQ (-2.2 V)
gm = gm0 a 1 - b = 5 mS a 1 - b = 2.25 mS
VP (-4 V)
1 1
b. rd = = = 20 k⍀
gos 50 mS
c. With rd,
rd + RD 20 k + 3.6 k
Zi = RS 储 c d = 1.1 k 储 c d
1 + gmrd 1 + (2.25 mS)(20 k)
= 1.1 k 储 0.51 k = 0.35 k⍀
Without rd,
Zi = RS 储 1>gm = 1.1 k 储 1>2.25 ms = 1.1 k 储 0.44 k
= 0.31 k⍀
Even though the condition rd Ú 10RD is not satisfied with rd = 20 k and
10RD = 36 k, both equations result in essentially the same level of impedance. In
this case, 1>gm was the predominant factor.
d. With rd,
Zo = RD 储 rd = 3.6 k 储 20 k = 3.05 k⍀
Without rd,
Zo = RD = 3.6 k⍀
Again the condition rd Ú 10RD is not satisfied, but both results are reasonably close.
RD is certainly the predominant factor in this example.
e. With rd,
RD 3.6 k
c gmRD + d c (2.25 mS)(3.6 k) + d
rd 20 k
Av = =
RD 3.6 k
c1 + d c1 + d
rd 20 k
8.1 + 0.18
= = 7.02
1 + 0.18
Vo
and Av = 1 Vo = AvVi = (7.02)(40 mV) = 280.8 mV
Vi
Without rd,
Av = gmRD = (2.25 mS)(3.6 k) = 8.1
with Vo = AvVi = (8.1)(40 mV) = 324 mV
In this case, the difference is a little more noticeable, but not dramatically so.

Example 8.9 demonstrates that even though the condition rd Ú 10RD was not satisfied,
the results for the parameters given were not significantly different using the exact and ap-
proximate equations. In fact, in most cases, the approximate equations can be used to find
a reasonable idea of particular levels with a reduced amount of effort.

8.7 SOURCE-FOLLOWER (COMMON-DRAIN)

CONFIGURATION
●
The JFET equivalent of the BJT emitter-follower configuration is the source-follower con-
figuration of Fig. 8.28. Note that the output is taken off the source terminal and, when the
dc supply is replaced by its short-circuit equivalent, the drain is grounded (hence, the ter-
minology common-drain).
Substituting the JFET equivalent circuit results in the configuration of Fig. 8.29. The
controlled source and the internal output impedance of the JFET are tied to ground at
one end and RS on the other, with Vo across RS. Since gmVgs, rd, and RS are connected to
504 FET AMPLIFIERS Phase Relationship Since Av of Eq. (8.43) is a positive quantity, Vo and Vi are in phase
for the JFET source-follower configuration.

EXAMPLE 8.10 A dc analysis of the source-follower network of Fig. 8.32 results in

VGSQ = -2.86 V and IDQ = 4.56 mA.
a. Determine gm.
b. Find rd.
c. Determine Zi.
d. Calculate Zo with and without rd. Compare results.
e. Determine Av with and without rd. Compare results.

+9 V

IDSS = 16 mA
VP = − 4 V
gos = 25 μS

+ 0.05 μ F

Vi RG 1 MΩ 0.05 μ F
+
Zi
RS 2.2 kΩ Vo
– Zo
–

FIG. 8.32
Network to be analyzed in Example 8.10.

Solution:
2IDSS 2(16 mA)
a. gm0 = = = 8 mS
0 VP 0 4V
VGSQ (-2.86 V)
gm = gm0 a 1 - b = 8 mS a 1 - b = 2.28 mS
VP (-4 V)
1 1
b. rd = = = 40 k⍀
gos 25 mS
c. Zi = RG = 1 M⍀
d. With rd,
Zo = rd 储 RS 储 1>gm = 40 k 储 2.2 k 储 1>2.28 mS
= 40 k 储 2.2 k 储 438.6 
= 362.52 ⍀
which shows that Zo is often relatively small and determined primarily by 1>gm.
Without rd,
Zo = RS 储 1>gm = 2.2 k 储 438.6  = 365.69 ⍀
which shows that rd typically has little effect on Zo.
e. With rd,
gm(rd 储 RS) (2.28 mS)(40 k 储 2.2 k)
Av = =
1 + gm(rd 储 RS) 1 + (2.28 mS)(40 k 储 2.2 k)
(2.28 mS)(2.09 k) 4.77
= = = 0.83
1 + (2.28 mS)(2.09 k) 1 + 4.77
which is less than 1, as predicted above.
 Without rd, DEPLETION-TYPE 505
gm RS MOSFETs
(2.28 mS)(2.2 k)
Av = =
1 + gm RS 1 + (2.28 mS)(2.2 k)
5.02
= = 0.83
1 + 5.02
which shows that rd usually has little effect on the gain of the configuration.

8.8 DEPLETION-TYPE MOSFETs

●
The fact that Shockley’s equation is also applicable to depletion-type MOSFETs
(D-MOSFETs) results in the same equation for gm. In fact, the ac equivalent model for
D-MOSFETs shown in Fig. 8.33 is exactly the same as that employed for JFETs, as shown
in Fig. 8.8.
The only difference offered by D-MOSFETs is that VGSQ can be positive for n-channel de-
vices and negative for p-channel units. The result is that gm can be greater than gm0, as demon-
strated by the example to follow. The range of rd is very similar to that encountered for JFETs.

G G D
D +

G Vgs gmVgs rd

S
S
– S

FIG. 8.33
D-MOSFET ac equivalent model.

EXAMPLE 8.11 The network of Fig. 8.34 was analyzed as Example 7.7, resulting in
VGSQ = 0.35 V and IDQ = 7.6 mA.
a. Determine gm and compare to gm0.
b. Find rd.
c. Sketch the ac equivalent network for Fig. 8.34.
d. Find Zi.
e. Calculate Zo.
f. Find Av.

18 V

RD 1.8 kΩ
C2
R1 110 MΩ
D Vo

IDSS = 6 mA
C1 VP = − 3 V
G
Vi gos = 10 μS

Zi S
Zo
R2 10 MΩ RS 150 Ω CS

FIG. 8.34
Network for Example 8.11.
506 FET AMPLIFIERS Solution:
2IDSS 2(6 mA)
a. gm0 = = = 4 mS
0 VP 0 3V
VGSQ (+0.35 V)
gm = gm0 a 1 - b = 4 mS a 1 - b = 4 mS(1 + 0.117) = 4.47 mS
VP (-3 V)
1 1
b. rd = = = 100 k⍀
yos 10 mS
c. See Fig. 8.35. Note the similarities with the network of Fig. 8.23. Equations (8.28)
through (8.32) are therefore applicable.

G D
+ + +
Zi rd RD Zo
Vi R1 110 MΩ R2 10 MΩ Vgs 4.47 × 10 −3 Vgs 100 kΩ 1.8 kΩ Vo

– – –
S S

FIG. 8.35
AC equivalent circuit for Fig. 8.34.

d. Eq. (8.28): Zi = R1 储 R2 = 10 M 储 110 M = 9.17 M⍀

e. Eq. (8.29): Zo = rd 储 RD = 100 k 储 1.8 k = 1.77 k⍀ ⬵ RD = 1.8 k⍀
f. rd Ú 10RD S 100 k Ú 18 k
Eq. (8.32): Av = -gmRD = -(4.47 mS)(1.8 k) = 8.05

8.9 ENHANCEMENT-TYPE MOSFETs

●
The enhancement-type MOSFET (E-MOSFET) can be either an n-channel (nMOS) or
p-channel (pMOS) device, as shown in Fig. 8.36. The ac small-signal equivalent circuit of
either device is shown in Fig. 8.36, revealing an open-circuit between gate and drain–source
channel and a current source from drain to source having a magnitude dependent on the gate-
to-source voltage. There is an output impedance from drain to source rd, which is usually
provided on specification sheets as a conductance gos or admittance yos. The device transcon-
ductance gm is provided on specification sheets as the forward transfer admittance yfs.
In our analysis of JFETs, an equation for gm was derived from Shockley’s equation. For
E-MOSFETs, the relationship between output current and controlling voltage is defined by
ID = k(VGS - VGS(Th))2

G pMOS
G D
S
+
gmVgs rd
Vgs
D –
S
G nMOS
1 1
gm = gfs = yfs rd = g = y
os os
S

FIG. 8.36
Enhancement MOSFET ac small-signal model.
 1 E-MOSFET DRAIN- 509
and gm W FEEDBACK
RF
CONFIGURATION

so that Av = -gm(RF 储 rd 储 RD) (8.50)

Since RF is usually W rd 储 RD and if rd Ú 10RD,

Av ⬵ -gmRD (8.51)
RF W rd 储 RD, rd Ú 10RD

Phase Relationship The negative sign for Av reveals that Vo and Vi are out of phase
by 180°.

EXAMPLE 8.12 The E-MOSFET of Fig. 8.40 was analyzed in Example 7.10, with the
result that k = 0.24 * 10-3 A>V2, VGSQ = 6.4 V, and IDQ = 2.75 mA.
a. Determine gm.
b. Find rd.
c. Calculate Zi with and without rd. Compare results.
d. Find Zo with and without rd. Compare results.
e. Find Av with and without rd. Compare results.

12 V

RD 2 kΩ

Vo
1 μF
RF 10 MΩ Zo
ID ( on) = 6 mA
Vi VGS ( on) = 8 V
1 μF VGS ( Th) = 3 V
gos = 20 μS
Zi

FIG. 8.40
Drain-feedback amplifier from Example 8.11.

Solution:
a. gm = 2k(VGSQ - VGS(Th)) = 2(0.24 * 10-3 A>V2)(6.4 V - 3 V)
= 1.63 mS
1 1
b. rd = = = 50 k⍀
gos 20 mS
c. With rd,
RF + rd 储 RD 10 M + 50 k 储 2 k
Zi = =
1 + gm(rd 储 RD) 1 + (1.63 mS)(50 k 储 2 k)
10 M + 1.92 k
= = 2.42 M⍀
1 + 3.13
Without rd,
RF 10 M
Zi ⬵ = = 2.53 M⍀
1 + gmRD 1 + (1.63 mS)(2 k)
which shows that since the condition rd Ú 10RD = 50 k Ú 40 k is satisfied, the
results for Zo with or without rd will be quite close.
d. With rd,
Zo = RF 储 rd 储 RD = 10 M 储 50 k 储 2 k = 49.75 k 储 2 k
= 1.92 k⍀
510 FET AMPLIFIERS Without rd,
Zo ⬵ RD = 2 k⍀
again providing very close results.
e. With rd,
Av = -gm(RF 储 rd 储 RD)
= -(1.63 mS)(10 M 储 50 k 储 2 k)
= -(1.63 mS)(1.92 k)
= ⴚ3.21
Without rd,
Av = -gmRD = -(1.63 mS)(2 k)
= ⴚ3.26
which is very close to the above result.

8.11 E-MOSFET VOLTAGE-DIVIDER CONFIGURATION

●
The last E-MOSFET configuration to be examined in detail is the voltage-divider network
of Fig. 8.41. The format is exactly the same as appearing in a number of earlier discussions.
Substituting the ac equivalent network for the E-MOSFET results in the configuration
of Fig. 8.42, which is exactly the same as Fig. 8.23. The result is that Eqs. (8.28) through
(8.32) are applicable, as listed below for the E-MOSFET.

VDD

RD

R1 Vo
D
Zo
C1
G
Vi D
Vi G Vo
S
+
Zi Zi Zo
R2 Vgs
R1 R2 gmVgs rd RD
RS CS
–
S

FIG. 8.41 FIG. 8.42

E-MOSFET voltage-divider configuration. AC equivalent network for the configuration of Fig. 8.41.

Zi

Zi = R1 储 R2 (8.52)

Zo

Zo = rd 储 RD (8.53)

For rd Ú 10RD,

Zo ⬵ Rd rd Ú 10RD
(8.54)

Av

Vo
Av = = -gm(rd 储 RD) (8.55)
Vi
and if rd Ú 10RD, DESIGNING FET 511
AMPLIFIER NETWORKS
Vo
Av = ⬵ -gm RD (8.56)
Vi

8.12 DESIGNING FET AMPLIFIER NETWORKS

●
Design problems at this stage are limited to obtaining a desired dc bias condition or ac
voltage gain. In most cases, the various equations developed are used “in reverse” to define
the parameters necessary to obtain the desired gain, input impedance, or output imped-
ance. To avoid unnecessary complexity during the initial stages of the design, the approxi-
mate equations are often employed because some variation will occur when calculated
resistors are replaced by standard values. Once the initial design is completed, the results
can be tested and refinements made using the complete equations.
Throughout the design procedure be aware that although superposition permits a sepa-
rate analysis and design of the network from a dc and an ac viewpoint, a parameter chosen
in the dc environment will often play an important role in the ac response. In particular,
recall that the resistance RG could be replaced by a short-circuit equivalent in the feedback
configuration because IG ⬵ 0 A for dc conditions, but for the ac analysis, it presents an
important high-impedance path between Vo and Vi. In addition, recall that gm is larger for
operating points closer to the ID axis (VGS = 0 V), requiring that RS be relatively small.
In the unbypassed RS network, a small RS will also contribute to a higher gain, but for the
source-follower, the gain is reduced from its maximum value of 1. In total, simply keep
in mind that network parameters can affect the dc and ac levels in different ways. Often a
balance must be made between a particular operating point and its effect on the ac response.
In most situations, the available dc supply voltage is known, the FET to be employed has
been determined, and the capacitors to be employed at the chosen frequency are defined.
It is then necessary to determine the resistive elements necessary to establish the desired
gain or impedance level. The next three examples determine the required parameters for a
specific gain.

EXAMPLE 8.13 Design the fixed-bias network of Fig. 8.43 to have an ac gain of 10. That
is, determine the value of RD.

VDD (+30 V)

RD

D Vo
C1 IDSS = 10 mA
G
Vi VP = – 4 V
0.1 μF gos = 20 μ S
RG
10 MΩ S

FIG. 8.43
Circuit for desired voltage gain in Example 8.13.

Solution: Since VGSQ = 0 V, the level of gm is gm0. The gain is therefore determined by
Av = -gm(RD 储 rd) = -gm0(RD 储 rd)
2IDSS 2(10 mA)
with gm0 = = = 5 mS
0 VP 0 4V
The result is -10 = -5 mS(RD 储 rd)
10
and RD 储 rd = = 2 k
5 mS
512 FET AMPLIFIERS From the device specifications,
1 1
rd = = = 50 k
gos 20 * 10-6 S
Substituting, we find
RD 储 rd = RD 储 50 k = 2 k
RD(50 k)
and = 2 k
RD + 50 k
or 50RD = 2(RD + 50 k) = 2RD + 100 k
with 48RD = 100 k
100 k
and RD = ⬵ 2.08 k
48
The closest standard value is 2 k⍀ (Appendix D), which would be employed for this
design.
The resulting level of VDSQ is then determined as follows:
VDSQ = VDD - IDQ RD = 30 V - (10 mA)(2 k) = 10 V
The levels of Zi and Zo are set by the levels of RG and RD, respectively. That is,
Zi = RG = 10 M⍀
Zo = RD 储 rd = 2 k 储 50 k = 1.92 k⍀ ⬵ RD = 2 k

EXAMPLE 8.14 Choose the values of RD and RS for the network of Fig. 8.44 that will
result in a gain of 8 using a relatively high level of gm for this device defined at VGSQ = 14VP.

VDD
+20 V

RD
C2
Vo
C1 0.1 μF
0V
Vi RL
0.1 μF 10 MΩ

RG IDSS = 10 mA gm 0 = 5 mS
10 MΩ CS VP = – 4 V
RS 40 μF gos = 20 μ S

FIG. 8.44
Network for desired voltage gain in Example 8.14.

Solution: The operating point is defined by

1 1
VGSQ = VP = (-4 V) = -1 V
4 4
VGSQ 2 (-1 V) 2
and ID = IDSS a 1 - b = 10 mA a 1 - b = 5.625 mA
VP (-4 V)
Determining gm, we obtain
VGSQ
gm = gm0 a 1 - b
VP
(-1 V)
= 5 mS a 1 - b = 3.75 mS
(-4 V)
The magnitude of the ac voltage gain is determined by
0 Av 0 = gm(RD 储 rd)
Substituting known values results in SUMMARY TABLE 513
8 = (3.75 mS)(RD 储 rd)
8
so that RD 储 rd = = 2.13 k
3.75 mS
The level of rd is defined by
1 1
rd = = = 50 k
gos 20 mS
and RD 储 50 k = 2.13 k
with the result that
RD = 2.2 k⍀
which is a standard value.
The level of RS is determined by the dc operating conditions as follows:
VGSQ = -IDRS
-1 V = -(5.625 mA)RS
1V
and RS = = 177.8 
5.625 mA
The closest standard value is 180 ⍀. In this example, RS does not appear in the ac design
because of the shorting effect of CS.

In the next example, RS is unbypassed and the design becomes a bit more complicated.

EXAMPLE 8.15 Determine RD and RS for the network of Fig. 8.44 to establish a gain of 8
if the bypass capacitor CS is removed.
Solution: VGSQ and IDQ are still 1 V and 5.625 mA, respectively, and since the equation
VGS = -ID RS has not changed, RS continues to equal the standard value of 180 ⍀ obtained
in Example 8.14.
The gain of an unbypassed self-bias configuration is
gmRD
Av = -
1 + gmRS
For the moment it is assumed that rd Ú 10(RD + RS). Using the full equation for Av at
this stage of the design would simply complicate the process unnecessarily.
Substituting (for the specified magnitude of 8 for the gain), we obtain
-(3.75 mS)RD (3.75 mS)RD
080 = ` ` =
1 + (3.75 mS)(180 ) 1 + 0.675
and 8(1 + 0.675) = (3.75 mS)RD
13.4
so that RD = = 3.573 k
3.75 mS
with the closest standard value at 3.6 k⍀.
We can now test the condition
rd Ú 10(RD + RS)
We have 50 k Ú 10(3.6 k + 0.18 k) = 10(3.78 k)
and 50 k Ú 37.8 k
which is satisfied—the solution stands!

8.13 SUMMARY TABLE

●
To provide a quick comparison between configurations and offer a listing that can be help-
ful for a variety of reasons, Table 8.1 was developed. The exact and approximate equations
for each important parameter are provided with a typical range of values for each. Although
 TABLE 8.1
Zi, Zo, and Av for various FET configurations

Configuration Zi Zo Vo
Av =
Vi
Fixed-bias
[JFET or D-MOSFET]
Fixed-bias +VDD
[JFET or D-MOSFET] Medium (2 k) Medium (- 10)
RD
C2 High (10 M)
C1
Vo = RD 储 r d = - gm(rd 储 RD)
Vi = RG
Zo ⬵ RD ⬵ - gmRD (rd Ú 10 RD)
RG (rd Ú 10 RD)
Zi
–V
GG
+
Self-bias
bypassed RS
[JFET or D-MOSFET]
Self-bias +VDD
bypassed RS Medium (2 k) Medium (- 10)
[JFET or D-MOSFET] RD High (10 M)
C2
Vo = RD 储 r d = - gm(rd 储 RD)
C1 = RG
Vi
Zo ⬵ RD ⬵ - gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Zi
RG
RS CS

Self-bias
unbypassed RS
[JFET or D-MOSFET]
Low (- 2)
Self-bias +VDD RS
unbypassed RS c 1 + gmRS + dR
rd D gmRD
[JFET or D-MOSFET] RD High (10 M) = =
C2 RS RD RD + RS
Vo c 1 + gmRS + + d 1 + gmRS +
C1 = RG rd rd rd
Vi
Zo
= RD gmRD
Zi rd Ú 10 RD or rd =   ⬵ -
RG 1 + gmRS 3 rd Ú 10 (RD + RS)4
RS

Voltage-divider bias
[JFET or D-MOSFET]
Voltage-divider bias +VDD
[JFET or D-MOSFET]
Medium (2 k) Medium (- 10)
RD High (10 M)
C2
R1
Vo = RD 储 r d = - gm(rd 储 RD)
C1
Vi = R1 储 R2
Zo ⬵ RD ⬵ - gmRD (rd Ú 10 RD)
(rd Ú 10 RD)
Zi
R2
RS CS

514
 TABLE 8.1
(Continued)

Configuration Zi Zo Vo
Av =
Vi
Common-gate
[JFET or D-MOSFET]
Medium (+ 10)
Common-gate +VDD Low (1 k⍀)
[JFET or D-MOSFET] Medium (2 k⍀) RD
RD r d + RD gmRD +
C1 Q1 C2 = RS 储 c d rd
1 + gmrd = RD 储 r d =
Vi Vo RD
1 +
⬵ RD rd
1
Zi RS Zo ⬵ RS 储 (Rd Ú 10 RD)

RG CS gm ⬵ gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Source-follower
[JFET or D-MOSFET]
Low ( 6 1)
Source-follower Low (100 k⍀)
[JFET or D-MOSFET] +VDD
High (10 M⍀) gm(rd 储 RS)
C1 = rd 储 RS 储 1>gm =
Vi 1 + gm(rd 储 RS)
C2 = RG
Zi RG
Vo ⬵ RS 储 1>gm gmRS
RS
(rd Ú 10 RS)
⬵
Zo
1 + gmRS
(rd Ú 10 RS)

Drain-feedback bias
E-MOSFET
Drain-Feedback bias +VDD Medium (1 M⍀)
E-MOSFET Medium (2 k⍀) Medium (- 10)
RD RF + r d 储 RD
RF C2 = = RF 储 r d 储 RD = - gm(RF 储 rd 储 RD)
Vo 1 + gm(rd 储 RD)
C1
Vi RF ⬵ RD ⬵ - gmRD
(RF, rd Ú 10RD)
Zo ⬵ (RF, rd Ú 10RD)
1 + gmRD
Zi (rd Ú 10 RD)

Voltage-divider bias
E-MOSFET
Voltage-divider bias +VDD
E-MOSFET
Medium (2 k⍀) Medium (−10)
RD
C2 Medium (1 M⍀)
R1 D Vo
= RD 储 r d = - gm(rd 储 RD)
C1
G = R1 储 R2
Vi
Zo ⬵ RD ⬵ - gmRD
S (rd Ú 10 RD) (rd Ú 10 RD)
Zi R2 RS

515
 TABLE 8.2

Configuration AvL ⴝ Vo 储 Vi Zi Zo

- gm(RD 储 RL) RG RD

+
Vss Including rd:
–
- gm(RD 储 RL 储 rd) RG RD 储 r d

- gm(RD 储 RL) RG RD
1 + gmRS 1 + gmRS

Including rd:
+
Vs - gm(RD 储 RL) RD
– RG ⬵
RD + RS 1 + gmRS
1 + gmRS +
rd

- gm(RD 储 RL) R 1 储 R2 RD

+
Vs Including rd:
–
- gm(RD 储 RL 储 rd) R 1 储 R2 RD 储 r d ;

gm(RS 储 RL) RG RS 储 1>gm

1 + gm(RS 储 RL)

+ Including rd:
Vs RS
– gmrd(RS 储 RL) gmrdRS
= RG 1 +
rd + RD + gmrd (RS 储 RL) r d + RD

gm(RD 储 RL) RS RD
1 + gmRS
+
Including rd: RS
Vs Zi = RD 储 r d
– gmrdRS
⬵ gm(RD 储 RL) 1 +
r d + RD 储 RL

519
520 FET AMPLIFIERS The input impedance of the cascade amplifier is that of stage 1,

Zi = RG1 (8.67)
and the output impedance is that of stage 2,

Zo = RD2 (8.68)
The main function of cascading stages is the larger overall gain achieved. Since dc bias and
ac calculations for a cascade amplifier follow those derived for the individual stages, an
example will demonstrate the various calculations to determine dc bias and ac operation.

EXAMPLE 8.16 Calculate the dc bias, voltage gain, input impedance, output impedance,
and resulting output voltage for the cascade amplifier shown in Fig. 8.48.

+20 V

2.4 kΩ 2.4 kΩ

D Vo
0.05 μF D 0.05 μF

Vi G IDSS = 10 mA
VP = −4 V G IDSS = 10 mA
10 mV
0.05 μF VP = −4 V

S S
3.3 MΩ 3.3 MΩ
+ +
680 Ω 100 μF 680 Ω 100 μF

FIG. 8.48
Cascade amplifier circuit for Example 8.16.

Solution: Both amplifier stages have the same dc bias. Using dc bias techniques from
Chapter 7 results in
2IDSS 2(10 mA)
VGSQ = -1.9 V, IDQ = 2.8 mA gm0 = = = 5 mS
0 VP 0 0 -4 V 0
and at the dc bias point,
VGSQ -1.9 V
gm = gm0 a 1 - b = (5 mS)a 1 - b = 2.6 mS
VP -4 V
Since the second stage is unloaded

Av2 = -gmRD = -(2.6 mS)(2.4 k⍀) = ⴚ6.24

For the first stage 2.4 k⍀ 储 3.3 M⍀ ⬵ 2.4 k⍀ resulting in the same gain.
The cascade amplifier voltage gain is

Eq. (8.66): Av = Av1Av2 = (-6.2)(-6.2) = 38.4

Take special note of the fact that the total gain is positive.
The output voltage is then
Vo = AvVi = (38.4)(10 mV) = 384 mV
The cascade amplifier input impedance is TROUBLESHOOTING 521
Zi = RG = 3.3 M⍀
The cascade amplifier output impedance (assuming that rd  Æ) is
Zo = RD = 2.4 k⍀

A combination of FET and BJT stages can also be used to provide high voltage gain and
high input impedance, as demonstrated by the next example.

EXAMPLE 8.17 For the cascade amplifier of Fig. 8.49, use the dc bias calculated in
Examples 5.15 and 8.16 to calculate input impedance, output impedance, voltage gain, and
resulting output voltage.

+20 V

2.4 kΩ 15 kΩ 2.2 kΩ
0.5 μF
D C Vo
0.5 μF
Vi G B
1 mV IDSS = 10 mA β = 200
0.05 μF VP = −4 V
S E

3.3 MΩ + 4.7 kΩ +
680 Ω 100 μF 1 kΩ 100 μF

FIG. 8.49
Cascaded JFET-BJT amplifier for Example 8.17.

Solution: Since Ri (stage 2) = 15 k 储 4.7 k 储 200(6.5 ) = 953.6 , the gain of

stage 1 (when loaded by stage 2) is
Av1 = -gm[RD 储 Ri (stage 2)]
= -2.6 mS(2.4 k 储 953.6 ) = -1.77
From Example 5.18, the voltage gain of stage 2 is Av2 = -338.46. The overall voltage
gain is then
Av = Av1Av2 = (-1.77)(-338.46) = 599.1
The output voltage is then
Vo = AvVi = (599.1)(1 mV) ⬇ 0.6 V
The input impedance of the amplifier is that of stage 1,
Zi = 3.3 M⍀
and the output impedance is that of stage 2,
Zo = RD = 2.2 k⍀

8.16 TROUBLESHOOTING
●
As mentioned before, troubleshooting a circuit is a combination of knowing the theory
and having experience using meters and an oscilloscope to check the operation of the
circuit. A good troubleshooter has a sense for what to check based on the behavior of
the networks. This ability is developed through building, testing, and repairing a wide
 7. The voltage gain for the fixed-bias and self-bias JFET configurations (with a bypassed COMPUTER ANALYSIS 531
source capacitance) is the same.
8. The ac analysis of JFETs and depletion-type MOSFETs is the same.
9. The ac equivalent network for an enhancement-type MOSFET is the same as that
employed for JFETs and depletion-type MOSFETs. The only difference is the equa-
tion for gm.
10. The magnitude of the gain of FET networks is typically between 2 and 20. The self-
bias configuration (without a bypass source capacitance) and the source-follower
are low-gain configurations.
11. There is no phase shift between input and output for the source-follower and common-
gate configurations. Most others have a 180° phase shift.
12. The output impedance for most FET configurations is determined primarily by RD.
For the source-follower configuration it is determined by RS and gm.
13. The input impedance for most FET configurations is quite high. However, it is quite
low for the common-gate configuration.
14. When troubleshooting any electronic or mechanical system, always check the
most obvious causes first.

Equations
ID
gm = yfs =
VGS
2IDSS
gm0 =
0 VP 0
VGS
gm = gm0 c 1 - d
VP
ID
gm = gm0
A IDSS
1 VDS
rd = = `
yos ID VGS = constant
For JFET and depletion-type MOSFET configurations, see Tables 8.1 and 8.2.

8.19 COMPUTER ANALYSIS

●
PSpice Windows
JFET Fixed-Bias Configuration The first JFET configuration to be analyzed in the ac
domain will be the fixed-bias configuration of Fig. 8.61, using a JFET with VP  4 V
and IDSS  10 mA. The 10-M resistor was added to act as a path to ground for the
capacitor but is essentially an open circuit for the ac analysis. The J2N3819 n-channel
JFET from the EVAL library was used, and the ac voltage is to be determined at four dif-
ferent points for comparison and review.
The constant Beta is determined by
IDSS 10 mA
Beta = = = 0.625 mA>V2
0 VP 0 2
42V2
and is inserted in the Edit Model dialog box obtained by the sequence EDIT-PROPERTIES.
Vto is also changed to 4 V. The remaining elements of the network are set as described
for the transistor in Chapter 5.
An analysis of the network results in the printout of Fig. 8.62. The CIRCUIT
DESCRIPTION includes all the elements of the network along with their assigned nodes.
In particular, note that Vi is set at 10 mV at a frequency of 10 kHz and a phase angle of 0
 FIG. 14.10
Transistor amplifier with unbypassed emitter resistor (RE) for current-series feedback: (a) amplifier circuit;
(b) ac equivalent circuit without feedback.

With Feedback
Io A -hfe >hie -hfe
Af = = = ⬵ (14.20)
Vs 1 + bA -hfe hie + hfeRE
1 + (-RE)a b
hie + RE
The input and output impedances are calculated as specified in Table 14.2:
hfe RE
Zif = Zi (1 + bA) ⬵ hie a 1 + b = hie + hfe RE (14.21)
hie
hfe RE
Zof = Zo(1 + bA) = RC a 1 + b (14.22)
hie
The voltage gain A with feedback is
Vo IoRC Io -hfe RC
Avf = = = a b RC = Af RC ⬵ (14.23)
Vs Vs Vs hie + hfe RE

EXAMPLE 14.5 Calculate the voltage gain of the circuit of Fig. 14.11.

FIG. 14.11
BJT amplifier with current-series feedback for Example 14.5.
761
762 FEEDBACK AND Solution: Without feedback,
OSCILLATOR CIRCUITS -hfe
Io -120
A = = = = -0.085
Vi hie + RE 900 + 510
Vf
b = = -RE = -510
Io
The factor (1  bA) is then
1 + bA = 1 + (-0.085)(-510) = 44.35
The gain with feedback is then
Io A -0.085
Af = = = = -1.92 * 10-3
Vs 1 + bA 44.35
and the voltage gain with feedback Avf is
Vo
Avf = = Af RC = (-1.92 * 10-3)(2.2 * 103) = ⴚ4.2
Vs
Without feedback (RE = 0), the voltage gain is
-RC -2.2 * 103
Av = = = ⴚ293.3
re 7.5

Voltage-Shunt Feedback
The constant-gain op-amp circuit of Fig. 14.12a provides voltage-shunt feedback. Refer-
ring to Fig. 14.2b and Table 14.1 and the op-amp ideal characteristics Ii = 0, Vi = 0, and
voltage gain of infinity, we have
Vo
A = =  (14.24)
Ii
If -1
b = = (14.25)
Vo Ro

Ro

Ro
If

R1
–
V1
–
Ii ∞ Vo
V1
Is = +
Vo R1
+

(b)
(a)

FIG. 14.12
Voltage-shunt negative feedback amplifier: (a) constant-gain circuit; (b) equivalent circuit.

The gain with feedback is then

Vo Vo A 1
Af = = = = = -Ro (14.26)
Is Ii 1 + bA b
This is a transfer resistance gain. The more usual gain is the voltage gain with feedback,
Vo Is 1 -Ro
Avf = = (-Ro) = (14.27)
Is V1 R1 R1
The circuit of Fig. 14.13 is a voltage-shunt feedback amplifier using an FET with no
feedback, Vf = 0.
Vo
A = ⬵ -gmRDRS (14.28)
Ii
 FEEDBACK AMPLIFIER— 763
PHASE AND FREQUENCY
CONSIDERATIONS

FIG. 14.13
Voltage-shunt feedback amplifier using an FET: (a) circuit; (b) equivalent circuit.

The feedback is
If -1
b = = (14.29)
Vo RF
With feedback, the gain of the circuit is
Vo A -gmRDRS
Af = = =
Is 1 + bA 1 + (-1>RF)(-gmRDRS)
-gmRDRSRF
= (14.30)
RF + gmRDRS
The voltage gain of the circuit with feedback is then
Vo Is -gmRDRSRF 1
Avf = = a b
Is Vs RF + gmRDRS RS
-gmRDRF RF
= = (-gmRD) (14.31)
RF + gmRDRS RF + gmRDRS

EXAMPLE 14.6 Calculate the voltage gain with and without feedback for the circuit of
Fig. 14.13a with values of gm = 5 mS, RD = 5.1 k, RS = 1 k, and RF = 20 k.
Solution: Without feedback, the voltage gain is
Av = -gm RD = -(5 * 10-3)(5.1 * 103) = ⴚ25.5
With feedback the gain is reduced to
RF
Avf = (-gm RD)
RF + gmRDRS
20 * 103
= (-25.5)
(20 * 103) + (5 * 10-3)(5.1 * 103)(1 * 103)
= -25.5(0.44) = ⴚ11.2

14.4 FEEDBACK AMPLIFIER—PHASE AND

FREQUENCY CONSIDERATIONS
●
So far we have considered the operation of a feedback amplifier in which the feedback sig-
nal was opposite to the input signal—negative feedback. In any practical circuit this condi-
tion occurs only for some mid-frequency range of operation. We know that an amplifier
768 FEEDBACK AND that at which the total phase shift is 180°. If one measured the phase shift per RC section,
OSCILLATOR CIRCUITS each section would not provide the same phase shift (although the overall phase shift is
180°). If it were desired to obtain exactly a 60° phase shift for each of three stages, then
emitter-follower stages would be needed for each RC section to prevent each from being
loaded from the following circuit.

FET Phase-Shift Oscillator

A practical version of a phase-shift oscillator circuit is shown in Fig. 14.21a. The circuit is
drawn to show clearly the amplifier and feedback network. The amplifier stage is self-
biased with a capacitor bypassed source resistor RS and a drain bias resistor RD. The FET
device parameters of interest are gm and rd. From FET amplifier theory, the amplifier gain
magnitude is calculated from
0 A 0 = gmRL (14.36)
where RL in this case is the parallel resistance of RD and rd,
RDrd
RL = (14.37)
RD + rd
We shall assume as a very good approximation that the input impedance of the FET ampli-
fier stage is infinite. This assumption is valid as long as the oscillator operating frequency
is low enough so that FET capacitive impedances can be neglected. The output impedance
of the amplifier stage given by RL should also be small compared to the impedance seen
looking into the feedback network so that no attenuation due to loading occurs. In practice,
these considerations are not always negligible, and the amplifier stage gain is then selected
somewhat larger than the needed factor of 29 to assure oscillator action.

FIG. 14.21
Practical phase-shift oscillator circuits: (a) FET version; (b) BJT version.

EXAMPLE 14.7 It is desired to design a phase-shift oscillator (as in Fig. 14.21a) using an
FET having gm = 5000 mS, rd = 40 k, and a feedback circuit value of R = 10 k. Select
the value of C for oscillator operation at 1 kHz and RD for A 7 29 to ensure oscillator action.
Solution: Equation (14.33) is used to solve for the capacitor value. Since f = 1>2pRC16, PHASE-SHIFT 769
we can solve for C: OSCILLATOR

1 1
C = = = 6.5 nF
2pRf16 (6.28)(10 * 10 )(1 * 103)(2.45)
3

Using Eq. (14.36), we solve for RL to provide a gain of, say, A = 40 (this allows for
some loading between RL and the feedback network input impedance):
0 A 0 = gmRL
0A0 40
RL = = = 8 k
gm 5000 * 10-6
Using Eq. (14.37), we solve for RD = 10 k⍀.

Transistor Phase-Shift Oscillator

If a transistor is used as the active element of the amplifier stage, the output of the feed-
back network is loaded appreciably by the relatively low input resistance (hie) of the tran-
sistor. Of course, an emitter-follower input stage followed by a common-emitter amplifier
stage could be used. If a single transistor stage is desired, however, the use of voltage-
shunt feedback (as shown in Fig. 14.21b) is more suitable. In this connection, the feedback
signal is coupled through the feedback resistor R in series with the amplifier stage input
resistance (Ri).
Analysis of the ac circuit provides the following equation for the resulting oscillator
frequency:

1 1
f = (14.38)
2pRC 16 + 4(RC >R)

For the loop gain to be greater than unity, the requirement on the current gain of the tran-
sistor is found to be
R RC
hfe 7 23 + 29 + 4 (14.39)
RC R

IC Phase-Shift Oscillator
As IC circuits have become more popular, they have been adapted to operate in oscillator
circuits. One need buy only an op-amp to obtain an amplifier circuit of stabilized gain set-
ting and incorporate some means of signal feedback to produce an oscillator circuit. For
example, a phase-shift oscillator is shown in Fig. 14.22. The output of the op-amp is fed to
a three-stage RC network, which provides the needed 180° of phase shift (at an attenuation
factor of 1/29). If the op-amp provides gain (set by resistors Ri and Rf) of greater than 29,

FIG. 14.22
Phase-shift oscillator using an op-amp.
770 FEEDBACK AND a loop gain greater than unity results and the circuit acts as an oscillator [oscillator fre-
OSCILLATOR CIRCUITS quency is given by Eq. (14.33)].

14.7 WIEN BRIDGE OSCILLATOR

●
A practical oscillator circuit uses an op-amp and RC bridge circuit, with the oscillator fre-
quency set by the R and C components. Figure 14.23 shows a basic version of a Wien
bridge oscillator circuit. Note the basic bridge connection. Resistors R1 and R2 and capaci-
tors C1 and C2 form the frequency-adjustment elements, and resistors R3 and R4 form part
of the feedback path. The op-amp output is connected as the bridge input at points a and c.
The bridge circuit output at points b and d is the input to the op-amp.
Neglecting loading effects of the op-amp input and output impedances, the analysis of
the bridge circuit results in
R3 R1 C2
= + (14.40)
R4 R2 C1

1
and fo = (14.41)
2p1R1C1R2C2

If, in particular, the values are R1 = R2 = R and C1 = C2 = C, the resulting oscillator

frequency is

1
fo = (14.42)
2pRC

R3
and = 2 (14.43)
R4

Thus a ratio of R3 to R4 greater than 2 will provide sufficient loop gain for the circuit to
oscillate at the frequency calculated using Eq. (14.42).

FIG. 14.23
Wien bridge oscillator circuit using an op-amp amplifier.

EXAMPLE 14.8 Calculate the resonant frequency of the Wien bridge oscillator of
Fig. 14.24.
Solution: Using Eq. (14.42) yields
1 1
fo = = = 3120.7 Hz
2pRC 2p(51 * 10 )(0.001 * 10-6)
3
772 FEEDBACK AND
OSCILLATOR CIRCUITS

FIG. 14.26
Edwin Henry Colpitts (1872–1949) FET Colpitts oscillator.
was a communications pioneer best
known for his invention of the Transistor Colpitts Oscillator A transistor Colpitts oscillator circuit can be made as
Colpitts oscillator. In 1915, his shown in Fig. 14.27. The circuit frequency of oscillation is given by Eq. (14.44).
Western Electric team successfully
demonstrated the first transatlantic
radio telephone. In 1895 he entered
Harvard University where he stud-
ied physics and mathematics. He
received a B.A. in 1896 and a mas-
ter’s degree in 1897 from that insti-
tution. In 1899, Colpitts accepted a
position with American Bell Tele-
phone Company. He moved to
Western Electric in 1907. His col-
league Ralph Hartley invented an
inductive coupling oscillator, which
Colpitts improved in 1915. Colpitts
served in the U.S. Army Signal
Corps during World War I and spent
some time in France as a staff offi-
cer involved with military commu-
nication. Colpitts died at home in
1949 in Orange, New Jersey.
(Courtesy of AT&T Archives and
History Center)

FIG. 14.27
Transistor Colpitts oscillator.

IC Colpitts Oscillator An op-amp Colpitts oscillator circuit is shown in Fig. 14.28. Again, the
op-amp provides the basic amplification needed, and the oscillator frequency is set by an LC
feedback network of a Colpitts configuration. The oscillator frequency is given by Eq. (14.44).

Hartley Oscillator
If the elements in the basic resonant circuit of Fig. 14.25 are X1 and X2 (inductors) and X3
(capacitor), the circuit is a Hartley oscillator.
FET Hartley Oscillator An FET Hartley oscillator circuit is shown in Fig. 14.29. The cir-
cuit is drawn so that the feedback network conforms to the form shown in the basic resonant
circuit (Fig. 14.25). Note, however, that inductors L1 and L2 have a mutual coupling M,
 FIG. 14.28 FIG. 14.29
Op-amp Colpitts oscillator. FET Hartley oscillator.

which must be taken into account in determining the equivalent inductance for the reso-
nant tank circuit. The circuit frequency of oscillation is then given approximately by
1
fo = (14.46)
2p1LeqC
with

Leq = L1 + L2 + 2M (14.47)

Transistor Hartley Oscillator Figure 14.30 shows a transistor Hartley oscillator circuit.
The circuit operates at a frequency given by Eq. (14.46).

Ralph Hartley was born in Nevada

in 1888 and attended the University
of Utah, receiving an A.B. degree in
1909. He became a Rhodes Scholar
at Oxford University in 1910 and
received a B.A. degree in 1912 and
a B.Sc. degree in 1913.
He returned to the United States
and was employed at the Research
Laboratory of the Western Electric
Company. In 1915 he was in charge
of radio receiver development for
Bell Systems. He developed the
Hartley oscillator and also a neutral-
izing circuit to eliminate triode sing-
ing resulting from internal coupling.
During World War I he established
the principles that led to sound-type
directional finders. He retired from
Bell Labs in 1950 and died on May
1, 1970.
(Courtesy of AT&T Archives and
History Center)
FIG. 14.30
Transistor Hartley oscillator circuit.
773
 FIG. 14.33
Crystal-controlled oscillator using a crystal (XTAL) in a series-feedback path: (a) BJT circuit; (b) FET circuit.

shown in Fig. 14.33. Resistors R1, R2, and RE provide a voltage-divider stabilized dc bias
circuit. Capacitor CE provides ac bypass of the emitter resistor, and the RFC coil provides
for dc bias while decoupling any ac signal on the power lines from affecting the output sig-
nal. The voltage feedback from collector to base is a maximum when the crystal impedance
is minimum (in series-resonant mode). The coupling capacitor CC has negligible impedance
at the circuit operating frequency but blocks any dc between collector and base.
The resulting circuit frequency of oscillation is set, then, by the series-resonant fre-
quency of the crystal. Changes in supply voltage, transistor device parameters, and so on,
have no effect on the circuit operating frequency, which is held stabilized by the crystal. The
circuit frequency stability is set by the crystal frequency stability, which is good.

Parallel-Resonant Circuits
Since the parallel-resonant impedance of a crystal is a maximum value, it is connected in
shunt. At the parallel-resonant operating frequency, a crystal appears as an inductive reac-
tance of largest value. Figure 14.34 shows a crystal connected as the inductor element in a

FIG. 14.34
Crystal-controlled oscillator operating in parallel-resonant mode.
775
776 FEEDBACK AND modified Colpitts circuit. The basic dc bias circuit should be evident. Maximum voltage is
OSCILLATOR CIRCUITS developed across the crystal at its parallel-resonant frequency. The voltage is coupled to
the emitter by a capacitor voltage divider—capacitors C1 and C2.
A Miller crystal-controlled oscillator circuit is shown in Fig. 14.35. A tuned LC circuit
in the drain section is adjusted near the crystal parallel-resonant frequency. The maximum
gate–source signal occurs at the crystal antiresonant frequency, controlling the circuit op-
erating frequency.

FIG. 14.35
Miller crystal-controlled oscillator.

Crystal Oscillator
An op-amp can be used in a crystal oscillator as shown in Fig. 14.36. The crystal is con-
nected in the series-resonant path and operates at the crystal series-resonant frequency.
The present circuit has a high gain, so that an output square-wave signal results as shown
in the figure. A pair of Zener diodes is shown at the output to provide output amplitude at
exactly the Zener voltage (VZ).

FIG. 14.36
Crystal oscillator using an op-amp.
14.10 UNIJUNCTION OSCILLATOR UNIJUNCTION 777
● OSCILLATOR
A particular device, the unijunction transistor, can be used in a single-stage oscillator cir-
cuit to provide a pulse signal suitable for digital-circuit applications. The unijunction tran-
sistor can be used in what is called a relaxation oscillator as shown by the basic circuit of
Fig. 14.37. Resistor RT and capacitor CT are the timing components that set the circuit
oscillating rate. The oscillating frequency may be calculated using Eq. (14.48), which
includes the unijunction transistor intrinsic stand-off ratio h as a factor (in addition to RT
and CT) in the oscillator operating frequency:

1
fo ⬵ (14.48)
RT CT ln [1>(1 - h)]

Typically, a unijunction transistor has a stand-off ratio from 0.4 to 0.6. Using a value of
h = 0.5, we get
1 1.44 1.44
fo ⬵ = =
RT CT ln [1>(1 - 0.5)] RT CT ln 2 RT CT
1.5
⬵ (14.49)
RT CT

FIG. 14.37 FIG. 14.38

Basic unijunction oscillator circuit. Unijunction oscillator waveforms.

Capacitor CT is charged through resistor RT toward supply voltage VBB. As long as the ca-
pacitor voltage VE is below a stand-off voltage (VP) set by the voltage across B1  B2 and
the transistor stand-off ratio h,
VP = hVB1VB2 - VD (14.50)
the unijunction emitter lead appears as an open circuit. When the emitter voltage across
capacitor CT exceeds this value (VP), the unijunction circuit fires, discharging the capaci-
tor, after which a new charge cycle begins. When the unijunction fires, a voltage rise is
developed across R1 and a voltage drop is developed across R2 as shown in Fig. 14.38. The
signal at the emitter is a sawtooth voltage waveform that at base 1 is a positive-going pulse
and at base 2 is a negative-going pulse. A few circuit variations of the unijunction oscillator
are provided in Fig. 14.39.
 FIG. 14.39
Some unijunction oscillator circuit configurations.

14.11 SUMMARY
●
Equations
Voltage-series feedback:
Vo A Vs
Af = = , Zif = = Zi + (bA)Zi = Zi(1 + bA),
Vs 1 + bA Ii
V Zo
Zof = =
I (1 + bA)
Voltage-shunt feedback:
A Zi
Af = , Zif =
1 + bA (1 + bA)
Current-series feedback:
V V
Zif = = Zi(1 + bA), Zof = = Zo(1 + bA)
I I
Current shunt feedback:
Zi V
Zif = , Zof = = Zo(1 + bA)
(1 + bA) I
Phase-shift oscillator:
1 1
f = , b =
2pRC16 29
Wien bridge oscillator:
1
fo =
2p1R1C1R2C2
Colpitts oscillator:
1 C1C2
fo = where Ceq =
2p1LCeq C1 + C2
Hartley oscillator:
1
fo = where Leq = L1 + L2 + 2M
2p1LeqC
Unijunction oscillator:
1
fo ⬵
RT CT ln [1>(1 - h)]
778