SECTION 4: MOSFETS

ECE 322 – Electronics I

2 MOSFET Device Introduction

K. Webb ECE 322

 MOSFETs
3

 We now turn our attention to another type of transistor, the

MOSFET:
 Metal Oxide Semiconductor Field Effect Transistor
 Many similarities to the BJT:
 Three terminals
 Voltage at one terminal controls current between the other two
◼ A transconductance device
 Two polarities: N-channel and P-channel MOSFETS
◼ Our focus will primarily be N-channel MOSFETs (NMOS devices)

N-Channel P-Channel
(NMOS): (PMOS):

K. Webb ECE 322

 MOSFETs
4

 MOSFETs are actually four-terminal devices

 Fourth terminal is the body, substrate, or bulk
 The body is often tied to the source, and we can mostly
ignore it
 Discrete devices
 Other times we must account for the body potential effect
on device behavior
 Often the case in integrated circuits

NMOS: PMOS:

K. Webb ECE 322

 Physical Structure - NMOS
5

Sedra/Smith

 P-type substrate
 N+ source and drain
 Metal gate electrode, and source/drain/body contacts
 Thin oxide insulates the gate from the rest of the device
 Region of substrate between the drain and source is the channel
 Channel dimensions: W and L
 We’ll see later why this is called an n-channel (NMOS) device

K. Webb ECE 322

 Terminal Voltages and Currents
6

 Terminal voltages and currents named

as shown
 Again, lower-case 𝑣/𝑖 and upper-case
subscript represents total (AC and DC)
voltage and current
 For an NMOS device in typical
operation:
𝑣𝐺𝑆 ≥ 0
𝑣𝐷𝑆 ≥ 0

 Gate oxide does not allow current to

flow, so
𝑖𝐺 = 0
and
𝑖𝐷 = 𝑖𝑆

K. Webb ECE 322

 MOSFET Operating Regions
7

 Three MOSFET operating regions:

 Cut-off

 Triode

 Saturation

 A MOSFET’s operating region is determined by its

terminal voltages
 Next, we will look in detail at each of these three
regions, along with their 𝑖 − 𝑣 characteristics

K. Webb ECE 322

8 Cut-Off Region

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 Cut-Off Region
9

 Gate and source both

grounded
𝑣𝐺𝑆 = 0

 Drain-to-source pathway looks

like two back-to-back diodes
 Very high drain-source
resistance (𝑟𝐷𝑆 = ∞)
 Even for 𝑣𝐷𝑆 > 0, no current
will flow
𝑖𝐷 = 0

 Looks like an open switch

 Similar to BJT cut-off operation
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10 Triode Region

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 Triode Region – Inversion
11

 Now, 𝑣𝐺𝑆 is increased, while 𝑣𝐷𝑆 is kept small

 Electric field established across gate oxide
 Holes in p-type substrate repelled deeper into substrate
 Electrons from drain and source attracted to region below the gate
 For large enough 𝑣𝐺𝑆 , p-type material below the gate is inverted to n-type
 An inversion layer
 Induced n-type channel connects drain to source
 Now, current can flow in response to 𝑣𝐷𝑆 , 𝑖𝐷 > 0

K. Webb ECE 322

 Threshold Voltage
12

 Channel is induced once 𝑣𝐺𝑆 exceeds a certain voltage:

 The threshold voltage
𝑣𝐺𝑆 ≥ 𝑉𝑡
 A device parameter
 Typically, 𝑉𝑡 = 300 𝑚𝑉 … 1 𝑉
 As 𝑣𝐺𝑆 increases beyond 𝑉𝑡 , the induced channel gets deeper
 As long as 𝑣𝐷𝑆 is small (𝑣𝐷𝑆 ≪ 𝑉𝑡 ), channel depth is uniform

K. Webb ECE 322

 Overdrive Voltage
13

 A channel is induced once 𝑣𝐺𝑆 exceeds the threshold voltage

 𝑣𝐺𝑆 in excess of the threshold voltage is called the overdrive voltage
or effective voltage:
𝑣𝑂𝑉 = 𝑣𝐺𝑆 − 𝑉𝑡

 As we will soon see, 𝑣𝑂𝑉 plays an important role in determining

device behavior

K. Webb ECE 322

 Triode Region
14

 As 𝑣𝐷𝑆 increases:
 Voltage varies along the channel
◼ 𝑣𝑆 near the source, 𝑣𝐷 near the drain
 Gate-to-channel voltage decreases closer to the drain
 Channel depth decreases closer to the drain
◼ Channel is tapered
 More current flows with increasing 𝑣𝐷𝑆 , but channel
resistance increases as channel becomes more tapered
K. Webb ECE 322
 Triode Region - 𝑖-𝑣 Relationship
15

 Drain current in the triode region:

𝑊 1
𝑖𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑣𝐺𝑆 − 𝑉𝑡 − 𝑣𝐷𝑆 𝑣𝐷𝑆
𝐿 2

𝑊 1
𝑖𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑣𝑂𝑉 − 𝑣𝐷𝑆 𝑣𝐷𝑆
𝐿 2
where:
◼ 𝜇𝑛 : electron mobility
◼ 𝐶𝑜𝑥 : oxide capacitance
◼ 𝑊: channel width
◼ 𝐿: channel length

 We can also express the drain current as

𝑊 1 𝑊 1 2
𝑖𝐷 = 𝑘𝑛′ 𝑣𝑂𝑉 − 𝑣𝐷𝑆 𝑣𝐷𝑆 = 𝑘𝑛′ 𝑣𝑂𝑉 𝑣𝐷𝑆 − 𝑣𝐷𝑆
𝐿 2 𝐿 2
where:
◼ 𝑘𝑛′ = 𝜇𝑛 𝐶𝑜𝑥 is the process transconductance parameter
K. Webb ECE 322
 Triode Region - 𝑖-𝑣 Relationship
16

 Triode region:
𝑣𝐺𝑆 > 𝑉𝑡
𝑣𝐷𝑆 < 𝑣𝑂𝑉
 For 𝑣𝐷𝑆 ≪ 𝑣𝑜𝑣
 Nearly a linear resistance
 Resistance linearly
proportional to 𝑣𝑂𝑉
1
𝑟𝐷𝑆 =
𝑊
𝑘𝑛′ 𝑣
𝐿 𝑂𝑉
 As 𝑣𝐷𝑆 increases
 Channel taper increases
 𝑟𝐷𝑆 increases
 𝑖𝐷 -𝑣𝐷𝑆 slope decreases

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17 Saturation Region

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 Device Operation – Channel Pinch-Off
18

 Eventually, for large enough 𝑣𝐷𝑆

 Gate-to-channel voltage near the drain no longer exceeds 𝑉𝑡
 Channel pinch-off occurs
 Channel disappears at the edge of the drain
 Pinch-off occurs when:
𝑣𝐺𝐷 = 𝑉𝑡 = 𝑣𝐺𝑆 − 𝑣𝐷𝑆
𝑣𝐷𝑆 = 𝑣𝐺𝑆 − 𝑉𝑡
𝑣𝐷𝑆 = 𝑣𝑂𝑉
K. Webb ECE 322
 Saturation Region
19

 Once channel pinch-off

occurs:
 Voltage at the drain-end of
the channel remains 𝑣𝑂𝑉 ,
even as 𝑣𝐷𝑆 increases
 Any increase in 𝑣𝐷𝑆 beyond
𝑣𝑂𝑉 is dropped across the
depletion region surrounding
the drain
 Voltage across the length of the channel is fixed at 𝑣𝑂𝑉
 Pinched-off channel shape does not change with 𝑣𝐷𝑆
 Drain current saturates at a constant value for constant 𝑣𝐺𝑆
 Analogous to the forward-active region for BJTs

K. Webb ECE 322

 Saturation - 𝑖-𝑣 Relationship
20

 Drain current in the saturation region still given by

𝑊 1 2
𝑖𝐷 = 𝑘𝑛′ 𝑣𝑂𝑉 𝑣𝐷𝑆 − 𝑣𝐷𝑆
𝐿 2

 But now, the voltage from the drain-end to source-end of

the channel is 𝑣𝑂𝑉
 Replacing 𝑣𝐷𝑆 with 𝑣𝑂𝑉 , the drain current relationship
becomes
1 ′ 𝑊 2 1 ′ 𝑊 2
𝑖𝐷 = 𝑘𝑛 𝑣 = 𝑘 𝑣𝐺𝑆 − 𝑉𝑡
2 𝐿 𝑂𝑉 2 𝑛 𝐿

 Purely a function of 𝑣𝐺𝑆 (or 𝑣𝑂𝑉 )

 Independent of 𝑣𝐷𝑆
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 Input I-V Characteristic
21

 In saturation, drain current

has a quadratic dependence
on 𝑣𝐺𝑆 (𝑣𝑂𝑉 )
1 ′𝑊 2
𝑖𝐷 = 𝑘𝑛 𝑣 − 𝑉𝑡
2 𝐿 𝐺𝑆
1 ′𝑊 2
𝑖𝐷 = 𝑘𝑛 𝑣𝑂𝑉
2 𝐿

K. Webb ECE 322

 Output I-V Characteristic
22

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 NMOS Operating Regions – Summary
23

 Cutoff:
 𝑣𝐺𝑆 < 𝑉𝑡
 𝑖𝐷 = 0

 Triode:
 𝑣𝐺𝑆 > 𝑉𝑡
 𝑣𝐷𝑆 < 𝑣𝑂𝑉 or 𝑣𝐺𝐷 > 𝑉𝑡
𝑊 12 𝑊 1 2
 𝑖𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝐿
𝑣𝑂𝑉 𝑣𝐷𝑆 − 2 𝑣𝐷𝑆 = 𝑘𝑛′ 𝐿
𝑣𝑂𝑉 𝑣𝐷𝑆 − 2 𝑣𝐷𝑆

 Saturation:
 𝑣𝐺𝑆 > 𝑉𝑡
 𝑣𝐷𝑆 > 𝑣𝑂𝑉 or 𝑣𝐺𝐷 < 𝑉𝑡
1 𝑊 2 1 𝑊 2
 𝑖𝐷 = 2 𝑘𝑛′ 𝑣𝐺𝑆 − 𝑉𝑡𝑝 = 2 𝑘𝑛′ 𝑣
𝐿 𝐿 𝑂𝑉

K. Webb ECE 322

24 P-Channel MOSFETs

K. Webb ECE 322

 P-Channel MOSFETs
25

 Voltage polarities and doping types reversed relative to NMOS

 N-type substrate
 P+ drain and source
 Negative threshold voltage: 𝑉𝑡𝑝 < 0
 Negative overdrive voltage: 𝑣𝑂𝑉 = 𝑣𝐺𝑆 − 𝑉𝑡𝑝 < 0
 Channel induced for 𝑣𝐺𝑆 ≤ 𝑉𝑡𝑝
 Substrate connected to source or most positive circuit voltage

K. Webb ECE 322

 PMOS – Operating Regions
26

 Cutoff:
 𝑣𝐺𝑆 > 𝑉𝑡𝑝
 𝑖𝐷 = 0

 Triode:
 𝑣𝐺𝑆 < 𝑉𝑡𝑝 , 𝑣𝐺𝑆 > 𝑉𝑡𝑝
 𝑣𝐷𝑆 > 𝑣𝑂𝑉 , 𝑣𝐷𝑆 < 𝑣𝑂𝑉
𝑊 12 𝑊 1 2
 𝑖𝐷 = 𝜇𝑝 𝐶𝑜𝑥 𝐿
𝑣𝑂𝑉 𝑣𝐷𝑆 − 2 𝑣𝐷𝑆 = 𝑘𝑝′ 𝐿
𝑣𝑂𝑉 𝑣𝐷𝑆 − 2 𝑣𝐷𝑆

 Saturation:
 𝑣𝐺𝑆 < 𝑉𝑡𝑝 , 𝑣𝐺𝑆 > 𝑉𝑡𝑝
 𝑣𝐷𝑆 < 𝑣𝑂𝑉 , 𝑣𝐷𝑆 > 𝑣𝑂𝑉
1 𝑊 2 1 𝑊 2
 𝑖𝐷 = 2 𝑘𝑝′ 𝑣𝐺𝑆 − 𝑉𝑡𝑝 = 2 𝑘𝑝′ 𝑣
𝐿 𝐿 𝑂𝑉

K. Webb ECE 322

 CMOS
27

 Complementary MOS or CMOS

 Both NMOS and PMOS fabricated on the same chip
 P-type substrate
 PMOS devices fabricated in n wells
 Most modern MOS chips are fabricated using CMOS technology

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28 Large-Signal MOSFET Model

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 Equivalent Circuit Models
29

 As was the case for BJTs, we use two types of

equivalent-circuit models for MOSFETs:
 Large-signal model
 Models the transistor’s behavior to DC signals
 Used to determine the transistor’s DC operating point

 Small-signal model
 Models the behavior in response to small signals
 Describes the response to the AC signals to be
amplified
 Properties of the small-signal model determined by the
DC operating point
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 Large-Signal Model – Saturation
30

 Large-signal behavior in the saturation region is modeled by the

following circuit:

 Replace the transistor with the appropriate model to determine the

DC operating point (Q-point)
 Saturation-region bias assumed
 If incorrect, model will say otherwise
 Because 𝑖𝐺 = 0, we generally do not need to explicitly use the
equivalent circuit model for large-signal analysis for MOSFETs
 Often just use the I-V model

K. Webb ECE 322

 DC Operating Point – Example 1
31

 Determine 𝐼𝐷 and 𝑉𝐷 for 𝜇𝑛 = 500

𝑐𝑚2
the following circuit 𝑉⋅𝑠
𝑓𝐹
 Is the device operating in 𝐶𝑜𝑥 = 3.8
𝜇𝑚2
the saturation region?
𝑉𝑡 = 500 𝑚𝑉

𝐿 = 0.5 𝜇𝑚
 The process 𝑊 = 50 𝜇𝑚
transconductance
parameter:
2 −15
𝑚 3.8 × 10 𝐹 𝜇𝐴
𝑘𝑛′ = 𝜇𝑛 𝐶𝑜𝑥 = 500 × 10 −4
⋅ = 190 2
𝑉 ⋅ 𝑠 1 × 10−12 𝑚2 𝑉

 Use the saturation region large-signal model

 I-V model, not necessarily the equivalent-circuit model
 Analysis will indicate if saturation assumption is incorrect

K. Webb ECE 322

 DC Operating Point – Example 1
32

 Drain current in saturation:

1 ′ 𝑊 2
𝐼𝐷 = 𝑘𝑛 𝑉𝐺𝑆 − 𝑉𝑡
2 𝐿
1 𝜇𝐴 50 𝜇𝑚 2
𝐼𝐷 = ⋅ 190 2 ⋅ 800 𝑚𝑉 − 500 𝑚𝑉
2 𝑉 0.5 𝜇𝑚

𝐼𝐷 = 855 𝜇𝐴

 Voltage at the drain:

𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷
𝑉𝐷 = 3.3 𝑉 − 855 𝜇𝐴 ⋅ 1.8 𝑘Ω

𝑉𝐷 = 1.76 𝑉

 The device is operating in the saturation region

 The drain-to-source voltage exceeds the overdrive voltage
𝑉𝐷𝑆 = 𝑉𝐷 = 1.76 𝑉 > 𝑉𝑂𝑉 = 𝑉𝐺𝑆 − 𝑉𝑡 = 300 𝑚𝑉
K. Webb ECE 322
 DC Operating Point – Example 2
33

 For the same circuit, determine

𝑉𝐺𝑆 for 𝑉𝐷 = 1 𝑉 𝑐𝑚2
𝜇𝑛 = 500
 Is the device still operating in the 𝑉⋅𝑠
saturation region? 𝑓𝐹
𝐶𝑜𝑥 = 3.8
𝜇𝑚2
 For 𝑉𝐷 = 1 𝑉 𝑉𝑡 = 500 𝑚𝑉
𝑉𝐷𝐷 − 𝑉𝐷 3.3 𝑉 − 1 𝑉 𝐿 = 0.5 𝜇𝑚
𝐼𝐷 = =
𝑅𝐷 1.8 𝑘Ω
𝑊 = 50 𝜇𝑚
2.3 𝑉
𝐼𝐷 = = 1.28 𝑚𝐴
1.8 𝑘Ω
 Assuming saturation-region operation
1 𝑊 2 1 𝜇𝐴 50 𝜇𝑚 2
𝐼𝐷 = 𝑘𝑛′ 𝑉𝑂𝑉 = ⋅ 190 2 ⋅ ⋅ 𝑉𝑂𝑉 = 1.28 𝑚𝐴
2 𝐿 2 𝑉 0.5 𝜇𝑚

 Solving for the overdrive voltage

𝑉𝑂𝑉 = 367 𝑚𝑉
K. Webb ECE 322
 DC Operating Point – Example 2
34

 The required gate-to-source voltage is

𝑉𝐺𝑆 = 𝑉𝑡 + 𝑉𝑂𝑉
𝑉𝐺𝑆 = 500 𝑚𝑉 + 367 𝑚𝑉
𝑉𝐺𝑆 = 867 𝑚𝑉

 The drain-to-source voltage exceeds

the overdrive voltage
 The transistor is operating in the
saturation region
𝑉𝐷𝑆 = 1𝑉 > 𝑉𝑂𝑉 = 367 𝑚𝑉

K. Webb ECE 322

 DC Operating Point – Example 3
35

 Find 𝑅𝐷 and 𝑅𝑆 for

𝜇𝐴
𝑘𝑛′ = 400
𝐼𝐷 = 200 𝜇𝐴 and 𝑉𝐷 = 200 𝑚𝑉 𝑉2
𝑉𝑡 = 500 𝑚𝑉
 First, determine 𝑅𝐷
𝐿 = 0.5 𝜇𝑚
𝑉𝐷𝐷 − 𝑉𝐷 1 𝑉 − 200 𝑚𝑉
𝑅𝐷 = = 𝑊 = 15 𝜇𝑚
𝐼𝐷 200 𝜇𝐴

𝑅𝐷 = 4 𝑘Ω

 Drain current in saturation is given by

1 𝑊 2 2𝐼𝐷 𝐿
𝐼𝐷 = 𝑘𝑛′ 𝑉 → 𝑉𝑂𝑉 =
2 𝐿 𝑂𝑉 𝑘𝑛′ 𝑊

2 ⋅ 200 𝜇𝐴 0.5𝜇𝑚
𝑉𝑂𝑉 = = 182.6 𝑚𝑉
400 𝜇𝐴/𝑉 2 15 𝜇𝑚

K. Webb ECE 322

 DC Operating Point – Example 3
36

 The gate-to-source voltage is

𝑉𝐺𝑆 = 𝑉𝑡 + 𝑉𝑂𝑉 = 500 𝑚𝑉 + 182.6 𝑚𝑉
𝑉𝐺𝑆 = 683 𝑚𝑉
 The gate is grounded, so the source
voltage is
𝑉𝑆 = 𝑉𝐺 − 𝑉𝐺𝑆 = −683 𝑚𝑉
 The source resistance is given by
𝑉𝑆 − 𝑉𝑆𝑆 −683 𝑚𝑉 − −1 𝑉
𝑅𝑆 = =
𝐼𝐷 200 𝜇𝐴

𝑅𝑆 = 1.59 𝑘Ω

K. Webb ECE 322

 DC Operating Point – Example 4
37

 Find 𝐼𝐷 and 𝑅𝐷 for 𝑉𝐷 = 100 𝑚𝑉 𝑊 𝑚𝐴

 What is the drain-to-source 𝑘𝑛′ =2 2
𝐿 𝑉
resistance, 𝑟𝐷𝑆 ? 𝑉𝑡 = 500 𝑚𝑉

 The device is in the triode region:

𝑉𝑂𝑉 = 𝑉𝐺𝑆 − 𝑉𝑡 = 2 𝑉 − 500 𝑚𝑉 = 1.5 𝑉
𝑉𝐷𝑆 = 100 𝑚𝑉 < 𝑉𝑂𝑉

 Drain current in triode is given by

𝑊 1
𝐼𝐷 = 𝑘𝑛′ 𝑉𝑂𝑉 − 𝑉𝐷𝑆 𝑉𝐷𝑆
𝐿 2
𝑚𝐴
𝐼𝐷 = 2 1.5 𝑉 − 50 𝑚𝑉 100 𝑚𝑉
𝑉2

𝐼𝐷 = 290 𝜇𝐴

K. Webb ECE 322

 DC Operating Point – Example 4
38

 The required drain resistance:

𝑉𝐷𝐷 − 𝑉𝐷 1.9 𝑉
𝑅𝐷 = =
𝐼𝐷 290 𝜇𝐴

𝑅𝐷 = 6.55 𝑘Ω

 The drain-to-source resistance in the triode

region is given by:
1
𝑟𝐷𝑆 =
𝑊
𝑘𝑛′ 𝐿 𝑉𝑂𝑉
1
𝑟𝐷𝑆 =
𝑚𝐴
2 2 1.5 𝑉
𝑉
𝑟𝐷𝑆 = 333 Ω

K. Webb ECE 322

 DC Operating Point – Example 5
39

 Find 𝐼𝐷 , 𝑉𝐺 , 𝑉𝐷 , and 𝑉𝑆 for the

following circuit

 The gate voltage is simply set by the 𝑘𝑛′

𝑊 𝑚𝐴
=1 2
voltage divider 𝐿 𝑉

10 𝑀Ω 𝑉𝑡 = 1 𝑉
𝑉𝐺 = 10 𝑉
10 𝑀Ω + 10 𝑀Ω
𝑉𝐺 = 5 𝑉

 Assuming operation in the saturation region, drain current is

1 ′ 𝑊 2
1 ′ 𝑊 2
𝐼𝐷 = 𝑘𝑛 𝑉𝐺𝑆 − 𝑉𝑡 = 𝑘𝑛 𝑉𝐺 − 𝐼𝐷 𝑅𝑆 − 𝑉𝑡
2 𝐿 2 𝐿
𝑚𝐴 2
𝐼𝐷 = 0.5 5 𝑉 − 𝐼𝐷 𝑅𝑆 − 1 𝑉
𝑉2

K. Webb ECE 322

 DC Operating Point – Example 5
40

𝑚𝐴 2
𝐼𝐷 = 0.5 2 4 𝑉 − 𝐼𝐷 ⋅ 6 𝑘Ω
𝑉
 This is a quadratic equation for 𝐼𝐷
𝐼𝐷 = 18𝐸3 𝐼𝐷2 − 24 𝐼𝐷 + 8𝐸 − 3

 Two possible solutions:

𝐼𝐷 = 889 𝜇𝐴 or 𝐼𝐷 = 500 𝜇𝐴
 For 𝐼𝐷 = 889 𝜇𝐴
𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 = 10 𝑉 − 889 𝜇𝐴 ⋅ 6 𝑘Ω = 4.67 𝑉
𝑉𝑆 = 𝐼𝐷 ⋅ 𝑅𝑆 = 889 𝜇𝐴 ⋅ 6 𝑘Ω = 5.33 𝑉
𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = −333 𝑚𝑉

K. Webb ECE 322

 DC Operating Point – Example 5
41

 For 𝐼𝐷 = 889 𝜇𝐴
 𝑉𝐺𝑆 < 0
 The transistor is in the cut-off region
 The valid solution to the quadratic equation
must be
𝐼𝐷 = 500 𝜇𝐴
 The drain and source voltages are
𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 = 10 𝑉 − 500 𝜇𝐴 ⋅ 6 𝑘Ω

𝑉𝐷 = 7 𝑉

𝑉𝑆 = 𝐼𝐷 ⋅ 𝑅𝑆 = 500 𝜇𝐴 ⋅ 6 𝑘Ω

𝑉𝑆 = 3 𝑉

K. Webb ECE 322

42 Channel-Length Modulation

K. Webb ECE 322

 Channel-Length Modulation
43

 So far, our MOSFET model in the saturation region models drain

current as independent of 𝑣𝐷𝑆
1 ′ 𝑊 2
𝑖𝐷 = 𝑘𝑛 𝑣𝑂𝑉
2 𝐿
 Flat I-V characteristic in the saturation region
 In reality, current increases as 𝑣𝐷𝑆 increases

 Increase in 𝑖𝐷 due to channel-length modulation

K. Webb ECE 322
 Channel-Length Modulation
44

 Justification for constant saturation current was:

 Channel shape does not change after pinch-off occurs
 Any additional 𝑣𝐷𝑆 is dropped across the depletion region
surrounding the drain
 But, as 𝑣𝐷𝑆 increases, the drain depletion region increases,
and the channel length decreases

K. Webb ECE 322

 Channel-Length Modulation
45

 Drain current is inversely proportional to channel length

1
𝑖𝐷 ∝
𝐿
 So, as 𝑣𝐷𝑆 increases, 𝐿 decreases, and 𝑖𝐷 increases
 Non-zero slope in the saturation region of the 𝑖𝐷 -𝑣𝐷𝑆 curve:

K. Webb ECE 322

 Channel-Length Modulation
46

 This effect is accounted for by the channel-length

modulation parameter, 𝜆
1 ′𝑊 2
𝑖𝐷 = 𝑘𝑛 𝑣𝐺𝑆 − 𝑉𝑡 1 + 𝜆𝑣𝐷𝑆
2 𝐿
 𝜆 is inversely proportional to channel length, 𝐿
1
 𝜆 related to the Early voltage: 𝜆 =
𝑉𝐴

K. Webb ECE 322

 Output Resistance
47

 Slope of the 𝑖𝐷 -𝑣𝐷𝑆 characteristic is the inverse of the

transistor’s output resistance
 Resistance seen looking into the drain
 Constant saturation current implies infinite output
resistance

K. Webb ECE 322

 Output Resistance
48

 Output resistance given by

−1
𝜕𝑖𝐷
𝑟𝑜 =
𝜕𝑣𝐷𝑆
 The inverse of the slope of the 𝑖𝐷 -𝑣𝐷𝑆 characteristic
 Channel-length modulation results in finite output resistance

K. Webb ECE 322

 Output Resistance
49

 Model the finite output resistance due to channel-length modulation

by adding a resistor to our large-signal model

 Output resistance given by

−1 −1
𝜕𝑖𝐷 𝜕 1 ′𝑊 2
𝑟𝑜 = = 𝑘 𝑣 − 𝑉𝑡 1 + 𝜆𝑣𝐷𝑆
𝜕𝑣𝐷𝑆 𝜕𝑣𝐷𝑆 2 𝑛 𝐿 𝐺𝑆

−1
𝜆 ′𝑊 2
𝑟𝑜 = 𝑘𝑛 𝑣 − 𝑉𝑡
2 𝐿 𝐺𝑆
1 𝑉𝐴
𝑟𝑜 = =
𝜆𝐼𝐷′ 𝐼𝐷′

K. Webb ECE 322

50 The Body Effect

K. Webb ECE 322

 The Body Effect
51

 So far, we have largely ignored the connection to the

substrate
 Equivalently, we have assumed it to be tied to the source:
NMOS: PMOS:

 This a valid assumption for discrete devices

 Not so for MOSFETs on integrated circuits (ICs)

K. Webb ECE 322

 The Body Effect
52

 For integrated circuits, the substrate is typically tied

to the most negative supply voltage for NMOS
devices
 PMOS n-wells tied to the most positive supply voltage
 Substrate for a given device may well be biased
below its source voltage (above for PMOS)
 This is the bias voltage for the channel region
 For 𝑉𝑆𝐵 > 0 (𝑉𝑆𝐵 < 0 for PMOS), the threshold
voltage is effectively increased
 This is the body effect

K. Webb ECE 322

53 MOSFETs as Switches

K. Webb ECE 322

 MOSFETs as Switches
54

 Our focus is on the use of MOSFETs for linear

amplifiers in analog circuits
 Operation in the saturation region
 MOSFETs are also useful as switches in digital
circuits
 Microprocessors contain billions of MOSFETs used as
switches on a single chip
 When operating as a switch, MOSFETs alternate
between the triode (on, closed) and cutoff (off,
open) regions

K. Webb ECE 322

 Triode/Cutoff Region Models
55

 MOSFETs used as switches operate alternately in the triode (closed)

and cutoff (open) regions
 Equivalent circuit models:

Triode Region (ON): Cutoff Region (OFF):

 𝑉𝐺𝑆 > 𝑉𝑡  𝑉𝐺𝑆 < 𝑉𝑡

◼ 𝑉𝐺𝑆 = 𝑉𝐷𝐷 ◼ 𝑉𝐺𝑆 = 0

 Switch is on  Switch is off

 𝐼𝐷 ≥ 0  𝐼𝐷 = 0
 𝑉𝐷𝑆 = 𝐼𝐷 𝑟𝐷𝑆 < 𝑉𝑂𝑉  𝑉𝐷𝑆 = 𝑉𝐷𝐷

K. Webb ECE 322

 Inverters
56

 The inverter is a fundamental building block of digital

logic circuits
 Output is the inverse of the input
 When the input is a logic high (1/T) the output is low (0/F)
 When the input is low (0/F) the output is high (1/T)

K. Webb ECE 322

 CMOS Inverter
57

 CMOS inverters make use of

NMOS and PMOS devices
acting as switches
 Input applied to gate of each
device
 Output taken from their drain
terminals
 When one switch is on, the
other is off
 Output connected to either
VDD or ground

K. Webb ECE 322

 CMOS Inverter
58

 Input is high:
 𝑉𝐼 = 𝑉𝐷𝐷

 𝑉𝐺𝑆𝑝 = 0 𝑉 < 𝑉𝑡𝑝

◼ PMOS device is off

 𝑉𝐺𝑆𝑛 = 𝑉𝐷𝐷 > 𝑉𝑡𝑛

◼ NMOS device is on
 𝑉𝑂 ≈ 0 𝑉

K. Webb ECE 322

 CMOS Inverter
59

 Input is low:
 𝑉𝐼 =0𝑉

 𝑉𝐺𝑆𝑝 = 𝑉𝐷𝐷 > 𝑉𝑡𝑝

◼ PMOS device is on

 𝑉𝐺𝑆𝑛 = 0 𝑉 < 𝑉𝑡𝑛

◼ NMOS device is off
 𝑉𝑂 ≈ 𝑉𝐷𝐷

K. Webb ECE 322

60 Small-Signal Models

K. Webb ECE 322

 MOSFET Small-Signal Hybrid-𝜋 Model
61

 Just as with BJTs, we use the large-signal model to determine

the MOSFET’s DC operating point
 DC terminal voltages and drain
current
 Need a small-signal model to
describes the MOSFETs
response to small signals
 To describe its behavior as an
amplifier

 Small-signal model parameters

determined by the DC
operating point

K. Webb ECE 322

 MOSFET Small-Signal Hybrid-𝜋 Model
62

 Similar to the BJT hybrid-𝜋 model

 But, input resistance at the gate is infinite:
𝑖𝑔 = 0

 Transconductance, 𝑔𝑚 , defined as
𝜕𝑖𝑑
𝑔𝑚 ≡
𝜕𝑣𝑔𝑠
 Where 𝑖𝑑 and 𝑣𝑔𝑠 are the small-signal components of the drain current
and gate-source voltage , respectively
 Transconductance determined by the DC operating point:
𝑊
𝑔𝑚 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑡
𝐿
𝑊
𝑔𝑚 = 𝑘𝑛′ 𝑉
𝐿 𝑂𝑉
K. Webb ECE 322
 MOSFET Small-Signal Hybrid-𝜋 Model
63

𝑊
𝑔𝑚 = 𝑘𝑛′ 𝑉
𝐿 𝑂𝑉
 Recall that DC drain current is given by
1 ′ 𝑊 2
𝐼𝐷 = 𝑘𝑛 𝑉
2 𝐿 𝑂𝑉
 Solving for 𝑉𝑂𝑉 :
2𝐼𝐷
𝑉𝑂𝑉 =
𝑊
𝑘𝑛′ 𝐿

 Substituting the 𝑉𝑂𝑉 expression into the 𝑔𝑚 expression:

𝑊 2𝐼𝐷 𝑊
𝑔𝑚 = 𝑘𝑛′ = 2𝑘𝑛′ 𝐼
𝐿 𝑊
𝑘𝑛′ 𝐿 𝐿 𝐷

K. Webb ECE 322

 MOSFET Small-Signal T-Model
64

 An alternative small-signal
MOSFET model is the T-model
 As with the BJT T-model, useful
when there is source resistance
 Though not immediately
obvious, note that 𝑖𝑔 = 0
𝑖𝑑 = 𝑖𝑠 = 𝑔𝑚 𝑣𝑔𝑠

 Resistance seen looking into

the source:
1
𝑅𝑠 =
𝑔𝑚

K. Webb ECE 322

 MOSFET Small-Signal Models
65

 In summary:
 Transconductance in terms
of overdrive voltage:

𝑊
𝑔𝑚 = 𝑘𝑛′ 𝑉
𝐿 𝑂𝑉

 Transconductance in terms
of drain current:

𝑊
𝑔𝑚 = 2𝑘𝑛′ 𝐼𝐷
𝐿

K. Webb ECE 322

 Small-Signal Models – Finite 𝑟𝑜
66

 We have seen that we can add output resistance to the

large-signal model to account for channel-length
modulation
 Can do the same for the small-signal model
 Will rarely, if ever, do this for the large signal model, but often will
for the small-signal model

𝑉𝐴
𝑟𝑜 =
𝐼𝐷

1
𝑉𝐴 =
𝜆

1 𝑊 2
𝐼𝐷 = 𝑘𝑛′ 𝑉
2 𝐿 𝑂𝑉
K. Webb ECE 322
 Using the MOSFET Models
67

 In the next section of the course, we will look at the

analysis and design of MOSFET amplifiers
 Biasnetwork and DC operating point
 Signal-path

 As was the case for BJT amplifiers, our general

procedure will be:
 Large-signal analysis
◼ DCoperating point
◼ Small-signal model parameters
 Small-signal analysis
◼ Circuit gain

K. Webb ECE 322