r

, ..

Field .Effect ,ransl .

'
'
.'

~ ; ~,'!7,r.,J~Y,,~r~.,~!i.be~.~ylJ~~ ~~------------,
Types of FETs, basics of construction and working principle; MOSFET structure and 1-V characteristics.
MOSFET as a switch. MOSFET as an amplifier. ·

DC Circuit Analysis : Types of biasing circuits of MOSFET (Numerical), de load line and region of
operation. ·

AC Circuit Analysis: Small signal model of MOSFET CS amplifier, derivation of expressions for voltage .
gain. and output impedance of MOSFET CS amplifier (Numerical).

3.1 INTRODUCTION to JFET .............. ... .... .... .... .... ..... ..... ..... ... ... ....... .. ........... ............. ...... ............ .... ......................... -:- ····· 3-4
UQ. Draw and explain the construction of Junction Field Effect Transistor. ..... 3-4
GQ. Explain JFET with the help of construction and V-I characteristics, how it is different than BJT ....... .............. 3-4
3.1.1 Construction of N-JFET and Symbol ............. .......... ...... .. ................. ... .. .......................................................... 3-4
GQ. Explain construction of N-channel JFET, explain frequency limitation factors ... ................. .... ........................ 3-4
3.1 .2 Construction of P-JFET and Symbol ................ ... ..... .. ...... .. .......................................... .. .. .. ......................... ..... 3-5
GQ. Draw and explain with suitable diagrams construction of P-channel JFET. Als? draw symbol used .............. 3-5
3.1.3 Operation of N-Channel JFET ... ................ ...... .... .. .. ... ........... :.... .: ............. .................. .................................... 3-6
UQ. Write short note on : Input and output characteristics of FET. ............... ... 3-6
UQ. Explain input and output characteristic of FET. ....................... ................... 3-6
GQ. Explain characteristics (Drain and Transfer) for N-channel JFET.............................. ................................ ..... 3-6
GQ. Write short note on : Regions of operation of FET ........ ...............:··.. ·· .. ·· ......... ..................................... ...... ..... 3-6
3.1.4 Transfer Characteristics of N-JFET :....................... ........................................................................................ 3-8
UQ. Write short note on: Transfer characteristics 9f FET. ............................. 3-8
GQ. Draw transfer characteristics of JFET using drain or output characteristics .......... .. ........................................ 3-8
GQ. Why JFET is known as "SQUARE LAW DEVICE"? .......... :.... ........... .............................................................. . 3-8
3. . Comparison between N and P Channel JFET .......... ....... ........ ..................................... .... ............................... 3-9
15
GQ. Explain difference between N-channel and P-channel JFET......................... .......... ....... ................................. 3-9
. . Comparison between CS and CE Output Characteristics ...... :...................................................................... 3-10
316
GQ. Compare output characteristics of Common Emitter (CE) and Common Source (CS) amplifier................... 3-10
3.2 INTRODUCTION TO MOSFETS ···· ··· ............................................................._. ............................................................ 3-11

UQ. What is MOSFET ? ···.. ········ .. ... ······ ··· .. ·........ ··· ... ·· ·................ ··.......... ·· ··· 3-11
UQ. What are the types of MOSFET ? (MU - a. 3(b . Dec . 15. 2 Marks .. ·· ...................................................... 3-11

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 lil Analog Electronics (MU-Sem.3-Electrical) 3-2 Field Effect Trans·1
stor
3.3 CONSTRuc11ON OF N-CHANNEL E-MOSFET ............................................·............................................................. 3-,,
UQ. Draw and explain N-channel Enhancement MOSFET with the help of suitable diagram .
(MU - a. 2(b). Ma 14. a. 2 a). ....................................................................................... a.,,
Dec. 14. 5 Marks
UQ. Explain the construction of N-channel Enhancement MOSFET with the help of suitable diagram .
(MU - a. 3 b) . Dec. 13. a. 3(b). Ma 15. 5 Marks) .............................................................................. . . . . a.,,
UQ. Explain construction of MOSFET. MU - a. 3 b. Dec. 15. a. 1(e). Dec. 18. s Marks) ................................. 3-,1
I
GQ. Draw a diagram showing constructional details of NEMOSFET. Write key points rega rd ing construction ... 3-11
I 3.4 THRESHOLD VOLTAGE AND FORMATION OF CHANNEL.. .................................................................................... 3-13
GQ. What is threshold voltage (VTN or VGs(TH,)? ................................................................................................... 3-13

Ii I
3.5
GQ. Explain in detail how channel is formed in NEMOSFET once VGs reaches to threshold voltage (VTN) ......... 3-13
STEP BY STEP OPERATION OF NEMOS WITH OUTPUT CHARACTERISTICS AND EQUATIONS ..................... 3-14
UQ. Draw and explain N-channel Enhancement MOSFET with the help of suitable diagram and equation .
(MU - 0. 2 b). Ma 14. 5 Marks) ................................................................................................................... 3-14
UQ. Draw and explain N-channel FET with the help of suitable diagram and equations .
(MU - a. 2 a). Dec. 14. 5 Marks ......................................................................... .......................................... 3-14
UQ. Explain the characteristics of Enhancement MOSFET. MU - a. 3(b). Ma 15. 5 Marks) ............................. 3-14
GQ. Explain operation of NEMOS step by step ..................................................................................................... 3-14
I
GQ. Explain how does current 10 flows, once channel pinches off ? ........................... .......................................... 3-17
I.
I 3.6 OUTPUT CHARACTERISTIC of NEMOS at CONSTANT VG 5 ........ .. .. ... .... .. ....... ...... .. .... ...................... ...................... 3-18
GQ. Draw an ideal output (Drain) characteristics of NEMOS with VGs constant and show different regions of
operation with equations ...... .. .................. .......................... ............................................................................ 3-18
GQ. Write equations and draw output characteristics of NEMOS for different regions ....................... :................. 3-18
I
!I
ll I
3.7
DRAIN AND TRANSFER CHARACTERISTICS OF NEMOS ............................... .. ... .................................................. 3-18
',.
GQ. Draw drain and transfer characteristics of NEMOS with necessary parameters .. .. ....................................... 3-18
GQ. Draw output and transfer characteristics of NEMOS. Show different regions ......................................... ...... 3-18
3.8
OPERATION AND CHARACTERISTIC OF PEMOSFET ...... .. ........................... ..... .'............ ....................................... 3-19
GQ.
With the help of diagram show different steps of ~peration of PEMOS ......................................................... 3-19
3.8.1
Operation of PEMOSFET ................................................................................. .. ........................................... 3-19
3.8.2 Output and Transfer Characteristics of PEMOSFET ..................................................................................... 3-20
GQ. Draw output and transfer characteristics of PEMOSFET.. ............................................................................. 3-20
3.9
MOSFET CONFIGURATIONS ...................................................................................... ................: .............................. 3-20
GQ. Whafare the different configurations in which MOSFET can be connected ? Compare .............................. 3-20
3.10
DEPLETION MOSFETS (D OR DE MOSFET) ............................................................................................................ 3-21
GQ. Explain structure of DMOSFET. Explain its operation for different values of vGs• Draw output and transfer
characteristics of NDMOSFET....................................................................................................................... 3-21
GQ. Explain with construction working and chacacteristic operation of n-channel D-MOSFET. Also compare it with
E-MOSFET.................................................. . 3-21
3.11
. ·································································································
MOSFET AS SWITCH ........................................................................................... . . 3-23
3.11.1 ·····················································
Applications .................................................................................................................................................... 3-23
GQ. Which are important area where MOSFET is being used as a switch ? ..... . .. ....... 3-23
3.11.2 Drawbacks of a Non-ideal Switch ..... ..... ............................ . ··································'····· . 3-24
···········································································
-.:;-:--::--::-:-::---:----:;:~~--:
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 ~ Analog Electronics (MU-Sem.3-Electrical) 3-3
Field Effect Transistor

3 24
GQ. Compare to an ideal switch, What are the shortcomings of a non-ideal switch .................. •·•··•·•··················· -

3.11.3 Operation of MOS as Switch and Its Advantages .......................................................................................... 3-25

3 25
GQ. Explain working of MOSFET as a switch in VLSI circuits .............................................................................. -

GQ. Explain the MOSFET as switch in VLSI. ........................................................................................................ 3-25

Advantages of MOSFET as a Switch in VLSI ................................................................................................ 3-26

3.11 .4
3-26
GQ. What are th e advahtages if MOSFET is used as a switch ? ...................... ............ .............................. •
3-27
3.12 BIASING OF MOSFETS ······································································································
····················· ·····················
UQ. Compare different biasing methods of JFET. ....... ....................................... 3-27

3.12.1 Drain to Gate Feedback Biasing .................................................................................................................... 3-27

3.12.2 Potential Divider (P ) Bias with Source (S) Feedback .................... ..................... .......................................... 3-29
0

3-30
3.13 PROBLEMS ON MOSFET BIASING (ANALYSIS AND DESIGN) ...............................................................................

3. 13.1 Design of Biasing Circuits .......... ........ ..... ....................................................................................................... 3-34

.. 3-38
3.14 LARGE SIGNAL TRANSFER CHARACTER ISTICS OF MOSFET ............ .....................·..........................................
GQ. Draw large signal transfer characteristics (V1 v/s V0) of NEMOS connected in the form of basic amplifier... 3-38
3-39
3.15 MOSFET AS AN AMPLIFIER ........ ................ .............................. .. ....... ... ................ ....................................................

UQ. Explain FET as differential amplifier. (MU - a. 1 (e). Dec. 13. 5 Marks) ..................................................... 3-39

UQ. Write a short note on : FET differenti13I amplifier (MU - a. 6. Ma 14. 10 Marks ·······································3-39

GQ. With the help of large signal transfer characteristics explain how MOSFET can be used as an amplifier.... 3-39
3-40
3.16 SMALL SIGNAL MODEL OF MOSFET .... .. .. .......... ............ ..... ................... ..... ............................................................

GQ. · Draw small signal model of MOSFET and explain importance of each parameter...... ................................. 3-40
3-41
3.17 MODELLING THE BODY EFFECT ......................... .................................... ...... .. .........................................................
....... 3-42
3.18 EQUATIONS FOR gm AND r0 OF MOSFET .........................................................................................................

GQ. Derive equation for transconduct ance (gm) and dynamic output resistance (r0 ) of MOSFET........................ 3-42
....... 3-43
3.19 MF AC ANALYSIS OF COMMON SOURCE AMPLIFIER ....................................................................................

3.19.1 Key Points to Draw AC Equivalent of Given Common Source Amplifier ....................................................... 3-43

3.19.2 Transfer of Resistance From S to D .......................................... .... ................................................................ 3-44

GQ. How to transfer Resistance from S to D ? ............... •· •·· •·· •••. •............................................................................ 3-44
.......... 3-45
3.20 TYPE I - EXAMPLES ON MF AC ANALYSIS OF CS AMPLIFIER ..... ...............................................................

•3.20.1 Examples with Rs Bypassed (or Rs= 0) •······································································································ 3-45

3.20.2 TYPE II - Examples With Rs Unbypassed ···················································································· ················ 3-48

• CHAPTER END ...........................................................................................................................................................3-51

_.,4 SACHJN SH.411 Yeature

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I 3.1 INTRODUCTION to JFET

There are two types of JFETs,
'
li
I
- -•-.--.·-· ..... . . - ..... ---- - --- -... -- -- - --- -- --- ---- - - - - --- - --.. -- -- ------ - .
: uo:· Draw and explain the construction of Junction Aeld :
(1) P-channel and

(2) N-channel.
l·. Effect Transistor. (MU - a. 1 f), Dec.
· 15. 5 Marks) :
I ''\. "
As in the case of BIT, N-channel JFET is nonnauy
: GQ. Explain JFET With the help of construction and V-1:
used with a well known reason that current in the
l ,
I •• •
characteristics, how it Is different than BJT.
• • .. .... • .. • • '- . .... ........ .. • .... ...... • .. .. .... .. .... • ...... ..........
.. ...... ..... .... .... .. • ...... • • ..
i N-channel JFET is due to electrons.
J

A JFET is a voltage operated device that can be used Electrons are having high mobility compared to holes•
in amplifiers and switching circuits, similar to BIT. therefore N-JFETs are fast responding and can be very'
Unlike BIT, a JFET requires virtually no input current. conveniently used in HF applications .
This gives an extremely high input resistance. With
very high input resistance. Potential
n
barrier or intemaily
generated field
JFET can be used in the applications , where problem of N-bar
(15 to 20 Kn)
"source getting loaded" is very high. It means use of
JFET reduces loading problem.
Like BIT, there are two types of JFETs, also namely
n-channel JFET (N-JFET) and p-channel JFET
(P-JFET). In N-JFET the main current through device ________ \ ----- -- Width of
is due to electrons while in P-JFET the current is due to
l n-channel depletion region
holes. (D) on n-bar side

Ohmic _ / S(Source)
contact

DSG W - Width of n-channel

D - Width of Depletion region
~ ~ D
Bottom view \_,/G (1G1)Fig. 3.1.2 : N-JFET
Bottom view
Fig. 3.1.2 shows the construction of N-channel JFET
DSG
with its symbol.

s- Source (a) (Refer Fig. 3.1.2) N-JFET consists of long N-bar

~oGTop view
□- Drain
G- Gate (15 to 20 kQ). Surfaces of bar (less in length) are taken
out in the form of a lead, (via o}lmic contacts) are
known as Drain (D) and Source (S). While sides which
..a.. are long in length are doped heavily with acceptor
Side view
atoms to form p+ region. These two p+ regions are
Fig. 3.1.1: Various JFET enclosures
internally shorted and only one contact is taken out
Fig. 3.1.1 shows several JFET packages, which are
known as Gate (G).
similar to BIT enclosures. Note the device terminal
(b) From Fig. 3.1.3, we can observe penetration (width) of
identification in each case.
depletion region on p+ (Gate) side and n-bar side. Sinet
~ 3.1.1 Construction of N-JFET and
p+is heavily doped, width of depletion region on P+
Symbol
(Gate side) is very thin (hence nonnally not shown)
l GQ, . ,E)(J)laln .conetructlon . of N-channel JFET, explai~
,\

r
i (r~ncy limitation
factors. ' ' ..,
~-- ----------------------- . --- ·------ ---- ·----------------- ----
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while width of depletion region on n-bar side (D) is
---
r [ii! Analog Electronics (MU-Sem.3-Electrical) 3 _5
Field Effect Transis tor

~ appreciable. In fact as we will see further, 'D' is

D1orain)

respansible for controlling conventional current Io or p

to source (S).
IDS from drain (D)

Heavi ly~
doped p - bar ,
r Moderately
, doped N - bar
Pt + · + + • r. I

+ +:
I
+ + I
I
Gate + + + +!I D ~I Width of
G depletion region
+ + + +: I
I

t_;_ + + + +,. ,: I
I
inn• reg ion

Penetration of depletion Internally

Penetration of depletion
short
region on p• side (very thin) reg ion on n-bar side Ohmic _/ S(Source)
contact
(a) Constru ction
(1G11)Fig. 3.1.3 : PN junction at input of N-JFET

As can be seen from Fig. 3.1.3, there exists a potential PB Moderat ely llodule
Heavily / doped P - bar
barrier (PB) or internally generated ELECTRIC FIELD doped N - ba7 \
p
between gate (p+) and n-bar. This (as will be shown
I
I
+ + +
I
Gate
later) helps a lot to keep current I 0 constant . G
D~ + + +
I
G I
I + + +
I
(c) The term "ELECTRIC FIELD" in the name of device
Penetrati on of Penetrat ion of
deserves some explanation. As we know the ability of depletion region depletion region
on P-bar side
permanent magnet to draw metal fillings to itself - on p• side (very thin)

without the ,need for actual contact. (b) PN Junction at input of P-JFET

The magnetic field of permanent magnet envelopes the D D

filling and attracts them to the magnet along the G G

shortest path provided by the magn;ti c flux li nes. In the ,

j
S junction S
same way there is internally generated electric field juncti~n

[Potential Barrier (PB)] is established by the change (c) Symbol

present, which controls the conduction path of the (1G2)Fig. 3.1.4 : Constru ction and symbol of P channel JFET

output current without need for direct contact between The construction of p-channel JFET is shown in
the controlling and controlled quantity. Fig. 3. l.4(a) with its symbol in Fig. 3. l.4(c).
The only difference between the p-channel and
&. 3.1.2 Construction of P-JFET and n-channel JFET is that a p-type semiconductor bar is
Symbol being used with two n-type gate regions.
--------- -~
~~--------------------- ---- ----:--- -------- --------- ~·'diagram
:·4Q. Draw • and explain with sui~le · sl In p-channel JEFT, current flows due to holes. This
~:: construction of P-channel JFEi: Also draw symbo'- i, because holes are majority carries in a p-type
rr- u.._.., , semiconductor bar. In n-channel JFET current flows
,, -:..: ... : __ -~ -:. _ _, __ - -- - - -- - -- --- - - __ _ _,_______ -- - - -- - ---
---- _ ___ _ J

due to flow of electrons.

J
I

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 Field Effect T r ~
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~ Analog Electronics (MU-Sem.3-Electrical) D1
+- D
0.75V
~ 3.1.3 Operation of N-Channel JFET
-------- ------------ ------- ------- -------------- ------------ -- -i D2
!·OQ;: . Write short note on : Input and output characteristics !
+- 0.5V
i .· · ot FET. W4•M•id@NMM1i=►il'lfffllffl l D3
l UQ; · Explain input and output characteristic of FET. I
+- 0.25V

i rfM•M•it@M•/44i=iiMMllffl l s
j ·''GQ.
:
Explain
N-channel JFET;
characteristics (Drain and Transfer) tor l
-
• Reverse bias Voltage
increasing tram S to D
l
·-
GQ. Write short
., - - - - - - - - - - - -
note on : Regions of operation of FET.
,,. - . _ ... _____ __ ___ __ _ ___ ___
:
l
_ _ ________ __ _ __ ____ _ ___ ,J
(1G5)Fig. 3.1.7
Refer Fig. 3.1.5. Operation of N-JFET will be
explained in three important conditions of biasing. (1) First point which we can underst and from Figs. 3.1.6
and 3.1. 7 is that if any value of voltage Vos
(A) When VGS is O (Switch S is at position 1)
(B) When VGs is negative (Switch S is at position 2)
(e.g. v os =
IV) is applied , then distribu tion of voltage
will be as shown in Fig. 3. 1.7. It is clear that as we
(C) When VGS is positive (Switch S is at position 3)
D _ ___,,._ _ __, move from S to D , the reverse bias voltage increases.
Io Therefo re width of depletio n region "D" also increases
Wedge shape and shape of depletio n region around p +, on both the
Depletion region
sides, will be as shown in Fig. 3. 1.5. This shape is
known as WEDGE shape.
G
1 (2) Now with V GS = 0, Vos is initially small voltage ; the
increase in D and reductio n in W will also be small.
3 1 Therefore 1 increases linearly with Vos·

fl
0

1 e- drift Since in this region, increase in current (1 0 ) is linearly

Vos proportional to voltage (V os), the region is known as
VGs VGs OHMIC REGION OR LINEAR REGION.
s (Fig. 3.1.8 portion 0 to A)
(1G3)Fig. 3.1.5
I0 (mA)
"" (A) Operation when V05 = O 6
f3 VGs = 0
(Switch S Is at position 1) · 1oss

D
Vos= 1V
(example)
' 5
g turatio_n reglo~

. 1 Increas ing resistance

p R .. . I : .due to decrease in w
D1
0.75V ·-r··
-- - -•---- .
I I
1-· · Slope showing
R •· ... ~ann, el r~~i5.~nce
0.5V ;__ ; 2 · +i ..
VGs I
R .. -I -
=O
D3
,I
.....
I

.... L
i
0 j 5
T
· V'os :
(1G4)Fig. 3.1.6 : Reverse bias potentials with VGS = 0
,.. •·••··; .. __ ,._ . .i .
(1Gl)Fig. 3.1.8 : D-duumel JFET drain

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 !i1
- Analog Electronics (MU-Sem.3-Electrical)

(3) If V0 5 is further . increased beyond y'OS (F"1g. 3.1.8),

.
increase m Io will not be linear w .r.t . v DS· This . IS.
3-7

Electric field
or PB
Field Effect Transistor

because decrease in W is more · Thi s causes curve i

. .
the charactens tlc after v = v'_
DS DS
n

(4) At a particular value of V os (with V as _ O) ·

- , W becomes
zero 3.1.9); this is known as ''p.meh -ofr' of JFET.
. (Fig.
This value of Vos is known as pm·ch-off. vo1tage, Vp. - electrons
Depletion regions join and w = 0
(5) Refer Fig. 3.1.9. At pinch-off (W = 0), there exists
potential barrier (PB) between p + (Gate) and N-channel
. s1.de, attracts (1G7)F:ig. 3.1.9 : ''Pinch-off "of channel at V DS = VP
on drain side. This PB (positive) on d ram
electrons from source side to keep Io constant. (6) Now, after V 0s = VP'
if V 0s is further increased (with
Vas = 0), 10 remains constant. This I0 is known as loss
Hence current flows even after w= 0 (as was stated).
and the region of characteristic is known as saturation
Since the current is due to effect of electric field, the
region or pinch-off region.
device is known as FIELD EFFECT tran sistor.

Increased
~ (B) Operation with switch "S" In position 2 and V05 (negative) Is applied, V 05 ls applied and

,. i

-4
v;; (a) Transfer characteristics (b) Output or Drain characteristics (c) Input junction J05

(1G8)Fig. 3.1.10 : Characteristics of n-channel JFET

(I) Up until now, V GS was zero. J 0 s was reverse biased and W was decreased to zero with the
help of Vos· It means vos
was responsibl e to make W_= 0 or to make channel pinch-off.
W will decrease. It
Now, if Vos (negative) is applied (with V 0s = 0), las is still reverse biased (Fig. 3.1.lO(c)) and
Therefore Vos required to make W = 0, will reduce.
means some job of Vos (to make W = 0) is done by Vas·
in
In other words as V GS will increase, Vos required to pinch-off channel will decrease, as shown
in Vos with
Fig. 3.1.1 O(b). This decrease in Vos with increase in Vas is parabolic. The curve showing variation
increase 1·n V is known as ''Locus of pinch-off voltages''.
GS observed that as Vos
(2) One important point from output and transfer characteristic (Figs. 3.1.lO(a) and (b)) can be
becomes more and more .negative, W goes on decreasing
increases (negative), 10 decreases. This is because as VGs
pl
which decreases area of channel (A). Since, R = A' with decrease in A, R is increased which finally
decreases 10 .

--4 SACHJN S11,4// Yea111re

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 Field Effect Tranlitto,
(il Analog Electronics (MU-Sem.3-Electrical) 3-8
----------------------------------------·-···-=-
:-~---~----- ---'JFET is knOWO as •SQUARE LAW DEVICE-? -~
(3) As we go on increasing VGs (negative), W decreases : GQ. Why ----·------- -- ----------- ----------- ---------- ;
therefore 10 decreases. At one vaJue of VGS• ·~---;~~- ~~-;ut characteristics of JFET we concluded th~t
V
VGs = - VP• W = 0 and 10 = 0. The JFET is known to be a range Of GS values from. zero to V GS(off) or VP
amount of dram current 10 . For an n
OFF. This V GS is known as V GS(oro· controIs the . ·
C hanne I JFET,
vGS(o ff) is negative and for p-channel
VGS(6ff) = IVpl ••• (3.1.1)
JFET VGS(off) is positive.
(4) As can be seen from Fig. 3.1.I0(a) and (b), we can oes control 10 , the relationship between
Because Vas d
easily draw transfer · characteri stics from output these two quantities is very important.
characteristics at constant vaJue of Vos· Mathematically Fig. 3 .1.11 is a typical trar_isfer . characteristics that

::;::.y;:c~:sr is ~vcn by Shoc~ey's equatioo

illustrate graphically the relationshi p between Vas and
Io- ,
Note that the bottom end of curve is at Vas = V GS(ofll
while top end of the curve is at a point on the I0 axis
(5) It can be easily seen from transfer characteristics that as
equaJ to loss·
input voltage Vas varies, the output current 10 varies. It
From the curve in Fig. 3. 1.11, we find operating limits
means input voltage controls output current. Hence
ofaJFET as
JFET is A VOLTAGE CONTROL DEVICE.
10 = 0 when Vas = V GS(off)
(6) In this region of drain or transfer characteri stics,
between Vas = 0 to Vas = Vascoro• JFET works as an And I0 = loss when V 0 s=0
amplifier.
I0 (mA)
B' (C) Operation with switch 'S' In position 3, VGs '
.. : r 1oss ·
positive, V05 is applied and increased.

With Vas positive, junction J0 s is forward biased.

• Therefore width of depletion region 'D' will be zero, which
makes PB = 0. Wis maximum. Now if positive value of Vas
changes, W remains constant (maximum). 10 remains VGS(off) _
0

constant and cannot be varied with Vas· Therefore JFET

will not work as an amplifier. Fig. 3.1.11

Drawing transfer characteristic from Drain

B' (D) Conclusion Characteristic
JFET is a voltage control device. For this, input · - Transfer characteristics curve can be developed from
junction should be reverse biased. Since input junction drain characteristics curve by plotting values of 1 for
0
is reverse biased, input resistance (unlike BJT) is very the values of Vas taken from the family of drain curves.
high. WOW ! It is a GOOD NEWS. It will reduce Each point on transfer characteris tics curve corresponds
loading effect. to specific values of Vas and 1 on drain curves. For
0
example, when Vas= - 2V, 1 = 4.32 mA. Also for this
0

Transfer Characteristics of specific JFET

~ 3.1.4
N-JFET VGS(off) = -5V and loss= + 12mA
,---------- ---- .. -,--~~•- : -:: -:---~~- - -~ - ~- :--:. . . ,,. ·: A JFET transfer characteris tic curve is nearly parabolic
: UQ. Write · short note :on . : Transfer cha~c s a(: in shape and is expressed as
:
I

t,~
:;
. FET.
Draw transfer ~ara~ris tlcs of..JFET .uslng·~i:ai;n ,~ ~
output ~racteris tlcs. ':
' ~:•
:
I

Vas
VGS(off)
J ... (3. J.2)

I~•••--------•••------------•-•----------•-•••-----•--••••-•-••-
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'1
- Analog Electro nics (MU-S em.3-E lectrica l) 3-9

With Equation (3.1.2), 10 can be determined for any

Vas ff VGS(off) and loss are known . These quantities are
Field Effect Transi stor

normally given in data sheet of JFET.

Notice the square term of Equation (3.1 .2). Because of
its form, a parabolic relationship is known as squar e
law.
Therefore JFET are known as SQUA RE LAW
-VGSM VGS(off) Vos DEVICES.

Fig. 3.1.12 : ·Transfer charac teristic from drain characteristic

~ 3.1.5 C~mparison between N and P Channel JFET

, " ', ,, ':::\,' , , ,~ '

.i>aram~rs , :/ N-Channel '

~P:€ha
" ·;
nneJ·
,, '

Electron
D D
Construction
n
.P
I
I
i- --
I + + I 1 +
: p :I : n
I G--,- --. n I
I I I
I
~- - - ___.) I· I
!,. _ _ _

s p-channel
n-channel S electron
(1G13)Flg. 3.1.14
(1G9)Fig. 3.1.13

Symbol
G
G
+
VGs -
s
(1G14)Flg. 3.1.16
(1G10)Fig. 3.1.15
... i" ---~ -····•···~- j ; ;
-- -- - -
~ Satura tion:-.j ..... L .j_
-, - :Io
Output characteristics
It -L-P,~~4;~=~1. .11?88
....._.. _
i , ipgt i iv~=f !
..1 ......... ;.....:..!..---•--···· ,---~-;
►

i..!--_;."-...- ~--r!~--1~ r-7 ·!,;-----+-----'•1v_-__1;---·· .

i"' " ;" ·+ ; __,_._
-·!______ .;..... ---: . ----~----- 1-·-...+---.. .- I
..,;- ~-~ -~......--:. + 'ZI/ · :f
:
1-~~ -+-- t-~-' 1' = 2V !
--1

•. vGSl~-Vp-~~~-- _:
; . .. ! . .. ' _ j (1G15)Fig. 3.1.18
(1G11)Fig, 3.1.1?
_..4 s.4CIIJNSlL4H ....,.,,..,
Teda-Neo Puhlieaaiom_ ftere ,4utl,on -,,ire__,.,_
 Field Effect Transistor
Analog Electronics (MU-Sem.3-Electrical) 3-10

Transfer characteristics
· _ :.~· .....

when JFET is in
saturation region

'fos

(1G1&)Fig. 3.1.20
(1G12)Fig. 3.1.19

VSD (sat) = VP - VGS

The saturation region VDS (sat) = VGS - VP
occurs at V DS{sat) where

a. 3.1.6 Comparison between CS and CE Output Characteristics

': -
:-::="." - .. 7- ...... · --~- :-, - -.-:-,:-,,; ., ; -; ,,--; - - -,,~:-... -· - '":_~; -; --; - - - .. - - -- - -- --- - - - -- -- - - - - - -- - - - - - --- - -- --- - - - - - - -- - - -- - - -- . . . ,· 1
·:~ -GO.
. ,~rnpare'. outpi.rt,characteristics of Common Emitter (CE) and Common Source (CS) arnplifle·r :. .
, .· ;. ;. ;.•· :, .; / -, .,. ._,,.,:,/,:. , , . _________ .; . ..... ~--:---------:-----------------.! .. .· ·.• :

_Sr• .. . I. Output ~baracteristics of CE 8'Dplifier Output characteristics of CS amplifier

',·.. ,-,;·, . '

No..
(1) Experimental setup · Experimental setup

le
Io
VeE Vee
VeE
(Constant) .__ ___....__ _,__ _ _,,'---.....__ __,
Vos
Voo

T Potentiometer to vary VCE Pot to vary Vos

V GS (Constant)

(1G,nFig. 3.1.21 (1G19)Fig. 3.1.22

(2)

1ut1 . ; . ; I.·. L L.. .t . I .

(1G20)Fig. 3.1.24
(1G11)Fig, 3.1.23

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 -
~
~

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\'
2~0~ -
i.--
Analog Electronics (MU-Sem 3-Electrical)

.~~i-~ua~rlstlcs of
,,, ,,, .,,
t·~
CE amplffler
..
''
3-11

Output cbancterJstlcs of CS ampllll~r;.,,

Feld
I Effect Transistor

·'

(3) This characteristics is drawn with v /1 Th

. • • BE e constant. en le This characteristics is drawn with Vas constant.
1s measured while V ce 1s varied.
~ Then 10 is measured with Vos varied.
(4) Divided in three regions : saturation, active and cut-off.
This is also divided in three regions: ohmic,
~
saturation and cut-off.
(5) For amplifier, Q-point should be in active region.
For amplifier, Q-point should be in saturation
region.
(6) In active region, there exists a slope, due to early effect.
Here also there is slope in saturation region due to
effect like early effect.
(7) Parameters which can be obtained are output resistance (r )
0 From this characteristic we can get output
and current gain (~).
.
resistance. ( rct' =-I =-I )
gos Yos

J 3.2 INTRODUCTION TO MOSFETS

wil
-
,. . -.. ,. . --""'. ·"' -.: --- - -- - - -.;. :-: 7-.~-.- ~--··77:-:,.- -.-,;: -.-- -._. ,._~-:; .. - - - ,.. - -:------ --- - - - "':"':-."' - - - - - - - - -~- - - -- - - ... - - - - - - - - - ..... - - :- - - - ... ... ,- -.-,_.- - --- - ... - - -.- ':"' "' - -.- .- --- - - - - - -- - - - - - - .,
; U,Q. What is _MOSFEJ ? . .• . , . , .
(MU - Q. 3 (b), Dec. 13. 3 Marks)
lt "'"/UQ . . Whatarethetyptl,sofMOSFET ,? . . . · . : ...
. ,:· - - -: .a.
. -._ _., -- - ·; --. .. - __-:: .-!---~:. __ >,::"·c·:<;:·-::. -, ·. ,• - ,'_': ·::'• ·.. /: . - - - :, - _,, - - - -- ·,.: :--·_ ,· - -- - - - - - - - - - - - - .:,._ . ·- s:· : .. ',; , :•: :- · :r:: :·::-~~;,, '\f':'::..· :,,· (MU 3(b). Dec . 15. 2 Marks)
J ._ ....•· _... _,
'%···,_ ·. - . - - . - - - - - - - - - -~

- MOSFET is also known as Insulated Gate FET (IGFET) is an active device in which current flowing through it can be
controlled by varying applied electric field. Compare to BIT, MOSFETs occupy very small area on IC chip.

- Since digital circuits can be designed using only

MOSFETs, with essentially no resistor or diodes MOSFETS
required, high density VLSI circuits like I
microprocessors and memories can be fabricated. Enhancement type Depletion type
I I
- It is because of MOSFETS that we have I I I I
n-channel p-channel n-channel p-channel
calculators in our hand and PC on our table. (NEMOS) (PEMOS) (NDMOS) (PDMOS)
Different types of MOSFETs are as shown in
Fig. 3.2.1 . (1K1)Fig. 3.2.1 : Types of MOSFET

J 3.3 CONSTRUCTION OF N-CHANNEL E-MOSFET

--·--------,-.------ ------- -- . . -.. . ----------------:"''"'--,-.-.---·"".':---:~':":-:~-=---~~:~--·~- - -,~.. ·:· -~- -~.,-,.: ' ., . ·._ . . '"·'· ·., ;-:' ~, -.".":; ,' . -.._""' ' - ~:
! UQ. o~ and explain N--channel Enhancement MOSFET with the help of sultable'd1agram. ~
''
''
'
0 I'
..
:,,• UQ. Explain the construct lon of ,T"\, • MOSFET with the help of suitable diagram.
-., -hamiel-Enhancement , ,:,
I t
I I
I I

'
I

, , Dec. 15. a. 1(e), Dec. 18,

a.. 3(b)
(MU - 5 Marks)
: !J~. Explain construction of MOSFET. ,,
!~ Draw a diagram showing con~t~lonal detal~~-~f-~~-~~~~~:~~!~-~~y~poln~regal'di~g-~~~!~~~-~-------- -------=-j
..... __ ,.-- --- ... -----........ __ . --- ----- -- .... --- ...... ----- - ----
'-',;,, _,..

· IJ'Aere Authon •pire .i.aat,ntioa

Teda-Neo Publication■--- .....4 SACIIIN Sll,4// Yenture
 ~ Analog Electronics (MU-Sem.3-Electrlcal) 3-12
Field Effect Transistor

► Step 1 Gate (G) Drain (D)

Source (S)
Metal or heavily doped
Oxide •-- -Vos- --i--- - VGo .. _,.,,..- polyslliconlayer
layer.... ..._.----- -~
(SiO 2 ) I'\.
___ ___......,.__--:=r:.~/::::J• ..L lox< 400 A
1 n• : T (oxide layer
: 11+
I
'' :
I
I
Channel region
:
I
/ ,
I
thickness)
I I
I 1.;
I
I : - ~- ,- --t-- Heavily doped
....
I I , 1
, -~ , n region
Normally ,,-
S & SS are
I .' I
'- - - - - - - - - - ~ Space charge region I ------ r--' r-- Depletion
internally
shorted I· L -6
(Channel length < 1O m)
·I region on p side

Substrate (SS)
/ - , ' - - - - - - - - - - " f Body
L---- (B) or bulk
I
p type substrate or body I
ss
(1K2)Fig. 3.3.1 : Construction of MOSFET

Penetration of depletion region in n+ (D and S) is negligible because they are heavily doped,
hence not shown.
► Step2
Due to these three layers shown in Fig. 3.3.2 device under consideration is MOS. G
These three layers together form a capacitor, known as oxide capacitor (C x).
0 Metal
2 E Oxide
C0 x (F/cm ) = 1a:x. The parameter E x is
0 the oxide pennittivity, which for silicon .
Semiconductor
MOSFET is E0 x = 3.9E0 • Where E0 = 8.85 X 10-
14
(Flem) is permittivity of free
space, t0 x is oxide thickness in cm.,
(1K3)Fig. 3.3.2

► Step3
Fig. 3.3.3 shows the pictorial understanding of width (W) and length (L)
of channel. The ratio (W/L) is known as aspect ratio. It is very important
parameter , while designing MOSFET s for different current ratings.

(1K4)Fig. 3.3.3

► Step 4
Referring Fig. 3.3.4, we can conclude following points :

Until and unless channel is not formed in s G

D
channel region (beneath Si02 layer), current
----;,,~~ ZZ?.l2Z Z?Z2ZZ ?Z2~~7 12Z:~L. l....--:-t" Vos
can't flow from D to S. This is because the : 'n+
·I ··:
region below Si02 works as back-to-back two I
I ,
.·. .,.
_, , . , .
I
I
._ __ ---•
diodes with cathodes common. But as soon as
Vas is greater than a particular voltage (VTN)
p
known as threshold voltages, channel is formed
in channel region and current can flow from D ~ Lowest voltage in circuit
to s. (1K5)Fig. 3.3.4
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 ['1 Analog Electronics (MU-Sem.3-Electrical)
3-13 Field Effect Transistor

- n+ - n+ - P forms a transi st0 r like structure refer Fig. 3.3.4 . To avoid MOSFET to work as BJT the base (SS) should be
~onnected to lowest potential in the circuit.

- Actually th ere are four terminals of MOSFET. But to avoid complication in biasing circuits, normally S and SS are
internally shorted therefore mostly there are three terminals D, s and a:
► Step 5 : Symbols of MOSFETs (Refer Fig. 3.3.5 and 3.3.6)

NEMOSFET PEMOSFET

D ., D

y
s s

(1K&)Fig. 3.3.S: NEMOSFET (1K7)Fig. J.3.6 : PEMOSFET

J 3.4 THRESHOLD VOLTAGE AND FORMATION OF CHANNEL Module

ff' {a) Threshold voltage

It is the voltage, which when applied to gate, channel is formed beneath sp2 layer and 10 just start flowing from
DtoS.

- Threshold voltage is normally abbreviated as V GS(th)• V111, VT• or VTN (N for n-channel). This voltage is given in data
sheet.

Ii" (b) Formation of Channel

Attracted minority
Repelled majority carriers (electrons)
carriers (holes) Substrate (SS)

(1Kl)Fig. 3.4.1 : Formation of channel

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 ◄
i'I Analog Electronics (MU-Sem.3-Electrical) 3-14 Field Effect Transistor

Initially there is no channel between D and S. Substrate is p type, therefore majority carriers are holes and minority
carriers are negatively charg~ electrons. Formation of channel taJces place as follows (Refer Fig. 3.4. l)
I. When a small value of VGS is applied, an electric field E is generated. Due to E, electrons gets drifted up, towards 0x.ide
layer (electron always travel in opposite direction to E). In other words electrons gets attracted towards oxide layer.
2
· Due to presence of SiO2 (insulator) layer, these electrons cannot reac~ upto Gate, therefore they get ACCUMULATED
beneath oxide layer. In this way area below oxide layer becomes LESS p.TYPE. Since presence of electric field E
helps in forming channel th~ device is known as FIELD EFFECT TRANSISTOR.
3.
As VGs is further increased·, holes, below oxide layer are repelled away from channel. Channel goes more towards
n-type.

4. Finally due to repulsion of holes, uncovered

negative ions further increases negative charges D
G
(Depletion region) in channel. In this way Vos=O
at VGs = VTN (threshold voltage for
N-channeVMOSFEn, N channel is formed
beneath Sp2 layer. This channel cen now
conduct 10 •

In Fig. 3.4.2, x is height of channel on drain (D)

side, while y is height of channel on source (S) p

side. In further topics we'll use these notations.

= ss
(1K9)Fig. 3.4.2 : Formation of channel (VGs~ VTN)

J 3.5 STEP BY STEP OPERATION OF NEMOS WITH OUTPUT

CHARACTERISTICS AND EQUATIONS

:~o~::
'r ,' 1..: 'j;~;~ ~-~i<plain~N-channel Enh~~cement MOSFET with the help of suitable diagram and equation.
·Y•;''.<'.?(i' ', ··• .. ·. , '
:
:
I o
I , o

r: U<;l. ..,Dra~{ anti explain N-channel FET with the help of suitable diagram and equations.
I . . . .
l
I

II 'o
I 0
: ._,,. , .'· . , -"·' , , I

: ua. -Explai_n:thecharact~ristics of Enhancement MOSFET.

I (MU • a. 3(b). Ma 15, 5 Marks)
l Gq. , Explai~ operation of NEMQS step by step. :
:_ ...-2;1tr:...;.;~:.;; _:. '- _•._-·-~-~-,t·i -i :.. ·~-·:.. _~- ___;,:. .. __________ ._·- __ ____ ________ ________ .. ___ ___ . . _______ __ _______ ____ __ ______ . . ___ ,:;:. ________ .. ___ - · ___ .... -- _......... _j

► Step 1 : Cut-off region (10 = o)

VGS=O
s G D
- VGS _ _..,.._ _ VGo io
Vos

VGs=O
Substrate 10 = 0
ptype ➔---"'---- Vos

(1K10)Fig. 3.5.1 (1K11)Fig. 3.5.l : Output characteristics

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►

~ Analog Electronics (MU-Sem.3-Electrical)

3 _15 Field Effect TransiSIOr

: With no bias voltage applied to gate CVas= o), two back to back diode exists in series between D and S. One diode (03)
t,etween n+ (D) and substrate and other diode (D4) between n+ (S) and substrate. These back to back diode prevents
conduction of current from D to S when Vos is applied. In fact the path between from D and S has very high resistance
(::: 1012 Q)

(b) Equations
Vas = 0 Vos ➔ applied and increased.
i0 = 0 ... (3.5.1)
This is the equation of MOSFET in cut-off region.
(c) Output characteristics (Refer Fig. 3.5.2)

► Step 2 : Ohmic region/Linear region/friode region with V very small (10 increases linearly with Vos).
08

VGS >> VTN Depletion region

on channel side ·
~Gs=4V ....
G
VGs - -~i---- - VGD Vos
very small
--rr-µ~~~~ 74~~~~~~ - Module
n+ - - - - - - - - - - - - - - ~L!___,,.~ upto 50 mV io
-ohmic region

I~~~{:=_=_=_=_=_=_=_~~=~==~~~§:::!:!-
I..'. ~
L
:n Depletion
region on
substrate
(part of triode
region)
~ side
- Slightly
reverse bias - ~,--
, - - - ----"---Vos
I I
p Jsso I I

LetVGs = 4V, ft.Vos .

VTN = 1V
(1K12)Flg. 3.5.3 : Channel formed MOSFET in ohmic region (1K13)Flg. 3.SA: Ohmic region

(a) In this region of operation, channel is created as shown in Fig. 3.5.3 by applying Vas~ VTN (Let V = 4V while
08
VTN = 1V). If applied Vos is small (in mV), diode D 1 is slightly reverse bias and increase in depletion region on both
sides (channel and substrate side) is very small. Therefore, decrease in height of channel (from bottom) on drain side is
very small (x' < x). Hence decrease in resistance of channel is negligible. Therefore for small values of V , increase in
05
current (1 0 ) is linear with voltage. Due to this, this region of characteristics is known as linear region.
(b) Equations : Vas > VTN for channel to exist. Vos is very small in mV. Equation for i0 for NEMOS in general is :

i0 =~[2(v0 s-VTN)v0 s-v~s] • where K,,=[½®K:]mAN 2.

Where, r is aspect ratio and K: = C0 x µ,.

K: is process transconductance parameter. It decides gm of MOS.

Eox oxide perrnitivity of Si Eox = (3.9) x (8.86 x 10-14 ) Flem

Cox=~ = thickness of oxide layer '

Equation for i0 can also be written as

ii
.
10 =
W
L
,[
K 0 (Vas -vTN) Vos -T
V~s]
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 [i1 Analog Electronlcs (MU-Sem.3-Electrical) 3-16

In this mode of operation v0 s is very small (in mV), therefore

2
Vos
2

=0.
Field Effect Transistor

-
Hence • w I
. .. (3.5.2)
lo = L K. [ Vos - VTN] Vos

· (3.5.2) md1cates
The Eq uation · · .
operation of MOSFET as linear resistance. Hence this region of operation is known as

OHMIC REGION and Equation (3.5.2) is for ohmic region of MOSFET.

(c) Output characteristics

In Equation (3.5.2) if we make gate-source voltage constant (i.e. vGs = V Gs) the MOS will work as DC resi stance, given
as,

ros = ... (3.5.3)

Equation (3.5.3) gives the basic concept of MOS being used as resistance in IC.
► Step 3 : Triode region or non-saturation region (non-linear)
(a) In this region the value of Vos is higher than its VGs > VTN
value in ohmic region. I0 increases in curve ~Gs=4V ...
G Vos=2V
with Vns· Refer Fig. 3.5.6. VGs---'----
Since Vos is high, D, will be more reverse bias
and more expansion of depletion region takes
place on channel and substrate side. Height of
channel (On D side) further decreases (x" < x'). - .Lll("_ _ _ _ More

Resistance of channel increases. Increase in p reverse bias

current (w.r.t. Vos) is not linear, but it increases
in curve with Vos·
(1K14)Flg. 3.5.5 : Triode region (MOSFET in non-linear region)

(b) Equations :

VTN = IV (e.g.);
io Triode _ __
Vos = 4V> VTN
r~
V00 = V0 -V0 =4-2=2>VTN Very / ~HigherV0s
lowv05 / : (Curve)
or (Vos - Vos) > VTN with these conditions drain current will be, I
I

I i0 = K.i [ 2 (v0 s - VTN) Vos -v:s] I .. (3.5.4) I

I

--1-------.......•- - - Vos
I
I
I
I
I

The Equation (3.5.4) represent MOSf'ET in non-linear triode ~gion. (1K15)Flg. 3.5.6: Non-linear part of triode region

(c) Output characteristics (Refer Fig. 3.5.6)

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-
~

►
Analog Electronics (MU-Sem.3-Electrical)

Step 4 : Saturation region

Vos> VrN
3-17
Field Effect Transistor

Vos =4 v
s G Vos= 3 v
lo
\ .
Saturation region
.

I
I
I
I VoS(sat)
p Jsss Vos
Vos Vrn

(1K11)Fig. 3.5.7: MOSFET in saturation region (1K17)Fig. 3.5.8 : .Saturation region

(a) As soon as V 0s reaches to a value such that VGs - Vos = vTN• reverse biasing of D 1 is such that depletion region on
channel side makes x = 0 (height of channel zero). This act of height of channel (on drain side) becoming zero is known
as PINCIIlNG-OFF of channel. After this, if Vos is further increased i 0 (ideally) remains constant or gets saturated.
This is reason why this region of output characteristics is known as SATURATION REGION. The value of Vos at
which MOSFET enters.in saturation is abbreviated as Voscsa1)·
:. VDS(~t) = VGS - VTN
(b) Equations: VGs~ VTN channel should exists. (V Gs= 4V, VTN = IV).
V GD = V GS - V DS = 1V = VTN ... V DS = VGS - V TN = VDS(sat)

io = Ku(vGs-VTN)
2
.I ... (3.5.5)

The Equation (3.5.5) is the equation of MOSFET in saturation region.

jTcfp:-:~~~~h~~~d~ ~~~i-l~~"~~~~~~,~!~~~~~~~~~~-~-?--~--~':l~_•;;~i±·JtJ3[i•:?£i•l2;j~§:~i~::,__ ~ -, r ·,

B" Row of Current (1 0 ) after Pinch-Off

At pinch-off, D, which represents junction between n+ drain and substrate (SS) is heavily reverse bias.

With Isso heavily reverse bias there Conventional

Electronic Io
exist an electric field E, which is Io" -f G
OS= Vo~(sat)
VGS---+--
capable of attracting electrons towards =Vos-VTN

drain. ~;;;:::~:t~~-
:-. , =====~ ./ Drifted or
attracted i
Hence electrons are drifted from Electric field due to _ _ _ - - duetoE•
reverse biasing of J550 .
channel to drain and electronic current It attracts electron from
channel
flows from S to channel, channel to D p

and finally D to positive terminal of

(1K23)Flg. 3.5.9 : Flow of current after pinch-off
Vos·

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 Iii Analog Electronics (MU-Sem. 3 -Electrlcal)
3-18 Field Effect Transistor
J 3.6 OUTPU T CHARACTERISTIC of NEMOS
at CONST ANT VGs
!- o,q. - 0~~~-;;; ld~:~~~
co-;i~>~;;~~ci;ri~~~ Ne-Mos;; v~~-~J~~~i-~~d-;;,~-diit;,;;~; ;~~~~~f~ if~::'"~J~;;~J,?,;"1
: · equations. · · · ,.,.,. ,,~,. ·
L-GQ. Write equa~on5- and draw Ol.ltp~ character1stlcs of NEMOS f~r,dlff~rent regions.
- -.. - - --- - - _,_- - - -- .. -.. -.: ; -- - -.. -· - - . • .'"• ,, .,:./;/ ..y 1· ", : ;:.,:;;:
- .:. ..... :i_- -- -- -.. -- - ---.. -~- .--- --- ..... • '•-.. - .. ,·_--.. -.. --- --- -.. : ,._- -.. -.. -..... -~-...... - - -- - -.. -- -·-··- - - - -- -- -- ----~..:,!;;,_,,;.;. !
(Refer Fig. 3.6.l)
Non-saturation Saturation
or triode region - - - - - region
Vos>,. VGs-VTN
Curve bends
because the VGs = 4 V
channel resistance Current saturates, because the channel
increases with Vos pinches off at the drain end , and Vos
no longer affect the channel
io = K,,[2 (VGS - VTN)Vos - Vos 2] 2
io = K,,<VGs - VTN)
VGs > VTN
/ Lohmic
Almost straight region
line with slope
proportional to
. - W • (VGS -VTN)
10 - L
Kn (VGs-VTN )vos
- -f----+ ------- +-- - - - - - - - - - - - - - - - Vos
0 ___.....__ Case II _....., ___ _ _ Case Ill - - - - •
Case
Vos(sat) VGs -VTN
(1 K18)Fig. 3.6.1 : Output characteristics of NEMOS

J 3.7 DRAIN AND TRANSFER CHARACTERISTICS OF NEMOS

.. . •·. ,-: . ......:.:~· ." . ' .->'· ·'··y····: .•,,;- . ,,··.,_'~•: . .,
GQ. Draw drain;cand tran$fe'r characttui~lci(bf NEMOS with necessary parameters: ,
> , ' '. , / -:::.~... .. . ·• . .• ,: , .~ :-_ \ , ' .• ·c.. 1
.. ·· , . .. :
GQ. . Ora.; o~tJ1;~
- . - ·. - ., .•~ - - :· ·s:><,:•·,· - - .. ·,..:<·:
81lp'
t/~ns,f,er chii,:acteri ~~ of;,N~~os . Show different
.,._ ,•• ::·-: •.:..·. ,,·,;,·-··~~:<::,,-.·,,_ ;. . : :-:., /,-,·;t,-·';.(:, _ ..,,.,y·;::•:_;,.,,:, .. ~)-~><C:;<";,,;:;.·•:;,:· ·._,. ••·. , ,,·,·- _ ' .-:·· , - .,,·,< - - - - -
::egionsr. ., .• . . '
,_,.__ . - - - _., :,,~ . .• ·'•, •. - - -- - - - .,,.. -
'. ,· ,. d , . :
. .- - - . - - ·.,_,,_ - - - ·'· ,._ - - _ .; - - - - - - - - ~- - - - ; - -~ i· ~

' l1f .,..-- ,_,. ··r ,.

(mA) , 4- Locus of Vso(sat)
I .
. t Vos~VGs +VTN/ . Vos~VGs+ VTN '··
·· _ Triode • lo "~ Saturation region - •
region · 1 .,, V >_YGS3 · : m,~
+·v/ =•" "- -~~ :· ..··:;· ... t::.,
_j,,-.,,..._~ --:---:------- .V1;3s2 j"
3->_ i
r·r.::' i·t=tJ 'I;· :.:.~: ~ J , ·: . .
io
,__,.....,..~---:---:---:--:-~--:-~- .~.iV
1 . ;,.),...,,i(fl1A)

fLL _: ,, : _, .. ,D~(<X!fl~

'; "-~ --

-VTN
; ·;v'~ ·•.~'n(" ,'.,.,,,
-, · f -
-v- -·· L:r,.,-;.v-:c---'---':......:.--+--,-,,-.:..
---'- ;,~=,;,,,_.,..,...,.,.,.,.,.,.,.,.,.,.,., ,..,..""",,,,"7:,,..,.,,_..(cut-01')
.
,,,, ~_, ✓ ,,_,,.,,_ "'! ,
., • . '
.,
,,,;, (volts) ,;,,
OS : f 1 : f
,o,. ,. L L .

(1K19JFig. 3.7.1 : Circuit diagram (1K20)Ffg. 3.7.2: Ideal output (1K21)Ffg. 3.7.3 : Transfer characteristic
characteristic of NEMOS
ofNEMOS
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►

!'1 Analog Electronics (MU-Sem.3-Electrical) 3_19

Field Effect Transistor

j J.8 OPERATION AND CHARACTERISTIC OF PEMOSFET

~~~~~~~~~~[~!~~~~~;~:~~;~~~f~~:f!~~~!:~~~~~~-:·::::: : ~:;~ ·~: ~~:: : : :~: : : ~.:~-~: ~:,J~;~·:1

s D
"?I. 3.8.1 Operation of PEMOSFET TVso
► Case I : (Refer Fig. 3.8.1)
J•
With YsG = channel not formed. D 3, D 4
: , - - - - 1 :>+--- --t<. ~ -+t-- - 'I p+
:_p_+-f..L
: ., , '· I
l
I I
~.__________""'_: D4 D3 -------'
(w.r.t. S, D and SS) are such that I0 = o.

I Io = 0 I n
Substrate
n-type

VTP= -1 V l.ss
..
(11131) Fig. 3.8.1

► Case II: (Refer Fig. 3.8.2)

Hole inversion
With V so ~ V TP• channel is formed, due to layer
accumulation of holes beneath SiO 2 layer. s G

I Io = 0 I
! ! ! ! ! ! ! +!! ! !!!! ! !! ! ! ! p't :
► Case ill : (Refer Fig. 3.8.3) I
:
p+
y_
,
__+_+
+,±,±,±, _+_+_+_+_+_+_:t:t:t:t,tt.t.t.
X
.·. ·.·. I

As V so increases :_ - - - - - _i- - - - -- - - -- - - - , - - - -j_ - ~- ~': J

Depletion region
1. Decrease in xis negligible. I 0 increases linearly. Channel channel side

2. With more increase in Vso, decrease in x is large, n

10 increases in curve. VTP=-1 V
W,
i0 = L kP [v sG + V TP] vso - linear region (1k40) Fig. 3.8.2

i0 = ~ [ 2(vsG + VTP) x Vso - vs~ ] - Triode region

VsG =4 V >VTP
Conventional
Electronic Io
Io"\ ,I'
s T G
so=2V
, p+.· ::::::::::::::::++++++
~ +++++++++++ +++++++ +

L---+ ~ Pinch-off
point (P)
x=O
n Electric field
n x=O
x' <x

(1k41) Fig. 3.8A

(11131) Fig. 3.8.3

► Case IV: (Refer Fig. 3.8.4)

With y _ VSD_ y SO + y TP x (height of channel or drain side) becomes zero, channel pinches off• Ideally I D
SD - (sal) - •
l'Cmains constant w.r.t. Vso· Device enters in saturation.

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 I
I
_1!
191
~ Analog Electronics (MU-Sem.3-Electrical) 3-20 Field Effect Transistor
'1
I W µpC 0 ,
~ = 2L
. W, L, C , are channel width, length and oxide capacitance
0 per unit area respectively.

~ 3.8.2 Output and Transfer Characteristics of PEMOSFET

, ,. <' ""'' " : .., .. , .... ¥ ... 1 ,. ~i.,,~ ...,,

_; v~,\~·'.:~1- :~_-~;_:~:;
; ; .,. .,/ NsG ·

~s:;:~ ~t;~~i:~Ii
' ! . . ; : ~ I

-~<:·:·~. "i::.
, ~sq< VTP (<;ut-olf) )"-;
.! .L , c:;ut-off region . __\__ :,. ..,,,
V~-~! i.
Ideal outp'ut characteristics' of NEMOS (yolts),,
·, -) . . {. .,.~ (, ~ ~ ' . . J... :,, .. ~
(1k42) Fig. 3.8.5 (1k43)Fig. 3.8.6 (1k44) Fig. 3.8.7 (1k45) Fig. 3.8.8

I 3.9 MOSFET CONFIGURATIONS

~ MOSFET Circuit Configurations JFET circuit

Most of the circuits using MOSF ET are two port networ TWO PORT
k (TPN), Refer , NETWORK

~
Fig. 3.9.1. .,, (TPN)
-'----+---1,t;;, -\i
: Input
port
'-"-"-...;;..+ -'-...;;....1

'
Fig. 3.9.1: Two Port Network
Depen ding upon the tennin al of MOSF ET comm on
to input and output
ports (for MF AC), MOSF ET can be connected
in three different
config uration s. These are comm on source (CS) comm
on gate (CG) and
comm on drain (CD).

r:r Common Source (CS)

This is the most widely used configuration. CS circuit

provjdes medium .
input and output imped ance levels. Both voltage gain
(Av) and curren t gain
(A ) are medium. Input voltag e (Vi) and output voltag
1 e (V0 ) are out of
phase.
Fig. 3.9.2 : Common source

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-
~ Analog Electronics (MU-Sem.3-Electrical)

r:r common Gate (CG)

- 'Ibis MOSFET configuration provides low input impedance while high

3-21
Field Effect Transistor

D
output impedance.

Although voltage gain is low an d the overall power gain is also low
. phase.
compare to other MOSFET configurations • V i an d VO are 10

Fig. 3.9.3 : Common gate

rr Common Drain (CD)

- This MOSFET configuration is also known as the source follower. The

reason for this is that the source voltage follows that of gate voltage. s
Offering a high input impedance and a low ~utput impedance. It is widely
used as buffer. The voltage gain is unity, although current gain is high. Vi
and VO are in phase.
•
Fig. 3.9.4 : Common drain
S' MOSFET configuratio n summary table
Table 3.9.1 : Configuration table

.
l\~lit~lJ~~~. . -CQ~~ratfoh .
C •.
j
:.v,_:,/y ,,
Common gate
.- ·.:!SF ;~r
Commoncl.r,.,tff·iltit:: (~9nun~n -~ urce ·,
·"' ,1'. .• ,. ,,, I, "'·,.
~/{. ;,' X 'w:\t,~ ' ., ,

Voltage gain High Low Medium

Current gain Low High Medium

Power gain Low Medium High

Input resistance Low High Medium

Output resistance High Low Medium

Phase relation between input and output 0 0 180°

J 3.10 DEPLETIO'N MOSFETS (D OR DE MOSFET)

, rEJii~~=~D-~ns~~ ~~,d\P~~(~~?·'?if •~ ,-~~~:·,,'°-~·~':lA

a.- N-channel DMOSFET

~~h~t•t~Jajl'l\wtth;,~~ffidion .wo_rktrig an.d .cti~ctertsf!c .. operation ·of ~-chan~L;,o-M~SF,~. ,AlsQ ,.~ ~i· it
k~~11ft~~~~~b~,~-~-'~_c"~I ~ ~-_~-;~CC-_::_------~::~·-~:.~--- _:~.:~ _: _~_------·-·--~ _:_-~ ---~-'-~~~-.:---,-'-~---- _: __ ~ ~~: :. __;:__L~£':d~c:·•:~ _·:~--'.:~i
Qr' Cuel:V08 =0

- . The construction of DMOS is (n channel) is very similar to EMOS. An actual channel is formed (during fabrication),
beneath SiO layer, by adding n-type impurity atoms to the P type substrate. It means in this MOSFET channel exists
2
even with vas = o. For Vos > o, Jsso is reverse bias and there is no current flow through substrate.

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 ◄

~ Analog Electronics (MU-Sem.3-Electrical) 3-22 Field Effect TranSisto,

With Vos = 0V, if Vos is increased upto a small

value (= IV), the drain current follows Ohm's law VGs =0 n-channel lo
(ios = Vos/ Ros) and is directly proportional to Vos·
Any increase in the value of v s beyond Vos(uiJ
0
, n+ :. :. :. : : : : : :. - :. :. -_ -_ -_ _x : n
(known as PINCH DOWN voltage), does not I

increase the drain current significantly. The region

beyond pinch off is called saturation region. The
-Sub strate
value of 10 , at Vos(ut) is known as drain to source
p
saturation current Ooss>·

The TERM DEPELTION MODE MEANS channel Height of channel on drain side = x
exists even with Vas = 0. (1k46) Fig. 3.10.1 : Height of channel on drain side = x

~ Case II : VGS < 0 (Deple tion mode or D-MODE)

With negative voltage applied to gate, some of

Depletion region
electrons from n-channel will repelled down. This creates or space
s VGs< OT G I 01 < I 0
uncovered positive ions beneath oxide layer. It means with charge region D
Vos negative.
(a) Electrons are repelled down.
(b) Space charge region or depletion region is generated.
(c) Width or height of channel decreases (x becomes x')
Repelled
The reduce thickness of channel decreases the electrons
channel conductance, which in tum reduces current 1 . p

-
0

When gate voltage is threshold voltage, which is

negative for this device, the induced space change region, Height of channei on Drain side= x'.
x' < x, resistance of channel increases I decreases
extends completely through the n-channel region, and 0

current goes to zero.

(1k47)Fig. 3.10.2 •

~ Case Ill : Vos > o (Enhan cemen t mode OR E-MOD

E) S VGs>O .,1.
y G
A positive value of Vas increases ~e
effective channel width in the same way as in •
- VGS - - - k - - -
-f Vos
---:-r -~~7 Zl.ll2 2?Z! ZZ~7 Zl.ll2 ~U-, ~
N-MOS. It .attracts electrons from suqstrate and I r,+ - - - - - - - - - - - - -
! ---- ---- --
creates an electron accumulation layer, which
increases drain current.
Attracted Accumulated
The electrons_ __ layer of
general output characteristics
p electronS
(io V/s Vos) and transfer characteristics for
NDMOSFET is given below :
x• > x, resistance of channel decreases, 1 increases
0

(1k41) Fig. 3.10.3

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L
-
~ Analog Electronics (MU-Sem.3-Electrical)

io
3-23

io
+
Field Effect Transistor

+
+ t iG .= 0 I +
Vos
Vos
Vos
VGS

-•·---...1.....---l s s
(1k49l Fig. 3.l0A : Symbol of D-Mode (1k50) Fig. 3.10.S : Symbol of E-Mode

i0 (mA)
i0 (mA) Vos(sal) = VGs-VTN '
~ o~:!on - - - - Enhancement mode~ Triode
I
1,, , , Saturation
- region •1 region ---
Voss VGs - VTN , / Vos<':: VGs - Vn:,1
,: VGs = +2V
32 ~ Vos= VGs - VTN
I
I
24 I
I
Module
I
I
VGs = OV
1oss 16

8
VGs,,; ·-2v ·
=-3V

0 4 8 10 14
-4 -2 0 2 4V +vGS (V)
VTN
-VTN VGS <~ V _(~~N)
(11151) Fig. 3.10.6 : Transfer characteristics (1k52)Fig. 3.10.7: Output characteristics

\~ ~ote': Working _
:-:--· .
of: NDMOS is somewhat similar to N-channel JFET. But NDMOSFET has·
. ': _:~: ._,_ ,_ - . - :····-,_
90e,:dtf~tJ taf;;f~r.fFefti:
:/.:.;/' - ;,;;/W✓,,r: /:,0,::'3. --, -.,~~~:._ :/? . \· "·\ <)~):(_._{·
',,.,<_><" ~n be operated with Vas negative only, while NDMOS -canbe ~perated with Vos negative;~n(f~ltl~Ei bdftifr-::Jf ·

I l.11 MOSFET AS SWITCH

'&. 3~ 11.1 Applications

t~I-: ~~~~~ij~~~\~ifi~;f~;~~~f~~:~~~-~:~~z~~f
@Ans.:
?:~~,:~~
~:2::~::~~:t!::~:t::'.~;:;:1~j~?~5~!t:;1t~
1

MOS switches find application in both analog and digital circuits.

Few of main areas of IC fabrication where MOSFET is used as switch are as follows :

o To connect capacitors in various configurations, this applicatipn is called switched capacitor circuits.

o Multiplexing and de-multiplexing.

o Modulation etc.

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 Analog Electronics (MU-Sem.3-Electrical)

~ 3.11.2 Drawbacks of a Non-Ideal Switch

3-24

r . . . --.---,. -------.. -.. . . -- "\----------.. . . . ------------------ --------.. ----.. . . . ---.. --.. -............ . . ---~--.. :--------. ,.
Field Effect Translator

-.. . . ;-~-~~.~-r~
-
:,' QQ, _ Compare to an Ideal switch, What are the shortcomings bf a hOn•ldeal switch:
_..,_ .. --~-- ...--. -.... -.......~ .... . -"-- -...... ... ,..,_ -- .. -- - --- -- . . ..... .. --- .... ......... - ... . -- -'- -- --- ---...·. . .......... --- ------· --- .......--- .... ----..
1

'
• • ·: ,

-------·
- - - ~ - - - ~ - - - .; -.: _ _ _ _ ~ _ ~ }'.''_ :

Iii Ana.:

4----:~
!c
."c
(Control voltage)

Fig. 3.U.1 : Three terminal swi(cb

foFF

roFF

A B

le
♦
Ce

Fig. 3.11.2 : Model for DOD linear switch

Components in Fig. 3.11.2 indicates non-idealities in a practical switch used in IC. These undesired parameters are as
follows :

r0 N: Resistance between two tenirinals of switch (A and B) where switch is ON. Ideally it should be zero.
r0 FF: Resistance between two terminals of switch in off condition. Ideally it should be infinite.
Variation in r0 N and r0 w : The value of these resistance changes with terminal voltage. Ideally this should not
happen.
Vos : SmaII voltage that may exists between A and B when switch is in ON state and current is zero. It is an offset
voltage. Ideally should be zero.
Ion- : Leakage current from switch when it is off. Ideally it should be zero.
IM J8 : Leakage current from switch terminais to ground. Ideally this should be zero.
CA and C11 : Parasitic capacitors between switch terminais and ground. Ideally their reactance should be infinite.
CAB: Capacitor between two terininais of switch. Ideally it should not exists.
r .• Parasitic -capacitors between control terminal C and tenninal A and B. These capacitors contribute to the
CAC' "'JIC
effect called charge feed through. Ideally these capacitors should be zero.

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 Field Effect Transistor

-
~
~ Analog Electronics (MU-Sem.3-Electrical)

3.11.3 Operation of MOS as Switch and Its Advantages

3-25

~
r~oa. , -- ---------------------- -------------------------------------------------------- - ----------------------
,Explain working of MOSFET as a switch in VLSI circuits. ,
-!
l
: GQ. :e,cplain the MOSFET as switch in VLSI. :
· ~------~-~-------------------~----------------------~--------------------------------------------------------------------- ~-------
ltf Ans.:
r:r Operation

t
Vo-"L

Fig. 3.11.3(a) : MOS as switch

Module

Fig. 3.11.3(b): Transfer characteristics

(A) Switch "OFF"
When V is less than VTN. Channel is not formed. Drain current i0 is zero. Operation is between XA.
1

I ros = roFF = oo I I I
with io = 0

Switch remains in OFF condition with I VO = V oo

This is because with i0 = 0, V 0 =Vo= Yoo- io Ro= Yoo·

(B) Switch "ON"

With V 1 > (V 08 + VTN) =Yoo·
Device heavily enter in "ON" condition, resulting in operation close to point C with VO very small. io is very high
because r08 = r0 N is very low. i.e.

io very high I =I roN O D - as good as connected to

ground and I =I
VO O

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 ~ Analog Electronlcs (MU-Sem.3-Electrtcal)

(C) rON of MOS

3-26
Fielcl Effect Transistor

-
It is [r0 + r. + r (channel)).
Typically by _design, the contribution of ro and rs is very small such that primary consideration is channel resistance.

:.Ir0 N = r (channel)!

(D) Expresalon for channel resistance

In "ON" state, voltage across switch (MOS) i.e. VO is very small while V1 = Vos is large (Yoo>·

MOS is in non-saturation region.

Therefore in this region MOS can be mathematically modeled as,

. ,w[ V~s]
Io= Kn L (Vos-VTN)Vos--2 -
Where Vos is less than Vos - VTN but greater than zero. Now the small signal channel resistance will be,

L
roN = aio / aVOS = K' w (V
n OS -
VTN- V )
DS

~ 3.11.4 Advantages of MOSFET as a Switch In VLSI

r·---·:;~---~ -·:'""is;,""·: ··;-~---~,:- ~ -~,~~? T ---;,---·;:);/~\-.----,,r ----~ :~:i;;-I:~;;;;(,::jfi;i:,.---.,.
7 ' - ,~: -, - ---- -- -- ~ -.a-----,_-·;:;,_:;::
:L -----
aa:- --What aJethe
-- -- - -- ·•'.X:·
advantages if MOSF:cf is used as a·switch ? · ' ,,.;, , · ··.w, ,:-<:-":-- -..i · ,. : ·. ·, . . , ·:
;>. _ _ ______ ..~t. _ _ ___ _ ,. _ _ _ _____ ,_ ___ _. _,. ~ _ · - - -- • • ·...... .... . . .. .. ..' _ v· _ ,-,. __ ,___ · ................. .... · - -.. ....... .. ··...... .. .. .. .. :.. .. .... ' .. ·, .... ...... •.. · J

(i) r0 ,.., : Resistance between two terminal of switch r0 FF (r0s) is very large. Therefore leakage current loFF (1 0 s (om) is
very small= 0.
(ii) In Fig. 3. l l.4(b) r0 N as a function of Vos is shown for V0s = 0.1 V and W/L = l , 2, 5 and 10.
25k~-----~----~

20k
c
B 15k
C:

~
·ij 10k
+ er
Vos=V
z0 5k

0
2 3 4 5
VGS(volts)

Fig. 3.11A(a) Fig. 3.11.4(b) : roN ( = f) or MOS

It is seen that lower values of r0 N is achieved for larger values of (W/L). When Vas app'roaches VTN(= 0.7 V), r N
0
approaches infinity because switch is turning off. It means by adjusting W/L ratio we can have parameters of MOS
(as a switch) near to ideal.
(iii) The offset voltage (Vos modelled in Fig. 3.11.2(b)) does not exists in MOS switches.
(iv) The capacitors eds (CAB in model 3.1 l.2(b)) is very small in MOS transistors.

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" ' Analog Electronics (MU-Sem.3-Electrical) 3-27 Field Effect Transistor

J J.12 BIASING OF MOSFETS

[~~~~~~~~~~~~~~~~~~~~~~~~~.~~~.•~~~-~--- ~~. ---~---:~--~--~-'.:~- --,r- :.~-~:~·~::~~:~-~~1i;111■,;ii@E~1,~!:j},!®~#!
Once the value of Io = IDQ is fixed with power supply and normally with resistance R , I should ~main constant to
0 0
avoid MOSFJ;:T going towards and entering in triode or cut-off region. This causes applied signal at output distorted.
UNFORTUNATELY
1. In discrete amplifier I 0 do vary due to

(a) variation in device parameters, when one MOSFET is replaced with other of same type and
(b) variation in temperature
2. For MOSFET fabricated in IC we know
IW i0 (mA)
1o = 2 ·L Cox ~ [V GS - VTN]2
MOSFET2
(a) From one MOSFET to other it is possible that the
aspect ratio (W/L) or C0 x may vary. This will
Module

a
change 10 .
(b) Also the threshold voltage VTN and conductivity
of channel varies with temperature. Therefore I0
will vary with temperature.
VGs(V)
3. Graphically we can see in Fig. 3.12.1 that when one
MOSFET is replaced with other /i 10 is large.

(tk54) Fig. 3.12.1

BIASING is used to keep l!,,.10 very low in all possible causes of variation in 10 . Following are different BIASING
METHODS.

~ 3.12.1 Drain to Gate Feedback Biasing

In this case of biasing a resistance' Ra is connected between D and G.

From circuit Ia= 0, :. Ia Ra= 0. :. Ra is short +Voo

lbis makes I V cs =Vos = V oo - lo Ro j

Short for
DC Ro

Now stabilization action due to presence of Ra can be explained as

follows : IG = 0
Vos=VGs
Let 1 increases by l!,.10 due to some reasons, Vos will decrease by AfoRo·
0

.
Smce v GS -- v OS• v GS will also decrease by ·same amount. As a result I0 Io
will decrease and overall increment in 10 will be much smaller than it was

assumed originally. (11155) Fig. 3.12.2

Teeb-Neo Puhliutiom----- Where Authors impire U111(Mtioa __ .,4 SACmNSll4H Venture

r

I. !il Analog Electronics (MU-Sem.3-Electrical) 3-28

Pictorially above point, i.e. how J0 remains more or less unchanged is shown in fig. 3· 12·3·
Field Effect Transistor

-
Let

'
I
I
\
',
Increase In
10 Is checked
_J ··· -
Fig. 3.12.3

DC Bias line (DCBL)and DC load line (DCLL)

Table 3.12.1
, -~·· • .. ).,.,. ,~., _-

" OCEL

Apply KVL in G loop Fig. 3.12.2. Apply KVL in D loop

VDD - IoRo - VGs = 0 :. Vos = Voo - IoRo

Write in form of equation of line as Write in the form of equation of line as

I ) Yoo
Io = ( - Ro Vos + Ro

y = m X + C y= m X + C.

with I0 = 0, Vos= Yoo with 10 = 0, Vos= Yoo

Yoo Yoo
Vas =0, Io=R Vos= 0, lo=R
D 0

io
. (mA)
(mA)

Voo
i0
----
Triod~
region : , Saturation
region
__...._
i,,.. , ( ..... _.
I

. Ro .
Voo
Ro i i DCBL ; 1oa
( ½.• Slope (- - 1 ) . DCLL
loo '/ ; - - Rs . . ··· srope =--1-
:
I •
Ro
+ - ~ c - ' ' ' - - . J _ - - - - 4 - -· Vos (V)
VGSa i Voo VGS = Vos (V) . ~OS(~t) Vosa ' i Voo

(1k51) Fig. 3.12.4

(11157) Fig. 3.12.5

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 !'1 Analog Electronics (MU-Sem.3-Electrical)
3-29 Field Effect Transistor

~ 3.12.2 Potential Divider (P0 ) Blas with Source (S) Feedback

+Voo
Voo

Io
R
VG= __2_ V
R 1 + R2 . DD
-
+VG
••---•u
(constant)+
I +
Vos

= constant
Feedback or_.- Rs
degeneration
resistance
Io

(1k51) Fig. 3.12.6 .

In this type of biasing V O is made constant by using potential divider bias resistances R 1 and ~ - R 1 and R2 are high
value resistances so that ac input resistance of amplifier is high.

In this case, V O = I
Vas + 10 Rs or Vos = V - 10 Rs
9
I ...(3. 12.l)

and lW
Io = 2 L µn Cox [V GS - VTN]
2
...(3.12.2) Module
Let
MOS parameter
Suppose I 0 increases due to variation in parameters, changes
when one MOS is replaced by other, (since VO is
constant) Vas will decrease, as Vas decrease, 10 '
decreases (Refer Equation (3.12.2)). Hence I0 more or MOS replaced
Increase in
Jess remains constant. 10 Is checked

- · Above point can be pictorially shown as in Fig. 3.12.7. Fig. 3.12.7

DCB,L -DCLL
Apply KVL in G loop and write it in the form of Apply KVL in D loop and write it in the form of
VO - Vas - I 0 Rs =0 Voo - Io Ro - Vos - Io Rs = 0

Io = (- ~s) V GS + ~: Io = -(Ro~ RJ Vos + RoV:;s

y = m X + C y = m X + C
with I0 =0, Yos=Yoo
with I0 = 0, Vas= Ya
Ya Yoo
Vos =0, Io-Ro+ Rs
Vas =0, Io=R
s
io
Io (mA)
(mA

Ioa

VTN Vosa
(1ldl0) Fig. 3.12.9
(11151) F1g. 3.12.8

_.,4 SACHIN SHAii Yeature

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 ◄

Iii Analog Electronics (MU-Sem.3-Electrical) 3-30 Field Effect Transistor

2
Alsol0 = Kn[Va s-VTN ] =0.12 [Vas- 3f
I J.1 J PROBLEMS ON MOSFET Equati ng Equati on (1) and Equati on (2) we get,
... (2)

BIASING (ANALYSIS AND 2

0.0984 [VGS- 3) = 18 - V GS
DESIGN) 2
0.0984 V GS + 0.41 V GS - 17 .11 = 0
Ex. 3.13.1 : For circuit sho~n calcula te IDQ , V osQ and VD :. Vas= 11.266 or Vas= - 15.433 selecti ng positiv e value
........---""T"'""' +v00 = 40V (NEMO S) : . Vcs= 11.266
Now10 =~[V0 s-VTN ] 2 =0.12 [11.26 6-3] 2
R0 =3kll
22 Mn :. 10 = 8.199 mA
Apply KVL in D loop
G---i
V DD - l o(RD + Rs) - Vos = 0

18 Mfl R2 Rs = 0.82 kn'

: . Vos = Voo- lo (RD +Rs) = 40-(8. 199 x 3.82)
Vos = 8.679V
V 0 is voltage at D, w .r.t GND. So start from GND
(1k74}Fig. Ex. 3.13.1
reach upto drain .
2
V GS= 10.48 V, Kn= 0.12 mAN ,
V0 = V 00 - l 0 R 0 = 40 - (8.199 x 3) = 15.403 V
0 soln.:
r::,- Result s
► Step 1 : DC analysi s
IDQ = 8.199 mA, V osQ= 8.679V,
Draw DC equiva lent circuit, with all capaci tors open
V DQ = 15.403 V
and all supply voltages shown with proper polarit y.

Ex. 3.13.2 : Find IDQ• V DSQ and V a sQ if V GS(THJ = 5V,

+ Ro
Io
I
, __.,._
I
100 N = 3 rnA and Vas(ON J = IO V.

Vo I I
Voo 40V

+
I I

R1 :
I
I

'
I

♦
I

Vost I

- I
I
I
Voo

7+
I
I
I = 40 V
Voo I
I

=40V ' VG I ♦
R2 I
I
I
I
I
Rs I .. .,.__.., I
I

!·---l_ _..,__ _ _ _ _ GND

A B
R2
18 Mfl ps
(1k75)F:ig. Ex. 3.13.l( a)

Find VG in directi ons A and B (Fig . Ex. 3.13. l (a)) and

•
equate
(4Hl)Fi g. Ex. 3.13.2
VG in directi on A = VG in directi on B
r:-,r
~ Soln.:
R2
R + R · V 00 = 10 Rs + V Gs ► Step 1 :
I 2 Calcul ate ~ c;>r K.
18-Vq s
= ...(1) Data given:
0.82

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 r
['1 Analog Electronics (MU-Sem.3-Electrical) 3-31
Field Effect Transistor

-- ID(on) = 3mA VaS(oo) = 10 V ~x¢ = 0.8210 + Vas

VTN = YaS(th) = 5V. ... (1)
:. V0s = 18 - 0.821 0
In data sheets of MOSFET' nonnall Y two pomts . on Substituting Equation (I) in shockley's equation we get 2
transfer characteristic are given (Fig E . Io = Ka [VGS - vTN]2 = 0.12 [18-0.82 Io -5]
· x. 3 •13 .2(a)), 1.e. 2
8.33 I0 = [169- 21.32 lo+ 0.67210 ]
(Vas(th)• 0) and (Vascon)• ID(on)). Since both the points are
Simplifying this we get
on the curve with equation i0 = ~ [Vos _ VTN]2 2 .
0.6721 0 - 29.65 I0 + 169 = 0
Io Solving this we get
(mA)
I0 = 37.39 mA and 10 =6.72 mA
Selecting lower value as IDQ

I IDQ = 6.72mA I
Io(onl ·► Step 3 : Calculation for voltages
3mA
Apply KVL in D-loop
Module
(VGS(th)• 0) VGS(on) VGs (V) V oo - lo (Ro + Rs) - VosQ = 0
= 10 V
(VTN, 0) :. YosQ = Yoo - Io <Ro+ Rs)

(4H2)Fig. Ex. 3.13.2(a) = 40 .,.. 6.72 (3.82) = 16.04 V = VDSQ

We can substitute any point [e.g. Voscon) and ~on)] in the From Equation (1) Vas = 18 - 0.82 10 = 18 - (0.82 x 6.72)

equation to get value of ~ or K. Vos = 12.48 V

r7' Results
(ID{on)) 3 mA
2 - 2 2
[V aS(on) - VTN] [10-5] V IDQ = 6.72 mA, VDSQ = 16.04 V
~ = 0.12mNV
2
VGSQ = 12.48 V

► Step 2
Ex. 3.13.3 : For the given E-MOSFET circuit determine
+ Io D-loop IDQ, VDSQ· VGS(TH) = VTN= 3 V, ID(ON) = 5mA, VGS(ON) = 6V
Ro ,- -+- - I
3 k!l f
,, '
' ,'' 24V
,, '
R1 + t,
Vos t,,

v~r ., 7 I+
+ : Voo
22 Mil VGS- , =40V 10MO
''
Rs :,' t,
=~V Va 8200 , '
18Mil ......... --
I I

I -
A 1 B I~

6.8MO
(4H3JFig. Ex. 3.13.2(b): DC equivalent circuit
To find J , equate Va in directions A and B from
0

Fig. Ex. 3.13.2(b).

VO in direction A = Va in direction B (4H4)Fig. EL 3.13.3 : Circuit diagram

Ri
+R VDD = Io Rs + Vas
I 2
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 ~ Analog Electronlcs (MU-Sem.3-Electrlcal) 3-32 Field Effect Transistor

~ Soln.: r:r Reaulta

► Step 1 : Calculate K,,

2- (I DC on))
I =
IDQ 4.95 mA, VDSQ =9.39 V
Io = K., [Vos - V TN] or Kn - [V - V 12
OS(on) TN
E x. 3 .13.4 .• For the circuit shown in 2
Fig. Ex. 3.13.4
5mA 2
K., = 2 2 0.55 mA/ V calculate Vos• lo and Vos· ~ = o. 3 rnA/V ' V TN = - 1V ·
[6- 3) V

► Step 2 : Calculation for IDQ and V DSQ·

-....------,-- v00 = +5 V

Draw DC equivalent circuit of given network with all 0.8k!l

14.5 kn
power supply shown and named.
Find voltage VG• seen in direction A, B and equate.

+ ,.Io
__,.. ... 5.5 kn 0 .6 k!l
Ro :
I
: I
I I _.....1...--------Vss =-5V
I I
I I

+ : •

.
(1k66)Fig. Ex. 3.13A
+ Vose t v 00
-

Io
I

: =40 V ~ Soln. :

Voo
=24V
!+
~s :
I

:
I
I

I
I
I

:
I
DC analysis

Draw DC equivalent circuit by connecting all DC

I - I I
l
.. ~-- I
supply separately and with correct polarity.

A B 0-loop

(4H5)Fig. Ex. 3.13.J(a)

Io
V c, in direction A = VG in direction B ,--..
I I
Rz I
I
l
I

Ri+Ri VDD = loRs+VGs I

I
I
I
I
I
R1 I I
+ I
I
I

1~~8 x 24 = ID x 0.75 + VGS 14.5 ill

_Vost I
I

+ I
l
I
Voo
=5V
.-. V GS = 9.71 - 0.75 ID

l-
I
... (1) Rs :
VG 0.6kQ
Substituting Equation (1) in equation for 10 I'
.Voo 1 -
2
ID= K..rvos-VTNJ =0.55[9.71-0.7510-31

1.81 ID = [6.71-0.75 loJ

2
2 5V +
Vss
5V
A
l B
lo
Vss:,_
5V

Oloop

I1 0 = 4.95 mA I (11117)Ftg. Ex. 3.13.4(a)

Using our usual method calculate V in directions A

Now apply KVL in D-loop. O
and B then equate.
V oo - Io (Ro + Rs) - V osQ = 0
V O in direction A = V O in direction B
:. VosQ = Yoo-Io CRo + Rs)

= 24- (4.95 X 2.95) = 9.39V

\
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l
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a
 -l

li1 Analog Electronics (MU-Sem.3-Electrical) 3-33

Field Effect Transistor

--_yss Yoo+ Yss

+ R1 + R2 . R2 = -Yss + Io Rs + Vas
ltf Soln.:
10
I + Vas
20 x 5.5 = 0.6 0 Io
2.75 = 0.6 I0 + Vas I · V
O(on) --,- ----- ----- - · GS(TH) -
-4V= VTN

= 5mA :...VGs(on) = 7 V j., ·

:. Vas = 2 -75 - 0.6 Io :Substituting this in I
Io(on) = 5 mA j
'
I.
Io = ~ [Vas-VTN] 2 I
,, :.,.. ,,,
•
' /, ~-·-.
I
I
= 0.3 [2.75 -0.6 I0 + 1)2 VTN VGS(on) VGs (V)

Io = 0.3[3 .75 - 0.6 I0 ]2 =4V = 7V

2
= 0.3 [14.062 - 4.5 10 + 0.36 10 ]
(1k77)Fig. Ex. 3.13.S(a)
= 4.21 8- 1.35 I0 + 0.1086 ~

-----.
I0
2 ,---- - ...... ----- ...
0.1081n - 2.35 I0 + 4.218 = 0 I , ' I

:
I
+ Io :I

By solving this we get I0 = 19.78 mA and I0 =

1.973 mA :Ro ♦
,---------✓
:

Selecting lower one I 0 = 1.973 mA II ..------f II

t :
V0s = 2.75 - 0.6 I 0 = 2.75 - (0.6 x 1.973) = 1.566
V j '----•II + I

t....,. _____+ ... - Vos

Voo
Apply KVL in D loop.

(V oo + Vss) - Io (Ro+ Rs) = Vos

:. V0 s = 10- 1.973(1.4)
VGs ~
=Vos:
. I

T
I
I
I
+

-
Rs
♦
,
:,
I
I
I

',!p - ---- _)
V08 = 7.23 7V
Loop
V0 5(sat) = Vas - VTN= 1.566 + 1 = 2.566 V
region. (1k71)Fig. Ex. 3.13.S(b)
Since Vos> V0 5 (sat) MOS is working in saturation
which
One point on transfer characteristics is given for
er Results

I Vcs= 1.566, I0 = 1.973 mA, Vos= 7.237 V

equation is
Io = ~ [Vas - VTN] or
2

Ex. 3.13.5 : For the network shown Fig. Ex. 3.13.5 ID(onl = ~ [VGS(on) - VTNJ2
Ill!lllll 5 mA
calculate DC voltages and currents. ~ = 2 -
22V [VGS(on) - VTN] [7 - 4] 2 V 2
2
1.2 k!l = 0.55 mNV

Apply KVL in loop shown (Fig. Ex. 3.13.5(b))

:. Io ... (1)

Also, ... (2)

0.51 kn
Equating Equation (1) and Equation (2)

(1k71)Flg. Ex. 3,13.5

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 Analog Electronlcs (MU-Sem.3-E
lectrlcal) 3-34 Field Effe ct Transistor

~
Yoo -Vo s
Ro+ Rs :. Vso = +0. 8=2 .21V
22- V0 s
1.71 = 0.55 [V 0s- 4) 2
Since 10 = 0, Io Ro= O

2 Roi s shor t and Vo= 0

:. 22- V0 s = 0.94 [V -8V 0 s+1 6]
2
OS
0.94 Vos - 6.52 V - 6.96 = 0 Vso = Vs- Va
05 solving this equation
= 2.2 1-0 =2. 21V =Y s
VosQ = 7.9V or Vos Q=- 0.94 ,
Vo = - V ss + I0 R0 = - 5 + 0.4 x 5
selecting positive value, ·.· NEMOS
= -5+ 2= -3V
VGSQ = 7.9V =Vo sQ
Yso = Vs- V 0 = 2.21 + 3 = 5.21 V
Yoo - Vos 22- 7.9 Test for region of operation
IDQ = -
Ro+ Rs 1.71
VSD(sat) = Vso + VTP
= 8.24mA
= 2.21 -0.8V = 1.41V
VDQ =V 00 -l0 R0 =22 -8.2 4x 1.2=
12.11 V .: V SD > V SD(sat) :. MO SFE T is in
VsQ =I0 Rs= 8.2 4x0 .51 =4. 2V saturation region as was assumed.
er Results

I~ = 8.24 Ma , VGSQ =7.9 V=V DSQ , VSQ

=4.2 V I
rr Results

Vs= 2.21V, V50 = 5.21V I

Ex. 3.13 .6 : For the amplifier show
n in Fig. Ex. 3.13.6 ~ 3.13.1 Design of Biasing Cir
calculate Vs and V so cuits
+5V =v00 Ex. 3.13.7 : Design the circ uit show
n such that I0 = 5mA.
loo Vso = 6V and ~ = 80 kn. For
the transistor shown
=0.4 mA
Vp= -1.7 5 v. -~= 3m AN2•
VsG , + Vs
V 1 = +5 V
Vso

R<; Vo .
= 50 kn
Ro
= 5 kn
-5V =Vs s r:
Rin
= 80 kn Ro
Kp= 200 µA/V2 VTP =-0. 8 V
(11111)Fig. EL 3.13.6 -10 V

0S oln .:
(1kl5)Flg. Ex. 3.13.7
Ass ume transistor is in saturation @S oln .:

IDQ = Kp(Vs 0 + VTP ) 2 or ► Step 1 : Draw DC equivalent circ uit

with D up and
S down for our convenience.
Yso = -~
\}If ;-.. : VTP
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-
~ Analog Electronics (MU-Sem.3-Electrlcal)

5mA
3-35

:. R2 =
1
~0+\ ~
Field Effect Transistor

k.Q =99.S kO = Ki

R2 +
Ro
Io
► Step S: Find R 1
I
Rin
= -
R
I I
+-
R 1 2
I
17
Vso = 6 V - Voo I I I _I_
- + + = 10V _I

V1
+
+
R,l VG tSG+
R, = Rio -
:. R, = 408 • 205 kO
~ = 80 - 99.5

V2
:5V =SV A B
r::r Designed circuit ,

+5V
(1ktS)Fig. Ex. 3.13.7(a)

► Step 2 : Find R 0 408.2 kO

Apply KVL in D loop

llodule
- Vso - Io Ro+ V oo = 0
R0 =0.8 kO
Yoo- Yso 10- 6
I =-5- k.Q=0.8W=R0
0
-5V -10V
► Step 3 : Calculate V so

Io = kp[Ysa+ vTp]2 '

~
(1k87)Fig. Ex. 3.13.7(b)
Ysa = -; -VTP
Ex. 3.1~.8: Design the circuit shown in Fig. Ex. 3.13.8.
Ysa = ""1¾ + 1.75 =3.04V = VSG
Voo= +2.5V

► Step 4 : Find R2 Io I
0.4 mAt Ro
R1Ri
~ = R 1 11 Ri= Ri + ~ = 80 k.Q (given)
V 0 = 0.5V

. R1 80k ...(1) VTN=0.7V

.. R1+~ = Ri lln cox= 100 µA/ v2
=
L 1 µm, W 32 µm =
Find V O in d irections A .and B and equate. · Rs ).::::Q

+ v 1 - IR, = - v so

vi+ Ysa = (R,:IJ (V, + V2) Vss=-2.5V

Now using Equation ( 1) (1kll)Fl1. Ex. 3.13.8

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 ◄

[ii Analog Electronics (MU-Sem. 3 -Electrlcal)

~Soln.:

µ., cox w 6
100 X 10- X 32 X 10- 6
3-36

Also k" =
Cox µnW
2L
6
Field Effect Transistor

200 X 10- X 4 X 10- 6

2 X0.8 X 10-G
-
2L 1 X 10-& 2
I = 0.5 mAN
I,

Io
=
=
l.6mAN 2

le;, [Vos - VTN]2

Vas = -vi + VTN=~ + 0.6 = IV

~
VO = VOS - Vs = 1 - 0 = 1V = V 0
:. Vas = ~+VTN Vo-Vs 3-1
: . Ro = Io = 80µ =25 kQ
= ~6 +0.7= 1.2V
r:r Results
2.5 -0.5
Ro = 0 _4 kO=Sk.Q R0 = 25 k.Q
Vas = Va-Vs
Ex. 3.13.10 : Design the PD bias circuit shown in
Vs = Vo - V GS= 0 - 1.2V = - 1.2V Fig. Ex. 3.13.10
- 1.2 + 2.5
Rs = 4 kn=3.2Sk.Q --...----- -...........,...-•v00 = 10 v
' Io= 0.32 mA
Vos = 0.5 + 1.2 = 1.7V
Ro
Vas -VTN = 1.2-0.7=0.SV=Vo v .,___ _. V 0 =3.4V
= overdrive voltage
.,___ _. V =1 .6V
MOS is in saturation region. 8
I
+
r::r Results = 1 µA Rs

I Ro = S k.Q' Rs = 3.25 w 1
Io

Ex. 3.13.9 : Design the circuit shown Fig. Ex. 3.13.9 If K0 = 0.5 mAtv2
V 00 =0, VTN= lV VTH= 1 V

v00 =+3V (tk9t)Fig. Ex. 3.13.10

Io I
80µAt Ro @° Soln.:

------vo Apply~g Vos= V 0 - Vs= 3.4- 1.6 = 1.8V

>..=O VOS(sat) =Vos-VTN=0.9-1 =-0.IV

VTN=0.6V
V oscsat) <Vos MOSFET is in saturation region.
lln Cox= 20 µA I v2
y =
L 0.8 µm, W 4 µm= Ro _i=.,1i t..n: Yoo-Vo
- 0.32 r..11" - SkQ
Io
-~ 1.6
(tlcll)Flg. Ex. 3.13.9 Rs - Io - 0.32 x 10 - 3 = SkQ

6!f soln.: Vas = ~ +V,,.=~ +1=1.8V

Since V 00 < VTN MOS is in saturation region:
Vs = Vo-Vos or

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Jtl Analog Electronics (MU-Sem.3•Electrical)
3-37 . Field Effect Transistor
Va -Vos+Vs=l.8 +1.6=3.4V
To find the region of operation
= Yoo-Vo =,G;-3.4} .
I 1µ = l.6MQ Let's find Vos
Va 3.4
Ro2 = -I- =1µ = 3.4 Mn Assuming transistor to be in saturation region.

Io = ~(Vos -VTN/
rr Results

Ro = SW, Rs = SkQ,
Vos = ~ - +VTN

~
1
= l.6MQ, 8<;2 = 3.4 MQ Vas = ~ m + 1.2 =2.32V

Ex. 3.13.11 : Design the circuit shown in Fig. Ex. 3.13.11 v;S(sat) = VGS - VTN= 2.32- 1.2V
for 10 = IOOµA and V0 s = 4.5V. If VTN = 1.2V,
2 VOS(sat) = 1.12V
ku=0.08mAN +5V
Since Vos > Voscsat)• transistor is in saturation region as was
assumed.

Vas = Va - Vs

Vs = VO + VGS= 0 - 2.32 V = - 2.32 V

Vos = Vo - Vs

-5V Vo = Y0 s+ Ys=4.5 + (-2.32)

= 2.18 V
(1k94)Fig. Ex. 3.13.11
Yoo-Vo 5 - 2.18
Now R0 = - lOOµA =28.2 kn
Io
@'Sol~.:
Draw DC equivalent circuit Fig. Ex. 3.13.1 l(a). RD = 28.2W
S~ce ~ = O, ~Ro= 0, :. Ro will work as short. Ys-Yss - 2.32 V - ! - 5}
Rs = =26.8 kQ
Io lOOµA
+v00 = 5 V
Rs = 26.SkQ

r:r Results
Vo
RD = 28.2W, Rs= 26.SkQ

-Vss = +5 v

(1111&)Flg. Es. J.13.1 l(a)

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 Iii Analog Electronics (MU-Sem.3 -Electrical) 3-38 Field Effect Transistor

I l.14 LARGE SIGNAL TRANSFER CHARACTERISTICS OF MOSFET

·aa: ·o;.;~ l~~~- ~i~~~,i~~;,~; ~h;~ci~ri~t1~-(v~ ~,~- v -NeMo·s-~~~-~~;;d- i~ -t;;; -~~ ~~~~~ ~~~~~~!~ ___"-_~{(~--
__ . .. .. - .. .... - ..... .. .... ·-· -.... .. . --- ........ .. ..... .. .. - --- - . . ---- .. ........ . . . --- .... ----.... - -- - . .. .... - ---- - -- ,~~
. . ... _ _... _ 0
) - ~;
\.
.. --.... -- ---- - .. .

- -.---+Vo o

Ro

+
io

(1k61)Fig. 3.14.1 : Basic CS amplifier

0 1--t-0 1 in--!-- 0 1 in io
(mA) Triode i
ut-off :saturation 1 triode _region Saturation
re ion :--,... region __,..-
Voo i----....' : '
!' .
X A: , ,: Voo I
I , I ,
I
I
I
I
Ro
I I
I = .-.;,. 1 Q point ,, VGS3>VsG2
I I
I
I
(VIQ, Voa) .
I

Vos -- - - :-- - ' - Q (VGSQ• Vosa)

f Uw '"' i
I I,
; : ·I
I I
I I 1oa
I
: ,: I

1r:-
I : . I

c 0
I:=--:..:-:..:V:..:~!.=-.=.-:..:-\/:..:~J•S::::'-Q:.::-..':.'~!:.:~:..:;:..:+~--V.=.-:..:~~:..:-:..:_·:.::-;__-;:-..~-:'.:-:=-'.-::::::-~.,~V:;IO::_O_.,..,I = VGS Vos(sat) .• , .... , Vosa
=VGs-VTN

(11183)Fig. 3.14.2: Transfer characteris tics for Fig. 3.14.1

(1k62)Fig. 3.14.3: Output characteris tics with load line
Let's draw transfer characteristics (Y /V0 ) step by step

Channel is not formed. Even ifY05 increases 10 = 0. From Fig. 3.14.1, Y = Y00 - I0 R0 . Since io= O, ioRo= o
0

I V0 = Voo I .
For (V1 = Vcs) < VTN, 10 = 0 and V0 = V00 I
Portion X to A in Fig. 3.14.2.
2. With (Vos= V,) ::!: Vn,
At V GS = vi = VTN channel is formed. Io starts flowing. Now if VOS is further increased, more number
of electrons are
attracted and gets accumulated in channel. Resistance of channel decreases. I increases. In Fig. 3.14.1
0 drop across Ro
increases, therefore (Vos .= V0) starts decreasing . Portion A to B in Fig. 3.14.2. This is the portion
of transfer
characteristics where MOSFET is in saturation. A Q-point is also shown in Fig. 3.14.2 with co-ordinate
(V,Q, y OQ).
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['1 Analog Electronics (MU-Sem.3-Electrical}
3-39 Field Effect Transistor

3. With V1 =Vos= Vos+ VTN

MOSFE! enters in _triode region of operation. This point is shown by point B in Fig. 3.14.2 and Fig. 3 · 14 ·3 it is
intersection of load line and broken curve of locus of v
DS(sut)'
4. With (V1 =Vos)> (Vos+ VTN)

MOSFET enters in deep triode region. Portion B to C in Fig. 3.14.2. Note that the characteristics curves in ~e triode
region _are bunched together, the output voltage decreases slowly towards zero. Here we have shown an operating poi~t
C obtained for Vi = V 00 .

J 3.15 MOSFET AS AN AMPLIFIER

-.. --.. . --- ... ---- - -- --- --- .. - - --- - - - ----- - ---- .. -- - - - - - - - -- .. -- - - -- - ---- -,- - ------ - ----- - -- - - - --- .. -------- - ---- .. - ------ .. ---- - -- .. ------ ..
-

ua. Explain FET as differential amplifier.

MU - a. 1 (e, Dec. 13, 5 Marks
ua. Write a short note on : FET differential af!lplifier MU - a. 6, Ma 14, 10 Marks
GQ. With the help of large signal transfer characteristics explain how MOSFET can be 'l,1sed ~ an amplifier.
--=-·······--··-··----· -··- -··--------·-- •- ---- -- ----------·-· -- ·-··-··· -···---·-·------ ·· ---~-~r~ --~--- ··----····--·--• -- --·- ·--
Vos= v~
0 1 --:-- 0 1 in --:-- 0 1 in
ut-off lsaturation : triode region Module
Voo .' : .
X A: I
1
• : • Slope at Q = Voltage gain
: I ,..
, . ••

: - • : - < • ~
: , vo
I I
I I
Vosa - - - - ~- - - -:- - -------~-?- --·- Time
I I
I I
I I I
I I
I I
1 t --
'I II
I I
I I
I I

----,---+- I I

---.--- +Voo I'

I
II
I
io
: : ·c
I:.:::--:.:-:.:;-~-'.:.:--:.:-:..¾:..::.p:.:.=-==-::.:.:-==-::.:.:=::.:::::~:::=::;::;t:::_.,. V_ I ; V GS
Ro VTN ,.DD

· Signal to be amplified
Vos= vo superimposed on DC
voltage v 10

lime

( 1diS) Fig. 3 . 15.1 : Basic circuit of amplifier (1k64)Fig. 3.15.2 : Transfer characteristics
1
·
To operate MOs as an ampli'fier. We select saturation bregion (A - B). Device is biased in middle of saturation region at
. . • t) The signal voltage to e amp 1·fi
1 1e d (vi ) 1s
· then supenmpose
· d on DC mput·
pomt Q (Quiescent porn . . . . . . voltage
. d f (v.) should be very small so that operation 1s m saturation region, and output is not distorted
vIQ = v~SQ . Amp 1tu e o I eform is larger by a factor equ al to the voltage ·
l · · ·
but amplified. The output wav gam of amplifier Av at Q-pomt.

dV 1 0
Where, Av = Ni v, = v IQ

. . al to the slope of transfer curve at the bias point Q. Observe that the slope is negative.
Thus the voltage gam 1s equ . . .
.
Therefore basic CS amp i·fi ·s inverting. It can be seen that v1 and v0 are out of phase.
1
1 1er
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 ~ Analog Electronlcs (MU-Sem. 3-Electrlcal)
3-40 Field Effect Transistor)

3 • 16 SMALL SIGNAL MODE Combin ing these two terms it is MUTUA L + TRANS
I L OF + CONDU CTANC E = Mutual transconductance == gm·
MOSFET

!. OQ. ----- -------- -------- ------- Or

Draw small slgnal model of MOS~ET- ~~d- ~~~l~l~-
; _____ ___ ,,1 ~~~': ! of each parameter. (3) Output resistance (ro)
--- - - --- - - - - - - - - - - - - -----. - .. - ---- - - - - - - - -· - .. 1 ..

W (A) Small algnal model of MOSFET Ideally, after Vos (sat)• (Refer Fig. 3.16.3) current J
0
(Refer Fig. 3.16.1 and 3.16.2) should remain constan t with increase in Vos·
id
But in practice due to channel length modulation, with

~
D i9 =0 increase in Vos• 10 also increase .

s Vds .t • t 7 This concept is responsible· for slope in saturation

! ~ i i
vgs Vgs Open Vds
region.

~ Zo ZG = oo

(1H1)Fig. 3.16.1 (1H2)Fig. 3.16.2

~ (B) Important Parameters

(1) Input impedan ce Z

6

(2) Transco nductan ce gm (mS or mU or rnAN)

(3) Output resistan ce (r ) VosCVolts)

0

(IH4)Fig. 3.16.3
· (1) Input impedance Z6
The inverse of slope of output characteristic (at Q
At the input of MOSFE T, there exists a layer of
insulato r (Sio 2), hence the input current ig 0. = point) gives output resistance (r ) of MOSFET.
0

In other words, input is as good as open circuit. = _1_ avos

11VGS =0 =~
Therefo re Za = oo. ro Slope V Gs constan t
(2) Transconductance 9m (mS or mU ·or mA/V)
... (3.16.1)
Since i8 = 0,
the output of MOSFE T is controlled by
Considering all 'points namely 2<,, gm and r we can
input voltage. Hence MOSFET is voltage control 0

device. i.e. draw small signal ac equivale nt circuit of MOSFET. In

id the Fig. 3.16.4 and Fig. 3.16.5 ac equivale nt circuit of

id oc Vgs or id = kV 8, or, k--
-ya• N and P channel MOSFE T is shown.
Where k is ratio of current to voltage, therefore it is
CONDU CTANC E. Since it is ratio of output to input
parame ter it is MUTUA L TRANS FER ratio.

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 Analog Electronics (MU-Sem. 3-Electrical) 3-41 Field Effect Transistor)

N-M9SFET

Vs +

Fig. 3.16.4 : AC model of N-MOS Fig.,3.16.5 : AC model of P-MOS

J 3.17 MODELL ING THE BODY Now if an ac component exists in the source to body
EFFECT voltage, vs 8 there will be an ac component induced in
VTN• which causes an ac component in drain current.
- When MOS is used as discrete component substrate or
Therefore a back-gate transconductance can be llodule

-
body and source are shorted. But in IC's body is not
connected to source,
defined as, 0.
- For an NMOS device, the body is connected to the
most negative potential in the circuit and will be at gmb = d VBS Q-point = d VsB Q-point

signal groµnd.

Io Qpoint

G DB
Using Equation (3.16.1),
~ v
GS_ + SB d io d 2

aVTN = aVTN ~ (Vas - VTN)

(b) AC voltages = - 2 ~ (Vas - VTN) =- gm

(a) DC voltages
Using Equation (3.17.l),
Fig. 3.17.. 1: NMOS Device
dVTN r
We must note that VsB = VsB + vsb must be greater than --- -ri
dVsB - 2 ✓2cj),+VsB =
or equal to zero.
Now the back-gate transconductance will be,
The simplified current voltage relationship will be
2
i0 = ~ (Vas - VTN)
and the threshold voltage VTN will be given as,

VTN = VTNO + r [✓2 cl>,+ VsB -ffer]

... (3.17 .. 1)
s
Fig. 3.17.l

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 ~ Analog Electronics (MU-Sem. 3-Electrical) 3-42 Field Effect Transistor)

Fig. 3.17 ..2 shows small signal model of MOSFET

•o. -- Kn[ VOS - VTN )2 + K,,[ 2{VOS - VTN) ] Vgs IDQ + id

including body effect. We must note current direction

id = Kn [ 2(V OS - VTN) ] Vgs
and the polarity of small signal source to body voltage.
If vbs > 0, then Vse decreases, VTN decreases and i0 &n = 2!
VP
=2Ka (VGSQ - V TN)

increases. · The current direction and voltage 2

Using IDQ = K,, [ VosQ- VTN 1
polarities are thus consistenL

T\ ranges from O to 0.23, while vb, will depend upon

1.-. gm= 2 ~
particular circuit.
~ (2) Dynamic output resistance (ro)
I l.18 EQUATIONS FOR Im AND fo
OF MOSFET If channel length modulation is considered in saturation

• ~--i k~0X 0 "-'"'>.•,/«~~~"~':::: '<:~' ...:..,'.~.,/·.~\=?;)":'t>):<: .\· ·:--,:/,i - ·i; "- ,·,,_~ region current i0 increases with Vos with V0 s constant.
: GQ. 'Oerwe° ~uatio.n l 9r . transcq~d~ct~mce (g;;J and ·• :
l eyn1mit output~e.Jis~nce·(ro) 'o t'~ 0$FET) '.
·-- - - ---- - - -- , _·. - -- - - - - -~ _ _ _., _ _______ ., ____ , . . _ <?''?' _-__ _ __ ·____ _:;;.- -- '~ .!
.,;-:, >i This causes slope to occur. It means slope in output

characteristic in saturation region is nothing but

~ (1) Transconductan ce (gm)
indication of CLM.

The output characteristics for NEMOS considering

CLM or early effect is shown in Fig. 3.18.2.

(1K36)Fig. 3.18.1

In saturation region

(1k25)Fig. 3.18.2 : Output cbaractemtlcs for NEMOS

= K,, [ V GS + Vgs - VTN ]2 =K,, [ (VGS - VTN) + V·gs ]2
Fig. 3.18.2 shows effect of Vos on i in the saturation
= K,, [ (VGS - VTN) 2 + 2(VGS - VTN) Vgs + Vgs
2 ]
0

region. The MOSFET parameter VA depends on the

= K,, [ y GS - VTN J2 + Kn [ 2~GS - VTN) + vgs J va•
process technology, for given process, is proportional
If 2(Vos - VTN ) >> va• then v281 term is eliminated. to the channel length.

Square tenn always s hows non-linearity i.e. distortion in Equation for i0 in saturation region with CLM in
output current io· consideration, is given as :

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 ~ Analog Electronics (MU-Sem. 3-Electrical)
3-43 Field _Effect Transistor)

When CLM is neglected, r is infin

0 ite. But if CLM is
considered then.

1 _ ~
ro - fl. Vos \ fl. V
GS=O
di 0I
= dv 0 s Vas= const
Vas= Vas
Where V is positive quantity like earl
, A

and A is known as channel length mod

y voltage in BJT,
ulation parameter.

J 3.1 9 MF AC ANALYSIS OF COMMON

SOURCE AMPLIFIER
1,. 3.19.1 Key Points to Dra
w AC Equivalent of Given Commo
n .Source Amplifier
~
Is S(source) connected to GND
?
I Module

YES .
Draw three lines NO.
Draw four lines
VG Vo
VG Vo

Vs
1 'i'

~
Is r0 t! 10 R0 Is r0 t! 10 R0 and
or not given ? r0 ,! 10(R8 +R0 )

I
or r0 not give n?

I
YES. NO: YES. NO.
Neglect r0 Connect r0 ' Neglect r0 Con nect r0

VG Vo VG Vo VG Vo

1 ro
1 Vgs
1 Vgs
Vga 9mVgs . ro

(1191)Flg. 3.19.1

-
. .
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 Field Effect Transistor
[i1 Analog Electronics (MU-Sem.3-Electrical)
3-44

a. 3.19.2 Transfer of Resistance From S to D

F~Q.----H~~~t~ ;~~d~-r- ~~j~~-f~S-t~ 6-?---------------~ ~ ~ ~ ~ ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~:~ ~~~~ ~ ~ ~ ~ ~ ~~ ~:~ ~ ~ ~~~•- -..'.' --~ --------·"----~-~ ~ ~ ~j
·Statement
th
(I + gm ro) and is connect ed in series wi ro
Whenev er a resistance is transferred from source to drain it is mu]tiplied by

on output side.

Proof

To prove above statemen t let us find Zo for the circuit shown in Fig. 3.19.2 and Fig. 3.19.3.
D

r
vi
Rs
Vo RL
·nvi
Vgs
s
Vs
ro
+

R,
T
l
Rs
'I'
Zo
(1 H92)Fig. 3.19.2 (1H93)F ig. 3.19.3

(a) Zo is nothing but output resistance seen from D. Therefore we use our conventi onal steps.
1. Rep]ace ·MOSFE T with model
2. Remove load (RJ
3. Short input (V i = 0)
4. Apply our own, known voltage (V0 ) across output terminals.
5. Measure (10 )
Vo
6. Then the output resistance Zn =-1- .
0

Steps to find Zo are as below. Refer Fig. 3.19.4(a ) and 3.1 9.4(b).

Jo

9mVgs q
lo
r ..
l 0 (measured)

Vo
(applied)
9mVgs
D
q
Io
Vo

rd

-Vgs Vo
r
l l
- 1oRs= Vgs Rs
Vgs Rs
+ +
Short
Zo
(a) (b)
(1H27)Fig. 3.19.4

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p
Fie ld Eff ec t Tra ns ist or

em.3-Electrical) 3-4 5
~ Analog Electronics (MU-S

Bu t

Transferred
Vo I,, Rs from S to D
= -g mR I+ - -ro-
s O ro
(tH21) Fig. 3.19.5

... (3. 19 .1)

Vo
I0 = 2 o = ro + gm ro Rs + Rs

Zo = ro + Rs (I + µ) ed to D, it ge ts
ica tes tha t Rs (w hic h was in S), wh en tra nsf err
is ind
me nte d in Fig. 3.19.5. Th
Equation (3.19.1) is im ple
is in series with r0 •
multiplied by ( 1 + gm r0 ) and Jfoduie
since r0 >> R 0
oa
,

-
Zo=r~
Io

O N MF
J 3. 20 TYPE I· EXAMPLES
CS
Ro = 3 .3 kn
AC ANALYSIS O F
+
AMPLIFIER R 1 =40 MO Vos
Voe
- =3 0V

Rs By pa ss ed +
3.20.1 Ex am ple s wi th
~

Ex. 3.2 0.1 :

(o r R 5 = 0)

Fo r the given MO SF ET
amplifier circuit, find
Voe
=3 0V I7 =~OM1!l71 VG
'-- -- -.. .L ... -- --
B A
rI
-'- -- -- -- -L _: ::.
lo
.._ _--- ' GN D

~ and R 0 • t cir cui t

Av,
(1Kt35)Fig. Ex . 3.2 0.l (a) : DC equivalen
te
ect ion s A and B an d eq ua
To find I0 , find VO in dir
in dir ect ion A
VG in direction B = VO
Rz V
oo = Io Rs + VGS
R1 + R2
IO
. 50 x 30 = 1.2 I0 + Va s

ting this in
VGs = 6 - 1.2 I0 Substitu
2
Io = ~ CVGs - VTN]
2
ro =rd = 40 k
k = k,, = 0.4 mA N ,
VGS(lh) = VTN = 3V ,
(1K134)Fig. Ex. 3.20.1 We get, I0 = 0.4 [ 6- 1.2 Io - 3
J2
Io = 0.4 [ 3 - 1.2 Io J2 =0.4 [9 - 7.2 Io + 1.44 Ii ]
@ s0 1n .:
76 Ii
Io = 3.6 - 2.88 10 + 0.5
► Step 1 : DC analysis 2
t by = 0
w DC equivalent circui 0.576 ID - 3.88 Io + 3.6
Using simple symbol, dra
opening al] capacitors.
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l
 ◄

~ Analog Electronics (MU-Sem.3-Electrical)

·Solving this we get,

I0 = 5.625 mA , I0 = I. 11 l mA
3-46

Ex. 3.20.2 : Find Iw, \'.'osQ• gm and Av=

.
V
y I
-
Field Effect Transistor

(Fig. Ex. 3.20.3)

Selecting lower value 10 = 1.111 mA +v00 = 5 v

Vas= ~+VTN= (~+3)

.,£
VGS = 4.666 V

► Step 2 : Calculation for MOS parameter

gm = 2 ✓~ IDQ = 2 ✓o.4 x 1.111 = 1.333 mS

r0 = rd =40 kQ VGSQ + 2V 2

► Step 3 : AC analysis • Kn= 0.25 mA/ v2

VTN= 0.8 V
Draw ac equivalent circuit by shorting all capacitors A.= 0
with Cs shorted, S is grounded therefore 3 lines. (1k96)Fig. Ex. 3.20.2
Vi=VG
0 soln.:

v.1 ~
= R1 II R2
rd
1
0
t 1
Ro Vo
DC analysis (Fig. Ex. 3.20.2(a))

Io

7-1
D-loop .
I _ _ ,.._

+ I
I
I
2;= Ri Zo lo +:
(1K136)Fig. Ex. 3.20.l(b): AC equivalent circuit Vost
- I
I
I
Impedances I
I
Voo
I
I
I ... ..,.. __ .,I =5V
~ = R1 II R2 = 8M Q

~ = ~ = 8M Q , :lo = rd = 40 kQ y

Z0 = rd II R0 = 3.048 kQ (1k97)Fig. Ex. 3.20.2(a): DC equivalent circuit

= Ra VasQ = 2V (given)

Voltage gain . Io = ~ rvas-VTNJ2

Attack on V,s , V85 = Vi = 0.25 [2 - 2

0.8] = 0.36mA

Vo = -gm Vg,Zo=-gm ViZo Apply KVL in D loop (Fig. Ex. 3.20.2(a))

Vo Vos = Yoo -IoRo

Av = y. = - gm 2
I
0 = - 1.333 X 3.048
= 5-0.36x 5
Av = -4.062
= 3.2V

a- Results gm = 2~<Vas-VTN)

Ri =8M'2 =Z1, R =3,048 W =Z Av= - 4.062

0 0,
= 2 X 0.25 X 1.2

= 0.6mS

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AC analysis (Fig . Ex. 3.20 .3(b ))
Io
3-47

lo
Field Effect Transistor

,------,
TT VI Vgs
9m vgs
Ro
+
Vo
I
I

♦:
I
I
I

+
+ I

nt circu it
(1k98)Fig. Ex. 3.20 .l(b) : AC equi vale r- ... ,
I '
R o,I '
', Rs
I I

t t
I . I
-f
!__ ---· v00 = 9V
G-loop y

(1k114)Fig. Ex. 3.20.3(a)

:. Av = - 0.6 X 5 =- 3
App ly KVL in G-lo op
B' Results
V ss - Io Rs - V so =0
IDQ = 0.36mA, VDSQ = 3.2V Yss - Ysa
... (1)
:. Io = Rs
g,,, = 0.6ms, Av= -3
Also from Equa tion for I0
2
lo = kp[V sa+V TP] ... (2)
Ex. 3.20 .3, Find
Ex. 3.20.3 : For the circu it show 2n in Fig.
IDQ, V 5DQ and Av. Ifkp = 2 mA N, Equa ting Equa tion (1) and Equa tion (2)
I 2
VTP =-2 V, A= 0.01 V- Yss -Vs a
Rs = kp [Vso + VTP]
+9 V= v 55
9-V SG
1.2 = 2 [VSG - 2]2

Rear rang ing the term s we get,

2.4 ~'1 - 8.6 V 50 + 0.6 = 0

Solv ing this we get,

V so = 3.5 V and V so= 0.07 V

ld be posi tive and
Sinc e we have PEM OS, V so shou
grea ter than V TP
-9 V= V00
I Vsc = 3.S VI
(tk113)Fig. Ex. 3.20.3 9-3 .5
Io = 7' T mA = 4.58 mA
@ Soln .:
► Step 1 : Calc ulati on for Io, Vsa
10 = 4.S8 mA I
. . 'th D up and S down
Draw DC equi vale nt circu it wi ► Step 2 : Calculation for MOS
Refer Fig. Ex. 3.20 .3(a) . Parameters,
all DC voltages with
- Open_all capa citor s and conn ect gm = 2 ✓lo kp = ✓4.58 X 2X2

prop er polarity.
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,r,n:n
r
◄

Analog Electronics (MU-Sem.3-Electrlc

-
al) 3-48 Field Effect Transistor
gm= 2 ~ =2 ✓ (4.58 )(2}xl0- 6 ~ 3.20.2 TYPE II - Examples
With Rs
Un bypassed
~ = 6.0SmS I Ex. 3.20 .4: For circuit in Fig. Ex. 3.20.4, find Av.
If V
r
0 =~=(01 x\.ss)ko =0.8 V,
2
ko= l mA N, A=O . · Tu

r0 = 21.83 k.Q I Voo = +5V

Ro
► Step 3 : Calculation for Vso
7 kn
Apply KVL in D-loop Vo

<Vbo + Yss) -lo Ro- Yso

(V ss + V oo) - Io (Ro + Rs) - V so = 0

Rs
Yso = 18-4 .58( 2.2) 0.5k n
,.__ ____,..___ Vss = -5 V
Vso = 7.92 vl
(1K105)Fig. Ex. 3.20.4: Circuit diagram
► Step 4 : Calculation for voltage
gain (A.,) 0 soln .:
Draw AC equivalent circuit by shorting
all capacitors ► Step 1 : DC analysis
and DC sources.
To find Av, we require gm, for which
VGSQ is required.
+ ·T + To get VGSQ• DC analysis is required.

Vj
Ro Vo
:. Draw DC equivalent circuit by open
~
(a)
l_ and connecting DC sources with proper
ing capacitor
polarity.
Fig. Ex. 3.20.4_(a).
+
vi
+ T+
'
Re, ro Ro Vo

+
Io
l_
(c)
Fig. Ex. 3.20.3 : AC equival; nt circuit Voo

(1K106)Fig. Ex. 3.20.4(a) : DC equivalent circuit

where z0 = R0 II r = (11121.83) k =
0 0.956 k.Q
Av = - 6.05 X 0.956 VG =-V ss+ IR2 =-V ss+ Yoo + Vss
R R R2
I+ 2

Av = -5.7 8 . 10
= -5 +20 ox3 5

~ Results = -3.2 5 V

I. l0 =4.S8mA, V80 =7. 92V , Av= -5.7 81

= - 3.25 V (Refer Fig. Ex. 3.20.4(a})

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 Analog Electronics (MU-Sem.3-Electrtcal) Field Effect Transistor

I
3-49
Io

D- loop
--- V1=Vo Vo Io= gm Vge

I
I' II
I I
I I

I
I
I
vgs gm Vgs
I I

:~~~-
I
I
♦ Vs
tI
!
V1 Ro Ro Vo =-IoRo
Io
:I ♦

1
I
I I
I I
I
I
I
I
Rs Rs
= 3.25 V iI t
I -
I
I
I
I
I
I
I I I
I

'- -◄- - ) Vss\

--- :

(IK107)Fig. Ex. 3.20.4(b) : SimpHfted DC equivalent circuit (1K10l)Flg. Ex. 3.20.4(c) : AC equivalent circuit

Replace circuit on LHS of G in Fig. Ex. 3.20.4(a) to get vg, = V8 -V,=V;- I Rs 0

simplified DC equivalent circuit as in Vo = -I0 R0 =-g~ VgsRo

Fig. Ex. 3.20.4(b). = - gm CV; - io Rs) Ro
KVL in G-loop (Fig. Ex. 3.20.4(b))
- VG - VGs - Io Rs + V ss = 0,
= - gm [ V; -( ~: Rs)] Ro
0

= - VG - Vos+ V ss 1.75- Vos [ Vo Rs]

lo R ... (1) = - gm Vi + ~ Ro
s 0.5
Also, I 0 = k.,, (Vas - V TN)2 = -gm Vi RO-gm Vo Rs
= l (V GS - V TN/ = 1 (V GS - 0.8)
2 ... (2) Vo (l + gm Rs) = .- gm Vi RO
Vo -gm Ro
F.quating Equation (l) and Equation (2) .. Av = ~= l +gmRs
1.75-Vas 2
= (V05 -0.8) -1.4 X 7
0.5
2
= l + 1.4 X 0.5
or 3.5 - 2 Vas = Vos - 1.6 Vas + 0.64
2 Av = -5.76
VGS + 0.4 V GS - 2.86 · = 0.
This gives Vas = + 1.5 q, Result

and Vas = -1.9 V.

For NEMOS, Vas should be positive
I Av = -5.76 I
VGS = + 1.5V Ex. 3.20.5 : Determine Av, R; and Ra for circuit shown in
1.75-Vas Fig. Ex. 3.20.5.
and 0.5 mA +5V

= I.75-1.5m A
0.5
180
= 0.5 mA
:. MOSFET parameters are
gm = 2Ku CVas-VTN ) = 2 X Im (l.5-0.8)
VTN = 0.8 V
= 1.4 mS
Kn=1mA/ v2
ro = 00

► Step 2 : AC analysis
- To find A draw ac equivalent circuit by shorting all
v• -sv
capacitors and DC supply.
(1K120)Flg. Ex. 3.20.S
- Replace MOSFET with its mf m~el.

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 Iii Analog Electronlcs (MU-Sem.3-ElectricaJ) 3.50 Field Effect Transistor
~ Soln.:
► Step 1 : DC analysis
► Step 2 : Calculation for MOS parameters --
Ii gm = 2 ✓1DQ~
Draw DC equivalent circuit by opening all capacitors = 2 ✓0.19x 1 mS
and connecting power supplies with correct polarity.
gm = 0.871 ms
...,
I
I
I
I
I I
6.3 kn : • ► Step 3 : AC analysis
R 1 = 180 kn Vo 'I Draw ac equivalent circuit with all capacitors and DC
IG = 0 VG ! + Voo -
+ '
I i

I
I sources short.
•
l
I
+ Vs '
I I
I I
For ac, S is not grounded therefore 4 lines.
30kn
Rs= 1 kn: I
I

Voo
= R2
-
VG ' I
I
I
! I
=SV

'
I

5V - I
\ I
I
I
I
=Vss+
+
A B
D-loop

(1K121)Fig. Ex. 3.20.S(a): DC equivalent circuit

Using standard method

zi Zo
VG in direction A = Va in direction B
(1K122)Fig. Ex. 3.20.S(b): AC equivalent circuit
- 'Ks + IR2 = - 'Ks + lo Rs + Vas
IO Impedances Z; =Ra= R1 II R2 =1801130 = 25.714 W
210 x 30 = I0 • 1 + Vas
Z0 = R0 = 6.3 kQ
I0 = 1.428- Vas .. .(1)
Voltage gain
Also we know,
Attack on V gs,
. 2
Io = ~ fVas - VTN]
Vgs = Vg-Vs =Vi-gm VgsRs
I0 = 1 [VGS - 0.8] 2 ... (2)
V; = V gs (I + gm Rs)
Equating Equation (1) and Equation (2) we get,
Vo = - gm Vgs Ro
2
1.428 - VGS = VGS - 1.6 VGS + 0.64
V0 - gm 'fas Ro
2
VGS - 0.6 VGS - 0. 788 Av= y =
= 0 i 'fss (I + gm Rs)
Vas = 1.237 V
-0.871 X 6.3
or Vas· = - 0.637 = l + 0.871 X 1

Since MOSFET is n-channel V0s should be positive. = 2.932

VGS =· 1.23 V W Reaulta

Now using Equation (1), Av= 2.932, Rt= Z1 = 25.714 kO, R.i =Ro= 6.3k0]
I0 = 1.428 - 1.23

= 0.19 mA =1 0

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